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int64 137
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stringlengths 137
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stringclasses 15
values | hash
stringlengths 32
32
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float64 0.25
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straywarrior/MadeCPUin21days
|
PC_REG.vhd
| 1 | 1,357 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 23:36:20 11/21/2015
-- Design Name:
-- Module Name: PC_REG - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PC_REG is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
stall : in STD_LOGIC;
PC_in : in STD_LOGIC_VECTOR (15 downto 0);
PC_out : out STD_LOGIC_VECTOR (15 downto 0)
);
end PC_REG;
architecture Behavioral of PC_REG is
begin
process (reset, clk)
begin
if (reset = '0') then
PC_out <= (others => '0');
elsif (clk'event and clk = '1' and stall = '0') then
PC_out <= PC_in;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
855f6636a8e8fffe7ed2e8ddb1624580
| 0.540899 | 3.956268 | false | false | false | false |
Bourgeoisie/ECE368-RISC16
|
368RISC/ipcore_dir/tmp/_cg/_dbg/Instruct_Memory.vhd
| 1 | 10,224 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.3 --
-- --
-- The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port --
-- Block Memory and Single Port Block Memory LogiCOREs, but is not a --
-- direct drop-in replacement. It should be used in all new Xilinx --
-- designs. The core supports RAM and ROM functions over a wide range of --
-- widths and depths. Use this core to generate block memories with --
-- symmetric or asymmetric read and write port widths, as well as cores --
-- which can perform simultaneous write operations to separate --
-- locations, and simultaneous read operations from the same location. --
-- For more information on differences in interface and feature support --
-- between this core and the Dual Port Block Memory and Single Port --
-- Block Memory LogiCOREs, please consult the data sheet. --
--------------------------------------------------------------------------------
-- Source Code Wrapper
-- This file is provided to wrap around the source code (if appropriate)
-- and is designed for use with XST
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY blk_mem_gen_v7_3;
USE blk_mem_gen_v7_3.blk_mem_gen_v7_3;
ENTITY Instruct_Memory IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END Instruct_Memory;
ARCHITECTURE spartan3e OF Instruct_Memory IS
COMPONENT blk_mem_gen_v7_3 IS
GENERIC (
c_family : STRING;
c_xdevicefamily : STRING;
c_elaboration_dir : STRING;
c_interface_type : INTEGER;
c_axi_type : INTEGER;
c_axi_slave_type : INTEGER;
c_has_axi_id : INTEGER;
c_axi_id_width : INTEGER;
c_mem_type : INTEGER;
c_byte_size : INTEGER;
c_algorithm : INTEGER;
c_prim_type : INTEGER;
c_load_init_file : INTEGER;
c_init_file_name : STRING;
c_init_file : STRING;
c_use_default_data : INTEGER;
c_default_data : STRING;
c_rst_type : STRING;
c_has_rsta : INTEGER;
c_rst_priority_a : STRING;
c_rstram_a : INTEGER;
c_inita_val : STRING;
c_has_ena : INTEGER;
c_has_regcea : INTEGER;
c_use_byte_wea : INTEGER;
c_wea_width : INTEGER;
c_write_mode_a : STRING;
c_write_width_a : INTEGER;
c_read_width_a : INTEGER;
c_write_depth_a : INTEGER;
c_read_depth_a : INTEGER;
c_addra_width : INTEGER;
c_has_rstb : INTEGER;
c_rst_priority_b : STRING;
c_rstram_b : INTEGER;
c_initb_val : STRING;
c_has_enb : INTEGER;
c_has_regceb : INTEGER;
c_use_byte_web : INTEGER;
c_web_width : INTEGER;
c_write_mode_b : STRING;
c_write_width_b : INTEGER;
c_read_width_b : INTEGER;
c_write_depth_b : INTEGER;
c_read_depth_b : INTEGER;
c_addrb_width : INTEGER;
c_has_mem_output_regs_a : INTEGER;
c_has_mem_output_regs_b : INTEGER;
c_has_mux_output_regs_a : INTEGER;
c_has_mux_output_regs_b : INTEGER;
c_mux_pipeline_stages : INTEGER;
c_has_softecc_input_regs_a : INTEGER;
c_has_softecc_output_regs_b : INTEGER;
c_use_softecc : INTEGER;
c_use_ecc : INTEGER;
c_has_injecterr : INTEGER;
c_sim_collision_check : STRING;
c_common_clk : INTEGER;
c_enable_32bit_address : INTEGER;
c_disable_warn_bhv_coll : INTEGER;
c_disable_warn_bhv_range : INTEGER;
c_use_bram_block : INTEGER
);
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v7_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF spartan3e : ARCHITECTURE IS "blk_mem_gen_v7_3, Xilinx CORE Generator 14.7";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF spartan3e : ARCHITECTURE IS "Instruct_Memory,blk_mem_gen_v7_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF spartan3e : ARCHITECTURE IS "Instruct_Memory,blk_mem_gen_v7_3,{c_addra_width=5,c_addrb_width=5,c_algorithm=1,c_axi_id_width=4,c_axi_slave_type=0,c_axi_type=1,c_byte_size=9,c_common_clk=0,c_default_data=0,c_disable_warn_bhv_coll=0,c_disable_warn_bhv_range=0,c_elaboration_dir=C_/Users/Brett/Documents/GitHub/ECE368-Risc/ipcore_dir/tmp/_cg/,c_enable_32bit_address=0,c_family=spartan3,c_has_axi_id=0,c_has_ena=0,c_has_enb=0,c_has_injecterr=0,c_has_mem_output_regs_a=0,c_has_mem_output_regs_b=0,c_has_mux_output_regs_a=0,c_has_mux_output_regs_b=0,c_has_regcea=0,c_has_regceb=0,c_has_rsta=0,c_has_rstb=0,c_has_softecc_input_regs_a=0,c_has_softecc_output_regs_b=0,c_init_file=BlankString,c_init_file_name=Instruct_Memory.mif,c_inita_val=0,c_initb_val=0,c_interface_type=0,c_load_init_file=1,c_mem_type=1,c_mux_pipeline_stages=0,c_prim_type=1,c_read_depth_a=32,c_read_depth_b=32,c_read_width_a=16,c_read_width_b=16,c_rst_priority_a=CE,c_rst_priority_b=CE,c_rst_type=SYNC,c_rstram_a=0,c_rstram_b=0,c_sim_collision_check=ALL,c_use_bram_block=0,c_use_byte_wea=0,c_use_byte_web=0,c_use_default_data=0,c_use_ecc=0,c_use_softecc=0,c_wea_width=1,c_web_width=1,c_write_depth_a=32,c_write_depth_b=32,c_write_mode_a=WRITE_FIRST,c_write_mode_b=WRITE_FIRST,c_write_width_a=16,c_write_width_b=16,c_xdevicefamily=spartan3e}";
BEGIN
U0 : blk_mem_gen_v7_3
GENERIC MAP (
c_addra_width => 5,
c_addrb_width => 5,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_elaboration_dir => "C:/Users/Brett/Documents/GitHub/ECE368-Risc/ipcore_dir/tmp/_cg/",
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "Instruct_Memory.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 32,
c_read_depth_b => 32,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 32,
c_write_depth_b => 32,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan3e"
)
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
END spartan3e;
|
mit
|
5eae559c6d0dfbcdac9828060a821a49
| 0.56651 | 3.369809 | false | false | false | false |
michel-castan/LILASHOME
|
doc/index_171.vhd
| 1 | 1,978 |
--------------------------------------------
-- généré par LILASV4 --
--------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.Numeric_Std.all;
use IEEE.std_logic_unsigned.all;
entity tst_code_logic_Moore is
port(
clk : IN std_logic := 'U';
rst : IN std_logic := 'U';
monter : OUT std_logic := 'U';
descendre : OUT std_logic := 'U';
DS : IN std_logic := 'U';
DI : IN std_logic := 'U';
MS : IN std_logic := 'U';
MI : IN std_logic := 'U';
MA : IN std_logic := 'U';
DA : IN std_logic := 'U');
end entity tst_code_logic_Moore;
architecture a_tst_code_logic_Moore of tst_code_logic_Moore is
-- déclaration des variables modules
-- déclaration des signaux internes
-- déclaration des variables locales
type typeEtat is (CabineArretDescente, CabineArretMontée, CabineEnMontée, CabineEnDescente);
signal etatCourant : typeEtat := CabineArretDescente;
begin
process (rst, clk)
begin
if (rst='1') then etatCourant <= CabineArretDescente;
monter <= '0';
descendre <= '0';
elsif (clk'EVENT and clk='1') then
case etatCourant is
when CabineArretDescente =>
if DS='1' then etatCourant <= CabineEnMontée;
monter <= '1';
descendre <= '0';
elsif DI='1' then etatCourant <= CabineEnDescente;
monter <= '0';
descendre <= '1';
end if;
when CabineArretMontée =>
if MS='1' then etatCourant <= CabineEnMontée;
monter <= '1';
descendre <= '0';
elsif MI='1' then etatCourant <= CabineEnDescente;
monter <= '0';
descendre <= '1';
end if;
when CabineEnMontée =>
if MA='1' then etatCourant <= CabineArretMontée;
monter <= '0';
descendre <= '0';
end if;
when CabineEnDescente =>
if DA='1' then etatCourant <= CabineArretDescente;
monter <= '0';
descendre <= '0';
end if;
end case;
end if;
end process;
end architecture a_tst_code_logic_Moore;
|
apache-2.0
|
692bceac6d6b850cdabc3aec3c6b5ebe
| 0.59084 | 3.26412 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_decoder_GNM4LOIHXZ.vhd
| 14 | 901 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNM4LOIHXZ is
generic ( decode : string := "01";
pipeline : natural := 1;
width : natural := 2);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNM4LOIHXZ is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 2,
decode => "01",
pipeline => 1)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture;
|
mit
|
5ed54a88ee0a0fee923346e1c92527dc
| 0.653718 | 2.925325 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg.vhd
| 1 | 71,560 |
-------------------------------------------------------------------------------
-- axi_sg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
-- Description: This entity is the top level entity for the AXI Scatter Gather
-- Engine.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_1.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/1/10 v1_00_a
-- ^^^^^^
-- CR567661
-- Remapped interrupt threshold control to be driven based on whether update
-- engine is included or not.
-- ~~~~~~
-- GAB 7/27/10 v1_00_a
-- ^^^^^^
-- CR569609
-- Remove double driven signal for exclude update engine mode
-- ~~~~~~
-- GAB 8/12/10 v1_00_a
-- ^^^^^^
-- CR572013
-- Added ability to disable threshold count reset on delay timer timeout in
-- order to match legacy SDMA operation.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- Added ch1_aclk and ch2_aclk to allow for asynchronous operation
-- Added C_ACLK_IS_ASYNC parameter to set mode of clock synchronization
-- ~~~~~~
-- GAB 10/21/10 v2_01_a
-- ^^^^^^
-- Rolled version to v2_01_a
-- Updated to axi_datamover_v3_00_a
-- Updated tstrb ports to tkeep ports
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- Updated AXI Datamover to incorperate new ports and ***_TDATA_WIDTH parameters
-- ~~~~~~
-- GAB 2/2/11 v2_02_a
-- ^^^^^^
-- Update to AXI Datamover v2_01_a
-- ~~~~~~
-- GAB 6/13/11 v3_00_a
-- ^^^^^^
-- Update to AXI Datamover v3_00_a
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream out for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_DESC_UPDATE : integer range 0 to 1 := 1;
-- Include or Exclude Scatter Gather Descriptor Update
-- 0 = Exclude Descriptor Update
-- 1 = Include Descriptor Update
C_INCLUDE_INTRPT : integer range 0 to 1 := 1;
-- Include/Exclude interrupt logic coalescing
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_FAMILY : string := "virtex6"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
dm_resetn : in std_logic ; --
--
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_bvalid : in std_logic ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rlast : in std_logic ; --
m_axi_sg_rvalid : in std_logic ; --
m_axi_sg_rready : out std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
--
--
-- Channel 1 Interrupt Coalescing Signals --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ; --
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
--
--
-- Channel 1 AXI Update Stream In --
s_axis_ch1_updt_aclk : in std_logic ; --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
--
-- Channel 2 Interrupt Coalescing Signals --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
--
-- Channel 2 AXI Update Stream In --
s_axis_ch2_updt_aclk : in std_logic ; --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
--
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--
-- Error addresses --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error : out std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant AXI_LITE_MODE : integer := 2; -- DataMover Lite Mode
constant EXCLUDE : integer := 0; -- Define Exclude as 0
constant NEVER_HALT : std_logic := '0'; -- Never halt sg datamover
-- Always include descriptor fetch (use lite datamover)
constant INCLUDE_DESC_FETCH : integer := AXI_LITE_MODE;
-- Selectable include descriptor update (use lite datamover)
constant INCLUDE_DESC_UPDATE : integer := AXI_LITE_MODE * C_INCLUDE_DESC_UPDATE;
-- Always allow address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- If async mode and number of descriptors to fetch is zero then set number
-- of descriptors to fetch as 1.
constant SG_FTCH_DESC2QUEUE : integer := max2(C_SG_FTCH_DESC2QUEUE,C_AXIS_IS_ASYNC);
constant SG_UPDT_DESC2QUEUE : integer := max2(C_SG_UPDT_DESC2QUEUE,C_AXIS_IS_ASYNC);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- DataMover MM2S Fetch Command Stream Signals
signal s_axis_ftch_cmd_tvalid : std_logic := '0';
signal s_axis_ftch_cmd_tready : std_logic := '0';
signal s_axis_ftch_cmd_tdata : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover MM2S Fetch Status Stream Signals
signal m_axis_ftch_sts_tvalid : std_logic := '0';
signal m_axis_ftch_sts_tready : std_logic := '0';
signal m_axis_ftch_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_ftch_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
-- DataMover MM2S Fetch Stream Signals
signal m_axis_mm2s_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_tkeep : std_logic_vector
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_mm2s_tlast : std_logic := '0';
signal m_axis_mm2s_tvalid : std_logic := '0';
signal m_axis_mm2s_tready : std_logic := '0';
-- DataMover S2MM Update Command Stream Signals
signal s_axis_updt_cmd_tvalid : std_logic := '0';
signal s_axis_updt_cmd_tready : std_logic := '0';
signal s_axis_updt_cmd_tdata : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover S2MM Update Status Stream Signals
signal m_axis_updt_sts_tvalid : std_logic := '0';
signal m_axis_updt_sts_tready : std_logic := '0';
signal m_axis_updt_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_updt_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
-- DataMover S2MM Update Stream Signals
signal s_axis_s2mm_tdata : std_logic_vector
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_tkeep : std_logic_vector
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0) := (others => '1');
signal s_axis_s2mm_tlast : std_logic := '0';
signal s_axis_s2mm_tvalid : std_logic := '0';
signal s_axis_s2mm_tready : std_logic := '0';
-- Channel 1 internals
signal ch1_ftch_active : std_logic := '0';
signal ch1_ftch_queue_empty : std_logic := '0';
signal ch1_ftch_queue_full : std_logic := '0';
signal ch1_nxtdesc_wren : std_logic := '0';
signal ch1_updt_active : std_logic := '0';
signal ch1_updt_queue_empty : std_logic := '0';
signal ch1_updt_curdesc_wren : std_logic := '0';
signal ch1_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_updt_ioc : std_logic := '0';
signal ch1_updt_ioc_irq_set_i : std_logic := '0';
signal ch1_dma_interr : std_logic := '0';
signal ch1_dma_slverr : std_logic := '0';
signal ch1_dma_decerr : std_logic := '0';
signal ch1_dma_interr_set_i : std_logic := '0';
signal ch1_dma_slverr_set_i : std_logic := '0';
signal ch1_dma_decerr_set_i : std_logic := '0';
signal ch1_updt_done : std_logic := '0';
signal ch1_ftch_pause : std_logic := '0';
-- Channel 2 internals
signal ch2_ftch_active : std_logic := '0';
signal ch2_ftch_queue_empty : std_logic := '0';
signal ch2_ftch_queue_full : std_logic := '0';
signal ch2_nxtdesc_wren : std_logic := '0';
signal ch2_updt_active : std_logic := '0';
signal ch2_updt_queue_empty : std_logic := '0';
signal ch2_updt_curdesc_wren : std_logic := '0';
signal ch2_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch2_updt_ioc : std_logic := '0';
signal ch2_updt_ioc_irq_set_i : std_logic := '0';
signal ch2_dma_interr : std_logic := '0';
signal ch2_dma_slverr : std_logic := '0';
signal ch2_dma_decerr : std_logic := '0';
signal ch2_dma_interr_set_i : std_logic := '0';
signal ch2_dma_slverr_set_i : std_logic := '0';
signal ch2_dma_decerr_set_i : std_logic := '0';
signal ch2_updt_done : std_logic := '0';
signal ch2_ftch_pause : std_logic := '0';
signal nxtdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ftch_cmnd_wr : std_logic := '0';
signal ftch_cmnd_data : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
signal ftch_stale_desc : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal updt_error_i : std_logic := '0';
signal ch1_irqthresh_decr : std_logic := '0'; --CR567661
signal ch2_irqthresh_decr : std_logic := '0'; --CR567661
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_error <= updt_error_i;
ftch_error <= ftch_error_i;
-- Always valid therefore fix to '1'
s_axis_s2mm_tkeep <= (others => '1');
-- Drive interrupt on complete set out
--ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i; -- CR567661
--ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i; -- CR567661
ch1_dma_interr_set <= ch1_dma_interr_set_i;
ch1_dma_slverr_set <= ch1_dma_slverr_set_i;
ch1_dma_decerr_set <= ch1_dma_decerr_set_i;
ch2_dma_interr_set <= ch2_dma_interr_set_i;
ch2_dma_slverr_set <= ch2_dma_slverr_set_i;
ch2_dma_decerr_set <= ch2_dma_decerr_set_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Manager
-------------------------------------------------------------------------------
I_SG_FETCH_MNGR : entity axi_vdma_v6_2.axi_sg_ftch_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,
ch1_updt_done => ch1_updt_done ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_interr_set => ch1_ftch_interr_set ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_curdesc => ch1_curdesc ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,
ch2_updt_done => ch2_updt_done ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_interr_set => ch2_ftch_interr_set ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren ,
ch2_taildesc => ch2_taildesc ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_curdesc => ch2_curdesc ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
nxtdesc => nxtdesc ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
mm2s_err => mm2s_err ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
updt_error => updt_error_i ,
ftch_error => ftch_error_i ,
ftch_error_addr => ftch_error_addr
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Queue
-------------------------------------------------------------------------------
I_SG_FETCH_QUEUE : entity axi_vdma_v6_2.axi_sg_ftch_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control
ch1_desc_flush => ch1_desc_flush ,
ch1_ftch_active => ch1_ftch_active ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control
ch2_ftch_active => ch2_ftch_active ,
ch2_desc_flush => ch2_desc_flush ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
nxtdesc => nxtdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => m_axis_ch1_ftch_aclk ,
m_axis_ch1_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_ch1_ftch_tlast ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => m_axis_ch2_ftch_aclk ,
m_axis_ch2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_ch2_ftch_tlast
);
-- Include Scatter Gather Descriptor Update logic
GEN_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 1 generate
begin
-- CR567661
-- Route update version of IOC set to threshold
-- counter decrement control
ch1_irqthresh_decr <= ch1_updt_ioc_irq_set_i;
ch2_irqthresh_decr <= ch2_updt_ioc_irq_set_i;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i;
ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i;
-------------------------------------------------------------------------------
-- Scatter Gather Update Manager
-------------------------------------------------------------------------------
I_SG_UPDATE_MNGR : entity axi_vdma_v6_2.axi_sg_updt_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_updt_idle => ch1_updt_idle ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
ch1_updt_interr_set => ch1_updt_interr_set ,
ch1_updt_slverr_set => ch1_updt_slverr_set ,
ch1_updt_decerr_set => ch1_updt_decerr_set ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_done => ch1_updt_done ,
-- Channel 2 Control and Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_updt_idle => ch2_updt_idle ,
ch2_updt_active => ch2_updt_active ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
ch2_updt_interr_set => ch2_updt_interr_set ,
ch2_updt_slverr_set => ch2_updt_slverr_set ,
ch2_updt_decerr_set => ch2_updt_decerr_set ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_done => ch2_updt_done ,
-- User Command Interface Ports (AXI Stream)
s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_updt_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_updt_sts_tready => m_axis_updt_sts_tready ,
m_axis_updt_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep ,
s2mm_err => s2mm_err ,
ftch_error => ftch_error_i ,
updt_error => updt_error_i ,
updt_error_addr => updt_error_addr
);
-------------------------------------------------------------------------------
-- Scatter Gather Update Queue
-------------------------------------------------------------------------------
I_SG_UPDATE_QUEUE : entity axi_vdma_v6_2.axi_sg_updt_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Channel 1 Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
-- Channel 2 Control
ch2_updt_active => ch2_updt_active ,
ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
-- Channel 2 Update Descriptor Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
-- S2MM Stream Out To DataMover
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => s_axis_ch1_updt_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => s_axis_ch2_updt_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis_ch2_updtsts_tlast => s_axis_ch2_updtsts_tlast
);
end generate GEN_DESC_UPDATE;
-- Exclude Scatter Gather Descriptor Update logic
GEN_NO_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 0 generate
begin
ch1_updt_idle <= '1';
ch1_updt_active <= '0';
-- ch1_updt_ioc_irq_set <= '0';--CR#569609
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set_i <= '0';
ch1_dma_slverr_set_i <= '0';
ch1_dma_decerr_set_i <= '0';
ch1_updt_done <= '1'; -- Always done
ch2_updt_idle <= '1';
ch2_updt_active <= '0';
-- ch2_updt_ioc_irq_set <= '0'; --CR#569609
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set_i <= '0';
ch2_dma_slverr_set_i <= '0';
ch2_dma_decerr_set_i <= '0';
ch2_updt_done <= '1'; -- Always done
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
m_axis_updt_sts_tready <= '0';
updt_error_i <= '0';
updt_error_addr <= (others => '0');
ch1_updt_curdesc_wren <= '0';
ch1_updt_curdesc <= (others => '0');
ch1_updt_queue_empty <= '0';
ch1_updt_ioc <= '0';
ch1_dma_interr <= '0';
ch1_dma_slverr <= '0';
ch1_dma_decerr <= '0';
ch2_updt_curdesc_wren <= '0';
ch2_updt_curdesc <= (others => '0');
ch2_updt_queue_empty <= '0';
ch2_updt_ioc <= '0';
ch2_dma_interr <= '0';
ch2_dma_slverr <= '0';
ch2_dma_decerr <= '0';
s_axis_s2mm_tdata <= (others => '0');
s_axis_s2mm_tlast <= '0';
s_axis_s2mm_tvalid <= '0';
s_axis_ch1_updtptr_tready <= '0';
s_axis_ch2_updtptr_tready <= '0';
s_axis_ch1_updtsts_tready <= '0';
s_axis_ch2_updtsts_tready <= '0';
-- CR567661
-- Route packet eof to threshold counter decrement control
ch1_irqthresh_decr <= ch1_packet_eof;
ch2_irqthresh_decr <= ch2_packet_eof;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_packet_eof;
ch2_updt_ioc_irq_set <= ch2_packet_eof;
end generate GEN_NO_DESC_UPDATE;
-------------------------------------------------------------------------------
-- Scatter Gather Interrupt Coalescing
-------------------------------------------------------------------------------
GEN_INTERRUPT_LOGIC : if C_INCLUDE_INTRPT = 1 generate
begin
I_AXI_SG_INTRPT : entity axi_vdma_v6_2.axi_sg_intrpt
generic map(
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_INCLUDE_DLYTMR => C_INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
ch1_irqthresh_decr => ch1_irqthresh_decr , -- CR567661
ch1_irqthresh_rstdsbl => ch1_irqthresh_rstdsbl , -- CR572013
ch1_dlyirq_dsble => ch1_dlyirq_dsble ,
ch1_irqdelay_wren => ch1_irqdelay_wren ,
ch1_irqdelay => ch1_irqdelay ,
ch1_irqthresh_wren => ch1_irqthresh_wren ,
ch1_irqthresh => ch1_irqthresh ,
ch1_packet_sof => ch1_packet_sof ,
ch1_packet_eof => ch1_packet_eof ,
ch1_ioc_irq_set => ch1_ioc_irq_set ,
ch1_dly_irq_set => ch1_dly_irq_set ,
ch1_irqdelay_status => ch1_irqdelay_status ,
ch1_irqthresh_status => ch1_irqthresh_status ,
ch2_irqthresh_decr => ch2_irqthresh_decr , -- CR567661
ch2_irqthresh_rstdsbl => ch2_irqthresh_rstdsbl , -- CR572013
ch2_dlyirq_dsble => ch2_dlyirq_dsble ,
ch2_irqdelay_wren => ch2_irqdelay_wren ,
ch2_irqdelay => ch2_irqdelay ,
ch2_irqthresh_wren => ch2_irqthresh_wren ,
ch2_irqthresh => ch2_irqthresh ,
ch2_packet_sof => ch2_packet_sof ,
ch2_packet_eof => ch2_packet_eof ,
ch2_ioc_irq_set => ch2_ioc_irq_set ,
ch2_dly_irq_set => ch2_dly_irq_set ,
ch2_irqdelay_status => ch2_irqdelay_status ,
ch2_irqthresh_status => ch2_irqthresh_status
);
end generate GEN_INTERRUPT_LOGIC;
GEN_NO_INTRPT_LOGIC : if C_INCLUDE_INTRPT = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_NO_INTRPT_LOGIC;
-------------------------------------------------------------------------------
-- Scatter Gather DataMover Lite
-------------------------------------------------------------------------------
I_SG_AXI_DATAMOVER : entity axi_datamover_v5_1.axi_datamover
generic map(
C_INCLUDE_MM2S => INCLUDE_DESC_FETCH, -- Lite
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_MM2S_STSFIFO => 0, -- Exclude
C_MM2S_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_MM2S_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_MM2S_DRE => 0, -- No DRE
C_MM2S_BURST_SIZE => 16, -- Set to Min
C_MM2S_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_MM2S_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_INCLUDE_S2MM => INCLUDE_DESC_UPDATE, -- Lite
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_S_AXIS_S2MM_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_S2MM_STSFIFO => 0, -- Exclude
C_S2MM_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_S2MM_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_S2MM_DRE => 0, -- No DRE
C_S2MM_BURST_SIZE => 16, -- Set to Min;
C_S2MM_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_S2MM_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aresetn => dm_resetn ,
mm2s_halt => NEVER_HALT ,
mm2s_halt_cmplt => open ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => m_axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_ftch_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- Datamover v4_032_a addional signals not needed for SG
--sg_ctl => (others => '0') ,
m_axi_mm2s_aruser => open ,
m_axi_s2mm_awuser => open ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_sg_araddr ,
m_axi_mm2s_arlen => m_axi_sg_arlen ,
m_axi_mm2s_arsize => m_axi_sg_arsize ,
m_axi_mm2s_arburst => m_axi_sg_arburst ,
m_axi_mm2s_arprot => m_axi_sg_arprot ,
m_axi_mm2s_arcache => m_axi_sg_arcache ,
m_axi_mm2s_arvalid => m_axi_sg_arvalid ,
m_axi_mm2s_arready => m_axi_sg_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_sg_rdata ,
m_axi_mm2s_rresp => m_axi_sg_rresp ,
m_axi_mm2s_rlast => m_axi_sg_rlast ,
m_axi_mm2s_rvalid => m_axi_sg_rvalid ,
m_axi_mm2s_rready => m_axi_sg_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_sg_aclk ,
m_axi_s2mm_aresetn => dm_resetn ,
s2mm_halt => NEVER_HALT ,
s2mm_halt_cmplt => open ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => m_axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_updt_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_updt_sts_tkeep ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_sg_awaddr ,
m_axi_s2mm_awlen => m_axi_sg_awlen ,
m_axi_s2mm_awsize => m_axi_sg_awsize ,
m_axi_s2mm_awburst => m_axi_sg_awburst ,
m_axi_s2mm_awprot => m_axi_sg_awprot ,
m_axi_s2mm_awcache => m_axi_sg_awcache ,
m_axi_s2mm_awvalid => m_axi_sg_awvalid ,
m_axi_s2mm_awready => m_axi_sg_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_sg_wdata ,
m_axi_s2mm_wstrb => m_axi_sg_wstrb ,
m_axi_s2mm_wlast => m_axi_sg_wlast ,
m_axi_s2mm_wvalid => m_axi_sg_wvalid ,
m_axi_s2mm_wready => m_axi_sg_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_sg_bresp ,
m_axi_s2mm_bvalid => m_axi_sg_bvalid ,
m_axi_s2mm_bready => m_axi_sg_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
end implementation;
|
gpl-2.0
|
d6be6370e2f1a125a76efada351d4cab
| 0.3872 | 4.245876 | false | false | false | false |
frznchckn/polarbear
|
hw/cores/uart_bfm/hdl/vhdl/uart_bfm_pkgbdy.vhd
| 1 | 1,887 |
--------------------------------------------------------------------------------
--|
--| Filename : uart_bfm_pkgbdy
--| Author : Russell L Friesenhahn
--| Origin Date : 20130828
--|
--------------------------------------------------------------------------------
--|
--| Abstract
--|
--| Package definition that provides functions and procedures that model a
--| UART interface to provide BFM capabilities.
--|
--------------------------------------------------------------------------------
--|
--| Modification History
--|
--|
--|
--------------------------------------------------------------------------------
--|
--| References
--|
--|
--|
--------------------------------------------------------------------------------
package body uart_bfm is
function parityCalc (
s : std_ulogic_vector(7 downto 0);
parityType : std_ulogic
)
return std_ulogic is
variable result : std_ulogic := parityType;
begin
for i in 7 downto 0 loop
result := result xor s(i);
end loop;
return result;
end parityCalc;
procedure uart_tx_byte (
parity : in string := "none"; -- none | odd | even
numStopbits : in integer := 1; -- 1 | 2
byte : in std_ulogic_vector(7 downto 0);
-- signal clk : in std_ulogic;
signal tx_bit : out std_logic
) is
begin
tx_bit <= '1';
-- tx_bit <= '0' after 8695 ns;
wait for 8681 ns;
tx_bit <= '0';
wait for 8681 ns;
for i in 0 to 7
loop
tx_bit <= byte(i);
wait for 8681 ns;
-- tx_bit <= byte(i) after 8695 ns;
end loop;
if parity = "odd"
then
tx_bit <= parityCalc(byte, '1');
wait for 8681 ns;
elsif parity = "even"
then
tx_bit <= parityCalc(byte, '0');
wait for 8681 ns;
end if;
tx_bit <= '1';
-- wait for 8681 ns;
-- tx_bit <= '1' after 8695 ns;
end uart_tx_byte;
end uart_bfm;
|
unlicense
|
4b0a370585f0c6c5f6e56e1e2a92872b
| 0.442501 | 4.120087 | false | false | false | false |
nulldozer/purisc
|
top_level.vhd
| 2 | 39,097 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
PORT(
--ONLY PHY CONNECTIONS IN TOP LEVEL
CLOCK_50 : IN STD_LOGIC;
SW : IN STD_LOGIC_VECTOR(17 downto 0);
HEX0, HEX1, HEX2, HEX3,
HEX4, HEX5, HEX6, HEX7 : OUT std_logic_vector(6 downto 0);
ENET0_MDC : OUT STD_LOGIC; -- Management data clock reference
ENET0_MDIO : INOUT STD_LOGIC; -- Management Data
ENET0_RESET_N : OUT STD_LOGIC; -- Hardware reset Signal
ENET0_RX_CLK : IN STD_LOGIC; -- GMII/MII Receive clock
ENET0_RX_COL : IN STD_LOGIC; -- GMII/MII Collision
ENET0_RX_CRS : IN STD_LOGIC; -- GMII/MII Carrier sense
ENET0_RX_DATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- GMII/MII Receive data
ENET0_RX_DV : IN STD_LOGIC; -- GMII/MII Receive data valid
ENET0_RX_ER : IN STD_LOGIC; -- GMII/MII Receive error
ENET0_TX_CLK : IN STD_LOGIC; -- MII Transmit Clock
ENET0_TX_DATA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- MII Transmit Data
ENET0_TX_EN : OUT STD_LOGIC; -- GMII/MII Transmit enable
ENET0_TX_ER : OUT STD_LOGIC
);
end;
architecture purisc of top_level is
component io_controller
PORT(
CLOCK_50 : IN STD_LOGIC;
RESET : IN STD_LOGIC;
wb_mem_adr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
wb_mem_sel_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wb_mem_we_o : OUT STD_LOGIC;
wb_mem_cyc_o : OUT STD_LOGIC;
wb_mem_stb_o : OUT STD_LOGIC;
wb_mem_ack_i : IN STD_LOGIC;
wb_mem_dat_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
wb_mem_dat_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wb_mem_err_i : IN STD_LOGIC;
ENET0_MDC : OUT STD_LOGIC; -- Management data clock reference
ENET0_MDIO : INOUT STD_LOGIC; -- Management Data
ENET0_RST_N : OUT STD_LOGIC; -- Hardware reset Signal
ENET0_RX_CLK : IN STD_LOGIC; -- GMII/MII Receive clock
ENET0_RX_COL : IN STD_LOGIC; -- GMII/MII Collision
ENET0_RX_CRS : IN STD_LOGIC; -- GMII/MII Carrier sense
ENET0_RX_DATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- GMII/MII Receive data
ENET0_RX_DV : IN STD_LOGIC; -- GMII/MII Receive data valid
ENET0_RX_ER : IN STD_LOGIC; -- GMII/MII Receive error
ENET0_TX_CLK : IN STD_LOGIC; -- MII Transmit Clock
ENET0_TX_DATA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- MII Transmit Data
ENET0_TX_EN : OUT STD_LOGIC; -- GMII/MII Transmit enable
ENET0_TX_ER : OUT STD_LOGIC; -- GMII/MII Transmit error
M : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
arq_n : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
tx_len : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
flag_ready : OUT STD_LOGIC;
flag_done_clear : OUT STD_LOGIC;
flag_ack : IN STD_LOGIC;
flag_done : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hex_val0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hex_val1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hex_val2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hex_val3 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hex_val4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hex_val5 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hex_val6 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hex_val7 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end component;
component io_memory_controller
PORT(
wb_rst_i : IN STD_LOGIC;
wb_clk_i : IN STD_LOGIC;
--connections to magics
mem_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
mem_data_w : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
mem_we : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mem_gl_en : OUT STD_LOGIC;
mem_gl_data_r : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
--WISHBONE slave
wb_adr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- WISHBONE address input
wb_sel_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- WISHBONE byte select input
wb_we_i : IN STD_LOGIC; -- WISHBONE write enable input
wb_cyc_i : IN STD_LOGIC; -- WISHBONE cycle input
wb_stb_i : IN STD_LOGIC; -- WISHBONE strobe input
wb_ack_o : OUT STD_LOGIC; -- WISHBONE acknowledge output
wb_dat_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- WISHBONE data input
wb_dat_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- WISHBONE data output
wb_err_o : OUT STD_LOGIC; -- WISHBONE error output
M : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
flag_ready : IN STD_LOGIC;
flag_ack : OUT STD_LOGIC;
flag_done_clear : IN STD_LOGIC;
arq_n : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
tx_len : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
end component;
component global_memory
PORT (
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
--compute group 0
ADDRESS_A_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_0_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_1_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_W_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_CG0 : IN STD_LOGIC;
ENABLE_CG0 : IN STD_LOGIC;
DATA_A_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_B_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_C_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_0_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_1_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
STALL_CG0 : OUT STD_LOGIC;
--compute group 1
ADDRESS_A_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_0_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_1_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_W_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_CG1 : IN STD_LOGIC;
ENABLE_CG1 : IN STD_LOGIC;
DATA_A_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_B_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_C_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_0_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_1_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
STALL_CG1 : OUT STD_LOGIC;
--compute group 2
ADDRESS_A_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_0_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_1_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_W_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_CG2 : IN STD_LOGIC;
ENABLE_CG2 : IN STD_LOGIC;
DATA_A_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_B_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_C_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_0_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_1_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
STALL_CG2 : OUT STD_LOGIC;
--compute group 3
ADDRESS_A_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_0_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_1_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_W_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_CG3 : IN STD_LOGIC;
ENABLE_CG3 : IN STD_LOGIC;
DATA_A_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_B_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_C_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_0_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_1_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
STALL_CG3 : OUT STD_LOGIC;
--IO controller
ADDRESS_IO : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_IO : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_IO : IN STD_LOGIC;
ENABLE_IO : IN STD_LOGIC;
DATA_RET_IO : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--DONE signals
DONE_C0 : OUT STD_LOGIC;
DONE_C1 : OUT STD_LOGIC;
DONE_C2 : OUT STD_LOGIC;
DONE_C3 : OUT STD_LOGIC;
DONE_C4 : OUT STD_LOGIC;
DONE_C5 : OUT STD_LOGIC;
DONE_C6 : OUT STD_LOGIC;
DONE_C7 : OUT STD_LOGIC;
RCC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end component;
component Compute_Group
PORT (
ADDRESS_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
IO_ENABLE : IN STD_LOGIC;
DATA_TO_W : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
GLOBAL_EN : OUT STD_LOGIC;
IDENT_IN : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
DATA_OUT_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
STALL_GLOB : IN STD_LOGIC
);
end component;
component convert_to_seven_seg
port (
data_in : in std_logic_vector(3 downto 0);
hex_out : out std_logic_vector(6 downto 0)
);
end component;
signal ident_cg0 : std_logic_vector(1 downto 0);
signal ident_cg1 : std_logic_vector(1 downto 0);
signal ident_cg2 : std_logic_vector(1 downto 0);
signal ident_cg3 : std_logic_vector(1 downto 0);
signal address_a_cg0_sig : std_logic_vector(31 downto 0);
signal address_b_cg0_sig : std_logic_vector(31 downto 0);
signal address_c_cg0_sig : std_logic_vector(31 downto 0);
signal address_0_cg0_sig : std_logic_vector(31 downto 0);
signal address_1_cg0_sig : std_logic_vector(31 downto 0);
signal address_w_cg0_sig : std_logic_vector(31 downto 0);
signal data_to_w_cg0_sig : std_logic_vector(31 downto 0);
signal w_en_cg0_sig : std_logic;
signal enable_global_cg0_sig : std_logic;
signal stall_global_cg0_sig : std_logic;
signal data_a_cg0_sig : std_logic_vector(31 downto 0);
signal data_b_cg0_sig : std_logic_vector(31 downto 0);
signal data_c_cg0_sig : std_logic_vector(31 downto 0);
signal data_0_cg0_sig : std_logic_vector(31 downto 0);
signal data_1_cg0_sig : std_logic_vector(31 downto 0);
signal address_a_cg1_sig : std_logic_vector(31 downto 0);
signal address_b_cg1_sig : std_logic_vector(31 downto 0);
signal address_c_cg1_sig : std_logic_vector(31 downto 0);
signal address_0_cg1_sig : std_logic_vector(31 downto 0);
signal address_1_cg1_sig : std_logic_vector(31 downto 0);
signal address_w_cg1_sig : std_logic_vector(31 downto 0);
signal data_to_w_cg1_sig : std_logic_vector(31 downto 0);
signal w_en_cg1_sig : std_logic;
signal enable_global_cg1_sig : std_logic;
signal stall_global_cg1_sig : std_logic;
signal data_a_cg1_sig : std_logic_vector(31 downto 0);
signal data_b_cg1_sig : std_logic_vector(31 downto 0);
signal data_c_cg1_sig : std_logic_vector(31 downto 0);
signal data_0_cg1_sig : std_logic_vector(31 downto 0);
signal data_1_cg1_sig : std_logic_vector(31 downto 0);
signal address_a_cg2_sig : std_logic_vector(31 downto 0);
signal address_b_cg2_sig : std_logic_vector(31 downto 0);
signal address_c_cg2_sig : std_logic_vector(31 downto 0);
signal address_0_cg2_sig : std_logic_vector(31 downto 0);
signal address_1_cg2_sig : std_logic_vector(31 downto 0);
signal address_w_cg2_sig : std_logic_vector(31 downto 0);
signal data_to_w_cg2_sig : std_logic_vector(31 downto 0);
signal w_en_cg2_sig : std_logic;
signal enable_global_cg2_sig : std_logic;
signal stall_global_cg2_sig : std_logic;
signal data_a_cg2_sig : std_logic_vector(31 downto 0);
signal data_b_cg2_sig : std_logic_vector(31 downto 0);
signal data_c_cg2_sig : std_logic_vector(31 downto 0);
signal data_0_cg2_sig : std_logic_vector(31 downto 0);
signal data_1_cg2_sig : std_logic_vector(31 downto 0);
signal address_a_cg3_sig : std_logic_vector(31 downto 0);
signal address_b_cg3_sig : std_logic_vector(31 downto 0);
signal address_c_cg3_sig : std_logic_vector(31 downto 0);
signal address_0_cg3_sig : std_logic_vector(31 downto 0);
signal address_1_cg3_sig : std_logic_vector(31 downto 0);
signal address_w_cg3_sig : std_logic_vector(31 downto 0);
signal data_to_w_cg3_sig : std_logic_vector(31 downto 0);
signal w_en_cg3_sig : std_logic;
signal enable_global_cg3_sig : std_logic;
signal stall_global_cg3_sig : std_logic;
signal data_a_cg3_sig : std_logic_vector(31 downto 0);
signal data_b_cg3_sig : std_logic_vector(31 downto 0);
signal data_c_cg3_sig : std_logic_vector(31 downto 0);
signal data_0_cg3_sig : std_logic_vector(31 downto 0);
signal data_1_cg3_sig : std_logic_vector(31 downto 0);
signal address_io_sig : std_logic_vector(31 downto 0);
signal data_to_w_io_sig : std_logic_vector(31 downto 0);
signal data_read_io_sig : std_logic_vector(31 downto 0);
signal w_en_io_sig : std_logic;
signal enable_io_cg0 : std_logic;
signal enable_io_cg1 : std_logic;
signal enable_io_cg2 : std_logic;
signal enable_io_cg3 : std_logic;
signal enable_io_global : std_logic;
-- signal test_reg : std_logic_vector(31 downto 0);
signal RESET_n : std_logic;
signal RESET : std_logic;
signal wb_adr : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
signal wb_we : std_logic;
signal wb_cyc : std_logic;
signal wb_stb : std_logic;
signal wb_ack : std_logic;
signal wb_dat_o : std_logic_vector(31 downto 0);
signal wb_dat_i : std_logic_vector(31 downto 0);
signal wb_err : std_logic;
signal M : std_logic_vector(15 downto 0);
signal hex_val0 : std_logic_vector(3 downto 0);
signal hex_val1 : std_logic_vector(3 downto 0);
signal hex_val2 : std_logic_vector(3 downto 0);
signal hex_val3 : std_logic_vector(3 downto 0);
signal hex_val4 : std_logic_vector(3 downto 0);
signal hex_val5 : std_logic_vector(3 downto 0);
signal hex_val6 : std_logic_vector(3 downto 0);
signal hex_val7 : std_logic_vector(3 downto 0);
signal mem_we : std_logic_vector(4 downto 0);
signal to_hex_0 : std_logic_vector(3 downto 0);
signal to_hex_1 : std_logic_vector(3 downto 0);
signal to_hex_2 : std_logic_vector(3 downto 0);
signal to_hex_3 : std_logic_vector(3 downto 0);
signal to_hex_4 : std_logic_vector(3 downto 0);
signal to_hex_5 : std_logic_vector(3 downto 0);
signal to_hex_6 : std_logic_vector(3 downto 0);
signal to_hex_7 : std_logic_vector(3 downto 0);
signal test_float_a : std_logic_vector(31 downto 0);
signal test_float_b : std_logic_vector(31 downto 0);
signal test_float_c : std_logic_vector(4 downto 0);
signal test_float_d : std_logic;
signal test_float_e : std_logic_vector(31 downto 0);
signal arq_n : std_logic_vector(15 downto 0);
signal tx_len : std_logic_vector(15 downto 0);
signal flag_ready : std_logic;
signal flag_ack : std_logic;
signal flag_done : std_logic_vector(7 downto 0);
signal flag_done_clear : std_logic;
signal DONE_C0 : std_logic;
signal DONE_C1 : std_logic;
signal DONE_C2 : std_logic;
signal DONE_C3 : std_logic;
signal DONE_C4 : std_logic;
signal DONE_C5 : std_logic;
signal DONE_C6 : std_logic;
signal DONE_C7 : std_logic;
signal perf_counter : unsigned(63 downto 0);
signal counter_active : std_logic;
signal ready_rising_edge : std_logic;
signal done_rising_edge : std_logic;
signal all_done : std_logic;
signal all_done_buff : std_logic;
signal ready_buff : std_logic;
signal RCC : std_logic_vector(3 downto 0);
signal enable_io_global_raw : std_logic;
begin
RESET_n <= SW(17);
RESET <= not RESET_n;
--IO CONTROLLER SIGNALS HARDCODED FOR NOW
ident_cg0 <= "00";
ident_cg1 <= "01";
ident_cg2 <= "10";
ident_cg3 <= "11";
-- address_io_sig <= "00000000000000000000000000000000";
-- data_to_w_io_sig <= "00000000000000000000000000000000";
-- w_en_io_sig <= '0';
-- enable_io_cg0 <= '0';
-- enable_io_cg1 <= '0';
-- enable_io_cg2 <= '0';
-- enable_io_cg3 <= '0';
-- enable_io_global <= '0';
enable_io_cg0 <= mem_we(0);
enable_io_cg1 <= mem_we(1);
enable_io_cg2 <= mem_we(2);
enable_io_cg3 <= mem_we(3);
------ w_en_cg0_sig <= mem_we(0);
------ w_en_cg1_sig <= mem_we(1);
------ w_en_cg2_sig <= mem_we(2);
------ w_en_cg3_sig <= mem_we(3);
w_en_io_sig <= mem_we(4);
enable_io_global <= enable_io_global_raw or w_en_io_sig;
ioc : io_controller PORT MAP(
CLOCK_50 => CLOCK_50,
RESET => RESET,
wb_mem_adr_o => wb_adr,
wb_mem_sel_o => wb_sel,
wb_mem_we_o => wb_we,
wb_mem_cyc_o => wb_cyc,
wb_mem_stb_o => wb_stb,
wb_mem_ack_i => wb_ack,
wb_mem_dat_o => wb_dat_o,
wb_mem_dat_i => wb_dat_i,
wb_mem_err_i => wb_err,
ENET0_MDC => ENET0_MDC, -- Management data clock reference
ENET0_MDIO => ENET0_MDIO, -- Management Data
ENET0_RST_N => ENET0_RESET_N, -- Hardware reset Signal
ENET0_RX_CLK => ENET0_RX_CLK, -- GMII/MII Receive clock
ENET0_RX_COL => ENET0_RX_COL, -- GMII/MII Collision
ENET0_RX_CRS => ENET0_RX_CRS, -- GMII/MII Carrier sense
ENET0_RX_DATA => ENET0_RX_DATA, -- GMII/MII Receive data
ENET0_RX_DV => ENET0_RX_DV, -- GMII/MII Receive data valid
ENET0_RX_ER => ENET0_RX_ER, -- GMII/MII Receive error
ENET0_TX_CLK => ENET0_TX_CLK, -- MII Transmit Clock
ENET0_TX_DATA => ENET0_TX_DATA, -- MII Transmit Data
ENET0_TX_EN => ENET0_TX_EN, -- GMII/MII Transmit enable
ENET0_TX_ER => ENET0_TX_ER, -- GMII/MII Transmit error
M => M,
flag_ready => flag_ready,
flag_ack => flag_ack,
flag_done_clear => flag_done_clear,
flag_done => flag_done,
hex_val0 => hex_val0,
hex_val1 => hex_val1,
hex_val2 => hex_val2,
hex_val3 => hex_val3,
hex_val4 => hex_val4,
hex_val5 => hex_val5,
hex_val6 => hex_val6,
hex_val7 => hex_val7,
arq_n => arq_n,
tx_len => tx_len
);
iomc : io_memory_controller PORT MAP(
--connections to magics
mem_addr => address_io_sig,
mem_data_w => data_to_w_io_sig,
mem_we => mem_we,
mem_gl_en => enable_io_global_raw,
mem_gl_data_r => data_read_io_sig,
wb_clk_i => CLOCK_50, -- WISHBONE clock
wb_rst_i => RESET, -- WISHBONE reset
wb_adr_i => wb_adr, -- WISHBONE address input
wb_sel_i => wb_sel, -- WISHBONE byte select input
wb_we_i => wb_we, -- WISHBONE write enable input
wb_cyc_i => wb_cyc, -- WISHBONE cycle input
wb_stb_i => wb_stb, -- WISHBONE strobe input
wb_ack_o => wb_ack, -- WISHBONE acknowledge output
wb_dat_i => wb_dat_o, -- WISHBONE data input
wb_dat_o => wb_dat_i, -- WISHBONE data output
wb_err_o => wb_err, -- WISHBONE error output
M => M,
flag_ready => flag_ready,
flag_ack => flag_ack,
flag_done_clear => flag_done_clear,
arq_n => arq_n,
tx_len => tx_len
);
Compute_Group_0 : Compute_Group PORT MAP (
ADDRESS_A => address_a_cg0_sig,
ADDRESS_B => address_b_cg0_sig,
ADDRESS_C => address_c_cg0_sig,
ADDRESS_0 => address_0_cg0_sig,
ADDRESS_1 => address_1_cg0_sig,
ADDRESS_W => address_w_cg0_sig,
ADDRESS_IO => address_io_sig,
DATA_IO => data_to_w_io_sig,
IO_ENABLE => enable_io_cg0,
DATA_TO_W => data_to_w_cg0_sig,
W_EN => w_en_cg0_sig,
CLK => CLOCK_50,
RESET_n => RESET_n,
GLOBAL_EN => enable_global_cg0_sig,
IDENT_IN => ident_cg0,
DATA_OUT_A => data_a_cg0_sig,
DATA_OUT_B => data_b_cg0_sig,
DATA_OUT_C => data_c_cg0_sig,
DATA_OUT_0 => data_0_cg0_sig,
DATA_OUT_1 => data_1_cg0_sig,
STALL_GLOB => stall_global_cg0_sig
);
Compute_Group_1 : Compute_Group PORT MAP (
ADDRESS_A => address_a_cg1_sig,
ADDRESS_B => address_b_cg1_sig,
ADDRESS_C => address_c_cg1_sig,
ADDRESS_0 => address_0_cg1_sig,
ADDRESS_1 => address_1_cg1_sig,
ADDRESS_W => address_w_cg1_sig,
ADDRESS_IO => address_io_sig,
DATA_IO => data_to_w_io_sig,
IO_ENABLE => enable_io_cg1,
DATA_TO_W => data_to_w_cg1_sig,
W_EN => w_en_cg1_sig,
CLK => CLOCK_50,
RESET_n => RESET_n,
GLOBAL_EN => enable_global_cg1_sig,
IDENT_IN => ident_cg1,
DATA_OUT_A => data_a_cg1_sig,
DATA_OUT_B => data_b_cg1_sig,
DATA_OUT_C => data_c_cg1_sig,
DATA_OUT_0 => data_0_cg1_sig,
DATA_OUT_1 => data_1_cg1_sig,
STALL_GLOB => stall_global_cg1_sig
);
Compute_Group_2 : Compute_Group PORT MAP (
ADDRESS_A => address_a_cg2_sig,
ADDRESS_B => address_b_cg2_sig,
ADDRESS_C => address_c_cg2_sig,
ADDRESS_0 => address_0_cg2_sig,
ADDRESS_1 => address_1_cg2_sig,
ADDRESS_W => address_w_cg2_sig,
ADDRESS_IO => address_io_sig,
DATA_IO => data_to_w_io_sig,
IO_ENABLE => enable_io_cg2,
DATA_TO_W => data_to_w_cg2_sig,
W_EN => w_en_cg2_sig,
CLK => CLOCK_50,
RESET_n => RESET_n,
GLOBAL_EN => enable_global_cg2_sig,
IDENT_IN => ident_cg2,
DATA_OUT_A => data_a_cg2_sig,
DATA_OUT_B => data_b_cg2_sig,
DATA_OUT_C => data_c_cg2_sig,
DATA_OUT_0 => data_0_cg2_sig,
DATA_OUT_1 => data_1_cg2_sig,
STALL_GLOB => stall_global_cg2_sig
);
Compute_Group_3 : Compute_Group PORT MAP (
ADDRESS_A => address_a_cg3_sig,
ADDRESS_B => address_b_cg3_sig,
ADDRESS_C => address_c_cg3_sig,
ADDRESS_0 => address_0_cg3_sig,
ADDRESS_1 => address_1_cg3_sig,
ADDRESS_W => address_w_cg3_sig,
ADDRESS_IO => address_io_sig,
DATA_IO => data_to_w_io_sig,
IO_ENABLE => enable_io_cg3,
DATA_TO_W => data_to_w_cg3_sig,
W_EN => w_en_cg3_sig,
CLK => CLOCK_50,
RESET_n => RESET_n,
GLOBAL_EN => enable_global_cg3_sig,
IDENT_IN => ident_cg3,
DATA_OUT_A => data_a_cg3_sig,
DATA_OUT_B => data_b_cg3_sig,
DATA_OUT_C => data_c_cg3_sig,
DATA_OUT_0 => data_0_cg3_sig,
DATA_OUT_1 => data_1_cg3_sig,
STALL_GLOB => stall_global_cg3_sig
);
level_2_memory : global_memory PORT MAP(
CLK => CLOCK_50,
RESET_n => RESET_n,
--compute group 0
ADDRESS_A_CG0 => address_a_cg0_sig,
ADDRESS_B_CG0 => address_b_cg0_sig,
ADDRESS_C_CG0 => address_c_cg0_sig,
ADDRESS_0_CG0 => address_0_cg0_sig,
ADDRESS_1_CG0 => address_1_cg0_sig,
ADDRESS_W_CG0 => address_w_cg0_sig,
DATA_TO_W_CG0 => data_to_w_cg0_sig,
W_EN_CG0 => w_en_cg0_sig,
ENABLE_CG0 => enable_global_cg0_sig,
DATA_A_TO_CG0 => data_a_cg0_sig,
DATA_B_TO_CG0 => data_b_cg0_sig,
DATA_C_TO_CG0 => data_c_cg0_sig,
DATA_0_TO_CG0 => data_0_cg0_sig,
DATA_1_TO_CG0 => data_1_cg0_sig,
STALL_CG0 => stall_global_cg0_sig,
--compute group 1
ADDRESS_A_CG1 => address_a_cg1_sig,
ADDRESS_B_CG1 => address_b_cg1_sig,
ADDRESS_C_CG1 => address_c_cg1_sig,
ADDRESS_0_CG1 => address_0_cg1_sig,
ADDRESS_1_CG1 => address_1_cg1_sig,
ADDRESS_W_CG1 => address_w_cg1_sig,
DATA_TO_W_CG1 => data_to_w_cg1_sig,
W_EN_CG1 => w_en_cg1_sig,
ENABLE_CG1 => enable_global_cg1_sig,
DATA_A_TO_CG1 => data_a_cg1_sig,
DATA_B_TO_CG1 => data_b_cg1_sig,
DATA_C_TO_CG1 => data_c_cg1_sig,
DATA_0_TO_CG1 => data_0_cg1_sig,
DATA_1_TO_CG1 => data_1_cg1_sig,
STALL_CG1 => stall_global_cg1_sig,
--compute group 2
ADDRESS_A_CG2 => address_a_cg2_sig,
ADDRESS_B_CG2 => address_b_cg2_sig,
ADDRESS_C_CG2 => address_c_cg2_sig,
ADDRESS_0_CG2 => address_0_cg2_sig,
ADDRESS_1_CG2 => address_1_cg2_sig,
ADDRESS_W_CG2 => address_w_cg2_sig,
DATA_TO_W_CG2 => data_to_w_cg2_sig,
W_EN_CG2 => w_en_cg2_sig,
ENABLE_CG2 => enable_global_cg2_sig,
DATA_A_TO_CG2 => data_a_cg2_sig,
DATA_B_TO_CG2 => data_b_cg2_sig,
DATA_C_TO_CG2 => data_c_cg2_sig,
DATA_0_TO_CG2 => data_0_cg2_sig,
DATA_1_TO_CG2 => data_1_cg2_sig,
STALL_CG2 => stall_global_cg2_sig,
--compute group 3
ADDRESS_A_CG3 => address_a_cg3_sig,
ADDRESS_B_CG3 => address_b_cg3_sig,
ADDRESS_C_CG3 => address_c_cg3_sig,
ADDRESS_0_CG3 => address_0_cg3_sig,
ADDRESS_1_CG3 => address_1_cg3_sig,
ADDRESS_W_CG3 => address_w_cg3_sig,
DATA_TO_W_CG3 => data_to_w_cg3_sig,
W_EN_CG3 => w_en_cg3_sig,
ENABLE_CG3 => enable_global_cg3_sig,
DATA_A_TO_CG3 => data_a_cg3_sig,
DATA_B_TO_CG3 => data_b_cg3_sig,
DATA_C_TO_CG3 => data_c_cg3_sig,
DATA_0_TO_CG3 => data_0_cg3_sig,
DATA_1_TO_CG3 => data_1_cg3_sig,
STALL_CG3 => stall_global_cg3_sig,
--IO controller
ADDRESS_IO => address_io_sig,
DATA_TO_W_IO => data_to_w_io_sig,
W_EN_IO => w_en_io_sig,
ENABLE_IO => enable_io_global,
DATA_RET_IO => data_read_io_sig,
--DONE flags
DONE_C0 => DONE_C0,
DONE_C1 => DONE_C1,
DONE_C2 => DONE_C2,
DONE_C3 => DONE_C3,
DONE_C4 => DONE_C4,
DONE_C5 => DONE_C5,
DONE_C6 => DONE_C6,
DONE_C7 => DONE_C7,
RCC => RCC
);
flag_done <= DONE_C7 & DONE_C6 & DONE_C5 & DONE_C4 & DONE_C3 & DONE_C2 & DONE_C1 & DONE_C0;
all_done <= DONE_C7 and DONE_C6 and DONE_C5 and DONE_C4 and DONE_C3 and DONE_C2 and DONE_C1 and DONE_C0;
-- process (SW, hex_val0, hex_val1, hex_val2, hex_val3, hex_val4, hex_val5,
-- hex_val6, hex_val7, test_reg) begin
-- if (SW(0) = '1')then
to_hex_0 <= hex_val0;
to_hex_1 <= hex_val1;
to_hex_2 <= hex_val2;
--to_hex_3 <= hex_val3;
to_hex_3 <= RCC;
to_hex_4 <= hex_val4;
to_hex_5 <= hex_val5;
to_hex_6 <= flag_done(3 downto 0);
to_hex_7 <= flag_done(7 downto 4);
--to_hex_6 <= hex_val6;
--to_hex_7 <= hex_val7;
-- else
-- to_hex_0 <= test_reg(3 downto 0);
-- to_hex_1 <= test_reg(7 downto 4);
-- to_hex_2 <= test_reg(11 downto 8);
-- to_hex_3 <= test_reg(15 downto 12);
-- to_hex_4 <= test_reg(19 downto 16);
-- to_hex_5 <= test_reg(23 downto 20);
-- to_hex_6 <= test_reg(27 downto 24);
-- to_hex_7 <= test_reg(31 downto 28);
-- end if;
-- end process;
hex_convert_0 : convert_to_seven_seg port map (
to_hex_0,
HEX0
);
hex_convert_1 : convert_to_seven_seg port map (
to_hex_1,
HEX1
);
hex_convert_2 : convert_to_seven_seg port map(
to_hex_2,
HEX2
);
hex_convert_3 : convert_to_seven_seg port map(
to_hex_3,
HEX3
);
hex_convert_4 : convert_to_seven_seg port map(
to_hex_4,
HEX4
);
hex_convert_5 : convert_to_seven_seg port map(
to_hex_5,
HEX5
);
hex_convert_6 : convert_to_seven_seg port map(
to_hex_6,
HEX6
);
hex_convert_7 : convert_to_seven_seg port map(
to_hex_7,
HEX7
);
--PERFORMANCE COUNTER LOGIC;
--buffering signals for edge detector
process (CLOCK_50, RESET_n, flag_ready, all_done) begin
if (RESET_n = '0') then
ready_buff <= '0';
all_done_buff <= '0';
elsif (rising_edge(CLOCK_50)) then
ready_buff <= flag_ready;
all_done_buff <= all_done;
end if;
end process;
--edge detector
ready_rising_edge <= (flag_ready xor ready_buff) and flag_ready;
done_rising_edge <= (all_done_buff xor all_done) and all_done;
--counter enable
process (CLOCK_50, RESET_n, ready_rising_edge, done_rising_edge) begin
if (RESET_n = '0') then
counter_active <= '0';
elsif (rising_edge(CLOCK_50)) then
if(ready_rising_edge = '1') then
counter_active <= '1';
elsif(done_rising_edge = '1') then
counter_active <= '0';
end if;
end if;
end process;
--counter itself
process (CLOCK_50, RESET_n, counter_active, ready_rising_edge) begin
if (RESET_n = '0') then
perf_counter <= "0000000000000000000000000000000000000000000000000000000000000000";
elsif (rising_edge(CLOCK_50)) then
if (counter_active = '1') then
perf_counter <= perf_counter + 1;
elsif (ready_rising_edge = '1') then
perf_counter <= "0000000000000000000000000000000000000000000000000000000000000000";
end if;
end if;
end process;
end;
|
gpl-2.0
|
87ed4171afcd2ab2d090e32c01279920
| 0.448244 | 3.684573 | false | false | false | false |
freecores/t48
|
rtl/vhdl/system/t8048.vhd
| 1 | 7,425 |
-------------------------------------------------------------------------------
--
-- T8048 Microcontroller System
--
-- $Id: t8048.vhd,v 1.11 2006-07-14 01:13:32 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t8048 is
port (
xtal_i : in std_logic;
reset_n_i : in std_logic;
t0_b : inout std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_b : inout std_logic_vector( 7 downto 0);
t1_i : in std_logic;
p2_b : inout std_logic_vector( 7 downto 0);
p1_b : inout std_logic_vector( 7 downto 0);
prog_n_o : out std_logic
);
end t8048;
library ieee;
use ieee.numeric_std.all;
use work.t48_system_comp_pack.t8048_notri;
architecture struct of t8048 is
signal t0_s : std_logic;
signal t0_dir_s : std_logic;
signal db_s : std_logic_vector( 7 downto 0);
signal db_dir_s : std_logic;
signal p2_s : std_logic_vector( 7 downto 0);
signal p2l_low_imp_s : std_logic;
signal p2h_low_imp_s : std_logic;
signal p1_s : std_logic_vector( 7 downto 0);
signal p1_low_imp_s : std_logic;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
t8048_notri_b : t8048_notri
generic map (
-- we don't need explicit gating of input ports
-- this is done implicitely by the bidirectional pads
gate_port_input_g => 0
)
port map (
xtal_i => xtal_i,
xtal_en_i => vdd_s,
reset_n_i => reset_n_i,
t0_i => t0_b,
t0_o => t0_s,
t0_dir_o => t0_dir_s,
int_n_i => int_n_i,
ea_i => ea_i,
rd_n_o => rd_n_o,
psen_n_o => psen_n_o,
wr_n_o => wr_n_o,
ale_o => ale_o,
db_i => db_b,
db_o => db_s,
db_dir_o => db_dir_s,
t1_i => t1_i,
p2_i => p2_b,
p2_o => p2_s,
p2l_low_imp_o => p2l_low_imp_s,
p2h_low_imp_o => p2h_low_imp_s,
p1_i => p1_b,
p1_o => p1_s,
p1_low_imp_o => p1_low_imp_s,
prog_n_o => prog_n_o
);
-----------------------------------------------------------------------------
-- Process bidirs
--
-- Purpose:
-- Assign bidirectional signals.
--
bidirs: process (t0_b, t0_s, t0_dir_s,
db_b, db_s, db_dir_s,
p1_b, p1_s, p1_low_imp_s,
p2_b, p2_s, p2l_low_imp_s, p2h_low_imp_s)
function port_bidir_f(port_value : in std_logic_vector;
low_imp : in std_logic) return std_logic_vector is
variable result_v : std_logic_vector(port_value'range);
begin
for idx in port_value'high downto port_value'low loop
if low_imp = '1' then
result_v(idx) := port_value(idx);
elsif port_value(idx) = '0' then
result_v(idx) := '0';
else
result_v(idx) := 'Z';
end if;
end loop;
return result_v;
end;
begin
-- Test 0 -----------------------------------------------------------------
if t0_dir_s = '1' then
t0_b <= t0_s;
else
t0_b <= 'Z';
end if;
-- Data Bus ---------------------------------------------------------------
if db_dir_s = '1' then
db_b <= db_s;
else
db_b <= (others => 'Z');
end if;
-- Port 1 -----------------------------------------------------------------
p1_b <= port_bidir_f(port_value => p1_s,
low_imp => p1_low_imp_s);
-- Port 2 -----------------------------------------------------------------
p2_b(3 downto 0) <= port_bidir_f(port_value => p2_s(3 downto 0),
low_imp => p2l_low_imp_s);
p2_b(7 downto 4) <= port_bidir_f(port_value => p2_s(7 downto 4),
low_imp => p2h_low_imp_s);
end process bidirs;
--
-----------------------------------------------------------------------------
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.10 2006/06/20 00:47:08 arniml
-- new input xtal_en_i
--
-- Revision 1.9 2005/11/02 23:41:43 arniml
-- properly drive P1 and P2 with low impedance markers
--
-- Revision 1.8 2005/11/01 21:38:31 arniml
-- wire signals for P2 low impedance marker issue
--
-- Revision 1.7 2004/12/03 19:44:36 arniml
-- removed obsolete constant
--
-- Revision 1.6 2004/12/02 22:08:42 arniml
-- introduced generic gate_port_input_g
-- forces masking of P1 and P2 input bus
--
-- Revision 1.5 2004/12/01 23:09:47 arniml
-- intruduced hierarchy t8048_notri where all system functionality
-- except bidirectional ports is handled
--
-- Revision 1.4 2004/10/24 09:10:16 arniml
-- Fix for:
-- P1 constantly in push-pull mode in t8048
--
-- Revision 1.3 2004/05/20 21:58:26 arniml
-- Fix for:
-- External Program Memory ignored when EA = 0
--
-- Revision 1.2 2004/03/29 19:40:14 arniml
-- rename pX_limp to pX_low_imp
--
-- Revision 1.1 2004/03/24 21:32:27 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
gpl-2.0
|
70704b010ccff791fc0ed36e1e69b0c7
| 0.529966 | 3.472872 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_case_statement_GNWMX2GCN2.vhd
| 4 | 837 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_case_statement_GNWMX2GCN2 is
generic ( number_outputs : integer := 2;
hasDefault : natural := 1;
pipeline : natural := 0;
width : integer := 16);
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(15 downto 0);
r0 : out std_logic;
r1 : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_case_statement_GNWMX2GCN2 is
begin
caseproc:process( input )
begin
case input is
when "0000000000000100" =>
r0 <= '1';
r1 <= '0';
when others =>
r0 <= '0';
r1 <= '1';
end case;
end process;
end architecture;
|
mit
|
2871540fb7a26b8206e6d9a42ac65b2d
| 0.653524 | 2.926573 | false | false | false | false |
frznchckn/polarbear
|
hw/cores/uart/tb/uart_tb.vhd
| 1 | 2,661 |
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.math_real.all;
-- use ieee.numeric_std.all;
-- use ieee.std_logic_unsigned.all
library uart_bfm;
use uart_bfm.uart_bfm.all;
-- library uart_rx;
-- use uart_rx.uart_rx;
entity uart_tb is
end uart_tb;
architecture tb of uart_tb is
component uart is
port(
Clk : in std_ulogic;
Rst : in std_ulogic;
BaudRateGen : in std_ulogic_vector(19 downto 0);
NumStopBits : in std_ulogic_vector(1 downto 0);
UseParity : in std_ulogic;
ParityType : in std_ulogic;
-- rx
BitRx : in std_ulogic;
ByteTx : out std_ulogic_vector(7 downto 0);
ByteTxValid : out std_ulogic;
ParErr : out std_ulogic;
StopErr : out std_ulogic;
-- tx
ByteRx : in std_ulogic_vector(7 downto 0);
ByteRxValid : in std_ulogic;
BitTx : out std_ulogic;
TxBusy : out std_ulogic
);
end component;
signal byte : std_ulogic_vector(7 downto 0) := X"A5";
signal uart_tx : std_logic;
signal clk : std_ulogic := '1';
signal rst : std_ulogic := '1';
signal dout : std_ulogic_vector(7 downto 0);
signal doutValid : std_ulogic;
signal uartByteRx : std_ulogic_vector(7 downto 0);
signal uartByteRxValid : std_ulogic;
signal uartBitTx : std_ulogic;
signal uartTxBusy : std_ulogic;
signal test_done : std_ulogic := '0';
begin
uart_0 : uart
port map (
Clk => clk,
Rst => rst,
BaudRateGen => X"00036",
NumStopBits => "01",
UseParity => '1',
ParityType => '1',
BitRx => uart_tx,
-- ByteTx => dout,
-- ByteTxValid => doutValid,
ByteTx => uartByteRx,
ByteTxValid => uartByteRxValid,
ParErr => open,
StopErr => open,
-- tx
ByteRx => uartByteRx,
ByteRxValid => uartByteRxValid,
BitTx => uartBitTx,
TxBusy => uartTxBusy
);
P_CLK : process
begin
clk <= '0';
loop
wait for 5 ns;
clk <= not clk;
exit when test_done = '1';
end loop;
assert test_done = '0'
report "test run completed"
severity note;
-- loop
-- clk <= not clk after 5 ns;
-- exit when test_done = '1';
-- end loop;
wait;
end process P_CLK;
rst <= '0' after 15 ns;
-- clk16 <= not clk16 after 271 ns;
P_STIMULUS : process
begin
wait for 100 ns;
uart_tx_byte("odd", 1, x"A5", uart_tx);
uart_tx_byte("odd", 1, x"FF", uart_tx);
uart_tx_byte("odd", 1, x"00", uart_tx);
uart_tx_byte("odd", 1, x"15", uart_tx);
wait for 150 us;
test_done <= '1';
wait;
end process P_STIMULUS;
end tb;
|
unlicense
|
be164c8f09857a90241b49c986e10b80
| 0.572341 | 3.229369 | false | true | false | false |
Ttl/bf_cpu
|
uart.vhd
| 1 | 7,909 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity uart is
generic (
CLK_FREQ : integer := 32; -- Main frequency (MHz)
SER_FREQ : integer := 9600; -- Baud rate (bps)
PARITY_BIT : boolean := true -- Parity bit enable/disable
);
port (
-- Control
clk : in std_logic; -- Main clock
rst : in std_logic; -- Main reset
-- External Interface
rx : in std_logic; -- RS232 received serial data
tx : out std_logic; -- RS232 transmitted serial data
-- uPC Interface
tx_req : in std_logic; -- Request SEND of data
tx_end : out std_logic; -- Data SENDED
tx_data : in std_logic_vector(7 downto 0); -- Data to transmit
rx_ready : out std_logic; -- Received data ready to uPC read
rx_data : out std_logic_vector(7 downto 0) -- Received data
);
end uart;
architecture Behavioral of uart is
-- Constants
constant UART_IDLE : std_logic := '1';
constant UART_START : std_logic := '0';
constant RST_LVL : std_logic := '1';
-- Types
type state_tx is (idle,data,parity,stop1,stop2); -- Stop1 and Stop2 are inter frame gap signals
type state_rx is (idle,data,parity);
-- RX Signals
signal rx_fsm : state_rx; -- Control of reception
signal rx_clk_en : std_logic; -- Received clock enable
signal rx_rcv_init : std_logic; -- Start of reception
signal rx_par_bit : std_logic; -- Calculated Parity bit
signal rx_data_deb : std_logic; -- Debounce RX data
signal rx_data_tmp : std_logic_vector(6 downto 0); -- Serial to parallel converter
signal rx_data_cnt : std_logic_vector(2 downto 0); -- Count received bits
-- TX Signals
signal tx_fsm : state_tx; -- Control of transmission
signal tx_init : std_logic; -- Resets tx_clk when tx_req is asserted
signal tx_start : std_logic; -- TX start signal for FSM
signal tx_clk_en : std_logic; -- Transmited clock enable
signal tx_par_bit : std_logic; -- Calculated Parity bit
signal tx_data_tmp : std_logic_vector(7 downto 0); -- Parallel to serial converter
signal tx_data_cnt : std_logic_vector(2 downto 0); -- Count transmited bits
-- Return a counter value that minimizes the error between real and wanted baud rate.
function counts(clk_freq, ser_freq : integer)
return integer is
variable tmp : integer := (clk_freq*1_000_000)/ser_freq;
begin
if abs(Real(clk_freq*1_000_000)/Real(tmp)-Real(ser_freq)) < abs(Real(clk_freq*1_000_000)/Real(tmp-1)-Real(ser_freq)) then
return tmp;
else
return tmp - 1;
end if;
end counts;
begin
tx_start_detect:process(clk)
variable tx_req_old, tx_init_old : std_logic;
begin
if clk'event and clk = '1' then
-- Falling edge detection
if tx_init_old = '0' and tx_req = '1' and tx_fsm = idle then
tx_init <= '1';
else
tx_init <= '0';
tx_start <= tx_req_old;
end if;
-- Default assignments
tx_req_old := tx_req;
tx_init_old := tx_init;
-- Reset condition
if rst = RST_LVL then
tx_req_old := '0';
tx_start <= '0';
tx_init <= '0';
end if;
end if;
end process;
tx_clk_gen:process(clk)
variable counter : integer range 0 to conv_integer(counts(CLK_FREQ, SER_FREQ));
begin
if clk'event and clk = '1' then
-- Normal Operation
if counter = counts(CLK_FREQ, SER_FREQ) or tx_init = '1' then
tx_clk_en <= '1';
counter := 0;
else
tx_clk_en <= '0';
counter := counter + 1;
end if;
-- Reset condition
if rst = RST_LVL then
tx_clk_en <= '0';
counter := 0;
end if;
end if;
end process;
tx_proc:process(clk)
variable data_cnt : std_logic_vector(2 downto 0);
begin
if clk'event and clk = '1' then
tx_end <= '0';
if tx_clk_en = '1' then
-- Default values
tx <= UART_IDLE;
-- FSM description
case tx_fsm is
-- Wait to transfer data
when idle =>
-- Send Init Bit
if tx_start = '1' then
tx <= UART_START;
tx_data_tmp <= tx_data;
tx_fsm <= data;
tx_data_cnt <= (others=>'1');
tx_par_bit <= '0';
end if;
-- Data receive
when data =>
tx <= tx_data_tmp(0);
tx_par_bit <= tx_par_bit xor tx_data_tmp(0);
if tx_data_cnt = 0 then
if PARITY_BIT then
tx_fsm <= parity;
else
tx_fsm <= stop1;
end if;
tx_data_cnt <= (others=>'1');
else
tx_data_tmp <= '0' & tx_data_tmp(7 downto 1);
tx_data_cnt <= tx_data_cnt - 1;
end if;
when parity =>
tx <= tx_par_bit;
tx_fsm <= stop1;
-- End of communication
when stop1 =>
-- Send Stop Bit
tx <= UART_IDLE;
tx_fsm <= stop2;
when stop2 =>
-- Send Stop Bit
tx_end <= '1';
tx <= UART_IDLE;
tx_fsm <= idle;
-- Invalid States
when others => null;
end case;
-- Reset condition
if rst = RST_LVL then
tx_fsm <= idle;
tx_par_bit <= '0';
tx_data_tmp <= (others=>'0');
tx_data_cnt <= (others=>'0');
end if;
end if;
end if;
end process;
rx_debounceer:process(clk)
variable deb_buf : std_logic_vector(3 downto 0);
begin
if clk'event and clk = '1' then
-- Debounce logic
if deb_buf = "0000" then
rx_data_deb <= '0';
elsif deb_buf = "1111" then
rx_data_deb <= '1';
end if;
-- Data storage to debounce
deb_buf := deb_buf(2 downto 0) & rx;
end if;
end process;
rx_start_detect:process(clk)
variable rx_data_old : std_logic;
begin
if clk'event and clk = '1' then
-- Falling edge detection
if rx_data_old = '1' and rx_data_deb = '0' and rx_fsm = idle then
rx_rcv_init <= '1';
else
rx_rcv_init <= '0';
end if;
-- Default assignments
rx_data_old := rx_data_deb;
-- Reset condition
if rst = RST_LVL then
rx_data_old := '0';
rx_rcv_init <= '0';
end if;
end if;
end process;
rx_clk_gen:process(clk)
variable counter : integer range 0 to conv_integer(counts(CLK_FREQ, SER_FREQ));
begin
if clk'event and clk = '1' then
-- Normal Operation
if counter = counts(CLK_FREQ, SER_FREQ) or rx_rcv_init = '1' then
rx_clk_en <= '1';
counter := 0;
else
rx_clk_en <= '0';
counter := counter + 1;
end if;
-- Reset condition
if rst = RST_LVL then
rx_clk_en <= '0';
counter := 0;
end if;
end if;
end process;
rx_proc:process(clk)
begin
if clk'event and clk = '1' then
-- Default values
rx_ready <= '0';
-- Enable on UART rate
if rx_clk_en = '1' then
-- FSM description
case rx_fsm is
-- Wait to transfer data
when idle =>
if rx_data_deb = UART_START then
rx_fsm <= data;
end if;
rx_par_bit <= '0';
rx_data_cnt <= (others=>'0');
-- Data receive
when data =>
-- Check data to generate parity
if PARITY_BIT then
rx_par_bit <= rx_par_bit xor rx;
end if;
if rx_data_cnt = 7 then
-- Data path
rx_data(7) <= rx;
for i in 0 to 6 loop
rx_data(i) <= rx_data_tmp(6-i);
end loop;
-- With parity verification
if PARITY_BIT then
rx_fsm <= parity;
-- Without parity verification
else
rx_ready <= '1';
rx_fsm <= idle;
end if;
else
rx_data_tmp <= rx_data_tmp(5 downto 0) & rx;
rx_data_cnt <= rx_data_cnt + 1;
end if;
when parity =>
-- Check received parity
rx_fsm <= idle;
if rx_par_bit = rx then
rx_ready <= '1';
end if;
when others => null;
end case;
-- Reset condition
if rst = RST_LVL then
rx_fsm <= idle;
rx_ready <= '0';
rx_data <= (others=>'0');
rx_data_tmp <= (others=>'0');
rx_data_cnt <= (others=>'0');
end if;
end if;
end if;
end process;
end Behavioral;
|
lgpl-3.0
|
d7d4e4a49cc4d031608d62100ec2776b
| 0.571122 | 2.671959 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_counter_GNKAA2ZBZG.vhd
| 4 | 1,632 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_counter_GNKAA2ZBZG is
generic ( use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "1";
use_sload : string := "false";
use_sclr : string := "true";
use_cout : string := "false";
modulus : integer := 8388608;
use_cnt_ena : string := "true";
width : natural := 24;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0");
port(
aclr : in std_logic;
aload : in std_logic;
aset : in std_logic;
cin : in std_logic;
clock : in std_logic;
cnt_ena : in std_logic;
cout : out std_logic;
data : in std_logic_vector((width)-1 downto 0);
direction : in std_logic;
ena : in std_logic;
q : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic;
sload : in std_logic;
sset : in std_logic;
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_counter_GNKAA2ZBZG is
Begin
-- DSP Builder Block - Simulink Block "Counter"
Counteri : lpm_counter Generic map (
LPM_WIDTH => 24,
LPM_DIRECTION => "UP",
LPM_MODULUS => 8388608,
LPM_AVALUE => "0",
LPM_SVALUE => "1",
LPM_TYPE => "LPM_COUNTER"
)
port map (
clock => clock,
cnt_en => cnt_ena,
aclr => aclr,
sclr => sclr,
q => q);
end architecture;
|
mit
|
daf3c2ee560b1d0dbf3077bd5974318c
| 0.609069 | 2.833333 | false | false | false | false |
Bourgeoisie/ECE368-RISC16
|
368RISC/Modules/Reg.vhd
| 1 | 752 |
---- Engineer: Brett Bourgeois
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.UMDRISC_pkg.ALL;
entity Reg is
generic (regSize : integer:= BITREG_16);
port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR(regSize-1 downto 0);
DataOut : out STD_LOGIC_VECTOR(regSize-1 downto 0);
Full_Instr : out STD_LOGIC_VECTOR(regSize-1 downto 0)
);
end Reg;
architecture Behavioral of Reg is
begin
Process(CLK, RST)
begin
if(RST = '1') then
DataOut <= (others =>'0');
elsif (CLK'event and CLK = '0') then -- trigger on falling edge
DataOut <= DataIn;
Full_Instr <=DataIn;
end if;
end process;
end Behavioral;
|
mit
|
8e836668cb6c13f9ffb4fd66dc8cf40f
| 0.655585 | 3.056911 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_SBitLogical.vhd
| 20 | 3,567 |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SBitLogical is
generic (
lpm_width : positive := 8 ;
lop : LogicalOperator := AltAND
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic
);
end alt_dspbuilder_SBitLogical;
architecture SBitLogical_SYNTH of alt_dspbuilder_SBitLogical is
signal worand : std_logic_vector(lpm_width-1 downto 0);
signal ndataa : std_logic_vector(lpm_width-1 downto 0);
signal result_int : std_logic;
begin
u0: alt_dspbuilder_sAltrBitPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion)
port map (d => result_int, r => result);
------------------AND--------------------------------
go1p:if lop = AltAND generate
gi:for i in 0 to lpm_width-1 generate
worand(i) <= '1';
end generate gi;
result_int <= '1' when (worand=dataa) else '0';
end generate;
------------------OR--------------------------------
go2p:if lop = AltOR generate
gi:for i in 0 to lpm_width-1 generate
worand(i) <= '1';
ndataa(i) <= not (dataa(i));
end generate gi;
result_int <= '0' when (ndataa=worand) else '1';
end generate;
------------------XOR--------------------------------
go3p:if lop = AltXOR generate
gif:if (lpm_width>2) generate
process(dataa)
variable interes : std_logic ;
begin
interes := dataa(0) xor dataa(1);
for i in 2 to lpm_width-1 loop
interes := dataa(i) xor interes;
end loop;
result_int <= interes;
end process;
end generate;
gif2:if (lpm_width<3) generate
result_int <= dataa(0) xor dataa(1);
end generate;
end generate;
------------------NOR--------------------------------
go4p:if lop = AltNOR generate
gi:for i in 0 to lpm_width-1 generate
worand(i) <= '1';
ndataa(i) <= not (dataa(i));
end generate gi;
result_int <= '1' when (ndataa=worand) else '0';
end generate;
------------------NAND--------------------------------
go5p:if lop = AltNAND generate
gi:for i in 0 to lpm_width-1 generate
worand(i) <= '1';
end generate gi;
result_int <= '0' when (worand=dataa) else '1';
end generate;
------------------NOT (Single Bit only)---------------
go6p:if lop = AltNOT generate
result_int <= not (dataa(0));
end generate;
end SBitLogical_SYNTH;
|
mit
|
11f8ab2be67e3ae1f0eb2c84be918d92
| 0.601906 | 3.62132 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/v_tc_v6_1/51f55007/hdl/v_tc_v6_1_vh_rfs.vhd
| 1 | 449,533 |
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`protect end_protected
|
gpl-2.0
|
957e1a06932f9279a76b0b443e728b55
| 0.955576 | 1.828634 | false | false | false | false |
nulldozer/purisc
|
Compute_Group/MAGIC_clocked/RAM_6.vhd
| 1 | 10,399 |
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM_6.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY RAM_6 IS
PORT
(
aclr : IN STD_LOGIC := '0';
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END RAM_6;
ARCHITECTURE SYN OF ram_6 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
init_file => "RAM_6.mif",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "CLEAR0",
outdata_aclr_b => "CLEAR0",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "OLD_DATA",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 10,
widthad_b => 10,
width_a => 32,
width_b => 32,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
aclr0 => aclr,
address_a => address_a,
address_b => address_b,
clock0 => clock,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "1"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "RAM_6.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INIT_FILE STRING "RAM_6.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
-- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
-- Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
-- Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
-- Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
-- Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_6.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_6.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_6.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_6.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_6_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
86df0026e9204a905b9226dd1377f265
| 0.666314 | 3.290823 | false | false | false | false |
ricardo-jasinski/vhdl-bit-matrix-lib
|
packages/bit_matrix_pkg.vhd
| 1 | 14,471 |
use std.textio.all;
-- Types and operations for working with boolean matrices. In a boolean matrix,
-- elements are of type bit, and operations are defined over the finite field
-- GF(2).
package bit_matrix_pkg is
type bit_matrix is array (natural range <>, natural range <>) of bit;
procedure inspect(matrix: bit_matrix; tag: string := "");
function to_bit_matrix(input_matrix: bit_matrix) return bit_matrix;
function bit_matrix_from_value(rows_count, cols_count: integer; value: bit) return bit_matrix;
function zeroes(rows_count, cols_count: integer) return bit_matrix;
function ones(rows_count, cols_count: integer) return bit_matrix;
function null_bit_matrix(rows_count, cols_count: integer) return bit_matrix;
function identity_bit_matrix(size: integer) return bit_matrix;
function matrix_column(m: bit_matrix; c: integer) return bit_vector;
function matrix_row(m: bit_matrix; r: integer) return bit_vector;
function exchange_rows(m: bit_matrix; r1, r2: integer) return bit_matrix;
function sub_matrix(m: bit_matrix; r1, c1, r2, c2: integer) return bit_matrix;
function transpose(m: bit_matrix) return bit_matrix;
function shift_left_matrix(matrix: bit_matrix; new_column: bit_vector) return bit_matrix;
function shift_left(matrix: bit_matrix) return bit_matrix;
function shift_left(matrix: bit_matrix; shift_amount: natural) return bit_matrix;
function replace_matrix_column(input_matrix: bit_matrix; new_column: bit_vector; column_index: integer) return bit_matrix;
function replace_element(row, col: integer; value: bit; matrix: bit_matrix) return bit_matrix;
function height(matrix: bit_matrix) return integer;
function width(matrix: bit_matrix) return integer;
function columns_within_range(m: bit_matrix; c1, c2: integer) return bit_matrix;
function leftmost_columns(matrix: bit_matrix; columns_count: integer) return bit_matrix;
function rightmost_columns(matrix: bit_matrix; columns_count: integer) return bit_matrix;
function "*"(vector: bit_vector; matrix: bit_matrix) return bit_vector;
function "*"(m1: bit_matrix; m2: bit_matrix) return bit_matrix;
-- maximum string lenght for a label/matrix name/identifier
constant LABEL_SIZE_MAX: integer := 80;
end package;
package body bit_matrix_pkg is
function exchange_rows(m: bit_matrix; r1, r2: integer) return bit_matrix is
constant ROWS_COUNT: integer := m'length(1);
constant COLS_COUNT: integer := m'length(2);
variable retMat: bit_matrix(1 to ROWS_COUNT, 1 to COLS_COUNT);
begin
retMat := m;
for i in 1 to ROWS_COUNT loop
for j in 1 to COLS_COUNT loop
if i = r1 then
retMat(i, j) := m(r2, j);
elsif i = r2 then
retMat(i, j) := m(r1, j);
end if;
end loop;
end loop;
return retMat;
end function exchange_rows;
-- extrai uma coluna de uma matriz, retornando-a na forma de um vetor
function matrix_column(m: bit_matrix; c: integer) return bit_vector is
variable retVect: bit_vector(m'range);
begin
for i in retVect'range loop
retVect(i) := m(i, c);
end loop;
return retVect;
end function matrix_column;
-- extrai uma linha de uma matriz, retornando-a na forma de um vetor
function matrix_row(m: bit_matrix; r: integer) return bit_vector is
variable retVect: bit_vector(m'range(2));
begin
for j in retVect'range loop
retVect(j) := m(r, j);
end loop;
return retVect;
end function matrix_row;
function bit_matrix_from_value(rows_count, cols_count: integer; value: bit) return bit_matrix is
variable matrix: bit_matrix(1 to rows_count, 1 to cols_count);
begin
for i in 1 to rows_count loop
for j in 1 to cols_count loop
matrix(i, j) := value;
end loop;
end loop;
return matrix;
end function;
function zeroes(rows_count, cols_count: integer) return bit_matrix is
begin
return bit_matrix_from_value(rows_count, cols_count, '0');
end function;
function ones(rows_count, cols_count: integer) return bit_matrix is
begin
return bit_matrix_from_value(rows_count, cols_count, '1');
end function;
-- retorna uma matriz com as dimensões especificadas e todos
-- os elementos iguais a '0'
function null_bit_matrix(rows_count, cols_count: integer) return bit_matrix is
begin
return zeroes(rows_count, cols_count);
end function;
-- Gera uma matrix identidade.
function identity_bit_matrix(size: integer) return bit_matrix is
variable matrix: bit_matrix(1 to size, 1 to size);
begin
for i in 1 to size loop
for j in 1 to size loop
if i = j then
matrix(i, j) := '1';
else
matrix(i, j) := '0';
end if;
end loop;
end loop;
return matrix;
end function;
-- retorna uma sub-matriz da matriz especificada
function sub_matrix(m: bit_matrix; r1, c1, r2, c2: integer) return bit_matrix is
constant rowsCount: integer := r2 - r1 + 1;
constant colsCount: integer := c2 - c1 + 1;
variable retMat: bit_matrix(1 to rowsCount, 1 to colsCount);
begin
for i in 1 to rowsCount loop
for j in 1 to colsCount loop
retMat(i, j) := m(r1 + i - 1, c1 + j - 1);
end loop;
end loop;
return retMat;
end function sub_matrix;
-- retorna uma sub-matriz da matriz especificada
function columns_within_range(m: bit_matrix; c1, c2: integer) return bit_matrix is
constant rowsCount: integer := m'length(1);
constant colsCount: integer := c2 - c1 + 1;
variable retMat: bit_matrix(1 to rowsCount, 1 to colsCount);
begin
for i in 1 to rowsCount loop
for j in c1 to c2 loop
retMat(i, j - c1 + 1) := m(i, j);
end loop;
end loop;
return retMat;
end function columns_within_range;
function leftmost_columns(matrix: bit_matrix; columns_count: integer) return bit_matrix is
begin
return columns_within_range(matrix, 1, columns_count);
end function;
function rightmost_columns(matrix: bit_matrix; columns_count: integer) return bit_matrix is
constant colsCount: integer := matrix'length(2);
begin
return columns_within_range(matrix, colsCount - columns_count + 1, colsCount);
end function;
function transpose(m: bit_matrix) return bit_matrix is
variable retMat: bit_matrix(m'range(2), m'range(1));
begin
for i in m'range(1) loop
for j in m'range(2) loop
retMat(j, i) := m(i, j);
end loop;
end loop;
return retMat;
end;
function to_bit_matrix(input_matrix: bit_matrix) return bit_matrix is
variable output_matrix: bit_matrix(1 to height(input_matrix), 1 to width(input_matrix));
variable x_offset: integer := 1 - input_matrix'left(1);
variable y_offset: integer := 1 - input_matrix'left(2);
begin
for i in output_matrix'range(1) loop
for j in output_matrix'range(2) loop
output_matrix(i, j) := input_matrix(i - y_offset, j - x_offset);
end loop;
end loop;
return output_matrix;
end;
function replace_element(row, col: integer; value: bit; matrix: bit_matrix) return bit_matrix is
variable output: bit_matrix(matrix'range(1), matrix'range(2));
begin
for i in matrix'range(1) loop
for j in matrix'range(2) loop
if i = row and j = col then
output(i, j) := value;
else
output(i, j) := matrix(i, j);
end if;
end loop;
end loop;
return output;
end;
function replace_matrix_column(input_matrix: bit_matrix; new_column: bit_vector; column_index: integer) return bit_matrix is
variable output: bit_matrix(input_matrix'range(1), input_matrix'range(2));
begin
for i in input_matrix'range(1) loop
for j in input_matrix'range(2) loop
if j = column_index then
output(i, j) := new_column(i);
else
output(i, j) := input_matrix(i, j);
end if;
end loop;
end loop;
return output;
end;
function "*"(vector: bit_vector; matrix: bit_matrix) return bit_vector is
variable result: bit_vector(matrix'range(2));
begin
for j in result'range loop
--result(j) := elements_xor(
result(j) := xor(
-- AND bit-a-bit entre o vetor 'v' e a coluna 'j' da matriz
vector and matrix_column(matrix, j)
);
end loop;
return result;
end function;
--------------------------------------------------------------------------------
---[ http://www.zweigmedia.com/RealWorld/tutorialsf1/frames3_2.html ]-----------
--------------------------------------------------------------------------------
-- The Product of Two Matrices: General Case
-- In general, we can take the product AB only if the number of columns of A
-- equals the number of rows of B (so that we can multiply the rows of A by the
-- columns of B as above).
--
-- Note: The product AB has as many rows as A and as many columns as B.
--
-- The product AB is then obtained as follows:
--
-- to obtain the 1,1 entry of AB, multiply Row 1 of A by Column 1 of B.
-- to obtain the 1,2 entry of AB, multiply Row 1 of A by Column 2 of B.
-- to obtain the 1,3 entry of AB, multiply Row 1 of A by Column 3 of B.
-- . . .
-- to obtain the 2,1 entry of AB, multiply Row 2 of A by Column 1 of B.
-- to obtain the 2,2 entry of AB, multiply Row 2 of A by Column 1 of B.
-- and so on. In general,
-- to obtain the i,j entry of AB, multiply Row i of A by Column j of B.
--------------------------------------------------------------------------------
-- multiplicação de duas matrizes binárias
function "*"(m1: bit_matrix; m2: bit_matrix) return bit_matrix is
variable result: bit_matrix(m1'range(1), m2'range(2));
variable m1_row: bit_vector(m1'range(2));
variable m2_col: bit_vector(m2'range(1));
begin
-- we can take the product AB only if the number of
-- columns of A equals the number of rows of B
assert width(m1) = height(m2);
for i in result'range(1) loop
m1_row := matrix_row(m1, i);
for j in result'range(2) loop
m2_col := matrix_column(m2, j);
--result(i, j) := elements_xor(
result(i, j) := xor(
-- AND bit-a-bit entre o vetor 'v' e a coluna 'j' da matriz
m1_row and m2_col
);
end loop;
end loop;
return result;
end function;
function shift_left_matrix(matrix: bit_matrix; new_column: bit_vector) return bit_matrix is
variable final: bit_matrix(matrix'range(1), matrix'range(2));
begin
for i in matrix'range(1) loop
for j in matrix'range(2) loop
if j < width(matrix) then
final(i, j) := matrix(i, j + 1);
else
final(i, j) := new_column(i);
end if;
end loop;
end loop;
return final;
end;
function shift_left(matrix: bit_matrix) return bit_matrix is
variable shifted_matrix: bit_matrix(matrix'range(1), matrix'range(2));
begin
-- for each matrix row
for i in matrix'range(1) loop
-- for each matrix column
for j in matrix'range(2) loop
-- is this the last column?
if j < width(matrix) then
shifted_matrix(i, j) := matrix(i, j + 1);
else
shifted_matrix(i, j) := '0';
end if; -- is this the last column?
end loop; -- for each matrix column
end loop; -- for each matrix row
return shifted_matrix;
end; -- function shift_left
function shift_left(matrix: bit_matrix; shift_amount: natural) return bit_matrix is
variable shifted_matrix: matrix'subtype;
constant NONZERO_COLUMNS_COUNT: natural := width(matrix) - shift_amount + 1;
begin
-- for each matrix row
for i in matrix'range(1) loop
-- for each matrix column
for j in matrix'range(2) loop
-- copy element or fill it with zero
if j < NONZERO_COLUMNS_COUNT then
shifted_matrix(i, j) := matrix(i, j + shift_amount);
else -- j >= NONZERO_COLUMNS_COUNT
shifted_matrix(i, j) := '0';
end if; -- copy element or fill it with zero
end loop; -- for each matrix column
end loop; -- for each matrix row
return shifted_matrix;
end; -- function shift_left
function height(matrix: bit_matrix) return integer is
begin
return matrix'length(1);
end function;
function width(matrix: bit_matrix) return integer is
begin
return matrix'length(2);
end function;
procedure inspect(matrix: bit_matrix; tag: string := "") is
variable row: line(matrix'range(2));
variable tag_text: line;
begin
if tag /= "" then
write(tag_text, tag & " ");
writeline(output, tag_text);
end if;
for i in matrix'range(1) loop
write(row, matrix_row(matrix, i));
writeline(output, row);
end loop;
end procedure;
end package body;
|
unlicense
|
858d80b64e96c1a7f33e5443a7a978de
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sukinull/hls_stream
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| 1 | 465,310 |
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`protect end_protected
|
gpl-2.0
|
16b7ebe933c6095a6b8f8445e2a7bd08
| 0.955853 | 1.826435 | false | false | false | false |
ricardo-jasinski/vhdl-bit-matrix-lib
|
packages/bit_vector_pkg.vhd
| 1 | 4,743 |
package bit_vector_pkg is
type integer_vector is array (natural range <>) of integer;
-- retorna um vetor com a largura especificada e todos
-- os elementos iguais a '0'
function null_bit_vector(w: integer) return bit_vector;
function zeroes(w: integer) return bit_vector;
function ones(w: integer) return bit_vector;
function unit_vector(size, nonzero_pos: integer) return bit_vector;
function weight(v: bit_vector) return integer;
-- operação AND entre os elementos de um vetor, retornando um bit
function elements_and(v: bit_vector) return bit;
-- operação OR entre os elementos de um vetor, retornando um bit
function elements_or(v: bit_vector) return bit;
-- operação XOR entre os elementos de um vetor, retornando um bit
function elements_xor(v: bit_vector) return bit;
-- cria um novo vetor, a partir de um subconjunto de elementos de um dado vetor
function VectorFromVectorElements(v: bit_vector; e: integer_vector) return bit_vector;
-- retorna um número inteiro a partir de um vetor de bits;
-- elemento mais à direita (menor índice) é o menos significativo
function integer_from_bit_vector(v: bit_vector) return integer;
-- retorna um vetor de bits a partir de um número inteiro;
-- elemento mais à direita (menor índice) é o menos significativo
function bit_vector_from_integer(i: integer; w: integer) return bit_vector;
end package bit_vector_pkg;
package body bit_vector_pkg is
-- retorna um vetor com a largura especificada e todos
-- os elementos iguais a '0'
function null_bit_vector(w: integer) return bit_vector is begin
return zeroes(w);
end function null_bit_vector;
function zeroes(w: integer) return bit_vector is
variable retVect: bit_vector(1 to w) := (others => '0');
begin
return retVect;
end function;
function ones(w: integer) return bit_vector is
variable retVect: bit_vector(1 to w) := (others => '1');
begin
return retVect;
end function;
function unit_vector(size, nonzero_pos: integer) return bit_vector is
variable result: bit_vector(1 to size) := (others => '0');
begin
result(nonzero_pos) := '1';
return result;
end function;
-- cria um novo vetor, a partir de um subconjunto de elementos de um dado vetor
function VectorFromVectorElements(v: bit_vector; e: integer_vector) return bit_vector is
variable retVect: bit_vector(e'range);
begin
for i in e'range loop
retVect(i) := v(e(i));
end loop;
return retVect;
end function VectorFromVectorElements;
function weight(v: bit_vector) return integer is
variable result: integer := 0;
begin
for i in v'range loop
if v(i) = '1' then
result := result + 1;
end if;
end loop;
return result;
end function;
-- operação XOR entre os elementos de um vetor, retornando um bit
function elements_xor(v: bit_vector) return bit is
variable result: bit;
begin
result := '0';
for i in v'range loop
result := result xor v(i);
end loop;
return result;
end function;
-- operação AND entre os elementos de um vetor, retornando um bit
function elements_and(v: bit_vector) return bit is
variable result: bit;
begin
result := '1';
for i in v'range loop
result := result and v(i);
end loop;
return result;
end function;
-- operação OR entre os elementos de um vetor, retornando um bit
function elements_or(v: bit_vector) return bit is
variable result: bit;
begin
result := '0';
for i in v'range loop
result := result or v(i);
end loop;
return result;
end function;
-- retorna um número inteiro a partir de um vetor de bits;
-- elemento mais à direita (menor índice) é o menos significativo
function integer_from_bit_vector(v: bit_vector) return integer is
variable retVal: integer range 0 to (2 ** v'length) - 1;
begin
retVal := 0;
for i in v'range loop
if (v(i) = '1') then
--retVal := retVal + 2 ** (v'high-i+1);
retVal := retVal + 2 ** (v'high-i);
end if;
end loop;
return retVal;
end function;
-- retorna um vetor de bits a partir de um número inteiro;
-- elemento mais à direita (menor índice) é o menos significativo
function bit_vector_from_integer(i: integer; w: integer) return bit_vector is
variable retVect: bit_vector(1 to w) := (others => '0');
variable temp: integer range 0 to 2**w-1 := 0;
begin
temp := i;
for j in retVect'high-1 downto retVect'low-1 loop
if (temp >= 2**j) then
retVect(retVect'high-j) := '1';
temp := temp - 2**j;
else
retVect(retVect'high-j) := '0';
end if;
end loop;
return retVect;
end function;
end package body;
|
unlicense
|
32afe6e9e5577511cd93d155f56e14c5
| 0.672781 | 3.693925 | false | false | false | false |
nulldozer/purisc
|
Compute_Group/MAGIC_clocked/create_opcode.vhd
| 2 | 17,365 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity create_opcode is
PORT (
COL_A : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_B : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_C : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_D : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_E : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_W : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
W_EN : IN STD_LOGIC;
--OUTPUTS OF READS
OPCODE_0 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_1 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_2 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_3 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_4 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_5 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_6 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_7 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end;
architecture gen of create_opcode is
begin
OPCODE_0(5) <= not(COL_A(2)) and not(COL_A(1)) and not(COL_A(0));
OPCODE_1(5) <= not(COL_A(2)) and not(COL_A(1)) and (COL_A(0));
OPCODE_2(5) <= not(COL_A(2)) and (COL_A(1)) and not(COL_A(0));
OPCODE_3(5) <= not(COL_A(2)) and (COL_A(1)) and (COL_A(0));
OPCODE_4(5) <= (COL_A(2)) and not(COL_A(1)) and not(COL_A(0));
OPCODE_5(5) <= (COL_A(2)) and not(COL_A(1)) and (COL_A(0));
OPCODE_6(5) <= (COL_A(2)) and (COL_A(1)) and not(COL_A(0));
OPCODE_7(5) <= (COL_A(2)) and (COL_A(1)) and (COL_A(0));
OPCODE_0(4) <= not(COL_B(2)) and not(COL_B(1)) and not(COL_B(0));
OPCODE_1(4) <= not(COL_B(2)) and not(COL_B(1)) and (COL_B(0));
OPCODE_2(4) <= not(COL_B(2)) and (COL_B(1)) and not(COL_B(0));
OPCODE_3(4) <= not(COL_B(2)) and (COL_B(1)) and (COL_B(0));
OPCODE_4(4) <= (COL_B(2)) and not(COL_B(1)) and not(COL_B(0));
OPCODE_5(4) <= (COL_B(2)) and not(COL_B(1)) and (COL_B(0));
OPCODE_6(4) <= (COL_B(2)) and (COL_B(1)) and not(COL_B(0));
OPCODE_7(4) <= (COL_B(2)) and (COL_B(1)) and (COL_B(0));
OPCODE_0(3) <= not(COL_C(2)) and not(COL_C(1)) and not(COL_C(0));
OPCODE_1(3) <= not(COL_C(2)) and not(COL_C(1)) and (COL_C(0));
OPCODE_2(3) <= not(COL_C(2)) and (COL_C(1)) and not(COL_C(0));
OPCODE_3(3) <= not(COL_C(2)) and (COL_C(1)) and (COL_C(0));
OPCODE_4(3) <= (COL_C(2)) and not(COL_C(1)) and not(COL_C(0));
OPCODE_5(3) <= (COL_C(2)) and not(COL_C(1)) and (COL_C(0));
OPCODE_6(3) <= (COL_C(2)) and (COL_C(1)) and not(COL_C(0));
OPCODE_7(3) <= (COL_C(2)) and (COL_C(1)) and (COL_C(0));
OPCODE_0(2) <= not(COL_D(2)) and not(COL_D(1)) and not(COL_D(0));
OPCODE_1(2) <= not(COL_D(2)) and not(COL_D(1)) and (COL_D(0));
OPCODE_2(2) <= not(COL_D(2)) and (COL_D(1)) and not(COL_D(0));
OPCODE_3(2) <= not(COL_D(2)) and (COL_D(1)) and (COL_D(0));
OPCODE_4(2) <= (COL_D(2)) and not(COL_D(1)) and not(COL_D(0));
OPCODE_5(2) <= (COL_D(2)) and not(COL_D(1)) and (COL_D(0));
OPCODE_6(2) <= (COL_D(2)) and (COL_D(1)) and not(COL_D(0));
OPCODE_7(2) <= (COL_D(2)) and (COL_D(1)) and (COL_D(0));
OPCODE_0(1) <= not(COL_E(2)) and not(COL_E(1)) and not(COL_E(0));
OPCODE_1(1) <= not(COL_E(2)) and not(COL_E(1)) and (COL_E(0));
OPCODE_2(1) <= not(COL_E(2)) and (COL_E(1)) and not(COL_E(0));
OPCODE_3(1) <= not(COL_E(2)) and (COL_E(1)) and (COL_E(0));
OPCODE_4(1) <= (COL_E(2)) and not(COL_E(1)) and not(COL_E(0));
OPCODE_5(1) <= (COL_E(2)) and not(COL_E(1)) and (COL_E(0));
OPCODE_6(1) <= (COL_E(2)) and (COL_E(1)) and not(COL_E(0));
OPCODE_7(1) <= (COL_E(2)) and (COL_E(1)) and (COL_E(0));
OPCODE_0(0) <= (not(COL_W(2)) and not(COL_W(1)) and not(COL_W(0))) and W_EN;
OPCODE_1(0) <= (not(COL_W(2)) and not(COL_W(1)) and (COL_W(0))) and W_EN;
OPCODE_2(0) <= (not(COL_W(2)) and (COL_W(1)) and not(COL_W(0))) and W_EN;
OPCODE_3(0) <= (not(COL_W(2)) and (COL_W(1)) and (COL_W(0))) and W_EN;
OPCODE_4(0) <= ((COL_W(2)) and not(COL_W(1)) and not(COL_W(0))) and W_EN;
OPCODE_5(0) <= ((COL_W(2)) and not(COL_W(1)) and (COL_W(0))) and W_EN;
OPCODE_6(0) <= ((COL_W(2)) and (COL_W(1)) and not(COL_W(0))) and W_EN;
OPCODE_7(0) <= ((COL_W(2)) and (COL_W(1)) and (COL_W(0))) and W_EN;
-- process (COL_A, COL_B, COL_C, COL_D, COL_E, COL_W, W_EN) begin
-- --assigning address A to column
-- if (COL_A = 0) then
-- OPCODE_0(5) <= '1';
-- OPCODE_1(5) <= '0';
-- OPCODE_2(5) <= '0';
-- OPCODE_3(5) <= '0';
-- OPCODE_4(5) <= '0';
-- OPCODE_5(5) <= '0';
-- OPCODE_6(5) <= '0';
-- OPCODE_7(5) <= '0';
-- elsif (COL_A = 1) then
-- OPCODE_0(5) <= '0';
-- OPCODE_1(5) <= '1';
-- OPCODE_2(5) <= '0';
-- OPCODE_3(5) <= '0';
-- OPCODE_4(5) <= '0';
-- OPCODE_5(5) <= '0';
-- OPCODE_6(5) <= '0';
-- OPCODE_7(5) <= '0';
-- elsif (COL_A = 2) then
-- OPCODE_0(5) <= '0';
-- OPCODE_1(5) <= '0';
-- OPCODE_2(5) <= '1';
-- OPCODE_3(5) <= '0';
-- OPCODE_4(5) <= '0';
-- OPCODE_5(5) <= '0';
-- OPCODE_6(5) <= '0';
-- OPCODE_7(5) <= '0';
-- elsif (COL_A = 3) then
-- OPCODE_0(5) <= '0';
-- OPCODE_1(5) <= '0';
-- OPCODE_2(5) <= '0';
-- OPCODE_3(5) <= '1';
-- OPCODE_4(5) <= '0';
-- OPCODE_5(5) <= '0';
-- OPCODE_6(5) <= '0';
-- OPCODE_7(5) <= '0';
-- elsif (COL_A = 4) then
-- OPCODE_0(5) <= '0';
-- OPCODE_1(5) <= '0';
-- OPCODE_2(5) <= '0';
-- OPCODE_3(5) <= '0';
-- OPCODE_4(5) <= '1';
-- OPCODE_5(5) <= '0';
-- OPCODE_6(5) <= '0';
-- OPCODE_7(5) <= '0';
-- elsif (COL_A = 5) then
-- OPCODE_0(5) <= '0';
-- OPCODE_1(5) <= '0';
-- OPCODE_2(5) <= '0';
-- OPCODE_3(5) <= '0';
-- OPCODE_4(5) <= '0';
-- OPCODE_5(5) <= '1';
-- OPCODE_6(5) <= '0';
-- OPCODE_7(5) <= '0';
-- elsif (COL_A = 6) then
-- OPCODE_0(5) <= '0';
-- OPCODE_1(5) <= '0';
-- OPCODE_2(5) <= '0';
-- OPCODE_3(5) <= '0';
-- OPCODE_4(5) <= '0';
-- OPCODE_5(5) <= '0';
-- OPCODE_6(5) <= '1';
-- OPCODE_7(5) <= '0';
-- elsif (COL_A = 7) then
-- OPCODE_0(5) <= '0';
-- OPCODE_1(5) <= '0';
-- OPCODE_2(5) <= '0';
-- OPCODE_3(5) <= '0';
-- OPCODE_4(5) <= '0';
-- OPCODE_5(5) <= '0';
-- OPCODE_6(5) <= '0';
-- OPCODE_7(5) <= '1';
-- else
-- OPCODE_0(5) <= '0';
-- OPCODE_1(5) <= '0';
-- OPCODE_2(5) <= '0';
-- OPCODE_3(5) <= '0';
-- OPCODE_4(5) <= '0';
-- OPCODE_5(5) <= '0';
-- OPCODE_6(5) <= '0';
-- OPCODE_7(5) <= '0';
-- end if;
--
-- --assigning address B to column
-- if (COL_B = 0) then
-- OPCODE_0(4) <= '1';
-- OPCODE_1(4) <= '0';
-- OPCODE_2(4) <= '0';
-- OPCODE_3(4) <= '0';
-- OPCODE_4(4) <= '0';
-- OPCODE_5(4) <= '0';
-- OPCODE_6(4) <= '0';
-- OPCODE_7(4) <= '0';
-- elsif (COL_B = 1) then
-- OPCODE_0(4) <= '0';
-- OPCODE_1(4) <= '1';
-- OPCODE_2(4) <= '0';
-- OPCODE_3(4) <= '0';
-- OPCODE_4(4) <= '0';
-- OPCODE_5(4) <= '0';
-- OPCODE_6(4) <= '0';
-- OPCODE_7(4) <= '0';
-- elsif (COL_B = 2) then
-- OPCODE_0(4) <= '0';
-- OPCODE_1(4) <= '0';
-- OPCODE_2(4) <= '1';
-- OPCODE_3(4) <= '0';
-- OPCODE_4(4) <= '0';
-- OPCODE_5(4) <= '0';
-- OPCODE_6(4) <= '0';
-- OPCODE_7(4) <= '0';
-- elsif (COL_B = 3) then
-- OPCODE_0(4) <= '0';
-- OPCODE_1(4) <= '0';
-- OPCODE_2(4) <= '0';
-- OPCODE_3(4) <= '1';
-- OPCODE_4(4) <= '0';
-- OPCODE_5(4) <= '0';
-- OPCODE_6(4) <= '0';
-- OPCODE_7(4) <= '0';
-- elsif (COL_B = 4) then
-- OPCODE_0(4) <= '0';
-- OPCODE_1(4) <= '0';
-- OPCODE_2(4) <= '0';
-- OPCODE_3(4) <= '0';
-- OPCODE_4(4) <= '1';
-- OPCODE_5(4) <= '0';
-- OPCODE_6(4) <= '0';
-- OPCODE_7(4) <= '0';
-- elsif (COL_B = 5) then
-- OPCODE_0(4) <= '0';
-- OPCODE_1(4) <= '0';
-- OPCODE_2(4) <= '0';
-- OPCODE_3(4) <= '0';
-- OPCODE_4(4) <= '0';
-- OPCODE_5(4) <= '1';
-- OPCODE_6(4) <= '0';
-- OPCODE_7(4) <= '0';
-- elsif (COL_B = 6) then
-- OPCODE_0(4) <= '0';
-- OPCODE_1(4) <= '0';
-- OPCODE_2(4) <= '0';
-- OPCODE_3(4) <= '0';
-- OPCODE_4(4) <= '0';
-- OPCODE_5(4) <= '0';
-- OPCODE_6(4) <= '1';
-- OPCODE_7(4) <= '0';
-- elsif (COL_B = 7) then
-- OPCODE_0(4) <= '0';
-- OPCODE_1(4) <= '0';
-- OPCODE_2(4) <= '0';
-- OPCODE_3(4) <= '0';
-- OPCODE_4(4) <= '0';
-- OPCODE_5(4) <= '0';
-- OPCODE_6(4) <= '0';
-- OPCODE_7(4) <= '1';
-- else
-- OPCODE_0(4) <= '0';
-- OPCODE_1(4) <= '0';
-- OPCODE_2(4) <= '0';
-- OPCODE_3(4) <= '0';
-- OPCODE_4(4) <= '0';
-- OPCODE_5(4) <= '0';
-- OPCODE_6(4) <= '0';
-- OPCODE_7(4) <= '0';
-- end if;
--
-- --assigning address C to column
-- if (COL_C = 0) then
-- OPCODE_0(3) <= '1';
-- OPCODE_1(3) <= '0';
-- OPCODE_2(3) <= '0';
-- OPCODE_3(3) <= '0';
-- OPCODE_4(3) <= '0';
-- OPCODE_5(3) <= '0';
-- OPCODE_6(3) <= '0';
-- OPCODE_7(3) <= '0';
-- elsif (COL_C = 1) then
-- OPCODE_0(3) <= '0';
-- OPCODE_1(3) <= '1';
-- OPCODE_2(3) <= '0';
-- OPCODE_3(3) <= '0';
-- OPCODE_4(3) <= '0';
-- OPCODE_5(3) <= '0';
-- OPCODE_6(3) <= '0';
-- OPCODE_7(3) <= '0';
-- elsif (COL_C = 2) then
-- OPCODE_0(3) <= '0';
-- OPCODE_1(3) <= '0';
-- OPCODE_2(3) <= '1';
-- OPCODE_3(3) <= '0';
-- OPCODE_4(3) <= '0';
-- OPCODE_5(3) <= '0';
-- OPCODE_6(3) <= '0';
-- OPCODE_7(3) <= '0';
-- elsif (COL_C = 3) then
-- OPCODE_0(3) <= '0';
-- OPCODE_1(3) <= '0';
-- OPCODE_2(3) <= '0';
-- OPCODE_3(3) <= '1';
-- OPCODE_4(3) <= '0';
-- OPCODE_5(3) <= '0';
-- OPCODE_6(3) <= '0';
-- OPCODE_7(3) <= '0';
-- elsif (COL_C = 4) then
-- OPCODE_0(3) <= '0';
-- OPCODE_1(3) <= '0';
-- OPCODE_2(3) <= '0';
-- OPCODE_3(3) <= '0';
-- OPCODE_4(3) <= '1';
-- OPCODE_5(3) <= '0';
-- OPCODE_6(3) <= '0';
-- OPCODE_7(3) <= '0';
-- elsif (COL_C = 5) then
-- OPCODE_0(3) <= '0';
-- OPCODE_1(3) <= '0';
-- OPCODE_2(3) <= '0';
-- OPCODE_3(3) <= '0';
-- OPCODE_4(3) <= '0';
-- OPCODE_5(3) <= '1';
-- OPCODE_6(3) <= '0';
-- OPCODE_7(3) <= '0';
-- elsif (COL_C = 6) then
-- OPCODE_0(3) <= '0';
-- OPCODE_1(3) <= '0';
-- OPCODE_2(3) <= '0';
-- OPCODE_3(3) <= '0';
-- OPCODE_4(3) <= '0';
-- OPCODE_5(3) <= '0';
-- OPCODE_6(3) <= '1';
-- OPCODE_7(3) <= '0';
-- elsif (COL_C = 7) then
-- OPCODE_0(3) <= '0';
-- OPCODE_1(3) <= '0';
-- OPCODE_2(3) <= '0';
-- OPCODE_3(3) <= '0';
-- OPCODE_4(3) <= '0';
-- OPCODE_5(3) <= '0';
-- OPCODE_6(3) <= '0';
-- OPCODE_7(3) <= '1';
-- else
-- OPCODE_0(3) <= '0';
-- OPCODE_1(3) <= '0';
-- OPCODE_2(3) <= '0';
-- OPCODE_3(3) <= '0';
-- OPCODE_4(3) <= '0';
-- OPCODE_5(3) <= '0';
-- OPCODE_6(3) <= '0';
-- OPCODE_7(3) <= '0';
-- end if;
-- --assigning address D to column
-- if (COL_D = 0) then
-- OPCODE_0(2) <= '1';
-- OPCODE_1(2) <= '0';
-- OPCODE_2(2) <= '0';
-- OPCODE_3(2) <= '0';
-- OPCODE_4(2) <= '0';
-- OPCODE_5(2) <= '0';
-- OPCODE_6(2) <= '0';
-- OPCODE_7(2) <= '0';
-- elsif (COL_D = 1) then
-- OPCODE_0(2) <= '0';
-- OPCODE_1(2) <= '1';
-- OPCODE_2(2) <= '0';
-- OPCODE_3(2) <= '0';
-- OPCODE_4(2) <= '0';
-- OPCODE_5(2) <= '0';
-- OPCODE_6(2) <= '0';
-- OPCODE_7(2) <= '0';
-- elsif (COL_D = 2) then
-- OPCODE_0(2) <= '0';
-- OPCODE_1(2) <= '0';
-- OPCODE_2(2) <= '1';
-- OPCODE_3(2) <= '0';
-- OPCODE_4(2) <= '0';
-- OPCODE_5(2) <= '0';
-- OPCODE_6(2) <= '0';
-- OPCODE_7(2) <= '0';
-- elsif (COL_D = 3) then
-- OPCODE_0(2) <= '0';
-- OPCODE_1(2) <= '0';
-- OPCODE_2(2) <= '0';
-- OPCODE_3(2) <= '1';
-- OPCODE_4(2) <= '0';
-- OPCODE_5(2) <= '0';
-- OPCODE_6(2) <= '0';
-- OPCODE_7(2) <= '0';
-- elsif (COL_D = 4) then
-- OPCODE_0(2) <= '0';
-- OPCODE_1(2) <= '0';
-- OPCODE_2(2) <= '0';
-- OPCODE_3(2) <= '0';
-- OPCODE_4(2) <= '1';
-- OPCODE_5(2) <= '0';
-- OPCODE_6(2) <= '0';
-- OPCODE_7(2) <= '0';
-- elsif (COL_D = 5) then
-- OPCODE_0(2) <= '0';
-- OPCODE_1(2) <= '0';
-- OPCODE_2(2) <= '0';
-- OPCODE_3(2) <= '0';
-- OPCODE_4(2) <= '0';
-- OPCODE_5(2) <= '1';
-- OPCODE_6(2) <= '0';
-- OPCODE_7(2) <= '0';
-- elsif (COL_D = 6) then
-- OPCODE_0(2) <= '0';
-- OPCODE_1(2) <= '0';
-- OPCODE_2(2) <= '0';
-- OPCODE_3(2) <= '0';
-- OPCODE_4(2) <= '0';
-- OPCODE_5(2) <= '0';
-- OPCODE_6(2) <= '1';
-- OPCODE_7(2) <= '0';
-- elsif (COL_D = 7) then
-- OPCODE_0(2) <= '0';
-- OPCODE_1(2) <= '0';
-- OPCODE_2(2) <= '0';
-- OPCODE_3(2) <= '0';
-- OPCODE_4(2) <= '0';
-- OPCODE_5(2) <= '0';
-- OPCODE_6(2) <= '0';
-- OPCODE_7(2) <= '1';
-- else
-- OPCODE_0(2) <= '0';
-- OPCODE_1(2) <= '0';
-- OPCODE_2(2) <= '0';
-- OPCODE_3(2) <= '0';
-- OPCODE_4(2) <= '0';
-- OPCODE_5(2) <= '0';
-- OPCODE_6(2) <= '0';
-- OPCODE_7(2) <= '0';
-- end if;
-- --assigning address E to column
-- if (COL_E = 0) then
-- OPCODE_0(1) <= '1';
-- OPCODE_1(1) <= '0';
-- OPCODE_2(1) <= '0';
-- OPCODE_3(1) <= '0';
-- OPCODE_4(1) <= '0';
-- OPCODE_5(1) <= '0';
-- OPCODE_6(1) <= '0';
-- OPCODE_7(1) <= '0';
-- elsif (COL_E = 1) then
-- OPCODE_0(1) <= '0';
-- OPCODE_1(1) <= '1';
-- OPCODE_2(1) <= '0';
-- OPCODE_3(1) <= '0';
-- OPCODE_4(1) <= '0';
-- OPCODE_5(1) <= '0';
-- OPCODE_6(1) <= '0';
-- OPCODE_7(1) <= '0';
-- elsif (COL_E = 2) then
-- OPCODE_0(1) <= '0';
-- OPCODE_1(1) <= '0';
-- OPCODE_2(1) <= '1';
-- OPCODE_3(1) <= '0';
-- OPCODE_4(1) <= '0';
-- OPCODE_5(1) <= '0';
-- OPCODE_6(1) <= '0';
-- OPCODE_7(1) <= '0';
-- elsif (COL_E = 3) then
-- OPCODE_0(1) <= '0';
-- OPCODE_1(1) <= '0';
-- OPCODE_2(1) <= '0';
-- OPCODE_3(1) <= '1';
-- OPCODE_4(1) <= '0';
-- OPCODE_5(1) <= '0';
-- OPCODE_6(1) <= '0';
-- OPCODE_7(1) <= '0';
-- elsif (COL_E = 4) then
-- OPCODE_0(1) <= '0';
-- OPCODE_1(1) <= '0';
-- OPCODE_2(1) <= '0';
-- OPCODE_3(1) <= '0';
-- OPCODE_4(1) <= '1';
-- OPCODE_5(1) <= '0';
-- OPCODE_6(1) <= '0';
-- OPCODE_7(1) <= '0';
-- elsif (COL_E = 5) then
-- OPCODE_0(1) <= '0';
-- OPCODE_1(1) <= '0';
-- OPCODE_2(1) <= '0';
-- OPCODE_3(1) <= '0';
-- OPCODE_4(1) <= '0';
-- OPCODE_5(1) <= '1';
-- OPCODE_6(1) <= '0';
-- OPCODE_7(1) <= '0';
-- elsif (COL_E = 6) then
-- OPCODE_0(1) <= '0';
-- OPCODE_1(1) <= '0';
-- OPCODE_2(1) <= '0';
-- OPCODE_3(1) <= '0';
-- OPCODE_4(1) <= '0';
-- OPCODE_5(1) <= '0';
-- OPCODE_6(1) <= '1';
-- OPCODE_7(1) <= '0';
-- elsif (COL_E = 7) then
-- OPCODE_0(1) <= '0';
-- OPCODE_1(1) <= '0';
-- OPCODE_2(1) <= '0';
-- OPCODE_3(1) <= '0';
-- OPCODE_4(1) <= '0';
-- OPCODE_5(1) <= '0';
-- OPCODE_6(1) <= '0';
-- OPCODE_7(1) <= '1';
-- else
-- OPCODE_0(1) <= '0';
-- OPCODE_1(1) <= '0';
-- OPCODE_2(1) <= '0';
-- OPCODE_3(1) <= '0';
-- OPCODE_4(1) <= '0';
-- OPCODE_5(1) <= '0';
-- OPCODE_6(1) <= '0';
-- OPCODE_7(1) <= '0';
-- end if;
-- --assigning address W to column
-- if (COL_W = 0) then
-- OPCODE_0(0) <= '1' and W_EN;
-- OPCODE_1(0) <= '0';
-- OPCODE_2(0) <= '0';
-- OPCODE_3(0) <= '0';
-- OPCODE_4(0) <= '0';
-- OPCODE_5(0) <= '0';
-- OPCODE_6(0) <= '0';
-- OPCODE_7(0) <= '0';
-- elsif (COL_W = 1) then
-- OPCODE_0(0) <= '0';
-- OPCODE_1(0) <= '1' and W_EN;
-- OPCODE_2(0) <= '0';
-- OPCODE_3(0) <= '0';
-- OPCODE_4(0) <= '0';
-- OPCODE_5(0) <= '0';
-- OPCODE_6(0) <= '0';
-- OPCODE_7(0) <= '0';
-- elsif (COL_W = 2) then
-- OPCODE_0(0) <= '0';
-- OPCODE_1(0) <= '0';
-- OPCODE_2(0) <= '1' and W_EN;
-- OPCODE_3(0) <= '0';
-- OPCODE_4(0) <= '0';
-- OPCODE_5(0) <= '0';
-- OPCODE_6(0) <= '0';
-- OPCODE_7(0) <= '0';
-- elsif (COL_W = 3) then
-- OPCODE_0(0) <= '0';
-- OPCODE_1(0) <= '0';
-- OPCODE_2(0) <= '0';
-- OPCODE_3(0) <= '1' and W_EN;
-- OPCODE_4(0) <= '0';
-- OPCODE_5(0) <= '0';
-- OPCODE_6(0) <= '0';
-- OPCODE_7(0) <= '0';
-- elsif (COL_W = 4) then
-- OPCODE_0(0) <= '0';
-- OPCODE_1(0) <= '0';
-- OPCODE_2(0) <= '0';
-- OPCODE_3(0) <= '0';
-- OPCODE_4(0) <= '1' and W_EN;
-- OPCODE_5(0) <= '0';
-- OPCODE_6(0) <= '0';
-- OPCODE_7(0) <= '0';
-- elsif (COL_W = 5) then
-- OPCODE_0(0) <= '0';
-- OPCODE_1(0) <= '0';
-- OPCODE_2(0) <= '0';
-- OPCODE_3(0) <= '0';
-- OPCODE_4(0) <= '0';
-- OPCODE_5(0) <= '1' and W_EN;
-- OPCODE_6(0) <= '0';
-- OPCODE_7(0) <= '0';
-- elsif (COL_W = 6) then
-- OPCODE_0(0) <= '0';
-- OPCODE_1(0) <= '0';
-- OPCODE_2(0) <= '0';
-- OPCODE_3(0) <= '0';
-- OPCODE_4(0) <= '0';
-- OPCODE_5(0) <= '0';
-- OPCODE_6(0) <= '1' and W_EN;
-- OPCODE_7(0) <= '0';
-- elsif (COL_W = 7) then
-- OPCODE_0(0) <= '0';
-- OPCODE_1(0) <= '0';
-- OPCODE_2(0) <= '0';
-- OPCODE_3(0) <= '0';
-- OPCODE_4(0) <= '0';
-- OPCODE_5(0) <= '0';
-- OPCODE_6(0) <= '0';
-- OPCODE_7(0) <= '1' and W_EN;
-- else
-- OPCODE_0(0) <= '0';
-- OPCODE_1(0) <= '0';
-- OPCODE_2(0) <= '0';
-- OPCODE_3(0) <= '0';
-- OPCODE_4(0) <= '0';
-- OPCODE_5(0) <= '0';
-- OPCODE_6(0) <= '0';
-- OPCODE_7(0) <= '0';
-- end if;
-- end process;
end gen;
|
gpl-2.0
|
8814de35633dbd2c125f2bc25abbd1b7
| 0.407256 | 1.912656 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_sMuxAltr.vhd
| 20 | 3,446 |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity alt_dspbuilder_sMuxAltr is
generic ( lpm_pipeline : natural:=0;
lpm_size : positive:=5;
lpm_widths : positive:=3;
lpm_width : positive:=8;
SelOneHot : natural:=0);
PORT ( clock : in std_logic ;
aclr : in std_logic := '0';
user_aclr : in std_logic := '0';
ena : in std_logic := '1';
data : in std_logic_vector (lpm_width*lpm_size-1 downto 0);
sel : in std_logic_vector (lpm_widths-1 downto 0);
result : out std_logic_vector (lpm_width-1 downto 0));
end alt_dspbuilder_sMuxAltr;
architecture synth of alt_dspbuilder_sMuxAltr is
function salive( ipp : integer; w : natural ) return std_logic_vector is
variable sxbus : std_logic_vector(w-1 downto 0);
begin
for i in 0 to w-1 loop
if ipp=i then
sxbus(i) :='1';
else
sxbus(i) :='0';
end if;
end loop;
return sxbus;
end;
signal selint : std_logic_vector(nbitnecessary(lpm_size)-1 downto 0);
signal dataa : std_logic_2d (lpm_size-1 downto 0, lpm_width-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gnoh:if SelOneHot=0 generate
selint <= sel;
end generate gnoh;
g_one_hot:if SelOneHot>0 generate
gi:for i in 0 to lpm_size-1 generate
selint <= int2ustd(i,nbitnecessary(lpm_size)) when sel = salive(i, lpm_size) else (others=>'Z');
end generate gi;
end generate g_one_hot;
g2d:for i in 1 to lpm_size generate
gw:for j in 0 to lpm_width-1 generate
dataa(i-1,j) <= data(j+(i-1)*lpm_width);
end generate gw;
end generate g2d;
gp:if lpm_pipeline>0 generate
U0 : lpm_mux generic map ( lpm_pipeline => lpm_pipeline,
lpm_size => lpm_size,
lpm_widths => nbitnecessary(lpm_size),
lpm_width => lpm_width,
lpm_type => "LPM_MUX")
port map ( sel => selint,
clken => ena,
aclr => aclr_i,
clock => clock,
data => dataa,
result => result);
end generate gp;
gc:if lpm_pipeline=0 generate
U0 : lpm_mux generic map ( lpm_size => lpm_size,
lpm_widths => nbitnecessary(lpm_size),
lpm_width => lpm_width,
lpm_type => "LPM_MUX")
port map ( sel => selint,
data => dataa,
result => result);
end generate gc;
end synth;
|
mit
|
5f34a113aa3f7dcb234bea3ffefd24dd
| 0.634068 | 3.37182 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
16x004-00_src/Source/pcie_x1_pkg.vhd
| 1 | 65,590 |
-------------------------------------------------------------------------------
-- Title : package for PCIe simulation model
-- Project : 16z091-
-------------------------------------------------------------------------------
-- File : pcie_x1_pkg.vhd
-- Author : [email protected]
-- Organization: MEN Mikro Elektronik GmbH
-- Created : 2012-10-02
-------------------------------------------------------------------------------
-- Simulator :
-- Synthesis :
-------------------------------------------------------------------------------
-- Description :
-- PCIe package for x1 configuration
-------------------------------------------------------------------------------
-- Hierarchy :
--
-------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.print_pkg.all;
use work.types_pkg.all;
use work.utils_pkg.all;
library pciebfm_lib;
use pciebfm_lib.pkg_plda_fio.all;
use pciebfm_lib.pkg_xbfm.all;
package pcie_x1_pkg is
-----------------------------------------------------
-- constants to use in terminal_out.tga(1 downto 0)
-----------------------------------------------------
constant IO_TRANSFER : std_logic_vector(1 downto 0) := "00";
constant MEM32_TRANSFER : std_logic_vector(1 downto 0) := "01";
constant CONFIG_TRANSFER : std_logic_vector(1 downto 0) := "10";
-----------------------------------------------------
-- constants to use in terminal_out.tga(3 downto 2)
-----------------------------------------------------
constant BFM_NBR_0 : std_logic_vector(1 downto 0) := "00";
constant BFM_NBR_1 : std_logic_vector(1 downto 0) := "01";
constant BFM_NBR_2 : std_logic_vector(1 downto 0) := "10";
constant BFM_NBR_3 : std_logic_vector(1 downto 0) := "11";
------------------------------
-- constants for general use
------------------------------
constant BFM_BUFFER_MAX_SIZE : integer := 1024;
constant DONT_CHECK32 : std_logic_vector(31 downto 0) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
--! function that calculates the last byte enables of a transfer
--! @param first_dw first enabled bytes of this transfer
--! @param byte_count amount of bytes for this transfer
--! @return last_dw(3 downto 0) last enabled bytes for this transfer
function calc_last_dw(
first_dw : std_logic_vector(3 downto 0);
byte_count : integer
) return std_logic_vector; -- returns std_logic_vector(3 downto 0)
--! procedure to check a value against a reference value
--! @param caller_proc string argument which is used in error messages to define the position where
--! this procedure was called from
--! @param ref_val 32bit reference value
--! @param check_val 32bit value that is checked against ref_val
--! @param byte_valid defines which byte of check_val is valid, invalid bytes are not compared
--! @return check_ok boolean argument which states whether the check was ok (=true) or not
procedure check_val(
caller_proc : in string;
ref_val : in std_logic_vector(31 downto 0);
check_val : in std_logic_vector(31 downto 0);
byte_valid : in std_logic_vector(3 downto 0);
check_ok : out boolean
);
--! procedure to initialize the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be initialized
--! @param io_add start address for the BFM internal I/O space
--! @param mem32_addr start address for the BFM internal MEM32 space
--! @param mem64_addr start address for the BFM internal MEM64 space
--! @param requester_id defines the requester ID that is used for every BFM transfer
--! @param max_payloadsize defines the maximum payload size for every write request
procedure init_bfm(
bfm_inst_nbr : in integer;
io_addr : in std_logic_vector(31 downto 0);
mem32_addr : in std_logic_vector(31 downto 0);
mem64_addr : in std_logic_vector(63 downto 0);
requester_id : in std_logic_vector(15 downto 0);
max_payloadsize : in integer
);
--! procedure to configure the BFM0, custom version for cfg record
--! @param cfg_i input record of type cfg_in_type
--! @return cfg_o returns record of cfg_out_type
procedure configure_bfm(
signal cfg_i : in cfg_in_type;
signal cfg_o : out cfg_out_type
);
--! procedure to configure the BFM, custom version for cfg record
--! @param cfg_i input record of type cfg_in_type
--! @return cfg_o returns record of cfg_out_type
procedure configure_bfm(
bfm_inst_nbr : in integer;
signal cfg_i : in cfg_in_type;
signal cfg_o : out cfg_out_type
);
--! procedure to configure the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be configured
--! @param max_payload_size maximum payload size for write requests
--! @param max_read_size maximum payload size for read requests
--! @param bar0 BAR0 settings
--! @param bar1 BAR1 settings
--! @param bar2 BAR2 settings
--! @param bar3 BAR3 settings
--! @param bar4 BAR4 settings
--! @param bar5 BAR5 settings
--! @param cmd_status_reg settings for the command status register
--! @param ctrl_status_reg settings for the control status register
procedure configure_bfm (
bfm_inst_nbr : in integer;
max_payload_size : in integer;
max_read_size : in integer;
bar0 : in std_logic_vector(31 downto 0);
bar1 : in std_logic_vector(31 downto 0);
bar2 : in std_logic_vector(31 downto 0);
bar3 : in std_logic_vector(31 downto 0);
bar4 : in std_logic_vector(31 downto 0);
bar5 : in std_logic_vector(31 downto 0);
cmd_status_reg : in std_logic_vector(31 downto 0);
ctrl_status_reg : in std_logic_vector(31 downto 0)
);
--! procedure to write values to the BFM internal memory
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param nbr_of_dw number of DWORDS that will be written
--! @param io_space set to true is I/O space is targeted
--! @param mem32 set to true is MEM32 space is targeted, otherwise MEM64 space is used
--! @param mem_addr offset for internal memory space, start at x"0000_0000"
--! @param start_data_val first data value to write, other values are defined by data_inc
--! @param data_inc defines the data increment added to start_data_val for DW 2 to nbr_of_dw
procedure set_bfm_memory(
bfm_inst_nbr : in integer;
nbr_of_dw : in integer;
io_space : in boolean;
mem32 : in boolean;
mem_addr : in std_logic_vector(31 downto 0);
start_data_val : in std_logic_vector(31 downto 0);
data_inc : in integer
);
--! procedure to read from BFM internal memory
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param nbr_of_dw number of DWORDS that will be written
--! @param io_space set to true is I/O space is targeted
--! @param mem32 set to true is MEM32 space is targeted, otherwise MEM64 space is used
--! @param mem_addr offset for internal memory space, start at x"0000_0000"
--! @return databuf_out returns a dword_vector that contains all data read from BFM internal memory
procedure get_bfm_memory(
bfm_inst_nbr : in integer;
nbr_of_dw : in integer;
io_space : in boolean;
mem32 : in boolean;
mem_addr : in std_logic_vector(31 downto 0);
databuf_out : out dword_vector(BFM_BUFFER_MAX_SIZE downto 0)
);
--! procedure to issue an I/O write to the DUT
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param byte_en bytes enables for this transfer
--! @param pcie_addr address at DUT to write to
--! @param data32 32bit data value to write
--! @param wait_end set to true to wait until transfer is finished and check for transfer errors
--! @return success returns true if transfer is done and finished without errors (if wait_end = true)
procedure bfm_wr_io(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
success : out boolean -- used when wait_end = true
);
--! procedure to issue an I/O read to the DUT
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param byte_en bytes enables for this transfer
--! @param pcie_addr address at DUT to read from
--! @param ref_data32 reference data value for read data check, use DONT_CHECK to skip check
--! @param wait_end set to true to wait until transfer is finished and check for transfer errors
--! @return data32_out 32bit data value returned from read
--! @return success returns true if transfer is done and finished without errors (if wait_end = true)
procedure bfm_rd_io(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
ref_data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
data32_out : out std_logic_vector(31 downto 0);
success : out boolean -- used when wait_end = true
);
--! procedure to issue an single MEM32 write request to the DUT
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param byte_en bytes enables for this transfer
--! @param pcie_addr address at DUT to write to
--! @param data32 32bit data value to write
--! @param wait_end set to true to wait until transfer is finished and check for transfer errors
--! @return success returns true if transfer is done and finished without errors (if wait_end = true)
procedure bfm_wr_mem32(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 0);
data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
success : out boolean
);
--! procedure to issue an burst MEM32 write request to the DUT
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param byte_count amount of bytes that shall be transferred
--! @param pcie_addr address at DUT to write to
--! @param data32 dword_vector that contains all data values to write
--! @param t_class defines the traffic class this transfer shall have, use "000" as default
--! @param attributes defines the attributes this transfer shall have, use "00" as default
--! @param wait_end set to true to wait until transfer is finished and check for transfer errors
--! @return success returns true if transfer is done and finished without errors (if wait_end = true)
procedure bfm_wr_mem32(
bfm_inst_nbr : in integer;
byte_count : in integer;
pcie_addr : in std_logic_vector(31 downto 0);
data32 : in dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
t_class : in std_logic_vector(2 downto 0);
attributes : in std_logic_vector(1 downto 0);
wait_end : in boolean;
success : out boolean
);
--! procedure to issue a single MEM32 read request to the DUT
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param byte_en bytes enables for this transfer
--! @param pcie_addr address at DUT to read from
--! @param ref_data32 reference data value for read data check, use DONT_CHECK to skip check
--! @param wait_end set to true to wait until transfer is finished and check for transfer errors
--! @return data32_out 32bit data value returned from read
--! @return success returns true if transfer is done and finished without errors (if wait_end = true)
procedure bfm_rd_mem32(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
ref_data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
data32_out : out std_logic_vector(31 downto 0);
success : out boolean -- used when wait_end = true
);
--! procedure to issue a burst MEM32 read request to the DUT
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param byte_count amount of bytes that shall be transferred
--! @param pcie_addr address at DUT to read from
--! @param ref_data32 dword_vector that contains the reference data values for read data check, use DONT_CHECK to skip check
--! @param t_class defines the traffic class this transfer shall have, use "000" as default
--! @param attributes defines the attributes this transfer shall have, use "00" as default
--! @param wait_end set to true to wait until transfer is finished and check for transfer errors
--! @return data32_out dword_vector that contains the data values returned from read
--! @return success returns true if transfer is done and finished without errors (if wait_end = true)
procedure bfm_rd_mem32(
bfm_inst_nbr : in integer;
byte_count : in integer;
pcie_addr : in std_logic_vector(31 downto 0);
ref_data32 : in dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
t_class : in std_logic_vector(2 downto 0);
attributes : in std_logic_vector(1 downto 0);
wait_end : in boolean;
data32_out : out dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
success : out boolean
);
--! procedure to issue a configuration type 0 write request to the DUT
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param byte_en bytes enables for this transfer
--! @param pcie_addr address at DUT to write to
--! @param data32 32bit data value to write
--! @param wait_end set to true to wait until transfer is finished and check for transfer errors
--! @return success returns true if transfer is done and finished without errors (if wait_end = true)
procedure bfm_wr_config(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
success : out boolean
);
--! procedure to issue a configuration type 0 read request to the DUT
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param byte_en bytes enables for this transfer
--! @param pcie_addr address at DUT to read from
--! @param ref_data32 reference data value for read data check, use DONT_CHECK to skip check
--! @param wait_end set to true to wait until transfer is finished and check for transfer errors
--! @return data32_out 32bit data value returned from read
--! @return success returns true if transfer is done and finished without errors (if wait_end = true)
procedure bfm_rd_config(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
ref_data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
data32_out : out std_logic_vector(31 downto 0);
success : out boolean
);
--! procedure to configure the DUT configuration space to enable MSI
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param msi_allowed number of MSI that are allowed, coded vector as defined by PCIe spec
--! @return returns true if the configuration was successful
procedure configure_msi(
bfm_inst_nbr : in integer;
msi_allowed : in std_logic_vector(2 downto 0);
success : out boolean
);
--! procedure that waits for an assert INTx message
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param legacy interrupt number, possible values: 0=A, 1=B, 2=C, 3=D
--! @return none, procedure will NOT return if irq was not asserted
procedure wait_on_irq_assert(
bfm_inst_nbr : in integer;
irq_nbr : in integer range 3 downto 0
);
--! procedure that waits for a deassert INTx message
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param legacy interrupt number, possible values: 0=A, 1=B, 2=C, 3=D
--! @return none, procedure will NOT return if irq was not deasserted
procedure wait_on_irq_deassert(
bfm_inst_nbr : in integer;
irq_nbr : in integer range 3 downto 0
);
end pcie_x1_pkg;
package body pcie_x1_pkg is
function calc_last_dw(
first_dw : std_logic_vector(3 downto 0);
byte_count : integer
) return std_logic_vector is
variable first_bytes : integer := 0;
variable last_bytes : integer := 0;
variable return_int : std_logic_vector(3 downto 0);
begin
if first_dw(0) = '1' then
first_bytes := first_bytes +1;
end if;
if first_dw(1) = '1' then
first_bytes := first_bytes +1;
end if;
if first_dw(2) = '1' then
first_bytes := first_bytes +1;
end if;
if first_dw(3) = '1' then
first_bytes := first_bytes +1;
end if;
last_bytes := (byte_count - first_bytes) mod 4;
if last_bytes = 0 then
return_int := "1111";
elsif last_bytes = 1 then
return_int := "0001";
elsif last_bytes = 2 then
return_int := "0011";
elsif last_bytes = 3 then
return_int := "0111";
else
return_int := "XXXX";
assert false report "ERROR in function calc_last_dw(): illegal value for variable last_bytes" severity error;
end if;
return return_int;
end;
procedure check_val(
caller_proc : in string;
ref_val : in std_logic_vector(31 downto 0);
check_val : in std_logic_vector(31 downto 0);
byte_valid : in std_logic_vector(3 downto 0);
check_ok : out boolean
) is
variable pass : boolean := true;
begin
if byte_valid(0) = '1' then
if ref_val(7 downto 0) /= check_val(7 downto 0) then
print_now("BFM ERROR in bfm_rd_mem32(): data read does not match given reference value - mismatch in byte0");
write_s_slvec("BFM ERROR in" & caller_proc & "(): reference value[7:0] = ",ref_val(7 downto 0));
write_s_slvec("BFM ERROR in" & caller_proc & "(): read value[7:0] = ",check_val(7 downto 0));
pass := false;
end if;
end if;
if byte_valid(1) = '1' then
if ref_val(15 downto 8) /= check_val(15 downto 8) then
print_now("BFM ERROR in bfm_rd_mem32(): data read does not match given reference value - mismatch in byte1");
write_s_slvec("BFM ERROR in" & caller_proc & "(): reference value[15:8] = ",ref_val(15 downto 8));
write_s_slvec("BFM ERROR in" & caller_proc & "(): read value[15:8] = ",check_val(15 downto 8));
pass := false;
end if;
end if;
if byte_valid(2) = '1' then
if ref_val(23 downto 16) /= check_val(23 downto 16) then
print_now("BFM ERROR in bfm_rd_mem32(): data read does not match given reference value - mismatch in byte2");
write_s_slvec("BFM ERROR in" & caller_proc & "(): reference value[23:16] = ",ref_val(23 downto 16));
write_s_slvec("BFM ERROR in" & caller_proc & "(): read value[23:16] = ",check_val(23 downto 16));
pass := false;
end if;
end if;
if byte_valid(3) = '1' then
if ref_val(31 downto 24) /= check_val(31 downto 24) then
print_now("BFM ERROR in bfm_rd_mem32(): data read does not match given reference value - mismatch in byte3");
write_s_slvec("BFM ERROR in" & caller_proc & "(): reference value[31:24] = ",ref_val(31 downto 24));
write_s_slvec("BFM ERROR in" & caller_proc & "(): read value[31:24] = ",check_val(31 downto 24));
pass := false;
end if;
end if;
check_ok := pass;
end procedure;
procedure init_bfm(
bfm_inst_nbr : in integer;
io_addr : in std_logic_vector(31 downto 0);
mem32_addr : in std_logic_vector(31 downto 0);
mem64_addr : in std_logic_vector(63 downto 0);
requester_id : in std_logic_vector(15 downto 0);
max_payloadsize : in integer
) is
begin
print_now_s("BFM: initialize PCIe BFM, bfm_inst_nbr ",bfm_inst_nbr);
xbfm_init(bfm_inst_nbr,io_addr,mem32_addr,mem64_addr);
xbfm_set_requesterid(bfm_inst_nbr,requester_id);
xbfm_set_maxpayload(bfm_inst_nbr,max_payloadsize);
print_now_s("BFM: Wait until link is initialized, bfm_inst_nbr ",bfm_inst_nbr);
xbfm_wait_linkup(bfm_inst_nbr);
print_now_s("BFM: link is up, bfm_inst_nbr ",bfm_inst_nbr);
end procedure;
procedure configure_bfm(
signal cfg_i : in cfg_in_type;
signal cfg_o : out cfg_out_type
) is
variable max_read : std_logic_vector(2 downto 0);
variable max_write : std_logic_vector(2 downto 0);
begin
------------------------------
-- set PCIe MAX_PAYLOAD_SIZE
------------------------------
if cfg_i.tstcfg.max_payload <= 128 then
max_write := "000";
elsif cfg_i.tstcfg.max_payload <= 256 then
max_write := "001";
elsif cfg_i.tstcfg.max_payload <= 512 then
max_write := "010";
elsif cfg_i.tstcfg.max_payload <= 1024 then
max_write := "011";
elsif cfg_i.tstcfg.max_payload <= 2048 then
max_write := "100";
elsif cfg_i.tstcfg.max_payload <= 4096 then
max_write := "101";
else
max_write := "000";
end if;
------------------------------
-- set PCIe MAX_READ_SIZE
------------------------------
if cfg_i.tstcfg.max_read <= 128 then
max_read := "000";
elsif cfg_i.tstcfg.max_read <= 256 then
max_read := "001";
elsif cfg_i.tstcfg.max_read <= 512 then
max_read := "010";
elsif cfg_i.tstcfg.max_read <= 1024 then
max_read := "011";
elsif cfg_i.tstcfg.max_read <= 2048 then
max_read := "100";
elsif cfg_i.tstcfg.max_read <= 4096 then
max_read := "101";
else
max_read := "000";
end if;
if(cfg_i.tstcfg.set_txt = 2) then write_label("none","configure BFM with typical values", -1); end if;
if(cfg_i.tstcfg.set_txt = 2) then print("Setup BARs and command/control/status registers"); end if;
xbfm_dword (0,XBFM_CFGWR0,x"00000010",x"F",x"11100000"); -- BAR0 4kb --> need 12Bit address --> here a 1MB (=20 Bit) address is used
xbfm_dword (0,XBFM_CFGWR0,x"00000014",x"F",x"22200000"); -- BAR1 8KB --> need 13Bit address --> here a 1MB (=20 Bit) address is used
xbfm_dword (0,XBFM_CFGWR0,x"00000018",x"F",x"33300000"); -- BAR2 is I/O mapped in z91 simulation and setup with adr.: x333......
xbfm_dword (0,XBFM_CFGWR0,x"0000001C",x"F",x"44400000"); -- not used in z91 simulation but prepared for future use
xbfm_dword (0,XBFM_CFGWR0,x"00000020",x"F",x"55500000"); -- not used in z91 simulation but prepared for future use
xbfm_dword (0,XBFM_CFGWR0,x"00000024",x"F",x"66600000"); -- not used in z91 simulation but prepared for future use
xbfm_dword (0,XBFM_CFGRD0,x"00000004",x"F",x"00100000"); -- Command/Status
xbfm_dword (0,XBFM_CFGWR0,x"00000004",x"F",x"000001FF"); -- Control/Status
xbfm_wait (0);
if(cfg_i.tstcfg.set_txt = 2) then print("Set max payload & max read request registers"); end if;
xbfm_dword (0,XBFM_CFGWR0,x"00000088",x"F",x"0000" & '0' & max_read & x"8" & max_write & "00000");
xbfm_dword (0,XBFM_CFGRD0,x"00000088",x"F",x"0000" & '0' & max_read & x"8" & max_write & "00000");
xbfm_wait (0);
write_label("ns","PCIe config via BFM done", -1);
end procedure;
procedure configure_bfm(
bfm_inst_nbr : in integer;
signal cfg_i : in cfg_in_type;
signal cfg_o : out cfg_out_type
) is
variable max_read : std_logic_vector(2 downto 0);
variable max_write : std_logic_vector(2 downto 0);
begin
------------------------------
-- set PCIe MAX_PAYLOAD_SIZE
------------------------------
if cfg_i.tstcfg.max_payload <= 128 then
max_write := "000";
elsif cfg_i.tstcfg.max_payload <= 256 then
max_write := "001";
elsif cfg_i.tstcfg.max_payload <= 512 then
max_write := "010";
elsif cfg_i.tstcfg.max_payload <= 1024 then
max_write := "011";
elsif cfg_i.tstcfg.max_payload <= 2048 then
max_write := "100";
elsif cfg_i.tstcfg.max_payload <= 4096 then
max_write := "101";
else
max_write := "000";
end if;
------------------------------
-- set PCIe MAX_READ_SIZE
------------------------------
if cfg_i.tstcfg.max_read <= 128 then
max_read := "000";
elsif cfg_i.tstcfg.max_read <= 256 then
max_read := "001";
elsif cfg_i.tstcfg.max_read <= 512 then
max_read := "010";
elsif cfg_i.tstcfg.max_read <= 1024 then
max_read := "011";
elsif cfg_i.tstcfg.max_read <= 2048 then
max_read := "100";
elsif cfg_i.tstcfg.max_read <= 4096 then
max_read := "101";
else
max_read := "000";
end if;
if(cfg_i.tstcfg.set_txt = 2) then write_label("none","configure BFM with typical values", -1); end if;
if(cfg_i.tstcfg.set_txt = 2) then print("Setup BARs and command/control/status registers"); end if;
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000010",x"F",x"11100000"); -- BAR0 4kb --> need 12Bit address --> here a 1MB (=20 Bit) address is used
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000014",x"F",x"22200000"); -- BAR1 8KB --> need 13Bit address --> here a 1MB (=20 Bit) address is used
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000018",x"F",x"33300000"); -- BAR2 is I/O mapped in z91 simulation and setup with adr.: x333......
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"0000001C",x"F",x"44400000"); -- not used in z91 simulation but prepared for future use
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000020",x"F",x"55500000"); -- not used in z91 simulation but prepared for future use
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000024",x"F",x"66600000"); -- not used in z91 simulation but prepared for future use
xbfm_dword (bfm_inst_nbr,XBFM_CFGRD0,x"00000004",x"F",x"00100000"); -- Command/Status
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000004",x"F",x"000001FF"); -- Control/Status
xbfm_wait (bfm_inst_nbr);
if(cfg_i.tstcfg.set_txt = 2) then print("Set max payload & max read request registers"); end if;
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000088",x"F",x"0000" & '0' & max_read & x"8" & max_write & "00000");
xbfm_dword (bfm_inst_nbr,XBFM_CFGRD0,x"00000088",x"F",x"0000" & '0' & max_read & x"8" & max_write & "00000");
xbfm_wait (bfm_inst_nbr);
write_label("ns","PCIe config via BFM done", -1);
end procedure;
procedure configure_bfm (
bfm_inst_nbr : in integer;
max_payload_size : in integer;
max_read_size : in integer;
bar0 : in std_logic_vector(31 downto 0);
bar1 : in std_logic_vector(31 downto 0);
bar2 : in std_logic_vector(31 downto 0);
bar3 : in std_logic_vector(31 downto 0);
bar4 : in std_logic_vector(31 downto 0);
bar5 : in std_logic_vector(31 downto 0);
cmd_status_reg : in std_logic_vector(31 downto 0);
ctrl_status_reg : in std_logic_vector(31 downto 0)
) is
variable max_read : std_logic_vector(2 downto 0);
variable max_write : std_logic_vector(2 downto 0);
begin
print_now("BFM: calculate max_payload_size and max_read_size");
------------------------------
-- set PCIe MAX_PAYLOAD_SIZE
------------------------------
if max_payload_size <= 128 then
max_write := "000";
elsif max_payload_size <= 256 then
max_write := "001";
elsif max_payload_size <= 512 then
max_write := "010";
elsif max_payload_size <= 1024 then
max_write := "011";
elsif max_payload_size <= 2048 then
max_write := "100";
elsif max_payload_size <= 4096 then
max_write := "101";
else
max_write := "000";
end if;
------------------------------
-- set PCIe MAX_READ_SIZE
------------------------------
if max_read_size <= 128 then
max_read := "000";
elsif max_read_size <= 256 then
max_read := "001";
elsif max_read_size <= 512 then
max_read := "010";
elsif max_read_size <= 1024 then
max_read := "011";
elsif max_read_size <= 2048 then
max_read := "100";
elsif max_read_size <= 4096 then
max_read := "101";
else
max_read := "000";
end if;
print_now_s("BFM: setup BARs and command/control/status registers, bfm_inst_nbr ",bfm_inst_nbr);
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000010",x"F",bar0); -- BAR0
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000014",x"F",bar1); -- BAR1
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000018",x"F",bar2); -- BAR2
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"0000001C",x"F",bar3); -- BAR3
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000020",x"F",bar4); -- BAR4
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000024",x"F",bar5); -- BAR5
xbfm_dword (bfm_inst_nbr,XBFM_CFGRD0,x"00000004",x"F",cmd_status_reg); -- Command/Status
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000004",x"F",ctrl_status_reg); -- Control/Status
print_now_s("BFM: wait until all values are set, bfm_inst_nbr ",bfm_inst_nbr);
xbfm_wait (bfm_inst_nbr);
print_now_s("BFM: set max_payload & max_read registers, bfm_inst_nbr ",bfm_inst_nbr);
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000088",x"F",x"0000" & '0' & max_read & x"8" & max_write & "00000");
xbfm_dword (bfm_inst_nbr,XBFM_CFGRD0,x"00000088",x"F",x"0000" & '0' & max_read & x"8" & max_write & "00000");
print_now_s("BFM: wait until all values are set, bfm_inst_nbr ",bfm_inst_nbr);
xbfm_wait (bfm_inst_nbr);
print_now_s("BFM: BARs and registers initialized, bfm_inst_nbr ",bfm_inst_nbr);
end procedure;
procedure set_bfm_memory(
bfm_inst_nbr : in integer;
nbr_of_dw : in integer;
io_space : in boolean;
mem32 : in boolean;
mem_addr : in std_logic_vector(31 downto 0);
start_data_val : in std_logic_vector(31 downto 0);
data_inc : in integer
) is
variable bfm_databuf : dword_vector(nbr_of_dw -1 downto 0);
begin
print_now_s("BFM: set BFM internal memory, bfm_inst_nbr ",bfm_inst_nbr);
print_s_i("BFM: number of dwords = ",nbr_of_dw);
print_s_std("BFM: start address = ", mem_addr);
print_s_std("BFM: initial data value = ", start_data_val);
print_s_i("BFM: data value increment = ",data_inc);
for i in 0 to nbr_of_dw -1 loop
bfm_databuf(i) := std_logic_vector(unsigned(start_data_val) + to_unsigned(i*data_inc,32));
end loop;
if io_space then
print("BFM: write data to IO space");
xbfm_memory_write(bfm_inst_nbr,XBFM_IO,mem_addr,nbr_of_dw,bfm_databuf);
else
if mem32 then
print("BFM: write data to MEM32 space");
xbfm_memory_write(bfm_inst_nbr,XBFM_MEM32,mem_addr,nbr_of_dw,bfm_databuf);
else
print("BFM: write data to MEM64 space");
xbfm_memory_write(bfm_inst_nbr,XBFM_MEM64,mem_addr,nbr_of_dw,bfm_databuf);
end if;
end if;
end procedure;
procedure get_bfm_memory(
bfm_inst_nbr : in integer;
nbr_of_dw : in integer;
io_space : in boolean;
mem32 : in boolean;
mem_addr : in std_logic_vector(31 downto 0);
databuf_out : out dword_vector(BFM_BUFFER_MAX_SIZE downto 0)
) is
begin
if nbr_of_dw > BFM_BUFFER_MAX_SIZE then
print_now_s("BFM ERROR in get_bfm_memory(): nbr_of_dw exceeds BFM_BUFFER_MAX_SIZE, bfm_inst_nbr ",bfm_inst_nbr);
else
print_now_s("BFM: get values from BFM internal memory, bfm_inst_nbr ",bfm_inst_nbr);
print_s_i("BFM: number of dwords = ",nbr_of_dw);
if io_space then
print("BFM: read data from IO space");
xbfm_memory_read(bfm_inst_nbr,XBFM_IO,mem_addr,nbr_of_dw,databuf_out);
else
if mem32 then
print("BFM: read data from MEM32 space");
xbfm_memory_read(bfm_inst_nbr,XBFM_MEM32,mem_addr,nbr_of_dw,databuf_out);
else
print("BFM: read data from MEM64 space");
xbfm_memory_read(bfm_inst_nbr,XBFM_MEM64,mem_addr,nbr_of_dw,databuf_out);
end if;
end if;
end if;
end procedure;
procedure bfm_wr_io(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
success : out boolean -- used when wait_end = true
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable pass : boolean := true;
begin
print_now_s("BFM: BFM I/O write, bfm_inst_nbr ",bfm_inst_nbr);
pass := true;
xbfm_dword_id(bfm_inst_nbr,XBFM_IOWR,pcie_addr & "00",byte_en,data32,bfm_trans_id);
if wait_end then
xbfm_wait_id(bfm_inst_nbr, bfm_trans_id, bfm_status, bfm_databuf);
---------------------------------------------
-- check for BFM errors during transmission
---------------------------------------------
if bfm_status /= XBFM_SC then
if bfm_status = XBFM_CA then
print_now("BFM ERROR in bfm_wr_io(): BFM status: completer abort");
elsif bfm_status = XBFM_UR then
print_now("BFM ERROR in bfm_wr_io(): BFM status: unsupported request");
elsif bfm_status = XBFM_TIMEOUT then
print_now("BFM ERROR in bfm_wr_io(): BFM status: completion timeout");
else
print_now("BFM ERROR in bfm_wr_io(): BFM status other than successful but unknown");
end if;
pass := false;
end if;
end if;
success := pass;
end procedure;
procedure bfm_rd_io(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
ref_data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
data32_out : out std_logic_vector(31 downto 0);
success : out boolean -- used when wait_end = true
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable pass : boolean := true;
begin
print_now_s("BFM: BFM I/O read, bfm_inst_nbr ",bfm_inst_nbr);
pass := true;
data32_out := (others => '0');
xbfm_dword_id(bfm_inst_nbr,XBFM_IORD,pcie_addr & "00",byte_en,bfm_databuf(0),bfm_trans_id);
if wait_end then
xbfm_wait_id(bfm_inst_nbr, bfm_trans_id, bfm_status, bfm_databuf);
---------------------------------------------
-- check for BFM errors during transmission
---------------------------------------------
if bfm_status /= XBFM_SC then
if bfm_status = XBFM_CA then
print_now("BFM ERROR in bfm_rd_io(): BFM status: completer abort");
elsif bfm_status = XBFM_UR then
print_now("BFM ERROR in bfm_rd_io(): BFM status: unsupported request");
elsif bfm_status = XBFM_TIMEOUT then
print_now("BFM ERROR in bfm_rd_io(): BFM status: completion timeout");
else
print_now("BFM ERROR in bfm_rd_io(): BFM status other than successful but unknown");
end if;
pass := false;
end if;
-----------------------------------
-- check if read value is correct
-----------------------------------
if ref_data32 = DONT_CHECK32 then
print_now("BFM: checking of read value skipped on user command");
else
check_val(
caller_proc => "bfm_rd_io",
ref_val => ref_data32,
check_val => bfm_databuf(0),
byte_valid => byte_en,
check_ok => pass
);
end if;
data32_out := bfm_databuf(0);
else
print("BFM: skipped check of read value because wait_end = false");
end if;
success := pass;
end procedure;
procedure bfm_wr_mem32(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 0);
data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
success : out boolean
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable pass : boolean := true;
begin
print_now_s("BFM: BFM MEM32 write (single), bfm_inst_nbr ",bfm_inst_nbr);
pass := true;
xbfm_dword_id(bfm_inst_nbr,XBFM_MWR,pcie_addr(31 downto 2) & "00",byte_en,data32,bfm_trans_id);
if wait_end then
xbfm_wait_id(bfm_inst_nbr, bfm_trans_id, bfm_status, bfm_databuf);
---------------------------------------------
-- check for BFM errors during transmission
---------------------------------------------
if bfm_status /= XBFM_SC then
if bfm_status = XBFM_CA then
print_now("BFM ERROR in bfm_wr_mem32(): BFM status: completer abort");
elsif bfm_status = XBFM_UR then
print_now("BFM ERROR in bfm_wr_mem32(): BFM status: unsupported request");
elsif bfm_status = XBFM_TIMEOUT then
print_now("BFM ERROR in bfm_wr_mem32(): BFM status: completion timeout");
else
print_now("BFM ERROR in bfm_wr_mem32(): BFM status other than successful but unknown");
end if;
pass := false;
end if;
else
print("BFM: skipped tranfer check because wait_end = false");
end if;
success := pass;
end procedure;
procedure bfm_wr_mem32(
bfm_inst_nbr : in integer;
byte_count : in integer;
pcie_addr : in std_logic_vector(31 downto 0);
data32 : in dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
t_class : in std_logic_vector(2 downto 0);
attributes : in std_logic_vector(1 downto 0);
wait_end : in boolean;
success : out boolean
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable pass : boolean := true;
begin
print_now_s("BFM: BFM MEM32 write (burst), bfm_inst_nbr ",bfm_inst_nbr);
pass := true;
xbfm_burst_id(bfm_inst_nbr,XBFM_MWR,x"0000_0000" & pcie_addr,byte_count,data32,t_class,attributes,bfm_trans_id);
if wait_end then
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
---------------------------------------------
-- check for BFM errors during transmission
---------------------------------------------
if bfm_status /= XBFM_SC then
if bfm_status = XBFM_CA then
print_now("BFM ERROR in bfm_wr_mem32(): BFM status: completer abort");
elsif bfm_status = XBFM_UR then
print_now("BFM ERROR in bfm_wr_mem32(): BFM status: unsupported request");
elsif bfm_status = XBFM_TIMEOUT then
print_now("BFM ERROR in bfm_wr_mem32(): BFM status: completion timeout");
else
print_now("BFM ERROR in bfm_wr_mem32(): BFM status other than successful but unknown");
end if;
pass := false;
end if;
else
print("BFM: skipped tranfer check because wait_end = false");
end if;
success := pass;
end procedure;
procedure bfm_rd_mem32(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
ref_data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
data32_out : out std_logic_vector(31 downto 0);
success : out boolean -- used when wait_end = true
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable pass : boolean := true;
begin
print_now_s("BFM: BFM MEM32 read, bfm_inst_nbr ",bfm_inst_nbr);
pass := true;
data32_out := (others => '0');
xbfm_dword_id(bfm_inst_nbr,XBFM_MRD,pcie_addr & "00",byte_en,bfm_databuf(0),bfm_trans_id);
if wait_end then
xbfm_wait_id(bfm_inst_nbr, bfm_trans_id, bfm_status, bfm_databuf);
---------------------------------------------
-- check for BFM errors during transmission
---------------------------------------------
if bfm_status /= XBFM_SC then
if bfm_status = XBFM_CA then
print_now("BFM ERROR in bfm_rd_mem32(): BFM status: completer abort");
elsif bfm_status = XBFM_UR then
print_now("BFM ERROR in bfm_rd_mem32(): BFM status: unsupported request");
elsif bfm_status = XBFM_TIMEOUT then
print_now("BFM ERROR in bfm_rd_mem32(): BFM status: completion timeout");
else
print_now("BFM ERROR in bfm_rd_mem32(): BFM status other than successful but unknown");
end if;
pass := false;
end if;
-----------------------------------
-- check if read value is correct
-----------------------------------
if ref_data32 = DONT_CHECK32 then
print_now("BFM: checking of read value skipped on user command");
else
check_val(
caller_proc => "bfm_rd_mem32",
ref_val => ref_data32,
check_val => bfm_databuf(0),
byte_valid => byte_en,
check_ok => pass
);
end if;
data32_out := bfm_databuf(0);
else
print("BFM: skipped check of read value because wait_end = false");
end if;
success := pass;
end procedure;
procedure bfm_rd_mem32(
bfm_inst_nbr : in integer;
byte_count : in integer;
pcie_addr : in std_logic_vector(31 downto 0);
ref_data32 : in dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
t_class : in std_logic_vector(2 downto 0);
attributes : in std_logic_vector(1 downto 0);
wait_end : in boolean;
data32_out : out dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
success : out boolean
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable pass : boolean := true;
variable byte_en : std_logic_vector(3 downto 0) := (others => '0');
variable first_DW_en : std_logic_vector(3 downto 0) := (others => '0');
variable last_DW_en : std_logic_vector(3 downto 0) := (others => '0');
begin
print_now_s("BFM: BFM MEM32 read (burst), bfm_inst_nbr ",bfm_inst_nbr);
pass := true;
data32_out := (others => (others => '0'));
case pcie_addr(1 downto 0) is
when "00" => first_DW_en := "1111";
when "01" => first_DW_en := "1110";
when "10" => first_DW_en := "1100";
when "11" => first_DW_en := "1000";
when others => first_DW_en := "1111";
end case;
last_DW_en := calc_last_dw(
first_dw => first_DW_en,
byte_count => byte_count );
xbfm_burst_id(bfm_inst_nbr,XBFM_MRD,x"0000_0000" & pcie_addr,byte_count,bfm_databuf,t_class,attributes,bfm_trans_id);
if wait_end then
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
---------------------------------------------
-- check for BFM errors during transmission
---------------------------------------------
if bfm_status /= XBFM_SC then
if bfm_status = XBFM_CA then
print_now("BFM ERROR in bfm_rd_mem32(): BFM status: completer abort");
elsif bfm_status = XBFM_UR then
print_now("BFM ERROR in bfm_rd_mem32(): BFM status: unsupported request");
elsif bfm_status = XBFM_TIMEOUT then
print_now("BFM ERROR in bfm_rd_mem32(): BFM status: completion timeout");
else
print_now("BFM ERROR in bfm_rd_mem32(): BFM status other than successful but unknown");
end if;
pass := false;
end if;
for i in 0 to (byte_count /4) -1 loop
if ref_data32(i) = DONT_CHECK32 then
print_now("BFM: checking of read value skipped on user command");
else
if i = 0 then
byte_en := first_DW_en;
elsif i = (byte_count /4) -1 then
byte_en := last_DW_en;
else
byte_en := x"F";
end if;
check_val(
caller_proc => "bfm_rd_mem32",
ref_val => ref_data32(i),
check_val => bfm_databuf(i),
byte_valid => byte_en,
check_ok => pass
);
end if;
wait for 0 ns;
end loop;
data32_out := bfm_databuf;
else
print("BFM: skipped check of read value because wait_end = false");
end if;
success := pass;
end procedure;
procedure bfm_wr_config(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
success : out boolean
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable pass : boolean := true;
begin
print_now_s("BFM: BFM configuration write, bfm_inst_nbr ",bfm_inst_nbr);
pass := true;
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGWR0,pcie_addr & "00",byte_en,data32,bfm_trans_id);
if wait_end then
xbfm_wait_id(bfm_inst_nbr, bfm_trans_id, bfm_status, bfm_databuf);
---------------------------------------------
-- check for BFM errors during transmission
---------------------------------------------
if bfm_status /= XBFM_SC then
if bfm_status = XBFM_CA then
print_now("BFM ERROR in bfm_wr_config(): BFM status: completer abort");
elsif bfm_status = XBFM_UR then
print_now("BFM ERROR in bfm_wr_config(): BFM status: unsupported request");
elsif bfm_status = XBFM_TIMEOUT then
print_now("BFM ERROR in bfm_wr_config(): BFM status: completion timeout");
else
print_now("BFM ERROR in bfm_wr_config(): BFM status other than successful but unknown");
end if;
pass := false;
end if;
else
print("BFM: skipped transfer check because wait_end = false");
end if;
success := pass;
end procedure;
procedure bfm_rd_config(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
ref_data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
data32_out : out std_logic_vector(31 downto 0);
success : out boolean
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable pass : boolean := true;
begin
print_now_s("BFM: BFM configuration read, bfm_inst_nbr ",bfm_inst_nbr);
pass := true;
data32_out := (others => '0');
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGRD0,pcie_addr & "00",byte_en,bfm_databuf(0),bfm_trans_id);
if wait_end then
xbfm_wait_id(bfm_inst_nbr, bfm_trans_id, bfm_status, bfm_databuf);
---------------------------------------------
-- check for BFM errors during transmission
---------------------------------------------
if bfm_status /= XBFM_SC then
if bfm_status = XBFM_CA then
print_now("BFM ERROR in bfm_rd_config(): BFM status: completer abort");
elsif bfm_status = XBFM_UR then
print_now("BFM ERROR in bfm_rd_config(): BFM status: unsupported request");
elsif bfm_status = XBFM_TIMEOUT then
print_now("BFM ERROR in bfm_rd_config(): BFM status: completion timeout");
else
print_now("BFM ERROR in bfm_rd_config(): BFM status other than successful but unknown");
end if;
pass := false;
end if;
-----------------------------------
-- check if read value is correct
-----------------------------------
if ref_data32 = DONT_CHECK32 then
print_now("BFM: checking of read value skipped on user command");
else
check_val(
caller_proc => "bfm_rd_config",
ref_val => ref_data32,
check_val => bfm_databuf(0),
byte_valid => byte_en,
check_ok => pass
);
end if;
data32_out := bfm_databuf(0);
else
print("BFM: skipped check of read value because wait_end = false");
end if;
success := pass;
end procedure;
procedure configure_msi(
bfm_inst_nbr : in integer;
msi_allowed : in std_logic_vector(2 downto 0);
success : out boolean
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(255 downto 0);
variable nextCapAddr : std_logic_vector(7 downto 0); -- address of next capability
variable data32bit : std_logic_vector(31 downto 0);
variable capID : std_logic_vector(7 downto 0);
variable msi_addr_is_64bit : std_logic;
variable temp_addr : std_logic_vector(31 downto 0);
variable pass : boolean;
begin
pass := true;
-- if(cfg_i.tstcfg.set_txt = 2) then print_now("Test MSI generation"); end if;
----------------------------------------------
-- configure PCIe config space to enable MSI
-- MSI capabilities registers for 32bit MSI addresses:
-- 31 16 15 8 7 0
-- -----------------------------------------------------
-- | message ctrl reg | next cap pointer | cap ID=0x05 | DW0
-- -----------------------------------------------------
-- | message address register | DW1
-- -----------------------------------------------------
-- | reserved | message data register | DW2
-- -----------------------------------------------------
-- MSI capabilities registers for 64bit MSI addresses:
-- 31 16 15 8 7 0
-- -----------------------------------------------------
-- | message ctrl reg | next cap pointer | cap ID=0x05 | DW0
-- -----------------------------------------------------
-- | least signif. 32bits of message address register | DW1
-- -----------------------------------------------------
-- | most signif. 32bits of message address register | DW2
-- -----------------------------------------------------
-- | reserved | message data register | DW3
-- -----------------------------------------------------
-- cycle:
-- 1. read status register and check bit4
-- if =1 then function has extended capabilities implemented
-- and capabilities pointer is implemented @DW13 = 0x34
-- 2. read capabilities pointer value which is start address of extended capabilities list
-- 3. read register @address from step 2 and check bit 7:0
-- if 7:0=0x05 then MSI register set is present
-- else read next address @15:8
-- 4. if MSI register set is found
-- check if 64bit addresses are used
-- program message address register to DW1 with 31:2=addr and 1:0=0
-- program message data register to DW2 with 31:16=0 and 15:0=data
-- 5. program DW0 with nbr of MSI allowed and enable MSI
-- read bit 19:17 of DW0 which contains nbr of MSI requested by function
-- program nbr of MSI allowed to DW0 bit 22:20 and enable MSI bit 16=1
----------------------------------------------
-- step1: read status register but disable data value check
print_now("Step1: read status register");
data32bit := (others => 'X');
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGRD0,x"0000_0004",x"F",data32bit,bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
data32bit := bfm_databuf(0);
if data32bit(20) = '0' then
--error because no next capabilities implemented
print_now("BFM ERROR in configure_msi(): function does not implement next capabilities structure thus MSI registers can not be programmmed.");
pass := false;
else
-- step2: read capabilities pointer
print_now("Step2: read capabilities pointer");
data32bit := (others => 'X');
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGRD0,x"0000_0034",x"F",data32bit,bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
data32bit := bfm_databuf(0);
nextCapAddr := data32bit(7 downto 0);
-- step3: read byte0 of registers pointed to by capabilities pointer
print_now("Step3: read byte0 of registers pointed to by capabilities pointer");
capID := (others => '0');
while capID /= x"05" loop
data32bit := (others => 'X');
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGRD0,x"000000" & nextCapAddr,x"F",data32bit,bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
data32bit := bfm_databuf(0);
capID := data32bit(7 downto 0);
if capID /= x"05" then
nextCapAddr := data32bit(15 downto 8);
end if;
end loop;
-- step4: write MSI register set contents
print_now("Step4: write MSI register set contents");
-- check if 64bit addresses are used
msi_addr_is_64bit := '0';
data32bit := (others => 'X');
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGRD0,x"000000" & nextCapAddr,x"F",data32bit,bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
data32bit := bfm_databuf(0);
msi_addr_is_64bit := data32bit(23);
-- program message address register to DW1 with 31:2=addr and 1:0=0
-- set to zero as 64bit addresses shall not be used
if msi_addr_is_64bit = '1' then
-- function does support 64bit addresses
temp_addr := x"000000" & nextCapAddr;
temp_addr := std_logic_vector(unsigned(temp_addr)+ to_unsigned(4,32));
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGWR0,temp_addr,x"F",x"AAAA_0034",bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
temp_addr := x"000000" & nextCapAddr;
temp_addr := std_logic_vector(unsigned(temp_addr)+ to_unsigned(8,32));
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGWR0,temp_addr,x"F",x"0000_0000",bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
-- program message data register to DW2 with 31:16=0 and 15:0=data
temp_addr := x"000000" & nextCapAddr;
temp_addr := std_logic_vector(unsigned(temp_addr)+ to_unsigned(12,32));
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGWR0,temp_addr,x"F",x"0000_2222",bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
else
-- fucntion does not support 64bit addresses
temp_addr := x"000000" & nextCapAddr;
temp_addr := std_logic_vector(unsigned(temp_addr)+ to_unsigned(4,32));
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGWR0,temp_addr,x"F",x"AAAA_0034",bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
-- program message data register to DW2 with 31:16=0 and 15:0=data
temp_addr := x"000000" & nextCapAddr;
temp_addr := std_logic_vector(unsigned(temp_addr)+ to_unsigned(8,32));
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGWR0,temp_addr,x"F",x"0000_2222",bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
end if;
-- step5: program DW0 with nbr of MSI allowed and enable MSI
print_now("Step5: program DW0 with nbr of MSI allowed and enable MSI");
------------------------------------------------------------------------------------------------
-- if msi_allowed = Z program the value given by "MSI requested" to the register "MSI allowed"
-- otherwise program value given by msi_allowed
------------------------------------------------------------------------------------------------
-- read bit 19:17 of DW0 which contains nbr of MSI requested by function
data32bit := (others => 'X');
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGRD0,x"000000" & nextCapAddr,x"F",data32bit,bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
data32bit := bfm_databuf(0);
-- program nbr of MSI allowed to DW0 bit 22:20 and enable MSI bit 16=1
if msi_allowed = "ZZZ" then
data32bit(22 downto 20) := data32bit(19 downto 17);
else
data32bit(22 downto 20) := msi_allowed;
end if;
data32bit(16) := '1';
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGWR0,x"000000" & nextCapAddr,"1100",data32bit,bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
end if;
success := pass;
end procedure;
procedure wait_on_irq_assert(
bfm_inst_nbr : in integer;
irq_nbr : in integer range 3 downto 0
) is
begin
if irq_nbr = 0 then
print_now("BFM: waiting on assert-INTA message");
xbfm_wait_event(bfm_inst_nbr, XBFM_INTAA_RCVD);
elsif irq_nbr = 1 then
print_now("BFM: waiting on assert-INTB message");
xbfm_wait_event(bfm_inst_nbr, XBFM_INTBA_RCVD);
elsif irq_nbr = 2 then
print_now("BFM: waiting on assert-INTC message");
xbfm_wait_event(bfm_inst_nbr, XBFM_INTCA_RCVD);
elsif irq_nbr = 3 then
print_now("BFM: waiting on assert-INTD message");
xbfm_wait_event(bfm_inst_nbr, XBFM_INTDA_RCVD);
else
assert false report "BFM ERROR in wait_on_irq_assert(): invalid value for interrupt number irq_nbr" severity failure;
end if;
end procedure wait_on_irq_assert;
procedure wait_on_irq_deassert(
bfm_inst_nbr : in integer;
irq_nbr : in integer range 3 downto 0
) is
begin
if irq_nbr = 0 then
print_now("BFM: waiting on deassert-INTA message");
xbfm_wait_event(bfm_inst_nbr, XBFM_INTAD_RCVD);
elsif irq_nbr = 1 then
print_now("BFM: waiting on deassert-INTB message");
xbfm_wait_event(bfm_inst_nbr, XBFM_INTBD_RCVD);
elsif irq_nbr = 2 then
print_now("BFM: waiting on deassert-INTC message");
xbfm_wait_event(bfm_inst_nbr, XBFM_INTCD_RCVD);
elsif irq_nbr = 3 then
print_now("BFM: waiting on deassert-INTD message");
xbfm_wait_event(bfm_inst_nbr, XBFM_INTDD_RCVD);
else
assert false report "BFM ERROR in wait_on_irq_deassert(): invalid value for interrupt number irq_nbr" severity failure;
end if;
end procedure wait_on_irq_deassert;
end;
|
gpl-3.0
|
69c56c968987c4e0435f2eb33ff65caa
| 0.560406 | 3.875561 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/generic_m20k/_primary.vhd
| 5 | 9,908 |
library verilog;
use verilog.vl_types.all;
entity generic_m20k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout: string := "none";
ecc_pipeline_stage_enabled: string := "false";
enable_ecc : string := "false";
width_eccstatus : integer := 2;
data_interleave_width_in_bits: integer := 1;
data_interleave_offset_in_bits: integer := 1;
port_a_logical_ram_depth: integer := 0;
port_a_logical_ram_width: integer := 0;
port_a_first_address: integer := 0;
port_a_last_address: integer := 0;
port_a_first_bit_number: integer := 0;
port_a_data_out_clear: string := "none";
port_a_data_out_clock: string := "none";
port_a_data_width: integer := 1;
port_a_address_width: integer := 1;
port_a_byte_enable_mask_width: integer := 1;
port_b_logical_ram_depth: integer := 0;
port_b_logical_ram_width: integer := 0;
port_b_first_address: integer := 0;
port_b_last_address: integer := 0;
port_b_first_bit_number: integer := 0;
port_b_address_clear: string := "none";
port_b_data_out_clear: string := "none";
port_b_data_in_clock: string := "clock1";
port_b_address_clock: string := "clock1";
port_b_write_enable_clock: string := "clock1";
port_b_read_enable_clock: string := "clock1";
port_b_byte_enable_clock: string := "clock1";
port_b_data_out_clock: string := "none";
port_b_data_width: integer := 1;
port_b_address_width: integer := 1;
port_b_byte_enable_mask_width: integer := 1;
port_a_read_during_write_mode: string := "new_data_no_nbe_read";
port_b_read_during_write_mode: string := "new_data_no_nbe_read";
power_up_uninitialized: string := "false";
lpm_type : string := "stratixv_ram_block";
lpm_hint : string := "true";
connectivity_checking: string := "off";
mem_init0 : string := "";
mem_init1 : string := "";
mem_init2 : string := "";
mem_init3 : string := "";
mem_init4 : string := "";
mem_init5 : string := "";
mem_init6 : string := "";
mem_init7 : string := "";
mem_init8 : string := "";
mem_init9 : string := "";
port_a_byte_size: integer := 0;
port_b_byte_size: integer := 0;
clk0_input_clock_enable: string := "none";
clk0_core_clock_enable: string := "none";
clk0_output_clock_enable: string := "none";
clk1_input_clock_enable: string := "none";
clk1_core_clock_enable: string := "none";
clk1_output_clock_enable: string := "none";
bist_ena : string := "false";
port_a_address_clear: string := "none";
port_a_data_in_clock: string := "clock0";
port_a_address_clock: string := "clock0";
port_a_write_enable_clock: string := "clock0";
port_a_byte_enable_clock: string := "clock0";
port_a_read_enable_clock: string := "clock0"
);
port(
portadatain : in vl_logic_vector;
portaaddr : in vl_logic_vector;
portawe : in vl_logic;
portare : in vl_logic;
portbdatain : in vl_logic_vector;
portbaddr : in vl_logic_vector;
portbwe : in vl_logic;
portbre : in vl_logic;
clk0 : in vl_logic;
clk1 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
ena3 : in vl_logic;
clr0 : in vl_logic;
clr1 : in vl_logic;
nerror : in vl_logic;
portabyteenamasks: in vl_logic_vector;
portbbyteenamasks: in vl_logic_vector;
portaaddrstall : in vl_logic;
portbaddrstall : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
eccstatus : out vl_logic_vector;
portadataout : out vl_logic_vector;
portbdataout : out vl_logic_vector;
dftout : out vl_logic_vector(8 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of logical_ram_name : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of init_file_layout : constant is 1;
attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1;
attribute mti_svvh_generic_type of enable_ecc : constant is 1;
attribute mti_svvh_generic_type of width_eccstatus : constant is 1;
attribute mti_svvh_generic_type of data_interleave_width_in_bits : constant is 1;
attribute mti_svvh_generic_type of data_interleave_offset_in_bits : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_a_first_address : constant is 1;
attribute mti_svvh_generic_type of port_a_last_address : constant is 1;
attribute mti_svvh_generic_type of port_a_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_data_width : constant is 1;
attribute mti_svvh_generic_type of port_a_address_width : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_b_first_address : constant is 1;
attribute mti_svvh_generic_type of port_b_last_address : constant is 1;
attribute mti_svvh_generic_type of port_b_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_read_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_width : constant is 1;
attribute mti_svvh_generic_type of port_b_address_width : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_a_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of port_b_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of connectivity_checking : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
attribute mti_svvh_generic_type of mem_init1 : constant is 1;
attribute mti_svvh_generic_type of mem_init2 : constant is 1;
attribute mti_svvh_generic_type of mem_init3 : constant is 1;
attribute mti_svvh_generic_type of mem_init4 : constant is 1;
attribute mti_svvh_generic_type of mem_init5 : constant is 1;
attribute mti_svvh_generic_type of mem_init6 : constant is 1;
attribute mti_svvh_generic_type of mem_init7 : constant is 1;
attribute mti_svvh_generic_type of mem_init8 : constant is 1;
attribute mti_svvh_generic_type of mem_init9 : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_size : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_size : constant is 1;
attribute mti_svvh_generic_type of clk0_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of bist_ena : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_read_enable_clock : constant is 1;
end generic_m20k;
|
mit
|
6b5b16aa29d08a1c14705820d07a115e
| 0.6304 | 3.449861 | false | false | false | false |
freecores/t48
|
rtl/vhdl/dmem_ctrl.vhd
| 1 | 7,210 |
-------------------------------------------------------------------------------
--
-- The Data Memory control unit.
-- All accesses to the Data Memory are managed here.
--
-- $Id: dmem_ctrl.vhd,v 1.5 2006-06-20 01:07:16 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.dmem_addr_t;
use work.t48_pack.word_t;
use work.t48_dmem_ctrl_pack.dmem_addr_ident_t;
entity t48_dmem_ctrl is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- Control Interface ------------------------------------------------------
data_i : in word_t;
write_dmem_addr_i : in boolean;
write_dmem_i : in boolean;
read_dmem_i : in boolean;
addr_type_i : in dmem_addr_ident_t;
bank_select_i : in std_logic;
data_o : out word_t;
-- Data Memory Interface --------------------------------------------------
dmem_data_i : in word_t;
dmem_addr_o : out dmem_addr_t;
dmem_we_o : out std_logic;
dmem_data_o : out word_t
);
end t48_dmem_ctrl;
library ieee;
use ieee.numeric_std.all;
use work.t48_pack.clk_active_c;
use work.t48_pack.res_active_c;
use work.t48_pack.bus_idle_level_c;
use work.t48_pack.to_stdLogic;
use work.t48_dmem_ctrl_pack.all;
architecture rtl of t48_dmem_ctrl is
signal dmem_addr_s,
dmem_addr_q : dmem_addr_t;
begin
-----------------------------------------------------------------------------
-- Process addr_decode
--
-- Purpose:
-- Decode/multiplex the address information for the Data Memory.
--
addr_decode: process (data_i,
addr_type_i,
bank_select_i,
dmem_addr_q)
variable stack_addr_v : unsigned(5 downto 0);
begin
-- default assignment
dmem_addr_s <= dmem_addr_q;
stack_addr_v := (others => '0');
case addr_type_i is
when DM_PLAIN =>
dmem_addr_s <= data_i;
when DM_REG =>
dmem_addr_s <= (others => '0');
dmem_addr_s(2 downto 0) <= data_i(2 downto 0);
-- implement bank switching
if bank_select_i = '1' then
-- dmem address 24 - 31: access proper set
dmem_addr_s(4 downto 3) <= "11";
end if;
when DM_STACK =>
-- build address from stack pointer
stack_addr_v(3 downto 1) := unsigned(data_i(2 downto 0));
-- dmem address 8 - 23
stack_addr_v := stack_addr_v + 8;
dmem_addr_s <= (others => '0');
dmem_addr_s(5 downto 0) <= std_logic_vector(stack_addr_v);
when DM_STACK_HIGH =>
dmem_addr_s(0) <= '1';
when others =>
-- do nothing
-- pragma translate_off
assert false
report "Unknown address type identification for Data Memory controller!"
severity error;
-- pragma translate_on
end case;
end process addr_decode;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process dmem_addr_reg
--
-- Purpose:
-- Implements the Data Memory Address Register.
-- This register is required to hold the address during a write operation
-- as we cannot hold the address in the input register of the
-- synchronous RAM (no clock suppression/gating).
--
-- NOTE: May be obsoleted by clock enable feature of generic RTL RAM.
--
dmem_addr_reg: process (res_i, clk_i)
begin
if res_i = res_active_c then
dmem_addr_q <= (others => '0');
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
if write_dmem_addr_i then
dmem_addr_q <= dmem_addr_s;
end if;
end if;
end if;
end process dmem_addr_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping.
-----------------------------------------------------------------------------
dmem_addr_o <= dmem_addr_s
when write_dmem_addr_i and en_clk_i else
dmem_addr_q;
-- data from bus is fed through
dmem_data_o <= data_i;
-- data to bus is enabled upon read request
data_o <= dmem_data_i
when read_dmem_i else
(others => bus_idle_level_c);
-- write enable to Data Memory is fed through
dmem_we_o <= to_stdLogic(write_dmem_i);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2005/06/11 10:08:43 arniml
-- introduce prefix 't48_' for all packages, entities and configurations
--
-- Revision 1.3 2004/04/24 23:44:25 arniml
-- move from std_logic_arith to numeric_std
--
-- Revision 1.2 2004/04/18 18:58:29 arniml
-- clean up sensitivity list
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
gpl-2.0
|
d4ab9637d8d3fe64035a46b45b495f78
| 0.547157 | 4.087302 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_decoder_GNEQGKKPXW.vhd
| 7 | 901 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNEQGKKPXW is
generic ( decode : string := "10";
pipeline : natural := 1;
width : natural := 2);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNEQGKKPXW is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 2,
decode => "10",
pipeline => 1)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture;
|
mit
|
df421072ac5469fc54cb2c7cbd111c0a
| 0.653718 | 2.963816 | false | false | false | false |
freecores/t48
|
rtl/vhdl/system/t8039.vhd
| 1 | 6,739 |
-------------------------------------------------------------------------------
--
-- T8039 Microcontroller System
--
-- $Id: t8039.vhd,v 1.7 2006-07-14 01:13:32 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t8039 is
port (
xtal_i : in std_logic;
reset_n_i : in std_logic;
t0_b : inout std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_b : inout std_logic_vector( 7 downto 0);
t1_i : in std_logic;
p2_b : inout std_logic_vector( 7 downto 0);
p1_b : inout std_logic_vector( 7 downto 0);
prog_n_o : out std_logic
);
end t8039;
use work.t48_system_comp_pack.t8039_notri;
architecture struct of t8039 is
signal t0_s : std_logic;
signal t0_dir_s : std_logic;
signal db_s : std_logic_vector( 7 downto 0);
signal db_dir_s : std_logic;
signal p2_s : std_logic_vector( 7 downto 0);
signal p2l_low_imp_s : std_logic;
signal p2h_low_imp_s : std_logic;
signal p1_s : std_logic_vector( 7 downto 0);
signal p1_low_imp_s : std_logic;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
t8039_notri_b : t8039_notri
generic map (
-- we don't need explicit gating of input ports
-- this is done implicitely by the bidirectional pads
gate_port_input_g => 0
)
port map (
xtal_i => xtal_i,
xtal_en_i => vdd_s,
reset_n_i => reset_n_i,
t0_i => t0_b,
t0_o => t0_s,
t0_dir_o => t0_dir_s,
int_n_i => int_n_i,
ea_i => ea_i,
rd_n_o => rd_n_o,
psen_n_o => psen_n_o,
wr_n_o => wr_n_o,
ale_o => ale_o,
db_i => db_b,
db_o => db_s,
db_dir_o => db_dir_s,
t1_i => t1_i,
p2_i => p2_b,
p2_o => p2_s,
p2l_low_imp_o => p2l_low_imp_s,
p2h_low_imp_o => p2h_low_imp_s,
p1_i => p1_b,
p1_o => p1_s,
p1_low_imp_o => p1_low_imp_s,
prog_n_o => prog_n_o
);
-----------------------------------------------------------------------------
-- Process bidirs
--
-- Purpose:
-- Assign bidirectional signals.
--
bidirs: process (t0_b, t0_s, t0_dir_s,
db_b, db_s, db_dir_s,
p1_b, p1_s, p1_low_imp_s,
p2_b, p2_s, p2l_low_imp_s, p2h_low_imp_s)
function port_bidir_f(port_value : in std_logic_vector;
low_imp : in std_logic) return std_logic_vector is
variable result_v : std_logic_vector(port_value'range);
begin
for idx in port_value'high downto port_value'low loop
if low_imp = '1' then
result_v(idx) := port_value(idx);
elsif port_value(idx) = '0' then
result_v(idx) := '0';
else
result_v(idx) := 'Z';
end if;
end loop;
return result_v;
end;
begin
-- Test 0 -----------------------------------------------------------------
if t0_dir_s = '1' then
t0_b <= t0_s;
else
t0_b <= 'Z';
end if;
-- Data Bus ---------------------------------------------------------------
if db_dir_s = '1' then
db_b <= db_s;
else
db_b <= (others => 'Z');
end if;
-- Port 1 -----------------------------------------------------------------
p1_b <= port_bidir_f(port_value => p1_s,
low_imp => p1_low_imp_s);
-- Port 2 -----------------------------------------------------------------
p2_b(3 downto 0) <= port_bidir_f(port_value => p2_s(3 downto 0),
low_imp => p2l_low_imp_s);
p2_b(7 downto 4) <= port_bidir_f(port_value => p2_s(7 downto 4),
low_imp => p2h_low_imp_s);
end process bidirs;
--
-----------------------------------------------------------------------------
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.6 2006/06/20 00:47:08 arniml
-- new input xtal_en_i
--
-- Revision 1.5 2005/11/02 23:41:43 arniml
-- properly drive P1 and P2 with low impedance markers
--
-- Revision 1.4 2005/11/01 21:37:45 arniml
-- wire signals for P2 low impedance marker issue
--
-- Revision 1.3 2004/12/03 19:43:12 arniml
-- added hierarchy t8039_notri
--
-------------------------------------------------------------------------------
|
gpl-2.0
|
3c1c8247ae0664975aa496a341fd8d2f
| 0.512984 | 3.537533 | false | false | false | false |
straywarrior/MadeCPUin21days
|
BubbleUnit.vhd
| 1 | 5,592 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 23:52:40 11/16/2015
-- Design Name:
-- Module Name: BubbleUnit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BubbleUnit is
Port ( RegOpA : in STD_LOGIC_VECTOR (3 downto 0);
RegOpB : in STD_LOGIC_VECTOR (3 downto 0);
RegWE_EXE : in STD_LOGIC;
RegDest_EXE : in STD_LOGIC_VECTOR (3 downto 0);
RegWE_MEM: in STD_LOGIC;
RegDest_MEM : in STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_EXE : in STD_LOGIC_VECTOR (3 downto 0);
MemRead_EXE : in STD_LOGIC;
MemWrite_EXE : in STD_LOGIC;
MemRead_MEM : in STD_LOGIC;
MemWrite_MEM : in STD_LOGIC;
MemAddr : in STD_LOGIC_VECTOR (15 downto 0);
pc_sel: in STD_LOGIC_VECTOR (1 downto 0);
CReg : in STD_LOGIC;
CRegA : in STD_LOGIC_VECTOR (3 downto 0);
CRegB : in STD_LOGIC_VECTOR (3 downto 0);
SerialFinish : in STD_LOGIC;
pc_stall : out STD_LOGIC;
InstAddrSel : out STD_LOGIC;
InstMemRead : out STD_LOGIC;
InstMemWrite : out STD_LOGIC;
Mem_Result_Sel : out STD_LOGIC;
IF_ID_stall : out STD_LOGIC;
ID_EXE_stall : out STD_LOGIC;
EXE_MEM_stall : out STD_LOGIC;
IF_ID_clear: out STD_LOGIC;
ID_EXE_clear : out STD_LOGIC;
EXE_MEM_clear: out STD_LOGIC
);
end BubbleUnit;
architecture Behavioral of BubbleUnit is
-- InstMem Collision, just like Data Memory Collision
signal InstMem_Collision_0 : STD_LOGIC := '0';
-- InstMem Collision control.
signal InstMem_Collision_1 : STD_LOGIC := '0';
-- Data Memory Collision: LW R0 R1, ADDU R1 R2 R3, R1 is in collision
signal DataMem_Collision_0 : STD_LOGIC := '0';
-- LW R0 R1, CMP R1 R2, R1 is in collision. Need 2 bubble
signal DataMem_Collision_1 : STD_LOGIC := '0';
--LW R0 R1, CMP R1 R2, R1 is in collision. Need 2 bubble
-- or CMP R1 R2 after another instruction after LW. Need 1 bubble
-- or AND R0 R2, B R0 imm. Need 1 bubble
signal DataMem_Collision_2 : STD_LOGIC := '0';
-- SW BF00 or LW BF00
signal DataMem_Collision_3 : STD_LOGIC := '0';
-- LW R3 R4 1
-- SW R3 R4 2
-- R4 is in collision
signal DataMem_Collision_4 : STD_LOGIC := '0';
begin
InstMem_Collision_0 <=
'1' when (MemAddr <= x"7FFF" and (MemRead_EXE = '1' or MemWrite_EXE = '1')) else
'0';
InstMem_Collision_1 <=
'1' when (MemAddr <= x"7FFF" and (MemRead_MEM = '1' or MemWrite_MEM = '1')) else
'0';
DataMem_Collision_0 <=
'1' when (MemRead_EXE = '1' and RegWE_EXE = '1' and (RegDest_EXE = RegOpA or RegDest_EXE = RegOpB) and RegDest_EXE /= "1111") else
'0';
DataMem_Collision_1 <=
'1' when (RegWE_EXE = '1' and (CReg = '1' and (RegDest_EXE = CRegA or RegDest_EXE = CRegB)) and RegDest_EXE /= "1111") else
'0';
DataMem_Collision_2 <=
'1' when (MemRead_MEM = '1' and RegWE_MEM = '1' and (CReg = '1' and (RegDest_MEM = CRegA or RegDest_MEM = CRegB)) and RegDest_EXE /= "1111") else
'0';
DataMem_Collision_3 <=
'1' when ((MemRead_MEM = '1' or MemWrite_MEM = '1') and MemAddr = x"BF00" and SerialFinish = '0') else
'0';
DataMem_Collision_4 <=
'1' when (MemRead_MEM = '1' and RegWE_MEM = '1' and MemWrite_EXE = '1' and RegMemDIn_EXE = RegDest_MEM) else
'0';
Mem_Result_Sel <=
'1' when (MemRead_MEM = '1' and MemAddr <= x"7FFF") else
'0' when (MemRead_MEM = '1' and MemAddr >= x"8000") else
'0';
IF_ID_clear <=
'1' when (pc_sel /= "00") else
'0';
IF_ID_stall <=
'1' when (InstMem_Collision_1 = '1' or DataMem_Collision_0 = '1'
or DataMem_Collision_1 = '1' or DataMem_Collision_2 = '1' or DataMem_Collision_3 = '1') else
'0';
pc_stall <=
'1' when (InstMem_Collision_1 = '1' or DataMem_Collision_0 = '1'
or DataMem_Collision_1 = '1' or DataMem_Collision_2 = '1' or DataMem_Collision_3 = '1') else
'0';
InstAddrSel <=
'1' when (InstMem_Collision_1 = '1') else
'0';
InstMemRead <=
MemRead_MEM when (InstMem_Collision_1 = '1') else
'1';
InstMemWrite <=
MemWrite_MEM when (InstMem_Collision_1 = '1') else
'0';
EXE_MEM_stall <=
'1' when (DataMem_Collision_3 = '1') else
'0';
ID_EXE_stall <=
'1' when (InstMem_Collision_1 = '1' or DataMem_Collision_3 = '1') else
'0';
ID_EXE_clear <=
'1' when (DataMem_Collision_0 = '1' or DataMem_Collision_1 = '1') else
'0';
EXE_MEM_clear <=
'1' when (InstMem_Collision_1 = '1') else
'0';
end Behavioral;
|
gpl-2.0
|
c079488c0473adf8139ff59ac84058d0
| 0.544886 | 3.484112 | false | false | false | false |
bobxiv/DispositivosLogicosProgramables-FICH
|
Proyecto 1 DLP TP Calculadora/Src/InputModule.vhd
| 1 | 6,462 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Emmanuel Rojas Fredini
--
-- Create Date: 17:28:27 10/08/2011
-- Design Name:
-- Module Name: CalculadoraFSM - CalculadoraStateMachineArchitecture
-- Project Name: Calculadora
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies: ArithmeticModule.vhdl, BCD2Binary.vhdl
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Descripcion:
--La calculadora recibe su entrada en forma serie, recibiendo cada uno de los
--datos en forma little endian. Recibe los datos en el siguiente orden:
-- 4 bits de un primer operando en formato bcd
-- 2 bits del codigo del operador segun especifica el modulo de aritmetica(ArithmeticModule)
-- 4 bits de un segundo operando en formato bcd
--Para volver a realizar otra operacion hay que enviar un reset a la calculadora ya que esta una vez
--que produce el resultado, esta se queda en un estado de espera infinito.
--
--El cambio de estado normal es sincronico pero el reset cambia el estado asincronicamente.
--El ouput de la calculadora antes de que se realize todo el input y luego la operacion aritmetica
--no esta establecido asi que no deberia tenerselo en cuenta.
entity CalculadoraFSM is
Port ( input : in std_logic;--Entrada seria a la calculadora(se estima sincronizada con el clock)
clock : in std_logic;--Clock de la maquina de estado finito
reset : in std_logic;--Reset asincronico de la calculadora
output : out std_logic_vector(15 downto 0));--resultado de la calculadora
end CalculadoraFSM;
architecture CalculadoraStateMachineArchitecture of CalculadoraFSM is
type estado is(LeerBit1Op1, LeerBit2Op1, LeerBit3Op1, LeerBit4Op1,
LeerOpCodeBit1, LeerOpCodeBit2,
LeerBit1Op2, LeerBit2Op2, LeerBit3Op2, LeerBit4Op2,
ConvertirBCD2Binario, Calcular, EsperarReset);
--Estado actual
signal estado_A: estado := LeerBit1Op1;
--Estado siguiente
signal estado_S: estado;
--Componente de aritmetica
COMPONENT ArithmeticModule
PORT(
A : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
Op : IN std_logic_vector(1 downto 0);
Res : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--ArithmeticModule Inputs
signal A : std_logic_vector(7 downto 0) := (others => '0');
signal B : std_logic_vector(7 downto 0) := (others => '0');
signal Op : std_logic_vector(1 downto 0) := (others => '0');
--ArithmeticModule Outputs
signal Res : std_logic_vector(15 downto 0);
--Componente de conversion de bcd a formato numerico binario
COMPONENT BCD2Binary
Port ( bcd : in STD_LOGIC_VECTOR(3 downto 0);
binary : out STD_LOGIC_VECTOR(7 downto 0));
END COMPONENT;
--BCD2Binary 1 Inputs
signal bcd1 : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
--BCD2Binary 1 Outputs
signal binary1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
--BCD2Binary 2 Inputs
signal bcd2 : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
--BCD2Binary 2 Outputs
signal binary2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
--Almacena la entrada a la calculadora
--No es totalmente necesario porque se podria cargar directamente en bcd1, bcd2 y Op
--pero cargarlo en este buffer hace que el proceso parezca mas secuencial y entendible
signal bufferEntrada : STD_LOGIC_VECTOR(9 downto 0);
begin
-- Instanciamos el Modulo de Aritmetica(AM)
am: ArithmeticModule PORT MAP (
A => A,
B => B,
Op => Op,
Res => output
--Res => Res
);
-- Instanciamos el Conversor de BCD a binario 1(bcd2binario1)
bcd2binario1: BCD2Binary PORT MAP (
bcd => bcd1,
binary => binary1
);
-- Instanciamos el Conversor de BCD a binario 2(bcd2binario2)
bcd2binario2: BCD2Binary PORT MAP (
bcd => bcd2,
binary => binary2
);
--Proceso del siguiente estado de la maquina de estado finito
SiguienteEstado: process(estado_A, input)
begin
case estado_A is
--Estados de lectura de la entrada a la calculadora
when LeerBit1Op1 =>
bufferEntrada(0) <= input;
estado_S <= LeerBit2Op1;
when LeerBit2Op1 =>
bufferEntrada(1) <= input;
estado_S <= LeerBit3Op1;
when LeerBit3Op1 =>
bufferEntrada(2) <= input;
estado_S <= LeerBit4Op1;
when LeerBit4Op1 =>
bufferEntrada(3) <= input;
estado_S <= LeerOpCodeBit1;
when LeerOpCodeBit1 =>
bufferEntrada(4) <= input;
estado_S <= LeerOpCodeBit2;
when LeerOpCodeBit2 =>
bufferEntrada(5) <= input;
estado_S <= LeerBit1Op2;
when LeerBit1Op2 =>
bufferEntrada(6) <= input;
estado_S <= LeerBit2Op2;
when LeerBit2Op2 =>
bufferEntrada(7) <= input;
estado_S <= LeerBit3Op2;
when LeerBit3Op2 =>
bufferEntrada(8) <= input;
estado_S <= LeerBit4Op2;
when LeerBit4Op2 =>
bufferEntrada(9) <= input;
estado_S <= ConvertirBCD2Binario;
--Conversion de los operandos de formato bcd a binario
when ConvertirBCD2Binario =>--Convierte los valores numericos de bcd a formato binario
bcd1 <= bufferEntrada(3 downto 0);
bcd2 <= bufferEntrada(9 downto 6);
estado_S <= Calcular;
--Calculo de la operacion
when Calcular =>--Realiza los calculos usanod el modulo de aritmetica
A <= binary1;
OP <= bufferEntrada(5 downto 4);
B <= binary2;
estado_S <= EsperarReset;
--Espera que se resetee la calculadora para hacer otro calculo
when EsperarReset =>
estado_S <= EsperarReset;--seguimos hasta que halla un reset en este estado
end case;
end process SiguienteEstado;
--Proceso de cambio de estado de la maquina de estado finito
CambioEstadoSincronico: process
begin
wait until reset='1' or rising_edge(clock);
if reset='1' then
estado_A <= LeerBit1Op1;--resetea la maquina de estado finito
else
estado_A <= estado_S;--actualiza el estado actual al estado siguiente
end if;
end process CambioEstadoSincronico;
end CalculadoraStateMachineArchitecture;
|
gpl-3.0
|
9488d8844536d6465d8d0fdc23f24777
| 0.655525 | 3.634421 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
16x004-00_src/Source/pcie_x1_sim.vhd
| 1 | 13,038 |
-------------------------------------------------------------------------------
-- Title : PCIe simulation model
-- Project : 16z091-
-------------------------------------------------------------------------------
-- File : pcie_x1_sim.vhd
-- Author : [email protected]
-- Organization: MEN Mikro Elektronik GmbH
-- Created : 2012-10-02
-------------------------------------------------------------------------------
-- Simulator :
-- Synthesis :
-------------------------------------------------------------------------------
-- Description :
-- PCIe simulation model for x1 configuration
-------------------------------------------------------------------------------
-- Hierarchy :
--
-------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.utils_pkg.all;
use work.print_pkg.all;
use work.pcie_x1_pkg.all;
use work.terminal_pkg.all;
library pciebfm_lib;
use pciebfm_lib.pkg_plda_fio.all;
use pciebfm_lib.pkg_xbfm.all;
entity pcie_x1_sim is
generic(
INSTANCE_NBR : integer range 3 downto 0 := 0; -- nbr of BFM instance
BFM_IO_SIZE : integer range 24 downto 12 := 16; -- 12 <= x <= 24
BFM_MEM32_SIZE : integer range 24 downto 12 := 16; -- 12 <= x <= 24
BFM_MEM64_SIZE : integer range 24 downto 12 := 16 -- 12 <= x <= 24
);
port(
clk : in std_logic;
rst : in std_logic;
-- BFM signals
clk125 : in std_logic;
clk250 : in std_logic;
rstn : in std_logic;
bfm_tx_0 : in std_logic;
bfm_rx_0 : out std_logic;
term_out : in terminal_out_type;
term_in : out terminal_in_type
);
end entity pcie_x1_sim;
architecture pcie_x1_sim_arch of pcie_x1_sim is
begin
print_s_i("DEBUG(1): BFM_IO_SIZE = ", BFM_IO_SIZE);
assert BFM_IO_SIZE >= 12 report "ERROR (pcie_x1_sim): value for generic BFM_IO_SIZE is too small" severity failure;
assert BFM_IO_SIZE <= 24 report "ERROR (pcie_x1_sim): value for generic BFM_IO_SIZE is too big" severity failure;
assert BFM_MEM32_SIZE >= 12 report "ERROR (pcie_x1_sim): value for generic BFM_MEM32_SIZE is too small" severity failure;
assert BFM_MEM32_SIZE <= 24 report "ERROR (pcie_x1_sim): value for generic BFM_MEM32_SIZE is too big" severity failure;
assert BFM_MEM64_SIZE >= 12 report "ERROR (pcie_x1_sim): value for generic BFM_MEM64_SIZE is too small" severity failure;
assert BFM_MEM64_SIZE <= 24 report "ERROR (pcie_x1_sim): value for generic BFM_MEM64_SIZE is too big" severity failure;
bfm_inst : entity pciebfm_lib.pldawrap_link
generic map (
BFM_ID => INSTANCE_NBR,
BFM_TYPE => '0',
BFM_LANES => 1,
BFM_WIDTH => 1,
IO_SIZE => BFM_IO_SIZE,
MEM32_SIZE => BFM_MEM32_SIZE,
MEM64_SIZE => BFM_MEM64_SIZE
)
port map (
clk125 => clk125,
clk250 => clk250,
rstn => rstn,
tx_rate => open,
tx_in0(0) => bfm_tx_0,
tx_in1(0) => '0',
tx_in2(0) => '0',
tx_in3(0) => '0',
tx_in4(0) => '0',
tx_in5(0) => '0',
tx_in6(0) => '0',
tx_in7(0) => '0',
tx_val => x"00", -- unused in serial mode (BFM_WIDTH = 1)
rx_out0(0) => bfm_rx_0,
rx_val => open, -- unused in serial mode (BFM_WIDTH = 1)
chk_txval => open,
chk_txdata => open,
chk_txdatak => open,
chk_rxval => open,
chk_rxdata => open,
chk_rxdatak => open,
chk_ltssm => open
);
main : process
variable first_be_en : std_logic_vector(3 downto 0);
variable byte_count : integer;
variable addr32_int : std_logic_vector(31 downto 0);
variable bfm_id : integer := 0;
variable success_int : boolean := false;
variable return_data32 : std_logic_vector(31 downto 0) := (others => '0');
variable return_data_vec : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable data_vec : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable temp_inst_nbr : std_logic_vector(1 downto 0);
begin
-- reset all
term_in.busy <= '1';
term_in.done <= true;
wait until rst = '0';
wait_clk(clk,1);
if term_out.start /= true then
wait until term_out.start = true;
end if;
loop
wait on term_out.start;
term_in.busy <= '1';
---------------------------
-- check for wrong values
---------------------------
temp_inst_nbr := std_logic_vector(to_unsigned(INSTANCE_NBR,2));
if temp_inst_nbr /= term_out.tga(3 downto 2) then
assert false report "ERROR (pcie_x1_sim): instance number in term_out.tga(3 downto 2) does not match INSTANCE_NBR for this component" severity failure;
end if;
assert term_out.typ <= 2 report "ERROR (pcie_x1_sim): illegal value for signal term_out.typ" severity failure;
assert term_out.wr <= 2 report "ERROR (pcie_x1_sim): illegal value for signal term_out.wr" severity failure;
if term_out.typ = 0 then
assert term_out.numb = 1 report "ERROR (pcie_x1_sim): illegal combination for signals term_out.typ and term_out.numb => bytewise burst is impossible" severity failure;
end if;
if term_out.typ = 1 then
assert term_out.numb = 1 report "ERROR (pcie_x1_sim): illegal combination for signals term_out.typ and term_out.numb => wordwise burst is impossible" severity failure;
end if;
assert term_out.numb <= 1024 report "ERROR (pcie_x1_sim): maximum value for signal term_out.numb is 1024" severity failure;
----------------------------
-- set values for this run
----------------------------
addr32_int := term_out.adr(31 downto 2) & "00";
byte_count := term_out.numb *4;
bfm_id := to_integer(unsigned(term_out.tga(3 downto 2)));
if term_out.typ = 0 then -- byte
if term_out.adr(1 downto 0) = "01" then
first_be_en := "0010";
elsif term_out.adr(1 downto 0) = "10" then
first_be_en := "0100";
elsif term_out.adr(1 downto 0) = "11" then
first_be_en := "1000";
else
first_be_en := "0001";
end if;
elsif term_out.typ = 1 then -- word
if term_out.adr(1) = '0' then
first_be_en := "0011";
else
first_be_en := "1100";
end if;
else -- long word
first_be_en := x"F";
end if;
for i in 0 to term_out.numb -1 loop
data_vec(i) := std_logic_vector(unsigned(term_out.dat) + to_unsigned(i,32));
return_data_vec(i) := (others => '0');
wait for 0 ns;
end loop;
if term_out.wr = 0 then -- read
if term_out.tga(1 downto 0) = IO_TRANSFER then -- I/O
bfm_rd_io(
bfm_inst_nbr => bfm_id,
byte_en => first_be_en,
pcie_addr => addr32_int(31 downto 2),
ref_data32 => term_out.dat,
wait_end => true,
data32_out => return_data32,
success => success_int
);
elsif term_out.tga(1 downto 0) = MEM32_TRANSFER then -- memory
if term_out.numb = 1 then
bfm_rd_mem32(
bfm_inst_nbr => bfm_id,
byte_en => first_be_en,
pcie_addr => addr32_int(31 downto 2),
ref_data32 => term_out.dat,
wait_end => true,
data32_out => return_data32,
success => success_int
);
else
bfm_rd_mem32(
bfm_inst_nbr => bfm_id,
byte_count => byte_count,
pcie_addr => addr32_int,
ref_data32 => data_vec,
t_class => "000",
attributes => "00",
wait_end => true,
data32_out => return_data_vec,
success => success_int
);
end if;
elsif term_out.tga(1 downto 0) = CONFIG_TRANSFER then -- configuration type 0
bfm_rd_config(
bfm_inst_nbr => bfm_id,
byte_en => first_be_en,
pcie_addr => addr32_int(31 downto 2),
ref_data32 => term_out.dat,
wait_end => true,
data32_out => return_data32,
success => success_int
);
else
assert false report "ERROR (pcie_x1_sim): term_out.tga(1 downto 0) = 11 is reserved" severity failure;
end if;
elsif term_out.wr = 1 then -- write
if term_out.tga(1 downto 0) = IO_TRANSFER then -- I/O
bfm_wr_io(
bfm_inst_nbr => bfm_id,
byte_en => first_be_en,
pcie_addr => addr32_int(31 downto 2),
data32 => term_out.dat,
wait_end => true,
success => success_int
);
elsif term_out.tga(1 downto 0) = MEM32_TRANSFER then -- memory
if term_out.numb = 1 then
bfm_wr_mem32(
bfm_inst_nbr => bfm_id,
byte_en => first_be_en,
pcie_addr => addr32_int,
data32 => term_out.dat,
wait_end => true,
success => success_int
);
else
bfm_wr_mem32(
bfm_inst_nbr => bfm_id,
byte_count => byte_count,
pcie_addr => addr32_int,
data32 => data_vec,
t_class => "000",
attributes => "00",
wait_end => true,
success => success_int
);
end if;
elsif term_out.tga(1 downto 0) = CONFIG_TRANSFER then -- configuration type 0
bfm_wr_config(
bfm_inst_nbr => bfm_id,
byte_en => first_be_en,
pcie_addr => addr32_int(31 downto 2),
data32 => term_out.dat,
wait_end => true,
success => success_int
);
else
assert false report "ERROR (pcie_x1_sim): term_out.tga(1 downto 0) = 11 is reserved" severity failure;
end if;
else -- wait
wait_clk(clk,term_out.numb);
end if;
--------------------------------------
-- return values and finish transfer
--------------------------------------
term_in.dat <= return_data32;
if success_int then
term_in.err <= 0;
else
term_in.err <= 1;
end if;
term_in.busy <= '0';
term_in.done <= term_out.start;
end loop;
end process main;
end architecture pcie_x1_sim_arch;
|
gpl-3.0
|
c5ecdb2df59a8dd4d1a1d0ce51172154
| 0.451373 | 4.127255 | false | false | false | false |
jandecaluwe/myhdl
|
example/manual/pck_myhdl_10.vhd
| 6 | 4,346 |
-- File: pck_myhdl_10.vhd
-- Generated by MyHDL 1.0dev
-- Date: Thu Jun 23 19:06:43 2016
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_10 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_logic;
function to_unsigned (arg: boolean; size: natural) return unsigned;
function to_signed (arg: boolean; size: natural) return signed;
function to_integer(arg: boolean) return integer;
function to_integer(arg: std_logic) return integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned;
function to_signed (arg: std_logic; size: natural) return signed;
function bool (arg: std_logic) return boolean;
function bool (arg: unsigned) return boolean;
function bool (arg: signed) return boolean;
function bool (arg: integer) return boolean;
function "-" (arg: unsigned) return signed;
function tern_op(cond: boolean; if_true: std_logic; if_false: std_logic) return std_logic;
function tern_op(cond: boolean; if_true: unsigned; if_false: unsigned) return unsigned;
function tern_op(cond: boolean; if_true: signed; if_false: signed) return signed;
end pck_myhdl_10;
package body pck_myhdl_10 is
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
function tern_op(cond: boolean; if_true: std_logic; if_false: std_logic) return std_logic is
begin
if cond then
return if_true;
else
return if_false;
end if;
end function tern_op;
function tern_op(cond: boolean; if_true: unsigned; if_false: unsigned) return unsigned is
begin
if cond then
return if_true;
else
return if_false;
end if;
end function tern_op;
function tern_op(cond: boolean; if_true: signed; if_false: signed) return signed is
begin
if cond then
return if_true;
else
return if_false;
end if;
end function tern_op;
end pck_myhdl_10;
|
lgpl-2.1
|
4cfe4bd5ec0a2144ea6b363f2f6b1dbc
| 0.602623 | 3.987156 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GNTS3MQUMJ.vhd
| 4 | 877 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNTS3MQUMJ is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNTS3MQUMJ is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 12 + 1 ,
width_inr=> 4,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(15 downto 0) => input,
xin(16) => '0', yout => output
);
end architecture;
|
mit
|
4fa86e1110429c52b8e753a81d6e0647
| 0.648803 | 3.088028 | false | false | false | false |
straywarrior/MadeCPUin21days
|
CPU_TOP.vhd
| 1 | 31,745 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 20:37:26 11/15/2015
-- Design Name:
-- Module Name: CPU_TOP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.Vcomponents.all;
entity CPU_TOP is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
RAM1ADDR : out STD_LOGIC_VECTOR (17 downto 0);
RAM1DATA : inout STD_LOGIC_VECTOR (15 downto 0);
RAM1EN : out STD_LOGIC;
RAM1OE : out STD_LOGIC;
RAM1RW : out STD_LOGIC;
RAM2ADDR : out STD_LOGIC_VECTOR (17 downto 0);
RAM2DATA : inout STD_LOGIC_VECTOR (15 downto 0);
RAM2EN : out STD_LOGIC;
RAM2OE : out STD_LOGIC;
RAM2RW : out STD_LOGIC;
-- Serial Port
SERIAL_DATA_READY : in STD_LOGIC;
SERIAL_RDN : out STD_LOGIC;
SERIAL_TBRE : in STD_LOGIC;
SERIAL_TSRE : in STD_LOGIC;
SERIAL_WRN : out STD_LOGIC;
-- For Debug
LED : out STD_LOGIC_VECTOR (15 downto 0);
SW : in STD_LOGIC_VECTOR (15 downto 0);
DLED_RIGHT : out STD_LOGIC_VECTOR (6 downto 0)
);
end CPU_TOP;
architecture Behavioral of CPU_TOP is
-- Universal component
component ClockDiv
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_2t : out STD_LOGIC;
clk_4t : out STD_LOGIC
);
end component;
signal clock_2t : STD_LOGIC;
signal clock_4t : STD_LOGIC;
component TwoInMuxer_16bit
Port ( input1 : in STD_LOGIC_VECTOR (15 downto 0);
input2 : in STD_LOGIC_VECTOR (15 downto 0);
opcode : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component FourInMuxer_16bit
Port ( input1 : in STD_LOGIC_VECTOR (15 downto 0);
input2 : in STD_LOGIC_VECTOR (15 downto 0);
input3 : in STD_LOGIC_VECTOR (15 downto 0);
input4 : in STD_LOGIC_VECTOR (15 downto 0);
opcode : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component BubbleUnit
Port ( RegOpA : in STD_LOGIC_VECTOR (3 downto 0);
RegOpB : in STD_LOGIC_VECTOR (3 downto 0);
RegWE_EXE : in STD_LOGIC;
RegDest_EXE : in STD_LOGIC_VECTOR (3 downto 0);
RegWE_MEM: in STD_LOGIC;
RegDest_MEM : in STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_EXE : in STD_LOGIC_VECTOR (3 downto 0);
MemRead_EXE : in STD_LOGIC;
MemWrite_EXE : in STD_LOGIC;
MemRead_MEM : in STD_LOGIC;
MemWrite_MEM : in STD_LOGIC;
MemAddr : in STD_LOGIC_VECTOR (15 downto 0);
pc_sel: in STD_LOGIC_VECTOR (1 downto 0);
CReg : in STD_LOGIC;
CRegA : in STD_LOGIC_VECTOR (3 downto 0);
CRegB : in STD_LOGIC_VECTOR (3 downto 0);
SerialFinish : in STD_LOGIC;
pc_stall : out STD_LOGIC;
InstAddrSel : out STD_LOGIC;
InstMemRead : out STD_LOGIC;
InstMemWrite : out STD_LOGIC;
Mem_Result_Sel : out STD_LOGIC;
IF_ID_stall : out STD_LOGIC;
ID_EXE_stall : out STD_LOGIC;
EXE_MEM_stall : out STD_LOGIC;
IF_ID_clear: out STD_LOGIC;
ID_EXE_clear : out STD_LOGIC;
EXE_MEM_clear: out STD_LOGIC
);
end component;
signal IF_ID_REG_STALL : STD_LOGIC;
signal IF_ID_REG_CLEAR : STD_LOGIC;
signal ID_EXE_REG_STALL : STD_LOGIC;
signal ID_EXE_REG_CLEAR : STD_LOGIC;
signal EXE_MEM_REG_STALL : STD_LOGIC;
signal EXE_MEM_REG_CLEAR : STD_LOGIC;
component ForwardingUnit
Port ( RegOpA : in STD_LOGIC_VECTOR (3 downto 0);
RegOpB : in STD_LOGIC_VECTOR (3 downto 0);
RegWE_MEM: in STD_LOGIC;
RegDest_MEM : in STD_LOGIC_VECTOR (3 downto 0);
RegWE_WB : in STD_LOGIC;
RegDest_WB : STD_LOGIC_VECTOR (3 downto 0);
MemRead_EXE : in STD_LOGIC;
MemRead_WB : in STD_LOGIC;
CReg : in STD_LOGIC;
CRegA : in STD_LOGIC_VECTOR (3 downto 0);
CRegB : in STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_EXE : in STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_MEM : in STD_LOGIC_VECTOR (3 downto 0);
RegAValSel : out STD_LOGIC;
RegBValSel : out STD_LOGIC;
RegRAValSel : out STD_LOGIC;
OperandASel : out STD_LOGIC_VECTOR (1 downto 0);
OperandBSel : out STD_LOGIC_VECTOR (1 downto 0);
MemDInSel_EXE : out STD_LOGIC_VECTOR (1 downto 0);
MemDInSel_MEM : out STD_LOGIC
);
end component;
-- IF Section
component PC_REG
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
stall : in STD_LOGIC;
PC_in : in STD_LOGIC_VECTOR (15 downto 0);
PC_out : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component PCAdder
Port ( A : in STD_LOGIC_VECTOR (15 downto 0);
B : in STD_LOGIC_VECTOR (15 downto 0);
result : out STD_LOGIC_VECTOR (15 downto 0));
end component;
COMPONENT InstMemoryControl
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
MemRead : in STD_LOGIC;
MemWrite: in STD_LOGIC;
MemAddr : in STD_LOGIC_VECTOR (15 downto 0);
MemData : in STD_LOGIC_VECTOR (15 downto 0);
MemOut : out STD_LOGIC_VECTOR (15 downto 0);
RAM2Addr : out STD_LOGIC_VECTOR (17 downto 0);
RAM2Data : inout STD_LOGIC_VECTOR (15 downto 0);
RAM2EN : out STD_LOGIC;
RAM2OE : out STD_LOGIC;
RAM2RW : out STD_LOGIC
);
end COMPONENT;
component IF_ID_REG
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
pc_in : in STD_LOGIC_VECTOR (15 downto 0);
inst_in : in STD_LOGIC_VECTOR (15 downto 0);
stall : in STD_LOGIC;
clear : in STD_LOGIC;
pc_out : out STD_LOGIC_VECTOR (15 downto 0);
inst_out : out STD_LOGIC_VECTOR (15 downto 0);
rx : out STD_LOGIC_VECTOR (3 downto 0);
ry : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
-- PC Register
signal PC_REG_IN : STD_LOGIC_VECTOR (15 downto 0);
signal PC_REG_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal PC_REG_STALL : STD_LOGIC;
-- Instruction Selector
signal INST_ADDR_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal INST_ADDR_SEL : STD_LOGIC;
-- Instruction Memory
signal INST_MEM_READ : STD_LOGIC;
signal INST_MEM_WRITE : STD_LOGIC;
signal INST_MEM_OUT : STD_LOGIC_VECTOR (15 downto 0);
-- PC Incr & PC Selector
signal PC_INCR_OUT : STD_LOGIC_VECTOR (15 downto 0);
-- signal PC_JUMP : STD_LOGIC_VECTOR (15 downto 0);
-- signal PC_SEL : STD_LOGIC_VECTOR (1 downto 0);
signal PC_INCR : STD_LOGIC_VECTOR (15 downto 0) := ( 0 => '1', others => '0');
-- IF/ID Register
-- ID Section
COMPONENT InstDecoder
PORT(
pc : IN std_logic_vector(15 downto 0);
inst : IN std_logic_vector(15 downto 0);
RegAVal : IN std_logic_vector(15 downto 0);
RegBVal : IN std_logic_vector(15 downto 0);
RAVal : IN std_logic_vector(15 downto 0);
SPVal : IN std_logic_vector(15 downto 0);
IHVal : IN std_logic_vector(15 downto 0);
pc_imm : OUT std_logic_vector(15 downto 0);
pc_sel : OUT std_logic_vector(1 downto 0);
T_in : in STD_LOGIC;
T_out : out STD_LOGIC;
CReg : OUT std_logic;
CRegA : OUT std_logic_vector(3 downto 0);
CRegB : OUT std_logic_vector(3 downto 0);
RegWE : OUT std_logic;
RegDest : OUT std_logic_vector(3 downto 0);
MemRd : OUT std_logic;
MemDIn : OUT std_logic_vector(15 downto 0);
RegMemDIn : out STD_LOGIC_VECTOR (3 downto 0);
MemWE : OUT std_logic;
opcode : OUT std_logic_vector(3 downto 0);
RegOpA : OUT std_logic_vector(3 downto 0);
RegOpB : OUT std_logic_vector(3 downto 0);
operandA : OUT std_logic_vector(15 downto 0);
operandB : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT T_REG
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
T_in : in STD_LOGIC;
T_out : out STD_LOGIC
);
END COMPONENT;
COMPONENT Register_Files
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
ASel : in STD_LOGIC_VECTOR (3 downto 0);
BSel : in STD_LOGIC_VECTOR (3 downto 0);
WSel : in STD_LOGIC_VECTOR (3 downto 0);
WE : in STD_LOGIC;
WVal : in STD_LOGIC_VECTOR (15 downto 0);
AVal : out STD_LOGIC_VECTOR (15 downto 0);
BVal : out STD_LOGIC_VECTOR (15 downto 0);
RAVal : out STD_LOGIC_VECTOR (15 downto 0);
SPVal : out STD_LOGIC_VECTOR (15 downto 0);
IHVal : out STD_LOGIC_VECTOR (15 downto 0)
);
end COMPONENT;
COMPONENT ID_EXE_REG
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clear : in STD_LOGIC;
stall : in STD_LOGIC;
RegWE_in : in STD_LOGIC;
RegDest_in : in STD_LOGIC_VECTOR (3 downto 0);
MemRd_in : in STD_LOGIC;
MemWE_in : in STD_LOGIC;
MemDIn_in : in STD_LOGIC_VECTOR (15 downto 0);
opcode_in : in STD_LOGIC_VECTOR (3 downto 0);
operandA_in : in STD_LOGIC_VECTOR (15 downto 0);
operandB_in : in STD_LOGIC_VECTOR (15 downto 0);
RegOpA_in : in STD_LOGIC_VECTOR (3 downto 0);
RegOpB_in : in STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_in : in STD_LOGIC_VECTOR (3 downto 0);
RegWE_out : out STD_LOGIC;
RegDest_out : out STD_LOGIC_VECTOR (3 downto 0);
MemRd_out : out STD_LOGIC;
MemWE_out : out STD_LOGIC;
MemDIn_out : out STD_LOGIC_VECTOR (15 downto 0);
opcode_out : out STD_LOGIC_VECTOR (3 downto 0);
operandA_out : out STD_LOGIC_VECTOR (15 downto 0);
operandB_out : out STD_LOGIC_VECTOR (15 downto 0);
RegOpA_out : out STD_LOGIC_VECTOR (3 downto 0);
RegOpB_out : out STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_out : out STD_LOGIC_VECTOR (3 downto 0)
);
end COMPONENT;
-- IF/ID Register Out
signal IF_ID_PC : STD_LOGIC_VECTOR (15 downto 0);
signal IF_ID_INST : STD_LOGIC_VECTOR (15 downto 0);
signal IF_ID_REGX : STD_LOGIC_VECTOR (3 downto 0);
signal IF_ID_REGY : STD_LOGIC_VECTOR (3 downto 0);
-- T Register & Instruction Decoder
signal T_REG_OUT : STD_LOGIC;
signal T_REG_IN : STD_LOGIC;
signal Decoder_PC_Imm: STD_LOGIC_VECTOR (15 downto 0);
signal Decoder_PC_Sel : STD_LOGIC_VECTOR (1 downto 0);
signal Decoder_RegDest : STD_LOGIC_VECTOR (3 downto 0);
signal Decoder_RegWrite : STD_LOGIC;
signal Decoder_MemRead : STD_LOGIC;
signal Decoder_MemDIn : STD_LOGIC_VECTOR (15 downto 0);
signal Decoder_RegMemDIn : STD_LOGIC_VECTOR (3 downto 0);
signal Decoder_MemWrite : STD_LOGIC;
signal Decoder_OpCode : STD_LOGIC_VECTOR (3 downto 0);
signal Decoder_OperandA : STD_LOGIC_VECTOR (15 downto 0);
signal Decoder_OperandB : STD_LOGIC_VECTOR (15 downto 0);
signal Decoder_RegOpA : STD_LOGIC_VECTOR (3 downto 0);
signal Decoder_RegOpB : STD_LOGIC_VECTOR (3 downto 0);
signal Decoder_CReg : STD_LOGIC;
signal Decoder_CRegA : STD_LOGIC_VECTOR (3 downto 0);
signal Decoder_CRegB : STD_LOGIC_VECTOR (3 downto 0);
-- Register Files
signal Regs_RegAVal : STD_LOGIC_VECTOR (15 downto 0);
signal Regs_RegBVal : STD_LOGIC_VECTOR (15 downto 0);
signal Regs_RAVal : STD_LOGIC_VECTOR (15 downto 0);
signal Regs_SPVal : STD_LOGIC_VECTOR (15 downto 0);
signal Regs_IHVal : STD_LOGIC_VECTOR (15 downto 0);
-- PC Adder
signal PC_JUMP_ADDR : STD_LOGIC_VECTOR (15 downto 0);
-- EXE Section
COMPONENT ALU
Port ( op : in STD_LOGIC_VECTOR (3 downto 0);
A : in STD_LOGIC_VECTOR (15 downto 0);
B : in STD_LOGIC_VECTOR (15 downto 0);
result : out STD_LOGIC_VECTOR (15 downto 0));
end COMPONENT;
COMPONENT EXE_MEM_REG
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clear : in STD_LOGIC;
stall : in STD_LOGIC;
RegWE_in : in STD_LOGIC;
RegDest_in : in STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_in : in STD_LOGIC_VECTOR (3 downto 0);
MemRd_in : in STD_LOGIC;
MemWE_in : in STD_LOGIC;
MemDIn_in : in STD_LOGIC_VECTOR (15 downto 0);
ALUout_in : in STD_LOGIC_VECTOR (15 downto 0);
RegWE_out : out STD_LOGIC;
RegDest_out : out STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_out : out STD_LOGIC_VECTOR (3 downto 0);
MemRd_out : out STD_LOGIC;
MemWE_out : out STD_LOGIC;
MemDIn_out : out STD_LOGIC_VECTOR (15 downto 0);
ALUout_out : out STD_LOGIC_VECTOR (15 downto 0)
);
end COMPONENT;
-- ID/EXE Register
signal ID_EXE_RegWrite : STD_LOGIC;
signal ID_EXE_RegDest : STD_LOGIC_VECTOR (3 downto 0);
signal ID_EXE_MemRead : STD_LOGIC;
signal ID_EXE_MemDIn : STD_LOGIC_VECTOR (15 downto 0);
signal ID_EXE_MemWrite : STD_LOGIC;
signal ID_EXE_RegMemDIn : STD_LOGIC_VECTOR (3 downto 0);
signal ID_EXE_OpCode : STD_LOGIC_VECTOR (3 downto 0);
signal ID_EXE_OperandA : STD_LOGIC_VECTOR (15 downto 0);
signal ID_EXE_OperandB : STD_LOGIC_VECTOR (15 downto 0);
signal ID_EXE_RegOpA : STD_LOGIC_VECTOR (3 downto 0);
signal ID_EXE_RegOpB : STD_LOGIC_VECTOR (3 downto 0);
-- Operand A Selector
signal OpA_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
-- Operand B Selector
signal OpB_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
-- ALU
signal ALU_RESULT : STD_LOGIC_VECTOR (15 downto 0);
-- EXE/MEM Register
signal MemDIn_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
-- Forwarding Unit
signal OpA_MUX_SEL : STD_LOGIC_VECTOR (1 downto 0);
signal OpB_MUX_SEL : STD_LOGIC_VECTOR (1 downto 0);
signal RegRA_MUX_SEL : STD_LOGIC;
signal RegAVal_MUX_SEL : STD_LOGIC;
signal RegBVal_MUX_SEL : STD_LOGIC;
signal EXE_MemDIn_MUX_SEL : STD_LOGIC_VECTOR (1 downto 0);
signal MEM_MemDIn_MUX_SEL : STD_LOGIC;
signal RegAVal_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal RegBVal_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal RegRA_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
-- MEM Section
COMPONENT DataMemoryControl
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
MemRead : in STD_LOGIC;
MemWrite: in STD_LOGIC;
MemAddr : in STD_LOGIC_VECTOR (15 downto 0);
MemData : in STD_LOGIC_VECTOR (15 downto 0);
MemOut : out STD_LOGIC_VECTOR (15 downto 0);
SerialFinish : out STD_LOGIC;
RAM1Addr : out STD_LOGIC_VECTOR (17 downto 0);
RAM1Data : inout STD_LOGIC_VECTOR (15 downto 0);
RAM1EN : out STD_LOGIC;
RAM1OE : out STD_LOGIC;
RAM1RW : out STD_LOGIC;
Serial_dataready : in STD_LOGIC;
Serial_rdn : out STD_LOGIC;
Serial_tbre : in STD_LOGIC;
Serial_tsre : in STD_LOGIC;
Serial_wrn : out STD_LOGIC;
DLED_Right : out STD_LOGIC_VECTOR (6 downto 0)
);
end COMPONENT;
COMPONENT MEM_WB_REG is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
RegWE_in : in STD_LOGIC;
RegDest_in : in STD_LOGIC_VECTOR (3 downto 0);
RegWriteVal_in : in STD_LOGIC_VECTOR (15 downto 0);
MemRd_in : in STD_LOGIC;
RegWE_out : out STD_LOGIC;
RegDest_out : out STD_LOGIC_VECTOR (3 downto 0);
RegWriteVal_out : out STD_LOGIC_VECTOR (15 downto 0);
MemRd_out : out STD_LOGIC
);
end COMPONENT;
-- EXE/MEM Register
signal EXE_MEM_RegWrite : STD_LOGIC;
signal EXE_MEM_RegDest : STD_LOGIC_VECTOR (3 downto 0);
signal EXE_MEM_RegMemDIn : STD_LOGIC_VECTOR (3 downto 0);
signal EXE_MEM_MemRead : STD_LOGIC;
signal EXE_MEM_MemDIn : STD_LOGIC_VECTOR (15 downto 0);
signal EXE_MEM_MemWrite : STD_LOGIC;
signal EXE_MEM_ALUOUT : STD_LOGIC_VECTOR (15 downto 0);
-- Data Memory & Serial Port
signal MEM_MemDIn_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal DATA_MEM_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal DATA_MEM_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal MEM_RESULT_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal MEM_RESULT_SEL : STD_LOGIC;
signal DATA_MEM_SERIAL_FINISH : STD_LOGIC;
-- WB Section
-- MEM/WB Register
signal MEM_WB_RegWrite : STD_LOGIC;
signal MEM_WB_RegDest : STD_LOGIC_VECTOR (3 downto 0);
signal MEM_WB_RegWriteVal : STD_LOGIC_VECTOR (15 downto 0);
signal MEM_WB_MemRead : STD_LOGIC;
begin
-- Universal
--LED <= ALU_RESULT;
LED <=
PC_REG_OUT when (SW = "0000000000000000") else
INST_ADDR_OUT when (SW = "0000000000000001") else
INST_MEM_OUT when (SW = "0000000000000010") else
Decoder_PC_Imm when (SW = "0000000000000011") else
PC_JUMP_ADDR when (SW = "0000000000000100") else
PC_REG_IN when (SW = "0000000000000101") else
IF_ID_PC when (SW = "0000000000010000") else
IF_ID_INST when (SW = "0000000000010001") else
"00000000" & IF_ID_REGX & IF_ID_REGY when (SW = "0000000000011001") else
(PC_REG_STALL & INST_ADDR_SEL & IF_ID_REG_STALL & IF_ID_REG_CLEAR
& ID_EXE_REG_STALL & ID_EXE_REG_CLEAR
& EXE_MEM_REG_STALL & EXE_MEM_REG_CLEAR & "00000000") when (SW = "0000000000011011") else
Decoder_OperandA when (SW = "0000000000010010") else
Decoder_OperandB when (SW = "0000000000010011") else
Decoder_RegOpA & Decoder_RegOpB & Decoder_CRegA & Decoder_CRegB when (SW = "0000000000010111") else
Decoder_RegDest & Decoder_RegWrite & Decoder_CReg & Decoder_MemRead & Decoder_MemWrite
& Decoder_PC_Sel & RegAVal_MUX_SEL & RegBVal_MUX_SEL & "0000" when (SW = "0000000000010110") else
RegAVal_MUX_OUT when (SW = "0000000000011110") else
RegBVal_MUX_OUT when (SW = "0000000000011100") else
ALU_RESULT when (SW = "0000000000100000") else
OpA_MUX_SEL & OpB_MUX_SEL & EXE_MemDIn_MUX_SEL & ID_EXE_RegOpA & ID_EXE_RegOpB & "00" when (SW = "0000000000100001") else
ID_EXE_OpCode & ID_EXE_MemRead & ID_EXE_MemWrite & ID_EXE_RegWrite & ID_EXE_RegDest & "00000" when (SW = "0000000000100011") else
ID_EXE_MemDIn when (SW = "0000000000100111") else
ID_EXE_RegMemDIn & "000000000000" when (SW = "0000000000100110") else
EXE_MEM_RegWrite & EXE_MEM_RegDest & EXE_MEM_MemRead & EXE_MEM_MemWrite
& SERIAL_DATA_READY & SERIAL_TBRE & SERIAL_TSRE & DATA_MEM_SERIAL_FINISH & "00000" when (SW = "0000000001000001") else
DATA_MEM_OUT when (SW = "0000000001000011") else
DATA_MEM_MUX_OUT when (SW = "0000000001000010") else
MEM_MemDIn_MUX_OUT when (SW = "0000000001000111") else
MEM_WB_RegWriteVal when (SW = "0000000010000000") else
MEM_WB_RegDest & MEM_WB_RegWrite & "00000000000" when (SW = "0000000010000001") else
(others => '0');
ClockDiv_0 : ClockDiv PORT MAP (
clk => clock,
reset => reset,
clk_2t => clock_2t,
clk_4t => clock_4t
);
BubbleUnit_0 : BubbleUnit PORT MAP (
RegOpA => Decoder_RegOpA,
RegOpB => Decoder_RegOpB,
RegWE_EXE => ID_EXE_RegWrite,
RegDest_EXE => ID_EXE_RegDest,
RegWE_MEM=> EXE_MEM_RegWrite,
RegDest_MEM => EXE_MEM_RegDest,
RegMemDIn_EXE => ID_EXE_RegMemDIn,
MemRead_EXE => ID_EXE_MemRead,
MemWrite_EXE => ID_EXE_MemWrite,
MemRead_MEM => EXE_MEM_MemRead,
MemWrite_MEM => EXE_MEM_MemWrite,
MemAddr => EXE_MEM_ALUOUT,
pc_sel=> Decoder_PC_Sel,
CReg => Decoder_CReg,
CRegA => Decoder_CRegA,
CRegB => Decoder_CRegB,
SerialFinish => DATA_MEM_SERIAL_FINISH,
pc_stall => PC_REG_STALL,
InstAddrSel => INST_ADDR_SEL,
InstMemRead => INST_MEM_READ,
InstMemWrite => INST_MEM_WRITE,
Mem_Result_Sel => MEM_RESULT_SEL,
IF_ID_stall => IF_ID_REG_STALL,
ID_EXE_stall => ID_EXE_REG_STALL,
EXE_MEM_stall => EXE_MEM_REG_STALL,
IF_ID_clear => IF_ID_REG_CLEAR,
ID_EXE_clear => ID_EXE_REG_CLEAR,
EXE_MEM_clear => EXE_MEM_REG_CLEAR
);
-- IF Section
PC_REG_0 : PC_REG PORT MAP (
clk => clock_4t,
reset => reset,
stall => PC_REG_STALL,
PC_in => PC_REG_IN,
PC_out => PC_REG_OUT
);
INST_ADDR_MUX : TwoInMuxer_16bit PORT MAP (
input1 => PC_REG_OUT,
input2 => EXE_MEM_ALUOUT,
opcode => INST_ADDR_SEL,
output => INST_ADDR_OUT
);
INST_MEMORY_0 : InstMemoryControl PORT MAP (
clk => clock,
reset => reset,
MemRead => INST_MEM_READ,
MemWrite => INST_MEM_WRITE,
MemAddr => INST_ADDR_OUT,
MemData => MEM_MemDIn_MUX_OUT,
MemOut => INST_MEM_OUT,
RAM2Addr => RAM2ADDR,
RAM2Data => RAM2DATA,
RAM2EN => RAM2EN,
RAM2OE => RAM2OE,
RAM2RW => RAM2RW
);
PCAdder_0 : PCAdder PORT MAP (
A => PC_REG_OUT,
B => PC_INCR,
result => PC_INCR_OUT
);
PC_REG_MUX : FourInMuxer_16bit PORT MAP (
input1 => PC_INCR_OUT,
input2 => Regs_RAVal,
input3 => Regs_RegAVal,
input4 => PC_JUMP_ADDR,
opcode => Decoder_PC_Sel,
output => PC_REG_IN
);
IF_ID_REG_0 : IF_ID_REG PORT MAP (
clk => clock_4t,
reset => reset,
pc_in => PC_INCR_OUT,
inst_in => INST_MEM_OUT,
stall => IF_ID_REG_STALL,
clear => IF_ID_REG_CLEAR,
pc_out => IF_ID_PC,
inst_out => IF_ID_INST,
rx => IF_ID_REGX,
ry => IF_ID_REGY
);
-- ID Section
PCAdder_1 : PCAdder PORT MAP (
A => IF_ID_PC,
B => Decoder_PC_Imm,
result => PC_JUMP_ADDR
);
InstDecoder_0 : InstDecoder PORT MAP (
pc => IF_ID_PC,
inst => IF_ID_INST,
RegAVal => RegAVal_MUX_OUT,
RegBVal => RegBVal_MUX_OUT,
RAVal => RegRA_MUX_OUT,
SPVal => Regs_SPVal,
IHVal => Regs_IHVal,
T_in => T_REG_OUT,
T_out => T_REG_IN,
pc_imm => Decoder_PC_Imm,
pc_sel => Decoder_PC_Sel,
RegWE => Decoder_RegWrite,
RegDest => Decoder_RegDest,
MemRd => Decoder_MemRead,
MemDIn => Decoder_MemDIn,
RegMemDIn => Decoder_RegMemDIn,
MemWE => Decoder_MemWrite,
opcode => Decoder_OpCode,
RegOpA => Decoder_RegOpA,
RegOpB => Decoder_RegOpB,
CReg => Decoder_CReg,
CRegA => Decoder_CRegA,
CRegB => Decoder_CRegB,
operandA => Decoder_OperandA,
operandB => Decoder_OperandB
);
Register_Files_0 : Register_Files PORT MAP (
clk => clock,
reset => reset,
ASel => IF_ID_REGX,
BSel => IF_ID_REGY,
WSel => MEM_WB_RegDest,
WE => MEM_WB_RegWrite,
WVal => MEM_WB_RegWriteVal,
AVal => Regs_RegAVal,
BVal => Regs_RegBVal,
RAVal => Regs_RAVal,
SPVal => Regs_SPVal,
IHVal => Regs_IHVal
);
T_REG_0 : T_REG PORT MAP (
clk => clock,
reset => reset,
T_in => T_REG_IN,
T_out => T_REG_OUT
);
ID_EXE_REG_0 : ID_EXE_REG PORT MAP (
clk => clock_4t,
reset => reset,
clear => ID_EXE_REG_CLEAR,
stall => ID_EXE_REG_STALL,
RegWE_in => Decoder_RegWrite,
RegDest_in => Decoder_RegDest,
RegMemDIn_in => Decoder_RegMemDIn,
MemRd_in => Decoder_MemRead,
MemWE_in => Decoder_MemWrite,
MemDIn_in => Decoder_MemDIn,
opcode_in => Decoder_OpCode,
operandA_in => Decoder_OperandA,
operandB_in => Decoder_OperandB,
RegOpA_in => Decoder_RegOpA,
RegOpB_in => Decoder_RegOpB,
RegWE_out => ID_EXE_RegWrite,
RegDest_out => ID_EXE_RegDest,
RegMemDIn_out => ID_EXE_RegMemDIn,
MemRd_out => ID_EXE_MemRead,
MemWE_out => ID_EXE_MemWrite,
MemDIn_out => ID_EXE_MemDIn,
opcode_out => ID_EXE_OpCode,
operandA_out => ID_EXE_OperandA,
operandB_out => ID_EXE_OperandB,
RegOpA_out => ID_EXE_RegOpA,
RegOpB_out => ID_EXE_RegOpB
);
RegAVal_MUX : TwoInMuxer_16bit PORT MAP (
input1 => Regs_RegAVal,
input2 => EXE_MEM_ALUOUT,
opcode => RegAVal_MUX_SEL,
output => RegAVal_MUX_OUT
);
RegBVal_MUX : TwoInMuxer_16bit PORT MAP (
input1 => Regs_RegBVal,
input2 => EXE_MEM_ALUOUT,
opcode => RegBVal_MUX_SEL,
output => RegBVal_MUX_OUT
);
RegRA_MUX : TwoInMuxer_16bit PORT MAP (
input1 => Regs_RAVal,
input2 => EXE_MEM_ALUOUT,
opcode => RegRA_MUX_SEL,
output => RegRA_MUX_OUT
);
-- EXE Section
ALU_0 : ALU PORT MAP (
op => ID_EXE_OpCode,
A => OpA_MUX_OUT,
B => OpB_MUX_OUT,
result => ALU_RESULT
);
OpA_MUX : FourInMuxer_16bit PORT MAP (
input1 => ID_EXE_OperandA,
input2 => EXE_MEM_ALUOUT,
input3 => MEM_WB_RegWriteVal,
input4 => "0000000000000000",
opcode => OpA_MUX_SEL,
output => OpA_MUX_OUT
);
OpB_MUX : FourInMuxer_16bit PORT MAP (
input1 => ID_EXE_OperandB,
input2 => EXE_MEM_ALUOUT,
input3 => MEM_WB_RegWriteVal,
input4 => "0000000000000000",
opcode => OpB_MUX_SEL,
output => OpB_MUX_OUT
);
MemDIn_MUX : FourInMuxer_16bit PORT MAP (
input1 => ID_EXE_MemDIn,
input2 => EXE_MEM_ALUOUT,
input3 => MEM_WB_RegWriteVal,
input4 => "0000000000000000",
opcode => EXE_MemDIn_MUX_SEL,
output => MemDIn_MUX_OUT
);
EXE_MEM_REG_0 : EXE_MEM_REG PORT MAP (
clk => clock_4t,
reset => reset,
clear => EXE_MEM_REG_CLEAR,
stall => EXE_MEM_REG_STALL,
RegWE_in => ID_EXE_RegWrite,
RegDest_in => ID_EXE_RegDest,
RegMemDIn_in => ID_EXE_RegMemDIn,
MemRd_in => ID_EXE_MemRead,
MemWE_in => ID_EXE_MemWrite,
MemDIn_in => MemDIn_MUX_OUT,
ALUout_in => ALU_RESULT,
RegWE_out => EXE_MEM_RegWrite,
RegDest_out => EXE_MEM_RegDest,
RegMemDIn_out => EXE_MEM_RegMemDIn,
MemRd_out => EXE_MEM_MemRead,
MemWE_out => EXE_MEM_MemWrite,
MemDIn_out => EXE_MEM_MemDIn,
ALUout_out => EXE_MEM_ALUOUT
);
ForwardingUnit_0 : ForwardingUnit PORT MAP (
RegOpA => ID_EXE_RegOpA,
RegOpB => ID_EXE_RegOpB,
RegWE_WB => MEM_WB_RegWrite,
RegDest_WB => MEM_WB_RegDest,
RegWE_MEM => EXE_MEM_RegWrite,
RegDest_MEM => EXE_MEM_RegDest,
MemRead_EXE => ID_EXE_MemRead,
MemRead_WB => MEM_WB_MemRead,
CReg => Decoder_CReg,
CRegA => Decoder_CRegA,
CRegB => Decoder_CRegB,
RegMemDIn_EXE => ID_EXE_RegMemDIn,
RegMemDIn_MEM => EXE_MEM_RegMemDIn,
RegAValSel => RegAVal_MUX_SEL,
RegBValSel => RegBVal_MUX_SEL,
RegRAValSel => RegRA_MUX_SEL,
OperandASel => OpA_MUX_SEL,
OperandBSel => OpB_MUX_SEL,
MemDInSel_EXE => EXE_MemDIn_MUX_SEL,
MemDInSel_MEM => MEM_MemDIn_MUX_SEL
);
-- MEM Section
DATA_MEMORY_0 : DataMemoryControl PORT MAP (
clk => clock,
reset => reset,
MemRead => EXE_MEM_MemRead,
MemWrite=> EXE_MEM_MemWrite,
MemAddr => EXE_MEM_ALUOUT,
MemData => MEM_MemDIn_MUX_OUT,
MemOut => DATA_MEM_OUT,
SerialFinish => DATA_MEM_SERIAL_FINISH,
RAM1Addr => RAM1ADDR,
RAM1Data => RAM1DATA,
RAM1EN => RAM1EN,
RAM1OE => RAM1OE,
RAM1RW => RAM1RW,
Serial_dataready => SERIAL_DATA_READY,
Serial_rdn => SERIAL_RDN,
Serial_tbre => SERIAL_TBRE,
Serial_tsre => SERIAL_TSRE,
Serial_wrn => SERIAL_WRN,
DLED_Right => DLED_RIGHT
);
MEM_MemDIn_MUX : TwoInMuxer_16bit PORT MAP (
input1 => EXE_MEM_MemDIn,
input2 => MEM_WB_RegWriteVal,
opcode => MEM_MemDIn_MUX_SEL,
output => MEM_MemDIn_MUX_OUT
);
MEM_MUX : TwoInMuxer_16bit PORT MAP (
input1 => DATA_MEM_OUT,
input2 => INST_MEM_OUT,
opcode => MEM_RESULT_SEL,
output => DATA_MEM_MUX_OUT
);
MEM_RESULT_MUX : TwoInMuxer_16bit PORT MAP (
input1 => EXE_MEM_ALUOUT,
input2 => DATA_MEM_MUX_OUT,
opcode => EXE_MEM_MemRead,
output => MEM_RESULT_MUX_OUT
);
MEM_WB_REG_0 : MEM_WB_REG PORT MAP (
clk => clock_4t,
reset => reset,
RegWE_in => EXE_MEM_RegWrite,
RegDest_in => EXE_MEM_RegDest,
RegWriteVal_in => MEM_RESULT_MUX_OUT,
MemRd_in => EXE_MEM_MemRead,
RegWE_out => MEM_WB_RegWrite,
RegDest_out => MEM_WB_RegDest,
RegWriteVal_out => MEM_WB_RegWriteVal,
MemRd_out => MEM_WB_MemRead
);
-- WB Section
end Behavioral;
|
gpl-2.0
|
a2e8722eed5d460212c93bfd20333091
| 0.545031 | 3.77019 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_sdecoderaltr.vhd
| 17 | 2,703 |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
mit
|
4eb8bca2f619bfd411de4679ab6e3936
| 0.647799 | 3.647773 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/ama_scanchain/_primary.vhd
| 5 | 2,723 |
library verilog;
use verilog.vl_types.all;
entity ama_scanchain is
generic(
width_scanin : integer := 1;
width_scanchain : integer := 1;
input_register_clock_0: string := "UNREGISTERED";
input_register_aclr_0: string := "NONE";
input_register_clock_1: string := "UNREGISTERED";
input_register_aclr_1: string := "NONE";
input_register_clock_2: string := "UNREGISTERED";
input_register_aclr_2: string := "NONE";
input_register_clock_3: string := "UNREGISTERED";
input_register_aclr_3: string := "NONE";
scanchain_register_clock: string := "UNREGISTERED";
scanchain_register_aclr: string := "NONE";
port_sign : string := "PORT_UNUSED";
number_of_multipliers: integer := 1;
width_scanin_msb: vl_notype;
width_scanchain_msb: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
sign : in vl_logic;
scanin : in vl_logic_vector;
data_out_0 : out vl_logic_vector;
data_out_1 : out vl_logic_vector;
data_out_2 : out vl_logic_vector;
data_out_3 : out vl_logic_vector;
scanout : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_scanin : constant is 1;
attribute mti_svvh_generic_type of width_scanchain : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_0 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_0 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_1 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_1 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_2 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_2 : constant is 1;
attribute mti_svvh_generic_type of input_register_clock_3 : constant is 1;
attribute mti_svvh_generic_type of input_register_aclr_3 : constant is 1;
attribute mti_svvh_generic_type of scanchain_register_clock : constant is 1;
attribute mti_svvh_generic_type of scanchain_register_aclr : constant is 1;
attribute mti_svvh_generic_type of port_sign : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of width_scanin_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanchain_msb : constant is 3;
end ama_scanchain;
|
mit
|
1d1d525c334d2a98f88728d3c650cc0a
| 0.636063 | 3.67973 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_updt_mngr.vhd
| 1 | 20,774 |
-------------------------------------------------------------------------------
-- axi_sg_updt_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_mngr.vhd
-- Description: This entity manages updating of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0
-- Starting update word offset
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
--
-- Channel 1 Control and Status --
ch1_updt_queue_empty : in std_logic ; --
ch1_updt_curdesc_wren : in std_logic ; --
ch1_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_ioc : in std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_active : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr : in std_logic ; --
ch1_dma_slverr : in std_logic ; --
ch1_dma_decerr : in std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
ch1_updt_done : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_updt_queue_empty : in std_logic ; --
ch2_updt_curdesc_wren : in std_logic ; --
ch2_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_ioc : in std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_active : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr : in std_logic ; --
ch2_dma_slverr : in std_logic ; --
ch2_dma_decerr : in std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
ch2_updt_done : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
s2mm_err : in std_logic ; --
--
ftch_error : in std_logic ; --
updt_error : out std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_updt_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_cmnd_wr : std_logic := '0';
signal updt_cmnd_data : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH
+CMD_BASE_WIDTH)-1 downto 0)
:= (others => '0');
signal updt_done : std_logic := '0';
signal updt_error_i : std_logic := '0';
signal updt_interr : std_logic := '0';
signal updt_slverr : std_logic := '0';
signal updt_decerr : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_error <= updt_error_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
I_UPDT_SG : entity axi_vdma_v6_2.axi_sg_updt_sm
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
ftch_error => ftch_error ,
-- Channel 1 Control and Status
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_idle => ch1_updt_idle ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set ,
ch1_dma_slverr_set => ch1_dma_slverr_set ,
ch1_dma_decerr_set => ch1_dma_decerr_set ,
ch1_updt_interr_set => ch1_updt_interr_set ,
ch1_updt_slverr_set => ch1_updt_slverr_set ,
ch1_updt_decerr_set => ch1_updt_decerr_set ,
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_done => ch1_updt_done ,
-- Channel 2 Control and Status
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_active => ch2_updt_active ,
ch2_updt_idle => ch2_updt_idle ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_dma_interr_set => ch2_dma_interr_set ,
ch2_dma_slverr_set => ch2_dma_slverr_set ,
ch2_dma_decerr_set => ch2_dma_decerr_set ,
ch2_updt_interr_set => ch2_updt_interr_set ,
ch2_updt_slverr_set => ch2_updt_slverr_set ,
ch2_updt_decerr_set => ch2_updt_decerr_set ,
ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_done => ch2_updt_done ,
-- DataMover Command
updt_cmnd_wr => updt_cmnd_wr ,
updt_cmnd_data => updt_cmnd_data ,
-- DataMover Status
updt_done => updt_done ,
updt_error => updt_error_i ,
updt_interr => updt_interr ,
updt_slverr => updt_slverr ,
updt_decerr => updt_decerr ,
updt_error_addr => updt_error_addr
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Command / Status Interface
-------------------------------------------------------------------------------
I_UPDT_CMDSTS_IF : entity axi_vdma_v6_2.axi_sg_updt_cmdsts_if
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from fetch sm
updt_cmnd_wr => updt_cmnd_wr ,
updt_cmnd_data => updt_cmnd_data ,
-- User Command Interface Ports (AXI Stream)
s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_updt_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_updt_sts_tready => m_axis_updt_sts_tready ,
m_axis_updt_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep ,
-- Scatter Gather Fetch Status
s2mm_err => s2mm_err ,
updt_done => updt_done ,
updt_error => updt_error_i ,
updt_interr => updt_interr ,
updt_slverr => updt_slverr ,
updt_decerr => updt_decerr
);
end implementation;
|
gpl-2.0
|
a174b6a87c552fd90ade5ba29fd78a70
| 0.362472 | 4.956812 | false | false | false | false |
Bourgeoisie/ECE368-RISC16
|
368RISC/ipcore_dir/instruct_blk_mem_gen_v7_3/simulation/instruct_blk_mem_gen_v7_3_tb.vhd
| 1 | 4,619 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: instruct_blk_mem_gen_v7_3_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY instruct_blk_mem_gen_v7_3_tb IS
END ENTITY;
ARCHITECTURE instruct_blk_mem_gen_v7_3_tb_ARCH OF instruct_blk_mem_gen_v7_3_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
instruct_blk_mem_gen_v7_3_synth_inst:ENTITY work.instruct_blk_mem_gen_v7_3_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
mit
|
32dcdbd9132628601db54f1bc69c3a28
| 0.618532 | 4.43708 | false | false | false | false |
Raane/Term-Assigment-TFE4140-mod-anal-dig-sys
|
Project/liaison/src/TestBench/ecc_TB.vhd
| 1 | 3,083 |
library ieee;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity ecc_tb is
end ecc_tb;
architecture TB_ARCHITECTURE of ecc_tb is
-- Component declaration of the tested unit
component ecc
port(
voted_data_out : in STD_LOGIC_VECTOR(7 downto 0);
status_out : in STD_LOGIC_VECTOR(2 downto 0);
ECC_signal : out STD_LOGIC_VECTOR(3 downto 0) );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal voted_data_out : STD_LOGIC_VECTOR(7 downto 0);
signal status_out : STD_LOGIC_VECTOR(2 downto 0);
-- Observed signals - signals mapped to the output ports of tested entity
signal ECC_signal : STD_LOGIC_VECTOR(3 downto 0);
-- Add your code here ...
begin
-- Unit Under Test port map
UUT : ecc
port map (
voted_data_out => voted_data_out,
status_out => status_out,
ECC_signal => ECC_signal
);
-- Add aliases for easiers treatment of data
--alias a is voted_data_out(0);
--alias b is voted_data_out(1);
--alias c is voted_data_out(2);
--alias d is voted_data_out(3);
--alias e is voted_data_out(4);
--alias f is voted_data_out(5);
--alias g is voted_data_out(6);
--alias h is voted_data_out(7);
--alias i is status_out(0);
--alias j is status_out(1);
--alias k is status_out(2);
--
--begin
-- 0 1 1 0 0 0 0 0
-- ECC_signal(0) <= a xor b xor d xor e xor g xor i xor k; --parity1
-- 0 0 1 1 0 1 0 1
-- ECC_signal(1) <= a xor c xor d xor f xor g xor j xor k; --parity2
-- 1 0 1 1 0 1 0 0
-- ECC_signal(2) <= b xor c xor d xor h xor i xor j xor k; --parity3
-- 0 1 0 1 0 1 0 1
-- ECC_signal(3) <= e xor f xor g xor h xor i xor j xor k; --parity4
process is
begin
-- Expected values:
-- ECC_signal(0) = 0 xor 0 xor 0 xor 0 xor 0 xor 0 xor 0 = 0
-- ECC_signal(1) = 0 xor 0 xor 0 xor 0 xor 0 xor 0 xor 0 = 0
-- ECC_signal(2) = 0 xor 0 xor 0 xor 0 xor 0 xor 0 xor 0 = 0
-- ECC_signal(3) = 0 xor 0 xor 0 xor 0 xor 0 xor 0 xor 0 = 0
voted_data_out <= "00000000";
status_out <= "000";
wait for 10 ns;
-- Expected values:
-- ECC_signal(0) = 1 xor 1 xor 1 xor 1 xor 1 xor 1 xor 1 = 1
-- ECC_signal(1) = 1 xor 1 xor 1 xor 1 xor 1 xor 1 xor 1 = 1
-- ECC_signal(2) = 1 xor 1 xor 1 xor 1 xor 1 xor 1 xor 1 = 1
-- ECC_signal(3) = 1 xor 1 xor 1 xor 1 xor 1 xor 1 xor 1 = 1
voted_data_out <= "11111111";
status_out <= "111";
wait for 10 ns;
-- Expected values:
-- ECC_signal(0) = 0 xor 1 xor 1 xor 0 xor 0 xor 0 xor 0 = 0
-- ECC_signal(0) = 0 xor 0 xor 1 xor 1 xor 0 xor 1 xor 0 = 1
-- ECC_signal(0) = 1 xor 0 xor 1 xor 1 xor 0 xor 1 xor 0 = 0
-- ECC_signal(0) = 0 xor 1 xor 0 xor 1 xor 0 xor 1 xor 0 = 1
voted_data_out <= "10101010";
status_out <= "010";
wait for 10 ns;
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_ecc of ecc_tb is
for TB_ARCHITECTURE
for UUT : ecc
use entity work.ecc(ecc);
end for;
end for;
end TESTBENCH_FOR_ecc;
|
apache-2.0
|
12907463668c19d2c3a2c91546652334
| 0.605579 | 2.818099 | false | true | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GN5VN2FCXZ.vhd
| 4 | 876 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN5VN2FCXZ is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN5VN2FCXZ is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 8 + 1 ,
width_inr=> 8,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(15 downto 0) => input,
xin(16) => '0', yout => output
);
end architecture;
|
mit
|
1c2586f59ad41cfaeb76f1115aeca919
| 0.648402 | 3.041667 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_testbench_capture_GNQX2JTRTZ.vhd
| 20 | 1,755 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
generic ( XFILE : string := "default";
DSPBTYPE : string := "");
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
function str(sl: std_logic) return character is
variable c: character;
begin
case sl is
when '0' => c := '0';
when '1' => c := '1';
when others => c := 'X';
end case;
return c;
end str;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := str(slv(i));
r := r + 1;
end loop;
return result;
end str;
procedure write_type_header(file f:text) is
use STD.textio.all;
variable my_line : line;
begin
write ( my_line, DSPBTYPE);
writeline ( f, my_line );
end procedure write_type_header ;
file oFile : text open write_mode is XFILE;
Begin
-- data capture
-- write type information to output file
write_type_header(oFile);
-- Writing Output Signal into file
Output:process(clock)
variable traceline : line ;
begin
if (aclr ='1') then
-- do not record
elsif clock'event and clock='1' then
write(traceline, str(input),justified=>left);
writeline(oFile,traceline);
end if ;
end process ;
end architecture;
|
mit
|
48e6c7c66c6ef52fbceab2155ebffade
| 0.62792 | 3.349237 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_divider.vhd
| 2 | 1,872 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_divider is
generic (
SIGNED : natural := 0;
WIDTH : natural := 8;
PIPELINE : natural := 0
);
port (
user_aclr : in std_logic;
denom : in std_logic_vector(width-1 downto 0);
quotient : out std_logic_vector(width-1 downto 0);
remain : out std_logic_vector(width-1 downto 0);
numer : in std_logic_vector(width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_divider;
architecture rtl of alt_dspbuilder_divider is
component alt_dspbuilder_divider_GNKAPZN5MO is
generic (
SIGNED : natural := 0;
WIDTH : natural := 24;
PIPELINE : natural := 0
);
port (
aclr : in std_logic;
clock : in std_logic;
denom : in std_logic_vector(24-1 downto 0);
ena : in std_logic;
numer : in std_logic_vector(24-1 downto 0);
quotient : out std_logic_vector(24-1 downto 0);
remain : out std_logic_vector(24-1 downto 0);
user_aclr : in std_logic
);
end component alt_dspbuilder_divider_GNKAPZN5MO;
begin
alt_dspbuilder_divider_GNKAPZN5MO_0: if ((SIGNED = 0) and (WIDTH = 24) and (PIPELINE = 0)) generate
inst_alt_dspbuilder_divider_GNKAPZN5MO_0: alt_dspbuilder_divider_GNKAPZN5MO
generic map(SIGNED => 0, WIDTH => 24, PIPELINE => 0)
port map(aclr => aclr, clock => clock, denom => denom, ena => ena, numer => numer, quotient => quotient, remain => remain, user_aclr => user_aclr);
end generate;
assert not (((SIGNED = 0) and (WIDTH = 24) and (PIPELINE = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
66a634dc73b133cbf5c8fef5ab00d108
| 0.697115 | 3.210978 | false | false | false | false |
Bourgeoisie/ECE368-RISC16
|
368RISC/Modules/UMDRISC_pkg.vhd
| 1 | 266 |
package UMDRISC_PKG is
CONSTANT DATA_WIDTH:INTEGER := 16;
CONSTANT ADDRESS_WIDTH:INTEGER := 16;
CONSTANT PC_WIDTH:INTEGER := 16;
CONSTANT BITREG_16:INTEGER := 16;
CONSTANT BITREG_5:INTEGER := 5;
end UMDRISC_PKG;
package body UMDRISC_PKG is
end UMDRISC_PKG;
|
mit
|
90d19eb27b48e954f22b97bb3272631d
| 0.733083 | 2.923077 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GNLHWQIRQK.vhd
| 4 | 871 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNLHWQIRQK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(2 downto 0);
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNLHWQIRQK is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 3 + 1 ,
width_inr=> 0,
width_outl=> 3,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(2 downto 0) => input,
xin(3) => '0', yout => output
);
end architecture;
|
mit
|
fdf5d1e7f867b57756487e7637e99fea
| 0.646383 | 3.05614 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GNMMXHT3UH.vhd
| 4 | 852 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNMMXHT3UH is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(3 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNMMXHT3UH is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 4 ,
width_inr=> 0,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(3 downto 0) => input,
yout => output
);
end architecture;
|
mit
|
64a8e1263650e358d045b33d24553ad7
| 0.656103 | 3.132353 | false | false | false | false |
Bourgeoisie/ECE368-RISC16
|
368RISC/ipcore_dir/tmp/_cg/Instruct_Memory/example_design/Instruct_Memory_exdes.vhd
| 2 | 5,014 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruct_Memory_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Instruct_Memory_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END Instruct_Memory_exdes;
ARCHITECTURE xilinx OF Instruct_Memory_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT Instruct_Memory IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : Instruct_Memory
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
mit
|
885a9262074bb03d848cda86315a35dd
| 0.561029 | 4.668529 | false | false | false | false |
freecores/t48
|
syn/t8048/jopcyc/t48_rom.vhd
| 2 | 885 |
-- This file was generated with hex2rom written by Daniel Wallner
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity rom_t48 is
port(
Clk : in std_logic;
A : in std_logic_vector(9 downto 0);
D : out std_logic_vector(7 downto 0)
);
end rom_t48;
architecture rtl of rom_t48 is
signal A_r : std_logic_vector(9 downto 0);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
A_r <= A;
end if;
end process;
process (A_r)
begin
case to_integer(unsigned(A_r)) is
when 000000 => D <= "00100011"; -- 0x0000
when 000001 => D <= "11111111"; -- 0x0001
when 000002 => D <= "00111001"; -- 0x0002
when 000003 => D <= "11010011"; -- 0x0003
when 000004 => D <= "00000001"; -- 0x0004
when 000005 => D <= "00000100"; -- 0x0005
when 000006 => D <= "00000010"; -- 0x0006
when others => D <= "--------";
end case;
end process;
end;
|
gpl-2.0
|
9b58b218f34f7c16f6506f54ccde3b33
| 0.628249 | 2.673716 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_sImpulse1nAltr.vhd
| 8 | 2,837 |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulse1nAltr is
generic (
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulse1nAltr ;
architecture syn of alt_dspbuilder_sImpulse1nAltr is
type States_ImpulseAltr is (sclear, shigh,slowend);
signal current_state : States_ImpulseAltr;
signal next_state : States_ImpulseAltr;
signal count : std_logic_vector(ToNatural(nbitnecessary(Impulsewidth)-1) downto 0);
begin
rp:process(clock,aclr)
begin
if aclr='1' then
current_state <= sclear;
count <= (others=>'0');
elsif clock'event and clock='1' then
if (sclr='1') then
current_state <= sclear;
count <= (others=>'0');
elsif (ena='1') then
current_state <= next_state;
count <= count+int2ustd(1,nbitnecessary(Impulsewidth));
end if;
end if;
end process;
cp:process(count,current_state, sclr,ena)
begin
case current_state is
when sclear =>
q <= '0';
if (ena='1') and (sclr='0') then
next_state <= shigh;
else
next_state <= sclear;
end if;
when shigh =>
q <= '1';
if (sclr='1') then
next_state <= sclear;
elsif (count=int2ustd(Impulsewidth,nbitnecessary(Impulsewidth))) and (ena='1') then
next_state <= slowend ;
else
next_state <= shigh;
end if;
when slowend =>
q <= '0';
if (sclr='1') then
next_state <= sclear;
else
next_state <= slowend ;
end if;
end case;
end process;
end syn;
|
mit
|
d97f37f9bf29b4c8e4355eca65249d9c
| 0.635178 | 3.757616 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
Testbench/vme_sim_pack.vhd
| 1 | 52,821 |
---------------------------------------------------------------
-- Title : vme Simulation Model Package
-- Project : none
---------------------------------------------------------------
-- File : vme_sim_pack.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 03/02/03
---------------------------------------------------------------
-- Simulator : Modelsim
-- Synthesis : no
---------------------------------------------------------------
-- Description :
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: vme_sim_pack.vhd,v $
-- Revision 1.2 2013/04/18 15:11:14 MMiehling
-- added vme_mstr_read64
--
-- Revision 1.1 2012/03/29 10:28:48 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee, std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.standard.ALL;
USE std.textio.all;
USE ieee.std_logic_textio.all;
USE work.print_pkg.all;
PACKAGE vme_sim_pack IS
--------------------------------TYPES-------------------------------------------
CONSTANT time_4 : time:= 35 ns;
CONSTANT time_5 : time:= 40 ns;
CONSTANT time_28 : time:= 30 ns;
CONSTANT time_27 : time:= 25 ns;
CONSTANT time_26 : time:= 5 ns; -- usually 0ns
CONSTANT time_19 : time:= 40 ns;
CONSTANT time_8 : time:= 35 ns;
CONSTANT time_12 : time:= 35 ns;
CONSTANT time_23 : time:= 10 ns;
CONSTANT time_11 : time:= 40 ns;
CONSTANT sl_base_A16 : std_logic_vector(3 DOWNTO 0):= "0001"; -- vme base address for A16 slave = 0x1000
CONSTANT sl_base_A24 : std_logic_vector(3 DOWNTO 0):= "0010"; -- vme base address for A24 slave = 0x20_0000
CONSTANT sl_base_CRCSR : std_logic_vector(3 DOWNTO 0):= "0100"; -- vme base address for CR/CSR slave = 0x40_0000
CONSTANT sl_base_A32 : std_logic_vector(3 DOWNTO 0):= "0011"; -- vme base address for A32 slave = 0x3000_0000
-- Address Modifiers
CONSTANT AM_A24_SUPER_BLT : std_logic_vector(5 DOWNTO 0):="111111";
CONSTANT AM_A24_SUPER_PROG : std_logic_vector(5 DOWNTO 0):="111110";
CONSTANT AM_A24_SUPER_DAT : std_logic_vector(5 DOWNTO 0):="111101";
CONSTANT AM_A24_SUPER_MBLT : std_logic_vector(5 DOWNTO 0):="111100";
CONSTANT AM_A24_NONPRIV_BLT : std_logic_vector(5 DOWNTO 0):="111011";
CONSTANT AM_A24_NONPRIV_PROG : std_logic_vector(5 DOWNTO 0):="111010";
CONSTANT AM_A24_NONPRIV_DAT : std_logic_vector(5 DOWNTO 0):="111001";
CONSTANT AM_A24_NONPRIV_MBLT : std_logic_vector(5 DOWNTO 0):="111000";
CONSTANT AM_CRCSR : std_logic_vector(5 DOWNTO 0):="101111";
CONSTANT AM_A16_SUPER : std_logic_vector(5 DOWNTO 0):="101101";
CONSTANT AM_A16_NONPRIV : std_logic_vector(5 DOWNTO 0):="101001";
CONSTANT AM_A32_SUPER_BLT : std_logic_vector(5 DOWNTO 0):="001111";
CONSTANT AM_A32_SUPER_PROG : std_logic_vector(5 DOWNTO 0):="001110";
CONSTANT AM_A32_SUPER_DAT : std_logic_vector(5 DOWNTO 0):="001101";
CONSTANT AM_A32_SUPER_MBLT : std_logic_vector(5 DOWNTO 0):="001100";
CONSTANT AM_A32_NONPRIV_BLT : std_logic_vector(5 DOWNTO 0):="001011";
CONSTANT AM_A32_NONPRIV_PROG : std_logic_vector(5 DOWNTO 0):="001010";
CONSTANT AM_A32_NONPRIV_DAT : std_logic_vector(5 DOWNTO 0):="001001";
CONSTANT AM_A32_NONPRIV_MBLT : std_logic_vector(5 DOWNTO 0):="001000";
SUBTYPE adr_type2 IS string(8 DOWNTO 1);
SUBTYPE adr_type IS std_logic_vector(31 DOWNTO 0);
SUBTYPE vec4 IS std_logic_vector(3 DOWNTO 0);
SUBTYPE am_type IS std_logic_vector(5 DOWNTO 0);
SUBTYPE data_type IS std_logic_vector(31 DOWNTO 0);
SUBTYPE data_type8 IS string(8 DOWNTO 1);
SUBTYPE data_type4 IS string(4 DOWNTO 1);
SUBTYPE data_type2 IS string(2 DOWNTO 1);
TYPE vme_mon_out_type IS record
err : integer;
END record;
------------------------------------------------------------------------------------------------------------------
-- vme_sim_mstr
------------------------------------------------------------------------------------------------------------------
TYPE mstr_in_type IS record
data : std_logic_vector(31 DOWNTO 0);
addr : std_logic_vector(31 DOWNTO 0);
dtackn : std_logic;
berrn : std_logic;
iackin : std_logic;
bg3n_in : std_logic;
bbsyn : std_logic;
asn : std_logic;
END record;
TYPE mstr_out_type IS record
sysresn : std_logic;
asn : std_logic;
dsan : std_logic;
dsbn : std_logic;
writen : std_logic;
addr : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
am : std_logic_vector(5 DOWNTO 0);
iackn : std_logic;
iackout : std_logic;
brn : std_logic_vector(3 DOWNTO 0);
bbsyn : std_logic;
berrn : std_logic;
END record;
PROCEDURE vme_mstr_init (
SIGNAL mstr_out : OUT mstr_out_type
);
PROCEDURE vme_mstr_write (
SIGNAL mstr_out : OUT mstr_out_type;
SIGNAL mstr_in : IN mstr_in_type;
adress : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
mode : character;
txt_out : integer; -- 0=quiet, 1=only errors, 2=all
number : integer;
tga : std_logic_vector(5 DOWNTO 0)
);
PROCEDURE vme_mstr_read (
SIGNAL mstr_out : OUT mstr_out_type;
SIGNAL mstr_in : IN mstr_in_type;
adress : std_logic_vector(31 DOWNTO 0);
ex_data : std_logic_vector(31 DOWNTO 0);
in_data : OUT std_logic_vector(31 DOWNTO 0);
mode : character;
txt_out : integer; -- 0=quiet, 1=only errors, 2=all
number : integer;
tga : std_logic_vector(5 DOWNTO 0);
err : OUT integer
) ;
PROCEDURE vme_mstr_write64 (
SIGNAL mstr_out : OUT mstr_out_type;
SIGNAL mstr_in : IN mstr_in_type;
adress : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
mode : character;
txt_out : integer; -- 0=quiet, 1=only errors, 2=all
number : integer;
tga : std_logic_vector(5 DOWNTO 0)
);
PROCEDURE vme_mstr_read64 (
SIGNAL mstr_out : OUT mstr_out_type;
SIGNAL mstr_in : IN mstr_in_type;
adress : std_logic_vector(31 DOWNTO 0);
ex_data : std_logic_vector(31 DOWNTO 0);
in_data : OUT std_logic_vector(31 DOWNTO 0);
mode : character;
txt_out : integer; -- 0=quiet, 1=only errors, 2=all
number : integer;
tga : std_logic_vector(5 DOWNTO 0);
err : OUT integer
) ;
------------------------------------------------------------------------------------------------------------------
-- vme_sim_slv
------------------------------------------------------------------------------------------------------------------
TYPE vme_slv_in_type IS record
conf_req : boolean; -- changes on signal will call vme_sim_slv subfunctions
req_type : integer; -- if set to 0 during conf_req state changes, write request to iram is requested
-- if set to 1 during conf_req state changes, read request from iram is requested
-- if set to 2 during conf_req state changes, interrupt request will be set to active
-- if set to 3 during conf_req state changes, address modifier of last access to slave is requested
adr : std_logic_vector(31 DOWNTO 0); -- address for config read write access
wr_dat : std_logic_vector(31 DOWNTO 0); -- write data to iram
irq : integer range 7 DOWNTO 0;
END record;
TYPE vme_slv_out_type IS record
conf_ack : boolean; -- if conf_req has changed state, subfunction end will result in conf_ack state change
rd_dat : std_logic_vector(31 DOWNTO 0); -- read data to iram
irq : std_logic_vector(7 DOWNTO 1);
rd_am : std_logic_vector(5 downto 0); -- address modifier of last access
END record;
TYPE mem_entry;
TYPE entry_ptr IS access mem_entry;
TYPE mem_entry IS record
address : integer;
data : std_logic_vector(31 DOWNTO 0);
nxt : entry_ptr;
END record;
TYPE head IS record
num_entries : integer;
list_ptr : entry_ptr;
END record;
TYPE head_ptr IS access head;
PROCEDURE wr_data (
CONSTANT location : IN integer;
CONSTANT data : IN std_logic_vector;
CONSTANT byte : IN std_logic_vector(3 DOWNTO 0);
VARIABLE first : INOUT head_ptr
);
PROCEDURE rd_data (
CONSTANT location : IN integer;
VARIABLE data : OUT std_logic_vector;
VARIABLE allocated : OUT boolean;
VARIABLE first : INOUT head_ptr
);
PROCEDURE rd_vme_slv (
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
adr : IN std_logic_vector(31 DOWNTO 0);
dat : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE wr_vme_slv (
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
adr : IN std_logic_vector(31 DOWNTO 0);
dat : IN std_logic_vector(31 DOWNTO 0)
) ;
PROCEDURE am_vme_slv (
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
am : OUT std_logic_vector(5 DOWNTO 0)
) ;
PROCEDURE init_vme_slv (
SIGNAL vme_slv_in : OUT vme_slv_in_type
) ;
PROCEDURE irq_vme_slv (
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
irq : IN integer range 7 DOWNTO 0;
dat : IN std_logic_vector(7 DOWNTO 0)
) ;
------------------------------------CONSTANTS----------------------------
FUNCTION hex_to_bit_vect (char_code : character) RETURN vec4;
FUNCTION conv_addr (addr : adr_type2) RETURN adr_type;
FUNCTION conv_data2 (data : data_type2; adr : adr_type) RETURN data_type;
FUNCTION conv_data4 (data : data_type4; adr : adr_type) RETURN data_type;
FUNCTION conv_data8 (data : data_type8) RETURN data_type;
FUNCTION conv_am (data : data_type2) RETURN am_type;
FUNCTION TO_HEX_STRING(val : std_logic_vector) RETURN string;
FUNCTION hex_to_character (hex_value : std_logic_vector(3 downto 0)) RETURN character;
PROCEDURE print(txt_out: IN integer; s: in string);
END vme_sim_pack;
-----------------------------------------------------------------------------------------------
PACKAGE BODY vme_sim_pack IS
PROCEDURE print(txt_out: IN integer; s: in string) is
variable l: line;
BEGIN
IF txt_out > 2 THEN
write(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
write(l, s);
writeline(output,l);
END IF;
END print;
--------------------------------------------------------------------------------------------
PROCEDURE vme_mstr_init (
SIGNAL mstr_out : OUT mstr_out_type
) IS
BEGIN
mstr_out.sysresn <= '0';
mstr_out.asn <= 'H';
mstr_out.dsan <= 'H';
mstr_out.dsbn <= 'H';
mstr_out.writen <= 'H';
mstr_out.addr <= (OTHERS => 'H');
mstr_out.data <= (OTHERS => 'H');
mstr_out.am <= (OTHERS => 'H');
mstr_out.iackn <= 'H';
mstr_out.iackout <= 'H';
mstr_out.brn <= (OTHERS => 'H');
mstr_out.bbsyn <= 'H';
mstr_out.berrn <= 'H';
WAIT FOR 10 ns;
mstr_out.sysresn <= 'H';
END PROCEDURE vme_mstr_init;
--------------------------------------------------------------------------------------------
PROCEDURE vme_mstr_write (
SIGNAL mstr_out : OUT mstr_out_type;
SIGNAL mstr_in : IN mstr_in_type;
adress : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
mode : character;
txt_out : integer; -- 0=quiet, 1=only errors, 2=all
number : integer;
tga : std_logic_vector(5 DOWNTO 0)
) IS
VARIABLE dsan : std_logic;
VARIABLE dsbn : std_logic;
VARIABLE vme_adr : std_logic_vector(31 DOWNTO 0);
VARIABLE dat_out : std_logic_vector(31 DOWNTO 0);
VARIABLE cnt : integer;
VARIABLE time_dat_changed : time;
BEGIN
print(txt_out, "VME_SIM_MSTR: do we have bus arbitration?");
IF mstr_in.bg3n_in /= '0' THEN
mstr_out.brn <= "0HHH"; -- request bus
WAIT until falling_edge(mstr_in.bg3n_in); -- wait until bus grant
END IF;
print(txt_out, "VME_SIM_MSTR: wait until prior access has finished");
IF mstr_in.bbsyn = '0' THEN
WAIT until rising_edge(mstr_in.bbsyn);
END IF;
-- occupy bus
mstr_out.bbsyn <= '0', 'H' AFTER 90 ns;
-- prepare
cnt := 0;
vme_adr := adress;
dat_out := (OTHERS => '0');
IF mode = 'b' THEN -- byte access
CASE adress(1 DOWNTO 0) IS
WHEN "00" => dsan := '1'; -- B0
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '1'; --lwordn
dat_out(15 DOWNTO 8) := data(7 DOWNTO 0);
WHEN "01" => dsan := '0'; -- B1
dsbn := '1';
vme_adr(1) := '0';
vme_adr(0) := '1'; --lwordn
dat_out(7 DOWNTO 0) := data(15 DOWNTO 8);
WHEN "10" => dsan := '1'; -- B2
dsbn := '0';
vme_adr(1) := '1';
vme_adr(0) := '1'; --lwordn
dat_out(15 DOWNTO 8) := data(23 DOWNTO 16);
WHEN "11" => dsan := '0'; -- B3
dsbn := '1';
vme_adr(1) := '1';
vme_adr(0) := '1'; --lwordn
dat_out(7 DOWNTO 0) := data(31 DOWNTO 24);
WHEN OTHERS => dsan := '1';
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '1'; --lwordn
dat_out(15 DOWNTO 8) := data(7 DOWNTO 0);
END CASE;
ELSIF mode = 'w' THEN -- word access
IF adress(1) = '0' THEN
dsan := '0'; -- B0,B1
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '1'; --lwordn
dat_out(15 DOWNTO 8) := data(7 DOWNTO 0);
dat_out(7 DOWNTO 0) := data(15 DOWNTO 8);
ELSE
dsan := '0'; -- B2, B3
dsbn := '0';
vme_adr(1) := '1';
vme_adr(0) := '1'; --lwordn
dat_out(15 DOWNTO 8) := data(23 DOWNTO 16);
dat_out(7 DOWNTO 0) := data(31 DOWNTO 24);
END IF;
ELSE -- long access (mode='l')
dsan := '0'; -- B0, B1, B2, B3
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '0'; --lwordn
dat_out(31 DOWNTO 24) := data(7 DOWNTO 0);
dat_out(23 DOWNTO 16) := data(15 DOWNTO 8);
dat_out(15 DOWNTO 8) := data(23 DOWNTO 16);
dat_out(7 DOWNTO 0) := data(31 DOWNTO 24);
END IF;
print(txt_out, "VME_SIM_MSTR: start of vme access");
print(txt_out, "VME_SIM_MSTR: address phase");
mstr_out.addr <= vme_adr;
mstr_out.am <= tga;
mstr_out.writen <= '0';
WAIT FOR 40 ns;
mstr_out.asn <= '0';
WAIT FOR 5 ns;
mstr_out.brn <= "HHHH"; -- release bus arbitration
print(txt_out, "VME_SIM_MSTR: data phase");
dat_phase: LOOP
mstr_out.data <= dat_out;
WAIT FOR 35 ns;
mstr_out.addr <= (OTHERS => 'H');
mstr_out.am <= (OTHERS => 'H');
mstr_out.writen <= 'H';
mstr_out.dsan <= dsan;
mstr_out.dsbn <= dsbn;
WAIT until falling_edge(mstr_in.dtackn);
print(txt_out, "VME_SIM_MSTR: got dtackn");
IF txt_out > 1 THEN
print_mtest("VME_MSTR: WRITE ", adress, dat_out, dat_out, TRUE);
END IF;
WAIT FOR 1 ns;
mstr_out.dsan <= 'H';
mstr_out.dsbn <= 'H';
cnt := cnt + 1;
IF cnt < number THEN -- burst
dat_out := dat_out + 1;
mstr_out.data <= dat_out;
ELSE
mstr_out.data <= (OTHERS => 'H');
mstr_out.asn <= 'H';
END IF;
time_dat_changed := now;
-- WAIT until rising_edge(mstr_in.dtackn);
-- WAIT FOR 1 ns;
-- mstr_out.asn <= 'H';
IF cnt = number THEN
exit dat_phase;
END IF;
IF time_dat_changed > 35 ns THEN
next dat_phase;
ELSE
WAIT FOR (35 ns - time_dat_changed);
next dat_phase;
END IF;
END LOOP;
END PROCEDURE vme_mstr_write;
--------------------------------------------------------------------------------------------
PROCEDURE vme_mstr_write64 (
SIGNAL mstr_out : OUT mstr_out_type;
SIGNAL mstr_in : IN mstr_in_type;
adress : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
mode : character;
txt_out : integer; -- 0=quiet, 1=only errors, 2=all
number : integer;
tga : std_logic_vector(5 DOWNTO 0)
) IS
VARIABLE dsan : std_logic;
VARIABLE dsbn : std_logic;
VARIABLE vme_adr : std_logic_vector(31 DOWNTO 0);
VARIABLE dat_out : std_logic_vector(31 DOWNTO 0);
VARIABLE cnt : integer;
VARIABLE time_dat_changed : time;
BEGIN
print(txt_out, "VME_SIM_MSTR: do we have bus arbitration?");
IF mstr_in.bg3n_in /= '0' THEN
mstr_out.brn <= "0HHH"; -- request bus
WAIT until falling_edge(mstr_in.bg3n_in); -- wait until bus grant
END IF;
print(txt_out, "VME_SIM_MSTR: wait until prior access has finished");
IF mstr_in.bbsyn = '0' THEN
WAIT until rising_edge(mstr_in.bbsyn);
END IF;
-- occupy bus
mstr_out.bbsyn <= '0', 'H' AFTER 90 ns;
-- prepare
cnt := 0;
vme_adr := adress;
dat_out := (OTHERS => '0');
-- mode = 'd'
dsan := '0'; -- B0, B1, B2, B3
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '0'; --lwordn
dat_out(31 DOWNTO 24) := data(7 DOWNTO 0);
dat_out(23 DOWNTO 16) := data(15 DOWNTO 8);
dat_out(15 DOWNTO 8) := data(23 DOWNTO 16);
dat_out(7 DOWNTO 0) := data(31 DOWNTO 24);
print(txt_out, "VME_SIM_MSTR: start of vme access");
print(txt_out, "VME_SIM_MSTR: address phase");
mstr_out.addr <= vme_adr;
mstr_out.am <= tga;
mstr_out.writen <= '0';
WAIT FOR 40 ns;
mstr_out.asn <= '0';
WAIT FOR 5 ns;
mstr_out.brn <= "HHHH"; -- release bus arbitration
print(txt_out, "VME_SIM_MSTR: address phase");
mstr_out.data <= (OTHERS => '0'); -- no data in first d64 phase: address phase
WAIT FOR 35 ns;
mstr_out.addr <= (OTHERS => 'H');
mstr_out.am <= (OTHERS => 'H');
mstr_out.writen <= 'H';
mstr_out.dsan <= dsan;
mstr_out.dsbn <= dsbn;
WAIT until falling_edge(mstr_in.dtackn);
print(txt_out, "VME_SIM_MSTR: got dtackn FOR address phase");
WAIT FOR 1 ns;
mstr_out.dsan <= 'H';
mstr_out.dsbn <= 'H';
WAIT until rising_edge(mstr_in.dtackn);
WAIT FOR 1 ns;
print(txt_out, "VME_SIM_MSTR: data phase");
dat_phase: LOOP
vme_adr:= NOT dat_out;
mstr_out.data <= dat_out;
mstr_out.addr <= vme_adr;
WAIT FOR 35 ns;
mstr_out.am <= (OTHERS => 'H');
mstr_out.writen <= 'H';
mstr_out.dsan <= dsan;
mstr_out.dsbn <= dsbn;
WAIT until falling_edge(mstr_in.dtackn);
print(txt_out, "VME_SIM_MSTR: got dtackn");
IF txt_out > 1 THEN
print_mtest("VME_MSTR: WRITE ", adress, (vme_adr & dat_out), (vme_adr & dat_out), TRUE);
END IF;
WAIT FOR 1 ns;
mstr_out.dsan <= 'H';
mstr_out.dsbn <= 'H';
cnt := cnt + 1;
IF cnt < number THEN -- burst
dat_out := dat_out + 1;
mstr_out.data <= dat_out;
mstr_out.addr <= vme_adr;
ELSE
mstr_out.data <= (OTHERS => 'H');
mstr_out.addr <= (OTHERS => 'H');
mstr_out.asn <= 'H';
END IF;
time_dat_changed := now;
-- WAIT until rising_edge(mstr_in.dtackn);
-- WAIT FOR 1 ns;
-- mstr_out.asn <= 'H';
IF cnt = number THEN
exit dat_phase;
END IF;
IF time_dat_changed > 35 ns THEN
next dat_phase;
ELSE
WAIT FOR (35 ns - time_dat_changed);
next dat_phase;
END IF;
END LOOP;
END PROCEDURE vme_mstr_write64;
--------------------------------------------------------------------------------------------
PROCEDURE vme_mstr_read (
SIGNAL mstr_out : OUT mstr_out_type;
SIGNAL mstr_in : IN mstr_in_type;
adress : std_logic_vector(31 DOWNTO 0);
ex_data : std_logic_vector(31 DOWNTO 0);
in_data : OUT std_logic_vector(31 DOWNTO 0);
mode : character;
txt_out : integer; -- 0=quiet, 1=only errors, 2=all
number : integer;
tga : std_logic_vector(5 DOWNTO 0);
err : OUT integer
) IS
VARIABLE dsan : std_logic;
VARIABLE dsbn : std_logic;
VARIABLE vme_adr : std_logic_vector(31 DOWNTO 0);
VARIABLE dat_in : std_logic_vector(31 DOWNTO 0);
VARIABLE cnt : integer;
VARIABLE time_dat_changed : time;
VARIABLE dat_phase_err : integer;
VARIABLE loc_err : integer;
VARIABLE expected : std_logic_vector(31 DOWNTO 0);
BEGIN
dat_phase_err := 0;
loc_err := 0;
expected := ex_data;
print(txt_out, "VME_SIM_MSTR: do we have bus arbitration?");
IF mstr_in.bg3n_in /= '0' THEN
mstr_out.brn <= "0HHH"; -- request bus
WAIT until falling_edge(mstr_in.bg3n_in); -- wait until bus grant
END IF;
print(txt_out, "VME_SIM_MSTR: wait until prior access has finished");
-- IF mstr_in.bbsyn = '0' THEN
-- WAIT until rising_edge(mstr_in.bbsyn);
-- END IF;
IF mstr_in.asn = '0' THEN
WAIT until rising_edge(mstr_in.asn);
END IF;
IF mstr_in.asn'LAST_EVENT < 40 ns AND mstr_in.asn /= '0' THEN
WAIT FOR (40 ns - mstr_in.asn'LAST_EVENT);
END IF;
-- occupy bus
mstr_out.bbsyn <= '0', 'H' AFTER 90 ns;
-- prepare
cnt := 0;
vme_adr := adress;
expected := (OTHERS => '0');
mstr_out.iackn <= 'H';
IF mode = 'b' OR mode = 'i' THEN -- byte access
IF mode = 'i' THEN
mstr_out.iackn <= '0'; -- indicate iack cycle
END IF;
CASE adress(1 DOWNTO 0) IS
WHEN "00" => dsan := '1'; -- B0
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '1'; --lwordn
expected(15 DOWNTO 8) := ex_data(7 DOWNTO 0);
WHEN "01" => dsan := '0'; -- B1
dsbn := '1';
vme_adr(1) := '0';
vme_adr(0) := '1'; --lwordn
expected(7 DOWNTO 0) := ex_data(15 DOWNTO 8);
WHEN "10" => dsan := '1'; -- B2
dsbn := '0';
vme_adr(1) := '1';
vme_adr(0) := '1'; --lwordn
expected(15 DOWNTO 8) := ex_data(23 DOWNTO 16);
WHEN "11" => dsan := '0'; -- B3
dsbn := '1';
vme_adr(1) := '1';
vme_adr(0) := '1'; --lwordn
expected(7 DOWNTO 0) := ex_data(31 DOWNTO 24);
WHEN OTHERS => dsan := '1';
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '1'; --lwordn
expected(15 DOWNTO 8) := ex_data(7 DOWNTO 0);
END CASE;
ELSIF mode = 'w' THEN -- word access
IF adress(1) = '0' THEN
dsan := '0'; -- B0,B1
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '1'; --lwordn
expected(15 DOWNTO 8) := ex_data(7 DOWNTO 0);
expected(7 DOWNTO 0) := ex_data(15 DOWNTO 8);
ELSE
dsan := '0'; -- B2, B3
dsbn := '0';
vme_adr(1) := '1';
vme_adr(0) := '1'; --lwordn
expected(15 DOWNTO 8) := ex_data(23 DOWNTO 16);
expected(7 DOWNTO 0) := ex_data(31 DOWNTO 24);
END IF;
ELSE -- long access (mode='l')
dsan := '0'; -- B0, B1, B2, B3
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '0'; --lwordn
expected(31 DOWNTO 24) := ex_data(7 DOWNTO 0);
expected(23 DOWNTO 16) := ex_data(15 DOWNTO 8);
expected(15 DOWNTO 8) := ex_data(23 DOWNTO 16);
expected(7 DOWNTO 0) := ex_data(31 DOWNTO 24);
END IF;
print(txt_out, "VME_SIM_MSTR: start of vme access");
print(txt_out, "VME_SIM_MSTR: address phase");
mstr_out.addr <= vme_adr;
mstr_out.am <= tga;
mstr_out.writen <= '1';
WAIT FOR 40 ns;
mstr_out.asn <= '0';
WAIT FOR 5 ns;
mstr_out.brn <= "HHHH"; -- release bus arbitration
print(txt_out, "VME_SIM_MSTR: data phase");
dat_phase: LOOP
dat_phase_err := 0;
WAIT FOR 35 ns;
mstr_out.addr <= (OTHERS => 'H');
mstr_out.am <= (OTHERS => 'H');
mstr_out.writen <= 'H';
mstr_out.dsan <= dsan;
mstr_out.dsbn <= dsbn;
WAIT until falling_edge(mstr_in.dtackn);
print(txt_out, "VME_SIM_MSTR: got dtackn");
WAIT FOR 1 ns;
dat_in := mstr_in.data;
IF mode = 'b' OR mode = 'i' THEN
IF adress(1 DOWNTO 0) = "01" AND dat_in(7 DOWNTO 0) /= expected(7 DOWNTO 0) THEN
dat_phase_err := dat_phase_err + 1;
ELSIF adress(1 DOWNTO 0) = "00" AND dat_in(15 DOWNTO 8) /= expected(15 DOWNTO 8) THEN
dat_phase_err := dat_phase_err + 1;
ELSIF adress(1 DOWNTO 0) = "11" AND dat_in(7 DOWNTO 0) /= expected(7 DOWNTO 0) THEN
dat_phase_err := dat_phase_err + 1;
ELSIF adress(1 DOWNTO 0) = "10" AND dat_in(15 DOWNTO 8) /= expected(15 DOWNTO 8) THEN
dat_phase_err := dat_phase_err + 1;
END IF;
ELSIF mode = 'w' THEN
IF adress(1) = '0' AND
(dat_in(7 DOWNTO 0) /= expected(7 DOWNTO 0) OR
dat_in(15 DOWNTO 8) /= expected(15 DOWNTO 8)) THEN
dat_phase_err := dat_phase_err + 1;
ELSIF adress(1) = '1' AND
(dat_in(7 DOWNTO 0) /= expected(7 DOWNTO 0) OR
dat_in(15 DOWNTO 8) /= expected(15 DOWNTO 8)) THEN
dat_phase_err := dat_phase_err + 1;
END IF;
-- ELSIF mode = 'y' THEN -- d64
-- IF dat_in2(7 DOWNTO 0) /= expected(7 DOWNTO 0) OR
-- dat_in2(15 DOWNTO 8) /= expected(15 DOWNTO 8) OR
-- dat_in2(23 DOWNTO 16) /= expected(23 DOWNTO 16) OR
-- dat_in2(31 DOWNTO 24) /= expected(31 DOWNTO 24) THEN
-- dat_phase_err := dat_phase_err + 1;
-- END IF;
-- expected := expected + 1;
-- IF dat_in(7 DOWNTO 0) /= expected(7 DOWNTO 0) OR
-- dat_in(15 DOWNTO 8) /= expected(15 DOWNTO 8) OR
-- dat_in(23 DOWNTO 16) /= expected(23 DOWNTO 16) OR
-- dat_in(31 DOWNTO 24) /= expected(31 DOWNTO 24) THEN
-- dat_phase_err := dat_phase_err + 1;
-- END IF;
ELSE -- mode = 'l'
IF dat_in(7 DOWNTO 0) /= expected(7 DOWNTO 0) OR
dat_in(15 DOWNTO 8) /= expected(15 DOWNTO 8) OR
dat_in(23 DOWNTO 16) /= expected(23 DOWNTO 16) OR
dat_in(31 DOWNTO 24) /= expected(31 DOWNTO 24) THEN
dat_phase_err := dat_phase_err + 1;
END IF;
END IF;
IF txt_out > 0 AND dat_phase_err > 0 THEN
print_mtest("VME_MSTR: READ ", adress, dat_in, expected, FALSE);
END IF;
IF txt_out > 1 AND dat_phase_err = 0 THEN
print_mtest("VME_MSTR: READ ", adress, dat_in, expected, TRUE);
END IF;
mstr_out.dsan <= 'H';
mstr_out.dsbn <= 'H';
mstr_out.iackn <= 'H';
cnt := cnt + 1;
IF cnt < number THEN -- burst
expected := expected + 1;
ELSE
mstr_out.asn <= 'H';
END IF;
time_dat_changed := now;
WAIT until rising_edge(mstr_in.dtackn);
WAIT FOR 1 ns;
loc_err := loc_err + dat_phase_err;
err := loc_err;
IF cnt = number THEN
mstr_out.asn <= 'H';
exit dat_phase;
END IF;
IF time_dat_changed > 35 ns THEN
next dat_phase;
ELSE
WAIT FOR (35 ns - time_dat_changed);
next dat_phase;
END IF;
END LOOP;
END PROCEDURE vme_mstr_read;
--------------------------------------------------------------------------------------------
PROCEDURE vme_mstr_read64 (
SIGNAL mstr_out : OUT mstr_out_type;
SIGNAL mstr_in : IN mstr_in_type;
adress : std_logic_vector(31 DOWNTO 0);
ex_data : std_logic_vector(31 DOWNTO 0);
in_data : OUT std_logic_vector(31 DOWNTO 0);
mode : character;
txt_out : integer; -- 0=quiet, 1=only errors, 2=all
number : integer;
tga : std_logic_vector(5 DOWNTO 0);
err : OUT integer
) IS
VARIABLE dsan : std_logic;
VARIABLE dsbn : std_logic;
VARIABLE vme_adr : std_logic_vector(31 DOWNTO 0);
VARIABLE dat_in : std_logic_vector(63 DOWNTO 0);
VARIABLE cnt : integer;
VARIABLE time_dat_changed : time;
VARIABLE dat_phase_err : integer;
VARIABLE loc_err : integer;
VARIABLE expected : std_logic_vector(63 DOWNTO 0);
BEGIN
dat_phase_err := 0;
loc_err := 0;
expected(31 DOWNTO 0) := ex_data;
print(txt_out, "VME_SIM_MSTR: do we have bus arbitration?");
IF mstr_in.bg3n_in /= '0' THEN
mstr_out.brn <= "0HHH"; -- request bus
WAIT until falling_edge(mstr_in.bg3n_in); -- wait until bus grant
END IF;
print(txt_out, "VME_SIM_MSTR: wait until prior access has finished");
IF mstr_in.bbsyn = '0' THEN
WAIT until rising_edge(mstr_in.bbsyn);
END IF;
-- occupy bus
mstr_out.bbsyn <= '0', 'H' AFTER 90 ns;
-- prepare
cnt := 0;
vme_adr := adress;
expected := (OTHERS => '0');
-- 64-bit access
dsan := '0'; -- B0, B1, B2, B3, B4, B5, B6
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '0'; --lwordn
expected(31 DOWNTO 24) := ex_data(7 DOWNTO 0);
expected(23 DOWNTO 16) := ex_data(15 DOWNTO 8);
expected(15 DOWNTO 8) := ex_data(23 DOWNTO 16);
expected(7 DOWNTO 0) := ex_data(31 DOWNTO 24);
expected(63 DOWNTO 32) := NOT expected(31 DOWNTO 0);
print(txt_out, "VME_SIM_MSTR: start of vme access");
print(txt_out, "VME_SIM_MSTR: address phase");
mstr_out.addr <= vme_adr;
mstr_out.am <= tga;
mstr_out.writen <= '1';
WAIT FOR 40 ns;
mstr_out.asn <= '0';
WAIT FOR 5 ns;
mstr_out.brn <= "HHHH"; -- release bus arbitration
print(txt_out, "VME_SIM_MSTR: address phase");
WAIT FOR 35 ns;
mstr_out.addr <= (OTHERS => 'H');
mstr_out.am <= (OTHERS => 'H');
mstr_out.writen <= 'H';
mstr_out.dsan <= dsan;
mstr_out.dsbn <= dsbn;
WAIT until falling_edge(mstr_in.dtackn);
print(txt_out, "VME_SIM_MSTR: got dtackn FOR address phase");
WAIT FOR 1 ns;
mstr_out.dsan <= 'H';
mstr_out.dsbn <= 'H';
WAIT until rising_edge(mstr_in.dtackn);
WAIT FOR 1 ns;
print(txt_out, "VME_SIM_MSTR: data phase");
dat_phase: LOOP
dat_phase_err := 0;
WAIT FOR 35 ns;
mstr_out.addr <= (OTHERS => 'H');
mstr_out.am <= (OTHERS => 'H');
mstr_out.writen <= 'H';
mstr_out.dsan <= dsan;
mstr_out.dsbn <= dsbn;
WAIT until falling_edge(mstr_in.dtackn);
print(txt_out, "VME_SIM_MSTR: got dtackn");
WAIT FOR 1 ns;
dat_in := mstr_in.addr & mstr_in.data;
IF dat_in(7 DOWNTO 0) /= expected(7 DOWNTO 0) OR
dat_in(15 DOWNTO 8) /= expected(15 DOWNTO 8) OR
dat_in(23 DOWNTO 16) /= expected(23 DOWNTO 16) OR
dat_in(31 DOWNTO 24) /= expected(31 DOWNTO 24) OR
dat_in(39 DOWNTO 32) /= expected(39 DOWNTO 32) OR
dat_in(47 DOWNTO 40) /= expected(47 DOWNTO 40) OR
dat_in(55 DOWNTO 48) /= expected(55 DOWNTO 48) OR
dat_in(63 DOWNTO 56) /= expected(63 DOWNTO 56) THEN
dat_phase_err := dat_phase_err + 1;
END IF;
IF txt_out > 0 AND dat_phase_err > 0 THEN
print_mtest("VME_MSTR: READ ", adress, dat_in, expected, FALSE);
END IF;
IF txt_out > 1 AND dat_phase_err = 0 THEN
print_mtest("VME_MSTR: READ ", adress, dat_in, expected, TRUE);
END IF;
mstr_out.dsan <= 'H';
mstr_out.dsbn <= 'H';
cnt := cnt + 1;
IF cnt < number THEN -- burst
expected(31 DOWNTO 0) := expected(31 DOWNTO 0) + 1;
expected(63 DOWNTO 32) := NOT expected(31 DOWNTO 0);
ELSE
mstr_out.asn <= 'H';
END IF;
time_dat_changed := now;
WAIT until rising_edge(mstr_in.dtackn);
WAIT FOR 1 ns;
loc_err := loc_err + dat_phase_err;
err := loc_err;
IF cnt = number THEN
mstr_out.asn <= 'H';
exit dat_phase;
END IF;
IF time_dat_changed > 35 ns THEN
next dat_phase;
ELSE
WAIT FOR (35 ns - time_dat_changed);
next dat_phase;
END IF;
END LOOP;
END PROCEDURE vme_mstr_read64;
--------------------------------------------------------------------------------------------
PROCEDURE init_vme_slv (
SIGNAL vme_slv_in : OUT vme_slv_in_type
) IS
BEGIN
vme_slv_in.req_type <= 0;
vme_slv_in.wr_dat <= (OTHERS => '0');
vme_slv_in.adr <= (OTHERS => '0');
vme_slv_in.conf_req <= FALSE;
vme_slv_in.irq <= 0;
END PROCEDURE init_vme_slv;
--------------------------------------------------------------------------------------------
PROCEDURE irq_vme_slv ( SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
irq : IN integer range 7 DOWNTO 0;
dat : IN std_logic_vector(7 DOWNTO 0)
) IS
BEGIN
vme_slv_in.req_type <= 2;
vme_slv_in.irq <= irq;
vme_slv_in.wr_dat(7 DOWNTO 0) <= dat;
vme_slv_in.conf_req <= NOT vme_slv_out.conf_ack;
WAIT on vme_slv_out.conf_ack;
END PROCEDURE irq_vme_slv;
--------------------------------------------------------------------------------------------
PROCEDURE wr_vme_slv ( SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
adr : IN std_logic_vector(31 DOWNTO 0);
dat : IN std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
vme_slv_in.req_type <= 0;
vme_slv_in.wr_dat <= dat;
vme_slv_in.adr <= adr;
vme_slv_in.conf_req <= NOT vme_slv_out.conf_ack;
WAIT on vme_slv_out.conf_ack;
END PROCEDURE wr_vme_slv;
--------------------------------------------------------------------------------------------
PROCEDURE am_vme_slv (
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
am : OUT std_logic_vector(5 DOWNTO 0)
) is
BEGIN
vme_slv_in.req_type <= 3;
vme_slv_in.conf_req <= NOT vme_slv_out.conf_ack;
WAIT on vme_slv_out.conf_ack;
am := vme_slv_out.rd_am;
END PROCEDURE am_vme_slv;
--------------------------------------------------------------------------------------------
PROCEDURE rd_vme_slv ( SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
adr : IN std_logic_vector(31 DOWNTO 0);
dat : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
vme_slv_in.req_type <= 1;
vme_slv_in.adr <= adr;
vme_slv_in.conf_req <= NOT vme_slv_out.conf_ack;
WAIT on vme_slv_out.conf_ack;
dat := vme_slv_out.rd_dat;
END PROCEDURE rd_vme_slv;
--------------------------------------------------------------------------------------------
PROCEDURE wr_data (
CONSTANT location : IN integer;
CONSTANT data : IN std_logic_vector;
CONSTANT byte : IN std_logic_vector(3 DOWNTO 0);
VARIABLE first : INOUT head_ptr
) IS
VARIABLE temp_ptr : entry_ptr;
VARIABLE new_ptr : entry_ptr;
VARIABLE prev_ptr : entry_ptr;
VARIABLE done : boolean:=FALSE;
BEGIN
done:= FALSE; -- set done to true when allocation occurs
IF first.num_entries = 0 THEN -- first access to memory
first.list_ptr := new mem_entry;
first.num_entries := 1;
first.list_ptr.address := location;
IF byte(0) = '1' THEN
first.list_ptr.data(7 DOWNTO 0) := data(7 DOWNTO 0);
END IF;
IF byte(1) = '1' THEN
first.list_ptr.data(15 DOWNTO 8) := data(15 DOWNTO 8);
END IF;
IF byte(2) = '1' THEN
first.list_ptr.data(23 DOWNTO 16) := data(23 DOWNTO 16);
END IF;
IF byte(3) = '1' THEN
first.list_ptr.data(31 DOWNTO 24) := data(31 DOWNTO 24);
END IF;
first.list_ptr.nxt := null;
done := TRUE;
ELSIF location < first.list_ptr.address THEN -- address is lowest value so far in allocation to put at head of list
new_ptr := new mem_entry;
IF byte(0) = '1' THEN
new_ptr.data(7 DOWNTO 0) := data(7 DOWNTO 0);
END IF;
IF byte(1) = '1' THEN
new_ptr.data(15 DOWNTO 8) := data(15 DOWNTO 8);
END IF;
IF byte(2) = '1' THEN
new_ptr.data(23 DOWNTO 16) := data(23 DOWNTO 16);
END IF;
IF byte(3) = '1' THEN
new_ptr.data(31 DOWNTO 24) := data(31 DOWNTO 24);
END IF;
new_ptr.nxt := first.list_ptr;
new_ptr.address := location;
first.list_ptr := new_ptr;
first.num_entries := first.num_entries + 1;
done := TRUE;
ELSE -- location must be >= first.list_ptr.address
temp_ptr := first.list_ptr;
while temp_ptr /= null AND NOT done LOOP
IF temp_ptr.address = location THEN -- address already allocated
IF byte(0) = '1' THEN
temp_ptr.data(7 DOWNTO 0) := data(7 DOWNTO 0);
END IF;
IF byte(1) = '1' THEN
temp_ptr.data(15 DOWNTO 8) := data(15 DOWNTO 8);
END IF;
IF byte(2) = '1' THEN
temp_ptr.data(23 DOWNTO 16) := data(23 DOWNTO 16);
END IF;
IF byte(3) = '1' THEN
temp_ptr.data(31 DOWNTO 24) := data(31 DOWNTO 24);
END IF;
done := TRUE;
ELSIF temp_ptr.address > location THEN
new_ptr := new mem_entry;
new_ptr.address := location;
IF byte(0) = '1' THEN
new_ptr.data(7 DOWNTO 0) := data(7 DOWNTO 0);
END IF;
IF byte(1) = '1' THEN
new_ptr.data(15 DOWNTO 8) := data(15 DOWNTO 8);
END IF;
IF byte(2) = '1' THEN
new_ptr.data(23 DOWNTO 16) := data(23 DOWNTO 16);
END IF;
IF byte(3) = '1' THEN
new_ptr.data(31 DOWNTO 24) := data(31 DOWNTO 24);
END IF;
new_ptr.nxt := temp_ptr;
prev_ptr.nxt := new_ptr; -- break pointer chain and insert new_ptr
first.num_entries := first.num_entries + 1;
done := TRUE;
ELSE
prev_ptr := temp_ptr;
temp_ptr := temp_ptr.nxt;
END IF;
END LOOP;
IF NOT done THEN
new_ptr := new mem_entry;
new_ptr.address := location;
IF byte(0) = '1' THEN
new_ptr.data(7 DOWNTO 0) := data(7 DOWNTO 0);
END IF;
IF byte(1) = '1' THEN
new_ptr.data(15 DOWNTO 8) := data(15 DOWNTO 8);
END IF;
IF byte(2) = '1' THEN
new_ptr.data(23 DOWNTO 16) := data(23 DOWNTO 16);
END IF;
IF byte(3) = '1' THEN
new_ptr.data(31 DOWNTO 24) := data(31 DOWNTO 24);
END IF;
new_ptr.nxt := null; -- add new_ptr TO END OF chain
prev_ptr.nxt := new_ptr;
first.num_entries := first.num_entries + 1;
done := TRUE;
END IF;
END IF;
WAIT FOR 0 ns;
END wr_data;
--------------------------------------------------------------------------------------------
PROCEDURE rd_data (
CONSTANT location : IN integer;
VARIABLE data : OUT std_logic_vector;
VARIABLE allocated : OUT boolean;
VARIABLE first : INOUT head_ptr
) IS
VARIABLE temp_ptr : entry_ptr;
VARIABLE is_allocated : boolean;
BEGIN
-- set allocated to true when read hits already allocated spot
is_allocated := FALSE;
IF (first.list_ptr /= null AND first.num_entries /= 0 AND location >= first.list_ptr.address) THEN
temp_ptr := first.list_ptr;
while (temp_ptr /= null AND NOT is_allocated AND location >= temp_ptr.address) LOOP
IF temp_ptr.address = location THEN -- address has been allocated
data := temp_ptr.data;
is_allocated := TRUE;
ELSE
temp_ptr := temp_ptr.nxt;
END IF;
END LOOP;
END IF;
IF NOT is_allocated THEN
data := (data'range => '1');
END IF;
allocated := is_allocated;
WAIT FOR 0 ns;
END rd_data;
FUNCTION hex_to_character (hex_value : std_logic_vector(3 downto 0))
return character is
begin
case hex_value is
when "0000" => return '0';
when "0001" => return '1';
when "0010" => return '2';
when "0011" => return '3';
when "0100" => return '4';
when "0101" => return '5';
when "0110" => return '6';
when "0111" => return '7';
when "1000" => return '8';
when "1001" => return '9';
when "1010" => return 'A';
when "1011" => return 'B';
when "1100" => return 'C';
when "1101" => return 'D';
when "1110" => return 'E';
when "1111" => return 'F';
when "ZZZZ" => return 'Z';
when others => return 'U';
end case;
end hex_to_character;
--------------------------------------------------------------------------------
-- the function can take multiple of 4 bits, upto 32 bits as input
function TO_HEX_STRING(val : std_logic_vector) return string is
variable temp : string(VAL'length / 4 downto 1);
alias valalias : std_logic_vector(VAL'length-1 downto 0) is val;
variable val32 : std_logic_vector(31 downto 0);
variable num : integer;
begin
-- temp := " ";
val32 := (others => '0');
val32(val'length-1 downto 0) := valalias;
for i in 1 to VAL'length / 4 loop
temp(i) := ' ';
temp(i) := hex_to_character(val32(i*4-1 downto i*4-4));
end loop;
return temp;
end TO_HEX_STRING;
--------------------------------------------------------------------------------
FUNCTION hex_to_bit_vect (char_code : character) RETURN vec4 IS
VARIABLE result : std_logic_vector(3 DOWNTO 0);
BEGIN
CASE char_code IS
WHEN '0' => result := "0000";
WHEN '1' => result := "0001";
WHEN '2' => result := "0010";
WHEN '3' => result := "0011";
WHEN '4' => result := "0100";
WHEN '5' => result := "0101";
WHEN '6' => result := "0110";
WHEN '7' => result := "0111";
WHEN '8' => result := "1000";
WHEN '9' => result := "1001";
WHEN 'a' => result := "1010";
WHEN 'b' => result := "1011";
WHEN 'c' => result := "1100";
WHEN 'd' => result := "1101";
WHEN 'e' => result := "1110";
WHEN 'f' => result := "1111";
WHEN OTHERS => result := "0000";
END CASE;
RETURN result;
END hex_to_bit_vect;
FUNCTION conv_addr (addr : adr_type2) RETURN adr_type IS
VARIABLE result : std_logic_vector(31 DOWNTO 0);
BEGIN
result(3 DOWNTO 0) := hex_to_bit_vect(addr(1));
result(7 DOWNTO 4) := hex_to_bit_vect(addr(2));
result(11 DOWNTO 8) := hex_to_bit_vect(addr(3));
result(15 DOWNTO 12) := hex_to_bit_vect(addr(4));
result(19 DOWNTO 16) := hex_to_bit_vect(addr(5));
result(23 DOWNTO 20) := hex_to_bit_vect(addr(6));
result(27 DOWNTO 24) := hex_to_bit_vect(addr(7));
result(31 DOWNTO 28) := hex_to_bit_vect(addr(8));
RETURN result;
END conv_addr;
FUNCTION conv_data2 (data : data_type2; adr : adr_type) RETURN data_type IS
VARIABLE result : std_logic_vector(31 DOWNTO 0);
BEGIN
result := (OTHERS => '0');
CASE adr(1 DOWNTO 0) IS
WHEN "00" => result(3 DOWNTO 0) := hex_to_bit_vect(data(1));
result(7 DOWNTO 4) := hex_to_bit_vect(data(2));
WHEN "01" => result(11 DOWNTO 8) := hex_to_bit_vect(data(1));
result(15 DOWNTO 12) := hex_to_bit_vect(data(2));
WHEN "10" => result(19 DOWNTO 16) := hex_to_bit_vect(data(1));
result(23 DOWNTO 20) := hex_to_bit_vect(data(2));
WHEN OTHERS => result(27 DOWNTO 24) := hex_to_bit_vect(data(1));
result(31 DOWNTO 28) := hex_to_bit_vect(data(2));
END CASE;
RETURN result;
END conv_data2;
FUNCTION conv_am (data : data_type2) RETURN am_type IS
VARIABLE result : std_logic_vector(7 DOWNTO 0);
BEGIN
result(3 DOWNTO 0) := hex_to_bit_vect(data(1));
result(7 DOWNTO 4) := hex_to_bit_vect(data(2));
RETURN result(5 DOWNTO 0);
END conv_am;
FUNCTION conv_data4 (data : data_type4; adr : adr_type) RETURN data_type IS
VARIABLE result : std_logic_vector(31 DOWNTO 0);
BEGIN
result := (OTHERS => '0');
CASE adr(1) IS
WHEN '0' =>
result(3 DOWNTO 0) := hex_to_bit_vect(data(1));
result(7 DOWNTO 4) := hex_to_bit_vect(data(2));
result(11 DOWNTO 8) := hex_to_bit_vect(data(3));
result(15 DOWNTO 12) := hex_to_bit_vect(data(4));
WHEN OTHERS =>
result(19 DOWNTO 16) := hex_to_bit_vect(data(1));
result(23 DOWNTO 20) := hex_to_bit_vect(data(2));
result(27 DOWNTO 24) := hex_to_bit_vect(data(3));
result(31 DOWNTO 28) := hex_to_bit_vect(data(4));
END CASE;
RETURN result;
END conv_data4;
FUNCTION conv_data8 (data : data_type8) RETURN data_type IS
VARIABLE result : std_logic_vector(31 DOWNTO 0);
BEGIN
result(3 DOWNTO 0) := hex_to_bit_vect(data(1));
result(7 DOWNTO 4) := hex_to_bit_vect(data(2));
result(11 DOWNTO 8) := hex_to_bit_vect(data(3));
result(15 DOWNTO 12) := hex_to_bit_vect(data(4));
result(19 DOWNTO 16) := hex_to_bit_vect(data(5));
result(23 DOWNTO 20) := hex_to_bit_vect(data(6));
result(27 DOWNTO 24) := hex_to_bit_vect(data(7));
result(31 DOWNTO 28) := hex_to_bit_vect(data(8));
RETURN result;
END conv_data8;
END vme_sim_pack;
|
gpl-3.0
|
1ed0ca9ada702a1ce9bce952631b9668
| 0.460593 | 3.853016 | false | false | false | false |
Bourgeoisie/ECE368-RISC16
|
368RISC/ipcore_dir/instruct_blk_mem_gen_v7_3.vhd
| 1 | 5,957 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file instruct_blk_mem_gen_v7_3.vhd when simulating
-- the core, instruct_blk_mem_gen_v7_3. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY instruct_blk_mem_gen_v7_3 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END instruct_blk_mem_gen_v7_3;
ARCHITECTURE instruct_blk_mem_gen_v7_3_a OF instruct_blk_mem_gen_v7_3 IS
-- synthesis translate_off
COMPONENT wrapped_instruct_blk_mem_gen_v7_3
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_instruct_blk_mem_gen_v7_3 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 4,
c_addrb_width => 4,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "20",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "instruct_blk_mem_gen_v7_3.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16,
c_read_depth_b => 16,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16,
c_write_depth_b => 16,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_instruct_blk_mem_gen_v7_3
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END instruct_blk_mem_gen_v7_3_a;
|
mit
|
07d4cb41730fea8aca32ab1a16d10d35
| 0.539533 | 3.775032 | false | false | false | false |
freecores/t48
|
rtl/vhdl/p2.vhd
| 1 | 8,412 |
-------------------------------------------------------------------------------
--
-- The Port 2 unit.
-- Implements the Port 2 logic.
--
-- $Id: p2.vhd,v 1.9 2006-06-20 00:46:04 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
use work.t48_pack.nibble_t;
entity t48_p2 is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
xtal_i : in std_logic;
xtal_en_i : in boolean;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
write_p2_i : in boolean;
write_exp_i : in boolean;
read_p2_i : in boolean;
read_reg_i : in boolean;
read_exp_i : in boolean;
-- Port 2 Interface -------------------------------------------------------
output_pch_i : in boolean;
pch_i : in nibble_t;
p2_i : in word_t;
p2_o : out word_t;
p2l_low_imp_o : out std_logic;
p2h_low_imp_o : out std_logic
);
end t48_p2;
use work.t48_pack.clk_active_c;
use work.t48_pack.res_active_c;
use work.t48_pack.bus_idle_level_c;
architecture rtl of t48_p2 is
-- the port output register
signal p2_q : word_t;
-- the low impedance markers
signal l_low_imp_q,
h_low_imp_q : std_logic;
signal en_clk_q : boolean;
signal l_low_imp_del_q,
h_low_imp_del_q : std_logic;
signal output_pch_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process p2_regs
--
-- Purpose:
-- Implements the port output and expander registers.
--
p2_regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
p2_q <= (others => '1');
l_low_imp_q <= '0';
h_low_imp_q <= '0';
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
-- default: reset low impedance marker
l_low_imp_q <= '0';
h_low_imp_q <= '0';
if write_p2_i then
-- write whole P2
p2_q <= data_i;
l_low_imp_q <= '1';
h_low_imp_q <= '1';
elsif write_exp_i then
-- write lower nibble of P2
p2_q(nibble_t'range) <= data_i(nibble_t'range);
l_low_imp_q <= '1';
end if;
end if;
end if;
end process p2_regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process p2_port
--
-- Purpose:
-- Generates the output byte vector for Port 2.
-- It is a synchronous process clocked with XTAL. This ensures that
-- P2 data and low impedance markers are free of glitches and stabilize
-- during the same clock/machine state.
-- On the other hand, P2 is delayed by 1 XTAL cycle.
--
p2_port: process (res_i, xtal_i)
begin
if res_i = res_active_c then
p2_o <= (others => '1');
l_low_imp_del_q <= '0';
h_low_imp_del_q <= '0';
output_pch_q <= false;
en_clk_q <= false;
elsif xtal_i'event and xtal_i = clk_active_c then
if xtal_en_i then
-- delay clock enable by one XTAL period
en_clk_q <= en_clk_i;
p2_o <= p2_q;
output_pch_q <= output_pch_i;
if output_pch_i then
p2_o(nibble_t'range) <= pch_i;
end if;
-- generate low impedance trigger for one XTAL clock period after
-- global clock enable when
-- a) switching to or from PCH
-- b) l_low_imp_q is active
if en_clk_q and
((output_pch_q xor output_pch_i) or
l_low_imp_q = '1') then
l_low_imp_del_q <= '1';
else
l_low_imp_del_q <= '0';
end if;
-- generate low impedance trigger for on XTAL clock period after
-- global clock enable when
-- h_low_imp_q is active
if en_clk_q and
h_low_imp_q = '1' then
h_low_imp_del_q <= '1';
else
h_low_imp_del_q <= '0';
end if;
end if;
end if;
end process p2_port;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process p2_data
--
-- Purpose:
-- Generates the T48 bus data.
--
p2_data: process (read_p2_i,
p2_i,
read_reg_i,
p2_q,
read_exp_i)
begin
data_o <= (others => bus_idle_level_c);
if read_p2_i then
if read_reg_i then
data_o <= p2_q;
elsif read_exp_i then
data_o <= "0000" & p2_i(nibble_t'range);
else
data_o <= p2_i;
end if;
end if;
end process p2_data;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
p2l_low_imp_o <= l_low_imp_del_q;
p2h_low_imp_o <= h_low_imp_del_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.8 2005/11/01 21:27:55 arniml
-- * change low impedance markers for P2
-- separate marker for low and high part
-- * p2_o output is also registered to prevent combinational
-- output to pads
--
-- Revision 1.7 2005/06/11 10:08:43 arniml
-- introduce prefix 't48_' for all packages, entities and configurations
--
-- Revision 1.6 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.5 2004/05/17 13:52:46 arniml
-- Fix bug "ANL and ORL to P1/P2 read port status instead of port output register"
--
-- Revision 1.4 2004/04/24 23:44:25 arniml
-- move from std_logic_arith to numeric_std
--
-- Revision 1.3 2004/03/29 19:39:58 arniml
-- rename pX_limp to pX_low_imp
--
-- Revision 1.2 2004/03/28 13:11:43 arniml
-- rework Port 2 expander handling
--
-- Revision 1.1 2004/03/23 21:31:53 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
gpl-2.0
|
961c9799f541ff9fd281400f0e0f378f
| 0.517713 | 3.750334 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_v_cresample_0_0/synth/tutorial_v_cresample_0_0.vhd
| 1 | 9,874 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:v_cresample:4.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY v_cresample_v4_0;
USE v_cresample_v4_0.v_cresample;
ENTITY tutorial_v_cresample_0_0 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tuser : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tuser : OUT STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC
);
END tutorial_v_cresample_0_0;
ARCHITECTURE tutorial_v_cresample_0_0_arch OF tutorial_v_cresample_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_v_cresample_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT v_cresample IS
GENERIC (
C_S_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_S_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
C_S_AXIS_VIDEO_FORMAT : INTEGER;
C_M_AXIS_VIDEO_FORMAT : INTEGER;
C_S_AXI_CLK_FREQ_HZ : INTEGER;
C_HAS_AXI4_LITE : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_HAS_DEBUG : INTEGER;
C_FAMILY : STRING;
C_MAX_COLS : INTEGER;
C_ACTIVE_COLS : INTEGER;
C_ACTIVE_ROWS : INTEGER;
C_CHROMA_PARITY : INTEGER;
C_FIELD_PARITY : INTEGER;
C_INTERLACED : INTEGER;
C_NUM_H_TAPS : INTEGER;
C_NUM_V_TAPS : INTEGER;
C_CONVERT_TYPE : INTEGER;
C_COEF_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
intc_if : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
irq : OUT STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tuser : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tuser : OUT STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT v_cresample;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tutorial_v_cresample_0_0_arch: ARCHITECTURE IS "v_cresample,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tutorial_v_cresample_0_0_arch : ARCHITECTURE IS "tutorial_v_cresample_0_0,v_cresample,{v_cresample=hardware_evaluation}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tutorial_v_cresample_0_0_arch: ARCHITECTURE IS "tutorial_v_cresample_0_0,v_cresample,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=v_cresample,x_ipVersion=4.0,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,[email protected](hardware_evaluation),C_S_AXIS_VIDEO_DATA_WIDTH=8,C_M_AXIS_VIDEO_DATA_WIDTH=8,C_S_AXIS_VIDEO_TDATA_WIDTH=24,C_M_AXIS_VIDEO_TDATA_WIDTH=16,C_S_AXIS_VIDEO_FORMAT=1,C_M_AXIS_VIDEO_FORMAT=0,C_S_AXI_CLK_FREQ_HZ=100000000,C_HAS_AXI4_LITE=0,C_HAS_INTC_IF=0,C_HAS_DEBUG=0,C_FAMILY=zynq,C_MAX_COLS=1920,C_ACTIVE_COLS=1920,C_ACTIVE_ROWS=1080,C_CHROMA_PARITY=1,C_FIELD_PARITY=1,C_INTERLACED=0,C_NUM_H_TAPS=3,C_NUM_V_TAPS=0,C_CONVERT_TYPE=2,C_COEF_WIDTH=16}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TUSER";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TLAST";
BEGIN
U0 : v_cresample
GENERIC MAP (
C_S_AXIS_VIDEO_DATA_WIDTH => 8,
C_M_AXIS_VIDEO_DATA_WIDTH => 8,
C_S_AXIS_VIDEO_TDATA_WIDTH => 24,
C_M_AXIS_VIDEO_TDATA_WIDTH => 16,
C_S_AXIS_VIDEO_FORMAT => 1,
C_M_AXIS_VIDEO_FORMAT => 0,
C_S_AXI_CLK_FREQ_HZ => 100000000,
C_HAS_AXI4_LITE => 0,
C_HAS_INTC_IF => 0,
C_HAS_DEBUG => 0,
C_FAMILY => "zynq",
C_MAX_COLS => 1920,
C_ACTIVE_COLS => 1920,
C_ACTIVE_ROWS => 1080,
C_CHROMA_PARITY => 1,
C_FIELD_PARITY => 1,
C_INTERLACED => 0,
C_NUM_H_TAPS => 3,
C_NUM_V_TAPS => 0,
C_CONVERT_TYPE => 2,
C_COEF_WIDTH => 16
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => aresetn,
s_axi_aclk => '0',
s_axi_aclken => '1',
s_axi_aresetn => '1',
s_axis_video_tdata => s_axis_video_tdata,
s_axis_video_tvalid => s_axis_video_tvalid,
s_axis_video_tready => s_axis_video_tready,
s_axis_video_tuser => s_axis_video_tuser,
s_axis_video_tlast => s_axis_video_tlast,
m_axis_video_tdata => m_axis_video_tdata,
m_axis_video_tvalid => m_axis_video_tvalid,
m_axis_video_tready => m_axis_video_tready,
m_axis_video_tuser => m_axis_video_tuser,
m_axis_video_tlast => m_axis_video_tlast,
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
s_axi_arvalid => '0',
s_axi_rready => '0'
);
END tutorial_v_cresample_0_0_arch;
|
gpl-2.0
|
03e4fe469dacde1f570ca9f40c80ed56
| 0.681689 | 3.227852 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_case_statement_GN4KF5KLTA.vhd
| 4 | 1,305 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_case_statement_GN4KF5KLTA is
generic ( number_outputs : integer := 5;
hasDefault : natural := 1;
pipeline : natural := 0;
width : integer := 3);
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(2 downto 0);
r0 : out std_logic;
r1 : out std_logic;
r2 : out std_logic;
r3 : out std_logic;
r4 : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_case_statement_GN4KF5KLTA is
begin
caseproc:process( input )
begin
case input is
when "000" =>
r0 <= '1';
r1 <= '0';
r2 <= '0';
r3 <= '0';
r4 <= '0';
when "001" =>
r0 <= '0';
r1 <= '1';
r2 <= '0';
r3 <= '0';
r4 <= '0';
when "010" =>
r0 <= '0';
r1 <= '0';
r2 <= '1';
r3 <= '0';
r4 <= '0';
when "100" =>
r0 <= '0';
r1 <= '0';
r2 <= '0';
r3 <= '1';
r4 <= '0';
when others =>
r0 <= '0';
r1 <= '0';
r2 <= '0';
r3 <= '0';
r4 <= '1';
end case;
end process;
end architecture;
|
mit
|
dd94b5c115b11030a3270ade46386e7e
| 0.501916 | 2.558824 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_v_rgb2ycrcb_0_0/sim/tutorial_v_rgb2ycrcb_0_0.vhd
| 1 | 9,235 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:v_rgb2ycrcb:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY v_rgb2ycrcb_v7_1;
USE v_rgb2ycrcb_v7_1.v_rgb2ycrcb;
ENTITY tutorial_v_rgb2ycrcb_0_0 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
s_axis_video_tuser_sof : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
m_axis_video_tuser_sof : OUT STD_LOGIC
);
END tutorial_v_rgb2ycrcb_0_0;
ARCHITECTURE tutorial_v_rgb2ycrcb_0_0_arch OF tutorial_v_rgb2ycrcb_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_v_rgb2ycrcb_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT v_rgb2ycrcb IS
GENERIC (
C_S_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_S_AXIS_VIDEO_FORMAT : INTEGER;
C_S_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_FORMAT : INTEGER;
C_M_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
c_s_axi_addr_width : INTEGER;
c_s_axi_data_width : INTEGER;
C_HAS_AXI4_LITE : INTEGER;
C_HAS_DEBUG : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_MAX_COLS : INTEGER;
C_ACTIVE_COLS : INTEGER;
C_ACTIVE_ROWS : INTEGER;
C_HAS_CLIP : INTEGER;
C_HAS_CLAMP : INTEGER;
C_ACOEF : INTEGER;
C_BCOEF : INTEGER;
C_CCOEF : INTEGER;
C_DCOEF : INTEGER;
C_YOFFSET : INTEGER;
C_CBOFFSET : INTEGER;
C_CROFFSET : INTEGER;
C_YMAX : INTEGER;
C_YMIN : INTEGER;
C_CBMAX : INTEGER;
C_CBMIN : INTEGER;
C_CRMAX : INTEGER;
C_CRMIN : INTEGER;
C_S_AXI_CLK_FREQ_HZ : INTEGER;
C_FAMILY : STRING
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
intc_if : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
irq : OUT STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
s_axis_video_tuser_sof : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
m_axis_video_tuser_sof : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT v_rgb2ycrcb;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tuser_sof: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tuser_sof: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TUSER";
BEGIN
U0 : v_rgb2ycrcb
GENERIC MAP (
C_S_AXIS_VIDEO_DATA_WIDTH => 8,
C_S_AXIS_VIDEO_FORMAT => 2,
C_S_AXIS_VIDEO_TDATA_WIDTH => 24,
C_M_AXIS_VIDEO_DATA_WIDTH => 8,
C_M_AXIS_VIDEO_FORMAT => 1,
C_M_AXIS_VIDEO_TDATA_WIDTH => 24,
c_s_axi_addr_width => 9,
c_s_axi_data_width => 32,
C_HAS_AXI4_LITE => 0,
C_HAS_DEBUG => 0,
C_HAS_INTC_IF => 0,
C_MAX_COLS => 1920,
C_ACTIVE_COLS => 1920,
C_ACTIVE_ROWS => 1080,
C_HAS_CLIP => 1,
C_HAS_CLAMP => 1,
C_ACOEF => 19595,
C_BCOEF => 7471,
C_CCOEF => 46727,
C_DCOEF => 36962,
C_YOFFSET => 16,
C_CBOFFSET => 128,
C_CROFFSET => 128,
C_YMAX => 240,
C_YMIN => 16,
C_CBMAX => 240,
C_CBMIN => 16,
C_CRMAX => 240,
C_CRMIN => 16,
C_S_AXI_CLK_FREQ_HZ => 100000000,
C_FAMILY => "zynq"
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => aresetn,
s_axi_aclk => '0',
s_axi_aclken => '1',
s_axi_aresetn => '1',
s_axis_video_tdata => s_axis_video_tdata,
s_axis_video_tready => s_axis_video_tready,
s_axis_video_tvalid => s_axis_video_tvalid,
s_axis_video_tlast => s_axis_video_tlast,
s_axis_video_tuser_sof => s_axis_video_tuser_sof,
m_axis_video_tdata => m_axis_video_tdata,
m_axis_video_tvalid => m_axis_video_tvalid,
m_axis_video_tready => m_axis_video_tready,
m_axis_video_tlast => m_axis_video_tlast,
m_axis_video_tuser_sof => m_axis_video_tuser_sof,
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
s_axi_arvalid => '0',
s_axi_rready => '0'
);
END tutorial_v_rgb2ycrcb_0_0_arch;
|
gpl-2.0
|
1cbc819073af7ee78ccb4c7688c5447f
| 0.659664 | 3.246046 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
16x001-00_src/Source/iram32_sim.vhd
| 1 | 48,645 |
---------------------------------------------------------------
-- Title : Wishbone RAM for simulation
-- Project : -
---------------------------------------------------------------
-- File : iram32_sim.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 13.12.2007
---------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : -
---------------------------------------------------------------
-- Description :
--
-- Simulation Model of a dynamic internal 64-bit wide RAM with wishbone slave interface for single and burst accesses.
--
-- Features:
-- 1. Functions
-- This sim-model provides the following functions: conf_iram, wr_iram, rd_iram and deallocate_iram.
-- 1.1 conf_iram: configure the following parameters: startdelay of address and data phase, waitstates of address and data
-- phase, break delay of address and data phase, enable external waitstate interface
-- 1.2 wr_iram: write data directly to the IRAM (the wishbone interface will not be used).
-- 1.3 rd_iram: read data directly from the IRAM (the wishbone interface will not be used).
-- 1.4 deallocate_iram: free the memory of the IRAM (clear the whole content). The depth of the RAM is 0 afterwards.
--
-- 2. Split transactions
-- The IRAM supports split transactions. Therefore the address phases and the dataphases are seperated (separate acknowledge for address
-- phase and for data phase). To use the IRAM for regular transactions (not split transactions) the address acknowledge shall be used as
-- acknowledge and all data waitstates have to be configured to 0.
--
-- 3. External waitstate interface
-- When the external waitstate interface is enabled by the conf_iram function, the parameters for start delay, waitstates and break delay
-- are not considered. Instead the external waitstate interface is used in the following way.
-- 3.1 Waitstate for one address / data phase are requested by the iram (*_ws_req = true).
-- 3.2 Number of waitstates is provided to the IRAM (*_ws_in).
-- 3.3 Waitstate is acknowledged to the IRAM (*_ws_ack = true).
-- 3.4 Waitstate interface is reset (*_ws_req = false, *_ws_ack = false).
--
-- 4. Internal waitstate generation
-- When the external waitstate interface is disabled by the conf_iram function, the parameters for start delay, waitstates and break delay
-- are considered for address and data acknowledge generation.
-- 4.1 Address startdelay: The address startdelay is the amount of clock cycles from the time where wishbone strobe and cycle are both
-- be active till the first rising edge of the address acknowledge (this is usable for single as well as for
-- burst accesses). The value 0 is invalid for the address startdelay and will be treated as 1.
-- 4.2 Address waitstates: The amount of address waitstates represents the amount of clock cycles between a falling edge of wishbone
-- address acknowledge and the rising edge of wishbone address acknowledge of the next data phase of a burst
-- (this is usable for burst accesses only).
-- 4.3 Address break delay: The address break delay has two parameter for configuration: length and position. The position parameter
-- specifies the amount of dataphases (of a burst) where the break-delay shall appear. The length-parameter is
-- comparative with the waitstates (0 = break delay disabled). If the break-delay is enabled (break delay
-- length > 0) and appears within a burst, no additional waitstates will be produced (even if they are different
-- from 0).
-- 4.4 Data startdelay: The data startdelay is the amount of clock cycles from the time where wishbone address acknowledge is active
-- for the first time till the first rising edge of the data acknowledge (this is usable for single as well as
-- for burst accesses). The value 0 is valid for the address startdelay.
-- 4.5 Data waitstates: The amount of data waitstates represents the amount of clock cycles between a falling edge of wishbone data
-- acknowledge and the rising edge of wishbone data acknowledge of the next data phase of a burst (this is
-- usable for burst accesses only).
-- 4.6 Data break delay: The address break delay has two parameter for configuration: length and position. The position parameter
-- specifies the amount of dataphases (of a burst) where the break-delay shall appear. The length-parameter is
-- comparative with the waitstates (0 = break delay disabled). If the break-delay is enabled (break delay
-- length > 0) and appears within a burst, no additional waitstates will be produced (even if they are different
-- from 0).
--
--
--
--
-- Generation of acknowledge:
--
-- external_ws
-- |
-- +------------+ |
-- | Address | +-----+ +-------------+
-- | Waitstate |------>| MUX |-------->| Address |-----+-------------------------------------------------------> aack
-- | Generation | | | | Acknowledge | |
-- +------------+ | | | Generation | |
-- | | +-------------+ |
-- ext. address waitstates ------>| | |
-- +-----+ | +-------------+
-- | | Data |
-- +-->| Phase |
-- | FIFO |
-- +-------------+
-- |
-- |
-- |
-- external_ws |
-- | | +-------------+
-- +------------+ | +->| Data |-----+------------------------> ack
-- | Data | +-----+ | Acknowledge | |
-- | Waitstates |------>| MUX |--------------------------------------->| Generation | |
-- | Generation | | | +-------------+ |
-- +------------+ | | |
-- | | | +-------------+
-- ext. data waitstates ------>| | +-------------+ +-->| Process |------> dat_o
-- +-----+ | Internal | | Data |
-- | Memory |<--------| Phase |<------ dat_i
-- | | +-------------+
-- +-------------+
--
--
--
---------------------------------------------------------------
-- Hierarchy:
--
-- iram32_sim.vhd
-- iram_pkg.vhd
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.all;
USE ieee.std_logic_textio.all;
USE work.print_pkg.all;
USE work.conversions.to_hex_str;
USE work.iram32_pkg.all;
ENTITY iram32_sim IS
GENERIC (
rddata_sel : boolean := TRUE; -- use wishbone byte select signal for read data
wbname : string := "wbmon";
sets : std_logic_vector(3 DOWNTO 0) := "1110";
-- 1110
-- ||||
-- |||+- write notes to Modelsim out
-- ||+-- write errors to Modelsim out
-- |+--- write notes to file out
-- +---- write errors to file out
timeout : integer := 100;
file_name : string :="iram.txt"
);
PORT (
iram_in : IN iram32_in_type;
iram_out : OUT iram32_out_type;
clk : IN std_logic;
rst : IN std_logic;
stb_i : IN std_logic;
ack_o : OUT std_logic;
aack_o : OUT std_logic;
err_o : OUT std_logic;
we_i : IN std_logic;
sel_i : IN std_logic_vector((DAT_BITS/8)-1 DOWNTO 0);
cti_i : IN std_logic_vector(2 DOWNTO 0);
bte_i : IN std_logic_vector(1 DOWNTO 0);
cyc_i : IN std_logic;
dat_o : OUT std_logic_vector(DAT_BITS-1 DOWNTO 0);
dat_i : IN std_logic_vector(DAT_BITS-1 DOWNTO 0);
adr_i : IN std_logic_vector(ADR_BITS-1 DOWNTO 0);
a_ws_req : OUT boolean;
a_ws_ack : IN boolean;
a_ws_in : IN natural;
d_ws_req : OUT boolean;
d_ws_ack : IN boolean;
d_ws_in : IN natural
);
END iram32_sim;
ARCHITECTURE iram32_sim_arch OF iram32_sim IS
SIGNAL dat_o_int : std_logic_vector(dat_o'range);
SIGNAL ack_o_int : std_logic;
SIGNAL aack_o_int : std_logic;
SIGNAL err_o_int : std_logic;
SIGNAL conf_ack : boolean;
SIGNAL a_ws_req_int: boolean;
SIGNAL a_ws_ack_internal: boolean;
SIGNAL a_ws_ack_int: boolean;
SIGNAL a_ws_end_acc: boolean;
SIGNAL a_ws_int: natural;
SIGNAL a_ws_internal: natural;
SIGNAL d_ws_req_int: boolean;
SIGNAL d_ws_ack_internal: boolean;
SIGNAL d_ws_ack_int: boolean;
SIGNAL d_ws_end_acc: boolean;
SIGNAL d_ws_int: natural;
SIGNAL d_ws_internal: natural;
SIGNAL external_ws: boolean;
SIGNAL aack_enable : boolean;
shared VARIABLE a_sd_stored : protected_shared_variable_natural ;
shared VARIABLE a_ws_stored : protected_shared_variable_natural ;
shared VARIABLE d_sd_stored : protected_shared_variable_natural ;
shared VARIABLE d_ws_stored : protected_shared_variable_natural ;
shared VARIABLE a_bd_pos_stored : protected_shared_variable_natural ;
shared VARIABLE a_bd_len_stored : protected_shared_variable_natural ;
shared VARIABLE d_bd_pos_stored : protected_shared_variable_natural ;
shared VARIABLE d_bd_len_stored : protected_shared_variable_natural ;
CONSTANT DEBUG_MEM_ADR_PHASE : boolean := FALSE;
CONSTANT DEBUG_FIFO_ENTRY : boolean := FALSE;
CONSTANT DEBUG_MEM_DAT_PHASE : boolean := FALSE;
CONSTANT DEBUG_MEM_DATA : boolean := FALSE;
CONSTANT DEBUG_ACK_CHECK : boolean := FALSE;
SIGNAL err: std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL dbg_a_sd: integer := 0;
SIGNAL dbg_a_ws: integer := 0;
SIGNAL dbg_a_sd_valid: boolean := FALSE;
SIGNAL dbg_a_ws_valid: boolean := FALSE;
SIGNAL time_cnt_sig: natural := 0;
SIGNAL dgb_ack: std_logic;
SIGNAL dgb_ack_dut: std_logic;
SIGNAL dbg_a_ws_dat_cnt: integer := 0;
BEGIN
dat_o <= dat_o_int;
ack_o <= ack_o_int;
aack_o <= aack_o_int;
err_o <= err_o_int;
iram_out.conf_ack <= conf_ack;
----------------------------------------------------------------------------------------
-- map internal / external waitstate generation
----------------------------------------------------------------------------------------
a_ws_req <= a_ws_req_int WHEN external_ws ELSE FALSE;
a_ws_ack_int <= a_ws_ack WHEN external_ws ELSE a_ws_ack_internal;
a_ws_int <= a_ws_in WHEN external_ws ELSE a_ws_internal;
d_ws_req <= d_ws_req_int WHEN external_ws ELSE FALSE;
d_ws_ack_int <= d_ws_ack WHEN external_ws ELSE d_ws_ack_internal;
d_ws_int <= d_ws_in WHEN external_ws ELSE d_ws_internal;
----------------------------------------------------------------------------------------
-- internal address waitstate generation
----------------------------------------------------------------------------------------
address_waitstates: PROCESS
VARIABLE dat_cnt : natural;
BEGIN
dat_cnt := 0;
a_ws_ack_internal <= FALSE;
a_ws_internal <= 0;
LOOP
WAIT until a_ws_req_int'event;
IF a_ws_req_int'event AND a_ws_req_int AND NOT external_ws THEN
IF a_ws_end_acc THEN
dat_cnt := 0;
END IF;
IF dat_cnt = 0 THEN
a_ws_internal <= a_sd_stored.get;
ELSIF dat_cnt = a_bd_pos_stored.get AND a_bd_pos_stored.get > 0 AND a_bd_len_stored.get > 0 THEN
a_ws_internal <= a_bd_len_stored.get;
ELSE
a_ws_internal <= a_ws_stored.get;
END IF;
dat_cnt := dat_cnt + 1;
gen_ack(a_ws_req_int, a_ws_ack_internal);
END IF;
dbg_a_ws_dat_cnt <= dat_cnt;
END LOOP;
END PROCESS;
----------------------------------------------------------------------------------------
-- internal data waitstate generation
----------------------------------------------------------------------------------------
data_waitstates: PROCESS
VARIABLE dat_cnt : natural;
BEGIN
dat_cnt := 0;
d_ws_ack_internal <= FALSE;
d_ws_internal <= 0;
LOOP
WAIT until d_ws_req_int'event;
IF d_ws_end_acc THEN
dat_cnt := 0;
END IF;
IF d_ws_req_int'event AND d_ws_req_int AND NOT external_ws THEN
IF dat_cnt = 0 THEN
d_ws_internal <= d_sd_stored.get;
ELSIF dat_cnt = d_bd_pos_stored.get AND d_bd_pos_stored.get > 0 AND d_bd_len_stored.get > 0 THEN
d_ws_internal <= d_bd_len_stored.get;
ELSE
d_ws_internal <= d_ws_stored.get;
END IF;
dat_cnt := dat_cnt + 1;
gen_ack(d_ws_req_int, d_ws_ack_internal);
END IF;
END LOOP;
END PROCESS;
----------------------------------------------------------------------------------------
-- main
----------------------------------------------------------------------------------------
PROCESS
VARIABLE data : std_logic_vector(dat_o'range);
VARIABLE astart_done, dstart_done :boolean;
VARIABLE mem_head : iram32_head_ptr;
VARIABLE allocated : boolean;
VARIABLE acc_req_buf : iram32_acc_req_buffer;
VARIABLE acc_req_wrptr : integer:=0;
VARIABLE acc_req_rdptr : integer:=0;
VARIABLE wradr_buf : iram32_wradr_buffer;
VARIABLE wradr_wrptr : integer:=0;
VARIABLE wradr_rdptr : integer:=0;
VARIABLE wrdat_buf : iram32_wrdat_buffer;
VARIABLE wrdat_wrptr : integer:=0;
VARIABLE wrdat_rdptr : integer:=0;
VARIABLE msg_rd : boolean := FALSE;
VARIABLE msg_wr : boolean := FALSE;
VARIABLE conf_ack_int : boolean;
VARIABLE a_ws_cnt : integer := 0;
VARIABLE d_ws_cnt : integer := 0;
VARIABLE temp_stb_i : std_logic;
VARIABLE temp_ack_o : std_logic;
VARIABLE temp_aack_o : std_logic;
VARIABLE temp_err_o : std_logic;
VARIABLE temp_we_i : std_logic;
VARIABLE temp_sel_i : std_logic_vector(sel_i'range);
VARIABLE temp_cti_i : std_logic_vector(cti_i'range);
VARIABLE temp_bte_i : std_logic_vector(bte_i'range);
VARIABLE temp_cyc_i : std_logic;
VARIABLE temp_dat_o : std_logic_vector(dat_o'range);
VARIABLE temp_dat_i : std_logic_vector(dat_i'range);
VARIABLE temp_adr_i : std_logic_vector(adr_i'range);
VARIABLE aack_o_int_var : std_logic;
VARIABLE ack_o_int_var : std_logic;
VARIABLE adr_int_read : std_logic_vector(adr_i'range);
VARIABLE acc_running : boolean;
VARIABLE time_cnt_var: natural := 0;
VARIABLE st_flag : boolean;
VARIABLE rising_edge_clk: boolean;
BEGIN
mem_head := new iram32_head'(0,null);
IF sets(0) = '1' THEN
msg_rd := TRUE;
msg_wr := TRUE;
END IF;
ack_o_int <= '0';
aack_o_int <= '0';
err_o_int <= '0';
dat_o_int <= (OTHERS => '0');
conf_ack <= iram_in.conf_req;
iram_out.rd_dat <= (OTHERS => '0');
a_ws_req_int <= FALSE;
a_ws_end_acc <= FALSE;
d_ws_req_int <= FALSE;
d_ws_end_acc <= FALSE;
acc_running := FALSE;
acc_req_wrptr := 0;
acc_req_rdptr := 0;
wradr_wrptr := 0;
wradr_rdptr := 0;
wrdat_wrptr := 0;
wrdat_rdptr := 0;
a_ws_cnt := 0;
d_ws_cnt := 0;
astart_done := FALSE;
dstart_done := FALSE;
conf_ack_int := FALSE;
WAIT until rising_edge(clk) AND rst = '0'; -- wait until bus has initialized
a_ws_cnt := 0;
gen_loop: LOOP
-- access running indication (used to delay config accesses when whishbone access is being performed)
IF acc_req_wrptr /= acc_req_rdptr OR (temp_stb_i = '1' AND temp_cyc_i = '1') THEN
acc_running := TRUE;
ELSE
acc_running := FALSE;
END IF;
rising_edge_clk := FALSE;
IF rising_edge(clk) THEN
WAIT FOR 1 ps;
-- store Wishbone signals at delayed rising edge of clk
temp_stb_i := stb_i ;
temp_ack_o := ack_o_int ;
temp_aack_o := aack_o_int ;
temp_err_o := err_o_int ;
temp_we_i := we_i ;
temp_sel_i := sel_i ;
temp_cti_i := cti_i ;
temp_bte_i := bte_i ;
temp_cyc_i := cyc_i ;
temp_dat_o := dat_o_int ;
temp_dat_i := dat_i ;
temp_adr_i := adr_i ;
rising_edge_clk := TRUE;
END IF;
--**************************************************************************************
-- Config Access
--
-- Wait until running accesses have finished and handle config request.
--**************************************************************************************
IF iram_in.conf_req = TRUE AND conf_ack_int = FALSE AND acc_running = FALSE THEN -- config access is only performed when no access is running
IF iram_in.config = TRUE THEN
a_sd_stored.set(iram_in.a_startdelay);
a_ws_stored.set(iram_in.a_waitstates);
d_sd_stored.set(iram_in.d_startdelay);
d_ws_stored.set(iram_in.d_waitstates);
a_bd_pos_stored.set(iram_in.a_break_delay_position);
a_bd_len_stored.set(iram_in.a_break_delay_length);
d_bd_pos_stored.set(iram_in.d_break_delay_position);
d_bd_len_stored.set(iram_in.d_break_delay_length);
external_ws <= iram_in.external_ws;
ELSIF iram_in.write_req = TRUE THEN
-- write to iram
wr_data(to_integer(signed(iram_in.adr)), iram_in.wr_dat, "1111", mem_head, msg_wr);
ELSE
-- read from iram
rd_data(to_integer(signed(iram_in.adr)), data, allocated, mem_head, msg_rd);
iram_out.rd_dat <= data;
END IF;
conf_ack_int := TRUE; -- handshake acknowledge
conf_ack <= conf_ack_int;
WAIT until iram_in.conf_req = FALSE;
conf_ack_int := FALSE; -- handshake acknowledge
conf_ack <= conf_ack_int;
END IF;
IF rising_edge_clk THEN
time_cnt_var := time_cnt_var + 1;
--**************************************************************************************
-- Wishbone Access
--
--**************************************************************************************
IF temp_stb_i = '1' AND temp_cyc_i = '1' THEN
--**************************************************************************************
-- Generate Address Acknowledge
--
-- Detect start of Wishbone access. Request waitstates for the current data phase.
-- Generate address acknowledge after the waitstates have been processed.
-- Indicate the end of an access to the address waitstate generation engine.
--**************************************************************************************
IF temp_we_i = '0' OR (temp_we_i = '1' AND acc_req_wrptr = acc_req_rdptr) THEN
IF NOT astart_done THEN -- detected start of burst
IF DEBUG_MEM_ADR_PHASE THEN REPORT "DEBUG_MEM_ADR_PHASE 1: first address phase detected" SEVERITY NOTE; END IF;
astart_done := TRUE; -- mark start of burst as done
gen_req(a_ws_req_int, a_ws_ack_int); -- get address waitstates
a_ws_end_acc <= FALSE; -- acknowledged by gen_req()
a_ws_cnt := 0; -- set address waitstate counter
adr_int_read := temp_adr_i; -- store address because internally incremented
IF temp_cti_i = "001" OR temp_cti_i = "011" THEN
st_flag := TRUE;
ELSE
st_flag := FALSE;
END IF;
ELSIF temp_aack_o = '1' THEN -- end of burst and acknowledge was set for the last clock cycle
IF DEBUG_MEM_ADR_PHASE THEN REPORT "DEBUG_MEM_ADR_PHASE 2: address phase finished" SEVERITY NOTE; END IF;
gen_req(a_ws_req_int, a_ws_ack_int); -- get address waitstates
-- a_ws_end_acc <= FALSE; -- acknowledged by gen_req()
a_ws_cnt := 0; -- set address waitstate counter
ELSE -- insert waitstate
IF DEBUG_MEM_ADR_PHASE THEN REPORT "DEBUG_MEM_ADR_PHASE 5: ELSE" SEVERITY NOTE; END IF;
IF a_ws_cnt < a_ws_int THEN
a_ws_cnt := a_ws_cnt + 1; -- increment waitstate counter
END IF;
END IF;
END IF;
END IF;
--IF DEBUG_MEM_ADR_PHASE THEN REPORT "DEBUG_MEM_ADR_PHASE 8: a_ws_cnt=" & integer'image(a_ws_cnt) & " a_ws_int=" & integer'image(a_ws_int) SEVERITY NOTE; END IF;
IF astart_done AND a_ws_cnt >= a_ws_int THEN
aack_o_int_var := '1';
ELSE
aack_o_int_var := '0';
END IF;
-- handle end of access for address phase
IF temp_stb_i = '0' OR temp_cyc_i = '0' THEN -- previous clock cycle was idle
astart_done := FALSE;
a_ws_end_acc <= TRUE;
--IF DEBUG_MEM_ADR_PHASE THEN REPORT "DEBUG_MEM_ADR_PHASE 6: set astart_done=false" SEVERITY NOTE; END IF;
ELSIF temp_stb_i = '1' AND temp_cyc_i = '1'AND aack_o_int_var = '1' AND (temp_cti_i = "000" OR temp_cti_i = "111" OR temp_cti_i = "001") THEN -- clock cycle is access and last data phase
astart_done := FALSE;
a_ws_end_acc <= TRUE;
--IF DEBUG_MEM_ADR_PHASE THEN REPORT "DEBUG_MEM_ADR_PHASE 7: set astart_done=false" SEVERITY NOTE; END IF;
END IF;
aack_o_int <= aack_o_int_var;
--**************************************************************************************
-- Store address phase into data phase FIFO
--
-- Store the current address phase.
--**************************************************************************************
IF aack_o_int_var = '1' THEN
IF temp_we_i = '1' THEN -- store address phase in FIFO in case of address acknowledge (write access)
-- store address phase to WRADR FIFO
IF DEBUG_FIFO_ENTRY THEN REPORT "DEBUG_FIFO_ENTRY 1: write: address phase = " & to_hex_str(adr_int_read) SEVERITY NOTE; END IF;
wradr_buf(wradr_wrptr).adr := adr_int_read;
incr(wradr_wrptr, WRDAT_BUFFER_SIZE, WRAP_ON);
END IF;
IF temp_we_i = '1' AND DEBUG_FIFO_ENTRY THEN REPORT "DEBUG_FIFO_ENTRY 2: write to adr_int_read = " & to_hex_str(adr_int_read) SEVERITY NOTE;
ELSIF DEBUG_FIFO_ENTRY THEN REPORT "DEBUG_FIFO_ENTRY 3: read from adr_int_read = " & to_hex_str(adr_int_read) SEVERITY NOTE;
END IF;
acc_req_buf(acc_req_wrptr).we := temp_we_i;
acc_req_buf(acc_req_wrptr).adr := adr_int_read;
acc_req_buf(acc_req_wrptr).cti := temp_cti_i;
acc_req_buf(acc_req_wrptr).eob_flag := FALSE; -- not end of burst delimiter
acc_req_buf(acc_req_wrptr).st_flag := st_flag;
acc_req_buf(acc_req_wrptr).time_cnt := time_cnt_var;
incr(acc_req_wrptr, ACC_REQ_BUFFER_SIZE, WRAP_ON);
IF DAT_BITS = 64 THEN
IF temp_cti_i = "011" AND adr_int_read(4 DOWNTO 3) = "11" THEN -- current address is stored for Linear Incrementing / Cache Line Wrap Burst
adr_int_read := std_logic_vector(unsigned(adr_int_read) - 3*8);
ELSE
adr_int_read := std_logic_vector(unsigned(adr_int_read) + 8);
END IF;
ELSIF DAT_BITS = 32 THEN
IF temp_cti_i = "011" AND adr_int_read(3 DOWNTO 2) = "11" THEN -- current address is stored for Linear Incrementing / Cache Line Wrap Burst
adr_int_read := std_logic_vector(unsigned(adr_int_read) - 3*4);
ELSE
adr_int_read := std_logic_vector(unsigned(adr_int_read) + 4);
END IF;
ELSE
REPORT "WRONG DATA WIDTH " SEVERITY NOTE;
END IF;
END IF;
--**************************************************************************************
-- Store end of access delimiter into data phase FIFO
--
-- Store a delimiter entry into data phase FIFO after the last address phases of an access
-- was stored.
--**************************************************************************************
IF aack_o_int_var = '1' AND (temp_cti_i = "000" OR temp_cti_i = "111" OR temp_cti_i = "001") THEN -- end of burst has been reached -> store delimiter
IF DEBUG_FIFO_ENTRY THEN REPORT "DEBUG_FIFO_ENTRY 1: write eob " SEVERITY NOTE; END IF;
acc_req_buf(acc_req_wrptr).we := '0';
acc_req_buf(acc_req_wrptr).adr := adr_int_read;
acc_req_buf(acc_req_wrptr).cti := temp_cti_i;
acc_req_buf(acc_req_wrptr).eob_flag := TRUE; -- end of burst delimiter
acc_req_buf(acc_req_wrptr).st_flag := FALSE;
acc_req_buf(acc_req_wrptr).time_cnt := time_cnt_var;
incr(acc_req_wrptr, ACC_REQ_BUFFER_SIZE, WRAP_ON);
END IF;
--**************************************************************************************
-- Handle end of access delimiter
--
-- Read all delimers out of data phase FIFO. Set the generation of data acknowledges to
-- an initial state.
--**************************************************************************************
while acc_req_wrptr /= acc_req_rdptr AND acc_req_buf(acc_req_rdptr).eob_flag LOOP -- special buffer entry: end of burst
IF DEBUG_MEM_DAT_PHASE THEN REPORT "DEBUG_MEM_DAT_PHASE 1: eob_flag" SEVERITY NOTE; END IF;
d_ws_end_acc <= TRUE; -- set flag d_ws_end_acc (reset automatic waitstate generation)
dstart_done := FALSE; -- indicate start of read burst is not handled yet
incr(acc_req_rdptr, ACC_REQ_BUFFER_SIZE, WRAP_ON);
END LOOP;
--**************************************************************************************
-- Generate Data Acknowledge
--
-- Read data phases out of data phase FIFO. Request waitstates for the current data phase.
-- Generate data acknowledge after the waitstates have been processed.
-- Indicate the end of an access to the data waitstate generation engine.
--**************************************************************************************
ack_o_int_var := '0';
IF acc_req_wrptr /= acc_req_rdptr THEN
-- write access (any data phase)
IF acc_req_buf(acc_req_rdptr).we = '1' THEN
IF DEBUG_MEM_DAT_PHASE THEN REPORT "DEBUG_MEM_DAT_PHASE 2: write: ack of write access (d_ws_int = 0)" SEVERITY NOTE; END IF;
dstart_done := TRUE; -- indicate start of access was handled
gen_req(d_ws_req_int, d_ws_ack_int); -- get waitstates
d_ws_end_acc <= FALSE;
d_ws_cnt := d_ws_int; -- set waitstate counter to immediately generate the acknowledge (no waitstates for write access)
-- read access (first or following data phase)
ELSIF dstart_done = FALSE OR d_ws_cnt >= d_ws_int THEN
gen_req(d_ws_req_int, d_ws_ack_int); -- get waitstates
d_ws_end_acc <= FALSE;
IF acc_req_buf(acc_req_rdptr).st_flag = TRUE THEN
d_ws_cnt := 0; -- enable data waitstates for split transaction
ELSE
d_ws_cnt := d_ws_int; -- disable data waitstates for non-split transaction
END IF;
IF DEBUG_MEM_DAT_PHASE THEN REPORT "DEBUG_MEM_DAT_PHASE 3: read: dstart_done=" & boolean'image(dstart_done) & " d_ws_cnt=" & integer'image(d_ws_cnt) & ", d_ws_int=" & integer'image(d_ws_int) SEVERITY NOTE; END IF;
-- ensure that data startdelay is hold
IF dstart_done = FALSE THEN
WHILE acc_req_buf(acc_req_rdptr).time_cnt /= time_cnt_var LOOP
d_ws_cnt := d_ws_cnt + 1;
acc_req_buf(acc_req_rdptr).time_cnt := acc_req_buf(acc_req_rdptr).time_cnt + 1;
END LOOP;
END IF;
dstart_done := TRUE; -- indicate start of access was handled
IF DEBUG_MEM_DAT_PHASE THEN REPORT "DEBUG_MEM_DAT_PHASE 3a: read: d_ws_cnt=" & integer'image(d_ws_cnt) & ", d_ws_int=" & integer'image(d_ws_int) SEVERITY NOTE; END IF;
-- insert waitstates for read access
ELSE
IF DEBUG_MEM_DAT_PHASE THEN REPORT "DEBUG_MEM_DAT_PHASE 4: ELSE" SEVERITY NOTE; END IF;
IF d_ws_cnt < d_ws_int THEN
d_ws_cnt := d_ws_cnt + 1; -- increment waitstate counter
END IF;
END IF;
END IF;
-- set data acknowledge in case all waitstates have been processed
IF dstart_done AND d_ws_cnt >= d_ws_int AND acc_req_wrptr /= acc_req_rdptr THEN
ack_o_int_var := '1';
ELSE
ack_o_int_var := '0';
END IF;
--**************************************************************************************
-- Process Data Phase
--
-- Handle the current data phase when the data acknowledge is set. For write accesses
-- write the input data of Wishbone bus to internal memory For read accesses perform a
-- read access to internal memory and output the read data on Wishbone interface.
--**************************************************************************************
IF ack_o_int_var = '1' THEN
IF acc_req_buf(acc_req_rdptr).we = '0' THEN
IF DEBUG_MEM_DATA THEN REPORT "DEBUG_MEM_DATA 1: read data from address " & to_hex_str(acc_req_buf(acc_req_rdptr).adr) SEVERITY NOTE; END IF;
rd_data(to_integer(signed(acc_req_buf(acc_req_rdptr).adr)), data, allocated, mem_head, msg_rd);
dat_o_int <= (OTHERS => '0');
IF rddata_sel THEN
FOR i IN temp_sel_i'low TO temp_sel_i'high LOOP
IF temp_sel_i(i) = '1' THEN
dat_o_int(i*8+7 DOWNTO i*8) <= data(i*8+7 DOWNTO i*8);
END IF;
END LOOP;
ELSE
dat_o_int <= data;
END IF;
ELSE
wr_data(to_integer(signed(acc_req_buf(acc_req_rdptr).adr)), temp_dat_i, temp_sel_i, mem_head, msg_wr);
END IF;
incr(acc_req_rdptr, ACC_REQ_BUFFER_SIZE, WRAP_ON);
END IF;
ack_o_int <= ack_o_int_var;
--**************************************************************************************
-- Handle end of access delimiter (second time - if more access delimiters are stored
-- after end of access)
--
-- Read all delimers out of data phase FIFO. Set the generation of data acknowledges to
-- an initial state.
--**************************************************************************************
while acc_req_wrptr /= acc_req_rdptr AND acc_req_buf(acc_req_rdptr).eob_flag LOOP -- special buffer entry: end of burst
IF DEBUG_MEM_DAT_PHASE THEN REPORT "DEBUG_MEM_DAT_PHASE 1: eob_flag" SEVERITY NOTE; END IF;
d_ws_end_acc <= TRUE; -- set flag d_ws_end_acc (reset automatic waitstate generation)
dstart_done := FALSE; -- indicate start of read burst is not handled yet
incr(acc_req_rdptr, ACC_REQ_BUFFER_SIZE, WRAP_ON);
END LOOP;
END IF;
IF rst /= '1' THEN
WAIT until rising_edge(clk) OR iram_in.conf_req'event OR rst = '1';
END IF;
IF rst = '1' THEN
exit gen_loop;
END IF;
END LOOP gen_loop;
END PROCESS;
--**************************************************************************************
-- Acknowledge Check
--
-- Check address acknowledge: detect startdelay and waitstates and check against the
-- IRAM configuration
-- Check data acknowledge : use IRAM configuration to generate a reference acknowledge
-- and check against data acknowledge of IRAM model
--
-- Note: The acknowledge check is disabled for external waitstates and break delay.
--**************************************************************************************
PROCESS
BEGIN
WAIT until unsigned(err) /= 0;
WAIT until rising_edge(clk);
WAIT until rising_edge(clk);
WAIT until rising_edge(clk);
WAIT until rising_edge(clk);
WAIT until rising_edge(clk);
REPORT "IRAM: END ON ERROR" SEVERITY failure;
END PROCESS;
PROCESS
VARIABLE time_cnt: natural := 0;
CONSTANT ACK_ARRAY_SIZE: natural := 100;
TYPE ack_array_type IS array (ACK_ARRAY_SIZE-1 DOWNTO 0) OF natural;
VARIABLE ack_array: ack_array_type;
VARIABLE ack_array_wrptr: natural;
VARIABLE ack_array_rdptr: natural;
VARIABLE ack_array_last_entry: natural;
VARIABLE first_adr_phase: boolean := TRUE;
VARIABLE a_ws: integer := 0;
VARIABLE a_ws_cnt: integer := 0;
VARIABLE dbg_d_sd_stored: integer;
VARIABLE dbg_d_ws_stored: integer;
VARIABLE st_flag: boolean;
VARIABLE disable: boolean := FALSE;
VARIABLE st_rd_access: boolean;
VARIABLE st_rd_access_q: boolean;
BEGIN
-- initialize aack array
FOR i1 IN ACK_ARRAY_SIZE-1 DOWNTO 0 LOOP
ack_array(i1) := 0;
END LOOP;
ack_array_rdptr := 0;
ack_array_wrptr := 0;
LOOP
WAIT until rising_edge(clk) OR (iram_in.conf_req'event AND iram_in.conf_req = FALSE);
dbg_a_sd_valid <= FALSE;
dbg_a_ws_valid <= FALSE;
IF iram_in.conf_req'event AND iram_in.conf_req = FALSE THEN
dbg_d_sd_stored := iram_in.d_startdelay;
dbg_d_ws_stored := iram_in.d_waitstates;
IF iram_in.d_break_delay_length /= 0 OR
iram_in.d_break_delay_position /= 0 OR
iram_in.a_break_delay_length /= 0 OR
iram_in.a_break_delay_position /= 0 OR
iram_in.external_ws /= FALSE THEN
disable := TRUE;
ELSE
disable := FALSE;
END IF;
END IF;
IF rising_edge(clk) AND NOT disable THEN
dgb_ack_dut <= ack_o_int;
-- check detect aack and store expected ack in FIFO
-- detect address phases
IF stb_i = '1' AND cyc_i = '1' THEN
IF aack_o_int = '1' AND first_adr_phase = TRUE THEN
IF DEBUG_ACK_CHECK THEN print_now("IRAM DEBUG: first address phase with aack=1, a_ws=" & integer'image(a_ws)); END IF;
first_adr_phase := FALSE;
st_rd_access_q := st_rd_access;
IF (cti_i = "011" OR cti_i = "001") AND we_i = '0' THEN
st_rd_access := TRUE;
ELSE
st_rd_access := FALSE;
END IF;
dbg_a_sd <= a_ws_cnt;
IF st_rd_access_q = TRUE AND we_i = '1' THEN
dbg_a_sd_valid <= FALSE;
ELSE
dbg_a_sd_valid <= TRUE;
END IF;
IF cti_i = "001" OR cti_i = "011" THEN
st_flag := TRUE;
ELSE
st_flag := FALSE;
END IF;
IF we_i = '1' OR st_flag = FALSE THEN
ack_array(ack_array_wrptr) := time_cnt;
ELSE
ack_array(ack_array_wrptr) := time_cnt + dbg_d_sd_stored;
ack_array_last_entry := ack_array(ack_array_wrptr);
END IF;
IF ack_array_wrptr = ACK_ARRAY_SIZE-1 THEN
ack_array_wrptr := 0;
ELSE
ack_array_wrptr := ack_array_wrptr + 1;
END IF;
IF ack_array_wrptr = ack_array_rdptr THEN REPORT "FATAL ERROR: ack_array overflow" SEVERITY failure; END IF;
ELSIF aack_o_int = '1' THEN
IF DEBUG_ACK_CHECK THEN print_now("IRAM DEBUG: address phase: cti=0b010, a_ws=" & integer'image(a_ws)); END IF;
dbg_a_ws <= a_ws_cnt;
dbg_a_ws_valid <= TRUE;
IF we_i = '1' OR st_flag = FALSE THEN
ack_array(ack_array_wrptr) := time_cnt;
ELSE
IF time_cnt > ack_array_last_entry+1 THEN
ack_array(ack_array_wrptr) := time_cnt + dbg_d_ws_stored;
ELSE
ack_array(ack_array_wrptr) := ack_array_last_entry+1 + dbg_d_ws_stored;
END IF;
END IF;
ack_array_last_entry := ack_array(ack_array_wrptr);
IF ack_array_wrptr = ACK_ARRAY_SIZE-1 THEN
ack_array_wrptr := 0;
ELSE
ack_array_wrptr := ack_array_wrptr + 1;
END IF;
IF ack_array_wrptr = ack_array_rdptr THEN REPORT "FATAL ERROR: ack_array overflow" SEVERITY failure; END IF;
ELSIF aack_o_int = '0' THEN
a_ws_cnt := a_ws_cnt + 1;
END IF;
END IF;
IF (stb_i = '1' AND cyc_i = '1' AND aack_o_int = '1' AND (cti_i = "000" OR cti_i = "111" OR cti_i = "001") ) OR
stb_i = '0' OR cyc_i = '0' THEN
first_adr_phase := TRUE;
END IF;
IF (stb_i = '1' AND cyc_i = '1' AND aack_o_int = '1' ) OR
stb_i = '0' OR cyc_i = '0' THEN
a_ws_cnt := 0;
END IF;
IF stb_i = '1' AND cyc_i = '1' THEN
IF DEBUG_ACK_CHECK THEN print_now("IRAM DEBUG: a_ws_cnt=" & integer'image(a_ws_cnt)); END IF;
END IF;
-- generate reference ack
dgb_ack <= '0';
IF ack_array_wrptr /= ack_array_rdptr THEN
IF DEBUG_ACK_CHECK THEN print_now("ack_array_wrptr=" & integer'image(ack_array_wrptr) & ", ack_array_rdptr=" & integer'image(ack_array_rdptr)); END IF;
IF DEBUG_ACK_CHECK THEN print_now("ack_array(ack_array_rdptr)=" & integer'image(ack_array(ack_array_rdptr)) & ", time_cnt=" & integer'image(time_cnt)); END IF;
IF time_cnt >= ack_array(ack_array_rdptr) THEN
dgb_ack <= '1';
IF ack_array_rdptr = ACK_ARRAY_SIZE-1 THEN
ack_array_rdptr := 0;
ELSE
ack_array_rdptr := ack_array_rdptr + 1;
END IF;
END IF;
END IF;
time_cnt := time_cnt + 1;
time_cnt_sig <= time_cnt;
END IF;
END LOOP;
END PROCESS;
PROCESS
VARIABLE disable: boolean := FALSE;
BEGIN
WAIT until rising_edge(clk) OR (iram_in.conf_req'event AND iram_in.conf_req = FALSE);
IF iram_in.conf_req'event AND iram_in.conf_req = FALSE THEN
IF iram_in.d_break_delay_length /= 0 OR
iram_in.d_break_delay_position /= 0 OR
iram_in.a_break_delay_length /= 0 OR
iram_in.a_break_delay_position /= 0 OR
iram_in.external_ws /= FALSE THEN
disable := TRUE;
ELSE
disable := FALSE;
END IF;
END IF;
IF rising_edge(clk) AND NOT disable THEN
err(2) <= '0';
IF dgb_ack /= dgb_ack_dut THEN
print_now("ERROR: dgb_ack_dut = " & std_logic'image(dgb_ack_dut) & " but shall be " & std_logic'image(dgb_ack));
err(2) <= '1';
END IF;
END IF;
END PROCESS;
PROCESS
VARIABLE disable: boolean := FALSE;
VARIABLE dbg_a_sd_stored: integer;
BEGIN
WAIT until rising_edge(clk) OR (iram_in.conf_req'event AND iram_in.conf_req = FALSE);
IF iram_in.conf_req'event AND iram_in.conf_req = FALSE THEN
dbg_a_sd_stored := iram_in.a_startdelay;
IF iram_in.d_break_delay_length /= 0 OR
iram_in.d_break_delay_position /= 0 OR
iram_in.a_break_delay_length /= 0 OR
iram_in.a_break_delay_position /= 0 OR
iram_in.external_ws /= FALSE THEN
disable := TRUE;
ELSE
disable := FALSE;
END IF;
END IF;
IF rising_edge(clk) AND NOT disable THEN
IF dbg_a_sd_valid THEN
err(0) <= '0';
IF dbg_a_sd /= dbg_a_sd_stored THEN
print_now("ERROR: dbg_a_sd = " & integer'image(dbg_a_sd) & " but shall be " & integer'image(dbg_a_sd_stored));
err(0) <= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS
VARIABLE disable: boolean := FALSE;
VARIABLE dbg_a_ws_stored: integer;
BEGIN
WAIT until rising_edge(clk) OR (iram_in.conf_req'event AND iram_in.conf_req = FALSE);
IF iram_in.conf_req'event AND iram_in.conf_req = FALSE THEN
dbg_a_ws_stored := iram_in.a_waitstates;
IF iram_in.d_break_delay_length /= 0 OR
iram_in.d_break_delay_position /= 0 OR
iram_in.a_break_delay_length /= 0 OR
iram_in.a_break_delay_position /= 0 OR
iram_in.external_ws /= FALSE THEN
disable := TRUE;
ELSE
disable := FALSE;
END IF;
END IF;
IF rising_edge(clk) AND NOT disable THEN
IF dbg_a_ws_valid THEN
err(1) <= '0';
IF dbg_a_ws /= dbg_a_ws_stored THEN
print_now("ERROR: dbg_a_ws = " & integer'image(dbg_a_ws) & " but shall be " & integer'image(dbg_a_ws_stored));
err(1) <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END iram32_sim_arch;
|
gpl-3.0
|
af41f1a0976af2e27bc86b193bf2043c
| 0.459739 | 4.371013 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_ftch_sm.vhd
| 1 | 47,057 |
-------------------------------------------------------------------------------
-- axi_sg_ftch_sm
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_sm.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 6/10/10 v1_00_a
-- ^^^^^^
-- Fixed issue with fetch idle asserting too soon when simultaneous update
-- decode error and stale descriptor error detected. This fixes CR564855.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 12/07/10 v4_03
-- ^^^^^^
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under
-- associated generate
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_sg_ftch_sm is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
updt_error : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_sg_idle : in std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
ch1_fetch_address : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_sg_idle : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
ch2_fetch_address : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
--
-- DataMover Command --
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
-- DataMover Status --
ftch_done : in std_logic ; --
ftch_error : in std_logic ; --
ftch_interr : in std_logic ; --
ftch_slverr : in std_logic ; --
ftch_decerr : in std_logic ; --
ftch_stale_desc : in std_logic ; --
ftch_error_early : in std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_ftch_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant FETCH_CMD_TAG : std_logic_vector(3 downto 0) := (others => '0');
-- DataMover Command Type
constant FETCH_CMD_TYPE : std_logic := '1';
-- DataMover Cmnd Reserved Bits
constant FETCH_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant FETCH_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0');
-- DataMover Cmnd Bytes to Xfer for Channel 1
constant FETCH_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH1_WORDS_TO_FETCH*4),SG_BTT_WIDTH));
-- DataMover Cmnd Bytes to Xfer for Channel 2
constant FETCH_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH2_WORDS_TO_FETCH*4),SG_BTT_WIDTH));
-- DataMover Cmnd Reserved Bits
constant FETCH_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH)
:= (others => '0');
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate
-- Required width in bits for C_SG_FTCH_DESC2QUEUE
--constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
--
---- Vector version of C_SG_FTCH_DESC2QUEUE
--constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_FTCH_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
FETCH_STATUS,
FETCH_ERROR
);
signal ftch_cs : SG_FTCH_STATE_TYPE;
signal ftch_ns : SG_FTCH_STATE_TYPE;
-- State Machine Signals
signal ch1_active_set : std_logic := '0';
signal ch2_active_set : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal ch1_ftch_sm_idle : std_logic := '0';
signal ch2_ftch_sm_idle : std_logic := '0';
signal ch1_pause_fetch : std_logic := '0';
signal ch2_pause_fetch : std_logic := '0';
-- Misc Signals
signal fetch_cmd_addr : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_active_i : std_logic := '0';
signal service_ch1 : std_logic := '0';
signal ch2_active_i : std_logic := '0';
signal service_ch2 : std_logic := '0';
signal fetch_cmd_btt : std_logic_vector
(SG_BTT_WIDTH-1 downto 0) := (others => '0');
signal ch1_stale_descriptor : std_logic := '0';
signal ch2_stale_descriptor : std_logic := '0';
signal ch1_ftch_interr_set_i : std_logic := '0';
signal ch2_ftch_interr_set_i : std_logic := '0';
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate
-- counts for keeping track of queue descriptors to prevent
-- fifo fill
--signal ch1_desc_ftched_count : std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
--signal ch2_desc_ftched_count : std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ch1_ftch_active <= ch1_active_i;
ch2_ftch_active <= ch2_active_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
SG_FTCH_MACHINE : process(ftch_cs,
ch1_active_i,
ch2_active_i,
service_ch1,
service_ch2,
ftch_error,
ftch_done)
begin
-- Default signal assignment
ch1_active_set <= '0';
ch2_active_set <= '0';
write_cmnd_cmb <= '0';
ch1_ftch_sm_idle <= '0';
ch2_ftch_sm_idle <= '0';
ftch_ns <= ftch_cs;
case ftch_cs is
-------------------------------------------------------------------
when IDLE =>
ch1_ftch_sm_idle <= not service_ch1;
ch2_ftch_sm_idle <= not service_ch2;
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
-- If channel 1 is running and not idle and queue is not full
-- then fetch descriptor for channel 1
elsif(service_ch1 = '1')then
ch1_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- If channel 2 is running and not idle and queue is not full
-- then fetch descriptor for channel 2
elsif(service_ch2 = '1')then
ch2_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
else
ftch_ns <= IDLE;
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
else
ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1;
ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2;
write_cmnd_cmb <= '1';
ftch_ns <= FETCH_STATUS;
end if;
-------------------------------------------------------------------
when FETCH_STATUS =>
ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1;
ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2;
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
elsif(ftch_done = '1')then
-- If just finished fethcing for channel 2 then...
if(ch2_active_i = '1')then
-- If ready, fetch descriptor for channel 1
if(service_ch1 = '1')then
ch1_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Else if channel 2 still ready then fetch
-- another descriptor for channel 2
elsif(service_ch2 = '1')then
ch1_ftch_sm_idle <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Otherwise return to IDLE
else
ftch_ns <= IDLE;
end if;
-- If just finished fethcing for channel 1 then...
elsif(ch1_active_i = '1')then
-- If ready, fetch descriptor for channel 2
if(service_ch2 = '1')then
ch2_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Else if channel 1 still ready then fetch
-- another descriptor for channel 1
elsif(service_ch1 = '1')then
ch2_ftch_sm_idle <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Otherwise return to IDLE
else
ftch_ns <= IDLE;
end if;
else
ftch_ns <= IDLE;
end if;
else
ftch_ns <= FETCH_STATUS;
end if;
-------------------------------------------------------------------
when FETCH_ERROR =>
ch1_ftch_sm_idle <= '1';
ch2_ftch_sm_idle <= '1';
ftch_ns <= FETCH_ERROR;
-------------------------------------------------------------------
when others =>
ftch_ns <= IDLE;
end case;
end process SG_FTCH_MACHINE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_cs <= IDLE;
else
ftch_cs <= ftch_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH1_FETCH : if C_INCLUDE_CH1 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_active_set = '1')then
ch1_active_i <= '0';
elsif(ch1_active_set = '1')then
ch1_active_i <= '1';
end if;
end if;
end process CH1_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 IDLE process. Indicates channel 1 fetch process is IDLE
-- This is 1 part of determining IDLE for a channel
-------------------------------------------------------------------------------
CH1_IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_idle <= '1';
-- SG Error therefore force IDLE
-- CR564855 - fetch idle asserted too soon when update error occured.
-- fetch idle does not need to be concerned with updt_error. This is
-- because on going fetch is guarentteed to complete regardless of dma
-- controller or sg update engine.
--elsif(updt_error = '1' or ftch_error = '1'
elsif(ftch_error = '1'
or ch1_ftch_interr_set_i = '1')then
ch1_ftch_idle <= '1';
-- When SG Fetch no longer idle then clear fetch idle
elsif(ch1_sg_idle = '0')then
ch1_ftch_idle <= '0';
-- If tail = cur and fetch queue is empty then
elsif(ch1_sg_idle = '1' and ch1_ftch_queue_empty = '1' and ch1_ftch_sm_idle = '1')then
ch1_ftch_idle <= '1';
end if;
end if;
end process CH1_IDLE_PROCESS;
-------------------------------------------------------------------------------
-- For No Fetch Queue, generate pause logic to prevent partial descriptor from
-- being fetched and then endless throttle on AXI read bus
-------------------------------------------------------------------------------
GEN_CH1_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
REG_PAUSE_FETCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- On descriptor update done clear pause
if(m_axi_sg_aresetn = '0' or ch1_updt_done = '1')then
ch1_pause_fetch <= '0';
-- If channel active and command written then pause
elsif(ch1_active_i='1' and write_cmnd_cmb = '1')then
ch1_pause_fetch <= '1';
end if;
end if;
end process REG_PAUSE_FETCH;
end generate GEN_CH1_FETCH_PAUSE;
-- Fetch queues so do not need to pause
GEN_CH1_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
-- -- CR585958
-- -- Required width in bits for C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
-- -- Vector version of C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-- signal desc_queued_incr : std_logic := '0';
-- signal desc_queued_decr : std_logic := '0';
--
-- -- CR585958
-- signal ch1_desc_ftched_count: std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
-- begin
--
-- desc_queued_incr <= '1' when ch1_active_i = '1'
-- and write_cmnd_cmb = '1'
-- and ch1_ftch_descpulled = '0'
-- else '0';
--
-- desc_queued_decr <= '1' when ch1_ftch_descpulled = '1'
-- and not (ch1_active_i = '1' and write_cmnd_cmb = '1')
-- else '0';
--
-- -- Keep track of descriptors queued version descriptors updated
-- DESC_FETCHED_CNTR : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch1_desc_ftched_count <= (others => '0');
-- elsif(desc_queued_incr = '1')then
-- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) + 1);
-- elsif(desc_queued_decr = '1')then
-- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) - 1);
-- end if;
-- end if;
-- end process DESC_FETCHED_CNTR;
--
-- REG_PAUSE_FETCH : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch1_pause_fetch <= '0';
-- elsif(ch1_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then
-- ch1_pause_fetch <= '1';
-- else
-- ch1_pause_fetch <= '0';
-- end if;
-- end if;
-- end process REG_PAUSE_FETCH;
--
--
--
ch1_pause_fetch <= ch1_ftch_pause;
end generate GEN_CH1_NO_FETCH_PAUSE;
-------------------------------------------------------------------------------
-- Channel 1 ready to be serviced?
-------------------------------------------------------------------------------
service_ch1 <= '1' when ch1_run_stop = '1' -- Channel running
and ch1_sg_idle = '0' -- SG Engine running
and ch1_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch1_stale_descriptor = '0' -- No Stale Descriptors
and ch1_desc_flush = '0' -- Not flushing desc
and ch1_pause_fetch = '0' -- Not pausing
else '0';
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
INT_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_interr_set_i <= '0';
-- Channel active and datamover int error or fetch done and descriptor stale
elsif((ch1_active_i = '1' and ftch_interr = '1')
or ((ftch_done = '1' or ftch_error = '1') and ch1_stale_descriptor = '1'))then
ch1_ftch_interr_set_i <= '1';
end if;
end if;
end process INT_ERROR_PROCESS;
ch1_ftch_interr_set <= ch1_ftch_interr_set_i;
SLV_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_slverr_set <= '0';
elsif(ch1_active_i = '1' and ftch_slverr = '1')then
ch1_ftch_slverr_set <= '1';
end if;
end if;
end process SLV_ERROR_PROCESS;
DEC_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_decerr_set <= '0';
elsif(ch1_active_i = '1' and ftch_decerr = '1')then
ch1_ftch_decerr_set <= '1';
end if;
end if;
end process DEC_ERROR_PROCESS;
-- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor
-- from being used by dma controller
ch1_ftch_err_early <= '1' when ftch_error_early = '1' and ch1_active_i = '1'
else '0';
-- Enable stale descriptor check
GEN_CH1_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 generate
begin
-----------------------------------------------------------------------
-- Stale Descriptor Error
-----------------------------------------------------------------------
CH1_STALE_DESC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset then clear flag
if(m_axi_sg_aresetn = '0')then
ch1_stale_descriptor <= '0';
elsif(ftch_stale_desc = '1' and ch1_active_i = '1' )then
ch1_stale_descriptor <= '1';
end if;
end if;
end process CH1_STALE_DESC;
end generate GEN_CH1_STALE_CHECK;
-- Disable stale descriptor check
GEN_CH1_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 generate
begin
ch1_stale_descriptor <= '0';
end generate GEN_CH1_NO_STALE_CHECK;
-- Early detection of Stale Descriptor (valid only in tailpntr mode) used
-- to prevent error'ed descriptor from being used.
ch1_ftch_stale_desc <= ch1_stale_descriptor;
end generate GEN_CH1_FETCH;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH1_FETCH : if C_INCLUDE_CH1 = 0 generate
begin
service_ch1 <= '0';
ch1_active_i <= '0';
ch1_ftch_idle <= '0';
ch1_ftch_interr_set <= '0';
ch1_ftch_slverr_set <= '0';
ch1_ftch_decerr_set <= '0';
ch1_ftch_err_early <= '0';
ch1_ftch_stale_desc <= '0';
end generate GEN_NO_CH1_FETCH;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH2_FETCH : if C_INCLUDE_CH2 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_active_set = '1')then
ch2_active_i <= '0';
elsif(ch2_active_set = '1')then
ch2_active_i <= '1';
end if;
end if;
end process CH2_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 2 IDLE process. Indicates channel 2 fetch process is IDLE
-- This is 1 part of determining IDLE for a channel
-------------------------------------------------------------------------------
CH2_IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_idle <= '1';
-- SG Error therefore force IDLE
-- CR564855 - fetch idle asserted too soon when update error occured.
-- fetch idle does not need to be concerned with updt_error. This is
-- because on going fetch is guarentteed to complete regardless of dma
-- controller or sg update engine.
-- elsif(updt_error = '1' or ftch_error = '1'
elsif(ftch_error = '1'
or ch2_ftch_interr_set_i = '1')then
ch2_ftch_idle <= '1';
-- When SG Fetch no longer idle then clear fetch idle
elsif(ch2_sg_idle = '0')then
ch2_ftch_idle <= '0';
-- If tail = cur and fetch queue is empty then
elsif(ch2_sg_idle = '1' and ch2_ftch_queue_empty = '1' and ch2_ftch_sm_idle = '1')then
ch2_ftch_idle <= '1';
end if;
end if;
end process CH2_IDLE_PROCESS;
-------------------------------------------------------------------------------
-- For No Fetch Queue, generate pause logic to prevent partial descriptor from
-- being fetched and then endless throttle on AXI read bus
-------------------------------------------------------------------------------
GEN_CH2_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
REG_PAUSE_FETCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- On descriptor update done clear pause
if(m_axi_sg_aresetn = '0' or ch2_updt_done = '1')then
ch2_pause_fetch <= '0';
-- If channel active and command written then pause
elsif(ch2_active_i='1' and write_cmnd_cmb = '1')then
ch2_pause_fetch <= '1';
end if;
end if;
end process REG_PAUSE_FETCH;
end generate GEN_CH2_FETCH_PAUSE;
-- Fetch queues so do not need to pause
GEN_CH2_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
-- -- CR585958
-- -- Required width in bits for C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
-- -- Vector version of C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-- signal desc_queued_incr : std_logic := '0';
-- signal desc_queued_decr : std_logic := '0';
--
-- -- CR585958
-- signal ch2_desc_ftched_count: std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
--
-- begin
--
-- desc_queued_incr <= '1' when ch2_active_i = '1'
-- and write_cmnd_cmb = '1'
-- and ch2_ftch_descpulled = '0'
-- else '0';
--
-- desc_queued_decr <= '1' when ch2_ftch_descpulled = '1'
-- and not (ch2_active_i = '1' and write_cmnd_cmb = '1')
-- else '0';
--
-- -- Keep track of descriptors queued version descriptors updated
-- DESC_FETCHED_CNTR : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch2_desc_ftched_count <= (others => '0');
-- elsif(desc_queued_incr = '1')then
-- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) + 1);
-- elsif(desc_queued_decr = '1')then
-- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) - 1);
-- end if;
-- end if;
-- end process DESC_FETCHED_CNTR;
--
-- REG_PAUSE_FETCH : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch2_pause_fetch <= '0';
-- elsif(ch2_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then
-- ch2_pause_fetch <= '1';
-- else
-- ch2_pause_fetch <= '0';
-- end if;
-- end if;
-- end process REG_PAUSE_FETCH;
--
ch2_pause_fetch <= ch2_ftch_pause;
end generate GEN_CH2_NO_FETCH_PAUSE;
-------------------------------------------------------------------------------
-- Channel 2 ready to be serviced?
-------------------------------------------------------------------------------
service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running
and ch2_sg_idle = '0' -- SG Engine running
and ch2_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch2_stale_descriptor = '0' -- No Stale Descriptors
and ch2_desc_flush = '0' -- Not flushing desc
and ch2_pause_fetch = '0' -- No fetch pause
else '0';
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
INT_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_interr_set_i <= '0';
-- Channel active and datamover int error or fetch done and descriptor stale
elsif((ch2_active_i = '1' and ftch_interr = '1')
or ((ftch_done = '1' or ftch_error = '1') and ch2_stale_descriptor = '1'))then
ch2_ftch_interr_set_i <= '1';
end if;
end if;
end process INT_ERROR_PROCESS;
ch2_ftch_interr_set <= ch2_ftch_interr_set_i;
SLV_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_slverr_set <= '0';
elsif(ch2_active_i = '1' and ftch_slverr = '1')then
ch2_ftch_slverr_set <= '1';
end if;
end if;
end process SLV_ERROR_PROCESS;
DEC_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_decerr_set <= '0';
elsif(ch2_active_i = '1' and ftch_decerr = '1')then
ch2_ftch_decerr_set <= '1';
end if;
end if;
end process DEC_ERROR_PROCESS;
-- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor
-- from being used by dma controller
ch2_ftch_err_early <= '1' when ftch_error_early = '1' and ch2_active_i = '1'
else '0';
-- Enable stale descriptor check
GEN_CH2_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 1 generate
begin
-----------------------------------------------------------------------
-- Stale Descriptor Error
-----------------------------------------------------------------------
CH2_STALE_DESC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset then clear flag
if(m_axi_sg_aresetn = '0')then
ch2_stale_descriptor <= '0';
elsif(ftch_stale_desc = '1' and ch2_active_i = '1' )then
ch2_stale_descriptor <= '1';
end if;
end if;
end process CH2_STALE_DESC;
end generate GEN_CH2_STALE_CHECK;
-- Disable stale descriptor check
GEN_CH2_NO_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 0 generate
begin
ch2_stale_descriptor <= '0';
end generate GEN_CH2_NO_STALE_CHECK;
-- Early detection of Stale Descriptor (valid only in tailpntr mode) used
-- to prevent error'ed descriptor from being used.
ch2_ftch_stale_desc <= ch2_stale_descriptor;
end generate GEN_CH2_FETCH;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH2_FETCH : if C_INCLUDE_CH2 = 0 generate
begin
service_ch2 <= '0';
ch2_active_i <= '0';
ch2_ftch_idle <= '0';
ch2_ftch_interr_set <= '0';
ch2_ftch_slverr_set <= '0';
ch2_ftch_decerr_set <= '0';
ch2_ftch_err_early <= '0';
ch2_ftch_stale_desc <= '0';
end generate GEN_NO_CH2_FETCH;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- Assign fetch address
fetch_cmd_addr <= ch1_fetch_address when ch1_active_i = '1'
else ch2_fetch_address;
-- Assign bytes to transfer (BTT)
fetch_cmd_btt <= FETCH_CH1_CMD_BTT when ch1_active_i = '1'
else FETCH_CH2_CMD_BTT;
-- When command by sm, drive command to ftch_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_cmnd_wr <= '0';
ftch_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
elsif(write_cmnd_cmb = '1')then
ftch_cmnd_wr <= '1';
ftch_cmnd_data <= FETCH_CMD_RSVD
& FETCH_CMD_TAG
& fetch_cmd_addr
& FETCH_MSB_IGNORED
& FETCH_CMD_TYPE
& FETCH_LSB_IGNORED
& fetch_cmd_btt;
else
ftch_cmnd_wr <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- Capture and hold fetch address in case an error occurs
-------------------------------------------------------------------------------
LOG_ERROR_ADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error_addr <= (others => '0');
elsif(write_cmnd_cmb = '1')then
ftch_error_addr <= fetch_cmd_addr;
end if;
end if;
end process LOG_ERROR_ADDR;
end implementation;
|
gpl-2.0
|
40fd16496e20e435449db4db5b80f30f
| 0.42032 | 4.447311 | false | false | false | false |
freecores/t48
|
rtl/vhdl/decoder.vhd
| 1 | 67,801 |
-------------------------------------------------------------------------------
--
-- The Decoder unit.
-- It decodes the instruction opcodes and executes them.
--
-- $Id: decoder.vhd,v 1.27 2008-05-02 21:20:41 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
use work.t48_pack.mstate_t;
use work.t48_alu_pack.alu_op_t;
use work.t48_cond_branch_pack.all;
use work.t48_dmem_ctrl_pack.all;
use work.t48_pmem_ctrl_pack.all;
entity t48_decoder is
generic (
-- store mnemonic in flip-flops (registered-out)
register_mnemonic_g : integer := 1
);
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
xtal_i : in std_logic;
xtal_en_i : in boolean;
ea_i : in std_logic;
ale_i : in boolean;
int_n_i : in std_logic;
t0_dir_o : out std_logic;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
alu_write_accu_o : out boolean;
alu_write_shadow_o : out boolean;
alu_write_temp_reg_o : out boolean;
alu_read_alu_o : out boolean;
bus_write_bus_o : out boolean;
bus_read_bus_o : out boolean;
dm_write_dmem_addr_o : out boolean;
dm_write_dmem_o : out boolean;
dm_read_dmem_o : out boolean;
p1_write_p1_o : out boolean;
p1_read_p1_o : out boolean;
p2_write_p2_o : out boolean;
p2_write_exp_o : out boolean;
p2_read_p2_o : out boolean;
p2_read_exp_o : out boolean;
pm_write_pcl_o : out boolean;
pm_read_pcl_o : out boolean;
pm_write_pch_o : out boolean;
pm_read_pch_o : out boolean;
pm_read_pmem_o : out boolean;
psw_read_psw_o : out boolean;
psw_read_sp_o : out boolean;
psw_write_psw_o : out boolean;
psw_write_sp_o : out boolean;
-- ALU Interface ----------------------------------------------------------
alu_carry_i : in std_logic;
alu_op_o : out alu_op_t;
alu_use_carry_o : out boolean;
alu_da_high_o : out boolean;
alu_accu_low_o : out boolean;
alu_p06_temp_reg_o : out boolean;
alu_p60_temp_reg_o : out boolean;
alu_da_overflow_i : in boolean;
-- BUS Interface ----------------------------------------------------------
bus_output_pcl_o : out boolean;
bus_bidir_bus_o : out boolean;
-- Clock Controller Interface ---------------------------------------------
clk_multi_cycle_o : out boolean;
clk_assert_psen_o : out boolean;
clk_assert_prog_o : out boolean;
clk_assert_rd_o : out boolean;
clk_assert_wr_o : out boolean;
clk_mstate_i : in mstate_t;
clk_second_cycle_i : in boolean;
-- Conditional Branch Logic Interface -------------------------------------
cnd_compute_take_o : out boolean;
cnd_branch_cond_o : out branch_conditions_t;
cnd_take_branch_i : in boolean;
cnd_comp_value_o : out comp_value_t;
cnd_f1_o : out std_logic;
cnd_tf_o : out std_logic;
-- Data Memory Controller Interface ---------------------------------------
dm_addr_type_o : out dmem_addr_ident_t;
-- Port 1 Interface -------------------------------------------------------
p1_read_reg_o : out boolean;
-- Port 2 Interface -------------------------------------------------------
p2_read_reg_o : out boolean;
p2_output_pch_o : out boolean;
-- Program Memory Controller Interface ------------------------------------
pm_inc_pc_o : out boolean;
pm_write_pmem_addr_o : out boolean;
pm_addr_type_o : out pmem_addr_ident_t;
-- Program Status Word Interface ------------------------------------------
psw_special_data_o : out std_logic;
psw_carry_i : in std_logic;
psw_aux_carry_i : in std_logic;
psw_f0_i : in std_logic;
psw_inc_stackp_o : out boolean;
psw_dec_stackp_o : out boolean;
psw_write_carry_o : out boolean;
psw_write_aux_carry_o : out boolean;
psw_write_f0_o : out boolean;
psw_write_bs_o : out boolean;
-- Timer Interface --------------------------------------------------------
tim_read_timer_o : out boolean;
tim_write_timer_o : out boolean;
tim_start_t_o : out boolean;
tim_start_cnt_o : out boolean;
tim_stop_tcnt_o : out boolean;
tim_overflow_i : in boolean
);
end t48_decoder;
use work.t48_pack.all;
use work.t48_alu_pack.all;
use work.t48_decoder_pack.all;
use work.t48_comp_pack.t48_int;
-- pragma translate_off
use work.t48_tb_pack.tb_istrobe_s;
-- pragma translate_on
architecture rtl of t48_decoder is
-- Enable fixing a bug of Quartus II 4.0
constant enable_quartus_bugfix_c : boolean := true;
-- Opcode Decoder
signal opc_multi_cycle_s : boolean;
signal opc_read_bus_s : boolean;
signal opc_inj_int_s : boolean;
signal opc_opcode_q : word_t;
signal opc_mnemonic_s : mnemonic_t;
signal last_cycle_s : boolean;
-- state translators
signal assert_psen_s : boolean;
-- branch taken handshake
signal branch_taken_s,
branch_taken_q : boolean;
signal pm_inc_pc_s : boolean;
signal pm_write_pmem_addr_s : boolean;
-- additional signal to increment PC during CALL
signal add_inc_pc_s : boolean;
-- addtional signal to set PC during RET(R)
signal add_write_pmem_addr_s : boolean;
-- Flag 1
signal clear_f1_s,
cpl_f1_s : boolean;
signal f1_q : std_logic;
-- memory bank select
signal clear_mb_s,
set_mb_s : boolean;
signal mb_q : std_logic;
-- T0 direction selection
signal ent0_clk_s : boolean;
signal t0_dir_q : std_logic;
signal data_s : word_t;
signal read_dec_s : boolean;
signal tf_s : std_logic;
signal bus_read_bus_s : boolean;
signal add_read_bus_s : boolean;
signal dm_write_dmem_s : boolean;
signal p2_output_exp_s : boolean;
signal movx_first_cycle_s : boolean;
-- interrupt handling
signal jtf_executed_s : boolean;
signal en_tcnti_s : boolean;
signal dis_tcnti_s : boolean;
signal en_i_s : boolean;
signal dis_i_s : boolean;
signal tim_int_s : boolean;
signal retr_executed_s : boolean;
signal int_executed_s : boolean;
signal int_pending_s : boolean;
signal int_in_progress_s : boolean;
-- the mnemonic
signal mnemonic_rec_s : mnemonic_rec_t;
signal mnemonic_q : mnemonic_t;
-- pragma translate_off
signal istrobe_res_q : std_logic;
signal istrobe_q : std_logic;
signal injected_int_q : std_logic;
-- pragma translate_on
begin
-- pragma translate_off
-- Register Mnemonic --------------------------------------------------------
assert (register_mnemonic_g = 1) or (register_mnemonic_g = 0)
report "register_mnemonic_g must be either 1 or 0!"
severity failure;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Opcode Decoder
--
mnemonic_rec_s <= decode_opcode_f(opcode => opc_opcode_q);
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process opc_regs
--
-- Purpose:
-- Implements the opcode and mnemonic registers.
--
opc_regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
opc_opcode_q <= (others => '0'); -- NOP
mnemonic_q <= MN_NOP;
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
if opc_read_bus_s then
opc_opcode_q <= data_i;
elsif opc_inj_int_s then
opc_opcode_q <= "00010100";
else
mnemonic_q <= mnemonic_rec_s.mnemonic;
end if;
end if;
end if;
end process opc_regs;
--
opc_multi_cycle_s <= mnemonic_rec_s.multi_cycle;
opc_mnemonic_s <= mnemonic_q
when register_mnemonic_g = 1 else
mnemonic_rec_s.mnemonic;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Interrupt Controller.
-----------------------------------------------------------------------------
int_b : t48_int
port map (
clk_i => clk_i,
res_i => res_i,
en_clk_i => en_clk_i,
xtal_i => xtal_i,
xtal_en_i => xtal_en_i,
clk_mstate_i => clk_mstate_i,
jtf_executed_i => jtf_executed_s,
tim_overflow_i => tim_overflow_i,
tf_o => tf_s,
en_tcnti_i => en_tcnti_s,
dis_tcnti_i => dis_tcnti_s,
int_n_i => int_n_i,
ale_i => ale_i,
last_cycle_i => last_cycle_s,
en_i_i => en_i_s,
dis_i_i => dis_i_s,
ext_int_o => open,
tim_int_o => tim_int_s,
retr_executed_i => retr_executed_s,
int_executed_i => int_executed_s,
int_pending_o => int_pending_s,
int_in_progress_o => int_in_progress_s
);
last_cycle_s <= not opc_multi_cycle_s or
(opc_multi_cycle_s and clk_second_cycle_i);
-----------------------------------------------------------------------------
-- Process machine_cycle
--
-- Purpose:
-- Generates the control signals that are basically needed for the
-- handling of a machine cycle.
--
machine_cycle: process (clk_mstate_i,
clk_second_cycle_i,
last_cycle_s,
ea_i,
assert_psen_s,
branch_taken_q,
int_pending_s,
p2_output_exp_s,
movx_first_cycle_s)
variable need_address_v : boolean;
begin
-- default assignments
clk_assert_psen_o <= false;
pm_inc_pc_s <= false;
pm_write_pmem_addr_s <= false;
pm_read_pmem_o <= false;
bus_output_pcl_o <= false;
p2_output_pch_o <= false;
opc_read_bus_s <= false;
opc_inj_int_s <= false;
bus_read_bus_s <= false;
need_address_v := not clk_second_cycle_i or
(clk_second_cycle_i and assert_psen_s);
case clk_mstate_i is
when MSTATE1 =>
if need_address_v then
if ea_i = '0' then
if not int_pending_s then
pm_read_pmem_o <= true;
end if;
else
if not int_pending_s then
bus_read_bus_s <= true;
end if;
p2_output_pch_o <= true;
end if;
end if;
if not clk_second_cycle_i then
if not int_pending_s then
opc_read_bus_s <= true;
else
opc_inj_int_s <= true; -- inject interrupt call
end if;
end if;
when MSTATE2 =>
if need_address_v and not branch_taken_q and
not int_pending_s then
pm_inc_pc_s <= true;
end if;
when MSTATE3 =>
if need_address_v then
-- Theory of operation:
-- Program Memory address is updated at end of State 3 (or end of
-- State 2 in case of a RET). Address information is thus available
-- latest with State 4.
-- This is the time where we need information about access target
-- (internal or external = EA). EA information needs to be stable
-- until end of State 1.
pm_write_pmem_addr_s <= true;
end if;
when MSTATE4 =>
if ea_i = '1' and
((not clk_second_cycle_i and assert_psen_s)
or last_cycle_s) then
clk_assert_psen_o <= true;
p2_output_pch_o <= true;
bus_output_pcl_o <= true;
end if;
when MSTATE5 =>
if ea_i = '1' and
(need_address_v or last_cycle_s) and
-- Suppress output of PCH when either
-- a) expander port is driven on P2, has priority
not p2_output_exp_s and
-- b) first cycle of MOVX, don't disturb external access
not movx_first_cycle_s then
p2_output_pch_o <= true;
end if;
when others =>
-- pragma translate_off
assert false
report "Unkown machine state!"
severity error;
-- pragma translate_on
end case;
end process machine_cycle;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process decode
--
-- Purpose:
-- Indentifies each single instruction and steps through the related
-- execution sequence.
--
decode: process (alu_carry_i,
psw_aux_carry_i,
alu_da_overflow_i,
clk_mstate_i,
clk_second_cycle_i,
cnd_take_branch_i,
opc_opcode_q,
opc_mnemonic_s,
psw_carry_i,
psw_f0_i,
f1_q,
mb_q,
tim_int_s,
int_pending_s,
int_in_progress_s)
procedure address_indirect_3_f is
begin
-- apply dmem address from selected register for indirect mode
if opc_opcode_q(3) = '0' or enable_quartus_bugfix_c then
dm_read_dmem_o <= true;
dm_write_dmem_addr_o <= true;
dm_addr_type_o <= DM_PLAIN;
end if;
end;
procedure and_or_xor_add_4_f is
begin
-- write dmem contents to Temp Reg
dm_read_dmem_o <= true;
alu_write_temp_reg_o <= true;
end;
procedure and_or_xor_add_5_f (alu_op : alu_op_t) is
begin
-- perform ALU operation and store in Accumulator
alu_op_o <= alu_op;
alu_read_alu_o <= true;
alu_write_accu_o <= true;
end;
procedure cond_jump_c2_m1_f is
begin
-- store address in Program Counter low byte if branch has to
-- be taken
-- if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
pm_write_pcl_o <= true;
branch_taken_s <= true;
-- end if;
end;
-- intermediate value of the Program Memory Bank Flag
variable mb_v : std_logic;
begin
-- default assignments
data_s <= (others => '-');
read_dec_s <= false;
branch_taken_s <= false;
clear_f1_s <= false;
cpl_f1_s <= false;
clear_mb_s <= false;
set_mb_s <= false;
add_inc_pc_s <= false;
assert_psen_s <= false;
alu_write_accu_o <= false;
alu_write_shadow_o <= false;
alu_write_temp_reg_o <= false;
alu_p06_temp_reg_o <= false;
alu_p60_temp_reg_o <= false;
alu_read_alu_o <= false;
bus_write_bus_o <= false;
bus_bidir_bus_o <= false;
dm_write_dmem_addr_o <= false;
dm_write_dmem_s <= false;
dm_read_dmem_o <= false;
pm_write_pcl_o <= false;
pm_read_pcl_o <= false;
pm_write_pch_o <= false;
pm_read_pch_o <= false;
pm_addr_type_o <= PM_PC;
psw_read_psw_o <= false;
psw_read_sp_o <= false;
psw_write_psw_o <= false;
psw_write_sp_o <= false;
alu_op_o <= ALU_NOP;
alu_use_carry_o <= false;
alu_da_high_o <= false;
alu_accu_low_o <= false;
clk_assert_prog_o <= false;
clk_assert_rd_o <= false;
clk_assert_wr_o <= false;
cnd_branch_cond_o <= COND_ON_BIT;
cnd_compute_take_o <= false;
cnd_comp_value_o <= opc_opcode_q(7 downto 5);
dm_addr_type_o <= DM_REG;
tim_read_timer_o <= false;
tim_write_timer_o <= false;
tim_start_t_o <= false;
tim_start_cnt_o <= false;
tim_stop_tcnt_o <= false;
p1_write_p1_o <= false;
p1_read_p1_o <= false;
p1_read_reg_o <= false;
p2_write_p2_o <= false;
p2_write_exp_o <= false;
p2_read_p2_o <= false;
p2_read_reg_o <= false;
p2_read_exp_o <= false;
p2_output_exp_s <= false;
psw_special_data_o <= '0';
psw_inc_stackp_o <= false;
psw_dec_stackp_o <= false;
psw_write_carry_o <= false;
psw_write_aux_carry_o <= false;
psw_write_f0_o <= false;
psw_write_bs_o <= false;
jtf_executed_s <= false;
en_tcnti_s <= false;
dis_tcnti_s <= false;
en_i_s <= false;
dis_i_s <= false;
retr_executed_s <= false;
int_executed_s <= false;
add_write_pmem_addr_s <= false;
ent0_clk_s <= false;
add_read_bus_s <= false;
movx_first_cycle_s <= false;
-- the Program Memory Bank Flag is held low when interrupts are in progress
-- according to the MCS-48 User's Manual
if int_in_progress_s then
mb_v := '0';
else
mb_v := mb_q;
end if;
-- prepare potential register indirect address mode
if not clk_second_cycle_i and clk_mstate_i = MSTATE2 then
data_s <= (others => '0');
if opc_opcode_q(3) = '1' then
data_s(2 downto 0) <= opc_opcode_q(2 downto 0);
else
data_s(2 downto 0) <= "00" & opc_opcode_q(0);
end if;
read_dec_s <= true;
dm_write_dmem_addr_o <= true;
dm_addr_type_o <= DM_REG;
end if;
case opc_mnemonic_s is
-- Mnemonic ADD ---------------------------------------------------------
when MN_ADD =>
case clk_mstate_i is
-- read RAM once for indirect address mode
when MSTATE3 =>
if not enable_quartus_bugfix_c or
opc_opcode_q(3) = '0' then
address_indirect_3_f;
end if;
-- store data from RAM to Temp Reg
when MSTATE4 =>
and_or_xor_add_4_f;
-- perform ADD and store in Accumulator
when MSTATE5 =>
and_or_xor_add_5_f(alu_op => ALU_ADD);
if opc_opcode_q(4) = '1' then
alu_use_carry_o <= true;
end if;
psw_special_data_o <= alu_carry_i;
psw_write_carry_o <= true;
psw_write_aux_carry_o <= true;
when others =>
null;
end case;
-- Mnemonic ADD_A_DATA --------------------------------------------------
when MN_ADD_A_DATA =>
assert_psen_s <= true;
if clk_second_cycle_i then
case clk_mstate_i is
-- write Temp Reg when contents of Program Memory is on bus
when MSTATE1 =>
alu_write_temp_reg_o <= true;
-- perform ADD and store in Accumulator
when MSTATE3 =>
and_or_xor_add_5_f(alu_op => ALU_ADD);
if opc_opcode_q(4) = '1' then
alu_use_carry_o <= true;
end if;
psw_special_data_o <= alu_carry_i;
psw_write_carry_o <= true;
psw_write_aux_carry_o <= true;
when others =>
null;
end case;
end if;
-- Mnemonic ANL ---------------------------------------------------------
when MN_ANL =>
case clk_mstate_i is
-- read RAM once for indirect address mode
when MSTATE3 =>
if not enable_quartus_bugfix_c or
opc_opcode_q(3) = '0' then
address_indirect_3_f;
end if;
-- store data from RAM to Temp Reg
when MSTATE4 =>
and_or_xor_add_4_f;
-- perform AND and store in Accumulator
when MSTATE5 =>
and_or_xor_add_5_f(alu_op => ALU_AND);
when others =>
null;
end case;
-- Mnemonic ANL_A_DATA --------------------------------------------------
when MN_ANL_A_DATA =>
assert_psen_s <= true;
if clk_second_cycle_i then
case clk_mstate_i is
-- write Temp Reg when contents of Program Memory is on bus
when MSTATE1 =>
alu_write_temp_reg_o <= true;
-- perform AND and store in Accumulator
when MSTATE3 =>
and_or_xor_add_5_f(alu_op => ALU_AND);
when others =>
null;
end case;
end if;
-- Mnemonic ANL_EXT -----------------------------------------------------
when MN_ANL_EXT =>
assert_psen_s <= true;
if not clk_second_cycle_i then
-- read port to Temp Reg
if clk_mstate_i = MSTATE5 then
if opc_opcode_q(1 downto 0) = "00" then
add_read_bus_s <= true;
elsif opc_opcode_q(1) = '0' then
p1_read_p1_o <= true;
p1_read_reg_o <= true;
else
p2_read_p2_o <= true;
p2_read_reg_o <= true;
end if;
alu_write_temp_reg_o <= true;
end if;
else
case clk_mstate_i is
-- write shadow Accumulator when contents of Program Memory is
-- on bus
when MSTATE1 =>
alu_write_shadow_o <= true;
-- loop shadow Accumulator through ALU to prevent update from
-- real Accumulator
when MSTATE2 =>
alu_read_alu_o <= true;
alu_write_shadow_o <= true;
-- write result of AND operation back to port
when MSTATE3 =>
alu_op_o <= ALU_AND;
alu_read_alu_o <= true;
if opc_opcode_q(1 downto 0) = "00" then
bus_write_bus_o <= true;
elsif opc_opcode_q(1) = '0' then
p1_write_p1_o <= true;
else
p2_write_p2_o <= true;
end if;
when others =>
null;
end case;
end if;
-- Mnemonic CALL --------------------------------------------------------
when MN_CALL =>
assert_psen_s <= true;
if not clk_second_cycle_i then
case clk_mstate_i is
-- read Stack Pointer and address Data Memory for low byte
-- also increment Program Counter to point to next instruction
when MSTATE3 =>
psw_read_sp_o <= true;
dm_write_dmem_addr_o <= true;
dm_addr_type_o <= DM_STACK;
-- only increment PC if this is not an injected CALL
-- injected CALLS are not located in Program Memory,
-- the PC points already to the instruction to be executed
-- after the interrupt
if not int_pending_s then
add_inc_pc_s <= true;
end if;
-- store Program Counter low byte on stack
when MSTATE4 =>
pm_read_pcl_o <= true;
dm_write_dmem_s <= true;
-- store Program Counter high byte and PSW on stack
-- increment Stack pointer
when MSTATE5 =>
psw_read_psw_o <= true;
pm_read_pch_o <= true;
dm_write_dmem_addr_o <= true;
dm_addr_type_o <= DM_STACK_HIGH;
dm_write_dmem_s <= true;
psw_inc_stackp_o <= true;
when others =>
null;
end case;
else
case clk_mstate_i is
-- store address in Program Counter low byte
when MSTATE1 =>
pm_write_pcl_o <= true;
branch_taken_s <= true;
if int_pending_s then
-- apply low part of vector address manually
data_s <= (others => '0');
data_s(1 downto 0) <= "11";
if tim_int_s then
data_s(2) <= '1';
end if;
read_dec_s <= true;
end if;
when MSTATE2 =>
pm_write_pch_o <= true;
read_dec_s <= true;
if not int_pending_s then
-- store high part of target address in Program Counter
data_s <= "0000" & mb_v & opc_opcode_q(7 downto 5);
else
-- apply high part of vector address manually
data_s <= (others => '0');
int_executed_s <= true;
end if;
when others =>
null;
end case;
end if;
-- Mnemonic CLR_A -------------------------------------------------------
when MN_CLR_A =>
-- write CLR output of ALU to Accumulator
if clk_mstate_i = MSTATE3 then
alu_op_o <= ALU_CLR;
alu_read_alu_o <= true;
alu_write_accu_o <= true;
end if;
-- Mnemonic CLR_C -------------------------------------------------------
when MN_CLR_C =>
-- store 0 to Carry
if clk_mstate_i = MSTATE3 then
psw_special_data_o <= '0';
psw_write_carry_o <= true;
end if;
-- Mnemonic CLR_F -------------------------------------------------------
when MN_CLR_F =>
-- store 0 to selected flag
if clk_mstate_i = MSTATE3 then
if opc_opcode_q(5) = '0' then
psw_special_data_o <= '0';
psw_write_f0_o <= true;
else
clear_f1_s <= true;
end if;
end if;
-- Mnemonic CPL_A -------------------------------------------------------
when MN_CPL_A =>
-- write CPL output of ALU to Accumulator
if clk_mstate_i = MSTATE3 then
alu_op_o <= ALU_CPL;
alu_read_alu_o <= true;
alu_write_accu_o <= true;
end if;
-- Mnemnonic CPL_C ------------------------------------------------------
when MN_CPL_C =>
-- write inverse of Carry to PSW
if clk_mstate_i = MSTATE3 then
psw_special_data_o <= not psw_carry_i;
psw_write_carry_o <= true;
end if;
-- Mnemonic CPL_F -------------------------------------------------------
when MN_CPL_f =>
-- write inverse of selected flag back to flag
if clk_mstate_i = MSTATE3 then
if opc_opcode_q(5) = '0' then
psw_special_data_o <= not psw_f0_i;
psw_write_f0_o <= true;
else
cpl_f1_s <= true;
end if;
end if;
-- Mnemonic DA ----------------------------------------------------------
when MN_DA =>
alu_op_o <= ALU_ADD;
case clk_mstate_i is
-- Step 1: Preload Temp Reg with 0x06
when MSTATE3 =>
alu_p06_temp_reg_o <= true;
-- Step 2: Check Auxiliary Carry and overflow on low nibble
-- Add 0x06 to shadow Accumulator if one is true
when MSTATE4 =>
if psw_aux_carry_i = '1' or alu_da_overflow_i then
alu_read_alu_o <= true;
alu_write_shadow_o <= true;
end if;
-- preload Temp Reg with 0x60
alu_p60_temp_reg_o <= true;
-- Step 3: Check overflow on high nibble
-- Add 0x60 to shadow Accumulator if true and store result
-- in Accumulator and PSW (only Carry)
when MSTATE5 =>
alu_da_high_o <= true;
if alu_da_overflow_i then
psw_special_data_o <= alu_carry_i;
else
alu_op_o <= ALU_NOP;
psw_special_data_o <= '0';
end if;
alu_read_alu_o <= true;
alu_write_accu_o <= true;
psw_write_carry_o <= true;
when others =>
null;
end case;
-- Mnemonic DEC ---------------------------------------------------------
when MN_DEC =>
case clk_mstate_i is
when MSTATE4 =>
-- DEC Rr: store data from RAM to shadow Accumulator
if opc_opcode_q(6) = '1' then
dm_read_dmem_o <= true;
alu_write_shadow_o <= true;
end if;
when MSTATE5 =>
alu_op_o <= ALU_DEC;
alu_read_alu_o <= true;
if opc_opcode_q(6) = '0' then
-- write DEC of Accumulator to Accumulator
alu_write_accu_o <= true;
else
-- store DEC of shadow Accumulator back to dmem
dm_write_dmem_s <= true;
end if;
when others =>
null;
end case;
-- Mnemonic DIS_EN_I ----------------------------------------------------
when MN_DIS_EN_I =>
if clk_mstate_i = MSTATE3 then
if opc_opcode_q(4) = '1' then
dis_i_s <= true;
else
en_i_s <= true;
end if;
end if;
-- Mnemonic DIS_EN_TCNTI ------------------------------------------------
when MN_DIS_EN_TCNTI =>
if clk_mstate_i = MSTATE3 then
if opc_opcode_q(4) = '1' then
dis_tcnti_s <= true;
else
en_tcnti_s <= true;
end if;
end if;
-- Mnemonic DJNZ --------------------------------------------------------
when MN_DJNZ =>
assert_psen_s <= true;
if not clk_second_cycle_i then
case clk_mstate_i is
-- store data from RAM to shadow Accumulator
when MSTATE4 =>
dm_read_dmem_o <= true;
alu_write_shadow_o <= true;
-- write DEC result of shadow Accumulator back to dmem and
-- conditional branch logic
when MSTATE5 =>
alu_op_o <= ALU_DEC;
alu_read_alu_o <= true;
dm_write_dmem_s <= true;
cnd_compute_take_o <= true;
cnd_branch_cond_o <= COND_Z;
cnd_comp_value_o(0) <= '0';
when others =>
null;
end case;
else
-- store address in Program Counter low byte if branch has to
-- be taken
if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
cond_jump_c2_m1_f;
end if;
end if;
-- Mnemonic ENT0_CLK ----------------------------------------------------
when MN_ENT0_CLK =>
if clk_mstate_i = MSTATE3 then
ent0_clk_s <= true;
end if;
-- Mnemonic IN ----------------------------------------------------------
when MN_IN =>
-- read Port and store in Accumulator
if clk_second_cycle_i and clk_mstate_i = MSTATE2 then
alu_write_accu_o <= true;
if opc_opcode_q(1) = '0' then
p1_read_p1_o <= true;
else
p2_read_p2_o <= true;
end if;
end if;
-- Mnemonic INS ---------------------------------------------------------
when MN_INS =>
clk_assert_rd_o <= true;
-- read BUS and store in Accumulator
if clk_second_cycle_i and clk_mstate_i = MSTATE2 then
alu_write_accu_o <= true;
add_read_bus_s <= true;
end if;
-- Mnemonic INC ---------------------------------------------------------
when MN_INC =>
case clk_mstate_i is
-- read RAM once for indirect address mode
when MSTATE3 =>
if not enable_quartus_bugfix_c or
opc_opcode_q(3) = '0' then
address_indirect_3_f;
end if;
when MSTATE4 =>
-- INC Rr; INC @ Rr: store data from RAM to shadow Accumulator
if opc_opcode_q(3 downto 2) /= "01" then
dm_read_dmem_o <= true;
alu_write_shadow_o <= true;
end if;
when MSTATE5 =>
alu_op_o <= ALU_INC;
alu_read_alu_o <= true;
if opc_opcode_q(3 downto 2) = "01" then
-- write INC output of ALU to Accumulator
alu_write_accu_o <= true;
else
-- store INC of shadow Accumulator back to dmem
dm_write_dmem_s <= true;
end if;
when others =>
null;
end case;
-- Mnemonic JBB ---------------------------------------------------------
when MN_JBB =>
assert_psen_s <= true;
cnd_branch_cond_o <= COND_ON_BIT;
if not clk_second_cycle_i then
-- read Accumulator and start branch calculation
if clk_mstate_i = MSTATE3 then
alu_read_alu_o <= true;
cnd_compute_take_o <= true;
-- cnd_comp_value_o is ok by default assignment
end if;
else
-- store address in Program Counter low byte if branch has to
-- be taken
if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
cond_jump_c2_m1_f;
end if;
end if;
-- Mnemonic JC ----------------------------------------------------------
when MN_JC =>
assert_psen_s <= true;
cnd_branch_cond_o <= COND_C;
if not clk_second_cycle_i then
-- start branch calculation
if clk_mstate_i = MSTATE3 then
cnd_compute_take_o <= true;
cnd_comp_value_o(0) <= opc_opcode_q(4);
end if;
else
-- store address in Program Counter low byte if branch has to
-- be taken
if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
cond_jump_c2_m1_f;
end if;
end if;
-- Mnemonic JF ----------------------------------------------------------
when MN_JF =>
assert_psen_s <= true;
if not clk_second_cycle_i then
-- start branch calculation
if clk_mstate_i = MSTATE3 then
cnd_compute_take_o <= true;
if opc_opcode_q(7) = '1' then
-- JF0
cnd_branch_cond_o <= COND_F0;
else
-- JF1
cnd_branch_cond_o <= COND_F1;
end if;
end if;
else
-- store address in Program Counter low byte if branch has to
-- be taken
if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
cond_jump_c2_m1_f;
end if;
end if;
-- Mnemonic JMP ---------------------------------------------------------
when MN_JMP =>
assert_psen_s <= true;
if clk_second_cycle_i then
case clk_mstate_i is
-- store address in Program Counter low byte
when MSTATE1 =>
pm_write_pcl_o <= true;
branch_taken_s <= true;
-- store high part of target address in Program Counter
when MSTATE2 =>
data_s <= "0000" & mb_v & opc_opcode_q(7 downto 5);
read_dec_s <= true;
pm_write_pch_o <= true;
when others =>
null;
end case;
end if;
-- Mnemonic JMPP --------------------------------------------------------
when MN_JMPP =>
assert_psen_s <= true;
if not clk_second_cycle_i then
-- write Accumulator to Program Memory address
-- (skip page offset update from Program Counter)
if clk_mstate_i = MSTATE3 then
alu_read_alu_o <= true;
pm_addr_type_o <= PM_PAGE;
end if;
else
if clk_mstate_i = MSTATE1 then
-- store address in Program Counter low byte
pm_write_pcl_o <= true;
branch_taken_s <= true;
end if;
end if;
-- Mnemonic JNI ---------------------------------------------------------
when MN_JNI =>
assert_psen_s <= true;
cnd_branch_cond_o <= COND_INT;
if not clk_second_cycle_i then
-- start branch calculation
if clk_mstate_i = MSTATE3 then
cnd_compute_take_o <= true;
end if;
else
-- store address in Program Counter low byte if branch has to
-- be taken
if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
cond_jump_c2_m1_f;
end if;
end if;
-- Mnemonic JT ----------------------------------------------------------
when MN_JT =>
assert_psen_s <= true;
if opc_opcode_q(6) = '0' then
cnd_branch_cond_o <= COND_T0;
else
cnd_branch_cond_o <= COND_T1;
end if;
if not clk_second_cycle_i then
-- start branch calculation
if clk_mstate_i = MSTATE3 then
cnd_compute_take_o <= true;
cnd_comp_value_o(0) <= opc_opcode_q(4);
end if;
else
-- store address in Program Counter low byte if branch has to
-- be taken
if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
cond_jump_c2_m1_f;
end if;
end if;
-- Mnemonic JTF ---------------------------------------------------------
when MN_JTF =>
assert_psen_s <= true;
cnd_branch_cond_o <= COND_TF;
if not clk_second_cycle_i then
-- start branch calculation
if clk_mstate_i = MSTATE3 then
cnd_compute_take_o <= true;
jtf_executed_s <= true;
end if;
else
-- store address in Program Counter low byte if branch has to
-- be taken
if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
cond_jump_c2_m1_f;
end if;
end if;
-- Mnemonic JZ ----------------------------------------------------------
when MN_JZ =>
assert_psen_s <= true;
cnd_branch_cond_o <= COND_Z;
if not clk_second_cycle_i then
-- read Accumulator and start branch calculation
if clk_mstate_i = MSTATE3 then
alu_read_alu_o <= true;
cnd_compute_take_o <= true;
cnd_comp_value_o(0) <= opc_opcode_q(6);
end if;
else
-- store address in Program Counter low byte if branch has to
-- be taken
if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
cond_jump_c2_m1_f;
end if;
end if;
-- Mnemonic MOV_A_DATA --------------------------------------------------
when MN_MOV_A_DATA =>
assert_psen_s <= true;
-- Write Accumulator when contents of Program Memory is on bus
-- during machine state 1 of second cycle.
if clk_second_cycle_i and clk_mstate_i = MSTATE1 then
alu_write_accu_o <= true;
end if;
-- Mnemonic MOV_A_RR ----------------------------------------------------
when MN_MOV_A_RR =>
case clk_mstate_i is
-- read RAM once for indirect address mode
when MSTATE3 =>
if not enable_quartus_bugfix_c or
opc_opcode_q(3) = '0' then
address_indirect_3_f;
end if;
-- read data from RAM and store in Accumulator
when MSTATE4 =>
and_or_xor_add_4_f;
alu_write_accu_o <= true;
when others =>
null;
end case;
-- Mnemonic MOV_A_PSW ---------------------------------------------------
when MN_MOV_A_PSW =>
if clk_mstate_i = MSTATE3 then
psw_read_psw_o <= true;
psw_read_sp_o <= true;
alu_write_accu_o <= true;
end if;
-- Mnemoniv MOV_PSW_A ---------------------------------------------------
when MN_MOV_PSW_A =>
if clk_mstate_i = MSTATE3 then
alu_read_alu_o <= true;
psw_write_psw_o <= true;
psw_write_sp_o <= true;
end if;
-- Mnemonic MOV_RR ------------------------------------------------------
when MN_MOV_RR =>
case clk_mstate_i is
-- read RAM once for indirect address mode
when MSTATE3 =>
if not enable_quartus_bugfix_c or
opc_opcode_q(3) = '0' then
address_indirect_3_f;
end if;
-- write Accumulator to dmem
when MSTATE5 =>
alu_read_alu_o <= true;
dm_write_dmem_s <= true;
when others =>
null;
end case;
-- Mnemonic MOV_RR_DATA -------------------------------------------------
when MN_MOV_RR_DATA =>
assert_psen_s <= true;
-- read RAM once for indirect address mode
if not clk_second_cycle_i and clk_mstate_i = MSTATE3 then
if not enable_quartus_bugfix_c or
opc_opcode_q(3) = '0' then
address_indirect_3_f;
end if;
end if;
-- Write Data Memory when contents of Program Memory is on bus
-- during machine state 1 of second cycle.
if clk_second_cycle_i and clk_mstate_i = MSTATE1 then
dm_write_dmem_s <= true;
end if;
-- Mnemonic MOV_T -------------------------------------------------------
when MN_MOV_T =>
if clk_mstate_i = MSTATE3 then
if opc_opcode_q(5) = '1' then
alu_read_alu_o <= true; -- MOV T, A
tim_write_timer_o <= true;
else
tim_read_timer_o <= true; -- MOV A, T
alu_write_accu_o <= true;
end if;
end if;
-- Mnemonic OUTD_PP_A ---------------------------------------------------
when MN_OUTD_PP_A =>
clk_assert_prog_o <= true;
if not clk_second_cycle_i then
case clk_mstate_i is
-- propagate expander port number to Port 2
when MSTATE3 =>
data_s(7 downto 4) <= (others => '0');
data_s(1 downto 0) <= opc_opcode_q(1 downto 0);
-- decide which 8243 command to use
case opc_opcode_q(7 downto 4) is
when "1001" =>
data_s(3 downto 2) <= "11"; -- ANLD command
when "1000" =>
data_s(3 downto 2) <= "10"; -- ORLD command
when "0011" =>
data_s(3 downto 2) <= "01"; -- MOVD command
when others =>
null;
end case;
read_dec_s <= true;
p2_write_exp_o <= true;
-- output expander port number on Port 2 while active edge of PROG
-- write Accumulator to expander port
when MSTATE4 =>
p2_output_exp_s <= true;
alu_read_alu_o <= true;
p2_write_exp_o <= true;
when MSTATE5 =>
p2_output_exp_s <= true;
when others =>
null;
end case;
else
-- hold expander port until inactive edge of PROG
if clk_mstate_i = MSTATE1 or clk_mstate_i = MSTATE2 then
p2_output_exp_s <= true;
end if;
end if;
-- Mnemonic MOVD_A_PP ---------------------------------------------------
when MN_MOVD_A_PP =>
clk_assert_prog_o <= true;
if not clk_second_cycle_i then
case clk_mstate_i is
-- propagate expander port number to Port 2
when MSTATE3 =>
data_s <= "0000" &
"00" & -- 8243 command: read
opc_opcode_q(1 downto 0);
read_dec_s <= true;
p2_write_exp_o <= true;
-- output expander port number on Port 2 while active edge of PROG
-- write 1's to expander port to set lower nibble of Port 2 to input
when MSTATE4 =>
p2_output_exp_s <= true;
data_s(nibble_t'range) <= (others => '1');
read_dec_s <= true;
p2_write_exp_o <= true;
when MSTATE5 =>
p2_output_exp_s <= true;
when others =>
null;
end case;
else
case clk_mstate_i is
-- hold expander port until inactive edge of PROG
when MSTATE1 =>
p2_output_exp_s <= true;
-- hold expander port until inactive edge of PROG
-- write Accumulator with nibble of expander port
when MSTATE2 =>
p2_read_p2_o <= true;
p2_output_exp_s <= true;
p2_read_exp_o <= true;
alu_write_accu_o <= true;
when others =>
null;
end case;
end if;
-- Mnemonic MOVP --------------------------------------------------------
when MN_MOVP =>
assert_psen_s <= true;
if not clk_second_cycle_i then
-- write Accumulator to Program Memory address
-- (skip page offset update from Program Counter)
if clk_mstate_i = MSTATE3 then
alu_read_alu_o <= true;
if opc_opcode_q(6) = '0' then
pm_addr_type_o <= PM_PAGE;
else
pm_addr_type_o <= PM_PAGE3;
end if;
end if;
else
if clk_mstate_i = MSTATE1 then
-- store data from Program Memory in Accumulator
alu_write_accu_o <= true;
-- trick & treat to prevent additional PC increment
-- our branch target is the previously incremented PC!
branch_taken_s <= true;
end if;
end if;
-- Mnemonic MOVX --------------------------------------------------------
when MN_MOVX =>
bus_bidir_bus_o <= true;
if opc_opcode_q(4) = '0' then
clk_assert_rd_o <= true;
else
clk_assert_wr_o <= true;
end if;
if not clk_second_cycle_i then
movx_first_cycle_s <= true;
case clk_mstate_i is
-- read dmem and put contents on BUS as external address
when MSTATE3 =>
dm_read_dmem_o <= true;
bus_write_bus_o <= true;
-- store contents of Accumulator to BUS
when MSTATE5 =>
if opc_opcode_q(4) = '1' then
alu_read_alu_o <= true;
bus_write_bus_o <= true;
end if;
when others =>
null;
end case;
else
if clk_mstate_i = MSTATE2 then
if opc_opcode_q(4) = '0' then
-- store contents of BUS in Accumulator
add_read_bus_s <= true;
alu_write_accu_o <= true;
else
-- store contents of Accumulator to BUS
-- to this to keep bus in output direction
alu_read_alu_o <= true;
bus_write_bus_o <= true;
end if;
end if;
end if;
-- Mnemonic NOP ---------------------------------------------------------
when MN_NOP =>
-- nothing to do
-- Mnemonic ORL ---------------------------------------------------------
when MN_ORL =>
case clk_mstate_i is
-- read RAM once for indirect address mode
when MSTATE3 =>
if not enable_quartus_bugfix_c or
opc_opcode_q(3) = '0' then
address_indirect_3_f;
end if;
-- store data from RAM to Temp Reg
when MSTATE4 =>
and_or_xor_add_4_f;
-- perform OR and store in Accumulator
when MSTATE5 =>
and_or_xor_add_5_f(alu_op => ALU_OR);
when others =>
null;
end case;
-- Mnemonic ORL_A_DATA --------------------------------------------------
when MN_ORL_A_DATA =>
assert_psen_s <= true;
if clk_second_cycle_i then
case clk_mstate_i is
-- write Temp Reg when contents of Program Memory is on bus
when MSTATE1 =>
alu_write_temp_reg_o <= true;
-- perform OR and store in Accumulator
when MSTATE3 =>
and_or_xor_add_5_f(alu_op => ALU_OR);
when others =>
null;
end case;
end if;
-- Mnemonic ORL_EXT -----------------------------------------------------
when MN_ORL_EXT =>
assert_psen_s <= true;
if not clk_second_cycle_i then
-- read port to Temp Reg
if clk_mstate_i = MSTATE5 then
if opc_opcode_q(1 downto 0) = "00" then
add_read_bus_s <= true;
elsif opc_opcode_q(1) = '0' then
p1_read_p1_o <= true;
p1_read_reg_o <= true;
else
p2_read_p2_o <= true;
p2_read_reg_o <= true;
end if;
alu_write_temp_reg_o <= true;
end if;
else
case clk_mstate_i is
-- write shadow Accumulator when contents of Program Memory is
-- on bus
when MSTATE1 =>
alu_write_shadow_o <= true;
-- loop shadow Accumulator through ALU to prevent update from
-- real Accumulator
when MSTATE2 =>
alu_read_alu_o <= true;
alu_write_shadow_o <= true;
-- write result of OR operation back to port
when MSTATE3 =>
alu_op_o <= ALU_OR;
alu_read_alu_o <= true;
if opc_opcode_q(1 downto 0) = "00" then
bus_write_bus_o <= true;
elsif opc_opcode_q(1) = '0' then
p1_write_p1_o <= true;
else
p2_write_p2_o <= true;
end if;
when others =>
null;
end case;
end if;
-- Mnemonic OUTL_EXT ----------------------------------------------------
when MN_OUTL_EXT =>
if opc_opcode_q(4) = '0' then
clk_assert_wr_o <= true;
end if;
-- read Accumulator and store in Port/BUS output register
if not clk_second_cycle_i and clk_mstate_i = MSTATE4 then
alu_read_alu_o <= true;
if opc_opcode_q(4) = '1' then
if opc_opcode_q(1) = '0' then
p1_write_p1_o <= true;
else
p2_write_p2_o <= true;
end if;
else
bus_write_bus_o <= true;
end if;
end if;
-- Mnemonic RET ---------------------------------------------------------
when MN_RET =>
if not clk_second_cycle_i then
case clk_mstate_i is
-- decrement Stack Pointer
when MSTATE3 =>
psw_dec_stackp_o <= true;
-- read Stack Pointer and address Data Memory for low byte
when MSTATE4 =>
psw_read_sp_o <= true;
dm_write_dmem_addr_o <= true;
dm_addr_type_o <= DM_STACK;
-- read Data Memory and store to Program Counter low
-- prepare address to Data memory for high byte
when MSTATE5 =>
dm_read_dmem_o <= true;
pm_write_pcl_o <= true;
dm_write_dmem_addr_o <= true;
dm_addr_type_o <= DM_STACK_HIGH;
when others =>
null;
end case;
else
case clk_mstate_i is
-- read Data Memory and store to Program Counter high and PSW
when MSTATE1 =>
dm_read_dmem_o <= true;
pm_write_pch_o <= true;
if opc_opcode_q(4) = '1' then
psw_write_psw_o <= true;
retr_executed_s <= true;
end if;
when MSTATE2 =>
add_write_pmem_addr_s <= true;
when others =>
null;
end case;
end if;
-- Mnemonic RL ----------------------------------------------------------
when MN_RL =>
if clk_mstate_i = MSTATE3 then
alu_op_o <= ALU_RL;
alu_read_alu_o <= true;
alu_write_accu_o <= true;
if opc_opcode_q(4) = '1' then
psw_special_data_o <= alu_carry_i;
psw_write_carry_o <= true;
alu_use_carry_o <= true;
end if;
end if;
-- Mnemonic RR ----------------------------------------------------------
when MN_RR =>
if clk_mstate_i = MSTATE3 then
alu_op_o <= ALU_RR;
alu_read_alu_o <= true;
alu_write_accu_o <= true;
if opc_opcode_q(4) = '0' then
psw_special_data_o <= alu_carry_i;
psw_write_carry_o <= true;
alu_use_carry_o <= true;
end if;
end if;
-- Mnemonic SEL_MB ------------------------------------------------------
when MN_SEL_MB =>
if clk_mstate_i = MSTATE3 then
if opc_opcode_q(4) = '1' then
set_mb_s <= true;
else
clear_mb_s <= true;
end if;
end if;
-- Mnemonic SEL_RB ------------------------------------------------------
when MN_SEL_RB =>
if clk_mstate_i = MSTATE3 then
psw_special_data_o <= opc_opcode_q(4);
psw_write_bs_o <= true;
end if;
-- Mnemonic STOP_TCNT ---------------------------------------------------
when MN_STOP_TCNT =>
if clk_mstate_i = MSTATE3 then
tim_stop_tcnt_o <= true;
end if;
-- Mnemonic STRT --------------------------------------------------------
when MN_STRT =>
if clk_mstate_i = MSTATE3 then
if opc_opcode_q(4) = '1' then
tim_start_t_o <= true;
else
tim_start_cnt_o <= true;
end if;
end if;
-- Mnemonic SWAP --------------------------------------------------------
when MN_SWAP =>
alu_op_o <= ALU_SWAP;
if clk_mstate_i = MSTATE3 then
alu_read_alu_o <= true;
alu_write_accu_o <= true;
end if;
-- Mnemonic XCH ---------------------------------------------------------
when MN_XCH =>
case clk_mstate_i is
-- read RAM once for indirect address mode
when MSTATE3 =>
if not enable_quartus_bugfix_c or
opc_opcode_q(3) = '0' then
address_indirect_3_f;
end if;
-- store data from RAM in Accumulator and Temp Reg
-- Accumulator is already shadowed!
when MSTATE4 =>
dm_read_dmem_o <= true;
alu_write_accu_o <= true;
alu_write_temp_reg_o <= true;
if opc_opcode_q(4) = '1' then
-- XCHD
-- only write lower nibble of Accumulator
alu_accu_low_o <= true;
end if;
-- store data from shadow (previous) Accumulator to dmem
when MSTATE5 =>
dm_write_dmem_s <= true;
alu_read_alu_o <= true;
if opc_opcode_q(4) = '1' then
-- XCHD
-- concatenate shadow Accumulator and Temp Reg
alu_op_o <= ALU_CONCAT;
end if;
when others =>
null;
end case;
-- Mnemonic XRL ---------------------------------------------------------
when MN_XRL =>
case clk_mstate_i is
-- read RAM once for indirect address mode
when MSTATE3 =>
if not enable_quartus_bugfix_c or
opc_opcode_q(3) = '0' then
address_indirect_3_f;
end if;
-- store data from RAM to Temp Reg
when MSTATE4 =>
and_or_xor_add_4_f;
-- perform XOR and store in Accumulator
when MSTATE5 =>
and_or_xor_add_5_f(alu_op => ALU_XOR);
when others =>
null;
end case;
-- Mnemonic XRL_A_DATA --------------------------------------------------
when MN_XRL_A_DATA =>
assert_psen_s <= true;
if clk_second_cycle_i then
case clk_mstate_i is
-- write Temp Reg when contents of Program Memory is on bus
when MSTATE1 =>
alu_write_temp_reg_o <= true;
-- perform XOR and store in Accumulator
when MSTATE3 =>
and_or_xor_add_5_f(alu_op => ALU_XOR);
when others =>
null;
end case;
end if;
-- Unimplemented mnemonic -----------------------------------------------
when others =>
-- this will behave like a NOP
-- pragma translate_off
assert false
report "Mnemonic not yet implemented."
severity warning;
-- pragma translate_on
end case;
end process decode;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process regs
--
-- Purpose:
-- Implements the various registes.
--
regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
branch_taken_q <= false;
f1_q <= '0';
mb_q <= '0';
t0_dir_q <= '0';
-- pragma translate_off
istrobe_res_q <= '1';
istrobe_q <= '0';
injected_int_q <= '0';
-- pragma translate_on
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
-- branch taken flag
if branch_taken_s then
branch_taken_q <= true;
elsif clk_mstate_i = MSTATE5 then
-- release flag when new instruction starts
branch_taken_q <= false;
end if;
-- Flag 1
if clear_f1_s then
f1_q <= '0';
elsif cpl_f1_s then
f1_q <= not f1_q;
end if;
-- Memory Bank select
if clear_mb_s then
mb_q <= '0';
elsif set_mb_s then
mb_q <= '1';
end if;
-- T0 direction selection
if ent0_clk_s then
t0_dir_q <= '1';
end if;
-- pragma translate_off
-- Marker for injected instruction ------------------------------------
if opc_inj_int_s then
injected_int_q <= '1';
elsif clk_mstate_i = MSTATE5 and last_cycle_s then
injected_int_q <= '0';
end if;
-- Remove istrobe after reset suppression -----------------------------
if clk_mstate_i = MSTATE5 and last_cycle_s then
istrobe_res_q <= '0';
end if;
-- pragma translate_on
end if;
-- pragma translate_off
-- Instruction Strobe ---------------------------------------------------
if clk_mstate_i = MSTATE5 and last_cycle_s and
injected_int_q = '0' then
if istrobe_res_q = '0' then
istrobe_q <= '1';
end if;
else
istrobe_q <= '0';
end if;
-- pragma translate_on
end if;
end process regs;
--
-----------------------------------------------------------------------------
-- pragma translate_off
-- assign to global signal for testbench
tb_istrobe_s <= istrobe_q;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
clk_multi_cycle_o <= opc_multi_cycle_s;
cnd_f1_o <= f1_q;
cnd_tf_o <= tf_s;
data_o <= data_s
when read_dec_s else
(others => bus_idle_level_c);
dm_write_dmem_o <= dm_write_dmem_s and en_clk_i;
pm_inc_pc_o <= pm_inc_pc_s or add_inc_pc_s;
pm_write_pmem_addr_o <= pm_write_pmem_addr_s or add_write_pmem_addr_s;
t0_dir_o <= t0_dir_q;
bus_read_bus_o <= bus_read_bus_s or add_read_bus_s;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.26 2008/04/29 21:19:21 arniml
-- better support for ISE/XST:
-- opc_table and opc_decoder merged into decoder_pack and decoder
--
-- Revision 1.25 2006/06/20 00:46:03 arniml
-- new input xtal_en_i
--
-- Revision 1.24 2005/11/14 21:12:29 arniml
-- suppress p2_output_pch_o when MOVX operation is accessing the
-- external memory
--
-- Revision 1.23 2005/11/07 19:25:01 arniml
-- fix sensitivity list
--
-- Revision 1.22 2005/11/01 21:25:37 arniml
-- * suppress p2_output_pch_o when p2_output_exp is active
-- * wire xtal_i to interrupt module
--
-- Revision 1.21 2005/10/31 10:08:33 arniml
-- Suppress assertion of bus_read_bus_s when interrupt is pending.
-- This should fix bug report
-- "PROBLEM WHEN INT AND JMP"
--
-- Revision 1.20 2005/09/13 21:08:34 arniml
-- move check for int_pending_s into ea_i_='0' branch
-- this fixes a glitch on PCH when an interrutp occurs
-- during external program memory fetch
--
-- Revision 1.19 2005/06/11 10:08:43 arniml
-- introduce prefix 't48_' for all packages, entities and configurations
--
-- Revision 1.18 2005/06/09 22:18:28 arniml
-- Move latching of BUS to MSTATE2
-- -> sample BUS at the end of RD'
--
-- Revision 1.17 2005/05/09 22:26:08 arniml
-- remove obsolete output stack_high_o
--
-- Revision 1.16 2004/10/25 19:39:24 arniml
-- Fix bug report:
-- "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
-- rd is asserted for INS A, BUS
-- wr is asserted for OUTL BUS, A
-- P1, P2 and BUS are written in first instruction cycle
--
-- Revision 1.15 2004/09/12 00:35:44 arniml
-- Fix bug report:
-- "PSENn Timing"
-- PSEN is now only asserted for the second cycle if explicitely
-- requested by assert_psen_s.
-- The previous implementation asserted PSEN together with RD or WR.
--
-- Revision 1.14 2004/06/30 21:18:28 arniml
-- Fix bug report:
-- "Program Memory bank can be switched during interrupt"
-- int module emits int_in_progress signal that is used inside the decoder
-- to hold mb low for JMP and CALL during interrupts
--
-- Revision 1.13 2004/05/20 21:51:40 arniml
-- clean-up use of ea_i
--
-- Revision 1.12 2004/05/17 14:40:09 arniml
-- assert p2_read_p2_o when expander port is read
--
-- Revision 1.11 2004/05/16 15:33:39 arniml
-- work around bug in Quartus II 4.0
--
-- Revision 1.10 2004/04/25 16:22:03 arniml
-- adjust external timing of BUS
--
-- Revision 1.9 2004/04/24 11:22:55 arniml
-- removed superfluous signal from sensitivity list
--
-- Revision 1.8 2004/04/18 18:57:43 arniml
-- + enhance instruction strobe generation
-- + rework address output under EA=1 conditions
--
-- Revision 1.7 2004/04/15 22:06:05 arniml
-- + add marker for injected calls
-- + suppress intstruction strobes for injected calls
--
-- Revision 1.6 2004/04/14 20:53:33 arniml
-- make istrobe visible through testbench package
--
-- Revision 1.5 2004/04/07 22:09:03 arniml
-- remove unused signals
--
-- Revision 1.4 2004/04/04 14:18:53 arniml
-- add measures to implement XCHD
--
-- Revision 1.3 2004/03/28 21:15:48 arniml
-- implemented mnemonic DA
--
-- Revision 1.2 2004/03/28 13:06:32 arniml
-- implement mnemonics:
-- + MOVD_A_PP
-- + OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
gpl-2.0
|
84cec76a6d42db94fdd901ea61613a90
| 0.455819 | 4.053629 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_ftch_q_mngr.vhd
| 1 | 37,589 |
-------------------------------------------------------------------------------
-- axi_sg_ftch_queue
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/27/10 v1_00_a
-- ^^^^^^
-- CR569609
-- Remove double driven signal for exclude update engine mode
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
library lib_pkg_v1_0;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_q_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data width
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_FAMILY : string := "virtex6"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
ch1_desc_flush : in std_logic ; --
ch1_ftch_active : in std_logic ; --
ch1_nxtdesc_wren : out std_logic ; --
ch1_ftch_queue_empty : out std_logic ; --
ch1_ftch_queue_full : out std_logic ; --
ch1_ftch_pause : out std_logic ; --
--
-- Channel 2 Control --
ch2_desc_flush : in std_logic ; --
ch2_ftch_active : in std_logic ; --
ch2_nxtdesc_wren : out std_logic ; --
ch2_ftch_queue_empty : out std_logic ; --
ch2_ftch_queue_full : out std_logic ; --
ch2_ftch_pause : out std_logic ; --
nxtdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : out std_logic ; --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tkeep : in std_logic_vector --
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
--
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ;
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
--
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic --
);
end axi_sg_ftch_q_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_q_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Determine the maximum word count for use in setting the word counter width
-- Set bit width on max num words to fetch
constant FETCH_COUNT : integer := max2(C_SG_CH1_WORDS_TO_FETCH
,C_SG_CH2_WORDS_TO_FETCH);
-- LOG2 to get width of counter
constant WORDS2FETCH_BITWIDTH : integer := clog2(FETCH_COUNT);
-- Zero value for counter
constant WORD_ZERO : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= (others => '0');
-- One value for counter
constant WORD_ONE : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,WORDS2FETCH_BITWIDTH));
-- Seven value for counter
constant WORD_SEVEN : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(7,WORDS2FETCH_BITWIDTH));
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal m_axis_mm2s_tready_i : std_logic := '0';
signal ch1_ftch_tready : std_logic := '0';
signal ch2_ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal fetch_word_count : std_logic_vector
(WORDS2FETCH_BITWIDTH-1 downto 0) := (others => '0');
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal lsbnxtdesc_tready : std_logic := '0';
signal msbnxtdesc_tready : std_logic := '0';
signal nxtdesc_tready : std_logic := '0';
signal ch1_writing_curdesc : std_logic := '0';
signal ch2_writing_curdesc : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- For 32-bit SG addresses then drive zero on msb
---------------------------------------------------------------------------
GEN_CURDESC_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
msb_curdesc <= (others => '0');
end generate GEN_CURDESC_32;
---------------------------------------------------------------------------
-- For 64-bit SG addresses then capture upper order adder to msb
---------------------------------------------------------------------------
GEN_CURDESC_64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CAPTURE_CURADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
msb_curdesc <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
msb_curdesc <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ C_M_AXI_SG_ADDR_WIDTH
downto DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT + 1);
end if;
end if;
end process CAPTURE_CURADDR;
end generate GEN_CURDESC_64;
-------------------------------------------------------------------------------
-- Fetch Stream Word Counter
-- The process is used to determine when to strip off NextDesc pointer from
-- stream and when to look at control word for complete bit set.
-------------------------------------------------------------------------------
REG_WORD_COUNTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- Clear on reset and on datamover command write
if(m_axi_sg_aresetn = '0' or ftch_cmnd_wr = '1'
or (m_axis_mm2s_tlast = '1' and m_axis_mm2s_tvalid = '1' and m_axis_mm2s_tready_i = '1'))then
fetch_word_count <= (others => '0');
-- If both tvalid=1 and tready = 1 then count
elsif(m_axis_mm2s_tvalid = '1' and m_axis_mm2s_tready_i = '1')then
fetch_word_count <= std_logic_vector(unsigned(fetch_word_count
(WORDS2FETCH_BITWIDTH-1 downto 0)) + 1);
end if;
end if;
end process REG_WORD_COUNTER;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc(31 downto 0) <= (others => '0');
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and fetch_word_count = WORD_ZERO)then
nxtdesc(31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process REG_LSB_NXTPNTR;
lsbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and fetch_word_count = WORD_ZERO
else '0';
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_NXTDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc(63 downto 32) <= (others => '0');
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Capture upper pointer, drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and fetch_word_count = WORD_ONE)then
nxtdesc(63 downto 32) <= m_axis_mm2s_tdata;
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert tready/wren for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and fetch_word_count = WORD_ONE
else '0';
end generate GEN_UPPER_MSB_NXTDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_NXTDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Throw away second word but drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and fetch_word_count = WORD_ONE)then
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and fetch_word_count = WORD_ONE
else '0';
end generate GEN_NO_UPR_MSB_NXTDESC;
-- Drive ready to DataMover for ether lsb or msb capture
nxtdesc_tready <= msbnxtdesc_tready or lsbnxtdesc_tready;
-- Generate logic for checking stale descriptor
GEN_STALE_DESC_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 or C_SG_CH2_ENBL_STALE_ERROR = 1 generate
begin
---------------------------------------------------------------------------
-- Examine Completed BIT to determine if stale descriptor fetched
---------------------------------------------------------------------------
CMPLTD_CHECK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ftch_stale_desc <= '0';
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and fetch_word_count = WORD_SEVEN
and m_axis_mm2s_tready_i = '1'
and m_axis_mm2s_tdata(DESC_STS_CMPLTD_BIT) = '1' )then
ftch_stale_desc <= '1';
else
ftch_stale_desc <= '0';
end if;
end if;
end process CMPLTD_CHECK;
end generate GEN_STALE_DESC_CHECK;
-- No needed logic for checking stale descriptor
GEN_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 and C_SG_CH2_ENBL_STALE_ERROR = 0 generate
begin
ftch_stale_desc <= '0';
end generate GEN_NO_STALE_CHECK;
-------------------------------------------------------------------------------
-- If channel 1 is included then generate ch1 logic
-------------------------------------------------------------------------------
GEN_CH1_FTCH_Q_IF : if C_INCLUDE_CH1 = 1 generate
begin
---------------------------------------------------------------------------
-- SG Queueing therefore pass stream signals to
-- FIFO
---------------------------------------------------------------------------
GEN_CH1_QUEUE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
begin
-- Instantiate the queue version
FTCH_QUEUE_I : entity axi_vdma_v6_2.axi_sg_ftch_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel Control
desc_flush => ch1_desc_flush ,
ftch_active => ch1_ftch_active ,
ftch_queue_empty => ch1_ftch_queue_empty ,
ftch_queue_full => ch1_ftch_queue_full ,
ftch_pause => ch1_ftch_pause ,
writing_nxtdesc_in => nxtdesc_tready ,
writing_curdesc_out => ch1_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => ch1_ftch_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_aclk => m_axis_ch1_ftch_aclk ,
m_axis_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch_tlast => m_axis_ch1_ftch_tlast
);
end generate GEN_CH1_QUEUE;
-- No SG Queueing therefore pass stream signals straight
-- out channel port
GEN_NO_CH1_QUEUE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
-- Instantiate the No queue version
NO_FTCH_QUEUE_I : entity axi_vdma_v6_2.axi_sg_ftch_noqueue
generic map (
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel Control
desc_flush => ch1_desc_flush ,
ftch_active => ch1_ftch_active ,
ftch_queue_empty => ch1_ftch_queue_empty ,
ftch_queue_full => ch1_ftch_queue_full ,
writing_nxtdesc_in => nxtdesc_tready ,
writing_curdesc_out => ch1_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => ch1_ftch_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch_tlast => m_axis_ch1_ftch_tlast
);
ch1_ftch_pause <= '0';
end generate GEN_NO_CH1_QUEUE;
end generate GEN_CH1_FTCH_Q_IF;
-------------------------------------------------------------------------------
-- Channel 1 excluded so tie outputs low
-------------------------------------------------------------------------------
GEN_NO_CH1_FTCH_Q_IF : if C_INCLUDE_CH1 = 0 generate
begin
ch1_ftch_queue_empty <= '0';
ch1_ftch_queue_full <= '0';
ch1_ftch_pause <= '0';
ch1_writing_curdesc <= '0';
ch1_ftch_tready <= '0';
m_axis_ch1_ftch_tdata <= (others => '0');
m_axis_ch1_ftch_tlast <= '0';
m_axis_ch1_ftch_tvalid <= '0';
end generate GEN_NO_CH1_FTCH_Q_IF;
-------------------------------------------------------------------------------
-- If channel 2 is included then generate ch1 logic
-------------------------------------------------------------------------------
GEN_CH2_FTCH_Q_IF : if C_INCLUDE_CH2 = 1 generate
begin
---------------------------------------------------------------------------
-- SG Queueing therefore pass stream signals to
-- FIFO
---------------------------------------------------------------------------
GEN_CH2_QUEUE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
begin
-- Instantiate the queue version
FTCH_QUEUE_I : entity axi_vdma_v6_2.axi_sg_ftch_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel Control
desc_flush => ch2_desc_flush ,
ftch_active => ch2_ftch_active ,
ftch_queue_empty => ch2_ftch_queue_empty ,
ftch_queue_full => ch2_ftch_queue_full ,
ftch_pause => ch2_ftch_pause ,
writing_nxtdesc_in => nxtdesc_tready ,
writing_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => ch2_ftch_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_aclk => m_axis_ch2_ftch_aclk ,
m_axis_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis_ftch_tlast => m_axis_ch2_ftch_tlast
);
end generate GEN_CH2_QUEUE;
-- No SG Queueing therefore pass stream signals straight
-- out channel port
GEN_NO_CH2_QUEUE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
-- Instantiate the No queue version
NO_FTCH_QUEUE_I : entity axi_vdma_v6_2.axi_sg_ftch_noqueue
generic map (
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel Control
desc_flush => ch2_desc_flush ,
ftch_active => ch2_ftch_active ,
ftch_queue_empty => ch2_ftch_queue_empty ,
ftch_queue_full => ch2_ftch_queue_full ,
writing_nxtdesc_in => nxtdesc_tready ,
writing_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => ch2_ftch_tready ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis_ftch_tlast => m_axis_ch2_ftch_tlast
);
ch2_ftch_pause <= '0';
end generate GEN_NO_CH2_QUEUE;
end generate GEN_CH2_FTCH_Q_IF;
-------------------------------------------------------------------------------
-- Channel 2 excluded so tie outputs low
-------------------------------------------------------------------------------
GEN_NO_CH2_FTCH_Q_IF : if C_INCLUDE_CH2 = 0 generate
begin
ch2_ftch_queue_empty <= '0';
ch2_ftch_queue_full <= '0';
ch2_ftch_pause <= '0';
ch2_writing_curdesc <= '0';
ch2_ftch_tready <= '0';
m_axis_ch2_ftch_tdata <= (others => '0');
m_axis_ch2_ftch_tlast <= '0';
m_axis_ch2_ftch_tvalid <= '0';
end generate GEN_NO_CH2_FTCH_Q_IF;
-------------------------------------------------------------------------------
-- DataMover TREADY MUX
-------------------------------------------------------------------------------
writing_curdesc <= ch1_writing_curdesc or ch2_writing_curdesc or ftch_cmnd_wr;
TREADY_MUX : process(writing_curdesc,
fetch_word_count,
nxtdesc_tready,
-- channel 1 signals
ch1_ftch_active,
ch1_desc_flush,
ch1_ftch_tready,
-- channel 2 signals
ch2_ftch_active,
ch2_desc_flush,
ch2_ftch_tready)
begin
-- If commmanded to flush descriptor then assert ready
-- to datamover until active de-asserts. this allows
-- any commanded fetches to complete.
if( (ch1_desc_flush = '1' and ch1_ftch_active = '1')
or(ch2_desc_flush = '1' and ch2_ftch_active = '1'))then
m_axis_mm2s_tready_i <= '1';
-- NOT ready if cmnd being written because
-- curdesc gets written to queue
elsif(writing_curdesc = '1')then
m_axis_mm2s_tready_i <= '0';
-- First two words drive ready from internal logic
elsif(fetch_word_count = WORD_ZERO or fetch_word_count = WORD_ONE)then
m_axis_mm2s_tready_i <= nxtdesc_tready;
-- Remainder stream words drive ready from channel input
else
m_axis_mm2s_tready_i <= (ch1_ftch_active and ch1_ftch_tready)
or (ch2_ftch_active and ch2_ftch_tready);
end if;
end process TREADY_MUX;
m_axis_mm2s_tready <= m_axis_mm2s_tready_i;
end implementation;
|
gpl-2.0
|
c5399a276a0cd5b98189d4cbc3bbab96
| 0.405385 | 4.629187 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_pipelined_adder.vhd
| 4 | 2,424 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_pipelined_adder is
generic (
OR_ACLR_INPUTS : natural := 1;
SIGNED : integer := 0;
NDIRECTION : integer := 1;
USE_CARRY_OUT_PORT : natural := 1;
USE_CARRY_PORT : natural := 1;
WIDTH : natural := 0;
PIPELINE : integer := 0
);
port (
user_aclr : in std_logic;
result : out std_logic_vector(width-1 downto 0);
clock : in std_logic;
dataa : in std_logic_vector(width-1 downto 0);
datab : in std_logic_vector(width-1 downto 0);
cout : out std_logic;
add_sub : in std_logic;
aclr : in std_logic;
cin : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_pipelined_adder;
architecture rtl of alt_dspbuilder_pipelined_adder is
component alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic (
OR_ACLR_INPUTS : natural := 1;
SIGNED : integer := 0;
NDIRECTION : integer := 0;
USE_CARRY_OUT_PORT : natural := 0;
USE_CARRY_PORT : natural := 0;
WIDTH : natural := 0;
PIPELINE : integer := 0
);
port (
aclr : in std_logic;
clock : in std_logic;
dataa : in std_logic_vector(0-1 downto 0);
datab : in std_logic_vector(0-1 downto 0);
ena : in std_logic;
result : out std_logic_vector(0-1 downto 0);
user_aclr : in std_logic
);
end component alt_dspbuilder_pipelined_adder_GNWEIMU3MK;
begin
alt_dspbuilder_pipelined_adder_GNWEIMU3MK_0: if ((OR_ACLR_INPUTS = 1) and (SIGNED = 0) and (NDIRECTION = 0) and (USE_CARRY_OUT_PORT = 0) and (USE_CARRY_PORT = 0) and (WIDTH = 0) and (PIPELINE = 0)) generate
inst_alt_dspbuilder_pipelined_adder_GNWEIMU3MK_0: alt_dspbuilder_pipelined_adder_GNWEIMU3MK
generic map(OR_ACLR_INPUTS => 1, SIGNED => 0, NDIRECTION => 0, USE_CARRY_OUT_PORT => 0, USE_CARRY_PORT => 0, WIDTH => 0, PIPELINE => 0)
port map(aclr => aclr, clock => clock, dataa => dataa, datab => datab, ena => ena, result => result, user_aclr => user_aclr);
end generate;
assert not (((OR_ACLR_INPUTS = 1) and (SIGNED = 0) and (NDIRECTION = 0) and (USE_CARRY_OUT_PORT = 0) and (USE_CARRY_PORT = 0) and (WIDTH = 0) and (PIPELINE = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
a8bf0d08e32eaeb955b9e810426136d4
| 0.682343 | 3.076142 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_axi_iic_0_0/synth/tutorial_axi_iic_0_0.vhd
| 1 | 10,095 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_iic:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_iic_v2_0;
USE axi_iic_v2_0.axi_iic;
ENTITY tutorial_axi_iic_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
iic2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
sda_i : IN STD_LOGIC;
sda_o : OUT STD_LOGIC;
sda_t : OUT STD_LOGIC;
scl_i : IN STD_LOGIC;
scl_o : OUT STD_LOGIC;
scl_t : OUT STD_LOGIC;
gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END tutorial_axi_iic_0_0;
ARCHITECTURE tutorial_axi_iic_0_0_arch OF tutorial_axi_iic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_axi_iic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_iic IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_IIC_FREQ : INTEGER;
C_TEN_BIT_ADR : INTEGER;
C_GPO_WIDTH : INTEGER;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_SCL_INERTIAL_DELAY : INTEGER;
C_SDA_INERTIAL_DELAY : INTEGER;
C_SDA_LEVEL : INTEGER;
C_SMBUS_PMBUS_HOST : INTEGER;
C_DEFAULT_VALUE : STD_LOGIC_VECTOR(7 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
iic2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
sda_i : IN STD_LOGIC;
sda_o : OUT STD_LOGIC;
sda_t : OUT STD_LOGIC;
scl_i : IN STD_LOGIC;
scl_o : OUT STD_LOGIC;
scl_t : OUT STD_LOGIC;
gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axi_iic;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tutorial_axi_iic_0_0_arch: ARCHITECTURE IS "axi_iic,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tutorial_axi_iic_0_0_arch : ARCHITECTURE IS "tutorial_axi_iic_0_0,axi_iic,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tutorial_axi_iic_0_0_arch: ARCHITECTURE IS "tutorial_axi_iic_0_0,axi_iic,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_iic,x_ipVersion=2.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_IIC_FREQ=100000,C_TEN_BIT_ADR=0,C_GPO_WIDTH=1,C_S_AXI_ACLK_FREQ_HZ=76000000,C_SCL_INERTIAL_DELAY=0,C_SDA_INERTIAL_DELAY=0,C_SDA_LEVEL=1,C_SMBUS_PMBUS_HOST=0,C_DEFAULT_VALUE=0x00}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF iic2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF sda_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_I";
ATTRIBUTE X_INTERFACE_INFO OF sda_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_O";
ATTRIBUTE X_INTERFACE_INFO OF sda_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_T";
ATTRIBUTE X_INTERFACE_INFO OF scl_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_I";
ATTRIBUTE X_INTERFACE_INFO OF scl_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_O";
ATTRIBUTE X_INTERFACE_INFO OF scl_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_T";
BEGIN
U0 : axi_iic
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_IIC_FREQ => 100000,
C_TEN_BIT_ADR => 0,
C_GPO_WIDTH => 1,
C_S_AXI_ACLK_FREQ_HZ => 76000000,
C_SCL_INERTIAL_DELAY => 0,
C_SDA_INERTIAL_DELAY => 0,
C_SDA_LEVEL => 1,
C_SMBUS_PMBUS_HOST => 0,
C_DEFAULT_VALUE => X"00"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
iic2intc_irpt => iic2intc_irpt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
sda_i => sda_i,
sda_o => sda_o,
sda_t => sda_t,
scl_i => scl_i,
scl_o => scl_o,
scl_t => scl_t,
gpo => gpo
);
END tutorial_axi_iic_0_0_arch;
|
gpl-2.0
|
b5bb92b7f77f9c22ad49855e530d54fb
| 0.685092 | 3.171536 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_intrpt.vhd
| 1 | 30,808 |
-------------------------------------------------------------------------------
-- axi_sg_intrpt
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_intrpt.vhd
-- Description: This entity handles interrupt coalescing
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 6/14/10 v1_00_a
-- ^^^^^^
-- CR565366
-- Fixed issue where simultaneous sof and eof caused delay timer to not enable
-- thus missing a delay interrupt. This issue occurs with small packets(i.e.
-- 2 data beats)
-- ~~~~~~
-- GAB 7/1/10 v1_00_a
-- ^^^^^^
-- CR567661
-- Remapped interrupt threshold control to be driven based on whether update
-- engine is included or not. Renamed interrupt threshold decrement control here
-- to match change in upper level.
-- ~~~~~~
-- GAB 8/3/10 v1_00_a
-- ^^^^^^
-- CR570398
-- Routed dlyirq_wren to reset delay timer logic on assertion
-- ~~~~~~
-- GAB 8/12/10 v1_00_a
-- ^^^^^^
-- CR572013
-- Added ability to disable threshold count reset on delay timer timeout in
-- order to match legacy SDMA operation.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_intrpt is
generic(
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_CH2 : integer range 0 to 1 := 1 ;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1 ;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125
-- Interrupt Delay Timer resolution in usec
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ch1_irqthresh_decr : in std_logic ;-- CR567661 --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
ch2_irqthresh_decr : in std_logic ;-- CR567661 --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) --
);
end axi_sg_intrpt;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_intrpt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Delay interrupt fast counter width
constant FAST_COUNT_WIDTH : integer := clog2(C_DLYTMR_RESOLUTION+1);
-- Delay interrupt fast counter terminal count
constant FAST_COUNT_TC : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_DLYTMR_RESOLUTION-1),FAST_COUNT_WIDTH));
-- Delay interrupt fast counter zero value
constant ZERO_FAST_COUNT : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_VALUE : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch1_dly_irq_set_i : std_logic := '0';
signal ch1_ioc_irq_set_i : std_logic := '0';
signal ch1_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch1_delay_cnt_en : std_logic := '0';
signal ch1_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch1_dly_fast_incr : std_logic := '0';
signal ch1_delay_zero : std_logic := '0';
signal ch1_delay_tc : std_logic := '0';
signal ch1_disable_delay : std_logic := '0';
signal ch2_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch2_dly_irq_set_i : std_logic := '0';
signal ch2_ioc_irq_set_i : std_logic := '0';
signal ch2_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch2_delay_cnt_en : std_logic := '0';
signal ch2_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch2_dly_fast_incr : std_logic := '0';
signal ch2_delay_zero : std_logic := '0';
signal ch2_delay_tc : std_logic := '0';
signal ch2_disable_delay : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Transmit channel included therefore generate transmit interrupt logic
GEN_INCLUDE_MM2S : if C_INCLUDE_CH1 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_thresh_count <= ONE_THRESHOLD;
ch1_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch1_irqthresh_wren = '1' or ch1_dly_irq_set_i = '1') then
elsif( (ch1_irqthresh_wren = '1')
or (ch1_dly_irq_set_i = '1' and ch1_irqthresh_rstdsbl = '0')) then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch1_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch1_thresh_count = ONE_THRESHOLD)then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '1';
else
ch1_thresh_count <= std_logic_vector(unsigned(ch1_thresh_count(7 downto 0)) - 1);
ch1_ioc_irq_set_i <= '0';
end if;
else
ch1_thresh_count <= ch1_thresh_count;
ch1_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch1_irqthresh_status <= ch1_thresh_count;
ch1_ioc_irq_set <= ch1_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH1_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
GEN_CH1_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '0';
elsif(ch1_dly_fast_cnt = ZERO_FAST_COUNT)then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '1';
else
ch1_dly_fast_cnt <= std_logic_vector(unsigned(ch1_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch1_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_FAST_COUNTER;
GEN_CH1_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_incr <= '0';
else
ch1_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch1_delay_zero <= '1' when ch1_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch1_delay_tc <= '1' when ch1_delay_count = ch1_irqdelay
and ch1_delay_zero = '0'
and ch1_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch1_disable_delay <= '1' when ch1_delay_zero = '1'
or ch1_dlyirq_dsble = '1'
or ch1_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '0';
elsif(ch1_dly_fast_incr = '1' and ch1_delay_tc = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '1';
elsif(ch1_dly_fast_incr = '1')then
ch1_delay_count <= std_logic_vector(unsigned(ch1_delay_count(7 downto 0)) + 1);
ch1_dly_irq_set_i <= '0';
else
ch1_delay_count <= ch1_delay_count;
ch1_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch1_irqdelay_status <= ch1_delay_count;
ch1_dly_irq_set <= ch1_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_disable_delay = '1')then
ch1_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch1_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch1_delay_cnt_en = '1' and ch1_packet_sof = '1'
and ch1_packet_eof = '0')then
ch1_delay_cnt_en <= '0';
elsif(ch1_packet_eof = '1')then
ch1_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH1_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH1_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch1_dly_irq_set <= '0';
ch1_dly_irq_set_i <= '0';
ch1_irqdelay_status <= (others => '0');
end generate GEN_NO_CH1_DELAY_INTR;
end generate GEN_INCLUDE_MM2S;
-- Receive channel included therefore generate receive interrupt logic
GEN_INCLUDE_S2MM : if C_INCLUDE_CH2 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_thresh_count <= ONE_THRESHOLD;
ch2_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch2_irqthresh_wren = '1' or ch2_dly_irq_set_i = '1') then
elsif( (ch2_irqthresh_wren = '1')
or (ch2_dly_irq_set_i = '1' and ch2_irqthresh_rstdsbl = '0')) then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch2_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch2_thresh_count = ONE_THRESHOLD)then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '1';
else
ch2_thresh_count <= std_logic_vector(unsigned(ch2_thresh_count(7 downto 0)) - 1);
ch2_ioc_irq_set_i <= '0';
end if;
else
ch2_thresh_count <= ch2_thresh_count;
ch2_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch2_irqthresh_status <= ch2_thresh_count;
ch2_ioc_irq_set <= ch2_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH2_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
GEN_CH2_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '0';
elsif(ch2_dly_fast_cnt = ZERO_FAST_COUNT)then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '1';
else
ch2_dly_fast_cnt <= std_logic_vector(unsigned(ch2_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch2_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_FAST_COUNTER;
GEN_CH2_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_incr <= '0';
else
ch2_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch2_delay_zero <= '1' when ch2_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch2_delay_tc <= '1' when ch2_delay_count = ch2_irqdelay
and ch2_delay_zero = '0'
and ch2_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch2_disable_delay <= '1' when ch2_delay_zero = '1'
or ch2_dlyirq_dsble = '1'
or ch2_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '0';
elsif(ch2_dly_fast_incr = '1' and ch2_delay_tc = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '1';
elsif(ch2_dly_fast_incr = '1')then
ch2_delay_count <= std_logic_vector(unsigned(ch2_delay_count(7 downto 0)) + 1);
ch2_dly_irq_set_i <= '0';
else
ch2_delay_count <= ch2_delay_count;
ch2_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch2_irqdelay_status <= ch2_delay_count;
ch2_dly_irq_set <= ch2_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_disable_delay = '1')then
ch2_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch2_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch2_delay_cnt_en = '1' and ch2_packet_sof = '1'
and ch2_packet_eof = '0')then
ch2_delay_cnt_en <= '0';
elsif(ch2_packet_eof = '1')then
ch2_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH2_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH2_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch2_dly_irq_set <= '0';
ch2_dly_irq_set_i <= '0';
ch2_irqdelay_status <= (others => '0');
end generate GEN_NO_CH2_DELAY_INTR;
end generate GEN_INCLUDE_S2MM;
-- Transmit channel not included therefore associated outputs to zero
GEN_EXCLUDE_MM2S : if C_INCLUDE_CH1 = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_MM2S;
-- Receive channel not included therefore associated outputs to zero
GEN_EXCLUDE_S2MM : if C_INCLUDE_CH2 = 0 generate
begin
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_S2MM;
end implementation;
|
gpl-2.0
|
88f2641fdc04b9c2dfa5df71d2a59860
| 0.462867 | 4.019833 | false | false | false | false |
nulldozer/purisc
|
Compute_Group/MAGIC_clocked/MAGIC.vhd
| 2 | 23,972 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MAGIC is
PORT (
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
HAZ_GLOB : IN STD_LOGIC;
--HAZARD_TEST : OUT STD_LOGIC;
DATA_OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
C0_STALL : OUT STD_LOGIC;
C1_STALL : OUT STD_LOGIC;
CORE_IDENT : OUT STD_LOGIC;
IO_ENABLE : IN STD_LOGIC
);
end;
architecture magic of MAGIC is
component SETUP
PORT(
CLK : IN STD_LOGIC;
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
STALL : OUT STD_LOGIC;
HAZARD : IN STD_LOGIC;
ram_0_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_0_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_0_wren_a : OUT STD_LOGIC;
ram_0_wren_b : OUT STD_LOGIC;
ram_1_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_1_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_1_wren_a : OUT STD_LOGIC;
ram_1_wren_b : OUT STD_LOGIC;
ram_2_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_2_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_2_wren_a : OUT STD_LOGIC;
ram_2_wren_b : OUT STD_LOGIC;
ram_3_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_3_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_3_wren_a : OUT STD_LOGIC;
ram_3_wren_b : OUT STD_LOGIC;
ram_4_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_4_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_4_wren_a : OUT STD_LOGIC;
ram_4_wren_b : OUT STD_LOGIC;
ram_5_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_5_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_5_wren_a : OUT STD_LOGIC;
ram_5_wren_b : OUT STD_LOGIC;
ram_6_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_6_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_6_wren_a : OUT STD_LOGIC;
ram_6_wren_b : OUT STD_LOGIC;
ram_7_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_7_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_7_wren_a : OUT STD_LOGIC;
ram_7_wren_b : OUT STD_LOGIC;
ram_0_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_1_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_2_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_3_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_4_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_5_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_6_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_7_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end component;
component ROUTE
PORT(
hazard : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
ram_0_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_1_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_2_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_3_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_4_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_5_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_6_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_7_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
OUTPUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OUTPUT_B : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OUTPUT_C : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OUTPUT_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OUTPUT_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end component;
component RAM_0
PORT
(
aclr : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (9 downto 0);
address_b : IN STD_LOGIC_VECTOR (9 downto 0);
clock : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component RAM_1
PORT
(
aclr : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (9 downto 0);
address_b : IN STD_LOGIC_VECTOR (9 downto 0);
clock : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component RAM_2
PORT
(
aclr : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (9 downto 0);
address_b : IN STD_LOGIC_VECTOR (9 downto 0);
clock : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component RAM_3
PORT
(
aclr : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (9 downto 0);
address_b : IN STD_LOGIC_VECTOR (9 downto 0);
clock : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component RAM_4
PORT
(
aclr : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (9 downto 0);
address_b : IN STD_LOGIC_VECTOR (9 downto 0);
clock : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component RAM_5
PORT
(
aclr : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (9 downto 0);
address_b : IN STD_LOGIC_VECTOR (9 downto 0);
clock : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component RAM_6
PORT
(
aclr : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (9 downto 0);
address_b : IN STD_LOGIC_VECTOR (9 downto 0);
clock : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component RAM_7
PORT
(
aclr : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (9 downto 0);
address_b : IN STD_LOGIC_VECTOR (9 downto 0);
clock : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal address_a_sig : std_logic_vector (31 downto 0);
signal address_b_sig : std_logic_vector (31 downto 0);
signal address_c_sig : std_logic_vector (31 downto 0);
signal address_0_sig : std_logic_vector (31 downto 0);
signal address_1_sig : std_logic_vector (31 downto 0);
signal address_w_sig : std_logic_vector (31 downto 0);
signal data_to_w_sig : std_logic_vector (31 downto 0);
signal w_en_sig : std_logic;
signal RESET : std_logic;
signal stall_flag : std_logic;
signal hazard : std_logic;
signal hazard_w_io : std_logic;
signal io_buffer_en : std_logic;
signal ram_0_port_a : std_logic_vector (9 downto 0);
signal ram_0_port_b : std_logic_vector (9 downto 0);
signal ram_0_wren_a : std_logic;
signal ram_0_wren_b : std_logic;
signal ram_1_port_a : std_logic_vector (9 downto 0);
signal ram_1_port_b : std_logic_vector (9 downto 0);
signal ram_1_wren_a : std_logic;
signal ram_1_wren_b : std_logic;
signal ram_2_port_a : std_logic_vector (9 downto 0);
signal ram_2_port_b : std_logic_vector (9 downto 0);
signal ram_2_wren_a : std_logic;
signal ram_2_wren_b : std_logic;
signal ram_3_port_a : std_logic_vector (9 downto 0);
signal ram_3_port_b : std_logic_vector (9 downto 0);
signal ram_3_wren_a : std_logic;
signal ram_3_wren_b : std_logic;
signal ram_4_port_a : std_logic_vector (9 downto 0);
signal ram_4_port_b : std_logic_vector (9 downto 0);
signal ram_4_wren_a : std_logic;
signal ram_4_wren_b : std_logic;
signal ram_5_port_a : std_logic_vector (9 downto 0);
signal ram_5_port_b : std_logic_vector (9 downto 0);
signal ram_5_wren_a : std_logic;
signal ram_5_wren_b : std_logic;
signal ram_6_port_a : std_logic_vector (9 downto 0);
signal ram_6_port_b : std_logic_vector (9 downto 0);
signal ram_6_wren_a : std_logic;
signal ram_6_wren_b : std_logic;
signal ram_7_port_a : std_logic_vector (9 downto 0);
signal ram_7_port_b : std_logic_vector (9 downto 0);
signal ram_7_wren_a : std_logic;
signal ram_7_wren_b : std_logic;
signal ram_0_sel_vector : std_logic_vector(9 downto 0);
signal ram_1_sel_vector : std_logic_vector(9 downto 0);
signal ram_2_sel_vector : std_logic_vector(9 downto 0);
signal ram_3_sel_vector : std_logic_vector(9 downto 0);
signal ram_4_sel_vector : std_logic_vector(9 downto 0);
signal ram_5_sel_vector : std_logic_vector(9 downto 0);
signal ram_6_sel_vector : std_logic_vector(9 downto 0);
signal ram_7_sel_vector : std_logic_vector(9 downto 0);
signal ram_0_sel : std_logic_vector(9 downto 0);
signal ram_1_sel : std_logic_vector(9 downto 0);
signal ram_2_sel : std_logic_vector(9 downto 0);
signal ram_3_sel : std_logic_vector(9 downto 0);
signal ram_4_sel : std_logic_vector(9 downto 0);
signal ram_5_sel : std_logic_vector(9 downto 0);
signal ram_6_sel : std_logic_vector(9 downto 0);
signal ram_7_sel : std_logic_vector(9 downto 0);
signal ram_0_out_a : std_logic_vector (31 downto 0);
signal ram_0_out_b : std_logic_vector (31 downto 0);
signal ram_1_out_a : std_logic_vector (31 downto 0);
signal ram_1_out_b : std_logic_vector (31 downto 0);
signal ram_2_out_a : std_logic_vector (31 downto 0);
signal ram_2_out_b : std_logic_vector (31 downto 0);
signal ram_3_out_a : std_logic_vector (31 downto 0);
signal ram_3_out_b : std_logic_vector (31 downto 0);
signal ram_4_out_a : std_logic_vector (31 downto 0);
signal ram_4_out_b : std_logic_vector (31 downto 0);
signal ram_5_out_a : std_logic_vector (31 downto 0);
signal ram_5_out_b : std_logic_vector (31 downto 0);
signal ram_6_out_a : std_logic_vector (31 downto 0);
signal ram_6_out_b : std_logic_vector (31 downto 0);
signal ram_7_out_a : std_logic_vector (31 downto 0);
signal ram_7_out_b : std_logic_vector (31 downto 0);
signal output_a : std_logic_vector (31 downto 0);
signal output_b : std_logic_vector (31 downto 0);
signal output_c : std_logic_vector (31 downto 0);
signal output_0 : std_logic_vector (31 downto 0);
signal output_1 : std_logic_vector (31 downto 0);
signal stall : std_logic;
signal hold : std_logic;
signal core_id : std_logic;
signal c0_stall_sig : std_logic;
signal c1_stall_sig : std_logic;
signal hazard_advanced : std_logic;
--
begin
input_control : SETUP PORT MAP (
CLK => CLK,
ADDRESS_A => address_a_sig,
ADDRESS_B => address_b_sig,
ADDRESS_C => address_c_sig,
ADDRESS_0 => address_0_sig,
ADDRESS_1 => address_1_sig,
ADDRESS_W => address_w_sig,
W_EN => w_en_sig,
RESET_n => RESET_n,
STALL => stall_flag,
HAZARD => hazard,
ram_0_port_a => ram_0_port_a,
ram_0_port_b => ram_0_port_b,
ram_0_wren_a => ram_0_wren_a,
ram_0_wren_b => ram_0_wren_b,
ram_1_port_a => ram_1_port_a,
ram_1_port_b => ram_1_port_b,
ram_1_wren_a => ram_1_wren_a,
ram_1_wren_b => ram_1_wren_b,
ram_2_port_a => ram_2_port_a,
ram_2_port_b => ram_2_port_b,
ram_2_wren_a => ram_2_wren_a,
ram_2_wren_b => ram_2_wren_b,
ram_3_port_a => ram_3_port_a,
ram_3_port_b => ram_3_port_b,
ram_3_wren_a => ram_3_wren_a,
ram_3_wren_b => ram_3_wren_b,
ram_4_port_a => ram_4_port_a,
ram_4_port_b => ram_4_port_b,
ram_4_wren_a => ram_4_wren_a,
ram_4_wren_b => ram_4_wren_b,
ram_5_port_a => ram_5_port_a,
ram_5_port_b => ram_5_port_b,
ram_5_wren_a => ram_5_wren_a,
ram_5_wren_b => ram_5_wren_b,
ram_6_port_a => ram_6_port_a,
ram_6_port_b => ram_6_port_b,
ram_6_wren_a => ram_6_wren_a,
ram_6_wren_b => ram_6_wren_b,
ram_7_port_a => ram_7_port_a,
ram_7_port_b => ram_7_port_b,
ram_7_wren_a => ram_7_wren_a,
ram_7_wren_b => ram_7_wren_b,
ram_0_sel_vector => ram_0_sel_vector,
ram_1_sel_vector => ram_1_sel_vector,
ram_2_sel_vector => ram_2_sel_vector,
ram_3_sel_vector => ram_3_sel_vector,
ram_4_sel_vector => ram_4_sel_vector,
ram_5_sel_vector => ram_5_sel_vector,
ram_6_sel_vector => ram_6_sel_vector,
ram_7_sel_vector => ram_7_sel_vector
);
RAM_0_inst : RAM_0 PORT MAP (
aclr => RESET,
address_a => ram_0_port_a,
address_b => ram_0_port_b,
clock => CLK,
data_a => data_to_w_sig,
data_b => data_to_w_sig,
wren_a => ram_0_wren_a,
wren_b => ram_0_wren_b,
q_a => ram_0_out_a,
q_b => ram_0_out_b
);
RAM_1_inst : RAM_1 PORT MAP (
aclr => RESET,
address_a => ram_1_port_a,
address_b => ram_1_port_b,
clock => CLK,
data_a => data_to_w_sig,
data_b => data_to_w_sig,
wren_a => ram_1_wren_a,
wren_b => ram_1_wren_b,
q_a => ram_1_out_a,
q_b => ram_1_out_b
);
RAM_2_inst : RAM_2 PORT MAP (
aclr => RESET,
address_a => ram_2_port_a,
address_b => ram_2_port_b,
clock => CLK,
data_a => data_to_w_sig,
data_b => data_to_w_sig,
wren_a => ram_2_wren_a,
wren_b => ram_2_wren_b,
q_a => ram_2_out_a,
q_b => ram_2_out_b
);
RAM_3_inst : RAM_3 PORT MAP (
aclr => RESET,
address_a => ram_3_port_a,
address_b => ram_3_port_b,
clock => CLK,
data_a => data_to_w_sig,
data_b => data_to_w_sig,
wren_a => ram_3_wren_a,
wren_b => ram_3_wren_b,
q_a => ram_3_out_a,
q_b => ram_3_out_b
);
RAM_4_inst : RAM_4 PORT MAP (
aclr => RESET,
address_a => ram_4_port_a,
address_b => ram_4_port_b,
clock => CLK,
data_a => data_to_w_sig,
data_b => data_to_w_sig,
wren_a => ram_4_wren_a,
wren_b => ram_4_wren_b,
q_a => ram_4_out_a,
q_b => ram_4_out_b
);
RAM_5_inst : RAM_5 PORT MAP (
aclr => RESET,
address_a => ram_5_port_a,
address_b => ram_5_port_b,
clock => CLK,
data_a => data_to_w_sig,
data_b => data_to_w_sig,
wren_a => ram_5_wren_a,
wren_b => ram_5_wren_b,
q_a => ram_5_out_a,
q_b => ram_5_out_b
);
RAM_6_inst : RAM_6 PORT MAP (
aclr => RESET,
address_a => ram_6_port_a,
address_b => ram_6_port_b,
clock => CLK,
data_a => data_to_w_sig,
data_b => data_to_w_sig,
wren_a => ram_6_wren_a,
wren_b => ram_6_wren_b,
q_a => ram_6_out_a,
q_b => ram_6_out_b
);
RAM_7_inst : RAM_7 PORT MAP (
aclr => RESET,
address_a => ram_7_port_a,
address_b => ram_7_port_b,
clock => CLK,
data_a => data_to_w_sig,
data_b => data_to_w_sig,
wren_a => ram_7_wren_a,
wren_b => ram_7_wren_b,
q_a => ram_7_out_a,
q_b => ram_7_out_b
);
output_control : ROUTE PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
hazard => hazard_w_io,
hazard_advanced => hazard_advanced,
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
ram_0_sel_vector => ram_0_sel,
ram_1_sel_vector => ram_1_sel,
ram_2_sel_vector => ram_2_sel,
ram_3_sel_vector => ram_3_sel,
ram_4_sel_vector => ram_4_sel,
ram_5_sel_vector => ram_5_sel,
ram_6_sel_vector => ram_6_sel,
ram_7_sel_vector => ram_7_sel,
OUTPUT_A => output_a,
OUTPUT_B => output_b,
OUTPUT_C => output_c,
OUTPUT_0 => output_0,
OUTPUT_1 => output_1
);
-- latch_outputs : process (CLK, RESET_n) begin
-- if (RESET_n = '0') then
-- DATA_OUT_A <= "00000000000000000000000000000000";
-- DATA_OUT_B <= "00000000000000000000000000000000";
-- DATA_OUT_C <= "00000000000000000000000000000000";
-- DATA_OUT_0 <= "00000000000000000000000000000000";
-- DATA_OUT_1 <= "00000000000000000000000000000000";
-- elsif (rising_edge(CLK)) then
-- DATA_OUT_A <= output_a;
-- DATA_OUT_B <= output_b;
-- DATA_OUT_C <= output_c;
-- DATA_OUT_0 <= output_0;
-- DATA_OUT_1 <= output_1;
-- end if;
-- end process;
--********above latching used for testing************
DATA_OUT_A <= output_a;
DATA_OUT_B <= output_b;
DATA_OUT_C <= output_c;
DATA_OUT_0 <= output_0;
DATA_OUT_1 <= output_1;
latch_vectors : process (CLK, RESET_n) begin
if (RESET_n = '0') then
ram_0_sel <= "0000000000";
ram_1_sel <= "0000000000";
ram_2_sel <= "0000000000";
ram_3_sel <= "0000000000";
ram_4_sel <= "0000000000";
ram_5_sel <= "0000000000";
ram_6_sel <= "0000000000";
ram_7_sel <= "0000000000";
hazard <= '0';
elsif (rising_edge(CLK)) then
ram_0_sel <= ram_0_sel_vector;
ram_1_sel <= ram_1_sel_vector;
ram_2_sel <= ram_2_sel_vector;
ram_3_sel <= ram_3_sel_vector;
ram_4_sel <= ram_4_sel_vector;
ram_5_sel <= ram_5_sel_vector;
ram_6_sel <= ram_6_sel_vector;
ram_7_sel <= ram_7_sel_vector;
hazard <= stall_flag;
end if;
end process;
-- latch_inputs : process (CLK, RESET_n) begin
-- if (RESET_n = '0') then
-- address_a_sig <= "00000000000000000000000000000000";
-- address_b_sig <= "00000000000000000000000000000000";
-- address_c_sig <= "00000000000000000000000000000000";
-- address_0_sig <= "00000000000000000000000000000000";
-- address_1_sig <= "00000000000000000000000000000000";
-- address_w_sig <= "00000000000000000000000000000000";
-- data_to_w_sig <= "00000000000000000000000000000000";
-- w_en_sig <= '0';
-- elsif (rising_edge(CLK)) then
-- address_a_sig <= ADDRESS_A;
-- address_b_sig <= ADDRESS_B;
-- address_c_sig <= ADDRESS_C;
-- address_0_sig <= ADDRESS_0;
-- address_1_sig <= ADDRESS_1;
-- address_w_sig <= ADDRESS_W;
-- data_to_w_sig <= DATA_TO_W;
-- w_en_sig <= W_EN;
-- end if;
-- end process;
--********above latching used for testing***************
address_a_sig <= ADDRESS_A;
address_b_sig <= ADDRESS_B;
address_c_sig <= ADDRESS_C;
address_0_sig <= ADDRESS_0;
address_1_sig <= ADDRESS_1;
address_w_sig <= ADDRESS_W;
data_to_w_sig <= DATA_TO_W;
w_en_sig <= W_EN;
RESET <= not RESET_n;
stall <= stall_flag or hazard_w_io; --maybe without io
hold <= c0_stall_sig and c1_stall_sig;
C0_STALL <= (not core_id) or c0_stall_sig; --flipped not statement
C1_STALL <= (core_id) or c1_stall_sig; --between these two lines
CORE_IDENT <= core_id;
hazard_w_io <= hazard or io_buffer_en;
--HAZARD_TEST <= hazard_w_io; --THIS IS FOR DEBUGGING
hazard_advanced <= hazard_w_io or stall_flag or HAZ_GLOB; --ALSO NEW
id_gen : process (CLK, RESET_n, hold) begin
if (RESET_n = '0') then
core_id <= '0';
elsif (rising_edge(CLK)) then
if (hold = '0' and IO_ENABLE = '0') then
core_id <= not core_id;
end if;
end if;
end process;
override_io : process (CLK, RESET_n) begin
if (RESET_n = '0') then
io_buffer_en <= '0';
elsif (rising_edge(CLK)) then
io_buffer_en <= IO_ENABLE;
end if;
end process;
stalling : process (core_id, stall_flag, stall) begin
if (core_id = '0' and stall = '1') then
c0_stall_sig <= stall;
c1_stall_sig <= stall_flag;
elsif (core_id = '1' and stall = '1') then
c0_stall_sig <= stall_flag;
c1_stall_sig <= stall;
else
c0_stall_sig <= '0';
c1_stall_sig <= '0';
end if;
end process;
end;
|
gpl-2.0
|
fced638b8bf265a6bbe266e72332b705
| 0.553521 | 2.658239 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_ASAT.vhd
| 20 | 3,282 |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_ASAT is
generic (
widthin : natural :=8;
widthout : natural :=4;
lpm_signed : BusArithm :=BusIsSigned
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_ASAT;
architecture ASAT_SYNTH of alt_dspbuilder_ASAT is
function GetWidthUsgn(win: natural;wout: natural ) return natural is
variable res : natural;
begin
if (win-wout>0) then
res :=win-wout-1;
else
res := 0;
end if;
return res;
end ;
signal msbone : std_logic_vector(widthin-widthout downto 0);
signal msbzero : std_logic_vector(widthin-widthout downto 0);
signal Unsignedmsbzero : std_logic_vector(GetWidthUsgn(widthin,widthout) downto 0);
signal MsbOverFlow : std_logic;
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
sat:if (widthin>widthout) generate
Gs : if lpm_signed=BusIsSigned generate
msbone <= (others=>'1');
msbzero <= (others=>'0');
MsbOverFlow <= '0' when (xin(widthin-1 downto widthout-1) = msbone or xin(widthin-1 downto widthout-1) = msbzero) else '1';
process(xin,MsbOverFlow)
begin
if (MsbOverFlow='0') then
yout(widthout-1 downto 0) <= xin(widthout-1 downto 0);
else
if (xin(widthin-1)='0') then
for i in 0 to widthout-2 loop
yout(i) <= '1'; -- max positif
end loop;
yout(widthout-1) <='0';
else
for i in 0 to widthout-2 loop
yout(i) <= '0'; -- max Negatif
end loop;
yout(widthout-1) <='1';
end if;
end if;
end process;
end generate Gs;
Gus : if lpm_signed=BusIsUnsigned generate
Unsignedmsbzero <= (others=>'0');
MsbOverFlow <= '0' when xin(widthin-1 downto widthout) = Unsignedmsbzero else '1';
process(xin,MsbOverFlow)
begin
if (MsbOverFlow='0') then
yout(widthout-1 downto 0) <= xin(widthout-1 downto 0);
else
yout <=(others=>'1'); -- Max Positive
end if;
end process;
end generate Gus;
end generate sat;
end ASAT_SYNTH;
|
mit
|
6b3bed7ee320df0e31113800f016f1b6
| 0.652346 | 3.473016 | false | false | false | false |
bobxiv/DispositivosLogicosProgramables-FICH
|
Practica/Maquina de Estados VHDL/MaquinaEstados.vhd
| 1 | 1,680 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:11:24 09/27/11
-- Design Name:
-- Module Name: MaquinaEstados - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MaquinaEstados is
Port ( in1 : in std_logic;
in2 : in std_logic;
clock : in std_logic;
reset : in std_logic;
out1 : out std_logic;
out2 : out std_logic);
end MaquinaEstados;
architecture Behavioral of MaquinaEstados is
type estado is(E0, E1, E2);
signal estado_A: estado := E0;
signal estado_F: estado;
begin
process(estado_A, in1, in2)--Comb
begin
case estado_A is
when E0 =>
out1 <= '0';
out2 <= '0';
estado_F <= E1;
when E1 =>
out1 <= '1';
if in1='1' then
estado_F <= E2;
else
estado_F <= E0;
end if;
when E2 =>
out1 <= '1';
out2 <= '1';
estado_F <= E2;
end case;
end process;
process--Registro
begin
wait until reset='1' or rising_edge(clock);
if reset='1' then
estado_A <= E0;
else
estado_A <= estado_F;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
9f9f6766069bd02e07bfa77aaf3f34c0
| 0.533333 | 3.313609 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
Testbench/vme_sim_mstr.vhd
| 1 | 7,826 |
---------------------------------------------------------------
-- Title : VME Simulation Master Model
-- Project : 16z002-
---------------------------------------------------------------
-- File : vme_sim_mstr.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 14/02/12
---------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
---------------------------------------------------------------
-- Description :
--
-- Design consists of VME Master behavioral model and an arbiter.
-- The arbiter gets active if after startup the bg3n line is '0'.
-- The master model can read or write up to 32bit and 64bit
-- data width.
-- The control of the model is via terminal connection.
---------------------------------------------------------------
-- Hierarchy:
--
-- vme_sim_pack.vhd
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: vme_sim_mstr.vhd,v $
-- Revision 1.2 2013/04/18 15:11:12 MMiehling
-- rework
--
-- Revision 1.1 2012/03/29 10:28:47 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.terminal_pkg.all;
USE work.vme_sim_pack.all;
USE work.print_pkg.all;
ENTITY vme_sim_mstr IS
PORT (
sysresn : INOUT std_logic;
asn : INOUT std_logic;
dsan : INOUT std_logic;
dsbn : INOUT std_logic;
writen : INOUT std_logic;
dtackn : IN std_logic;
berrn : INOUT std_logic;
addr : INOUT std_logic_vector(31 DOWNTO 0);
data : INOUT std_logic_vector(31 DOWNTO 0);
am : INOUT std_logic_vector(5 DOWNTO 0);
iackn : INOUT std_logic;
iackout : OUT std_logic;
iackin : IN std_logic;
vb_irq1n : INOUT std_logic;
vb_irq2n : INOUT std_logic;
vb_irq3n : INOUT std_logic;
vb_irq4n : INOUT std_logic;
vb_irq5n : INOUT std_logic;
vb_irq6n : INOUT std_logic;
vb_irq7n : INOUT std_logic;
vb_acfailn : INOUT std_logic;
bg3n_in : IN std_logic;
bg3n_out : OUT std_logic;
brn : INOUT std_logic_vector(3 DOWNTO 0);
bbsyn : INOUT std_logic;
terminal_in_x : OUT terminal_in_type;
terminal_out_x : IN terminal_out_type
);
END vme_sim_mstr;
ARCHITECTURE vme_sim_mstr_arch OF vme_sim_mstr IS
SIGNAL mstr_in : mstr_in_type;
SIGNAL mstr_out : mstr_out_type;
SIGNAL sim_slot1 : boolean;
SIGNAL bg3n_int : std_logic;
SIGNAL bg3n_sim : std_logic;
SIGNAL busy : std_logic;
BEGIN
vb_irq1n <= 'H';
vb_irq2n <= 'H';
vb_irq3n <= 'H';
vb_irq4n <= 'H';
vb_irq5n <= 'H';
vb_irq6n <= 'H';
vb_irq7n <= 'H';
vb_acfailn <= 'H';
mstr_in.data <= data;
mstr_in.addr <= addr;
mstr_in.dtackn <= dtackn ;
mstr_in.berrn <= berrn ;
mstr_in.iackin <= iackin ;
mstr_in.bg3n_in <= bg3n_sim;
mstr_in.bbsyn <= bbsyn ;
mstr_in.asn <= asn ;
sysresn <= mstr_out.sysresn ;
asn <= mstr_out.asn ;
dsan <= mstr_out.dsan ;
dsbn <= mstr_out.dsbn ;
writen <= mstr_out.writen ;
addr <= mstr_out.addr ;
data <= mstr_out.data ;
am <= mstr_out.am ;
iackn <= mstr_out.iackn ;
iackout <= mstr_out.iackout ;
brn <= mstr_out.brn ;
bbsyn <= mstr_out.bbsyn ;
berrn <= mstr_out.berrn ;
sl1_det: PROCESS(sysresn)
BEGIN
IF rising_edge(sysresn) AND bg3n_in = '0' THEN
sim_slot1 <= TRUE;
ELSIF rising_edge(sysresn) AND bg3n_in = '1' THEN
sim_slot1 <= FALSE;
END IF;
END PROCESS sl1_det;
sim_arbiter: PROCESS(bg3n_in, sysresn, bbsyn, brn, sim_slot1)
BEGIN
IF sysresn = '0' THEN
bg3n_int <= '1';
bg3n_sim <= '0';
ELSIF sim_slot1 = TRUE THEN -- sim model is in slot1
-- IF brn(3) = '0' AND bbsyn /= '0' THEN -- there is a request
-- bg3n_int <= '0';
-- ELSE
-- bg3n_int <= '1';
-- END IF;
IF mstr_out.brn(3) = '0' AND bbsyn /= '0' AND bg3n_int /= '0' THEN -- there is a request from simmaster and no grant to dut
bg3n_int <= '1';
bg3n_sim <= '0'; -- grant TO simmaster
ELSIF brn(3) = '0' AND bbsyn /= '0' THEN -- there is a request from dut
bg3n_int <= '0'; -- grant to dut
bg3n_sim <= '1';
ELSE
bg3n_int <= '1';
bg3n_sim <= '1';
END IF;
ELSE
bg3n_int <= '1';
bg3n_sim <= bg3n_in;
END IF;
END PROCESS sim_arbiter;
bg3n_out <= bg3n_int;
main: PROCESS
VARIABLE ind_err : integer;
VARIABLE err : integer;
VARIABLE vme_typ : character;
VARIABLE in_data : std_logic_vector(31 DOWNTO 0);
BEGIN
-- reset phase
err := 0;
vme_mstr_init(mstr_out);
terminal_in_x.done <= TRUE;
terminal_in_x.busy <= '0';
busy <= '0';
LOOP
WAIT on terminal_out_x.start;
busy <= '1';
terminal_in_x.busy <= '1';
IF terminal_out_x.typ = 0 THEN
vme_typ := 'b';
ELSIF terminal_out_x.typ = 1 THEN
vme_typ := 'w';
ELSIF terminal_out_x.typ = 2 THEN
vme_typ := 'l';
ELSIF terminal_out_x.typ = 3 THEN
vme_typ := 'd';
ELSIF terminal_out_x.typ = 4 THEN
vme_typ := 'i';
ELSE
print("vme_sim_mstr: wrong terminal.typ coding!");
END IF;
IF vme_typ = 'd' AND terminal_out_x.wr = 0 AND terminal_out_x.numb > 1 THEN -- 64 bit read
vme_mstr_read64(mstr_out, mstr_in, terminal_out_x.adr, terminal_out_x.dat, in_data, vme_typ, terminal_out_x.txt, terminal_out_x.numb, terminal_out_x.tga, err);
ELSIF vme_typ = 'd' AND terminal_out_x.wr = 1 AND terminal_out_x.numb > 1 THEN -- 64 bit write
vme_mstr_write64(mstr_out, mstr_in, terminal_out_x.adr, terminal_out_x.dat, vme_typ, terminal_out_x.txt, terminal_out_x.numb, terminal_out_x.tga);
ELSIF terminal_out_x.wr = 0 THEN -- 32 or 16 or 8 bit read
vme_mstr_read(mstr_out, mstr_in, terminal_out_x.adr, terminal_out_x.dat, in_data, vme_typ, terminal_out_x.txt, terminal_out_x.numb, terminal_out_x.tga, err);
ELSIF terminal_out_x.wr = 1 THEN -- 32 or 16 or 8 bit write
vme_mstr_write(mstr_out, mstr_in, terminal_out_x.adr, terminal_out_x.dat, vme_typ, terminal_out_x.txt, terminal_out_x.numb, terminal_out_x.tga);
ELSIF terminal_out_x.wr = 2 THEN -- wait
WAIT FOR terminal_out_x.numb * 10 ns;
ELSE
print("vme_sim_mstr: wrong terminal.wr coding!");
END IF;
terminal_in_x.dat <= in_data;
terminal_in_x.err <= err;
terminal_in_x.busy <= '0';
busy <= '0';
terminal_in_x.done <= terminal_out_x.start;
END LOOP;
END PROCESS;
END vme_sim_mstr_arch;
|
gpl-3.0
|
87fe79121bf43c511d8e3334905d8d63
| 0.495017 | 3.4613 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/generic_pll/_primary.vhd
| 5 | 1,932 |
library verilog;
use verilog.vl_types.all;
entity generic_pll is
generic(
lpm_type : string := "generic_pll";
duty_cycle : integer := 50;
output_clock_frequency: string := "0 ps";
phase_shift : string := "0 ps";
reference_clock_frequency: string := "0 ps";
sim_additional_refclk_cycles_to_lock: integer := 0;
fractional_vco_multiplier: string := "false";
use_khz : integer := 1
);
port(
refclk : in vl_logic;
rst : in vl_logic;
fbclk : in vl_logic;
writerefclkdata : in vl_logic_vector(63 downto 0);
writeoutclkdata : in vl_logic_vector(63 downto 0);
writephaseshiftdata: in vl_logic_vector(63 downto 0);
writedutycycledata: in vl_logic_vector(63 downto 0);
outclk : out vl_logic;
locked : out vl_logic;
fboutclk : out vl_logic;
readrefclkdata : out vl_logic_vector(63 downto 0);
readoutclkdata : out vl_logic_vector(63 downto 0);
readphaseshiftdata: out vl_logic_vector(63 downto 0);
readdutycycledata: out vl_logic_vector(63 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of duty_cycle : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of phase_shift : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of sim_additional_refclk_cycles_to_lock : constant is 1;
attribute mti_svvh_generic_type of fractional_vco_multiplier : constant is 1;
attribute mti_svvh_generic_type of use_khz : constant is 1;
end generic_pll;
|
mit
|
39dd506cd3080c4b6740e8c36564e2e7
| 0.612836 | 3.736944 | false | false | false | false |
freecores/t48
|
bench/vhdl/tb.vhd
| 1 | 18,038 |
-------------------------------------------------------------------------------
--
-- The testbench for t48_core.
--
-- $Id: tb.vhd,v 1.14 2006-06-21 01:04:05 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb is
end tb;
use work.t48_core_comp_pack.all;
use work.t48_tb_pack.all;
architecture behav of tb is
-- clock period, 11 MHz
constant period_c : time := 90 ns;
component if_timing
port(
xtal_i : in std_logic;
ale_i : in std_logic;
psen_n_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
prog_n_i : in std_logic;
db_bus_i : in std_logic_vector(7 downto 0);
p2_i : in std_logic_vector(7 downto 0)
);
end component;
component lpm_rom
generic (
LPM_WIDTH : positive;
LPM_TYPE : string := "LPM_ROM";
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_FILE : string;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_HINT : string := "UNUSED"
);
port (
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
inclock : in std_logic;
outclock : in std_logic;
memenab : in std_logic;
q : out std_logic_vector(LPM_WIDTH-1 downto 0)
);
end component;
signal xtal_s : std_logic;
signal xtal_n_s : std_logic;
signal res_n_s : std_logic;
signal xtal3_s : std_logic;
signal int_n_s : std_logic;
signal ale_s : std_logic;
signal rom_addr_s : std_logic_vector(11 downto 0);
signal rom_data_s : std_logic_vector( 7 downto 0);
signal ram_data_to_s : std_logic_vector( 7 downto 0);
signal ram_data_from_s : std_logic_vector( 7 downto 0);
signal ram_addr_s : std_logic_vector( 7 downto 0);
signal ram_we_s : std_logic;
signal p1_s : std_logic_vector( 7 downto 0);
signal t48_p1_s : std_logic_vector( 7 downto 0);
signal p1_low_imp_s : std_logic;
signal p2_s : std_logic_vector( 7 downto 0);
signal t48_p2_s : std_logic_vector( 7 downto 0);
signal p2l_low_imp_s : std_logic;
signal p2h_low_imp_s : std_logic;
signal psen_n_s : std_logic;
signal prog_n_s : std_logic;
signal bus_s : std_logic_vector( 7 downto 0);
signal t48_bus_s : std_logic_vector( 7 downto 0);
signal bus_dir_s : std_logic;
signal ext_mem_addr_q : std_logic_vector( 7 downto 0);
signal ext_ram_data_from_s : std_logic_vector( 7 downto 0);
signal ext_ram_we_q : std_logic;
signal rd_n_s : std_logic;
signal wr_n_s : std_logic;
signal ext_rom_data_s : std_logic_vector( 7 downto 0);
signal ext_rom_addr_s : std_logic_vector(11 downto 0);
signal tb_p1_q : std_logic_vector( 7 downto 0);
signal tb_p2_q : std_logic_vector( 7 downto 0);
signal ext_mem_sel_we_q : boolean;
signal ena_ext_ram_q : boolean;
signal ena_tb_periph_q : boolean;
signal zero_s : std_logic;
signal one_s : std_logic;
signal zero_byte_s : std_logic_vector( 7 downto 0);
begin
zero_s <= '0';
one_s <= '1';
zero_byte_s <= (others => '0');
-----------------------------------------------------------------------------
-- Internal ROM, 2k bytes
-- Initialized by file rom_t49.hex.
-----------------------------------------------------------------------------
rom_internal_2k : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_TYPE => "LPM_ROM",
LPM_WIDTHAD => 11,
LPM_NUMWORDS => 2 ** 11,
LPM_FILE => "rom_t49.hex",
LPM_ADDRESS_CONTROL => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_HINT => "UNUSED"
)
port map (
address => rom_addr_s(10 downto 0),
inclock => xtal_s,
outclock => zero_s, -- unused
memenab => one_s,
q => rom_data_s
);
-----------------------------------------------------------------------------
-- External ROM, 2k bytes
-- Initialized by file rom_t49_ext.hex.
-----------------------------------------------------------------------------
ext_rom_addr_s(11 downto 8) <= t48_p2_s(3 downto 0);
ext_rom_addr_s( 7 downto 0) <= ext_mem_addr_q;
rom_external_2k : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_TYPE => "LPM_ROM",
LPM_WIDTHAD => 11,
LPM_NUMWORDS => 2 ** 11,
LPM_FILE => "rom_t49_ext.hex",
LPM_ADDRESS_CONTROL => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_HINT => "UNUSED"
)
port map (
address => ext_rom_addr_s(10 downto 0),
inclock => xtal_s,
outclock => zero_s, -- unused
memenab => one_s,
q => ext_rom_data_s
);
-----------------------------------------------------------------------------
-- Internal RAM, 256 bytes
-----------------------------------------------------------------------------
ram_256 : generic_ram_ena
generic map (
addr_width_g => 8,
data_width_g => 8
)
port map (
clk_i => xtal_s,
a_i => ram_addr_s,
we_i => ram_we_s,
ena_i => one_s,
d_i => ram_data_to_s,
d_o => ram_data_from_s
);
-----------------------------------------------------------------------------
-- External RAM, 256 bytes
-----------------------------------------------------------------------------
ext_ram_b : generic_ram_ena
generic map (
addr_width_g => 8,
data_width_g => 8
)
port map (
clk_i => xtal_s,
a_i => ext_mem_addr_q,
we_i => ext_ram_we_q,
ena_i => one_s,
d_i => bus_s,
d_o => ext_ram_data_from_s
);
t48_core_b : t48_core
generic map (
xtal_div_3_g => 1,
register_mnemonic_g => 1,
include_port1_g => 1,
include_port2_g => 1,
include_bus_g => 1,
include_timer_g => 1,
sample_t1_state_g => 4
)
port map (
xtal_i => xtal_s,
xtal_en_i => one_s,
reset_i => res_n_s,
t0_i => p1_s(0),
t0_o => open,
t0_dir_o => open,
int_n_i => int_n_s,
ea_i => rom_addr_s(11),
rd_n_o => rd_n_s,
psen_n_o => psen_n_s,
wr_n_o => wr_n_s,
ale_o => ale_s,
db_i => bus_s,
db_o => t48_bus_s,
db_dir_o => bus_dir_s,
t1_i => p1_s(1),
p2_i => p2_s,
p2_o => t48_p2_s,
p2l_low_imp_o => p2l_low_imp_s,
p2h_low_imp_o => p2h_low_imp_s,
p1_i => p1_s,
p1_o => t48_p1_s,
p1_low_imp_o => p1_low_imp_s,
prog_n_o => prog_n_s,
clk_i => xtal_s,
en_clk_i => xtal3_s,
xtal3_o => xtal3_s,
dmem_addr_o => ram_addr_s,
dmem_we_o => ram_we_s,
dmem_data_i => ram_data_from_s,
dmem_data_o => ram_data_to_s,
pmem_addr_o => rom_addr_s,
pmem_data_i => rom_data_s
);
if_timing_b : if_timing
port map (
xtal_i => xtal_s,
ale_i => ale_s,
psen_n_i => psen_n_s,
rd_n_i => rd_n_s,
wr_n_i => wr_n_s,
prog_n_i => prog_n_s,
db_bus_i => bus_s,
p2_i => t48_p2_s
);
-----------------------------------------------------------------------------
-- Port logic
--
ports: process (t48_p1_s,
p1_low_imp_s,
t48_p2_s,
p2l_low_imp_s,
p2h_low_imp_s)
function t48_port_f(t48_p : std_logic_vector;
low_imp : std_logic) return std_logic_vector is
variable p_v : std_logic_vector(t48_p'range);
begin
if low_imp = '1' then
p_v := t48_p;
else
for i in p_v'range loop
if t48_p(i) = '1' then
p_v(i) := 'H';
else
p_v(i) := t48_p(i);
end if;
end loop;
end if;
return p_v;
end;
begin
p1_s <= t48_port_f(t48_p => t48_p1_s,
low_imp => p1_low_imp_s);
p2_s(3 downto 0) <= t48_port_f(t48_p => t48_p2_s(3 downto 0),
low_imp => p2l_low_imp_s);
p2_s(7 downto 4) <= t48_port_f(t48_p => t48_p2_s(7 downto 4),
low_imp => p2h_low_imp_s);
end process ports;
--
-----------------------------------------------------------------------------
bus_s <= t48_bus_s
when bus_dir_s = '1' else
(others => 'Z');
bus_s <= ext_ram_data_from_s
when rd_n_s = '0' and ena_ext_ram_q else
(others => 'Z');
bus_s <= ext_rom_data_s
when psen_n_s = '0' else
(others => 'Z');
-----------------------------------------------------------------------------
-- External memory access signals
--
ext_mem: process (wr_n_s,
ext_mem_addr_q,
ena_ext_ram_q,
ale_s,
bus_s,
xtal_s)
begin
if ale_s'event and ale_s = '0' then
if not is_X(bus_s) then
ext_mem_addr_q <= bus_s;
else
ext_mem_addr_q <= (others => '0');
end if;
end if;
if wr_n_s'event and wr_n_s = '1' then
-- write enable for external RAM
if ena_ext_ram_q then
ext_ram_we_q <= '1';
end if;
-- process external memory selector
if ext_mem_addr_q = "11111111" then
ext_mem_sel_we_q <= true;
end if;
end if;
if xtal_s'event and xtal_s = '1' then
ext_ram_we_q <= '0';
ext_mem_sel_we_q <= false;
end if;
end process ext_mem;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process ext_mem_sel
--
-- Purpose:
-- Select external memory address space.
-- This is either
-- + external RAM
-- + testbench peripherals
--
ext_mem_sel: process (res_n_s, xtal_s)
begin
if res_n_s = '0' then
ena_ext_ram_q <= true;
ena_tb_periph_q <= false;
elsif xtal_s'event and xtal_s = '1' then
if ext_mem_sel_we_q then
if bus_s(0) = '1' then
ena_ext_ram_q <= true;
else
ena_ext_ram_q <= false;
end if;
if bus_s(1) = '1' then
ena_tb_periph_q <= true;
else
ena_tb_periph_q <= false;
end if;
end if;
end if;
end process ext_mem_sel;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process tb_periph
--
-- Purpose:
-- Implements the testbenc peripherals driving P1 and P2.
--
tb_periph: process (res_n_s, wr_n_s)
function oc_f (pX : std_logic_vector) return std_logic_vector is
variable r_v : std_logic_vector(pX'range);
begin
for i in pX'range loop
if pX(i) = '0' then
r_v(i) := '0';
else
r_v(i) := 'H';
end if;
end loop;
return r_v;
end;
begin
if res_n_s = '0' then
tb_p1_q <= (others => 'H');
tb_p2_q <= (others => 'H');
elsif wr_n_s'event and wr_n_s = '1' then
if ena_tb_periph_q then
case ext_mem_addr_q is
-- P1
when "00000000" =>
tb_p1_q <= oc_f(t48_bus_s);
-- P2
when "00000001" =>
tb_p2_q <= oc_f(t48_bus_s);
when others =>
null;
end case;
end if;
end if;
end process tb_periph;
--
-----------------------------------------------------------------------------
p1_s <= tb_p1_q;
p2_s <= tb_p2_q;
xtal_n_s <= not xtal_s;
-----------------------------------------------------------------------------
-- The clock generator
--
clk_gen: process
begin
xtal_s <= '0';
wait for period_c/2;
xtal_s <= '1';
wait for period_c/2;
end process clk_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The reset generator
--
res_gen: process
begin
res_n_s <= '0';
wait for 5 * period_c;
res_n_s <= '1';
wait;
end process res_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The interrupt generator
--
int_gen: process
begin
int_n_s <= '1';
wait for 750 * period_c;
int_n_s <= '0';
wait for 45 * period_c;
end process int_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- End of simulation detection
--
eos: process
begin
outer: loop
wait on tb_accu_s;
if tb_accu_s = "10101010" then
wait on tb_accu_s;
if tb_accu_s = "01010101" then
wait on tb_accu_s;
if tb_accu_s = "00000001" then
-- wait for instruction strobe of this move
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
-- wait for next strobe
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
assert false
report "Simulation Result: PASS."
severity note;
else
assert false
report "Simulation Result: FAIL."
severity note;
end if;
assert false
report "End of simulation reached."
severity failure;
end if;
end if;
end loop;
end process eos;
--
-----------------------------------------------------------------------------
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.13 2006/06/20 00:45:26 arniml
-- new input xtal_en_i
--
-- Revision 1.12 2005/11/01 21:21:48 arniml
-- split low impedance markers for P2
--
-- Revision 1.11 2005/09/07 17:39:40 arniml
-- fix missing assignment to outclock
--
-- Revision 1.10 2004/05/21 11:24:47 arniml
-- split 4k internal ROM into
-- + 2k internal ROM
-- + 2k external ROM
-- EA of t48_core is driven by MSB of internal ROM address
-- if upper 2k block is selected, the system switches to EA mode on the fly
--
-- Revision 1.9 2004/05/17 14:43:33 arniml
-- add testbench peripherals for P1 and P2
-- this became necessary to observe a difference between externally applied
-- port data and internally applied port data
--
-- Revision 1.8 2004/04/25 20:41:48 arniml
-- connect if_timing to P2 output of T48
--
-- Revision 1.7 2004/04/25 16:23:21 arniml
-- added if_timing
--
-- Revision 1.6 2004/04/14 20:57:44 arniml
-- wait for instruction strobe after final end-of-simulation detection
-- this ensures that the last mov instruction is part of the dump and
-- enables 100% matching with i8039 simulator
--
-- Revision 1.5 2004/03/29 19:45:15 arniml
-- rename pX_limp to pX_low_imp
--
-- Revision 1.4 2004/03/28 21:30:25 arniml
-- connect prog_n_o
--
-- Revision 1.3 2004/03/26 22:39:28 arniml
-- enhance simulation result string
--
-- Revision 1.2 2004/03/24 23:22:35 arniml
-- put ext_ram on falling clock edge to sample the write enable properly
--
-- Revision 1.1 2004/03/24 21:42:10 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
gpl-2.0
|
274581a590758fdc09d35e926abde5fe
| 0.467458 | 3.558493 | false | false | false | false |
piliguori/Linear-Regression
|
Src/LinearRegression.vhd
| 1 | 23,012 |
--! @file LinearRegression.vhd
--!
--! @authors Salvatore Barone <[email protected]> <br>
--! Alfonso Di Martino <[email protected]> <br>
--! Sossio Fiorillo <[email protected]> <br>
--! Pietro Liguori <[email protected]> <br>
--!
--! @date 03 07 2017
--!
--! @copyright
--! Copyright 2017 Salvatore Barone <[email protected]> <br>
--! Alfonso Di Martino <[email protected]> <br>
--! Sossio Fiorillo <[email protected]> <br>
--! Pietro Liguori <[email protected]> <br>
--!
--! This file is part of Linear-Regression.
--!
--! Linear-Regression is free software; you can redistribute it and/or modify it under the terms of
--! the GNU General Public License as published by the Free Software Foundation; either version 3 of
--! the License, or any later version.
--!
--! Linear-Regression is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
--! without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--! GNU General Public License for more details.
--!
--! You should have received a copy of the GNU General Public License along with this program; if not,
--! write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
--! USA.
--!
--! @addtogroup LinearRegression
--! @{
--! @brief Regressione Lineare in VHDL.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! @mainpage
--! @brief Regressione Lineare.
--! @details
--! Il componente permette di effettuare la regressione lineare.
--!
--! Prende 6 segnali dati in ingresso e, attraverso l'utilizzo di moltiplicatori e sottrattori, oltre
--! all'opportuno troncamento dei valori intermedi calcolati, restituisce i parametri di uscita m ed q, rispettivamente coefficiente
--! angolare e intercetta della retta di regressione. La rappresentazione dei segnali è in signed fixed point. Lo schema a blocchi
--! dell'interfaccia del componente è riportata di seguito.
--! @htmlonly
--! <div align='center'>
--! <img src="../schemes/LinearRegressionBlackBox.png"/>
--! </div>
--! @endhtmlonly
--! <h3>Ingressi</h3>
--! - clock: segnale di clock, fornisce il segnale di temporizzazione ai componenti interni
--! - load: segnale di load, agisce solo sui registri di bufferizzazione dei segnali dati in ingresso; si veda la documentazione dell'architettura implementativa
--! - reset_n: segnale di reset asincrono (active-low) per i registri interni
--! - prim: costante in input, 6 bit di parte intera e 0 decimale (m.n = 5.0)
--! - A: 6 bit di parte intera e 18 decimale (m.n = 5.18)
--! - B: msb di peso -1 (m.n = -1.24)
--! - C: msb di peso -7 (m.n = -7.30)
--! - Sum1: 9 bit di parte intera e 15 decimale (m.n = 8.15)
--! - Sum2: 3 bit di parte intera e 21 decimale (m.n = 2.21)
--!
--! <h3>Uscite</h3>
--! - m: coefficiente angolare della retta di regressione, 11 bit di parte intera e 13 decimale (m.n = 10.13)
--! - q: intercetta della retta di regressione, 3 bit di parte intera e 21 decimale (m.n = 2.21)
--!
--! <h3>Rappresentazione dei segnali</h3>
--! La rappresentazione dei segnali A, B, C e prim è calzante con i valori costanti degli stessi, forniti per effettuare il test
--! del componente.
--! <table>
--! <tr><th>Segnale</th><th>Valore</th><th>Rappresentazione</th></tr>
--! <tr><td>A</td><td>30.769230769230795</td><td>Q<sub>5,18</sub></td></tr>
--! <tr><td>B</td><td>0.3</td><td>Q<sub>-1,24</sub></td></tr>
--! <tr><td>C</td><td>0.0049</td><td>Q<sub>-7,30</sub></td></tr>
--! <tr><td>prim</td><td>25</td><td>Q<sub>5,0</sub></td></tr>
--! </table>
--! La rappresentazione ottimale per i segnali Sum1 e Sum2 è stata scelta in base a valori trovati empiricamente con 10M test
--! preliminari.
--! <table>
--! <tr><th>Segnale</th><th>Valore</th><th>Rappresentazione</th></tr>
--! <tr><td>Sum1</td><td>[-3; 189]</td><td>Q<sub>5,18</sub></td></tr>
--! <tr><td>Sum2</td><td>[-0.09; 3]</td><td>Q<sub>2,21</sub></td></tr>
--! </table>
--! Come per i segnali precedenti, la rappresentazione per m e per q è stata scelta in base a valori trovati empiricamente
--! con 10M test preliminari.
--! <table>
--! <tr><th>Segnale</th><th>Valore</th><th>Rappresentazione</th></tr>
--! <tr><td>m</td><td>[-27; 606]</td><td>Q<sub>10,13</sub></td></tr>
--! <tr><td>q</td><td>[-2.62; 2.59]</td><td>Q<sub>2,21</sub></td></tr>
--! </table>
entity LinearRegression is
Port ( clk : in std_logic; --! segnale di clock, fornisce il segnale di temporizzazione ai componenti interni
load : in std_logic; --! segnale di load, agisce solo sui registri di bufferizzazione dei segnali dati in ingresso; si veda la documentazione dell'architettura implementativa
reset_n : in std_logic; --! segnale di reset asincrono (active-low) per i registri interni
prim : in STD_LOGIC_VECTOR (5 downto 0); --! costante in input, 6 bit di parte intera e 0 decimale (m.n = 5.0)
Sum2 : in STD_LOGIC_VECTOR (23 downto 0); --! segnale in input, 3 bit di parte intera e 21 decimale (m.n = 2.21)
B : in STD_LOGIC_VECTOR (23 downto 0); --! segnale in input, msb di peso -1 (m.n = -1.24)
Sum1 : in STD_LOGIC_VECTOR (23 downto 0); --! segnale in input, 9 bit di parte intera e 15 decimale (m.n = 8.15)
C : in STD_LOGIC_VECTOR (23 downto 0); --! segnale in input, msb di peso -7 (m.n = -7.30)
A : in STD_LOGIC_VECTOR (23 downto 0); --! segnale in input, 6 bit di parte intera e 18 decimale (m.n = 5.18)
m : out STD_LOGIC_VECTOR (23 downto 0); --! coefficiente angolare della retta di regressione, 11 bit di parte intera e 13 decimale (m.n = 10.13)
q : out STD_LOGIC_VECTOR (23 downto 0)); --! intercetta della retta di regressione, 3 bit di parte intera e 21 decimale (m.n = 2.21)
end LinearRegression;
--! Per il calcolo dei parametri della regressione vengono utilizzati opportunamente dei moltiplicatori
--! e addizionatori/sottrattori. Per effettuare i calcoli in fixed point vengono adoperati opportuni troncamenti/
--! espansioni dei segnali.
--! Il componente ha un'architettura pipelined, così come mostrato nello schema di seguito, nel quale sono indicati,
--! usando la notazione standard, le rappresentazioni binarie dei segnali dato in signed fixed-point. Si noti che
--! il segnale "load" agisce solo sul primo dei registri della pipe.
--! @htmlonly
--! <div align='center'>
--! <img src="../schemes/LinearRegression.png"/>
--! </div>
--! @endhtmlonly
--!
--! <h3>Rappresentazione dei segnali intermedi</h3>
--! La rappresentazione ottimale per i segnali intermedi è stata scelta in base a valori trovati empiricamente con 10M test
--! preliminari, in modo da minimizzare il numero di bit usati per la loro rappresentazione ed, al contempo, minimizzare l'
--! errore commesso nella loro rappresentazione.
--! <table>
--! <tr>
--! <th>Componente</th>
--! <th>Ingressi</th>
--! <th>Uscita</th>
--! <th>Intervallo</th>
--! <th>Rappresentazione<br>Ottimale</th>
--! </tr>
--! <tr>
--! <td>MULT1</td>
--! <td>B (Q<sub>-1.24</sub>)<br>Sum1 (Q<sub>8.15</sub>)</td>
--! <td>mult1_out (Q<sub>8.39</sub>)</td>
--! <td>[-0.3; 56]</td>
--! <td>P1 (Q<sub>7.16</sub>)*</td>
--! </tr>
--! <tr>
--! <td>MULT2</td>
--! <td>Sum2 (Q<sub>2.21</sub>)<br>B (Q<sub>-1.24</sub>)</td>
--! <td>mult2_out (Q<sub>2.45</sub>)</td>
--! <td>[-0.02; 0.9090]</td>
--! <td>P2 (Q<sub>0.23</sub>)</td>
--! </tr>
--! <tr>
--! <td>MULT3</td>
--! <td>Sum2 (Q<sub>2.21</sub>)<br>Prim (Q<sub>5.0</sub>)</td>
--! <td>mult3_out (Q<sub>8.21</sub>)</td>
--! <td>[-2.37; 80]</td>
--! <td>P3 (Q<sub>7.16</sub>)</td>
--! </tr>
--! <tr>
--! <td>MULT4</td>
--! <td>Sum1 (Q<sub>8.15</sub>)<br>C(Q<sub>-7.30</sub>)</td>
--! <td>mult4_out (Q<sub>2.45</sub>)</td>
--! <td>[-0.0049; 0.95]</td>
--! <td>P4 (Q<sub>0.23</sub>)</td>
--! </tr>
--! <tr>
--! <td>SUB5</td>
--! <td>P3(Q<sub>7.16</sub>)<br>P1(Q<sub>7.16</sub>)</td>
--! <td>S5 (Q<sub>7.16</sub>)</td>
--! <td>[-0.13; 19.21]</td>
--! <td>Q<sub>7.16</sub></td>
--! </tr>
--! <tr>
--! <td>SUB6</td>
--! <td>P4(Q<sub>0.23</sub>)<br>P2(Q<sub>0.23</sub>)</td>
--! <td>S6 (Q<sub>0.23</sub>)</td>
--! <td>[-0.08; 0.08]</td>
--! <td>Q<sub>0.23</sub></td>
--! </tr>
--! <tr>
--! <td>MULTM</td>
--! <td>A(Q<sub>5.18</sub>)<br>S5(Q<sub>7.16</sub>)</td>
--! <td>multM_out (Q<sub>13.34</sub>)</td>
--! <td>[-27; 606]</td>
--! <td>m (Q<sub>10.13</sub>)</td>
--! </tr>
--! <tr>
--! <td>MULTQ</td>
--! <td>A(Q<sub>5.18</sub>)<br>S6(Q<sub>0.23</sub>)</td>
--! <td>multQ_out (Q<sub>6.41</sub>)</td>
--! <td>[-2.62; 2.59]</td>
--! <td>q (Q<sub>2.21</sub>)</td>
--! </tr>
--! </table>
--! *N.B. La rappresentazione ottimale sarebbe Q<sub>6.17</sub>, ma il segnale va sommato con P3, la cui rappresentazione
--! è Q<sub>7.16</sub>, per cui si è adottata quest'ultima.
architecture Structural of LinearRegression is
component GenericBuffer is
Generic ( width : natural := 8;
edge : std_logic := '1');
Port ( clock : in std_logic;
reset_n : in std_logic;
load : in std_logic;
data_in : in std_logic_vector(width-1 downto 0);
data_out : out std_logic_vector(width-1 downto 0));
end component;
component multiplier is
Generic ( nbits1 : natural := 8;
nbits2 : natural := 8);
Port ( factor1 : in STD_LOGIC_VECTOR (nbits1-1 downto 0);
factor2 : in STD_LOGIC_VECTOR (nbits2-1 downto 0);
prod : out STD_LOGIC_VECTOR (nbits1+nbits2-1 downto 0));
end component;
component subtractor is
generic ( nbits : natural := 32);
port ( sub1 : in std_logic_vector(nbits-1 downto 0);
sub2 : in std_logic_vector(nbits-1 downto 0);
diff : out std_logic_vector(nbits-1 downto 0));
end component;
----------------------------------------------------------------------------------------------------------------------------
-- Segnali di uscita del pipe-stage 0, si faccia riferimento allo schema architetturale
signal prim_buff0 : std_logic_vector (5 downto 0) := (others => '0'); --! segnale prim bufferizzato, uscita del pipe-stage 0
signal sum2_buff0 : std_logic_vector (23 downto 0) := (others => '0'); --! segnale sum2 bufferizzato, uscita del pipe-stage 0
signal b_buff0 : std_logic_vector (23 downto 0) := (others => '0'); --! segnale b bufferizzato, uscita del pipe-stage 0
signal sum1_buff0 : std_logic_vector (23 downto 0) := (others => '0'); --! segnale sum1 bufferizzato, uscita del pipe-stage 0
signal c_buff0 : std_logic_vector (23 downto 0) := (others => '0'); --! segnale c bufferizzato, uscita del pipe-stage 0
signal a_buff0 : std_logic_vector (23 downto 0) := (others => '0'); --! segnale a bufferizzato, uscita del pipe-stage 0
-----------------------------------------------------------------------------------------------------------------------------
-- Segnali di uscita di MULT1, MULT2, MULT3 e MULT4
--! Uscita di MULT1 espressa su 48 bit, di cui 9 per la parte intera e 39 per quella decimale (m.n = 8.39).
signal mult1_out : std_logic_vector (47 downto 0) := (others => '0');
--! Uscita di MULT2 espressa su 48 bit, di cui 3 per la parte intera e 45 per quella decimale (m.n = 2.45).
signal mult2_out : std_logic_vector (47 downto 0) := (others => '0');
--! Uscita di MULT3 espressa su 30 bit, di cui 9 per la parte intera e 21 per quella decimale (m.n = 8.21).
signal mult3_out : std_logic_vector (29 downto 0) := (others => '0');
--! Uscita di MULT4 espressa su 48 bit, di cui 3 per la parte intera e 45 per quella decimale (m.n = 2.45).
signal mult4_out : std_logic_vector (47 downto 0) := (others => '0');
----------------------------------------------------------------------------------------------------------------------------
-- Segnali di uscita del pipe-stage 1, si faccia riferimento allo schema architetturale
--! L'uscita di MULT1 deve essere espressa su 24 bit, di cui 8 bit per la parte intera e 16 per quella decimale ( m.n = 7.16 ).
signal P1_buff1 : std_logic_vector (23 downto 0) := (others => '0');
--!L'uscita di MULT2 deve essere espressa su 24 bit, di cui 1 per la parte intera e 23 per quella decimale (m.n = 0.23).
signal P2_buff1 : std_logic_vector (23 downto 0) := (others => '0');
--! L'uscita di MULT3 deve essere espressa su 24 bit di cui 8 sono per la parte intera, e 16 per quella decimale (m.n = 7.16).
signal P3_buff1 : std_logic_vector (23 downto 0) := (others => '0');
--! L'uscita di MULT4 deve essere espressa su 24 bit, di cui 1 per la parte intera e 23 per quella decimale ( m.n = 0.23 ).
signal P4_buff1 : std_logic_vector (23 downto 0) := (others => '0');
--! segnale A bufferizzato, uscita del pipe-stage 1
signal A_buff1 : std_logic_vector (23 downto 0) := (others => '0');
-----------------------------------------------------------------------------------------------------------------------------
-- Segnali di uscita di SUB5 e SUB6
--! L'uscita di SUB5 deve essere espressa su 24 bit, di cui 8 per la parte intera e 16 per quella decimale ( m.n = 7.16 ).
signal S5 : std_logic_vector (23 downto 0) := (others => '0');
--! L'uscita di SUB6 deve essere espressa su 24 bit, di cui 1 per la parte intera e 23 per quella decimale ( m.n = 0.23 ).
signal S6 : std_logic_vector (23 downto 0) := (others => '0');
----------------------------------------------------------------------------------------------------------------------------
-- Segnali di uscita del pipe-stage 2, si faccia riferimento allo schema architetturale
signal S5_buff2 : std_logic_vector (23 downto 0) := (others => '0');
signal S6_buff2 : std_logic_vector (23 downto 0) := (others => '0');
--! segnale A bufferizzato, uscita del pipe-stage 2
signal A_buff2 : std_logic_vector (23 downto 0) := (others => '0');
-----------------------------------------------------------------------------------------------------------------------------
-- Segnali di uscita di MULTM e MULTQ
--! Uscita di MULTM espressa su 48 bit, di cui 14 per la parte intera e 34 per quella decimale (m.n = 13.34).
signal multM_out : std_logic_vector (47 downto 0) := (others => '0');
--! Uscita di MULTQ espressa su 48 bit, di cui 7 per la parte intera e 41 per quella decimale (m.n = 6.41).
signal multQ_out : std_logic_vector (47 downto 0) := (others => '0');
begin
----------------------------------------------------------------------------------------------------------------------------------
-- Istanze pipe-stage 0
----------------------------------------------------------------------------------------------------------------------------------
--! buffer di pipe-stage 0 per l'ingresso prim, 6 bit
pipestage0_buff_prim : GenericBuffer
Generic map ( width => 6,
edge => '1')
Port map ( clock => clk,
reset_n => reset_n,
load => load,
data_in => prim,
data_out => prim_buff0);
--! buffer di pipe-stage 0 per l'ingresso A, 24 bit
pipestage0_buff_A : GenericBuffer
Generic map ( width => 24,
edge => '1')
Port map ( clock => clk,
reset_n => reset_n,
load => load,
data_in => A,
data_out => A_buff0);
--! buffer di pipe-stage 0 per l'ingresso B, 24 bit
pipestage0_buff_B : GenericBuffer
Generic map ( width => 24,
edge => '1')
Port map ( clock => clk,
reset_n => reset_n,
load => load,
data_in => B,
data_out => B_buff0);
--! buffer di pipe-stage 0 per l'ingresso C, 24 bit
pipestage0_buff_C : GenericBuffer
Generic map ( width => 24,
edge => '1')
Port map ( clock => clk,
reset_n => reset_n,
load => load,
data_in => C,
data_out => C_buff0);
--! buffer di pipe-stage 0 per l'ingresso Sum1, 24 bit
pipestage0_buff_Sum1 : GenericBuffer
Generic map ( width => 24,
edge => '1')
Port map ( clock => clk,
reset_n => reset_n,
load => load,
data_in => Sum1,
data_out => Sum1_buff0);
--! buffer di pipe-stage 0 per l'ingresso Sum2, 24 bit
pipestage0_buff_Sum2 : GenericBuffer
Generic map ( width => 24,
edge => '1')
Port map ( clock => clk,
reset_n => reset_n,
load => load,
data_in => Sum2,
data_out => Sum2_buff0);
----------------------------------------------------------------------------------------------------------------------------------
-- Instanze MULT1, MULT2, MULT3 e MULT4
----------------------------------------------------------------------------------------------------------------------------------
MULT3: multiplier
Generic map( nbits1 => 6,
nbits2 => 24)
port map ( factor1 => prim_buff0,
factor2 => Sum2_buff0,
prod => mult3_out);
MULT2: multiplier
Generic map( nbits1 => 24,
nbits2 => 24)
port map ( factor1 => Sum2_buff0,
factor2 => B_buff0,
prod => mult2_out);
MULT1: multiplier
Generic map( nbits1 => 24,
nbits2 => 24)
port map ( factor1 => B_buff0,
factor2 => Sum1_buff0,
prod => mult1_out);
MULT4: multiplier
Generic map( nbits1 => 24,
nbits2 => 24)
port map ( factor1 => Sum1_buff0,
factor2 => C_buff0,
prod => mult4_out);
----------------------------------------------------------------------------------------------------------------------------------
-- Istanze pipe-stage 1
----------------------------------------------------------------------------------------------------------------------------------
--! buffer di pipe-stage 1 per l'ingresso A, 24 bit<br>
pipestage1_buff_A : GenericBuffer
Generic map ( width => 24,
edge => '1')
Port map ( clock => clk,
reset_n => reset_n,
load => '1',
data_in => A_buff0,
data_out => A_buff1);
--! buffer di pipe-stage 1 per il segnale P1, 24 bit<br>
--! Viene effettuato anche il cambio di rappresentazione dell'uscita di MULT1 da 48 bit, di cui 9 per la parte intera
--! (m.n = 8.39) a 24 bit, di cui 8 per la parte intera (m.n = 7.16). Viene troncato 1 bit in testa e 23 in coda.
pipestage1_buff_P1 : GenericBuffer
Generic map ( width => 24,
edge => '1')
Port map ( clock => clk,
reset_n => reset_n,
load => '1',
data_in => mult1_out(46 downto 23),
data_out => P1_buff1);
--! buffer di pipe-stage 1 per il segnale P2, 24 bit<br>
--! Viene effettuato il cambio di rappresentazione dell'uscita di MULT2 da 48 bit, di cui 3 per la parte intera
--! (m.n = 2.45) a 24 bit, di cui 1 per la parte intera (m.n = 0.23). Quindi tronchiamo 2 bit in testa e 22 in coda.
pipestage1_buff_P2 : GenericBuffer
Generic map ( width => 24,
edge => '1')
Port map ( clock => clk,
reset_n => reset_n,
load => '1',
data_in => mult2_out(45 downto 22),
data_out => P2_buff1);
--! buffer di pipe-stage 1 per il segnale P3, 24 bit<br>
--! Viene effettuato il cambio di rappresentazione dell'uscita di MULT3 da 30 bit, di cui 9 per la parte intera
--! (m.n = 8.21) a 24 bit, di cui 8 per la parte intera (m.n = 7.16). Quindi tronchiamo 1 bit in testa e 5 in coda.
pipestage1_buff_P3 : GenericBuffer
Generic map ( width => 24,
edge => '1')
Port map ( clock => clk,
reset_n => reset_n,
load => '1',
data_in => mult3_out(28 downto 5),
data_out => P3_buff1);
--! buffer di pipe-stage 1 per il segnale P4, 24 bit<br>
--! Viene effettuato il cambio di rappresentazione dell'uscita di MULT4 da 48 bit, di cui 3 per la parte intera
--! (m.n = 2.45) a 24 bit, di cui 1 per la parte intera (m.n = 0.23). Quindi tronchiamo 2 bit in testa e 22 in coda.
pipestage1_buff_P4 : GenericBuffer
Generic map ( width => 24,
edge => '1')
Port map ( clock => clk,
reset_n => reset_n,
load => '1',
data_in => mult4_out(45 downto 22),
data_out => P4_buff1);
----------------------------------------------------------------------------------------------------------------------------------
-- Instanze SUB5 e SUB6
----------------------------------------------------------------------------------------------------------------------------------
SUB5: subtractor
Generic map (nbits => 24)
port map( sub1 => P3_buff1,
sub2 => P1_buff1,
diff => S5);
SUB6: subtractor
Generic map (nbits => 24)
port map( sub1 => P4_buff1,
sub2 => P2_buff1,
diff => S6);
----------------------------------------------------------------------------------------------------------------------------------
-- Istanze pipe-stage 2
----------------------------------------------------------------------------------------------------------------------------------
--! buffer di pipe-stage 2 per il segnale A, 24 bit
pipestage2_buff_A : GenericBuffer
Generic map ( width => 24,
edge => '1')
Port map ( clock => clk,
reset_n => reset_n,
load => load,
data_in => A_buff1,
data_out => A_buff2);
--! buffer di pipe-stage 2 per il segnale S5, 24 bit
pipestage2_buff_S5 : GenericBuffer
Generic map ( width => 24,
edge => '1')
Port map ( clock => clk,
reset_n => reset_n,
load => '1',
data_in => S5,
data_out => S5_buff2);
--! buffer di pipe-stage 2 per il segnale S6, 24 bit
pipestage2_buff_S6 : GenericBuffer
Generic map ( width => 24,
edge => '1')
Port map ( clock => clk,
reset_n => reset_n,
load => '1',
data_in => S6,
data_out => S6_buff2);
----------------------------------------------------------------------------------------------------------------------------------
-- Instanze MULTM e MULTQ
----------------------------------------------------------------------------------------------------------------------------------
--! Istanziazione del moltiplicatore MULTM<br>
--! Prende in ingresso i segnali S5_buff2 e A_buff2. L'uscita è espressa su 48bit.
--! L'uscita di MULTM deve essere portata da una rappresentazione di 48 bit con 14 bit di parte intera e 34
--! decimale (m.n = 13.34), ad una di 24 bit con 11 bit di parte intera e 13 decimale (m.n = 10.13).
--! Quindi tronca 3 bit in testa e 21 in coda.
MULTM: multiplier
Generic map( nbits1 => 24,
nbits2 => 24)
port map ( factor1 => S5_buff2,
factor2 => A_buff2,
prod => multM_out);
m <= multM_out (44 downto 21);
--! Istanziazione del moltiplicatore MULTQ<br>
--! Prende in ingresso i segnali S6_buff2 e A_buff2. L'uscita è espressa su 48bit.
--! L'uscita di MULTQ deve essere portata da una rappresentazione di 48 bit con 7 bit di parte intera e 41 decimale.
--! (m.n = 6.41), ad una di 24 bit con 3 bit di parte intera e 21 decimale (m.n = 2.21). Qindi tronca 4 bit in testa
--! e 20 in coda.
MULTQ: multiplier
Generic map( nbits1 => 24,
nbits2 => 24)
port map ( factor1 => A_buff2,
factor2 => S6_buff2,
prod => multQ_out);
q <= multQ_out(43 downto 20);
end Structural;
--! @}
|
gpl-3.0
|
ee329d698fe47cabd8641e2f72d35dae
| 0.560237 | 3.052555 | false | false | false | false |
nkkav/color_maker-s3esk
|
clockdiv.vhd
| 1 | 740 |
library IEEE;
use IEEE.std_logic_1164.all;
entity clockdiv is
generic (
DIVPARAM : integer := 5_000_000
);
port (
clk_i : in std_logic;
rst : in std_logic;
clk_o : out std_logic
);
end clockdiv;
architecture rtl of clockdiv is
signal count : integer range 0 to DIVPARAM;
signal temp_q : std_logic;
begin
process (clk_i, rst)
begin
if (rst = '1') then
count <= 0;
temp_q <= '0';
elsif (rising_edge(clk_i)) then
if (count = DIVPARAM/2-1) then
count <= 0;
temp_q <= not (temp_q);
else
count <= count + 1;
end if;
end if;
end process;
clk_o <= temp_q;
end rtl;
|
bsd-3-clause
|
6101b8c3337fdfbd130ffb4247b7b999
| 0.505405 | 3.288889 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/db/alt_dspbuilder_decoder.vhd
| 2 | 2,462 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic := '0';
sclr : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNEQGKKPXW is
generic (
DECODE : string := "10";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(2-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNEQGKKPXW;
component alt_dspbuilder_decoder_GNM4LOIHXZ is
generic (
DECODE : string := "01";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(2-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNM4LOIHXZ;
begin
alt_dspbuilder_decoder_GNEQGKKPXW_0: if ((DECODE = "10") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNEQGKKPXW_0: alt_dspbuilder_decoder_GNEQGKKPXW
generic map(DECODE => "10", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNM4LOIHXZ_1: if ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNM4LOIHXZ_1: alt_dspbuilder_decoder_GNM4LOIHXZ
generic map(DECODE => "01", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "10") and (PIPELINE = 1) and (WIDTH = 2)) or ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
0cc2ed576f298ed19f0dc3d9794dc9a4
| 0.65394 | 3.120406 | false | false | false | false |
freecores/t48
|
rtl/vhdl/timer.vhd
| 1 | 8,640 |
-------------------------------------------------------------------------------
--
-- The Timer/Counter unit.
--
-- $Id: timer.vhd,v 1.7 2006-11-30 14:31:59 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
use work.t48_pack.mstate_t;
entity t48_timer is
generic (
-- state in which T1 is sampled (3 or 4)
sample_t1_state_g : integer := 4
);
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
t1_i : in std_logic;
clk_mstate_i : in mstate_t;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
read_timer_i : in boolean;
write_timer_i : in boolean;
-- Decoder Interface ------------------------------------------------------
start_t_i : in boolean;
start_cnt_i : in boolean;
stop_tcnt_i : in boolean;
overflow_o : out std_logic
);
end t48_timer;
library ieee;
use ieee.numeric_std.all;
use work.t48_pack.all;
architecture rtl of t48_timer is
-- the 8 bit counter core
signal counter_q : unsigned(word_t'range);
signal overflow_q : boolean;
-- increment signal for the counter core
type inc_type_t is (NONE, TIMER, COUNTER);
signal increment_s : boolean;
signal inc_sel_q : inc_type_t;
-- T1 edge detector
signal t1_q : std_logic;
signal t1_inc_s : boolean;
-- timer prescaler
signal prescaler_q : unsigned(4 downto 0);
signal pre_inc_s : boolean;
begin
-----------------------------------------------------------------------------
-- Verify the generics
-----------------------------------------------------------------------------
-- pragma translate_off
assert (sample_t1_state_g = 3) or (sample_t1_state_g = 4)
report "sample_t1_state_g must be either 3 or 4!"
severity failure;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Process t1_edge
--
-- Purpose:
-- Implements the edge detector for T1.
--
t1_edge: process (t1_i,
t1_q,
clk_mstate_i)
begin
t1_inc_s <= false;
-- sample in state according to generic
-- Old devices: sample at the beginning of state 3
-- New devices: sample in state 4
if (sample_t1_state_g = 3 and clk_mstate_i = MSTATE3) or
(sample_t1_state_g = 4 and clk_mstate_i = MSTATE4) then
-- detect falling edge
if t1_q = '1' and t1_i = '0' then
t1_inc_s <= true;
end if;
end if;
end process t1_edge;
--
-----------------------------------------------------------------------------
pre_inc_s <= clk_mstate_i = MSTATE4 and prescaler_q = 31;
-----------------------------------------------------------------------------
-- Process inc_sel
--
-- Purpose:
-- Select increment source (timer, counter or none).
--
inc_sel: process (inc_sel_q,
pre_inc_s,
t1_inc_s)
begin
-- default assignment
increment_s <= false;
case inc_sel_q is
when NONE =>
increment_s <= false;
when TIMER =>
increment_s <= pre_inc_s;
when COUNTER =>
increment_s <= t1_inc_s;
when others =>
null;
end case;
end process inc_sel;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process regs
--
-- Purpose:
-- Implements the counter, the prescaler and other registers.
--
regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
overflow_q <= false;
t1_q <= '0';
prescaler_q <= (others => '0');
inc_sel_q <= NONE;
counter_q <= (others => '0');
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
-- Counter Core and overflow ------------------------------------------
overflow_q <= false;
if write_timer_i then
counter_q <= unsigned(data_i);
elsif increment_s then
counter_q <= counter_q + 1;
if counter_q = 255 then
overflow_q <= true;
end if;
end if;
-- T1 edge detector ---------------------------------------------------
if (sample_t1_state_g = 3 and clk_mstate_i = MSTATE3) or
(sample_t1_state_g = 4 and clk_mstate_i = MSTATE4) then
t1_q <= t1_i;
end if;
-- Prescaler ----------------------------------------------------------
if start_t_i then
prescaler_q <= (others => '0');
elsif clk_mstate_i = MSTATE3 then
prescaler_q <= prescaler_q + 1;
end if;
-- Increment Selector -------------------------------------------------
if start_t_i then
inc_sel_q <= TIMER;
elsif start_cnt_i then
inc_sel_q <= COUNTER;
elsif stop_tcnt_i then
inc_sel_q <= NONE;
end if;
end if;
end if;
end process regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
data_o <= std_logic_vector(counter_q)
when read_timer_i else
(others => bus_idle_level_c);
overflow_o <= to_stdLogic(overflow_q);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.6 2005/06/11 10:08:43 arniml
-- introduce prefix 't48_' for all packages, entities and configurations
--
-- Revision 1.5 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.4 2004/07/04 13:06:45 arniml
-- counter_q is not cleared during reset
-- this would match all different descriptions of the Counter as
-- a) if the software assumes that the Counter is modified during reset, it
-- will initialize the Counter anyhow
-- b) the special case 'Counter not modified during reset' is covered
--
-- Revision 1.3 2004/05/16 15:32:57 arniml
-- fix edge detector bug for counter
--
-- Revision 1.2 2004/04/15 22:05:13 arniml
-- increment prescaler with MSTATE4
--
-- Revision 1.1 2004/03/23 21:31:53 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
gpl-2.0
|
f6090896c5fcddaf051876c6adc3e46b
| 0.512731 | 4.224939 | false | false | false | false |
piliguori/Linear-Regression
|
Src/testbench/automatic_tb.vhd
| 1 | 4,250 |
--! @file automatic_tb.vhd
--!
--! @authors Salvatore Barone <[email protected]> <br>
--! Alfonso Di Martino <[email protected]> <br>
--! Sossio Fiorillo <[email protected]> <br>
--! Pietro Liguori <[email protected]> <br>
--!
--! @date 05 07 2017
--!
--! @copyright
--! Copyright 2017 Salvatore Barone <[email protected]> <br>
--! Alfonso Di Martino <[email protected]> <br>
--! Sossio Fiorillo <[email protected]> <br>
--! Pietro Liguori <[email protected]> <br>
--!
--!
--! This file is part of Linear-Regression.
--!
--! Linear-Regression is free software; you can redistribute it and/or modify it under the terms of
--! the GNU General Public License as published by the Free Software Foundation; either version 3 of
--! the License, or any later version.
--!
--! Linear-Regression is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
--! without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--! GNU General Public License for more details.
--!
--! You should have received a copy of the GNU General Public License along with this program; if not,
--! write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
--! USA.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all; -- per le operazioni su file
entity automatic_tb is
end automatic_tb;
architecture behavioral of automatic_tb is
component LinearRegression
Port ( clk : in std_logic;
load : in std_logic;
reset_n : in std_logic;
prim : in STD_LOGIC_VECTOR (5 downto 0);
Sum2 : in STD_LOGIC_VECTOR (23 downto 0);
B : in STD_LOGIC_VECTOR (23 downto 0);
Sum1 : in STD_LOGIC_VECTOR (23 downto 0);
C : in STD_LOGIC_VECTOR (23 downto 0);
A : in STD_LOGIC_VECTOR (23 downto 0);
m : out STD_LOGIC_VECTOR (23 downto 0);
q : out STD_LOGIC_VECTOR (23 downto 0));
end component;
constant clock_period : time := 10ns;
signal clk : std_logic := '0';
signal load : std_logic := '0';
signal reset_n : std_logic := '0';
signal prim : std_logic_vector (5 downto 0) := b"011001";
signal a : std_logic_vector (23 downto 0) := x"7B13B1";
signal b : std_logic_vector (23 downto 0) := x"4CCCCC";
signal c : std_logic_vector (23 downto 0) := x"504816";
signal sum1 : std_logic_vector (23 downto 0) := (others=>'0');
signal sum2 : std_logic_vector (23 downto 0) := (others=>'0');
signal m : std_logic_vector (23 downto 0) := (others=>'0');
signal q : std_logic_vector (23 downto 0) := (others=>'0');
-- oggetti per lettura/scrittura su file
file dataset : text;
file results : text;
begin
clock_process : process
begin
clk <= not clk;
wait for clock_period / 2;
end process clock_process;
UUT : LinearRegression
port map( clk => clk,
load => load,
reset_n => reset_n,
prim => prim,
sum2 => sum2,
b => b,
sum1 => sum1,
c => c,
a => a,
m => m,
q => q);
stim_proc : process
variable rline : line;
variable wline : line;
variable r_sum1 : std_logic_vector (23 downto 0) := (others=>'0');
variable r_sum2 : std_logic_vector (23 downto 0) := (others=>'0');
variable r_m : std_logic_vector (23 downto 0) := (others=>'0');
variable r_q : std_logic_vector (23 downto 0) := (others=>'0');
variable w_dm : std_logic_vector (23 downto 0) := (others=>'0');
variable w_dq : std_logic_vector (23 downto 0) := (others=>'0');
variable space : character;
begin
wait for 10*clock_period;
reset_n <= '1';
load <= '1';
file_open(dataset, "/home/ssaa/dataset.txt", read_mode);
file_open(results, "/home/ssaa/outputPostSynth.txt", write_mode);
while not endfile(dataset) loop
readline(dataset, rline);
read(rline, r_sum1); read(rline, space);
read(rline, r_sum2);
sum1 <= r_sum1;
sum2 <= r_sum2;
wait for 4*clock_period;
write(wline, m, right, 24);
write(wline, ' ', right, 1);
write(wline, q, right, 24);
writeline(results, wline);
end loop;
file_close(dataset);
file_close(results);
wait;
end process;
end behavioral;
|
gpl-3.0
|
0b51906713f015f2a8022efb60d29ab4
| 0.646118 | 2.972028 | false | false | false | false |
michel-castan/LILASHOME
|
doc/index_166.vhd
| 1 | 913 |
--------------------------------------------
-- généré par LILASV4 --
--------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.Numeric_Std.all;
use IEEE.std_logic_unsigned.all;
entity tst_code_logic_LocalInternal is
port(
a : IN std_logic := '0';
b : IN std_logic := '0';
cin : IN std_logic := '0';
cout : OUT std_logic := '0';
s : OUT std_logic := '0');
end entity tst_code_logic_LocalInternal;
architecture a_tst_code_logic_LocalInternal of tst_code_logic_LocalInternal is
-- déclaration des variables modules
-- déclaration des signaux internes
signal p : std_logic := 'U';
-- déclaration des variables locales
begin
process (a, b, p, cin)
variable g : std_logic;
begin
g := (a and b);
p <= (a or b);
cout <= (g or (p and cin));
s <= (a xor b xor cin);
end process;
end architecture a_tst_code_logic_LocalInternal;
|
apache-2.0
|
4dae00dccee51da4fc22fa40975a3283
| 0.587652 | 3.160279 | false | false | false | false |
Bourgeoisie/ECE368-RISC16
|
368RISC/ipcore_dir/tmp/_cg/Instruct_Memory/simulation/bmg_stim_gen.vhd
| 2 | 12,278 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SDP Configuration
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB: OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL DO_READ_R : STD_LOGIC := '0';
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
SIGNAL PORTA_WR : STD_LOGIC:='0';
SIGNAL COUNT : INTEGER :=0;
SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD : STD_LOGIC:='0';
SIGNAL COUNT_RD : INTEGER :=0;
SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((5 <= 5),WR_RD_DEEP_COUNT,
((16/16)*WR_RD_DEEP_COUNT));
CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((5 <= 5),WR_RD_DEEP_COUNT,
((16/16)*WR_RD_DEEP_COUNT));
BEGIN
ADDRA <= WRITE_ADDR(4 DOWNTO 0) ;
DINA <= DINA_INT ;
ADDRB <= READ_ADDR(4 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16 ,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
PORTA_WR_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR<='1';
ELSE
PORTA_WR<=PORTB_RD_COMPLETE;
END IF;
END IF;
END PROCESS;
PORTB_RD_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_RD<='0';
ELSE
PORTB_RD<=PORTA_WR_L2;
END IF;
END IF;
END PROCESS;
PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
ELSIF(PORTB_RD_COMPLETE='1') THEN
LATCH_PORTB_RD_COMPLETE <='1';
ELSIF(PORTA_WR_HAPPENED='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_L1 <='0';
PORTB_RD_L2 <='0';
ELSE
PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
PORTB_RD_L2 <= PORTB_RD_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_R1 <='0';
PORTA_WR_R2 <='0';
ELSE
PORTA_WR_R1 <= PORTA_WR;
PORTA_WR_R2 <= PORTA_WR_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_HAPPENED <= PORTA_WR_R2;
PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_COMPLETE<='0';
ELSIF(PORTA_WR_COMPLETE='1') THEN
LATCH_PORTA_WR_COMPLETE <='1';
--ELSIF(PORTB_RD_HAPPENED='1') THEN
ELSE
LATCH_PORTA_WR_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_L1 <='0';
PORTA_WR_L2 <='0';
ELSE
PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
PORTA_WR_L2 <= PORTA_WR_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_R1 <='0';
PORTB_RD_R2 <='0';
ELSE
PORTB_RD_R1 <= PORTB_RD;
PORTB_RD_R2 <= PORTB_RD_R1;
END IF;
END IF;
END PROCESS;
PORTB_RD_HAPPENED <= PORTB_RD_R2;
PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
start_rd_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
incr_rd_cnt <= '0';
elsif(portb_rd ='1') then
incr_rd_cnt <='1';
elsif(portb_rd_complete='1') then
incr_rd_cnt <='0';
end if;
end if;
end process;
RD_COUNTER: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
count_rd <= 0;
elsif(incr_rd_cnt='1') then
count_rd<=count_rd+1;
end if;
--if(count_rd=(wr_rd_deep_count)) then
if(count_rd=(RD_DEEP_COUNT)) then
count_rd<=0;
end if;
end if;
end process;
DO_READ<='1' when (count_rd <RD_DEEP_COUNT and incr_rd_cnt='1') else '0';
PORTA_WR_COMPLETE <= '1' when (count=WR_DEEP_COUNT) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
incr_wr_cnt <= '0';
elsif(porta_wr ='1') then
incr_wr_cnt <='1';
elsif(porta_wr_complete='1') then
incr_wr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
count <= 0;
elsif(incr_wr_cnt='1') then
count<=count+1;
end if;
if(count=(WR_DEEP_COUNT)) then
count<=0;
end if;
end if;
end process;
DO_WRITE<='1' when (count <WR_DEEP_COUNT and incr_wr_cnt='1') else '0';
BEGIN_SHIFT_REG: FOR I IN 0 TO 5 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLKB,
RST => TB_RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLKB,
RST =>TB_RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
REGCE_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_R <= '0';
ELSE
DO_READ_R <= DO_READ;
END IF;
END IF;
END PROCESS;
WEA(0) <= DO_WRITE ;
END ARCHITECTURE;
|
mit
|
bdd5bfa8cac877e45710601936de8974
| 0.542515 | 3.544457 | false | false | false | false |
cathalmccabe/PYNQ
|
boards/ip/audio_direct_1.1/src/pdm_des.vhd
| 8 | 3,943 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:24:14 01/31/2014
-- Design Name:
-- Module Name: pdm_des - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pdm_des is
generic(
C_NR_OF_BITS : integer := 16;
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_PDM_FREQ_MHZ : integer range 1 to 3 := 3
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
done_o : out std_logic;
data_o : out std_logic_vector(15 downto 0);
-- PDM
pdm_m_clk_o : out std_logic;
pdm_m_data_i : in std_logic;
pdm_lrsel_o : out std_logic
);
end pdm_des;
architecture Behavioral of pdm_des is
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal cnt_clk : integer range 0 to 127 := 0;
signal clk_int, clk_intt : std_logic := '0';
signal pdm_clk_rising, pdm_clk_falling : std_logic;
signal pdm_tmp : std_logic_vector((C_NR_OF_BITS-1) downto 0);
signal cnt_bits : integer range 0 to 31 := 0;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
-- with L/R Sel tied to GND => output = DATA1 (rising edge)
pdm_lrsel_o <= '0';
------------------------------------------------------------------------
-- Deserializer
------------------------------------------------------------------------
-- sample input serial data process
SHFT_IN: process(clk_i)
begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
pdm_tmp <= pdm_tmp(C_NR_OF_BITS-2 downto 0) & pdm_m_data_i;
end if;
end if;
end process SHFT_IN;
-- counter for the number of sampled bits
CNT: process(clk_i) begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-1) then
cnt_bits <= 0;
else
cnt_bits <= cnt_bits + 1;
end if;
end if;
end if;
end process CNT;
-- done gen
process(clk_i)
begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-1) then
done_o <= '1';
data_o <= pdm_tmp;
end if;
else
done_o <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------
-- slave clock generator
------------------------------------------------------------------------
CLK_CNT: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' or cnt_clk = ((C_SYS_CLK_FREQ_MHZ/(C_PDM_FREQ_MHZ*2))-1) then
cnt_clk <= 0;
clk_int <= not clk_int;
else
cnt_clk <= cnt_clk + 1;
end if;
clk_intt <= clk_int;
end if;
end process CLK_CNT;
pdm_m_clk_o <= clk_int;
pdm_clk_rising <= '1' when clk_int = '1' and clk_intt = '0' and en_i = '1' else '0';
--pdm_clk_falling <= '1' when cnt_clk = ((clk_div/2)-1) else '0';
end Behavioral;
|
bsd-3-clause
|
6e11a75b051fb432687be632ff8ebe8d
| 0.458788 | 3.850586 | false | false | false | false |
bobxiv/DispositivosLogicosProgramables-FICH
|
Practica/Contador binario vhdl/contadorbinario_synthesis.vhd
| 1 | 9,710 |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: H.42
-- \ \ Application: netgen
-- / / Filename: contadorbinario_synthesis.vhd
-- /___/ /\ Timestamp: Tue Sep 20 14:51:22 2011
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -ar Structure -w -ofmt vhdl -sim contadorbinario.ngc contadorbinario_synthesis.vhd
-- Device : xc3s200-5-ft256
-- Input file : contadorbinario.ngc
-- Output file : contadorbinario_synthesis.vhd
-- # of Entities : 1
-- Design Name : contadorbinario
-- Xilinx : C:/Xilinx
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Development System Reference Guide, Chapter 23
-- Synthesis and Verification Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity contadorbinario is
port (
reset : in STD_LOGIC := 'X';
count_direction : in STD_LOGIC := 'X';
clock : in STD_LOGIC := 'X';
clock_enable : in STD_LOGIC := 'X';
count : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end contadorbinario;
architecture Structure of contadorbinario is
signal reset_IBUF : STD_LOGIC;
signal count_direction_IBUF : STD_LOGIC;
signal clock_BUFGP : STD_LOGIC;
signal clock_enable_IBUF : STD_LOGIC;
signal Q_n0001 : STD_LOGIC;
signal count_temp_n0002 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N3 : STD_LOGIC;
signal contadorbinario_count_temp_n0000_0_cyo : STD_LOGIC;
signal N4 : STD_LOGIC;
signal contadorbinario_count_temp_n0000_1_cyo : STD_LOGIC;
signal N5 : STD_LOGIC;
signal contadorbinario_count_temp_n0000_2_cyo : STD_LOGIC;
signal N6 : STD_LOGIC;
signal contadorbinario_count_temp_n0000_3_cyo : STD_LOGIC;
signal N7 : STD_LOGIC;
signal contadorbinario_count_temp_n0000_4_cyo : STD_LOGIC;
signal N8 : STD_LOGIC;
signal contadorbinario_count_temp_n0000_5_cyo : STD_LOGIC;
signal N9 : STD_LOGIC;
signal contadorbinario_count_temp_n0000_6_cyo : STD_LOGIC;
signal count_temp : STD_LOGIC_VECTOR ( 7 downto 0 );
signal count_temp_n0000 : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
count_temp_6 : FDE
port map (
D => count_temp_n0000(6),
CE => Q_n0001,
C => clock_BUFGP,
Q => count_temp(6)
);
count_temp_n00021_INV_0 : INV
port map (
I => count_direction_IBUF,
O => count_temp_n0002
);
Q_n00011 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => clock_enable_IBUF,
I1 => reset_IBUF,
O => Q_n0001
);
count_temp_7 : FDE
port map (
D => count_temp_n0000(7),
CE => Q_n0001,
C => clock_BUFGP,
Q => count_temp(7)
);
contadorbinario_count_temp_n0000_7_xor : XORCY
port map (
CI => contadorbinario_count_temp_n0000_6_cyo,
LI => N10,
O => count_temp_n0000(7)
);
count_temp_0 : FDE
port map (
D => count_temp_n0000(0),
CE => Q_n0001,
C => clock_BUFGP,
Q => count_temp(0)
);
count_temp_1 : FDE
port map (
D => count_temp_n0000(1),
CE => Q_n0001,
C => clock_BUFGP,
Q => count_temp(1)
);
count_temp_2 : FDE
port map (
D => count_temp_n0000(2),
CE => Q_n0001,
C => clock_BUFGP,
Q => count_temp(2)
);
count_temp_3 : FDE
port map (
D => count_temp_n0000(3),
CE => Q_n0001,
C => clock_BUFGP,
Q => count_temp(3)
);
count_temp_4 : FDE
port map (
D => count_temp_n0000(4),
CE => Q_n0001,
C => clock_BUFGP,
Q => count_temp(4)
);
count_temp_5 : FDE
port map (
D => count_temp_n0000(5),
CE => Q_n0001,
C => clock_BUFGP,
Q => count_temp(5)
);
contadorbinario_count_temp_n0000_7_lut : LUT2_L
generic map(
INIT => X"9"
)
port map (
I0 => count_temp(7),
I1 => count_direction_IBUF,
LO => N10
);
count_1_OBUF : OBUF
port map (
I => count_temp(1),
O => count(1)
);
count_0_OBUF : OBUF
port map (
I => count_temp(0),
O => count(0)
);
contadorbinario_count_temp_n0000_0_cy : MUXCY
port map (
CI => count_temp_n0002,
DI => count_temp(0),
S => N3,
O => contadorbinario_count_temp_n0000_0_cyo
);
contadorbinario_count_temp_n0000_0_xor : XORCY
port map (
CI => count_temp_n0002,
LI => N3,
O => count_temp_n0000(0)
);
contadorbinario_count_temp_n0000_0_lut : LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => count_direction_IBUF,
I1 => count_temp(0),
LO => N3
);
contadorbinario_count_temp_n0000_1_cy : MUXCY
port map (
CI => contadorbinario_count_temp_n0000_0_cyo,
DI => count_temp(1),
S => N4,
O => contadorbinario_count_temp_n0000_1_cyo
);
contadorbinario_count_temp_n0000_1_xor : XORCY
port map (
CI => contadorbinario_count_temp_n0000_0_cyo,
LI => N4,
O => count_temp_n0000(1)
);
contadorbinario_count_temp_n0000_1_lut : LUT2_L
generic map(
INIT => X"9"
)
port map (
I0 => count_direction_IBUF,
I1 => count_temp(1),
LO => N4
);
contadorbinario_count_temp_n0000_2_cy : MUXCY
port map (
CI => contadorbinario_count_temp_n0000_1_cyo,
DI => count_temp(2),
S => N5,
O => contadorbinario_count_temp_n0000_2_cyo
);
contadorbinario_count_temp_n0000_2_xor : XORCY
port map (
CI => contadorbinario_count_temp_n0000_1_cyo,
LI => N5,
O => count_temp_n0000(2)
);
contadorbinario_count_temp_n0000_2_lut : LUT2_L
generic map(
INIT => X"9"
)
port map (
I0 => count_direction_IBUF,
I1 => count_temp(2),
LO => N5
);
contadorbinario_count_temp_n0000_3_cy : MUXCY
port map (
CI => contadorbinario_count_temp_n0000_2_cyo,
DI => count_temp(3),
S => N6,
O => contadorbinario_count_temp_n0000_3_cyo
);
contadorbinario_count_temp_n0000_3_xor : XORCY
port map (
CI => contadorbinario_count_temp_n0000_2_cyo,
LI => N6,
O => count_temp_n0000(3)
);
contadorbinario_count_temp_n0000_3_lut : LUT2_L
generic map(
INIT => X"9"
)
port map (
I0 => count_direction_IBUF,
I1 => count_temp(3),
LO => N6
);
contadorbinario_count_temp_n0000_4_cy : MUXCY
port map (
CI => contadorbinario_count_temp_n0000_3_cyo,
DI => count_temp(4),
S => N7,
O => contadorbinario_count_temp_n0000_4_cyo
);
contadorbinario_count_temp_n0000_4_xor : XORCY
port map (
CI => contadorbinario_count_temp_n0000_3_cyo,
LI => N7,
O => count_temp_n0000(4)
);
contadorbinario_count_temp_n0000_4_lut : LUT2_L
generic map(
INIT => X"9"
)
port map (
I0 => count_direction_IBUF,
I1 => count_temp(4),
LO => N7
);
contadorbinario_count_temp_n0000_5_cy : MUXCY
port map (
CI => contadorbinario_count_temp_n0000_4_cyo,
DI => count_temp(5),
S => N8,
O => contadorbinario_count_temp_n0000_5_cyo
);
contadorbinario_count_temp_n0000_5_xor : XORCY
port map (
CI => contadorbinario_count_temp_n0000_4_cyo,
LI => N8,
O => count_temp_n0000(5)
);
contadorbinario_count_temp_n0000_5_lut : LUT2_L
generic map(
INIT => X"9"
)
port map (
I0 => count_direction_IBUF,
I1 => count_temp(5),
LO => N8
);
contadorbinario_count_temp_n0000_6_cy : MUXCY
port map (
CI => contadorbinario_count_temp_n0000_5_cyo,
DI => count_temp(6),
S => N9,
O => contadorbinario_count_temp_n0000_6_cyo
);
contadorbinario_count_temp_n0000_6_xor : XORCY
port map (
CI => contadorbinario_count_temp_n0000_5_cyo,
LI => N9,
O => count_temp_n0000(6)
);
contadorbinario_count_temp_n0000_6_lut : LUT2_L
generic map(
INIT => X"9"
)
port map (
I0 => count_direction_IBUF,
I1 => count_temp(6),
LO => N9
);
clock_BUFGP_0 : BUFGP
port map (
I => clock,
O => clock_BUFGP
);
reset_IBUF_1 : IBUF
port map (
I => reset,
O => reset_IBUF
);
count_direction_IBUF_2 : IBUF
port map (
I => count_direction,
O => count_direction_IBUF
);
clock_enable_IBUF_3 : IBUF
port map (
I => clock_enable,
O => clock_enable_IBUF
);
count_7_OBUF : OBUF
port map (
I => count_temp(7),
O => count(7)
);
count_6_OBUF : OBUF
port map (
I => count_temp(6),
O => count(6)
);
count_5_OBUF : OBUF
port map (
I => count_temp(5),
O => count(5)
);
count_4_OBUF : OBUF
port map (
I => count_temp(4),
O => count(4)
);
count_3_OBUF : OBUF
port map (
I => count_temp(3),
O => count(3)
);
count_2_OBUF : OBUF
port map (
I => count_temp(2),
O => count(2)
);
end Structure;
|
gpl-3.0
|
300d73577053d6b112bbb6036387e54a
| 0.54449 | 3.263866 | false | false | false | false |
lelongdunet/dspunit
|
sim/bench_div.vhd
| 2 | 4,333 |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2009 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=3000ns
-->SIMSAVFILE=dspdiv.sav
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity bench_div is
end bench_div;
--=----------------------------------------------------------------------------
architecture archi_bench_div of bench_div is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_sig_width : integer := 16;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
component dspdiv
generic (
sig_width : integer
);
port (
num : in std_logic_vector((2*sig_width - 1) downto 0);
den : in std_logic_vector((sig_width - 1) downto 0);
clk : in std_logic;
q : out std_logic_vector((sig_width - 1) downto 0);
r : out std_logic_vector((2*sig_width - 3) downto 0)
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_clk : std_logic;
signal s_reset : std_logic;
signal s_num : std_logic_vector((2*c_sig_width - 1) downto 0);
signal s_den : std_logic_vector((c_sig_width - 1) downto 0);
signal s_q : std_logic_vector((c_sig_width - 1) downto 0);
signal s_r : std_logic_vector((2*c_sig_width - 3) downto 0);
begin -- archs_bench_div
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
clock_gen_1 : clock_gen
generic map (
tpw => 5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
dspdiv_1 : dspdiv
generic map (
sig_width => c_sig_width)
port map (
num => s_num,
den => s_den,
clk => s_clk,
q => s_q,
r => s_r);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_num <= x"00050000", x"05000000" after 21 ns, x"00050000" after 31 ns;
s_den <= x"0406", x"0400" after 11 ns, x"FBFA" after 41 ns, x"0400" after 51 ns;
-- s_num <= x"00050000",x"00050000" after 11 ns, x"FFFB0000" after 21 ns;
-- s_den <= x"0406",x"FC00" after 31 ns;
end archi_bench_div;
-------------------------------------------------------------------------------
|
gpl-3.0
|
a1348938f9b0e0d03f89ff655d69549c
| 0.406647 | 4.689394 | false | false | false | false |
straywarrior/MadeCPUin21days
|
Register_Files_Test.vhd
| 1 | 3,885 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:42:00 11/24/2015
-- Design Name:
-- Module Name: Z:/Project/MadeCPUin21days/Register_Files_Test.vhd
-- Project Name: MadeCPUin21days
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Register_Files
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Register_Files_Test IS
END Register_Files_Test;
ARCHITECTURE behavior OF Register_Files_Test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Register_Files
PORT(
clk : IN std_logic;
reset : IN std_logic;
ASel : IN std_logic_vector(3 downto 0);
BSel : IN std_logic_vector(3 downto 0);
WSel : IN std_logic_vector(3 downto 0);
WE : IN std_logic;
WVal : IN std_logic_vector(15 downto 0);
AVal : OUT std_logic_vector(15 downto 0);
BVal : OUT std_logic_vector(15 downto 0);
RAVal : OUT std_logic_vector(15 downto 0);
SPVal : OUT std_logic_vector(15 downto 0);
IHVal : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal ASel : std_logic_vector(3 downto 0) := (others => '0');
signal BSel : std_logic_vector(3 downto 0) := (others => '0');
signal WSel : std_logic_vector(3 downto 0) := (others => '0');
signal WE : std_logic := '0';
signal WVal : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal AVal : std_logic_vector(15 downto 0);
signal BVal : std_logic_vector(15 downto 0);
signal RAVal : std_logic_vector(15 downto 0);
signal SPVal : std_logic_vector(15 downto 0);
signal IHVal : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Register_Files PORT MAP (
clk => clk,
reset => reset,
ASel => ASel,
BSel => BSel,
WSel => WSel,
WE => WE,
WVal => WVal,
AVal => AVal,
BVal => BVal,
RAVal => RAVal,
SPVal => SPVal,
IHVal => IHVal
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state.
reset <= '1';
wait for 10 ns;
reset <= '0';
wait for 10 ns;
-- insert stimulus here
ASel <= "0000";
BSel <= "0001";
WSel <= "1001";
WVal <= "1010010100001000";
WE <= '1';
wait for 20 ns;
ASel <= "0000";
BSel <= "0001";
WSel <= "0001";
WVal <= "1010010100001001";
WE <= '1';
wait for 20 ns;
ASel <= "0001";
BSel <= "0010";
WSel <= "0001";
WVal <= "1010010100001010";
WE <= '1';
wait for 20 ns;
wait;
end process;
END;
|
gpl-2.0
|
0997b757ebbed8c005622457fffdde1e
| 0.550322 | 3.916331 | false | true | false | false |
michaelmiehling/A25_VME_TB
|
Testbench/M25P32/ACDC_check.vhd
| 1 | 10,758 |
-------------------------------------------------------
-- Author: Hugues CREUSY
--February 2004
-- VHDL model
-- project: M25P32 50 MHz,
-- release: 1.0
-----------------------------------------------------
-- Unit : ACDC_check_pkg
-----------------------------------------------------
-------------------------------------------------------------
-- These VHDL models are provided "as is" without warranty
-- of any kind, included but not limited to, implied warranty
-- of merchantability and fitness for a particular purpose.
-------------------------------------------------------------
--------------------------------------------------------------------------
--
-- ACDC CHECK --
--
--------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL;
LIBRARY STD;
USE STD.textio.ALL;
--------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------
-- This entity receives SPI port signals and one signal write operation
-- from the internal logic
--------------------------------------------------------------------------
Entity ACDC_check is
generic ( Tc: TIME;
Tr: TIME;
tSLCH: TIME;
tCHSL: TIME;
tCH : TIME;
tCL : TIME;
tDVCH: TIME;
tCHDX: TIME;
tCHSH : TIME;
tSHCH: TIME;
tSHSL: TIME;
tHLCH: TIME;
tCHHH: TIME ;
tHHCH: TIME;
tCHHL: TIME;
tVSL: TIME ;
tPUW: TIME ;
tWHSL: TIME;
tSHWL: TIME;
Vwi: REAL;
Vccmin: REAL;
Vccmax: REAL
);
port (VCC: IN REAL; C, D, S, HOLD : IN std_logic;
write_op,read_op: IN boolean;
wrsr: IN boolean;
srwd_wrsr: IN boolean;
write_protect: IN boolean;
Power_up: OUT boolean
);
END ACDC_check;
--------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------
-- Several processes test and verify AC/DC characteristics
-- and timings
--------------------------------------------------------------
ARCHITECTURE spy OF ACDC_check IS
SIGNAL VCCmin_ok,Vwi_ok: boolean:=false;
SIGNAL high_time,low_time: TIME:=100 ns;
SIGNAL t_c_rise,t_c_fall: TIME:=100 ns;
SIGNAL t_write_protect_fall: TIME:=0 ns;
SIGNAL t_s_rise, t_s_fall: TIME:= 0 ns;
BEGIN
---------------------------------------------------
-- This process checks Vcc level:
-- VCCmin<VCC<VCCmax
-- VCC>Vwi
---------------------------------------------------
VCC_watch: PROCESS
BEGIN
WAIT ON VCC;
IF (VCC>VCCmax) THEN
REPORT "VCC>VCCmax no more instructions guaranteed"
severity ERROR;
END IF;
IF ((VCC>=Vccmin) AND (VCC'last_value<Vccmin)) THEN
Vccmin_ok <= true;
END IF;
IF ((VCC<=Vccmin) AND (VCC'last_value>Vccmin)) THEN
Vccmin_ok <= false;
IF write_op THEN
REPORT "VCC<VCCmin : write cycle not guaranteed"
severity ERROR;
ELSE REPORT "VCC<VCCmin : no more instructions guaranteed"
severity WARNING;
END IF;
END IF;
IF ((VCC>=Vwi) AND (VCC'last_value<Vwi)) THEN
Vwi_ok <= true;
Power_up<=true;
END IF;
IF ((VCC<=Vwi) AND (VCC'last_value>Vwi)) THEN
Vwi_ok <= false;
Power_up<=false;
IF write_op THEN
REPORT "VCC<Vwi and write cycle in progress: data corrupted"
severity FAILURE;
ELSE REPORT "VCC<Vwi: the chip is now reset"
severity WARNING;
END IF;
END IF;
END PROCESS VCC_watch;
------------------------------------------------------------------------
-- This process checks that no write instruction is sent during power up
------------------------------------------------------------------------
PUW:PROCESS
BEGIN
WAIT ON write_op;
IF (write_op) THEN
ASSERT (Vwi_ok AND (Vwi_ok'stable(tPUW)))
REPORT "No write instruction is allowed until a time delay of tPUW"
severity ERROR;
END IF;
END PROCESS PUW;
----------------------------------------------
-- This process checks pulses length on pin /S
----------------------------------------------
SHSL_watch:PROCESS
VARIABLE t0,t1:TIME:= 0 ns;
BEGIN
WAIT ON S;
IF ( S='1') THEN
t0:=now;
t_s_rise<=t0;
WAIT UNTIL (S'event AND S='0');
t1:=now;
t_s_fall<=t1;
IF ((t1-t0)<tSHSL) THEN
REPORT "tSHSL condition violated"
severity ERROR;
END IF;
END IF;
END PROCESS SHSL_watch;
---------------------------------------------------------------
-- This process checks select setup and hold timings
-- and Vccmin to select low timing
---------------------------------------------------------------
S_watch1:PROCESS
VARIABLE t:TIME:=0 ns;
BEGIN
WAIT ON S;
IF (S='0' AND HOLD/='0') THEN
ASSERT (Vwi_ok)
REPORT "VCC<Vwi: chip is on reset mode and will not respond"
severity FAILURE;
IF (NOT Vccmin_ok) THEN
REPORT "Vcc<Vccmin: operation not guaranteed"
severity ERROR;
ELSIF (Vccmin_ok AND (NOT Vccmin_ok'stable(tVSL))) THEN
REPORT "Vcc must be greater than VCCmin during at least tVSL before chip is selected"
severity ERROR;
END IF;
ASSERT (Vccmin_ok AND Vccmin_ok'stable(tVSL))
REPORT "Vcc must be greater than VCCmin during at least tVSL before chip is selected"
severity ERROR;
t:=now;
IF ((t-t_c_rise)<tCHSL) THEN
REPORT "tCHSL condition violated"
severity ERROR;
END IF;
IF (C='1')THEN
WAIT ON C FOR tSLCH;
WAIT ON C FOR tSLCH;
IF (C'event=true AND C='1' AND(NOW-t)<tSLCH) THEN
REPORT "tSLCH condition violated"
severity ERROR;
END IF;
ELSIF (C='0') THEN
WAIT ON C FOR tSLCH;
IF (C'event=true AND (NOW-t)<tSLCH) THEN
REPORT "tSLCH condition violated"
severity ERROR;
END IF;
END IF;
END IF;
END PROCESS S_watch1;
------------------------------------------------------
-- This process checks deselect setup timings
------------------------------------------------------
S_watch2:PROCESS
VARIABLE t:TIME:=0 ns;
BEGIN
WAIT ON S;
t:=now;
IF (S='1' AND HOLD /='0') THEN
IF ((t-t_c_rise)<tCHSH AND NOW/=0 ns) THEN
REPORT "tCHSH condition violated"
severity ERROR;
END IF;
IF (C='1') THEN
WAIT ON C FOR tSHCH;
WAIT ON C FOR tSHCH;
IF (C'event=true AND C='1' AND (NOW-t)<tSHCH) THEN
REPORT "tSHCH condition violated"
severity ERROR;
END IF;
ELSIF (C='0') THEN
WAIT ON C FOR tSHCH;
IF (C'event=true AND (NOW-t)<tSHCH) THEN
REPORT "tSHCH condition violated"
severity ERROR;
END IF;
END IF;
END IF;
END PROCESS S_watch2;
-----------------------------------
-- This process checks hold timings
-----------------------------------
hold_watch:PROCESS
VARIABLE t:TIME:=0 ns;
BEGIN
WAIT ON hold;
IF (hold='0') THEN
IF (C='1')THEN
IF (NOT C'stable(tCHHL)) THEN
REPORT "tCHHL condition violated"
severity ERROR;
END IF;
t:=NOW;
ELSIF (C='0') THEN
WAIT ON C FOR tHLCH;
IF (C'event=true AND (NOW-t)/=tHLCH) THEN
REPORT "tHLCH condition violated"
severity ERROR;
END IF;
END IF;
END IF;
IF (hold='1') THEN
IF (C='1') THEN
IF (NOT C'stable(tCHHH)) THEN
REPORT "tCHHH condition violated"
severity ERROR;
END IF;
t:=NOW;
ELSIF (C='0') THEN
WAIT ON C FOR tHHCH;
IF (C'event=true AND (NOW-t)/=tHHCH) THEN
REPORT "tHHCH condition violated"
severity ERROR;
END IF;
END IF;
END IF;
END PROCESS hold_watch;
----------------------------------------------------
-- This process checks data hold and setup timings
----------------------------------------------------
D_watch: PROCESS
VARIABLE t:TIME:=0 ns;
BEGIN
WAIT ON D;
IF (C='1')THEN
IF (NOT C'stable(tCHDX)) THEN
IF (S='0'AND HOLD='1') THEN REPORT "tCHDX condition violated" severity ERROR; END IF;
END IF;
t:=NOW;
ELSIF (C='0') THEN
WAIT ON C FOR tDVCH;
IF (C'event=true AND (NOW-t)/=tDVCH) THEN
IF (S='0'AND HOLD='1') THEN REPORT "tDVCH condition violated" severity ERROR; END IF;
END IF;
END IF;
END PROCESS D_watch;
---------------------------------------
-- This process checks clock high time
---------------------------------------
C_high_watch: PROCESS
VARIABLE t1:TIME:=0 ns;
BEGIN
WAIT ON C;
IF ( C='1') THEN
IF (S='1') THEN
high_time <= 100 ns;
t_c_rise<=now;
ELSE
t_c_rise<=now;
WAIT UNTIL (C'event AND C='0');
t1:=now;
high_time<=t1-t_c_rise;
IF ((t1-t_c_rise)<tCH) THEN
IF (S='0'AND HOLD='1') THEN
REPORT "tCH condition violated"
severity ERROR;
END IF;
END IF;
END IF;
END IF;
END PROCESS C_high_watch;
---------------------------------------
-- This process checks clock low time
---------------------------------------
C_low_watch: PROCESS
VARIABLE t1:TIME:=0 ns;
BEGIN
WAIT ON C;
IF ( C='0') THEN
IF (S='1') THEN
low_time <= 100 ns;
ELSE
t_c_fall<=now;
WAIT UNTIL (C'event AND C='1');
t1:=now;
low_time <= t1-t_c_fall;
IF ((t1-t_c_fall)<tCL) THEN
IF (S='0'AND HOLD='1') THEN
REPORT "tCL condition violated"
severity ERROR;
END IF;
END IF;
ENd IF;
END IF;
END PROCESS C_low_watch;
-------------------------------------------------
-- This process checks clock frequency
-------------------------------------------------
freq_watch: PROCESS(high_time,low_time)
BEGIN
IF read_op THEN
IF ((high_time+low_time)<Tr) THEN
IF (S='0' AND HOLD='1') THEN REPORT "Clock frequency condition violated for READ instruction: fR>20MHz" severity ERROR; END IF;
END IF;
ELSIF ((high_time+low_time)<Tc) THEN
IF (S='0' AND HOLD='1') THEN REPORT "Clock frequency condition violated: fC>25MHz" severity ERROR; END IF;
END IF;
END PROCESS freq_watch;
--------------------------------------------------------------------------
-- This process detects the write_protect negative transitions
--------------------------------------------------------------------------
write_protect_watch: PROCESS
BEGIN
WAIT ON write_protect;
IF (NOW /= 0 ns) THEN
IF (NOT write_protect) THEN t_write_protect_fall <= NOW; END IF;
END IF;
END PROCESS write_protect_watch;
--------------------------------------------------------
-- This process checks the TWHSL parameter
--------------------------------------------------------
TWHSL_watch: PROCESS
BEGIN
WAIT ON srwd_wrsr;
IF (NOW /= 0 ns) THEN
IF ((t_s_fall - t_write_protect_fall) < tWHSL) THEN
REPORT "tWHSL condition violated"
severity FAILURE;
END IF;
END IF;
END PROCESS TWHSL_watch;
--------------------------------------------------------
-- This process checks the TSHWL parameter
--------------------------------------------------------
TSHWL_watch: PROCESS
VARIABLE t0:TIME:=0 ns;
BEGIN
WAIT ON write_protect;
IF (NOW /= 0 ns) THEN
t0 := NOW;
IF ( write_protect AND WRSR) THEN
IF ((t0 -t_s_rise) < tSHWL) THEN REPORT "tSHWL condition violated" severity FAILURE; END IF;
END IF;
END IF;
END PROCESS TSHWL_watch;
END SPY;
|
gpl-3.0
|
3f2428b6b2558d21fddaf096e43102c1
| 0.51952 | 3.644309 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_updt_noqueue.vhd
| 1 | 24,236 |
-------------------------------------------------------------------------------
-- axi_sg_updt_noqueue
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_noqueue.vhd
-- Description: This entity provides the descriptor update for the No Queue mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Seperated update queues into two seperate files, no queue and queue to
-- simplify maintainance.
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
library lib_pkg_v1_0;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33
-- 1 IOC bit + 32 Update Status Bits
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface In **-- --
--*********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface Out**-- --
--*********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Contstants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal writing_curdesc : std_logic := '0';
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
signal writing_status : std_logic := '0';
signal curdesc_tready : std_logic := '0';
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- the channel
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= updt_active and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active,
s_axis_updtptr_tvalid,
s_axis_updtsts_tvalid,
s_axis_updtsts_tlast,
m_axis_updt_tready)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
writing_curdesc <= '0';
curdesc_tready <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if(s_axis_updtptr_tvalid = '1' and updt_active = '1')then
writing_curdesc <= '1';
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor
when READ_CURDESC_LSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(s_axis_updtptr_tvalid = '1' and updt_active = '1')then
write_curdesc_lsb <= '1';
pntr_ns <= READ_CURDESC_MSB;
else
pntr_ns <= READ_CURDESC_LSB;
end if;
---------------------------------------------------------------
-- Get upper current descriptor
when READ_CURDESC_MSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(s_axis_updtptr_tvalid = '1')then
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
writing_status <= s_axis_updtsts_tvalid;
if(s_axis_updtsts_tvalid = '1' and m_axis_updt_tready = '1'
and s_axis_updtsts_tlast = '1')then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
when others =>
pntr_ns <= IDLE;
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
-- Status stream signals
m_axis_updt_tdata <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid <= s_axis_updtsts_tvalid and writing_status;
m_axis_updt_tlast <= s_axis_updtsts_tlast and writing_status;
s_axis_updtsts_tready <= m_axis_updt_tready and writing_status;
-- Pointer stream signals
s_axis_updtptr_tready <= curdesc_tready;
-- Indicate need for channel service for update state machine
updt_queue_empty <= not s_axis_updtsts_tvalid;
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_msb = '1')then
updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re = '1')then
updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re = '1')then
dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re = '1')then
dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re = '1')then
dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
end implementation;
|
gpl-2.0
|
a1deb5525f3f342fdc01854ed7d70505
| 0.392887 | 5.136922 | false | false | false | false |
nulldozer/purisc
|
Compute_Group/MAGIC_clocked/RAM_5.vhd
| 1 | 10,399 |
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM_5.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY RAM_5 IS
PORT
(
aclr : IN STD_LOGIC := '0';
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END RAM_5;
ARCHITECTURE SYN OF ram_5 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
init_file => "RAM_5.mif",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "CLEAR0",
outdata_aclr_b => "CLEAR0",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "OLD_DATA",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 10,
widthad_b => 10,
width_a => 32,
width_b => 32,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
aclr0 => aclr,
address_a => address_a,
address_b => address_b,
clock0 => clock,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "1"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "RAM_5.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INIT_FILE STRING "RAM_5.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
-- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
-- Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
-- Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
-- Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
-- Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_5.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_5.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_5.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_5.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_5_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
00bb4770d6072c4d9805d58020e56f33
| 0.666314 | 3.290823 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
16x004-01_src/Source/pcie_sim_pkg.vhd
| 1 | 46,199 |
--------------------------------------------------------------------------------
-- Title : simulation package for PCIe simulation model 16x004-01
-- Project :
--------------------------------------------------------------------------------
-- File : pcie_sim_pkg.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2017-05-31
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
--------------------------------------------------------------------------------
-- Hierarchy :
--------------------------------------------------------------------------------
-- Copyright (C) 2017, MEN Mikro Elektronik Nuremberg GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.print_pkg.all;
use work.utils_pkg.all;
use work.altpcietb_bfm_constants.all;
use work.altpcietb_bfm_log.all;
use work.altpcietb_bfm_req_intf.all;
use work.altpcietb_bfm_shmem.all;
use work.altpcietb_bfm_rdwr.all;
use work.altpcietb_bfm_configure.all;
package pcie_sim_pkg is
type dword_vector is array (integer range <>) of std_logic_vector(31 downto 0);
-- +----------------------------------------------------------------------------
-- | constants
-- +----------------------------------------------------------------------------
-----------------------------------------------------
-- constants to use in terminal_out.tga(1 downto 0)
-----------------------------------------------------
constant IO_TRANSFER : std_logic_vector(1 downto 0) := "00";
constant MEM32_TRANSFER : std_logic_vector(1 downto 0) := "01";
constant CONFIG_TRANSFER : std_logic_vector(1 downto 0) := "10";
constant SETUP_CYCLE : std_logic_vector(1 downto 0) := "11";
-----------------------------------------------------
-- constants to use in terminal_out.tga(3 downto 2)
-----------------------------------------------------
constant BFM_NBR_0 : std_logic_vector(1 downto 0) := "00";
constant BFM_NBR_1 : std_logic_vector(1 downto 0) := "01";
constant BFM_NBR_2 : std_logic_vector(1 downto 0) := "10";
constant BFM_NBR_3 : std_logic_vector(1 downto 0) := "11";
------------------------------
-- constants for general use
------------------------------
constant BFM_BUFFER_MAX_SIZE : integer := 1024;
constant DONT_CHECK32 : std_logic_vector(31 downto 0) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
constant ZERO_32BIT : std_logic_vector(31 downto 0) := (others => '0');
-- +----------------------------------------------------------------------------
-- | functions
-- +----------------------------------------------------------------------------
--! function that calculates the last byte enables of a transfer
--! @param first_dw first enabled bytes of this transfer
--! @param byte_count amount of bytes for this transfer
--! @return last_dw(3 downto 0) last enabled bytes for this transfer
function calc_last_dw(
first_dw : std_logic_vector(3 downto 0);
byte_count : integer
) return std_logic_vector; -- returns std_logic_vector(3 downto 0)
-- +----------------------------------------------------------------------------
-- | procedures
-- +----------------------------------------------------------------------------
--! procedure to check a value against a reference value
--! @param caller_proc string argument which is used in error messages to define the position where
--! this procedure was called from
--! @param ref_val 32bit reference value
--! @param check_val 32bit value that is checked against ref_val
--! @param byte_valid defines which byte of check_val is valid, invalid bytes are not compared
--! @return check_ok boolean argument which states whether the check was ok (=true) or not
procedure check_val(
caller_proc : in string;
ref_val : in std_logic_vector(31 downto 0);
check_val : in std_logic_vector(31 downto 0);
byte_valid : in std_logic_vector(3 downto 0);
check_ok : out boolean
);
--! procedure to initialize the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be initialized
--! @param io_add start address for the BFM internal I/O space
--! @param mem32_addr start address for the BFM internal MEM32 space
--! @param mem64_addr start address for the BFM internal MEM64 space
--! @param requester_id defines the requester ID that is used for every BFM transfer
--! @param max_payloadsize defines the maximum payload size for every write request
procedure init_bfm(
bfm_inst_nbr : in integer;
io_addr : in std_logic_vector(31 downto 0);
mem32_addr : in std_logic_vector(31 downto 0);
mem64_addr : in std_logic_vector(63 downto 0);
requester_id : in std_logic_vector(15 downto 0);
max_payloadsize : in integer
);
procedure set_bfm_memory(
nbr_of_dw : in integer;
mem_addr : in std_logic_vector(31 downto 0);
start_data_val : in std_logic_vector(31 downto 0);
data_inc : in integer
);
procedure get_bfm_memory(
nbr_of_dw : in integer;
mem_addr : in std_logic_vector(31 downto 0);
databuf_out : out dword_vector(BFM_BUFFER_MAX_SIZE downto 0)
);
-----------------------------------------------
-- single memory write to 32bit address space
-----------------------------------------------
procedure bfm_wr_mem32(
pcie_addr : in std_logic_vector(1 downto 0);
bar_num : in natural;
bar_offset : in natural;
byte_count : in natural range 4 downto 1;
data32 : in std_logic_vector(31 downto 0);
success : out boolean
);
----------------------------------------------
-- burst memory write to 32bit address space
----------------------------------------------
procedure bfm_wr_mem32(
bar_num : in natural;
bar_offset : in natural;
byte_count : in integer;
data32 : in dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
success : out boolean
);
procedure bfm_rd_mem32(
bar_num : in natural;
bar_offset : in natural;
byte_en : in std_logic_vector(3 downto 0);
ref_data32 : in std_logic_vector(31 downto 0);
data32_out : out std_logic_vector(31 downto 0);
success : out boolean
);
procedure bfm_rd_mem32(
bar_num : in natural;
bar_offset : in natural;
byte_count : in integer;
ref_data32 : in dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
data32_out : out dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
success : out boolean
);
procedure bfm_wr_config(
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
data32 : in std_logic_vector(31 downto 0);
success : out boolean
);
procedure bfm_rd_config(
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
ref_data32 : in std_logic_vector(31 downto 0);
data32_out : out std_logic_vector(31 downto 0);
success : out boolean
);
procedure wait_on_irq_assert(
irq_nbr : in integer range 3 downto 0
);
procedure wait_on_irq_deassert(
irq_nbr : in integer range 3 downto 0
);
procedure bfm_configure_msi(
constant msi_addr : in natural; -- MSI address in shared memory
msi_data : in std_logic_vector(15 downto 0); -- contained in MSI message
msi_allocated : out std_logic_vector(2 downto 0); -- amount of allocated MSI
success : out boolean
);
procedure bfm_calc_msi_expected(
constant msi_allocated : in std_logic_vector(2 downto 0); -- amount of allocated MSI
constant msi_data : in std_logic_vector(15 downto 0); -- MSI data value as programmed to config space
constant msi_nbr : in integer range 32 downto 0;
variable msi_expected : out std_logic_vector(31 downto 0) -- MSI vector as expected from EP
);
procedure bfm_poll_msi(
constant track_msi : in natural;
constant msi_addr : in natural;
constant msi_expected : in std_logic_vector(31 downto 0);
constant txt_out : in integer;
success : out boolean
);
end package pcie_sim_pkg;
package body pcie_sim_pkg is
function calc_last_dw(
first_dw : std_logic_vector(3 downto 0);
byte_count : integer
) return std_logic_vector is
variable first_bytes : integer := 0;
variable last_bytes : integer := 0;
variable return_int : std_logic_vector(3 downto 0);
begin
if first_dw(0) = '1' then
first_bytes := first_bytes +1;
end if;
if first_dw(1) = '1' then
first_bytes := first_bytes +1;
end if;
if first_dw(2) = '1' then
first_bytes := first_bytes +1;
end if;
if first_dw(3) = '1' then
first_bytes := first_bytes +1;
end if;
last_bytes := (byte_count - first_bytes) mod 4;
if last_bytes = 0 then
return_int := "1111";
elsif last_bytes = 1 then
return_int := "0001";
elsif last_bytes = 2 then
return_int := "0011";
elsif last_bytes = 3 then
return_int := "0111";
else
return_int := "XXXX";
assert false report "ERROR in function calc_last_dw(): illegal value for variable last_bytes" severity error;
end if;
return return_int;
end;
procedure check_val(
caller_proc : in string;
ref_val : in std_logic_vector(31 downto 0);
check_val : in std_logic_vector(31 downto 0);
byte_valid : in std_logic_vector(3 downto 0);
check_ok : out boolean
) is
variable pass : boolean := true;
begin
if byte_valid(0) = '1' then
if ref_val(7 downto 0) /= check_val(7 downto 0) then
print_now("BFM ERROR in " & caller_proc & "(): data read does not match given reference value - mismatch in byte0");
write_s_slvec("BFM ERROR in " & caller_proc & "(): reference value[7:0] = ",ref_val(7 downto 0));
write_s_slvec("BFM ERROR in " & caller_proc & "(): read value[7:0] = ",check_val(7 downto 0));
pass := false;
end if;
end if;
if byte_valid(1) = '1' then
if ref_val(15 downto 8) /= check_val(15 downto 8) then
print_now("BFM ERROR in " & caller_proc & "(): data read does not match given reference value - mismatch in byte1");
write_s_slvec("BFM ERROR in " & caller_proc & "(): reference value[15:8] = ",ref_val(15 downto 8));
write_s_slvec("BFM ERROR in " & caller_proc & "(): read value[15:8] = ",check_val(15 downto 8));
pass := false;
end if;
end if;
if byte_valid(2) = '1' then
if ref_val(23 downto 16) /= check_val(23 downto 16) then
print_now("BFM ERROR in " & caller_proc & "(): data read does not match given reference value - mismatch in byte2");
write_s_slvec("BFM ERROR in " & caller_proc & "(): reference value[23:16] = ",ref_val(23 downto 16));
write_s_slvec("BFM ERROR in " & caller_proc & "(): read value[23:16] = ",check_val(23 downto 16));
pass := false;
end if;
end if;
if byte_valid(3) = '1' then
if ref_val(31 downto 24) /= check_val(31 downto 24) then
print_now("BFM ERROR in " & caller_proc & "(): data read does not match given reference value - mismatch in byte3");
write_s_slvec("BFM ERROR in " & caller_proc & "(): reference value[31:24] = ",ref_val(31 downto 24));
write_s_slvec("BFM ERROR in " & caller_proc & "(): read value[31:24] = ",check_val(31 downto 24));
pass := false;
end if;
end if;
check_ok := pass;
end procedure;
procedure init_bfm(
bfm_inst_nbr : in integer;
io_addr : in std_logic_vector(31 downto 0);
mem32_addr : in std_logic_vector(31 downto 0);
mem64_addr : in std_logic_vector(63 downto 0);
requester_id : in std_logic_vector(15 downto 0);
max_payloadsize : in integer
) is
begin
print_now("BFM: initialize PCIe BFM");
ebfm_cfg_rp_ep(
bar_table => BAR_TABLE_POINTER, -- defined in BFM shared memory
ep_bus_num => 1,
ep_dev_num => 1,
rp_max_rd_req_size => max_payloadsize,
display_ep_config => 1, -- display config space after endpoint config setup
addr_map_4GB_limit => 0 -- limit BAR assignment to 4GB address map
);
print_now("BFM: link is up");
end procedure;
procedure set_bfm_memory(
nbr_of_dw : in integer;
mem_addr : in std_logic_vector(31 downto 0);
start_data_val : in std_logic_vector(31 downto 0);
data_inc : in integer
) is
variable var_byte_len : integer;
variable var_addr : natural;
variable var_data_buf : std_logic_vector(nbr_of_dw *32 -1 downto 0);
begin
for i in 0 to nbr_of_dw -1 loop
var_data_buf(i*32+31 downto i*32) := std_logic_vector(unsigned(start_data_val) + to_unsigned(i*data_inc,32));
end loop;
var_byte_len := natural(nbr_of_dw *4);
var_addr := to_integer(unsigned(mem_addr));
-------------------------------------------------------------------------------------------
-- Altera BFM doesn't distinguish between I/O and memory space concerning rd/wr functions
-------------------------------------------------------------------------------------------
shmem_write(
addr => var_addr,
data => var_data_buf,
leng => var_byte_len
);
end procedure;
procedure get_bfm_memory(
nbr_of_dw : in integer;
mem_addr : in std_logic_vector(31 downto 0);
databuf_out : out dword_vector(BFM_BUFFER_MAX_SIZE downto 0)
) is
variable var_databuf_max : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable var_byte_len : integer;
variable var_addr : natural;
variable var_data_buf : std_logic_vector(nbr_of_dw *32 -1 downto 0);
begin
if nbr_of_dw > BFM_BUFFER_MAX_SIZE then
print_now("BFM ERROR in get_bfm_memory(): nbr_of_dw exceeds BFM_BUFFER_MAX_SIZE");
else
var_byte_len := natural(nbr_of_dw *4);
var_addr := to_integer(unsigned(mem_addr));
var_data_buf := shmem_read(addr => var_addr, leng => var_byte_len);
for i in 0 to nbr_of_dw -1 loop
var_databuf_max(i) := var_data_buf(i*32+31 downto i*32);
end loop;
databuf_out := var_databuf_max;
end if;
end procedure;
procedure bfm_wr_mem32(
pcie_addr : in std_logic_vector(1 downto 0);
bar_num : in natural;
bar_offset : in natural;
byte_count : in natural range 4 downto 1;
data32 : in std_logic_vector(31 downto 0);
success : out boolean
) is
variable var_pass : boolean := true;
variable var_local_addr : natural := 0;
begin
var_pass := true;
-----------------------------------------
-- write user data to BFM shared memory
-----------------------------------------
var_local_addr := 0;
shmem_write(
addr => var_local_addr,
data => data32,
leng => 4 --byte_count
);
---------------------------
-- transfer data via PCIe
---------------------------
var_local_addr := 0 + (to_integer(unsigned(pcie_addr)));
ebfm_barwr(
bar_table => BAR_TABLE_POINTER,
bar_num => bar_num,
pcie_offset => bar_offset,
lcladdr => var_local_addr, -- shmem address
byte_len => byte_count, --4,
tclass => 0
);
report "WARNING (bfm_wr_mem32 - single): return value for success is always true" severity warning;
success := var_pass;
end procedure;
procedure bfm_wr_mem32(
bar_num : in natural;
bar_offset : in natural;
byte_count : in integer;
data32 : in dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
success : out boolean
) is
variable var_data_buf : std_logic_vector(8*byte_count -1 downto 0);
variable var_pass : boolean := true;
variable var_nbr_of_dw : integer;
variable var_local_addr : natural := 0;
variable var_copy_dw_cntr : natural := 0;
variable var_copy_byte_cntr : natural := 0;
begin
var_pass := true;
var_nbr_of_dw := byte_count / 4;
-----------------------------------------------------------------
-- copy user data:
-- use var_copy_counter to access the correct 32bit data vector
-- in the dword_vector structure, use i to copy the correct
-- portion of the 32bit vector
-----------------------------------------------------------------
for i in 0 to byte_count -1 loop
var_copy_byte_cntr := i mod 4;
if (i > 0) and (i mod 4 = 0) then
var_copy_dw_cntr := var_copy_dw_cntr +1;
end if;
wait for 0 ns;
var_data_buf(i*8+7 downto i*8) := data32(var_copy_dw_cntr)(var_copy_byte_cntr*8+7 downto var_copy_byte_cntr*8);
end loop;
-----------------------------------------
-- write user data to BFM shared memory
-----------------------------------------
var_local_addr := 0; -- + bar_offset;
shmem_write(
addr => var_local_addr,
data => var_data_buf,
leng => byte_count -- length in bytes
);
---------------------------
-- transfer data via PCIe
---------------------------
ebfm_barwr(
bar_table => BAR_TABLE_POINTER,
bar_num => bar_num,
pcie_offset => bar_offset,
lcladdr => var_local_addr, -- shmem address
byte_len => byte_count,
tclass => 0
);
report "WARNING (bfm_wr_mem32 - burst): return value for success is always true" severity warning;
success := var_pass;
end procedure;
procedure bfm_rd_mem32(
bar_num : in natural;
bar_offset : in natural;
byte_en : in std_logic_vector(3 downto 0);
ref_data32 : in std_logic_vector(31 downto 0);
data32_out : out std_logic_vector(31 downto 0);
success : out boolean
) is
variable var_byte_len : natural := 0;
variable var_pass : boolean := true;
variable var_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable var_local_addr : natural := 0;
variable var_byte_offset : natural := 0;
begin
var_pass := true;
data32_out := (others => '0');
-----------------------------------------------------
-- initialize data buffer with known default values
-----------------------------------------------------
for i in 0 to BFM_BUFFER_MAX_SIZE loop
var_databuf(i) := x"CAFE_AFFE";
end loop;
if byte_en(0) = '1' then
var_byte_len := var_byte_len +1;
end if;
if byte_en(1) = '1' then
var_byte_len := var_byte_len +1;
end if;
if byte_en(2) = '1' then
var_byte_len := var_byte_len +1;
end if;
if byte_en(3) = '1' then
var_byte_len := var_byte_len +1;
end if;
--------------------------------------------------------------------
-- bar_offset is DW aligned thus prepared for 32bit transfers
-- adapt for byte offset
--------------------------------------------------------------------
case byte_en is
when "0001" =>
var_byte_offset := 0;
when "0010" =>
var_byte_offset := 1;
when "0100" =>
var_byte_offset := 2;
when "1000" =>
var_byte_offset := 3;
when "0011" =>
var_byte_offset := 0;
when "1100" =>
var_byte_offset := 2;
when "1111" =>
var_byte_offset := 0;
when others =>
var_byte_offset := 0;
end case;
-------------------------------------------------
-- add byte offset to PCIe read function to get
-- properly formed PCIe TLP format
-------------------------------------------------
var_local_addr := 0;
ebfm_barrd_wait(
bar_table => BAR_TABLE_POINTER,
bar_num => bar_num,
pcie_offset => (bar_offset + var_byte_offset),
lcladdr => (var_local_addr + var_byte_offset),
byte_len => var_byte_len,
tclass => 0
);
get_bfm_memory(
nbr_of_dw => 1,
mem_addr => std_logic_vector(to_unsigned(var_local_addr,32)),
databuf_out => var_databuf
);
-----------------------------------
-- check if read value is correct
-----------------------------------
if ref_data32 = DONT_CHECK32 then
print_now("BFM: checking of read value skipped on user command");
else
check_val(
caller_proc => "bfm_rd_mem32 - single",
ref_val => ref_data32,
check_val => var_databuf(0),
byte_valid => byte_en,
check_ok => var_pass
);
end if;
data32_out := var_databuf(0);
success := var_pass;
end procedure;
procedure bfm_rd_mem32(
bar_num : in natural;
bar_offset : in natural;
byte_count : in integer;
ref_data32 : in dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
data32_out : out dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
success : out boolean
) is
variable var_databuf_max : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable var_databuf : std_logic_vector(byte_count *8 -1 downto 0);
variable var_pass : boolean := true;
variable var_pass_temp : boolean := true;
variable var_nbr_of_dw : integer;
variable var_local_addr : natural := 0;
variable byte_en : std_logic_vector(3 downto 0) := (others => '0');
variable first_DW_en : std_logic_vector(3 downto 0) := (others => '0');
variable last_DW_en : std_logic_vector(3 downto 0) := (others => '0');
variable var_copy_dw_cntr : natural := 0;
variable var_copy_byte_cntr : natural := 0;
begin
var_pass := true;
data32_out := (others => (others => '0'));
var_nbr_of_dw := byte_count /4;
wait for 0 ns;
-----------------------------------------------------
-- initialize data buffer with known default values
-----------------------------------------------------
for i in 0 to BFM_BUFFER_MAX_SIZE loop
var_databuf_max(i) := x"CAFE_AFFE";
end loop;
var_local_addr := 0;
ebfm_barrd_wait(
bar_table => BAR_TABLE_POINTER,
bar_num => bar_num,
pcie_offset => bar_offset,
lcladdr => var_local_addr,
byte_len => byte_count,
tclass => 0
);
var_databuf := shmem_read(addr => 0, leng => byte_count);
---------------------------------------------------------
-- copy read data:
-- use i to iterate through bytes
-- use var_copy_dw_cntr to iterate through dword vector
-- use var_copy_byte_cntr to iterate through bytes
---------------------------------------------------------
for i in 0 to byte_count -1 loop
var_copy_byte_cntr := i mod 4;
wait for 0 ns;
if (i > 0) and (i mod 4 = 0) then
var_copy_dw_cntr := var_copy_dw_cntr +1;
wait for 0 ns;
end if;
var_databuf_max(var_copy_dw_cntr)(var_copy_byte_cntr*8+7 downto var_copy_byte_cntr*8) := var_databuf(i*8+7 downto i*8);
end loop;
-----------------------------------
-- check if read value is correct
-----------------------------------
for i in 0 to var_nbr_of_dw -1 loop
if ref_data32(i) = DONT_CHECK32 then
print_now("BFM: checking of read value skipped on user command");
else
check_val(
caller_proc => "bfm_rd_mem32 - burst",
ref_val => ref_data32(i),
check_val => var_databuf_max(i),
byte_valid => x"F",
check_ok => var_pass_temp
);
end if;
var_pass := var_pass and var_pass_temp;
end loop;
data32_out := var_databuf_max;
success := var_pass;
end procedure;
procedure bfm_wr_config(
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
data32 : in std_logic_vector(31 downto 0);
success : out boolean
) is
variable var_pcie_addr : std_logic_vector(31 downto 0) := (others => '0');
variable var_compl_status : std_logic_vector(2 downto 0);
variable var_databuf : std_logic_vector(31 downto 0);
variable var_byte_len : natural := 0;
variable var_cfg_space_addr : natural := 0;
variable var_shmem_addr : natural := 0;
variable var_pass : boolean := true;
begin
var_pass := true;
var_pcie_addr(31 downto 2) := pcie_addr;
var_databuf := (others => '0');
--------------------------------------------------------------------------
-- given PCIe address is DW aligned thus address offset for byte or word
-- access must be calculated manually
-- BUT there may be no hole in bytes e.g. byte_en = "1010" is illegal
-- valid:
-- "1111" / "0111" / "0011" / "0001" / "1100" / "0010" / "0100" / "1000"
-- consider this when retrieving data from shared memory!
--------------------------------------------------------------------------
case byte_en is
when "1111" =>
var_byte_len := 4;
var_pcie_addr(1 downto 0) := "00";
var_databuf := data32;
when "0111" =>
var_byte_len := 3;
var_pcie_addr(1 downto 0) := "00";
var_databuf := data32;
when "0011" =>
var_byte_len := 2;
var_pcie_addr(1 downto 0) := "00";
var_databuf := data32;
when "0001" =>
var_byte_len := 1;
var_pcie_addr(1 downto 0) := "00";
var_databuf := data32;
when "1100" =>
var_byte_len := 2;
var_pcie_addr(1 downto 0) := "10";
var_databuf := data32;
when "0010" =>
var_byte_len := 1;
var_pcie_addr(1 downto 0) := "01";
var_databuf := data32;
when "0100" =>
var_byte_len := 1;
var_pcie_addr(1 downto 0) := "10";
var_databuf := data32;
when "1000" =>
var_byte_len := 1;
var_pcie_addr(1 downto 0) := "11";
var_databuf := data32;
when others =>
var_byte_len := 0;
var_pcie_addr := x"0000_0006"; -- status register is RO or RW1C thus safe for dummy write
var_databuf := (others => '0');
end case;
var_cfg_space_addr := to_integer(unsigned(var_pcie_addr));
ebfm_cfgwr_imm_wait(
bus_num => 1,
dev_num => 1,
fnc_num => 0,
regb_ad => var_cfg_space_addr,
regb_ln => var_byte_len,
imm_data => var_databuf,
compl_status => var_compl_status
);
if var_compl_status = "000" then
var_pass := true; -- successful completion
elsif var_compl_status = "001" then
print_now("ERROR(bfm_wr_config): return status for config write is unsupported request");
var_pass := false;
elsif var_compl_status = "010" then
print_now("ERROR(bfm_wr_config): return status for config write is configuration request retry status");
var_pass := false;
elsif var_compl_status = "100" then
print_now("ERROR(bfm_wr_config): return status for config write is completer abort");
var_pass := false;
end if;
success := var_pass;
end procedure;
procedure bfm_rd_config(
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
ref_data32 : in std_logic_vector(31 downto 0);
data32_out : out std_logic_vector(31 downto 0);
success : out boolean
) is
variable var_pcie_addr : std_logic_vector(31 downto 0) := (others => '0');
variable var_databuf : std_logic_vector(31 downto 0);
variable var_compl_status : std_logic_vector(2 downto 0);
variable var_byte_len : natural := 0;
variable var_cfg_space_addr : natural := 0;
variable var_shmem_addr : natural := 0;
variable var_pass : boolean := true;
begin
var_pass := true;
data32_out := (others => '0');
var_compl_status := (others => '1');
var_pcie_addr(31 downto 2) := pcie_addr;
var_databuf := x"FADE_FADE";
var_shmem_addr := 0;
--------------------------------------------------------------------------
-- given PCIe address is DW aligned thus address offset for byte or word
-- access must be calculated manually
-- BUT there may be no hole in bytes e.g. byte_en = "1010" is illegal
-- valid:
-- "1111" / "0111" / "0011" / "0001" / "1100" / "0010" / "0100" / "1000"
-- consider this when retrieving data from shared memory!
--------------------------------------------------------------------------
case byte_en is
when "1111" =>
var_byte_len := 4;
var_pcie_addr(1 downto 0) := "00";
when "0111" =>
var_byte_len := 3;
var_pcie_addr(1 downto 0) := "00";
when "0011" =>
var_byte_len := 2;
var_pcie_addr(1 downto 0) := "00";
when "0001" =>
var_byte_len := 1;
var_pcie_addr(1 downto 0) := "00";
when "1100" =>
var_byte_len := 2;
var_pcie_addr(1 downto 0) := "10";
when "0010" =>
var_byte_len := 1;
var_pcie_addr(1 downto 0) := "01";
when "0100" =>
var_byte_len := 1;
var_pcie_addr(1 downto 0) := "10";
when "1000" =>
var_byte_len := 1;
var_pcie_addr(1 downto 0) := "11";
when others =>
var_byte_len := 0;
var_pcie_addr := (others => '0');
end case;
var_cfg_space_addr := to_integer(unsigned(var_pcie_addr));
ebfm_cfgrd_wait(
bus_num => 1,
dev_num => 1,
fnc_num => 0,
regb_ad => var_cfg_space_addr,
regb_ln => var_byte_len,
lcladdr => var_shmem_addr,
compl_status => var_compl_status
);
if var_compl_status = "000" then
var_pass := true; -- successful completion
elsif var_compl_status = "001" then
print_now("ERROR(bfm_rd_config): return status for config read is unsupported request");
var_pass := false;
elsif var_compl_status = "010" then
print_now("ERROR(bfm_rd_config): return status for config read is configuration request retry status");
var_pass := false;
elsif var_compl_status = "100" then
print_now("ERROR(bfm_rd_config): return status for config read is completer abort");
var_pass := false;
end if;
--------------------------------------
-- read value from BFM shared memory
--------------------------------------
var_databuf := shmem_read(addr => var_shmem_addr, leng => var_byte_len);
---------------------------------------------------------------------------
-- copy data read from shared memory to expected position for check_val()
---------------------------------------------------------------------------
case byte_en is
when "1100" =>
var_databuf(31 downto 16) := var_databuf(15 downto 0);
when "0010" =>
var_databuf(15 downto 8) := var_databuf(7 downto 0);
when "0100" =>
var_databuf(23 downto 16) := var_databuf(7 downto 0);
when "1000" =>
var_databuf(31 downto 24) := var_databuf(7 downto 0);
when others => -- byte position ok
var_databuf := var_databuf;
end case;
-----------------------------------
-- check if read value is correct
-----------------------------------
if ref_data32 = DONT_CHECK32 then
print_now("BFM: checking of read value skipped on user command");
else
check_val(
caller_proc => "bfm_rd_config",
ref_val => ref_data32,
check_val => var_databuf,
byte_valid => byte_en,
check_ok => var_pass
);
end if;
data32_out := var_databuf;
success := var_pass;
end procedure;
procedure wait_on_irq_assert(
irq_nbr : in integer range 3 downto 0
) is
begin
report "ERROR: NO CONTENT IN PROCEDURE WAIT_ON_IRQ_ASSERT" severity error;
end procedure;
procedure wait_on_irq_deassert(
irq_nbr : in integer range 3 downto 0
) is
begin
report "ERROR: NO CONTENT IN PROCEDURE WAIT_ON_IRQ_DEASSERT" severity error;
end procedure;
procedure bfm_configure_msi(
constant msi_addr : in natural; -- MSI address in shared memory
msi_data : in std_logic_vector(15 downto 0); -- contained in MSI message
msi_allocated : out std_logic_vector(2 downto 0); -- amount of allocated MSI
success : out boolean
) is
function check_compl_status(
compl_status : in std_logic_vector(2 downto 0)
) return boolean is
variable var_pass : boolean := false;
begin
if compl_status = "000" then
var_pass := true; -- successful completion
elsif compl_status = "001" then
print_now("ERROR(bfm_configure_msi): return status for config read is unsupported request");
var_pass := false;
elsif compl_status = "010" then
print_now("ERROR(bfm_configure_msi): return status for config read is configuration request retry status");
var_pass := false;
elsif compl_status = "100" then
print_now("ERROR(bfm_configure_msi): return status for config read is completer abort");
var_pass := false;
end if;
return var_pass;
end function check_compl_status;
constant MSI_CAP_ADDR : natural := 80; -- MSI capabilities register
constant TRAFFIC_CLASS : std_logic_vector(2 downto 0) := "000";
constant BUS_NUM : natural := 1;
constant DEV_NUM : natural := 1;
constant FUNC_NUM : natural := 0;
variable var_pass : boolean := true;
variable var_msi_ctrl_reg : std_logic_vector(15 downto 0) := (others => '0');
variable var_msi_is_64b : std_logic_vector(0 downto 0) := (others => '0');
variable var_is_multi_mess : std_logic_vector(2 downto 0) := (others => '0');
variable var_multi_mess_en : std_logic_vector(2 downto 0) := (others => '0');
variable var_msi_en : std_logic := '0';
variable var_compl_status : std_logic_vector(2 downto 0) := (others => '0');
variable var_msi_addr : std_logic_vector(31 downto 0) := (others => '0');
begin
var_pass := true;
var_msi_addr := std_logic_vector(to_unsigned(msi_addr,32));
-- read EP config space
ebfm_cfgrd_wait(
bus_num => BUS_NUM,
dev_num => DEV_NUM,
fnc_num => FUNC_NUM,
regb_ad => MSI_CAP_ADDR,
regb_ln => 4,
lcladdr => msi_addr,
compl_status => var_compl_status
);
var_pass := check_compl_status(var_compl_status);
-- check if EP has 64bit MSI and multi message enabled
var_msi_ctrl_reg := shmem_read(msi_addr +2, 2);
var_msi_is_64b := var_msi_ctrl_reg(7 downto 7);
var_is_multi_mess := var_msi_ctrl_reg(3 downto 1);
var_multi_mess_en := var_is_multi_mess;
-- enable msi
var_msi_en := '1';
-- write changed content back tp EP config space
ebfm_cfgwr_imm_wait(
bus_num => BUS_NUM,
dev_num => DEV_NUM,
fnc_num => FUNC_NUM,
regb_ad => MSI_CAP_ADDR,
regb_ln => 4,
imm_data => (x"00" & var_msi_is_64b &
var_multi_mess_en &
var_is_multi_mess &
var_msi_en & x"0000"),
compl_status => var_compl_status
);
var_pass := check_compl_status(var_compl_status);
msi_allocated := var_multi_mess_en;
-- program all msi capability registers (64 and 32 bit!)
if var_msi_is_64b = "1" then -- 64bit addressing
-- set lower address where MSI will be written
ebfm_cfgwr_imm_wait(
bus_num => BUS_NUM,
dev_num => DEV_NUM,
fnc_num => FUNC_NUM,
regb_ad => (MSI_CAP_ADDR +4),
regb_ln => 4,
imm_data => var_msi_addr,
compl_status => var_compl_status
);
var_pass := check_compl_status(var_compl_status);
-- set upper address where MSI will be written
ebfm_cfgwr_imm_wait(
bus_num => BUS_NUM,
dev_num => DEV_NUM,
fnc_num => FUNC_NUM,
regb_ad => (MSI_CAP_ADDR +4),
regb_ln => 4,
imm_data => x"0000_0000",
compl_status => var_compl_status
);
var_pass := check_compl_status(var_compl_status);
-- set which data value shall be writen when endpoint issues MSI
ebfm_cfgwr_imm_wait(
bus_num => BUS_NUM,
dev_num => DEV_NUM,
fnc_num => FUNC_NUM,
regb_ad => (MSI_CAP_ADDR +12),
regb_ln => 4,
imm_data => x"0000" & msi_data,
compl_status => var_compl_status
);
var_pass := check_compl_status(var_compl_status);
else -- 32bit addressing
-- set lower address where MSI will be written
ebfm_cfgwr_imm_wait(
bus_num => BUS_NUM,
dev_num => DEV_NUM,
fnc_num => FUNC_NUM,
regb_ad => (MSI_CAP_ADDR +4),
regb_ln => 4,
imm_data => var_msi_addr,
compl_status => var_compl_status
);
var_pass := check_compl_status(var_compl_status);
-- set which data value shall be writen when endpoint issues MSI
ebfm_cfgwr_imm_wait(
bus_num => BUS_NUM,
dev_num => DEV_NUM,
fnc_num => FUNC_NUM,
regb_ad => (MSI_CAP_ADDR +8),
regb_ln => 4,
imm_data => x"0000" & msi_data,
compl_status => var_compl_status
);
var_pass := check_compl_status(var_compl_status);
end if;
-- clear MSI location in shared memory
shmem_write(msi_addr, x"FADE_FADE", 4);
success := var_pass;
end procedure;
procedure bfm_calc_msi_expected(
constant msi_allocated : in std_logic_vector(2 downto 0); -- amount of allocated MSI
constant msi_data : in std_logic_vector(15 downto 0); -- MSI data value as programmed to config space
constant msi_nbr : in integer range 32 downto 0;
variable msi_expected : out std_logic_vector(31 downto 0) -- MSI vector as expected from EP
) is
variable var_msi_expected : std_logic_vector(31 downto 0);
variable var_msi_nbr : std_logic_vector(4 downto 0) := (others => '0');
variable var_max_msi_allowed : integer range 32 downto 1 := 1;
begin
-- calculate MSI number
case msi_allocated is
when "000" =>
var_max_msi_allowed := 1;
when "001" =>
var_max_msi_allowed := 2;
when "010" =>
var_max_msi_allowed := 4;
when "011" =>
var_max_msi_allowed := 8;
when "100" =>
var_max_msi_allowed := 16;
when "101" =>
var_max_msi_allowed := 32;
when others =>
var_max_msi_allowed := 1;
end case;
-----------------------------------------------------------------------------
-- if we use more MSI than are allocated then wrap the number automatically
-----------------------------------------------------------------------------
var_msi_nbr := std_logic_vector(to_unsigned((msi_nbr mod var_max_msi_allowed),5));
if (msi_allocated = "000") then
var_msi_expected := x"0000" & msi_data(15 downto 0);
elsif (msi_allocated = "001") then
var_msi_expected := x"0000" & msi_data(15 downto 1) & var_msi_nbr(0 downto 0);
elsif (msi_allocated = "010") then
var_msi_expected := x"0000" & msi_data(15 downto 2) & var_msi_nbr(1 downto 0);
elsif (msi_allocated = "011") then
var_msi_expected := x"0000" & msi_data(15 downto 3) & var_msi_nbr(2 downto 0);
elsif (msi_allocated = "100") then
var_msi_expected := x"0000" & msi_data(15 downto 4) & var_msi_nbr(3 downto 0);
elsif (msi_allocated = "101") then
var_msi_expected := x"0000" & msi_data(15 downto 5) & var_msi_nbr(4 downto 0);
else
print_now("ERROR(bfm_calc_msi_expected): illegal value for multi message enable");
var_msi_expected := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
msi_expected := var_msi_expected;
end procedure;
procedure bfm_poll_msi(
constant track_msi : in natural;
constant msi_addr : in natural;
constant msi_expected : in std_logic_vector(31 downto 0);
constant txt_out : in integer;
success : out boolean
) is
constant POLLING_TIMEOUT : natural := 5 * 2048;
variable var_pass : boolean := true;
variable var_loop_val : natural range 1 downto 0 := 1;
variable var_poll_timer : natural := 0;
variable var_msi_received : std_logic_vector(15 downto 0) := (others => '0');
begin
var_pass := true;
track_msi_loop : for i in 1 to track_msi loop
if txt_out >=2 then print_s_i("bfm_poll_msi(): tracking MSI number: ", i); end if;
var_loop_val := 1;
while var_loop_val = 1 loop
wait for 10 ns;
--wait for 10 us;
var_poll_timer := var_poll_timer +1;
var_msi_received := (others => '0');
var_msi_received := shmem_read(msi_addr, 2);
if var_msi_received = msi_expected(15 downto 0) then
-- clear shared memory location and exit polling loop
shmem_write(msi_addr, x"FADE_FADE", 4);
var_loop_val := 0;
end if;
-- manage internal timeout
if var_poll_timer >= POLLING_TIMEOUT then
var_pass := false;
if txt_out >= 1 then
print_now("ERROR(bfm_poll_msi): no MSI captured within timeout time");
end if;
success := var_pass;
exit track_msi_loop;
end if;
end loop;
end loop track_msi_loop;
success := var_pass;
end procedure;
end package body pcie_sim_pkg;
|
gpl-3.0
|
0e9974cb13446df27b7cd912870e59f6
| 0.498279 | 4.017304 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_v_rgb2ycrcb_0_0/synth/tutorial_v_rgb2ycrcb_0_0.vhd
| 1 | 10,417 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:v_rgb2ycrcb:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY v_rgb2ycrcb_v7_1;
USE v_rgb2ycrcb_v7_1.v_rgb2ycrcb;
ENTITY tutorial_v_rgb2ycrcb_0_0 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
s_axis_video_tuser_sof : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
m_axis_video_tuser_sof : OUT STD_LOGIC
);
END tutorial_v_rgb2ycrcb_0_0;
ARCHITECTURE tutorial_v_rgb2ycrcb_0_0_arch OF tutorial_v_rgb2ycrcb_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_v_rgb2ycrcb_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT v_rgb2ycrcb IS
GENERIC (
C_S_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_S_AXIS_VIDEO_FORMAT : INTEGER;
C_S_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_FORMAT : INTEGER;
C_M_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
c_s_axi_addr_width : INTEGER;
c_s_axi_data_width : INTEGER;
C_HAS_AXI4_LITE : INTEGER;
C_HAS_DEBUG : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_MAX_COLS : INTEGER;
C_ACTIVE_COLS : INTEGER;
C_ACTIVE_ROWS : INTEGER;
C_HAS_CLIP : INTEGER;
C_HAS_CLAMP : INTEGER;
C_ACOEF : INTEGER;
C_BCOEF : INTEGER;
C_CCOEF : INTEGER;
C_DCOEF : INTEGER;
C_YOFFSET : INTEGER;
C_CBOFFSET : INTEGER;
C_CROFFSET : INTEGER;
C_YMAX : INTEGER;
C_YMIN : INTEGER;
C_CBMAX : INTEGER;
C_CBMIN : INTEGER;
C_CRMAX : INTEGER;
C_CRMIN : INTEGER;
C_S_AXI_CLK_FREQ_HZ : INTEGER;
C_FAMILY : STRING
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
intc_if : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
irq : OUT STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
s_axis_video_tuser_sof : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
m_axis_video_tuser_sof : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT v_rgb2ycrcb;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tutorial_v_rgb2ycrcb_0_0_arch: ARCHITECTURE IS "v_rgb2ycrcb,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tutorial_v_rgb2ycrcb_0_0_arch : ARCHITECTURE IS "tutorial_v_rgb2ycrcb_0_0,v_rgb2ycrcb,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tutorial_v_rgb2ycrcb_0_0_arch: ARCHITECTURE IS "tutorial_v_rgb2ycrcb_0_0,v_rgb2ycrcb,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=v_rgb2ycrcb,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXIS_VIDEO_DATA_WIDTH=8,C_S_AXIS_VIDEO_FORMAT=2,C_S_AXIS_VIDEO_TDATA_WIDTH=24,C_M_AXIS_VIDEO_DATA_WIDTH=8,C_M_AXIS_VIDEO_FORMAT=1,C_M_AXIS_VIDEO_TDATA_WIDTH=24,c_s_axi_addr_width=9,c_s_axi_data_width=32,C_HAS_AXI4_LITE=0,C_HAS_DEBUG=0,C_HAS_INTC_IF=0,C_MAX_COLS=1920,C_ACTIVE_COLS=1920,C_ACTIVE_ROWS=1080,C_HAS_CLIP=1,C_HAS_CLAMP=1,C_ACOEF=19595,C_BCOEF=7471,C_CCOEF=46727,C_DCOEF=36962,C_YOFFSET=16,C_CBOFFSET=128,C_CROFFSET=128,C_YMAX=240,C_YMIN=16,C_CBMAX=240,C_CBMIN=16,C_CRMAX=240,C_CRMIN=16,C_S_AXI_CLK_FREQ_HZ=100000000,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tuser_sof: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tuser_sof: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TUSER";
BEGIN
U0 : v_rgb2ycrcb
GENERIC MAP (
C_S_AXIS_VIDEO_DATA_WIDTH => 8,
C_S_AXIS_VIDEO_FORMAT => 2,
C_S_AXIS_VIDEO_TDATA_WIDTH => 24,
C_M_AXIS_VIDEO_DATA_WIDTH => 8,
C_M_AXIS_VIDEO_FORMAT => 1,
C_M_AXIS_VIDEO_TDATA_WIDTH => 24,
c_s_axi_addr_width => 9,
c_s_axi_data_width => 32,
C_HAS_AXI4_LITE => 0,
C_HAS_DEBUG => 0,
C_HAS_INTC_IF => 0,
C_MAX_COLS => 1920,
C_ACTIVE_COLS => 1920,
C_ACTIVE_ROWS => 1080,
C_HAS_CLIP => 1,
C_HAS_CLAMP => 1,
C_ACOEF => 19595,
C_BCOEF => 7471,
C_CCOEF => 46727,
C_DCOEF => 36962,
C_YOFFSET => 16,
C_CBOFFSET => 128,
C_CROFFSET => 128,
C_YMAX => 240,
C_YMIN => 16,
C_CBMAX => 240,
C_CBMIN => 16,
C_CRMAX => 240,
C_CRMIN => 16,
C_S_AXI_CLK_FREQ_HZ => 100000000,
C_FAMILY => "zynq"
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => aresetn,
s_axi_aclk => '0',
s_axi_aclken => '1',
s_axi_aresetn => '1',
s_axis_video_tdata => s_axis_video_tdata,
s_axis_video_tready => s_axis_video_tready,
s_axis_video_tvalid => s_axis_video_tvalid,
s_axis_video_tlast => s_axis_video_tlast,
s_axis_video_tuser_sof => s_axis_video_tuser_sof,
m_axis_video_tdata => m_axis_video_tdata,
m_axis_video_tvalid => m_axis_video_tvalid,
m_axis_video_tready => m_axis_video_tready,
m_axis_video_tlast => m_axis_video_tlast,
m_axis_video_tuser_sof => m_axis_video_tuser_sof,
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
s_axi_arvalid => '0',
s_axi_rready => '0'
);
END tutorial_v_rgb2ycrcb_0_0_arch;
|
gpl-2.0
|
5a97b154ca26b89764752d1d4cad52a4
| 0.671595 | 3.11141 | false | false | false | false |
straywarrior/MadeCPUin21days
|
InstMemoryControl.vhd
| 1 | 3,452 |
---------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 21:17:00 11/15/2015
-- Design Name:
-- Module Name: InstMemoryControl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InstMemoryControl is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
MemRead : in STD_LOGIC;
MemWrite: in STD_LOGIC;
MemAddr : in STD_LOGIC_VECTOR (15 downto 0);
MemData : in STD_LOGIC_VECTOR (15 downto 0);
MemOut : out STD_LOGIC_VECTOR (15 downto 0);
RAM2Addr : out STD_LOGIC_VECTOR (17 downto 0);
RAM2Data : inout STD_LOGIC_VECTOR (15 downto 0);
RAM2EN : out STD_LOGIC;
RAM2OE : out STD_LOGIC;
RAM2RW : out STD_LOGIC
);
end InstMemoryControl;
architecture Behavioral of InstMemoryControl is
type state_type is (s0, s1, s2, s3);
signal state : state_type;
begin
RAM2Addr(17 downto 16) <= (others => '0');
RAM2Addr(15 downto 0) <= MemAddr;
RAM2Data <=
(others => 'Z') when MemRead = '1' else
MemData when MemWrite = '1' else
(others => 'Z');
MemOut <= RAM2Data;
process (reset, clk)
begin
if (reset = '0') then
state <= s0;
RAM2EN <= '1';
RAM2OE <= '1';
RAM2RW <= '1';
elsif (clk'event and clk = '1') then
if (state = s0) then
state <= s1;
RAM2EN <= '0';
RAM2OE <= '1';
RAM2RW <= '1';
elsif (state = s1) then
state <= s2;
-- Read Memory (LW rx ry imm)
if (MemRead = '1' and MemAddr >= x"0000" and MemAddr <= x"7FFF") then
RAM2EN <= '0';
RAM2OE <= '0';
RAM2RW <= '1';
-- Write Memory (SW rx ry imm)
elsif (MemWrite = '1' and MemAddr >= x"0000" and MemAddr <= x"7FFF") then
RAM2EN <= '0';
RAM2OE <= '1';
RAM2RW <= '0';
end if;
elsif (state = s2) then
state <= s3;
-- Read Memory (LW rx ry imm)
if (MemRead = '1' and MemAddr >= x"0000" and MemAddr <= x"7FFF") then
RAM2EN <= '0';
RAM2OE <= '0';
RAM2RW <= '1';
-- Write Memory (SW rx ry imm)
elsif (MemWrite = '1' and MemAddr >= x"0000" and MemAddr <= x"7FFF") then
RAM2EN <= '0';
RAM2OE <= '1';
RAM2RW <= '1';
end if;
elsif (state = s3) then
state <= s0;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
2da0838642739f506732ccba55a60470
| 0.462341 | 4.075561 | false | false | false | false |
dominiklohmann/mikrorechner
|
vhdl/sram.vhd
| 1 | 5,657 |
-- sram.vhd ------------------------------------------------------
------------------------------------------------------------------------------
-- Andreas Maeder 01-feb-2007
-- -simulation model of a simple SRAM
-- -no timing !!
--
-- parameters addrWd -address width 2..32 [8]
-- dataWd -data with 2..32 [8]
-- fileID -filename [sram.dat]
--
-- package sramPkg
-- entity sram
-- architecture simModel
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- sramPkg ------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package sramPkg is
type fileIOty is (none, dump, load);
component sram is
generic ( addrWd : integer range 2 to 32 := 8; -- #address bits
dataWd : integer range 2 to 32 := 8; -- #data bits
fileId : string := "sram.dat"); -- filename
port ( nCS : in std_logic; -- not Chip Select
nWE : in std_logic; -- not Write Enable
nOE : in std_logic; -- not Output Enable
addr : in std_logic_vector(addrWd-1 downto 0);
data : inout std_logic_vector(dataWd-1 downto 0);
fileIO : in fileIOty := none);
end component sram;
end package sramPkg;
------------------------------------------------------------------------------
-- sram ------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.sramPkg.all;
entity sram is
generic ( addrWd : integer range 2 to 32 := 8; -- #address bits
dataWd : integer range 2 to 32 := 8; -- #data bits
fileId : string := "sram.dat"); -- filename
port ( nCS : in std_logic; -- not Chip Select
nWE : in std_logic; -- not Write Enable
nOE : in std_logic; -- not Output Enable
addr : in std_logic_vector(addrWd-1 downto 0);
data : inout std_logic_vector(dataWd-1 downto 0);
fileIO : in fileIOty := none);
end entity sram;
-- sram(simModel) ------------------------------------------------------
------------------------------------------------------------------------------
architecture simModel of sram is
begin
-- sram simulation model
----------------------------------------------------------------------------
sramP: process (nCS, nWE, nOE, addr, data, fileIO) is
constant addrHi : natural := (2**addrWd)-1;
subtype sramEleTy is std_logic_vector(dataWd-1 downto 0);
type sramMemTy is array (0 to addrHi) of sramEleTy;
variable sramMem : sramMemTy;
file ioFile : text;
variable ioLine : line;
variable ioStat : file_open_status;
variable rdStat : boolean;
variable ioAddr : integer range sramMem'range;
variable ioData : std_logic_vector(dataWd-1 downto 0);
begin
-- fileIO dump/load the SRAM contents into/from file
--------------------------------------------------------------------------
if fileIO'event then
if fileIO = dump then -- dump sramData ----------------------
file_open(ioStat, ioFile, fileID, write_mode);
assert ioStat = open_ok
report "SRAM - dump: error opening data file"
severity error;
for dAddr in sramMem'range loop
write(ioLine, dAddr); -- format line:
write(ioLine, ' '); -- <addr> <data>
write(ioLine, std_logic_vector(sramMem(dAddr)));
writeline(ioFile, ioLine); -- write line
end loop;
file_close(ioFile);
elsif fileIO = load then -- load sramData ----------------------
file_open(ioStat, ioFile, fileID, read_mode);
assert ioStat = open_ok
report "SRAM - load: error opening data file"
severity error;
while not endfile(ioFile) loop
readline(ioFile, ioLine); -- read line
read(ioLine, ioAddr, rdStat); -- read <addr>
if rdStat then -- <data>
read(ioLine, ioData, rdStat);
end if;
if rdStat then
sramMem(ioAddr) := ioData;
else
report "SRAM - load: format error in data file"
severity error;
end if;
end loop;
file_close(ioFile);
end if; -- fileIO = ...
end if; -- fileIO'event
-- consistency checks
------------------------------------------------------------------------
if nCS'event then assert not Is_X(nCS)
report "SRAM: nCS - X value"
severity warning;
end if;
if nWE'event then assert not Is_X(nWE)
report "SRAM: nWE - X value"
severity warning;
end if;
if nOE'event then assert not Is_X(nOE)
report "SRAM: nOE - X value"
severity warning;
end if;
if addr'event then assert not Is_X(addr)
report "SRAM: addr - X value"
severity warning;
end if;
-- if data'event then assert not Is_X(data)
-- report "SRAM: data - X value"
-- severity warning;
-- end if;
-- here starts the real work...
------------------------------------------------------------------------
data <= (others => 'Z'); -- output disabled
if nCS = '0' then -- chip enabled
if nWE = '0' then -- +write cycle
sramMem(to_integer(unsigned(addr))) := data;
elsif nWE = '1' and nOE ='0' then -- +read cycle
data <= sramMem(to_integer(unsigned(addr)));
end if; -- nWE = ...
end if; -- nCS = '0'
end process sramP;
end architecture simModel;
------------------------------------------------------------------------------
-- sram.vhd - end ------------------------------------------------------
|
mit
|
0cbde1738f330fffe5581ce0af7ef249
| 0.487007 | 3.82747 | false | false | false | false |
straywarrior/MadeCPUin21days
|
InstDecoder_Test.vhd
| 1 | 8,562 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:33:51 11/14/2015
-- Design Name:
-- Module Name: InstDecoder_Test
-- Project Name: MadeCPUin21days
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: InstDecoder
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY InstDecoder_Test IS
END InstDecoder_Test;
ARCHITECTURE behavior OF InstDecoder_Test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT InstDecoder
PORT(
pc : IN std_logic_vector(15 downto 0);
inst : IN std_logic_vector(15 downto 0);
RegAVal : IN std_logic_vector(15 downto 0);
RegBVal : IN std_logic_vector(15 downto 0);
RAVal : IN std_logic_vector(15 downto 0);
SPVal : IN std_logic_vector(15 downto 0);
IHVal : IN std_logic_vector(15 downto 0);
pc_imm : OUT std_logic_vector(15 downto 0);
pc_sel : OUT std_logic_vector(1 downto 0);
T_in : in STD_LOGIC;
T_out : out STD_LOGIC;
CReg : OUT std_logic;
CRegA : OUT std_logic_vector(3 downto 0);
CRegB : OUT std_logic_vector(3 downto 0);
RegWE : OUT std_logic;
RegDest : OUT std_logic_vector(3 downto 0);
MemRd : OUT std_logic;
MemDIn : OUT std_logic_vector(15 downto 0);
MemWE : OUT std_logic;
opcode : OUT std_logic_vector(3 downto 0);
RegOpA : OUT std_logic_vector(3 downto 0);
RegOpB : OUT std_logic_vector(3 downto 0);
operandA : OUT std_logic_vector(15 downto 0);
operandB : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT T_REG
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
T_in : in STD_LOGIC;
T_out : out STD_LOGIC
);
END COMPONENT;
--Inputs
signal pc : std_logic_vector(15 downto 0) := (others => '0');
signal inst : std_logic_vector(15 downto 0) := (others => '0');
signal RegAVal : std_logic_vector(15 downto 0) := (others => '0');
signal RegBVal : std_logic_vector(15 downto 0) := (others => '0');
signal RAVal : std_logic_vector(15 downto 0) := (others => '0');
signal SPVal : std_logic_vector(15 downto 0) := (others => '0');
signal IHVal : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal pc_imm : std_logic_vector(15 downto 0);
signal pc_sel : std_logic_vector(1 downto 0);
signal RegWE : std_logic;
signal RegDest : std_logic_vector(3 downto 0);
signal MemRd : std_logic;
signal MemDIn : std_logic_vector(15 downto 0);
signal MemWE : std_logic;
signal opcode : std_logic_vector(3 downto 0);
signal CReg : std_logic;
signal CRegA : std_logic_vector(3 downto 0);
signal CRegB : std_logic_vector(3 downto 0);
signal RegOpA : std_logic_vector(3 downto 0);
signal RegOpB : std_logic_vector(3 downto 0);
signal operandA : std_logic_vector(15 downto 0);
signal operandB : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace clock below with
-- appropriate port name
signal clock : std_logic;
constant clock_period : time := 50 ns;
signal reset : std_logic;
--Medium Line
signal T_REG_out : std_logic;
signal T_REG_in : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: InstDecoder PORT MAP (
pc => pc,
inst => inst,
RegAVal => RegAVal,
RegBVal => RegBVal,
RAVal => RAVal,
SPVal => SPVal,
IHVal => IHVal,
pc_imm => pc_imm,
pc_sel => pc_sel,
RegWE => RegWE,
RegDest => RegDest,
MemRd => MemRd,
MemDIn => MemDIn,
MemWE => MemWE,
opcode => opcode,
RegOpA => RegOpA,
RegOpB => RegOpB,
operandA => operandA,
operandB => operandB,
CReg => CReg,
CRegA => CRegA,
CRegB => CRegB,
T_in => T_REG_out,
T_out => T_REG_in
);
t_reg_0 : T_REG PORT MAP(
clock, reset, T_REG_in, T_REG_out
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 25 ns;
reset <= '0';
wait for 75 ns;
-- LI R0 x"FF"
inst <= "0110100011111111";
wait for clock_period;
-- SW R0 R1 1
inst <= "1101100000100001";
wait for clock_period;
-- R Type
-- ADDU
inst <= "1110000101001101";
wait for clock_period;
-- SUBU
inst <= "1110011101100111";
wait for clock_period;
-- SLT
inst <= "1110100101100010";
wait for clock_period;
-- SLTU
inst <= "1110101101000011";
wait for clock_period;
-- SLLV
inst <= "1110100101000100";
wait for clock_period;
-- SRLV
inst <= "1110110101100110";
wait for clock_period;
-- SRAV
inst <= "1110110000100111";
wait for clock_period;
-- CMP
inst <= "1110101010101010";
wait for clock_period;
-- NEG
inst <= "1110101010101011";
wait for clock_period;
-- AND
inst <= "1110101010101100";
wait for clock_period;
-- OR
inst <= "1110101010101101";
wait for clock_period;
-- XOR
inst <= "1110101010101110";
wait for clock_period;
-- NOT
inst <= "1110101010101111";
wait for clock_period;
-- MFPC
inst <= "1110101001000000";
wait for clock_period;
-- MFIH
inst <= "1111001100000000";
wait for clock_period;
-- MTIH
inst <= "1111000100000001";
wait for clock_period;
-- SLL
inst <= "0011000101001000";
wait for clock_period;
-- SRA
inst <= "0011001011011010";
wait for clock_period;
-- SRA
inst <= "0011000101001011";
wait for clock_period;
-- MOVE
inst <= "0111101100100000";
wait for clock_period;
-- MTSP
inst <= "0110010000100000";
wait for clock_period;
-- I Type
-- ADDSP3
inst <= "0000001000100001";
wait for clock_period;
-- ADDIU3
inst <= "0100001000100001";
wait for clock_period;
-- ADDIU
inst <= "0100100100100010";
wait for clock_period;
-- SLTI
inst <= "0101001000100011";
wait for clock_period;
-- SLTUI
inst <= "0101100100100100";
wait for clock_period;
-- SW_RS
inst <= "0110001000100101";
wait for clock_period;
-- ADDSP
inst <= "0110001100100110";
wait for clock_period;
-- LI
inst <= "0110100100100111";
wait for clock_period;
-- CMPI
inst <= "0111001000101000";
wait for clock_period;
-- LW_SP
inst <= "1001001100101001";
wait for clock_period;
-- LW
inst <= "1001110000101010";
wait for clock_period;
-- SW_SP
inst <= "1101010100101011";
wait for clock_period;
-- SW
inst <= "1101111000101100";
wait for clock_period;
-- B Type
-- B
inst <= "0001010000101101";
wait for clock_period;
-- BEQZ
inst <= "0010000100101110";
wait for clock_period;
-- BNEZ
inst <= "0010110000101111";
wait for clock_period;
-- BTEQZ
inst <= "0110000000110000";
wait for clock_period;
-- BTNEZ
inst <= "0110000100110001";
wait for clock_period;
-- J Type
-- JR
inst <= "1110101000000000";
wait for clock_period;
-- JRRA
inst <= "1110100000100000";
wait for clock_period;
-- JALR
inst <= "1110101111000000";
wait for clock_period;
-- INT
inst <= "1111100000000000";
wait for clock_period;
-- NOP
inst <= "0000100000000000";
wait for clock_period;
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
f77d8536b5be22992d267c81e4bedd62
| 0.585144 | 3.631043 | false | false | false | false |
Ttl/bf_cpu
|
stack.vhd
| 1 | 1,251 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.bfconfig.all;
-- Stack used to store PC for jumps
entity stack is
Port ( clk, reset : in STD_LOGIC;
enable : in STD_LOGIC;
push_notpop : in STD_LOGIC;
pcin : in pctype;
pcout : out pctype);
end stack;
architecture Behavioral of stack is
type stacktype is array(0 to 2**STACK_SIZE-1) of pctype;
signal mem : stacktype;
signal async_read : pctype;
signal enable_delay : std_logic;
signal mem_out : pctype;
begin
process(clk, reset, push_notpop, enable, pcin, mem)
variable pointer : unsigned(STACK_SIZE-1 downto 0);
begin
if reset = '1' then
pointer := to_unsigned(0, STACK_SIZE);
elsif rising_edge(clk) then
enable_delay <= enable;
if enable = '1' then
if push_notpop = '1' then
-- Push
pointer := pointer + 1;
mem(to_integer(pointer)) <= pcin;
async_read <= pcin;
else
-- Pop
pointer := pointer - 1;
end if;
end if;
mem_out <= mem(to_integer(pointer));
end if;
end process;
pcout <= async_read when enable_delay = '1' else mem_out;
end Behavioral;
|
lgpl-3.0
|
386de5da0fe2b430ead17a7ca6379e6e
| 0.585931 | 3.594828 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_multiplier.vhd
| 2 | 2,359 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_multiplier is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "AUTO";
SIGNED : natural := 0;
OUTPUTMSB : integer := 8;
AWIDTH : natural := 8;
BWIDTH : natural := 8;
OUTPUTLSB : integer := 0;
PIPELINE : integer := 0
);
port (
user_aclr : in std_logic;
result : out std_logic_vector(OutputMsb-OutputLsb+1-1 downto 0);
clock : in std_logic;
dataa : in std_logic_vector(aWidth-1 downto 0);
datab : in std_logic_vector(bWidth-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_multiplier;
architecture rtl of alt_dspbuilder_multiplier is
component alt_dspbuilder_multiplier_GNEIWYOKUR is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "YES";
SIGNED : natural := 0;
OUTPUTMSB : integer := 47;
AWIDTH : natural := 24;
BWIDTH : natural := 24;
OUTPUTLSB : integer := 0;
PIPELINE : integer := 0
);
port (
aclr : in std_logic;
clock : in std_logic;
dataa : in std_logic_vector(24-1 downto 0);
datab : in std_logic_vector(24-1 downto 0);
ena : in std_logic;
result : out std_logic_vector(48-1 downto 0);
user_aclr : in std_logic
);
end component alt_dspbuilder_multiplier_GNEIWYOKUR;
begin
alt_dspbuilder_multiplier_GNEIWYOKUR_0: if ((DEDICATED_MULTIPLIER_CIRCUITRY = "YES") and (SIGNED = 0) and (OUTPUTMSB = 47) and (AWIDTH = 24) and (BWIDTH = 24) and (OUTPUTLSB = 0) and (PIPELINE = 0)) generate
inst_alt_dspbuilder_multiplier_GNEIWYOKUR_0: alt_dspbuilder_multiplier_GNEIWYOKUR
generic map(DEDICATED_MULTIPLIER_CIRCUITRY => "YES", SIGNED => 0, OUTPUTMSB => 47, AWIDTH => 24, BWIDTH => 24, OUTPUTLSB => 0, PIPELINE => 0)
port map(aclr => aclr, clock => clock, dataa => dataa, datab => datab, ena => ena, result => result, user_aclr => user_aclr);
end generate;
assert not (((DEDICATED_MULTIPLIER_CIRCUITRY = "YES") and (SIGNED = 0) and (OUTPUTMSB = 47) and (AWIDTH = 24) and (BWIDTH = 24) and (OUTPUTLSB = 0) and (PIPELINE = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
86ba5768205d280585622cbac7946ebc
| 0.694362 | 3.399135 | false | false | false | false |
freecores/t48
|
rtl/vhdl/t48_core.vhd
| 1 | 23,793 |
-------------------------------------------------------------------------------
--
-- T48 Microcontroller Core
--
-- $Id: t48_core.vhd,v 1.12 2006-07-14 01:12:08 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2004, 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-- Limitations :
-- =============
--
-- Compared to the original MCS-48 architecture, the following limitations
-- apply:
--
-- * Single-step mode not implemented.
-- Not selected for future implementation.
--
-- * Reading of internal Program Memory not implemented.
-- Not selected for future implementation.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t48_core is
generic (
-- divide XTAL1 by 3 to derive Clock States
xtal_div_3_g : integer := 1;
-- store mnemonic in flip-flops (registered-out)
register_mnemonic_g : integer := 1;
-- include the port 1 module
include_port1_g : integer := 1;
-- include the port 2 module
include_port2_g : integer := 1;
-- include the BUS module
include_bus_g : integer := 1;
-- include the timer module
include_timer_g : integer := 1;
-- state in which T1 is sampled (3 or 4)
sample_t1_state_g : integer := 4
);
port (
-- T48 Interface ----------------------------------------------------------
xtal_i : in std_logic;
xtal_en_i : in std_logic;
reset_i : in std_logic;
t0_i : in std_logic;
t0_o : out std_logic;
t0_dir_o : out std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_i : in std_logic_vector( 7 downto 0);
db_o : out std_logic_vector( 7 downto 0);
db_dir_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 7 downto 0);
p2_o : out std_logic_vector( 7 downto 0);
p2l_low_imp_o : out std_logic;
p2h_low_imp_o : out std_logic;
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p1_low_imp_o : out std_logic;
prog_n_o : out std_logic;
-- Core Interface ---------------------------------------------------------
clk_i : in std_logic;
en_clk_i : in std_logic;
xtal3_o : out std_logic;
dmem_addr_o : out std_logic_vector( 7 downto 0);
dmem_we_o : out std_logic;
dmem_data_i : in std_logic_vector( 7 downto 0);
dmem_data_o : out std_logic_vector( 7 downto 0);
pmem_addr_o : out std_logic_vector(11 downto 0);
pmem_data_i : in std_logic_vector( 7 downto 0)
);
end t48_core;
use work.t48_alu_pack.alu_op_t;
use work.t48_cond_branch_pack.branch_conditions_t;
use work.t48_cond_branch_pack.comp_value_t;
use work.t48_dmem_ctrl_pack.dmem_addr_ident_t;
use work.t48_pmem_ctrl_pack.pmem_addr_ident_t;
use work.t48_comp_pack.all;
use work.t48_pack.bus_idle_level_c;
use work.t48_pack.word_t;
use work.t48_pack.pmem_addr_t;
use work.t48_pack.mstate_t;
use work.t48_pack.to_stdLogic;
use work.t48_pack.to_boolean;
architecture struct of t48_core is
signal t48_data_s : word_t;
signal xtal_en_s : boolean;
signal en_clk_s : boolean;
-- ALU signals
signal alu_data_s : word_t;
signal alu_write_accu_s : boolean;
signal alu_write_shadow_s : boolean;
signal alu_write_temp_reg_s : boolean;
signal alu_read_alu_s : boolean;
signal alu_carry_s : std_logic;
signal alu_aux_carry_s : std_logic;
signal alu_op_s : alu_op_t;
signal alu_use_carry_s : boolean;
signal alu_da_high_s : boolean;
signal alu_da_overflow_s : boolean;
signal alu_accu_low_s : boolean;
signal alu_p06_temp_reg_s : boolean;
signal alu_p60_temp_reg_s : boolean;
-- BUS signals
signal bus_write_bus_s : boolean;
signal bus_read_bus_s : boolean;
signal bus_output_pcl_s : boolean;
signal bus_bidir_bus_s : boolean;
signal bus_data_s : word_t;
-- Clock Controller signals
signal clk_multi_cycle_s : boolean;
signal clk_assert_psen_s : boolean;
signal clk_assert_prog_s : boolean;
signal clk_assert_rd_s : boolean;
signal clk_assert_wr_s : boolean;
signal clk_mstate_s : mstate_t;
signal clk_second_cycle_s : boolean;
signal psen_s : boolean;
signal prog_s : boolean;
signal rd_s : boolean;
signal wr_s : boolean;
signal ale_s : boolean;
signal xtal3_s : boolean;
-- Conditional Branch Logic signals
signal cnd_compute_take_s : boolean;
signal cnd_branch_cond_s : branch_conditions_t;
signal cnd_take_branch_s : boolean;
signal cnd_comp_value_s : comp_value_t;
signal cnd_f1_s : std_logic;
signal cnd_tf_s : std_logic;
-- Data Memory Controller signals
signal dm_write_dmem_addr_s : boolean;
signal dm_write_dmem_s : boolean;
signal dm_read_dmem_s : boolean;
signal dm_addr_type_s : dmem_addr_ident_t;
signal dm_data_s : word_t;
-- Decoder signals
signal dec_data_s : word_t;
-- Port 1 signals
signal p1_write_p1_s : boolean;
signal p1_read_p1_s : boolean;
signal p1_read_reg_s : boolean;
signal p1_data_s : word_t;
-- Port 2 signals
signal p2_write_p2_s : boolean;
signal p2_write_exp_s : boolean;
signal p2_read_p2_s : boolean;
signal p2_read_reg_s : boolean;
signal p2_read_exp_s : boolean;
signal p2_output_pch_s : boolean;
signal p2_data_s : word_t;
-- Program Memory Controller signals
signal pm_write_pcl_s : boolean;
signal pm_read_pcl_s : boolean;
signal pm_write_pch_s : boolean;
signal pm_read_pch_s : boolean;
signal pm_read_pmem_s : boolean;
signal pm_inc_pc_s : boolean;
signal pm_write_pmem_addr_s : boolean;
signal pm_data_s : word_t;
signal pm_addr_type_s : pmem_addr_ident_t;
signal pmem_addr_s : pmem_addr_t;
-- PSW signals
signal psw_read_psw_s : boolean;
signal psw_read_sp_s : boolean;
signal psw_write_psw_s : boolean;
signal psw_write_sp_s : boolean;
signal psw_carry_s : std_logic;
signal psw_aux_carry_s : std_logic;
signal psw_f0_s : std_logic;
signal psw_bs_s : std_logic;
signal psw_special_data_s : std_logic;
signal psw_inc_stackp_s : boolean;
signal psw_dec_stackp_s : boolean;
signal psw_write_carry_s : boolean;
signal psw_write_aux_carry_s : boolean;
signal psw_write_f0_s : boolean;
signal psw_write_bs_s : boolean;
signal psw_data_s : word_t;
-- Timer signals
signal tim_overflow_s : boolean;
signal tim_of_s : std_logic;
signal tim_read_timer_s : boolean;
signal tim_write_timer_s : boolean;
signal tim_start_t_s : boolean;
signal tim_start_cnt_s : boolean;
signal tim_stop_tcnt_s : boolean;
signal tim_data_s : word_t;
begin
-----------------------------------------------------------------------------
-- Check generics for valid values.
-----------------------------------------------------------------------------
-- pragma translate_off
assert include_timer_g = 0 or include_timer_g = 1
report "include_timer_g must be either 1 or 0!"
severity failure;
assert include_port1_g = 0 or include_port1_g = 1
report "include_port1_g must be either 1 or 0!"
severity failure;
assert include_port2_g = 0 or include_port2_g = 1
report "include_port2_g must be either 1 or 0!"
severity failure;
assert include_bus_g = 0 or include_bus_g = 1
report "include_bus_g must be either 1 or 0!"
severity failure;
-- pragma translate_on
xtal_en_s <= to_boolean(xtal_en_i);
en_clk_s <= to_boolean(en_clk_i);
alu_b : t48_alu
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
data_o => alu_data_s,
write_accu_i => alu_write_accu_s,
write_shadow_i => alu_write_shadow_s,
write_temp_reg_i => alu_write_temp_reg_s,
read_alu_i => alu_read_alu_s,
carry_i => psw_carry_s,
carry_o => alu_carry_s,
aux_carry_o => alu_aux_carry_s,
alu_op_i => alu_op_s,
use_carry_i => alu_use_carry_s,
da_high_i => alu_da_high_s,
da_overflow_o => alu_da_overflow_s,
accu_low_i => alu_accu_low_s,
p06_temp_reg_i => alu_p06_temp_reg_s,
p60_temp_reg_i => alu_p60_temp_reg_s
);
bus_mux_b : t48_bus_mux
port map (
alu_data_i => alu_data_s,
bus_data_i => bus_data_s,
dec_data_i => dec_data_s,
dm_data_i => dm_data_s,
pm_data_i => pm_data_s,
p1_data_i => p1_data_s,
p2_data_i => p2_data_s,
psw_data_i => psw_data_s,
tim_data_i => tim_data_s,
data_o => t48_data_s
);
clock_ctrl_b : t48_clock_ctrl
generic map (
xtal_div_3_g => xtal_div_3_g
)
port map (
clk_i => clk_i,
xtal_i => xtal_i,
xtal_en_i => xtal_en_s,
res_i => reset_i,
en_clk_i => en_clk_s,
xtal3_o => xtal3_s,
t0_o => t0_o,
multi_cycle_i => clk_multi_cycle_s,
assert_psen_i => clk_assert_psen_s,
assert_prog_i => clk_assert_prog_s,
assert_rd_i => clk_assert_rd_s,
assert_wr_i => clk_assert_wr_s,
mstate_o => clk_mstate_s,
second_cycle_o => clk_second_cycle_s,
ale_o => ale_s,
psen_o => psen_s,
prog_o => prog_s,
rd_o => rd_s,
wr_o => wr_s
);
cond_branch_b : t48_cond_branch
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
compute_take_i => cnd_compute_take_s,
branch_cond_i => cnd_branch_cond_s,
take_branch_o => cnd_take_branch_s,
accu_i => alu_data_s,
t0_i => To_X01Z(t0_i),
t1_i => To_X01Z(t1_i),
int_n_i => int_n_i,
f0_i => psw_f0_s,
f1_i => cnd_f1_s,
tf_i => cnd_tf_s,
carry_i => psw_carry_s,
comp_value_i => cnd_comp_value_s
);
use_db_bus: if include_bus_g = 1 generate
db_bus_b : t48_db_bus
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
ea_i => ea_i,
data_i => t48_data_s,
data_o => bus_data_s,
write_bus_i => bus_write_bus_s,
read_bus_i => bus_read_bus_s,
output_pcl_i => bus_output_pcl_s,
bidir_bus_i => bus_bidir_bus_s,
pcl_i => pmem_addr_s(word_t'range),
db_i => db_i,
db_o => db_o,
db_dir_o => db_dir_o
);
end generate;
skip_db_bus: if include_bus_g = 0 generate
bus_data_s <= (others => bus_idle_level_c);
db_o <= (others => '0');
db_dir_o <= '0';
end generate;
decoder_b : t48_decoder
generic map (
register_mnemonic_g => register_mnemonic_g
)
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
xtal_i => xtal_i,
xtal_en_i => xtal_en_s,
ea_i => ea_i,
ale_i => ale_s,
int_n_i => int_n_i,
t0_dir_o => t0_dir_o,
data_i => t48_data_s,
data_o => dec_data_s,
alu_write_accu_o => alu_write_accu_s,
alu_write_shadow_o => alu_write_shadow_s,
alu_write_temp_reg_o => alu_write_temp_reg_s,
alu_read_alu_o => alu_read_alu_s,
bus_write_bus_o => bus_write_bus_s,
bus_read_bus_o => bus_read_bus_s,
dm_write_dmem_addr_o => dm_write_dmem_addr_s,
dm_write_dmem_o => dm_write_dmem_s,
dm_read_dmem_o => dm_read_dmem_s,
p1_write_p1_o => p1_write_p1_s,
p1_read_p1_o => p1_read_p1_s,
pm_write_pcl_o => pm_write_pcl_s,
p2_write_p2_o => p2_write_p2_s,
p2_write_exp_o => p2_write_exp_s,
p2_read_p2_o => p2_read_p2_s,
pm_read_pcl_o => pm_read_pcl_s,
pm_write_pch_o => pm_write_pch_s,
pm_read_pch_o => pm_read_pch_s,
pm_read_pmem_o => pm_read_pmem_s,
psw_read_psw_o => psw_read_psw_s,
psw_read_sp_o => psw_read_sp_s,
psw_write_psw_o => psw_write_psw_s,
psw_write_sp_o => psw_write_sp_s,
alu_carry_i => alu_carry_s,
alu_op_o => alu_op_s,
alu_use_carry_o => alu_use_carry_s,
alu_da_high_o => alu_da_high_s,
alu_da_overflow_i => alu_da_overflow_s,
alu_accu_low_o => alu_accu_low_s,
alu_p06_temp_reg_o => alu_p06_temp_reg_s,
alu_p60_temp_reg_o => alu_p60_temp_reg_s,
bus_output_pcl_o => bus_output_pcl_s,
bus_bidir_bus_o => bus_bidir_bus_s,
clk_multi_cycle_o => clk_multi_cycle_s,
clk_assert_psen_o => clk_assert_psen_s,
clk_assert_prog_o => clk_assert_prog_s,
clk_assert_rd_o => clk_assert_rd_s,
clk_assert_wr_o => clk_assert_wr_s,
clk_mstate_i => clk_mstate_s,
clk_second_cycle_i => clk_second_cycle_s,
cnd_compute_take_o => cnd_compute_take_s,
cnd_branch_cond_o => cnd_branch_cond_s,
cnd_take_branch_i => cnd_take_branch_s,
cnd_comp_value_o => cnd_comp_value_s,
cnd_f1_o => cnd_f1_s,
cnd_tf_o => cnd_tf_s,
dm_addr_type_o => dm_addr_type_s,
tim_read_timer_o => tim_read_timer_s,
tim_write_timer_o => tim_write_timer_s,
tim_start_t_o => tim_start_t_s,
tim_start_cnt_o => tim_start_cnt_s,
tim_stop_tcnt_o => tim_stop_tcnt_s,
p1_read_reg_o => p1_read_reg_s,
p2_read_reg_o => p2_read_reg_s,
p2_read_exp_o => p2_read_exp_s,
p2_output_pch_o => p2_output_pch_s,
pm_inc_pc_o => pm_inc_pc_s,
pm_write_pmem_addr_o => pm_write_pmem_addr_s,
pm_addr_type_o => pm_addr_type_s,
psw_special_data_o => psw_special_data_s,
psw_carry_i => psw_carry_s,
psw_aux_carry_i => psw_aux_carry_s,
psw_f0_i => psw_f0_s,
psw_inc_stackp_o => psw_inc_stackp_s,
psw_dec_stackp_o => psw_dec_stackp_s,
psw_write_carry_o => psw_write_carry_s,
psw_write_aux_carry_o => psw_write_aux_carry_s,
psw_write_f0_o => psw_write_f0_s,
psw_write_bs_o => psw_write_bs_s,
tim_overflow_i => tim_overflow_s
);
dmem_ctrl_b : t48_dmem_ctrl
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
write_dmem_addr_i => dm_write_dmem_addr_s,
write_dmem_i => dm_write_dmem_s,
read_dmem_i => dm_read_dmem_s,
addr_type_i => dm_addr_type_s,
bank_select_i => psw_bs_s,
data_o => dm_data_s,
dmem_data_i => dmem_data_i,
dmem_addr_o => dmem_addr_o,
dmem_we_o => dmem_we_o,
dmem_data_o => dmem_data_o
);
use_timer: if include_timer_g = 1 generate
timer_b : t48_timer
generic map (
sample_t1_state_g => sample_t1_state_g
)
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
t1_i => To_X01Z(t1_i),
clk_mstate_i => clk_mstate_s,
data_i => t48_data_s,
data_o => tim_data_s,
read_timer_i => tim_read_timer_s,
write_timer_i => tim_write_timer_s,
start_t_i => tim_start_t_s,
start_cnt_i => tim_start_cnt_s,
stop_tcnt_i => tim_stop_tcnt_s,
overflow_o => tim_of_s
);
end generate;
skip_timer: if include_timer_g = 0 generate
tim_data_s <= (others => bus_idle_level_c);
tim_of_s <= '0';
end generate;
tim_overflow_s <= to_boolean(tim_of_s);
use_p1: if include_port1_g = 1 generate
p1_b : t48_p1
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
data_o => p1_data_s,
write_p1_i => p1_write_p1_s,
read_p1_i => p1_read_p1_s,
read_reg_i => p1_read_reg_s,
p1_i => p1_i,
p1_o => p1_o,
p1_low_imp_o => p1_low_imp_o
);
end generate;
skip_p1: if include_port1_g = 0 generate
p1_data_s <= (others => bus_idle_level_c);
p1_o <= (others => '0');
p1_low_imp_o <= '0';
end generate;
use_p2: if include_port2_g = 1 generate
p2_b : t48_p2
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
xtal_i => xtal_i,
xtal_en_i => xtal_en_s,
data_i => t48_data_s,
data_o => p2_data_s,
write_p2_i => p2_write_p2_s,
write_exp_i => p2_write_exp_s,
read_p2_i => p2_read_p2_s,
read_reg_i => p2_read_reg_s,
read_exp_i => p2_read_exp_s,
output_pch_i => p2_output_pch_s,
pch_i => pmem_addr_s(11 downto 8),
p2_i => p2_i,
p2_o => p2_o,
p2l_low_imp_o => p2l_low_imp_o,
p2h_low_imp_o => p2h_low_imp_o
);
end generate;
skip_p2: if include_port2_g = 0 generate
p2_data_s <= (others => bus_idle_level_c);
p2_o <= (others => '0');
p2l_low_imp_o <= '0';
p2h_low_imp_o <= '0';
end generate;
pmem_ctrl_b : t48_pmem_ctrl
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
data_o => pm_data_s,
write_pcl_i => pm_write_pcl_s,
read_pcl_i => pm_read_pcl_s,
write_pch_i => pm_write_pch_s,
read_pch_i => pm_read_pch_s,
inc_pc_i => pm_inc_pc_s,
write_pmem_addr_i => pm_write_pmem_addr_s,
addr_type_i => pm_addr_type_s,
read_pmem_i => pm_read_pmem_s,
pmem_addr_o => pmem_addr_s,
pmem_data_i => pmem_data_i
);
psw_b : t48_psw
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
data_o => psw_data_s,
read_psw_i => psw_read_psw_s,
read_sp_i => psw_read_sp_s,
write_psw_i => psw_write_psw_s,
write_sp_i => psw_write_sp_s,
special_data_i => psw_special_data_s,
inc_stackp_i => psw_inc_stackp_s,
dec_stackp_i => psw_dec_stackp_s,
write_carry_i => psw_write_carry_s,
write_aux_carry_i => psw_write_aux_carry_s,
write_f0_i => psw_write_f0_s,
write_bs_i => psw_write_bs_s,
carry_o => psw_carry_s,
aux_carry_i => alu_aux_carry_s,
aux_carry_o => psw_aux_carry_s,
f0_o => psw_f0_s,
bs_o => psw_bs_s
);
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
ale_o <= to_stdLogic(ale_s);
psen_n_o <= to_stdLogic(not psen_s);
prog_n_o <= to_stdLogic(not prog_s);
rd_n_o <= to_stdLogic(not rd_s);
wr_n_o <= to_stdLogic(not wr_s);
xtal3_o <= to_stdLogic(xtal3_s);
pmem_addr_o <= pmem_addr_s;
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.11 2006/06/20 00:46:04 arniml
-- new input xtal_en_i
--
-- Revision 1.10 2005/11/01 21:32:58 arniml
-- wire signals for P2 low impeddance marker issue
--
-- Revision 1.9 2005/06/11 10:08:43 arniml
-- introduce prefix 't48_' for all packages, entities and configurations
--
-- Revision 1.8 2005/05/04 20:12:37 arniml
-- Fix bug report:
-- "Wrong clock applied to T0"
-- t0_o is generated inside clock_ctrl with a separate flip-flop running
-- with xtal_i
--
-- Revision 1.7 2004/05/01 11:58:04 arniml
-- update notice about expander port instructions
--
-- Revision 1.6 2004/04/07 22:09:03 arniml
-- remove unused signals
--
-- Revision 1.5 2004/04/04 14:18:53 arniml
-- add measures to implement XCHD
--
-- Revision 1.4 2004/03/29 19:39:58 arniml
-- rename pX_limp to pX_low_imp
--
-- Revision 1.3 2004/03/28 21:27:50 arniml
-- update wiring for DA support
--
-- Revision 1.2 2004/03/28 13:13:20 arniml
-- connect control signal for Port 2 expander
--
-- Revision 1.1 2004/03/23 21:31:53 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
gpl-2.0
|
db9df8921422a44ccaad2aa24cb30a94
| 0.515362 | 3.022485 | false | false | false | false |
freecores/t48
|
rtl/vhdl/t8243/t8243.vhd
| 1 | 4,980 |
-------------------------------------------------------------------------------
--
-- The T8243 asynchronous toplevel
--
-- $Id: t8243.vhd,v 1.1 2006-07-13 22:53:56 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t8243 is
port (
-- Control Interface ------------------------------------------------------
cs_n_i : in std_logic;
prog_n_i : in std_logic;
-- Port 2 Interface -------------------------------------------------------
p2_b : inout std_logic_vector(3 downto 0);
-- Port 4 Interface -------------------------------------------------------
p4_b : inout std_logic_vector(3 downto 0);
-- Port 5 Interface -------------------------------------------------------
p5_b : inout std_logic_vector(3 downto 0);
-- Port 6 Interface -------------------------------------------------------
p6_b : inout std_logic_vector(3 downto 0);
-- Port 7 Interface -------------------------------------------------------
p7_b : inout std_logic_vector(3 downto 0)
);
end t8243;
use work.t8243_comp_pack.t8243_async_notri;
architecture struct of t8243 is
signal p2_s,
p4_s,
p5_s,
p6_s,
p7_s : std_logic_vector(3 downto 0);
signal p2_en_s,
p4_en_s,
p5_en_s,
p6_en_s,
p7_en_s : std_logic;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
-----------------------------------------------------------------------------
-- The asynchronous T8243
-----------------------------------------------------------------------------
t8243_async_notri_b : t8243_async_notri
port map (
reset_n_i => vdd_s, -- or generate power-on reset
cs_n_i => cs_n_i,
prog_n_i => prog_n_i,
p2_i => p2_b,
p2_o => p2_s,
p2_en_o => p2_en_s,
p4_i => p4_b,
p4_o => p4_s,
p4_en_o => p4_en_s,
p5_i => p5_b,
p5_o => p5_s,
p5_en_o => p5_en_s,
p6_i => p6_b,
p6_o => p6_s,
p6_en_o => p6_en_s,
p7_i => p7_b,
p7_o => p7_s,
p7_en_o => p7_en_s
);
-----------------------------------------------------------------------------
-- Bidirectional pad structures
-----------------------------------------------------------------------------
p2_b <= p2_s
when p2_en_s = '1' else
(others => 'Z');
p4_b <= p4_s
when p4_en_s = '1' else
(others => 'Z');
p5_b <= p5_s
when p5_en_s = '1' else
(others => 'Z');
p6_b <= p6_s
when p6_en_s = '1' else
(others => 'Z');
p7_b <= p7_s
when p7_en_s = '1' else
(others => 'Z');
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
gpl-2.0
|
93310bedcb87cf93cbf5ca2b55188fc9
| 0.487751 | 3.984 | false | false | false | false |
Bourgeoisie/ECE368-RISC16
|
368RISC/Data Path/Decode/decode_dp.vhd
| 1 | 1,430 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Brett Bourgeois
--
-- Create Date: 11:49:41 04/24/2015
-- Design Name:
-- Module Name: decode_dp - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE work.UMDRISC_pkg.ALL;
use work.all;
entity decode is
port (
--Input
clk: in std_logic;
rst: in std_logic;
--
ADRS_A: in std_logic_vector (3 downto 0);
ADRS_B: in std_logic_vector (3 downto 0);
imm: in std_logic_vector (3 downto 0);
instruction: in std_logic_vector (15 downto 0);
--Control Signals
imm_mux_sel: in std_logic;
--Output
--==
imm_out : out std_logic
--==
);
end decode;
architecture Structural of decode is
signal imm_mux_out: std_logic_vector(7 downto 0) := (others => '0');
begin
--MUX2to1
MUX2to1: entity work.MUX2to1
generic map( vectorSize => adrs_width)
port map(
SEL => imm_mux_sel,
IN_1 => ADRS_B,
IN_2 => imm,
OUTPUT => imm_mux_out
);
--Register Bank
-- regBank: entity work.regbank
-- port map(
-- );
--registers to hold data
end Structural;
architecture behavioral of decode is
begin
end behavioral;
|
mit
|
e6c5ed65c9e3f7b0d361d4b702eb0c4b
| 0.566434 | 3.191964 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_testbench_capture_GNHCRI5YMO.vhd
| 20 | 1,775 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GNHCRI5YMO is
generic ( XFILE : string := "default";
DSPBTYPE : string := "");
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_capture_GNHCRI5YMO is
function str(sl: std_logic) return character is
variable c: character;
begin
case sl is
when '0' => c := '0';
when '1' => c := '1';
when others => c := 'X';
end case;
return c;
end str;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := str(slv(i));
r := r + 1;
end loop;
return result;
end str;
procedure write_type_header(file f:text) is
use STD.textio.all;
variable my_line : line;
begin
write ( my_line, DSPBTYPE);
writeline ( f, my_line );
end procedure write_type_header ;
file oFile : text open write_mode is XFILE;
Begin
-- data capture
-- write type information to output file
write_type_header(oFile);
-- Writing Output Signal into file
Output:process(clock)
variable traceline : line ;
begin
if (aclr ='1') then
-- do not record
elsif clock'event and clock='1' then
write(traceline, str(input),justified=>left);
writeline(oFile,traceline);
end if ;
end process ;
end architecture;
|
mit
|
63efdf8d6e1b45d3d7c028c3a48a6256
| 0.629296 | 3.349057 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_single_pulse_GN2XGKTRR3.vhd
| 8 | 831 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic ( delay : positive := 1;
signal_type : string := "Step Down";
impulse_width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
result : out std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_single_pulse_GN2XGKTRR3 is
Begin
SinglePulsei : alt_dspbuilder_sStepAltr Generic map (
StepDelay => 1,
direction => 0 )
port map (
clock => clock,
ena => ena,
q => result,
sclr => sclr,
user_aclr => '0',
aclr => aclr);
end architecture;
|
mit
|
e089c3a5d103cd953c2a1bbfbc0be1ad
| 0.655836 | 2.85567 | false | false | false | false |
Ttl/bf_cpu
|
cpu.vhd
| 1 | 3,917 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.bfconfig.all;
--pragma synthesis_off
use IEEE.NUMERIC_STD.ALL;
--pragma synthesis_on
entity cpu is
Generic ( INSTRUCTIONS : string := "scripts/instructions.mif"
);
Port ( clk, reset : in STD_LOGIC;
tx : out STD_LOGIC;
rx : in STD_LOGIC);
end cpu;
architecture Behavioral of cpu is
signal instr : std_logic_vector(7 downto 0);
-- Decoder signals
signal d_alutoreg : std_logic;
signal d_alua, d_alub : std_logic_vector(1 downto 0);
signal d_write, d_read : std_logic;
signal d_jumpf, d_jumpb : std_logic;
signal pc : pctype;
-- RAM signals
constant i_wd : std_logic_vector(7 downto 0) := (others => '0');
constant i_we : std_logic := '0';
-- Datapath signals
signal readdata, writedata : std_logic_vector(7 downto 0);
signal alu_z : std_logic;
-- UART signals
signal uart_tx_req : std_logic;
signal uart_tx_end : std_logic;
signal uart_rx_ready : std_logic;
-- Control signals
signal c_skip : std_logic;
-- Execute state signals
signal e_alutoreg, e_skip : std_logic;
signal e_alua, e_alub : std_logic_vector(1 downto 0);
--pragma synthesis_off
-- Currently executing instruction
signal instr_ex : std_logic_vector(7 downto 0);
--pragma synthesis_on
begin
instr_mem : entity work.memory
Generic map(
CONTENTS => INSTRUCTIONS
)
Port map( clk => clk,
a1 => pc,
wd => i_wd,
d1 => instr,
we => i_we);
decoder1 : entity work.decoder
Port map( instr => instr,
d_alutoreg => d_alutoreg,
d_alua => d_alua,
d_alub => d_alub,
d_write => d_write,
d_read => d_read,
d_jumpf => d_jumpf,
d_jumpb => d_jumpb
);
control1 : entity work.control
Port map( clk => clk,
reset => reset,
d_jumpf => d_jumpf,
d_jumpb => d_jumpb,
d_write => d_write,
d_read => d_read,
c_skip => c_skip,
alu_z => alu_z,
pc_out => pc,
uart_tx_end => uart_tx_end,
uart_rx_ready => uart_rx_ready
);
process(clk)
begin
if rising_edge(clk) then
e_alutoreg <= d_alutoreg;
e_alua <= d_alua;
e_alub <= d_alub;
e_skip <= c_skip;
--pragma synthesis_off
instr_ex <= instr;
--pragma synthesis_on
end if;
end process;
datapath1 : entity work.datapath
Port map( clk => clk,
reset => reset,
c_skip => e_skip,
d_alutoreg => e_alutoreg,
d_alua => e_alua,
d_alub => e_alub,
readdata => readdata,
writedata => writedata,
alu_z => alu_z);
uart_tx_req <= d_write and not e_skip;
--pragma synthesis_off
-- Print sent data
process
begin
wait until uart_tx_req = '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
if to_integer(unsigned(writedata)) > 31 and to_integer(unsigned(writedata)) < 127 then
report "Sent ASCII: "&character'image(character'val(to_integer(unsigned(writedata))));
else
report "Sent Dec: "&integer'image(to_integer(unsigned(writedata)));
end if;
wait until uart_tx_end = '1';
end process;
-- Print received data
process
begin
wait until uart_rx_ready = '1';
wait until rising_edge(clk);
if to_integer(unsigned(readdata)) > 31 and to_integer(unsigned(readdata)) < 127 then
report "Received ASCII: "&character'image(character'val(to_integer(unsigned(readdata))));
else
report "Received Dec: "&integer'image(to_integer(unsigned(readdata)));
end if;
end process;
--pragma synthesis_on
uart1 : entity work.uart
Generic map(
CLK_FREQ => 72,
SER_FREQ => 115200,
PARITY_BIT => false
)
Port map (
clk => clk,
rst => reset,
rx => rx,
tx => tx,
tx_req => uart_tx_req,
tx_end => uart_tx_end,
tx_data => writedata,
rx_ready => uart_rx_ready,
rx_data => readdata
);
end Behavioral;
|
lgpl-3.0
|
48dae56b6d5e6ce6d32f5b7395d87030
| 0.602502 | 3.272348 | false | false | false | false |
Ttl/bf_cpu
|
reg_file.vhd
| 1 | 712 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.bfconfig.all;
entity reg_file is
Port ( clk : in STD_LOGIC;
a1 : in pointertype;
wd : in STD_LOGIC_VECTOR (7 downto 0);
d1 : out STD_LOGIC_VECTOR (7 downto 0);
we : in STD_LOGIC);
end reg_file;
architecture Behavioral of reg_file is
type memtype is array(0 to 2**REG_SIZE-1) of std_logic_vector(7 downto 0);
signal reg_mem : memtype := (others => (others => '0'));
begin
process(clk, we, a1, reg_mem)
begin
if rising_edge(clk) then
if we = '1' then
reg_mem(to_integer(unsigned(a1))) <= wd;
end if;
end if;
d1 <= reg_mem(to_integer(unsigned(a1)));
end process;
end Behavioral;
|
lgpl-3.0
|
29c2fd9bccfac1aeaf50c939e9992279
| 0.641854 | 2.825397 | false | false | false | false |
cathalmccabe/PYNQ
|
boards/ip/audio_codec_ctrl_v1.0/src/address_decoder.vhd
| 4 | 21,808 |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v1.01.a
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common_types.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity work.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity work.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
|
bsd-3-clause
|
294c1cfe7cf45f7a5d6fec39370e65cb
| 0.456759 | 4.500206 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_testbench_salt_GN6DKNTQ5M.vhd
| 13 | 1,747 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN6DKNTQ5M is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GN6DKNTQ5M is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 2) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
mit
|
09e2612cc115922d68165a2d268c44d2
| 0.630223 | 3.006885 | false | false | false | false |
freecores/t48
|
rtl/vhdl/pmem_ctrl.vhd
| 1 | 7,836 |
-------------------------------------------------------------------------------
--
-- The Program Memory control unit.
-- All operations related to the Program Memory are managed here.
--
-- $Id: pmem_ctrl.vhd,v 1.5 2005-06-11 10:08:43 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.pmem_addr_t;
use work.t48_pack.word_t;
use work.t48_pmem_ctrl_pack.pmem_addr_ident_t;
entity t48_pmem_ctrl is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
write_pcl_i : in boolean;
read_pcl_i : in boolean;
write_pch_i : in boolean;
read_pch_i : in boolean;
inc_pc_i : in boolean;
write_pmem_addr_i : in boolean;
addr_type_i : in pmem_addr_ident_t;
read_pmem_i : in boolean;
-- Porgram Memroy Interface -----------------------------------------------
pmem_addr_o : out pmem_addr_t;
pmem_data_i : in word_t
);
end t48_pmem_ctrl;
library ieee;
use ieee.numeric_std.all;
use work.t48_pmem_ctrl_pack.all;
use work.t48_pack.res_active_c;
use work.t48_pack.clk_active_c;
use work.t48_pack.bus_idle_level_c;
use work.t48_pack.pmem_addr_width_c;
use work.t48_pack.dmem_addr_width_c;
use work.t48_pack.page_t;
architecture rtl of t48_pmem_ctrl is
-- implemented counter width of Program Counter
-- the upper bit is only altered by JMP, CALL and RET(R)
subtype pc_count_range_t is natural range pmem_addr_width_c-2 downto 0;
-- the Program Counter
signal program_counter_q : unsigned(pmem_addr_t'range);
-- the Program Memory address
signal pmem_addr_s,
pmem_addr_q : std_logic_vector(pmem_addr_t'range);
begin
-----------------------------------------------------------------------------
-- Process program_counter
--
-- Purpose:
-- Implements the Program Counter.
--
program_counter: process (res_i, clk_i)
begin
if res_i = res_active_c then
program_counter_q <= (others => '0');
pmem_addr_q <= (others => '0');
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
-- parallel load mode
if write_pcl_i then
program_counter_q(data_i'range) <= UNSIGNED(data_i);
elsif write_pch_i then
program_counter_q(pmem_addr_width_c-1 downto data_i'high+1) <=
UNSIGNED(data_i(pmem_addr_width_c - dmem_addr_width_c - 1 downto 0));
elsif inc_pc_i then
-- increment mode
-- the MSB is not modified by linear increments
-- it can only be altered by JMP, CALL or RET(R)
program_counter_q(pc_count_range_t) <=
program_counter_q(pc_count_range_t) + 1;
end if;
-- set pmem address
if write_pmem_addr_i then
pmem_addr_q <= pmem_addr_s;
end if;
end if;
end if;
end process program_counter;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process pmem_addr
--
-- Purpose:
-- Multiplex the Program Memory address.
--
pmem_addr: process (program_counter_q,
addr_type_i,
pmem_addr_q,
data_i)
begin
-- default assignment
pmem_addr_s <= STD_LOGIC_VECTOR(program_counter_q);
case addr_type_i is
when PM_PC =>
-- default is ok
null;
when PM_PAGE =>
pmem_addr_s(word_t'range) <= data_i;
-- take page address from program counter
-- => important for JMPP, MOVP!
-- they must wrap to next page when at FF!
when PM_PAGE3 =>
pmem_addr_s(word_t'range) <= data_i;
-- page address is explicitely specified
pmem_addr_s(page_t'range) <= "0011";
when others =>
null;
end case;
end process pmem_addr;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process data_output
--
-- Purpose:
-- Multiplex the data bus output.
--
data_output: process (read_pmem_i,
read_pcl_i,
read_pch_i,
pmem_data_i,
program_counter_q)
begin
data_o <= (others => bus_idle_level_c);
if read_pmem_i then
data_o <= pmem_data_i;
elsif read_pcl_i then
data_o <= STD_LOGIC_VECTOR(program_counter_q(data_o'range));
elsif read_pch_i then
data_o(3 downto 0) <= STD_LOGIC_VECTOR(program_counter_q(pmem_addr_width_c-1 downto data_o'high+1));
end if;
end process data_output;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
pmem_addr_o <= pmem_addr_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2005/06/08 19:13:53 arniml
-- fix bug report
-- "MSB of Program Counter changed upon PC increment"
--
-- Revision 1.3 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.2 2004/04/24 23:44:25 arniml
-- move from std_logic_arith to numeric_std
--
-- Revision 1.1 2004/03/23 21:31:53 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
gpl-2.0
|
efd88dcf7f2044e637eef672a4f85c1a
| 0.54173 | 4.035015 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_delay_GNIYBMGPQQ.vhd
| 4 | 1,062 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNIYBMGPQQ is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "000000000000000000001111";
width : positive := 24);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNIYBMGPQQ is
Begin
-- Delay Element
Delay1i : alt_dspbuilder_SDelay generic map (
LPM_WIDTH => 24,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture;
|
mit
|
5a7af3c6afb9446a714ae1235d8bbeac
| 0.635593 | 3.025641 | false | false | false | false |
nkkav/color_maker-s3esk
|
color_maker_top_tb.vhd
| 1 | 3,059 |
library IEEE, STD;
use STD.textio.all;
use IEEE.std_logic_textio.all; -- needs VHDL-2008
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity color_maker_top_tb is
end color_maker_top_tb;
architecture tb_arch of color_maker_top_tb is
-- UUT component
component color_maker_top
port (
clk : in std_logic;
rst : in std_logic;
sldsw : in std_logic_vector(2 downto 0);
red : out std_logic;
green : out std_logic;
blue : out std_logic;
vs : out std_logic;
hs : out std_logic
);
end component;
-- I/O signals
signal clk : std_logic := '0';
signal rst : std_logic;
signal sldsw : std_logic_vector(2 downto 0);
signal red : std_logic;
signal green : std_logic;
signal blue : std_logic;
signal vs : std_logic;
signal hs : std_logic;
-- Constant declarations
constant CLK_PERIOD : time := 20 ns;
-- Declare results file
file ResultsFile: text open write_mode is "color_maker_top_results.txt";
begin
uut : color_maker_top
port map (
clk => clk,
rst => rst,
sldsw => sldsw,
red => red,
green => green,
blue => blue,
vs => vs,
hs => hs
);
CLK_GEN_PROC: process(clk)
begin
if (clk = '0') then
clk <= '1';
else
clk <= not clk after CLK_PERIOD/2;
end if;
end process CLK_GEN_PROC;
RST_STIM: process
begin
rst <= '1';
wait for CLK_PERIOD;
rst <= '0';
wait for 8*415000*CLK_PERIOD;
end process RST_STIM;
DATA_STIM: process
variable line_el: line;
begin
sldsw <= "000";
wait for 2*CLK_PERIOD;
-- cycle through all colors, one frame each
for color in 1 to 8 loop
wait for 415000*CLK_PERIOD;
sldsw <= std_logic_vector(to_unsigned(color, 3));
-- write(line_el, 'c');
-- write(line_el, color);
-- Write the hsync
-- write(line_el, 's');
-- write(line_el, sldsw);
-- writeline(ResultsFile, line_el);
-- wait for 415000*CLK_PERIOD;
end loop;
end process DATA_STIM;
process (clk)
variable line_el: line;
variable red_ext : std_logic_vector(2 downto 0);
variable green_ext : std_logic_vector(2 downto 0);
variable blue_ext : std_logic_vector(1 downto 0);
begin
if rising_edge(clk) then
-- Write the time
write(line_el, now);
write(line_el, ':');
-- Write the hsync
write(line_el, ' ');
write(line_el, hs);
-- Write the vsync
write(line_el, ' ');
write(line_el, vs);
-- Write the red component
red_ext := red & red & red;
write(line_el, ' ');
write(line_el, red_ext);
-- Write the green component
green_ext := green & green & green;
write(line_el, ' ');
write(line_el, green_ext);
-- Write the blue component
blue_ext := blue & blue;
write(line_el, ' ');
write(line_el, blue_ext);
writeline(ResultsFile, line_el);
end if;
end process;
end tb_arch;
|
bsd-3-clause
|
b99053d2dec2be2860e4db4eba771e83
| 0.569467 | 3.325 | false | false | false | false |
nulldozer/purisc
|
Compute_Group/MAGIC_clocked/FLOW.vhd
| 2 | 4,398 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FLOW is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
ROW_A : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_B : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_C : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_D : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_E : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_W : IN STD_LOGIC_VECTOR(9 downto 0);
HAZARD : IN STD_LOGIC;
EQUALITY : OUT STD_LOGIC;
ADDRESS_A : OUT STD_LOGIC_VECTOR(9 downto 0);
ADDRESS_B : OUT STD_LOGIC_VECTOR(9 downto 0);
SEL_VECTOR : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
WREN_A : OUT STD_LOGIC;
WREN_B : OUT STD_LOGIC
);
end;
architecture flow of FLOW is
component SELECTOR
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
EQUALITY : OUT STD_LOGIC;
sel_A_0 : OUT STD_LOGIC;
sel_B_0 : OUT STD_LOGIC;
sel_C_0 : OUT STD_LOGIC;
sel_D_0 : OUT STD_LOGIC;
sel_E_0 : OUT STD_LOGIC;
sel_W_0 : OUT STD_LOGIC;
sel_A_1 : OUT STD_LOGIC;
sel_B_1 : OUT STD_LOGIC;
sel_C_1 : OUT STD_LOGIC;
sel_D_1 : OUT STD_LOGIC;
sel_E_1 : OUT STD_LOGIC;
sel_W_1 : OUT STD_LOGIC
);
end component;
component tristate
PORT(
my_in : in std_logic_vector(9 downto 0);
sel : in std_logic;
my_out : out std_logic_vector(9 downto 0)
);
end component;
signal sel_a0 : std_logic;
signal sel_b0 : std_logic;
signal sel_c0 : std_logic;
signal sel_d0 : std_logic;
signal sel_e0 : std_logic;
signal sel_w0 : std_logic;
signal sel_a1 : std_logic;
signal sel_b1 : std_logic;
signal sel_c1 : std_logic;
signal sel_d1 : std_logic;
signal sel_e1 : std_logic;
signal sel_w1 : std_logic;
begin
select_address : SELECTOR PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE,
EQUALITY => EQUALITY,
SEL_A_0 => sel_a0,
SEL_B_0 => sel_b0,
SEL_C_0 => sel_c0,
SEL_D_0 => sel_d0,
SEL_E_0 => sel_e0,
SEL_W_0 => sel_w0,
SEL_A_1 => sel_a1,
SEL_B_1 => sel_b1,
SEL_C_1 => sel_c1,
SEL_D_1 => sel_d1,
SEL_E_1 => sel_e1,
SEL_W_1 => sel_w1
);
TRI_0_PORT_A : tristate PORT MAP (
my_in => ROW_A,
sel => sel_a0,
my_out => ADDRESS_A
);
TRI_1_PORT_A : tristate PORT MAP (
my_in => ROW_B,
sel => sel_b0,
my_out => ADDRESS_A
);
TRI_2_PORT_A : tristate PORT MAP (
my_in => ROW_C,
sel => sel_c0,
my_out => ADDRESS_A
);
TRI_3_PORT_A : tristate PORT MAP (
my_in => ROW_D,
sel => sel_d0,
my_out => ADDRESS_A
);
TRI_4_PORT_A : tristate PORT MAP (
my_in => ROW_E,
sel => sel_e0,
my_out => ADDRESS_A
);
TRI_5_PORT_A : tristate PORT MAP (
my_in => ROW_W,
sel => sel_w0,
my_out => ADDRESS_A
);
TRI_0_PORT_B : tristate PORT MAP (
my_in => ROW_A,
sel => sel_a1,
my_out => ADDRESS_B
);
TRI_1_PORT_B : tristate PORT MAP (
my_in => ROW_B,
sel => sel_b1,
my_out => ADDRESS_B
);
TRI_2_PORT_B : tristate PORT MAP (
my_in => ROW_C,
sel => sel_c1,
my_out => ADDRESS_B
);
TRI_3_PORT_B : tristate PORT MAP (
my_in => ROW_D,
sel => sel_d1,
my_out => ADDRESS_B
);
TRI_4_PORT_B : tristate PORT MAP (
my_in => ROW_E,
sel => sel_e1,
my_out => ADDRESS_B
);
TRI_5_PORT_B : tristate PORT MAP (
my_in => ROW_W,
sel => sel_w1,
my_out => ADDRESS_B
);
WREN_A <= '0';
process (HAZARD, OPCODE) begin --addred this if block
if (HAZARD = '1') then
WREN_B <= '0';
else
WREN_B <= OPCODE(0); --used to be just this line
end if;
end process;
SEL_VECTOR <= sel_a0 & sel_a1 & sel_b0 & sel_b1 & sel_c0 & sel_c1 & sel_d0 & sel_d1 & sel_e0 & sel_e1;
end;
|
gpl-2.0
|
220a58a0e68de7752c720885aca4fc3b
| 0.486357 | 2.799491 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
Testbench/z126_01_altremote_update_sim_model.vhd
| 1 | 2,480 |
---------------------------------------------------------------
-- Title : Altera remote update controller model
-- Project : -
---------------------------------------------------------------
-- Author : Andreas Geissler
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 05/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description :
--
---------------------------------------------------------------
-- Hierarchy:
--
---------------------------------------------------------------
-- Copyright (C) 2014, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: $
--
-- $Log: $
--
--
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
ENTITY z126_01_ru_cycloneiii IS
PORT (
clock : IN std_logic ;
data_in : IN std_logic_vector (23 DOWNTO 0);
param : IN std_logic_vector (2 DOWNTO 0);
read_param : IN std_logic ;
read_source : IN std_logic_vector (1 DOWNTO 0);
reconfig : IN std_logic ;
reset : IN std_logic ;
reset_timer : IN std_logic ;
write_param : IN std_logic ;
busy : OUT std_logic ;
data_out : OUT std_logic_vector (28 DOWNTO 0)
);
END z126_01_ru_cycloneiii;
ARCHITECTURE z126_01_ru_cycloneiii_arch OF z126_01_ru_cycloneiii IS
BEGIN
busy_p: PROCESS
BEGIN
WAIT UNTIL rising_edge(clock) OR reset = '1';
IF reset = '1' THEN
busy <= '0';
ELSIF read_param = '1' OR read_param = '1' THEN
WAIT FOR 100 ns;
WAIT UNTIL rising_edge(clock);
busy <= '1';
WAIT FOR 600 ns;
WAIT UNTIL rising_edge(clock);
busy <= '0';
END IF;
END PROCESS;
data_out <= (OTHERS => '0');
END z126_01_ru_cycloneiii_arch;
|
gpl-3.0
|
5a5aad62b31a1fa8fab2c949980788d2
| 0.418548 | 4.661654 | false | false | false | false |
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