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Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/Test_Pattern_Generator_GN_Test_Pattern_Generator_CTRL_PAK_TRANSLATE.vhd | 2 | 30,854 | -- Test_Pattern_Generator_GN_Test_Pattern_Generator_CTRL_PAK_TRANSLATE.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.11.10:36:05
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_CTRL_PAK_TRANSLATE is
port (
ctrl_pak1 : out std_logic_vector(23 downto 0); -- ctrl_pak1.wire
dil : in std_logic_vector(3 downto 0) := (others => '0'); -- dil.wire
col : in std_logic_vector(31 downto 0) := (others => '0'); -- col.wire
ctrl_pak2 : out std_logic_vector(23 downto 0); -- ctrl_pak2.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
row : in std_logic_vector(31 downto 0) := (others => '0'); -- row.wire
ctrl_pak3 : out std_logic_vector(23 downto 0) -- ctrl_pak3.wire
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_CTRL_PAK_TRANSLATE;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_CTRL_PAK_TRANSLATE is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GNTS3MQUMJ is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNTS3MQUMJ;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_cast_GNJ7VFHJ4A is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNJ7VFHJ4A;
component alt_dspbuilder_cast_GNMYKU6OLE is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNMYKU6OLE;
component alt_dspbuilder_cast_GN5VN2FCXZ is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN5VN2FCXZ;
component alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNAUBM7IRL;
component alt_dspbuilder_bus_concat_GNWZPLIVXS is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNWZPLIVXS;
component alt_dspbuilder_bus_concat_GNIIOZRPJD is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNIIOZRPJD;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_constant_GNPLBTTHPL is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNPLBTTHPL;
component alt_dspbuilder_port_GNCNBVQF75 is
port (
input : in std_logic_vector(3 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_port_GNCNBVQF75;
component alt_dspbuilder_bus_concat_GN55ETJ4VI is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GN55ETJ4VI;
component alt_dspbuilder_cast_GNMMXHT3UH is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(3 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNMMXHT3UH;
component alt_dspbuilder_cast_GNNZHXLS76 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNNZHXLS76;
signal bus_concatenation12_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation12:output -> Bus_Concatenation13:a
signal bus_concatenation10_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation10:output -> Bus_Concatenation14:a
signal bus_concatenation11_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation11:output -> Bus_Concatenation14:b
signal bus_concatenation15_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation15:output -> Bus_Concatenation16:a
signal bus_concatenation14_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation14:output -> Bus_Concatenation16:b
signal bus_concatenation5_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation5:output -> Bus_Concatenation13:b
signal bus_concatenation2_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation2:output -> Bus_Concatenation6:a
signal bus_concatenation3_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation3:output -> Bus_Concatenation6:b
signal bus_concatenation7_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation7:output -> Bus_Concatenation12:a
signal bus_concatenation6_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation6:output -> Bus_Concatenation8:a
signal bus_concatenation4_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation4:output -> Bus_Concatenation8:b
signal bus_concatenation9_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation9:output -> Bus_Concatenation12:b
signal bus_conversion_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion:output -> Bus_Concatenation3:b
signal bus_conversion2_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion2:output -> Bus_Concatenation2:b
signal bus_conversion3_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion3:output -> Bus_Concatenation5:b
signal bus_conversion4_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion4:output -> Bus_Concatenation4:b
signal bus_conversion5_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion5:output -> Bus_Concatenation9:b
signal bus_conversion6_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion6:output -> Bus_Concatenation7:b
signal bus_conversion7_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion7:output -> Bus_Concatenation11:b
signal bus_conversion8_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion8:output -> Bus_Concatenation10:b
signal bus_concatenation8_output_wire : std_logic_vector(23 downto 0); -- Bus_Concatenation8:output -> ctrl_pak1_0:input
signal bus_concatenation13_output_wire : std_logic_vector(23 downto 0); -- Bus_Concatenation13:output -> ctrl_pak2_0:input
signal bus_concatenation16_output_wire : std_logic_vector(23 downto 0); -- Bus_Concatenation16:output -> ctrl_pak3_0:input
signal dil_0_output_wire : std_logic_vector(3 downto 0); -- dil_0:output -> cast8:input
signal cast8_output_wire : std_logic_vector(3 downto 0); -- cast8:output -> Bus_Concatenation15:b
signal col_0_output_wire : std_logic_vector(31 downto 0); -- col_0:output -> [cast10:input, cast11:input, cast12:input, cast9:input]
signal cast9_output_wire : std_logic_vector(15 downto 0); -- cast9:output -> Bus_Conversion:input
signal cast10_output_wire : std_logic_vector(15 downto 0); -- cast10:output -> Bus_Conversion2:input
signal cast11_output_wire : std_logic_vector(15 downto 0); -- cast11:output -> Bus_Conversion3:input
signal cast12_output_wire : std_logic_vector(15 downto 0); -- cast12:output -> Bus_Conversion4:input
signal row_0_output_wire : std_logic_vector(31 downto 0); -- row_0:output -> [cast13:input, cast14:input, cast15:input, cast16:input]
signal cast13_output_wire : std_logic_vector(15 downto 0); -- cast13:output -> Bus_Conversion5:input
signal cast14_output_wire : std_logic_vector(15 downto 0); -- cast14:output -> Bus_Conversion6:input
signal cast15_output_wire : std_logic_vector(15 downto 0); -- cast15:output -> Bus_Conversion7:input
signal cast16_output_wire : std_logic_vector(15 downto 0); -- cast16:output -> Bus_Conversion8:input
signal constant10_output_wire : std_logic_vector(3 downto 0); -- Constant10:output -> cast17:input
signal cast17_output_wire : std_logic_vector(3 downto 0); -- cast17:output -> Bus_Concatenation2:a
signal constant19_output_wire : std_logic_vector(3 downto 0); -- Constant19:output -> cast18:input
signal cast18_output_wire : std_logic_vector(3 downto 0); -- cast18:output -> Bus_Concatenation3:a
signal constant21_output_wire : std_logic_vector(3 downto 0); -- Constant21:output -> cast19:input
signal cast19_output_wire : std_logic_vector(3 downto 0); -- cast19:output -> Bus_Concatenation4:a
signal constant22_output_wire : std_logic_vector(3 downto 0); -- Constant22:output -> cast20:input
signal cast20_output_wire : std_logic_vector(3 downto 0); -- cast20:output -> Bus_Concatenation5:a
signal constant23_output_wire : std_logic_vector(3 downto 0); -- Constant23:output -> cast21:input
signal cast21_output_wire : std_logic_vector(3 downto 0); -- cast21:output -> Bus_Concatenation7:a
signal constant24_output_wire : std_logic_vector(3 downto 0); -- Constant24:output -> cast22:input
signal cast22_output_wire : std_logic_vector(3 downto 0); -- cast22:output -> Bus_Concatenation9:a
signal constant25_output_wire : std_logic_vector(3 downto 0); -- Constant25:output -> cast23:input
signal cast23_output_wire : std_logic_vector(3 downto 0); -- cast23:output -> Bus_Concatenation10:a
signal constant26_output_wire : std_logic_vector(3 downto 0); -- Constant26:output -> cast24:input
signal cast24_output_wire : std_logic_vector(3 downto 0); -- cast24:output -> Bus_Concatenation11:a
signal constant27_output_wire : std_logic_vector(3 downto 0); -- Constant27:output -> cast25:input
signal cast25_output_wire : std_logic_vector(3 downto 0); -- cast25:output -> Bus_Concatenation15:a
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Bus_Concatenation10:aclr, Bus_Concatenation11:aclr, Bus_Concatenation12:aclr, Bus_Concatenation13:aclr, Bus_Concatenation14:aclr, Bus_Concatenation15:aclr, Bus_Concatenation16:aclr, Bus_Concatenation2:aclr, Bus_Concatenation3:aclr, Bus_Concatenation4:aclr, Bus_Concatenation5:aclr, Bus_Concatenation6:aclr, Bus_Concatenation7:aclr, Bus_Concatenation8:aclr, Bus_Concatenation9:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Bus_Concatenation10:clock, Bus_Concatenation11:clock, Bus_Concatenation12:clock, Bus_Concatenation13:clock, Bus_Concatenation14:clock, Bus_Concatenation15:clock, Bus_Concatenation16:clock, Bus_Concatenation2:clock, Bus_Concatenation3:clock, Bus_Concatenation4:clock, Bus_Concatenation5:clock, Bus_Concatenation6:clock, Bus_Concatenation7:clock, Bus_Concatenation8:clock, Bus_Concatenation9:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion2 : component alt_dspbuilder_cast_GNTS3MQUMJ
generic map (
round => 0,
saturate => 0
)
port map (
input => cast10_output_wire, -- input.wire
output => bus_conversion2_output_wire -- output.wire
);
col_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => col, -- input.wire
output => col_0_output_wire -- output.wire
);
bus_conversion3 : component alt_dspbuilder_cast_GNJ7VFHJ4A
generic map (
round => 0,
saturate => 0
)
port map (
input => cast11_output_wire, -- input.wire
output => bus_conversion3_output_wire -- output.wire
);
bus_conversion4 : component alt_dspbuilder_cast_GNMYKU6OLE
generic map (
round => 0,
saturate => 0
)
port map (
input => cast12_output_wire, -- input.wire
output => bus_conversion4_output_wire -- output.wire
);
bus_conversion : component alt_dspbuilder_cast_GN5VN2FCXZ
generic map (
round => 0,
saturate => 0
)
port map (
input => cast9_output_wire, -- input.wire
output => bus_conversion_output_wire -- output.wire
);
bus_concatenation7 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast21_output_wire, -- a.wire
b => bus_conversion6_output_wire, -- b.wire
output => bus_concatenation7_output_wire -- output.wire
);
bus_concatenation8 : component alt_dspbuilder_bus_concat_GNWZPLIVXS
generic map (
widthB => 8,
widthA => 16
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation6_output_wire, -- a.wire
b => bus_concatenation4_output_wire, -- b.wire
output => bus_concatenation8_output_wire -- output.wire
);
bus_concatenation5 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast20_output_wire, -- a.wire
b => bus_conversion3_output_wire, -- b.wire
output => bus_concatenation5_output_wire -- output.wire
);
bus_concatenation6 : component alt_dspbuilder_bus_concat_GNIIOZRPJD
generic map (
widthB => 8,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation2_output_wire, -- a.wire
b => bus_concatenation3_output_wire, -- b.wire
output => bus_concatenation6_output_wire -- output.wire
);
bus_concatenation3 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast18_output_wire, -- a.wire
b => bus_conversion_output_wire, -- b.wire
output => bus_concatenation3_output_wire -- output.wire
);
bus_concatenation4 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast19_output_wire, -- a.wire
b => bus_conversion4_output_wire, -- b.wire
output => bus_concatenation4_output_wire -- output.wire
);
bus_concatenation2 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast17_output_wire, -- a.wire
b => bus_conversion2_output_wire, -- b.wire
output => bus_concatenation2_output_wire -- output.wire
);
ctrl_pak2_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => bus_concatenation13_output_wire, -- input.wire
output => ctrl_pak2 -- output.wire
);
ctrl_pak3_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => bus_concatenation16_output_wire, -- input.wire
output => ctrl_pak3 -- output.wire
);
constant10 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant10_output_wire -- output.wire
);
ctrl_pak1_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => bus_concatenation8_output_wire, -- input.wire
output => ctrl_pak1 -- output.wire
);
constant19 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant19_output_wire -- output.wire
);
dil_0 : component alt_dspbuilder_port_GNCNBVQF75
port map (
input => dil, -- input.wire
output => dil_0_output_wire -- output.wire
);
constant27 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant27_output_wire -- output.wire
);
constant26 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant26_output_wire -- output.wire
);
constant23 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant23_output_wire -- output.wire
);
bus_concatenation13 : component alt_dspbuilder_bus_concat_GNWZPLIVXS
generic map (
widthB => 8,
widthA => 16
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation12_output_wire, -- a.wire
b => bus_concatenation5_output_wire, -- b.wire
output => bus_concatenation13_output_wire -- output.wire
);
constant22 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant22_output_wire -- output.wire
);
bus_concatenation12 : component alt_dspbuilder_bus_concat_GNIIOZRPJD
generic map (
widthB => 8,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation7_output_wire, -- a.wire
b => bus_concatenation9_output_wire, -- b.wire
output => bus_concatenation12_output_wire -- output.wire
);
constant25 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant25_output_wire -- output.wire
);
bus_concatenation11 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast24_output_wire, -- a.wire
b => bus_conversion7_output_wire, -- b.wire
output => bus_concatenation11_output_wire -- output.wire
);
constant24 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant24_output_wire -- output.wire
);
bus_concatenation10 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast23_output_wire, -- a.wire
b => bus_conversion8_output_wire, -- b.wire
output => bus_concatenation10_output_wire -- output.wire
);
bus_concatenation16 : component alt_dspbuilder_bus_concat_GN55ETJ4VI
generic map (
widthB => 16,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation15_output_wire, -- a.wire
b => bus_concatenation14_output_wire, -- b.wire
output => bus_concatenation16_output_wire -- output.wire
);
constant21 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant21_output_wire -- output.wire
);
bus_concatenation15 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast25_output_wire, -- a.wire
b => cast8_output_wire, -- b.wire
output => bus_concatenation15_output_wire -- output.wire
);
row_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => row, -- input.wire
output => row_0_output_wire -- output.wire
);
bus_concatenation14 : component alt_dspbuilder_bus_concat_GNIIOZRPJD
generic map (
widthB => 8,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation10_output_wire, -- a.wire
b => bus_concatenation11_output_wire, -- b.wire
output => bus_concatenation14_output_wire -- output.wire
);
bus_concatenation9 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast22_output_wire, -- a.wire
b => bus_conversion5_output_wire, -- b.wire
output => bus_concatenation9_output_wire -- output.wire
);
bus_conversion8 : component alt_dspbuilder_cast_GNJ7VFHJ4A
generic map (
round => 0,
saturate => 0
)
port map (
input => cast16_output_wire, -- input.wire
output => bus_conversion8_output_wire -- output.wire
);
bus_conversion7 : component alt_dspbuilder_cast_GNTS3MQUMJ
generic map (
round => 0,
saturate => 0
)
port map (
input => cast15_output_wire, -- input.wire
output => bus_conversion7_output_wire -- output.wire
);
bus_conversion6 : component alt_dspbuilder_cast_GN5VN2FCXZ
generic map (
round => 0,
saturate => 0
)
port map (
input => cast14_output_wire, -- input.wire
output => bus_conversion6_output_wire -- output.wire
);
bus_conversion5 : component alt_dspbuilder_cast_GNMYKU6OLE
generic map (
round => 0,
saturate => 0
)
port map (
input => cast13_output_wire, -- input.wire
output => bus_conversion5_output_wire -- output.wire
);
cast8 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => dil_0_output_wire, -- input.wire
output => cast8_output_wire -- output.wire
);
cast9 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast9_output_wire -- output.wire
);
cast10 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast10_output_wire -- output.wire
);
cast11 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast11_output_wire -- output.wire
);
cast12 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast12_output_wire -- output.wire
);
cast13 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => row_0_output_wire, -- input.wire
output => cast13_output_wire -- output.wire
);
cast14 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => row_0_output_wire, -- input.wire
output => cast14_output_wire -- output.wire
);
cast15 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => row_0_output_wire, -- input.wire
output => cast15_output_wire -- output.wire
);
cast16 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => row_0_output_wire, -- input.wire
output => cast16_output_wire -- output.wire
);
cast17 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant10_output_wire, -- input.wire
output => cast17_output_wire -- output.wire
);
cast18 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant19_output_wire, -- input.wire
output => cast18_output_wire -- output.wire
);
cast19 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant21_output_wire, -- input.wire
output => cast19_output_wire -- output.wire
);
cast20 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant22_output_wire, -- input.wire
output => cast20_output_wire -- output.wire
);
cast21 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant23_output_wire, -- input.wire
output => cast21_output_wire -- output.wire
);
cast22 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant24_output_wire, -- input.wire
output => cast22_output_wire -- output.wire
);
cast23 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant25_output_wire, -- input.wire
output => cast23_output_wire -- output.wire
);
cast24 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant26_output_wire, -- input.wire
output => cast24_output_wire -- output.wire
);
cast25 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant27_output_wire, -- input.wire
output => cast25_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_CTRL_PAK_TRANSLATE
| mit | 8a6f3c825dafb7cc9cdf6a77f8e012ab | 0.609289 | 3.250869 | false | false | false | false |
freecores/t48 | bench/vhdl/t48_rom-lpm-a.vhd | 1 | 3,689 | -------------------------------------------------------------------------------
--
-- T8x48 ROM
-- Wrapper for ROM model from the LPM library.
--
-- $Id: t48_rom-lpm-a.vhd,v 1.1 2006-06-21 00:58:27 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
architecture lpm of t48_rom is
component lpm_rom
generic (
LPM_WIDTH : positive;
LPM_TYPE : string := "LPM_ROM";
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_FILE : string;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_HINT : string := "UNUSED"
);
port (
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
inclock : in std_logic;
outclock : in std_logic;
memenab : in std_logic;
q : out std_logic_vector(LPM_WIDTH-1 downto 0)
);
end component;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
rom_b : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_TYPE => "LPM_ROM",
LPM_WIDTHAD => 10,
LPM_NUMWORDS => 2 ** 10,
LPM_FILE => "rom_t48.hex",
LPM_ADDRESS_CONTROL => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_HINT => "UNUSED"
)
port map (
address => rom_addr_i,
inclock => clk_i,
outclock => clk_i,
memenab => vdd_s,
q => rom_data_o
);
end lpm;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | c304236bd69b07fa417f266592e50400 | 0.578748 | 4.412679 | false | false | false | false |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_v_tpg_0_0/synth/tutorial_v_tpg_0_0.vhd | 1 | 12,937 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:v_tpg:6.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY v_tpg_v6_0;
USE v_tpg_v6_0.v_tpg;
ENTITY tutorial_v_tpg_0_0 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
irq : OUT STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
m_axis_video_tuser : OUT STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END tutorial_v_tpg_0_0;
ARCHITECTURE tutorial_v_tpg_0_0_arch OF tutorial_v_tpg_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_v_tpg_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT v_tpg IS
GENERIC (
C_S_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_S_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
C_S_AXIS_VIDEO_FORMAT : INTEGER;
C_M_AXIS_VIDEO_FORMAT : INTEGER;
C_S_AXIS_VIDEO_TUSER_WIDTH : INTEGER;
C_M_AXIS_VIDEO_TUSER_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_CLK_FREQ_HZ : INTEGER;
C_ACTIVE_ROWS : INTEGER;
C_ACTIVE_COLS : INTEGER;
C_PATTERN_CONTROL : INTEGER;
C_MOTION_SPEED : INTEGER;
C_CROSS_HAIRS : INTEGER;
C_ZPLATE_HOR_CONTROL : INTEGER;
C_ZPLATE_VER_CONTROL : INTEGER;
C_BOX_SIZE : INTEGER;
C_BOX_COLOR : INTEGER;
C_STUCK_PIXEL_THRESH : INTEGER;
C_NOISE_GAIN : INTEGER;
C_BAYER_PHASE : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_HAS_AXI4_LITE : INTEGER;
C_HAS_VTIMING : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
intc_if : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
irq : OUT STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
s_axis_video_tuser : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
m_axis_video_tuser : OUT STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
hblank_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
vblank_in : IN STD_LOGIC;
active_video_in : IN STD_LOGIC
);
END COMPONENT v_tpg;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tutorial_v_tpg_0_0_arch: ARCHITECTURE IS "v_tpg,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tutorial_v_tpg_0_0_arch : ARCHITECTURE IS "tutorial_v_tpg_0_0,v_tpg,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tutorial_v_tpg_0_0_arch: ARCHITECTURE IS "tutorial_v_tpg_0_0,v_tpg,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=v_tpg,x_ipVersion=6.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXIS_VIDEO_DATA_WIDTH=8,C_M_AXIS_VIDEO_DATA_WIDTH=8,C_S_AXIS_VIDEO_TDATA_WIDTH=16,C_M_AXIS_VIDEO_TDATA_WIDTH=8,C_S_AXIS_VIDEO_FORMAT=0,C_M_AXIS_VIDEO_FORMAT=12,C_S_AXIS_VIDEO_TUSER_WIDTH=0,C_M_AXIS_VIDEO_TUSER_WIDTH=1,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_S_AXI_CLK_FREQ_HZ=100000000,C_ACTIVE_ROWS=1080,C_ACTIVE_COLS=1920,C_PATTERN_CONTROL=4106,C_MOTION_SPEED=0,C_CROSS_HAIRS=6553700,C_ZPLATE_HOR_CONTROL=30,C_ZPLATE_VER_CONTROL=1,C_BOX_SIZE=50,C_BOX_COLOR=0,C_STUCK_PIXEL_THRESH=0,C_NOISE_GAIN=0,C_BAYER_PHASE=2,C_HAS_INTC_IF=0,C_HAS_AXI4_LITE=1,C_HAS_VTIMING=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF irq: SIGNAL IS "xilinx.com:signal:interrupt:1.0 irq_intf INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TUSER";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 s_axi_aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RREADY";
BEGIN
U0 : v_tpg
GENERIC MAP (
C_S_AXIS_VIDEO_DATA_WIDTH => 8,
C_M_AXIS_VIDEO_DATA_WIDTH => 8,
C_S_AXIS_VIDEO_TDATA_WIDTH => 16,
C_M_AXIS_VIDEO_TDATA_WIDTH => 8,
C_S_AXIS_VIDEO_FORMAT => 0,
C_M_AXIS_VIDEO_FORMAT => 12,
C_S_AXIS_VIDEO_TUSER_WIDTH => 0,
C_M_AXIS_VIDEO_TUSER_WIDTH => 1,
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_CLK_FREQ_HZ => 100000000,
C_ACTIVE_ROWS => 1080,
C_ACTIVE_COLS => 1920,
C_PATTERN_CONTROL => 4106,
C_MOTION_SPEED => 0,
C_CROSS_HAIRS => 6553700,
C_ZPLATE_HOR_CONTROL => 30,
C_ZPLATE_VER_CONTROL => 1,
C_BOX_SIZE => 50,
C_BOX_COLOR => 0,
C_STUCK_PIXEL_THRESH => 0,
C_NOISE_GAIN => 0,
C_BAYER_PHASE => 2,
C_HAS_INTC_IF => 0,
C_HAS_AXI4_LITE => 1,
C_HAS_VTIMING => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => aresetn,
irq => irq,
s_axis_video_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_video_tvalid => '0',
s_axis_video_tlast => '0',
s_axis_video_tuser => '0',
m_axis_video_tdata => m_axis_video_tdata,
m_axis_video_tvalid => m_axis_video_tvalid,
m_axis_video_tready => m_axis_video_tready,
m_axis_video_tlast => m_axis_video_tlast,
m_axis_video_tuser => m_axis_video_tuser,
s_axi_aclk => s_axi_aclk,
s_axi_aclken => s_axi_aclken,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
hsync_in => '0',
hblank_in => '0',
vsync_in => '1',
vblank_in => '0',
active_video_in => '0'
);
END tutorial_v_tpg_0_0_arch;
| gpl-2.0 | 94f841c33fb1aa5648cb3ea68fa2a51f | 0.676896 | 3.133963 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_testbench_salt_GN7Z4SHGOK.vhd | 17 | 1,749 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 32) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
| mit | aafe4cfc014ae4ee0cf8daf1cb4be39c | 0.630646 | 3.010327 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_delay.vhd | 2 | 5,379 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
sclr : in std_logic := '0';
aclr : in std_logic := '0';
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic := '0'
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNPJ4Y7BVC is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "00000000000000000000000000100000";
WIDTH : positive := 32
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(32-1 downto 0) := (others=>'0');
output : out std_logic_vector(32-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNPJ4Y7BVC;
component alt_dspbuilder_delay_GNIYBMGPQQ is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "000000000000000000001111";
WIDTH : positive := 24
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(24-1 downto 0) := (others=>'0');
output : out std_logic_vector(24-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNIYBMGPQQ;
component alt_dspbuilder_delay_GNNBTO2F3L is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "000000000000000000000010";
WIDTH : positive := 24
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(24-1 downto 0) := (others=>'0');
output : out std_logic_vector(24-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNNBTO2F3L;
component alt_dspbuilder_delay_GNVJUPFOX3 is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "000000000000000000000000";
WIDTH : positive := 24
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(24-1 downto 0) := (others=>'0');
output : out std_logic_vector(24-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNVJUPFOX3;
begin
alt_dspbuilder_delay_GNPJ4Y7BVC_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "00000000000000000000000000100000") and (WIDTH = 32)) generate
inst_alt_dspbuilder_delay_GNPJ4Y7BVC_0: alt_dspbuilder_delay_GNPJ4Y7BVC
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "00000000000000000000000000100000", WIDTH => 32)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNIYBMGPQQ_1: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "000000000000000000001111") and (WIDTH = 24)) generate
inst_alt_dspbuilder_delay_GNIYBMGPQQ_1: alt_dspbuilder_delay_GNIYBMGPQQ
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "000000000000000000001111", WIDTH => 24)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNNBTO2F3L_2: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "000000000000000000000010") and (WIDTH = 24)) generate
inst_alt_dspbuilder_delay_GNNBTO2F3L_2: alt_dspbuilder_delay_GNNBTO2F3L
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "000000000000000000000010", WIDTH => 24)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNVJUPFOX3_3: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "000000000000000000000000") and (WIDTH = 24)) generate
inst_alt_dspbuilder_delay_GNVJUPFOX3_3: alt_dspbuilder_delay_GNVJUPFOX3
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "000000000000000000000000", WIDTH => 24)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "00000000000000000000000000100000") and (WIDTH = 32)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "000000000000000000001111") and (WIDTH = 24)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "000000000000000000000010") and (WIDTH = 24)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "000000000000000000000000") and (WIDTH = 24)))
report "Please run generate again" severity error;
end architecture rtl;
| mit | ecf90aaf124ef781b5ac970bd5a35cce | 0.666667 | 3.261977 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/altera_lnsim/altera_mult_add/_primary.vhd | 5 | 43,630 | library verilog;
use verilog.vl_types.all;
entity altera_mult_add is
generic(
extra_latency : integer := 0;
dedicated_multiplier_circuitry: string := "AUTO";
dsp_block_balancing: string := "AUTO";
selected_device_family: string := "Stratix V";
lpm_type : string := "altera_mult_add";
lpm_hint : string := "UNUSED";
width_a : integer := 1;
input_register_a0: string := "UNREGISTERED";
input_aclr_a0 : string := "NONE";
input_source_a0 : string := "DATAA";
input_register_a1: string := "UNREGISTERED";
input_aclr_a1 : string := "NONE";
input_source_a1 : string := "DATAA";
input_register_a2: string := "UNREGISTERED";
input_aclr_a2 : string := "NONE";
input_source_a2 : string := "DATAA";
input_register_a3: string := "UNREGISTERED";
input_aclr_a3 : string := "NONE";
input_source_a3 : string := "DATAA";
input_a0_latency_clock: string := "UNREGISTERED";
input_a0_latency_aclr: string := "NONE";
input_a1_latency_clock: string := "UNREGISTERED";
input_a1_latency_aclr: string := "NONE";
input_a2_latency_clock: string := "UNREGISTERED";
input_a2_latency_aclr: string := "NONE";
input_a3_latency_clock: string := "UNREGISTERED";
input_a3_latency_aclr: string := "NONE";
width_b : integer := 1;
input_register_b0: string := "UNREGISTERED";
input_aclr_b0 : string := "NONE";
input_source_b0 : string := "DATAB";
input_register_b1: string := "UNREGISTERED";
input_aclr_b1 : string := "NONE";
input_source_b1 : string := "DATAB";
input_register_b2: string := "UNREGISTERED";
input_aclr_b2 : string := "NONE";
input_source_b2 : string := "DATAB";
input_register_b3: string := "UNREGISTERED";
input_aclr_b3 : string := "NONE";
input_source_b3 : string := "DATAB";
input_b0_latency_clock: string := "UNREGISTERED";
input_b0_latency_aclr: string := "NONE";
input_b1_latency_clock: string := "UNREGISTERED";
input_b1_latency_aclr: string := "NONE";
input_b2_latency_clock: string := "UNREGISTERED";
input_b2_latency_aclr: string := "NONE";
input_b3_latency_clock: string := "UNREGISTERED";
input_b3_latency_aclr: string := "NONE";
width_c : integer := 1;
input_register_c0: string := "UNREGISTERED";
input_aclr_c0 : string := "NONE";
input_register_c1: string := "UNREGISTERED";
input_aclr_c1 : string := "NONE";
input_register_c2: string := "UNREGISTERED";
input_aclr_c2 : string := "NONE";
input_register_c3: string := "UNREGISTERED";
input_aclr_c3 : string := "NONE";
input_c0_latency_clock: string := "UNREGISTERED";
input_c0_latency_aclr: string := "NONE";
input_c1_latency_clock: string := "UNREGISTERED";
input_c1_latency_aclr: string := "NONE";
input_c2_latency_clock: string := "UNREGISTERED";
input_c2_latency_aclr: string := "NONE";
input_c3_latency_clock: string := "UNREGISTERED";
input_c3_latency_aclr: string := "NONE";
width_result : integer := 34;
output_register : string := "UNREGISTERED";
output_aclr : string := "NONE";
port_signa : string := "PORT_UNUSED";
representation_a: string := "UNSIGNED";
signed_register_a: string := "UNREGISTERED";
signed_aclr_a : string := "NONE";
signed_latency_clock_a: string := "UNREGISTERED";
signed_latency_aclr_a: string := "NONE";
port_signb : string := "PORT_UNUSED";
representation_b: string := "UNSIGNED";
signed_register_b: string := "UNREGISTERED";
signed_aclr_b : string := "NONE";
signed_latency_clock_b: string := "UNREGISTERED";
signed_latency_aclr_b: string := "NONE";
number_of_multipliers: integer := 1;
multiplier1_direction: string := "NONE";
multiplier3_direction: string := "NONE";
multiplier_register0: string := "UNREGISTERED";
multiplier_aclr0: string := "NONE";
multiplier_register1: string := "UNREGISTERED";
multiplier_aclr1: string := "NONE";
multiplier_register2: string := "UNREGISTERED";
multiplier_aclr2: string := "NONE";
multiplier_register3: string := "UNREGISTERED";
multiplier_aclr3: string := "NONE";
port_addnsub1 : string := "PORT_UNUSED";
addnsub_multiplier_register1: string := "UNREGISTERED";
addnsub_multiplier_aclr1: string := "NONE";
addnsub_multiplier_latency_clock1: string := "UNREGISTERED";
addnsub_multiplier_latency_aclr1: string := "NONE";
port_addnsub3 : string := "PORT_UNUSED";
addnsub_multiplier_register3: string := "UNREGISTERED";
addnsub_multiplier_aclr3: string := "NONE";
addnsub_multiplier_latency_clock3: string := "UNREGISTERED";
addnsub_multiplier_latency_aclr3: string := "NONE";
adder1_rounding : string := "NO";
addnsub1_round_register: string := "UNREGISTERED";
addnsub1_round_aclr: string := "NONE";
adder3_rounding : string := "NO";
addnsub3_round_register: string := "UNREGISTERED";
addnsub3_round_aclr: string := "NONE";
multiplier01_rounding: string := "NO";
mult01_round_register: string := "UNREGISTERED";
mult01_round_aclr: string := "NONE";
multiplier23_rounding: string := "NO";
mult23_round_register: string := "UNREGISTERED";
mult23_round_aclr: string := "NONE";
width_msb : integer := 17;
output_rounding : string := "NO";
output_round_type: string := "NEAREST_INTEGER";
output_round_register: string := "UNREGISTERED";
output_round_aclr: string := "NONE";
chainout_rounding: string := "NO";
chainout_round_register: string := "UNREGISTERED";
chainout_round_aclr: string := "NONE";
chainout_round_output_register: string := "UNREGISTERED";
chainout_round_output_aclr: string := "NONE";
multiplier01_saturation: string := "NO";
mult01_saturation_register: string := "UNREGISTERED";
mult01_saturation_aclr: string := "NONE";
multiplier23_saturation: string := "NO";
mult23_saturation_register: string := "UNREGISTERED";
mult23_saturation_aclr: string := "NONE";
port_mult0_is_saturated: string := "NONE";
port_mult1_is_saturated: string := "NONE";
port_mult2_is_saturated: string := "NONE";
port_mult3_is_saturated: string := "NONE";
width_saturate_sign: integer := 1;
output_saturation: string := "NO";
port_output_is_overflow: string := "PORT_UNUSED";
output_saturate_type: string := "ASYMMETRIC";
output_saturate_register: string := "UNREGISTERED";
output_saturate_aclr: string := "NONE";
chainout_saturation: string := "NO";
port_chainout_sat_is_overflow: string := "PORT_UNUSED";
chainout_saturate_register: string := "UNREGISTERED";
chainout_saturate_aclr: string := "NONE";
chainout_saturate_output_register: string := "UNREGISTERED";
chainout_saturate_output_aclr: string := "NONE";
scanouta_register: string := "UNREGISTERED";
scanouta_aclr : string := "NONE";
width_chainin : integer := 1;
chainout_adder : string := "NO";
chainout_register: string := "UNREGISTERED";
chainout_aclr : string := "NONE";
zero_chainout_output_register: string := "UNREGISTERED";
zero_chainout_output_aclr: string := "NONE";
shift_mode : string := "NO";
rotate_register : string := "UNREGISTERED";
rotate_aclr : string := "NONE";
rotate_output_register: string := "UNREGISTERED";
rotate_output_aclr: string := "NONE";
shift_right_register: string := "UNREGISTERED";
shift_right_aclr: string := "NONE";
shift_right_output_register: string := "UNREGISTERED";
shift_right_output_aclr: string := "NONE";
zero_loopback_register: string := "UNREGISTERED";
zero_loopback_aclr: string := "NONE";
zero_loopback_output_register: string := "UNREGISTERED";
zero_loopback_output_aclr: string := "NONE";
accumulator : string := "NO";
accum_direction : string := "ADD";
loadconst_value : integer := 0;
use_sload_accum_port: string := "NO";
accum_sload_register: string := "UNREGISTERED";
accum_sload_aclr: string := "NONE";
accum_sload_latency_clock: string := "UNREGISTERED";
accum_sload_latency_aclr: string := "NONE";
loadconst_control_register: string := "UNREGISTERED";
loadconst_control_aclr: string := "NONE";
double_accum : string := "NO";
systolic_delay1 : string := "UNREGISTERED";
systolic_delay3 : string := "UNREGISTERED";
systolic_aclr1 : string := "NONE";
systolic_aclr3 : string := "NONE";
preadder_mode : string := "SIMPLE";
preadder_direction_0: string := "ADD";
preadder_direction_1: string := "ADD";
preadder_direction_2: string := "ADD";
preadder_direction_3: string := "ADD";
width_coef : integer := 1;
coefsel0_register: string := "UNREGISTERED";
coefsel0_aclr : string := "NONE";
coefsel1_register: string := "UNREGISTERED";
coefsel1_aclr : string := "NONE";
coefsel2_register: string := "UNREGISTERED";
coefsel2_aclr : string := "NONE";
coefsel3_register: string := "UNREGISTERED";
coefsel3_aclr : string := "NONE";
coef0_0 : integer := 0;
coef0_1 : integer := 0;
coef0_2 : integer := 0;
coef0_3 : integer := 0;
coef0_4 : integer := 0;
coef0_5 : integer := 0;
coef0_6 : integer := 0;
coef0_7 : integer := 0;
coef1_0 : integer := 0;
coef1_1 : integer := 0;
coef1_2 : integer := 0;
coef1_3 : integer := 0;
coef1_4 : integer := 0;
coef1_5 : integer := 0;
coef1_6 : integer := 0;
coef1_7 : integer := 0;
coef2_0 : integer := 0;
coef2_1 : integer := 0;
coef2_2 : integer := 0;
coef2_3 : integer := 0;
coef2_4 : integer := 0;
coef2_5 : integer := 0;
coef2_6 : integer := 0;
coef2_7 : integer := 0;
coef3_0 : integer := 0;
coef3_1 : integer := 0;
coef3_2 : integer := 0;
coef3_3 : integer := 0;
coef3_4 : integer := 0;
coef3_5 : integer := 0;
coef3_6 : integer := 0;
coef3_7 : integer := 0;
coefsel0_latency_clock: string := "UNREGISTERED";
coefsel0_latency_aclr: string := "NONE";
coefsel1_latency_clock: string := "UNREGISTERED";
coefsel1_latency_aclr: string := "NONE";
coefsel2_latency_clock: string := "UNREGISTERED";
coefsel2_latency_aclr: string := "NONE";
coefsel3_latency_clock: string := "UNREGISTERED";
coefsel3_latency_aclr: string := "NONE";
latency : integer := 0;
signed_pipeline_register_a: string := "UNREGISTERED";
signed_pipeline_aclr_a: string := "NONE";
signed_pipeline_register_b: string := "UNREGISTERED";
signed_pipeline_aclr_b: string := "NONE";
addnsub_multiplier_pipeline_register1: string := "UNREGISTERED";
addnsub_multiplier_pipeline_aclr1: string := "NONE";
addnsub_multiplier_pipeline_register3: string := "UNREGISTERED";
addnsub_multiplier_pipeline_aclr3: string := "NONE";
addnsub1_round_pipeline_register: string := "UNREGISTERED";
addnsub1_round_pipeline_aclr: string := "NONE";
addnsub3_round_pipeline_register: string := "UNREGISTERED";
addnsub3_round_pipeline_aclr: string := "NONE";
output_round_pipeline_register: string := "UNREGISTERED";
output_round_pipeline_aclr: string := "NONE";
chainout_round_pipeline_register: string := "UNREGISTERED";
chainout_round_pipeline_aclr: string := "NONE";
output_saturate_pipeline_register: string := "UNREGISTERED";
output_saturate_pipeline_aclr: string := "NONE";
chainout_saturate_pipeline_register: string := "UNREGISTERED";
chainout_saturate_pipeline_aclr: string := "NONE";
rotate_pipeline_register: string := "UNREGISTERED";
rotate_pipeline_aclr: string := "NONE";
shift_right_pipeline_register: string := "UNREGISTERED";
shift_right_pipeline_aclr: string := "NONE";
zero_loopback_pipeline_register: string := "UNREGISTERED";
zero_loopback_pipeline_aclr: string := "NONE";
accum_sload_pipeline_register: string := "UNREGISTERED";
accum_sload_pipeline_aclr: string := "NONE";
width_clock_all_wire_msb: integer := 3;
width_aclr_all_wire_msb: integer := 3;
width_ena_all_wire_msb: integer := 3;
width_a_total_msb: vl_notype;
width_a_msb : vl_notype;
width_b_total_msb: vl_notype;
width_b_msb : vl_notype;
width_c_total_msb: vl_notype;
width_c_msb : vl_notype;
width_scanina : vl_notype;
width_scanina_msb: vl_notype;
width_scaninb : vl_notype;
width_scaninb_msb: vl_notype;
width_sourcea_msb: vl_notype;
width_sourceb_msb: vl_notype;
width_scanouta_msb: vl_notype;
width_scanoutb_msb: vl_notype;
width_chainin_msb: vl_notype;
width_result_msb: vl_notype;
width_coef_msb : vl_notype;
dataa_split_ext_require: vl_notype;
dataa_port_sign : vl_notype;
width_a_ext : vl_notype;
width_a_ext_msb : vl_notype;
datab_split_ext_require: vl_notype;
datab_port_sign : vl_notype;
width_b_ext : vl_notype;
width_b_ext_msb : vl_notype;
coef_ext_require: vl_notype;
coef_port_sign : vl_notype;
width_coef_ext : vl_notype;
width_coef_ext_msb: vl_notype;
datac_split_ext_require: vl_notype;
datac_port_sign : vl_notype;
width_c_ext : vl_notype;
width_c_ext_msb : vl_notype;
width_scanchain : vl_notype;
width_scanchain_msb: vl_notype;
scanchain_port_sign: vl_notype;
preadder_representation: vl_notype;
width_preadder_input_a: vl_notype;
width_preadder_input_a_msb: vl_notype;
width_preadder_adder_result: vl_notype;
width_preadder_output_a: vl_notype;
width_preadder_output_a_msb: vl_notype;
width_preadder_output_b: vl_notype;
width_preadder_output_b_msb: vl_notype;
multiplier_input_representation_a: vl_notype;
multiplier_input_representation_b: vl_notype;
width_mult_source_a: vl_notype;
width_mult_source_a_msb: vl_notype;
width_mult_source_b: vl_notype;
width_mult_source_b_msb: vl_notype;
width_mult_result: vl_notype;
width_mult_result_msb: vl_notype;
width_adder_source: vl_notype;
width_adder_source_msb: vl_notype;
width_adder_result: vl_notype;
width_adder_result_msb: vl_notype;
width_chainin_ext: vl_notype;
width_original_result: vl_notype;
width_original_result_msb: vl_notype;
result_ext_width: vl_notype;
width_result_output: vl_notype;
width_result_output_msb: vl_notype
);
port(
dataa : in vl_logic_vector;
datab : in vl_logic_vector;
datac : in vl_logic_vector;
scanina : in vl_logic_vector;
scaninb : in vl_logic_vector;
sourcea : in vl_logic_vector;
sourceb : in vl_logic_vector;
clock3 : in vl_logic;
clock2 : in vl_logic;
clock1 : in vl_logic;
clock0 : in vl_logic;
aclr3 : in vl_logic;
aclr2 : in vl_logic;
aclr1 : in vl_logic;
aclr0 : in vl_logic;
ena3 : in vl_logic;
ena2 : in vl_logic;
ena1 : in vl_logic;
ena0 : in vl_logic;
signa : in vl_logic;
signb : in vl_logic;
addnsub1 : in vl_logic;
addnsub3 : in vl_logic;
result : out vl_logic_vector;
scanouta : out vl_logic_vector;
scanoutb : out vl_logic_vector;
mult01_round : in vl_logic;
mult23_round : in vl_logic;
mult01_saturation: in vl_logic;
mult23_saturation: in vl_logic;
addnsub1_round : in vl_logic;
addnsub3_round : in vl_logic;
mult0_is_saturated: out vl_logic;
mult1_is_saturated: out vl_logic;
mult2_is_saturated: out vl_logic;
mult3_is_saturated: out vl_logic;
output_round : in vl_logic;
chainout_round : in vl_logic;
output_saturate : in vl_logic;
chainout_saturate: in vl_logic;
overflow : out vl_logic;
chainout_sat_overflow: out vl_logic;
chainin : in vl_logic_vector;
zero_chainout : in vl_logic;
rotate : in vl_logic;
shift_right : in vl_logic;
zero_loopback : in vl_logic;
accum_sload : in vl_logic;
sload_accum : in vl_logic;
coefsel0 : in vl_logic_vector(2 downto 0);
coefsel1 : in vl_logic_vector(2 downto 0);
coefsel2 : in vl_logic_vector(2 downto 0);
coefsel3 : in vl_logic_vector(2 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of extra_latency : constant is 1;
attribute mti_svvh_generic_type of dedicated_multiplier_circuitry : constant is 1;
attribute mti_svvh_generic_type of dsp_block_balancing : constant is 1;
attribute mti_svvh_generic_type of selected_device_family : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of width_a : constant is 1;
attribute mti_svvh_generic_type of input_register_a0 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_a0 : constant is 1;
attribute mti_svvh_generic_type of input_source_a0 : constant is 1;
attribute mti_svvh_generic_type of input_register_a1 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_a1 : constant is 1;
attribute mti_svvh_generic_type of input_source_a1 : constant is 1;
attribute mti_svvh_generic_type of input_register_a2 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_a2 : constant is 1;
attribute mti_svvh_generic_type of input_source_a2 : constant is 1;
attribute mti_svvh_generic_type of input_register_a3 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_a3 : constant is 1;
attribute mti_svvh_generic_type of input_source_a3 : constant is 1;
attribute mti_svvh_generic_type of input_a0_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_a0_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_a1_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_a1_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_a2_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_a2_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_a3_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_a3_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of width_b : constant is 1;
attribute mti_svvh_generic_type of input_register_b0 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_b0 : constant is 1;
attribute mti_svvh_generic_type of input_source_b0 : constant is 1;
attribute mti_svvh_generic_type of input_register_b1 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_b1 : constant is 1;
attribute mti_svvh_generic_type of input_source_b1 : constant is 1;
attribute mti_svvh_generic_type of input_register_b2 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_b2 : constant is 1;
attribute mti_svvh_generic_type of input_source_b2 : constant is 1;
attribute mti_svvh_generic_type of input_register_b3 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_b3 : constant is 1;
attribute mti_svvh_generic_type of input_source_b3 : constant is 1;
attribute mti_svvh_generic_type of input_b0_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_b0_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_b1_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_b1_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_b2_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_b2_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_b3_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_b3_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of width_c : constant is 1;
attribute mti_svvh_generic_type of input_register_c0 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_c0 : constant is 1;
attribute mti_svvh_generic_type of input_register_c1 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_c1 : constant is 1;
attribute mti_svvh_generic_type of input_register_c2 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_c2 : constant is 1;
attribute mti_svvh_generic_type of input_register_c3 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_c3 : constant is 1;
attribute mti_svvh_generic_type of input_c0_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_c0_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_c1_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_c1_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_c2_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_c2_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_c3_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_c3_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of width_result : constant is 1;
attribute mti_svvh_generic_type of output_register : constant is 1;
attribute mti_svvh_generic_type of output_aclr : constant is 1;
attribute mti_svvh_generic_type of port_signa : constant is 1;
attribute mti_svvh_generic_type of representation_a : constant is 1;
attribute mti_svvh_generic_type of signed_register_a : constant is 1;
attribute mti_svvh_generic_type of signed_aclr_a : constant is 1;
attribute mti_svvh_generic_type of signed_latency_clock_a : constant is 1;
attribute mti_svvh_generic_type of signed_latency_aclr_a : constant is 1;
attribute mti_svvh_generic_type of port_signb : constant is 1;
attribute mti_svvh_generic_type of representation_b : constant is 1;
attribute mti_svvh_generic_type of signed_register_b : constant is 1;
attribute mti_svvh_generic_type of signed_aclr_b : constant is 1;
attribute mti_svvh_generic_type of signed_latency_clock_b : constant is 1;
attribute mti_svvh_generic_type of signed_latency_aclr_b : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of multiplier1_direction : constant is 1;
attribute mti_svvh_generic_type of multiplier3_direction : constant is 1;
attribute mti_svvh_generic_type of multiplier_register0 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr0 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register1 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr1 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register2 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr2 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register3 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr3 : constant is 1;
attribute mti_svvh_generic_type of port_addnsub1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_register1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_aclr1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_clock1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_aclr1 : constant is 1;
attribute mti_svvh_generic_type of port_addnsub3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_register3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_aclr3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_clock3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_aclr3 : constant is 1;
attribute mti_svvh_generic_type of adder1_rounding : constant is 1;
attribute mti_svvh_generic_type of addnsub1_round_register : constant is 1;
attribute mti_svvh_generic_type of addnsub1_round_aclr : constant is 1;
attribute mti_svvh_generic_type of adder3_rounding : constant is 1;
attribute mti_svvh_generic_type of addnsub3_round_register : constant is 1;
attribute mti_svvh_generic_type of addnsub3_round_aclr : constant is 1;
attribute mti_svvh_generic_type of multiplier01_rounding : constant is 1;
attribute mti_svvh_generic_type of mult01_round_register : constant is 1;
attribute mti_svvh_generic_type of mult01_round_aclr : constant is 1;
attribute mti_svvh_generic_type of multiplier23_rounding : constant is 1;
attribute mti_svvh_generic_type of mult23_round_register : constant is 1;
attribute mti_svvh_generic_type of mult23_round_aclr : constant is 1;
attribute mti_svvh_generic_type of width_msb : constant is 1;
attribute mti_svvh_generic_type of output_rounding : constant is 1;
attribute mti_svvh_generic_type of output_round_type : constant is 1;
attribute mti_svvh_generic_type of output_round_register : constant is 1;
attribute mti_svvh_generic_type of output_round_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_rounding : constant is 1;
attribute mti_svvh_generic_type of chainout_round_register : constant is 1;
attribute mti_svvh_generic_type of chainout_round_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_round_output_register : constant is 1;
attribute mti_svvh_generic_type of chainout_round_output_aclr : constant is 1;
attribute mti_svvh_generic_type of multiplier01_saturation : constant is 1;
attribute mti_svvh_generic_type of mult01_saturation_register : constant is 1;
attribute mti_svvh_generic_type of mult01_saturation_aclr : constant is 1;
attribute mti_svvh_generic_type of multiplier23_saturation : constant is 1;
attribute mti_svvh_generic_type of mult23_saturation_register : constant is 1;
attribute mti_svvh_generic_type of mult23_saturation_aclr : constant is 1;
attribute mti_svvh_generic_type of port_mult0_is_saturated : constant is 1;
attribute mti_svvh_generic_type of port_mult1_is_saturated : constant is 1;
attribute mti_svvh_generic_type of port_mult2_is_saturated : constant is 1;
attribute mti_svvh_generic_type of port_mult3_is_saturated : constant is 1;
attribute mti_svvh_generic_type of width_saturate_sign : constant is 1;
attribute mti_svvh_generic_type of output_saturation : constant is 1;
attribute mti_svvh_generic_type of port_output_is_overflow : constant is 1;
attribute mti_svvh_generic_type of output_saturate_type : constant is 1;
attribute mti_svvh_generic_type of output_saturate_register : constant is 1;
attribute mti_svvh_generic_type of output_saturate_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_saturation : constant is 1;
attribute mti_svvh_generic_type of port_chainout_sat_is_overflow : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_register : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_output_register : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_output_aclr : constant is 1;
attribute mti_svvh_generic_type of scanouta_register : constant is 1;
attribute mti_svvh_generic_type of scanouta_aclr : constant is 1;
attribute mti_svvh_generic_type of width_chainin : constant is 1;
attribute mti_svvh_generic_type of chainout_adder : constant is 1;
attribute mti_svvh_generic_type of chainout_register : constant is 1;
attribute mti_svvh_generic_type of chainout_aclr : constant is 1;
attribute mti_svvh_generic_type of zero_chainout_output_register : constant is 1;
attribute mti_svvh_generic_type of zero_chainout_output_aclr : constant is 1;
attribute mti_svvh_generic_type of shift_mode : constant is 1;
attribute mti_svvh_generic_type of rotate_register : constant is 1;
attribute mti_svvh_generic_type of rotate_aclr : constant is 1;
attribute mti_svvh_generic_type of rotate_output_register : constant is 1;
attribute mti_svvh_generic_type of rotate_output_aclr : constant is 1;
attribute mti_svvh_generic_type of shift_right_register : constant is 1;
attribute mti_svvh_generic_type of shift_right_aclr : constant is 1;
attribute mti_svvh_generic_type of shift_right_output_register : constant is 1;
attribute mti_svvh_generic_type of shift_right_output_aclr : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_register : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_aclr : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_output_register : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_output_aclr : constant is 1;
attribute mti_svvh_generic_type of accumulator : constant is 1;
attribute mti_svvh_generic_type of accum_direction : constant is 1;
attribute mti_svvh_generic_type of loadconst_value : constant is 1;
attribute mti_svvh_generic_type of use_sload_accum_port : constant is 1;
attribute mti_svvh_generic_type of accum_sload_register : constant is 1;
attribute mti_svvh_generic_type of accum_sload_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_sload_latency_clock : constant is 1;
attribute mti_svvh_generic_type of accum_sload_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of loadconst_control_register : constant is 1;
attribute mti_svvh_generic_type of loadconst_control_aclr : constant is 1;
attribute mti_svvh_generic_type of double_accum : constant is 1;
attribute mti_svvh_generic_type of systolic_delay1 : constant is 1;
attribute mti_svvh_generic_type of systolic_delay3 : constant is 1;
attribute mti_svvh_generic_type of systolic_aclr1 : constant is 1;
attribute mti_svvh_generic_type of systolic_aclr3 : constant is 1;
attribute mti_svvh_generic_type of preadder_mode : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_0 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_1 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_2 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_3 : constant is 1;
attribute mti_svvh_generic_type of width_coef : constant is 1;
attribute mti_svvh_generic_type of coefsel0_register : constant is 1;
attribute mti_svvh_generic_type of coefsel0_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel1_register : constant is 1;
attribute mti_svvh_generic_type of coefsel1_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel2_register : constant is 1;
attribute mti_svvh_generic_type of coefsel2_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel3_register : constant is 1;
attribute mti_svvh_generic_type of coefsel3_aclr : constant is 1;
attribute mti_svvh_generic_type of coef0_0 : constant is 1;
attribute mti_svvh_generic_type of coef0_1 : constant is 1;
attribute mti_svvh_generic_type of coef0_2 : constant is 1;
attribute mti_svvh_generic_type of coef0_3 : constant is 1;
attribute mti_svvh_generic_type of coef0_4 : constant is 1;
attribute mti_svvh_generic_type of coef0_5 : constant is 1;
attribute mti_svvh_generic_type of coef0_6 : constant is 1;
attribute mti_svvh_generic_type of coef0_7 : constant is 1;
attribute mti_svvh_generic_type of coef1_0 : constant is 1;
attribute mti_svvh_generic_type of coef1_1 : constant is 1;
attribute mti_svvh_generic_type of coef1_2 : constant is 1;
attribute mti_svvh_generic_type of coef1_3 : constant is 1;
attribute mti_svvh_generic_type of coef1_4 : constant is 1;
attribute mti_svvh_generic_type of coef1_5 : constant is 1;
attribute mti_svvh_generic_type of coef1_6 : constant is 1;
attribute mti_svvh_generic_type of coef1_7 : constant is 1;
attribute mti_svvh_generic_type of coef2_0 : constant is 1;
attribute mti_svvh_generic_type of coef2_1 : constant is 1;
attribute mti_svvh_generic_type of coef2_2 : constant is 1;
attribute mti_svvh_generic_type of coef2_3 : constant is 1;
attribute mti_svvh_generic_type of coef2_4 : constant is 1;
attribute mti_svvh_generic_type of coef2_5 : constant is 1;
attribute mti_svvh_generic_type of coef2_6 : constant is 1;
attribute mti_svvh_generic_type of coef2_7 : constant is 1;
attribute mti_svvh_generic_type of coef3_0 : constant is 1;
attribute mti_svvh_generic_type of coef3_1 : constant is 1;
attribute mti_svvh_generic_type of coef3_2 : constant is 1;
attribute mti_svvh_generic_type of coef3_3 : constant is 1;
attribute mti_svvh_generic_type of coef3_4 : constant is 1;
attribute mti_svvh_generic_type of coef3_5 : constant is 1;
attribute mti_svvh_generic_type of coef3_6 : constant is 1;
attribute mti_svvh_generic_type of coef3_7 : constant is 1;
attribute mti_svvh_generic_type of coefsel0_latency_clock : constant is 1;
attribute mti_svvh_generic_type of coefsel0_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel1_latency_clock : constant is 1;
attribute mti_svvh_generic_type of coefsel1_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel2_latency_clock : constant is 1;
attribute mti_svvh_generic_type of coefsel2_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel3_latency_clock : constant is 1;
attribute mti_svvh_generic_type of coefsel3_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of latency : constant is 1;
attribute mti_svvh_generic_type of signed_pipeline_register_a : constant is 1;
attribute mti_svvh_generic_type of signed_pipeline_aclr_a : constant is 1;
attribute mti_svvh_generic_type of signed_pipeline_register_b : constant is 1;
attribute mti_svvh_generic_type of signed_pipeline_aclr_b : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_register1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_aclr1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_register3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_aclr3 : constant is 1;
attribute mti_svvh_generic_type of addnsub1_round_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of addnsub1_round_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of addnsub3_round_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of addnsub3_round_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of output_round_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of output_round_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_round_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of chainout_round_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of output_saturate_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of output_saturate_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of rotate_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of rotate_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of shift_right_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of shift_right_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_sload_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of accum_sload_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of width_clock_all_wire_msb : constant is 1;
attribute mti_svvh_generic_type of width_aclr_all_wire_msb : constant is 1;
attribute mti_svvh_generic_type of width_ena_all_wire_msb : constant is 1;
attribute mti_svvh_generic_type of width_a_total_msb : constant is 3;
attribute mti_svvh_generic_type of width_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_b_total_msb : constant is 3;
attribute mti_svvh_generic_type of width_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_c_total_msb : constant is 3;
attribute mti_svvh_generic_type of width_c_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanina : constant is 3;
attribute mti_svvh_generic_type of width_scanina_msb : constant is 3;
attribute mti_svvh_generic_type of width_scaninb : constant is 3;
attribute mti_svvh_generic_type of width_scaninb_msb : constant is 3;
attribute mti_svvh_generic_type of width_sourcea_msb : constant is 3;
attribute mti_svvh_generic_type of width_sourceb_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanouta_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanoutb_msb : constant is 3;
attribute mti_svvh_generic_type of width_chainin_msb : constant is 3;
attribute mti_svvh_generic_type of width_result_msb : constant is 3;
attribute mti_svvh_generic_type of width_coef_msb : constant is 3;
attribute mti_svvh_generic_type of dataa_split_ext_require : constant is 3;
attribute mti_svvh_generic_type of dataa_port_sign : constant is 3;
attribute mti_svvh_generic_type of width_a_ext : constant is 3;
attribute mti_svvh_generic_type of width_a_ext_msb : constant is 3;
attribute mti_svvh_generic_type of datab_split_ext_require : constant is 3;
attribute mti_svvh_generic_type of datab_port_sign : constant is 3;
attribute mti_svvh_generic_type of width_b_ext : constant is 3;
attribute mti_svvh_generic_type of width_b_ext_msb : constant is 3;
attribute mti_svvh_generic_type of coef_ext_require : constant is 3;
attribute mti_svvh_generic_type of coef_port_sign : constant is 3;
attribute mti_svvh_generic_type of width_coef_ext : constant is 3;
attribute mti_svvh_generic_type of width_coef_ext_msb : constant is 3;
attribute mti_svvh_generic_type of datac_split_ext_require : constant is 3;
attribute mti_svvh_generic_type of datac_port_sign : constant is 3;
attribute mti_svvh_generic_type of width_c_ext : constant is 3;
attribute mti_svvh_generic_type of width_c_ext_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanchain : constant is 3;
attribute mti_svvh_generic_type of width_scanchain_msb : constant is 3;
attribute mti_svvh_generic_type of scanchain_port_sign : constant is 3;
attribute mti_svvh_generic_type of preadder_representation : constant is 3;
attribute mti_svvh_generic_type of width_preadder_input_a : constant is 3;
attribute mti_svvh_generic_type of width_preadder_input_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_preadder_adder_result : constant is 3;
attribute mti_svvh_generic_type of width_preadder_output_a : constant is 3;
attribute mti_svvh_generic_type of width_preadder_output_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_preadder_output_b : constant is 3;
attribute mti_svvh_generic_type of width_preadder_output_b_msb : constant is 3;
attribute mti_svvh_generic_type of multiplier_input_representation_a : constant is 3;
attribute mti_svvh_generic_type of multiplier_input_representation_b : constant is 3;
attribute mti_svvh_generic_type of width_mult_source_a : constant is 3;
attribute mti_svvh_generic_type of width_mult_source_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_source_b : constant is 3;
attribute mti_svvh_generic_type of width_mult_source_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_result : constant is 3;
attribute mti_svvh_generic_type of width_mult_result_msb : constant is 3;
attribute mti_svvh_generic_type of width_adder_source : constant is 3;
attribute mti_svvh_generic_type of width_adder_source_msb : constant is 3;
attribute mti_svvh_generic_type of width_adder_result : constant is 3;
attribute mti_svvh_generic_type of width_adder_result_msb : constant is 3;
attribute mti_svvh_generic_type of width_chainin_ext : constant is 3;
attribute mti_svvh_generic_type of width_original_result : constant is 3;
attribute mti_svvh_generic_type of width_original_result_msb : constant is 3;
attribute mti_svvh_generic_type of result_ext_width : constant is 3;
attribute mti_svvh_generic_type of width_result_output : constant is 3;
attribute mti_svvh_generic_type of width_result_output_msb : constant is 3;
end altera_mult_add;
| mit | b8515bba39dea5499083fdf77c749a1a | 0.664245 | 3.687458 | false | false | false | false |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_ftch_cmdsts_if.vhd | 1 | 14,926 | -------------------------------------------------------------------------------
-- axi_sg_ftch_cmdsts_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Fetch command write interface from fetch sm --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
ftch_done : out std_logic ; --
ftch_error : out std_logic ; --
ftch_interr : out std_logic ; --
ftch_slverr : out std_logic ; --
ftch_decerr : out std_logic ; --
ftch_error_early : out std_logic --
);
end axi_sg_ftch_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_slverr_i : std_logic := '0';
signal ftch_decerr_i : std_logic := '0';
signal ftch_interr_i : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal sg_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sg_rvalid : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_slverr <= ftch_slverr_i;
ftch_decerr <= ftch_decerr_i;
ftch_interr <= ftch_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_ftch_cmd_tvalid <= '0';
s_axis_ftch_cmd_tdata <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
s_axis_ftch_cmd_tvalid <= '1';
s_axis_ftch_cmd_tdata <= ftch_cmnd_data;
elsif(s_axis_ftch_cmd_tready = '1')then
s_axis_ftch_cmd_tvalid <= '0';
s_axis_ftch_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_ftch_sts_tready <= '0';
else
m_axis_ftch_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_ftch_sts_tvalid = '1')then
ftch_done <= m_axis_ftch_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
ftch_slverr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
ftch_decerr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_DECERR_BIT);
ftch_interr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Early SlvErr and DecErr detections
-- Early detection primarily required for non-queue mode because fetched desc
-- is immediatle fed to DMA controller. Status from SG Datamover arrives
-- too late to stop the insuing transfer on fetch error
-------------------------------------------------------------------------------
REG_MM_RD_SIGNALS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_rresp <= (others => '0');
sg_rvalid <= '0';
else
sg_rresp <= m_axi_sg_rresp;
sg_rvalid <= m_axi_sg_rvalid;
end if;
end if;
end process REG_MM_RD_SIGNALS;
REG_ERLY_FTCH_ERROR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error_early <= '0';
elsif(sg_rvalid = '1' and (sg_rresp = SLVERR_RESP
or sg_rresp = DECERR_RESP))then
ftch_error_early <= '1';
end if;
end if;
end process REG_ERLY_FTCH_ERROR;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error <= ftch_slverr_i or ftch_decerr_i or ftch_interr_i;
-- Log errors into a global error output
FETCH_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error <= '0';
elsif(mm2s_error = '1')then
ftch_error <= '1';
end if;
end if;
end process FETCH_ERROR_PROCESS;
end implementation;
| gpl-2.0 | bffac96a50590155dbce223b69232130 | 0.410827 | 4.807085 | false | false | false | false |
cathalmccabe/PYNQ | boards/ip/audio_codec_ctrl_v1.0/src/iis_ser.vhd | 4 | 4,342 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:20:51 08/06/2012
-- Design Name:
-- Module Name: iis_ser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity iis_ser is
Port ( CLK_100MHZ : in STD_LOGIC; --gbuf clock
SCLK : in STD_LOGIC; --logic (not used as clk)
LRCLK : in STD_LOGIC; --logic (not used as clk)
SDATA : out STD_LOGIC;
EN : in STD_LOGIC;
LDATA : in STD_LOGIC_VECTOR (23 downto 0);
RDATA : in STD_LOGIC_VECTOR (23 downto 0));
end iis_ser;
architecture Behavioral of iis_ser is
--bit cntr counts to 25 (not 24) so that it can set sdata to zero after
--the 24th bit has been sent to the receiver
constant bit_cntr_max : std_logic_vector(4 downto 0) := "11001";--25
type IIS_STATE_TYPE is (RESET, WAIT_LEFT, WRITE_LEFT, WAIT_RIGHT, WRITE_RIGHT);
signal start_left : std_logic;
signal start_right : std_logic;
signal write_bit : std_logic;
signal sclk_d1 : std_logic := '0';
signal lrclk_d1 : std_logic := '0';
signal bit_cntr : std_logic_vector(4 downto 0) := (others => '0');
signal ldata_reg : std_logic_vector(23 downto 0) := (others => '0');
signal rdata_reg : std_logic_vector(23 downto 0) := (others => '0');
signal sdata_reg : std_logic := '0';
signal iis_state : IIS_STATE_TYPE := RESET;
begin
process(CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
sclk_d1 <= SCLK;
lrclk_d1 <= LRCLK;
end if;
end process;
--Detect falling edge on LRCLK
start_left <= (lrclk_d1 and not(LRCLK));
--Detect rising edge on LRCLK
start_right <= (not(lrclk_d1) and LRCLK);
--Detect falling edge on SCLK
write_bit <= (sclk_d1 and not(SCLK));
--Next state logic
next_iis_state_process : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
case iis_state is
when RESET =>
if (EN = '1') then
iis_state <= WAIT_LEFT;
end if;
when WAIT_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_left = '1') then
iis_state <= WRITE_LEFT;
end if;
when WRITE_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_RIGHT;
end if;
when WAIT_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_right = '1') then
iis_state <= WRITE_RIGHT;
end if;
when WRITE_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_LEFT;
end if;
when others=> --should never be reached
iis_state <= RESET;
end case;
end if;
end process;
process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = WRITE_RIGHT or iis_state = WRITE_LEFT) then
if (write_bit = '1') then
bit_cntr <= bit_cntr + 1;
end if;
else
bit_cntr <= (others => '0');
end if;
end if;
end process;
data_shift_proc : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = RESET) then
ldata_reg <= (others => '0');
rdata_reg <= (others => '0');
elsif ((iis_state = WAIT_LEFT) and (start_left = '1')) then
ldata_reg <= LDATA;
rdata_reg <= RDATA;
else
if (iis_state = WRITE_LEFT and write_bit = '1') then
ldata_reg(23 downto 1) <= ldata_reg(22 downto 0);
ldata_reg(0) <= '0';
end if;
if (iis_state = WRITE_RIGHT and write_bit = '1') then
rdata_reg(23 downto 1) <= rdata_reg(22 downto 0);
rdata_reg(0) <= '0';
end if;
end if;
end if;
end process data_shift_proc;
sdata_update_proc : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = RESET) then
sdata_reg <= '0';
elsif (iis_state = WRITE_LEFT and write_bit = '1') then
sdata_reg <= ldata_reg(23);
elsif (iis_state = WRITE_RIGHT and write_bit = '1') then
sdata_reg <= rdata_reg(23);
end if;
end if;
end process sdata_update_proc;
SDATA <= sdata_reg;
end Behavioral;
| bsd-3-clause | 3f10518c56a789ed510360b47592a861 | 0.581069 | 3.144098 | false | false | false | false |
freecores/t48 | rtl/vhdl/int.vhd | 1 | 8,892 | -------------------------------------------------------------------------------
--
-- The Interrupt Controller.
-- It collects the interrupt sources and notifies the decoder.
--
-- $Id: int.vhd,v 1.7 2006-06-20 00:46:03 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.mstate_t;
entity t48_int is
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
xtal_i : in std_logic;
xtal_en_i : in boolean;
clk_mstate_i : in mstate_t;
jtf_executed_i : in boolean;
tim_overflow_i : in boolean;
tf_o : out std_logic;
en_tcnti_i : in boolean;
dis_tcnti_i : in boolean;
int_n_i : in std_logic;
ale_i : in boolean;
last_cycle_i : in boolean;
en_i_i : in boolean;
dis_i_i : in boolean;
ext_int_o : out boolean;
tim_int_o : out boolean;
retr_executed_i : in boolean;
int_executed_i : in boolean;
int_pending_o : out boolean;
int_in_progress_o : out boolean
);
end t48_int;
use work.t48_pack.all;
architecture rtl of t48_int is
constant tim_int_c : std_logic := '0';
constant ext_int_c : std_logic := '1';
type int_state_t is (IDLE, PENDING, INT);
signal int_state_s,
int_state_q : int_state_t;
signal timer_flag_q : boolean;
signal timer_overflow_q : boolean;
signal timer_int_enable_q : boolean;
signal int_q : boolean;
signal int_enable_q : boolean;
signal ale_q : boolean;
signal int_type_q : std_logic;
signal int_in_progress_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process nstate
--
-- Purpose:
-- Determines the next state of the Interrupt controller FSM.
--
nstate: process (int_state_q,
int_type_q,
int_in_progress_q,
int_executed_i,
retr_executed_i,
clk_mstate_i,
last_cycle_i)
begin
int_state_s <= int_state_q;
case int_state_q is
when IDLE =>
if int_in_progress_q and
last_cycle_i and clk_mstate_i = MSTATE5 then
int_state_s <= PENDING;
end if;
when PENDING =>
if int_executed_i then
int_state_s <= INT;
end if;
when INT =>
if retr_executed_i then
int_state_s <= IDLE;
end if;
when others =>
int_state_s <= IDLE;
end case;
end process nstate;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process regs
--
-- Purpose:
-- Implement the various registers.
-- They are designed according Figure "Interrupt Logic" of
-- "The Single Component MCS-48 System".
--
regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
timer_flag_q <= false;
timer_overflow_q <= false;
timer_int_enable_q <= false;
int_enable_q <= false;
int_type_q <= '0';
int_state_q <= IDLE;
int_in_progress_q <= false;
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
int_state_q <= int_state_s;
if jtf_executed_i then
timer_flag_q <= false;
elsif tim_overflow_i then
timer_flag_q <= true;
end if;
if (int_type_q = tim_int_c and int_executed_i) or
not timer_int_enable_q then
timer_overflow_q <= false;
elsif tim_overflow_i then
timer_overflow_q <= true;
end if;
if dis_tcnti_i then
timer_int_enable_q <= false;
elsif en_tcnti_i then
timer_int_enable_q <= true;
end if;
if dis_i_i then
int_enable_q <= false;
elsif en_i_i then
int_enable_q <= true;
end if;
if retr_executed_i then
int_in_progress_q <= false;
elsif (int_q and int_enable_q) or
timer_overflow_q then
int_in_progress_q <= true;
if not int_in_progress_q then
int_type_q <= to_stdLogic(int_q and int_enable_q);
end if;
end if;
end if;
end if;
end process regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process xtal_regs
--
-- Purpose:
-- Implements the sequential registers clocked with XTAL.
--
xtal_regs: process (res_i, xtal_i)
begin
if res_i = res_active_c then
int_q <= false;
ale_q <= false;
elsif xtal_i'event and xtal_i = clk_active_c then
if xtal_en_i then
ale_q <= ale_i;
if last_cycle_i and
ale_q and not ale_i then
int_q <= not to_boolean(int_n_i);
end if;
end if;
end if;
end process xtal_regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
tf_o <= to_stdLogic(timer_flag_q);
ext_int_o <= int_type_q = ext_int_c;
tim_int_o <= int_type_q = tim_int_c;
int_pending_o <= int_state_q = PENDING;
int_in_progress_o <= int_in_progress_q and int_state_q /= IDLE;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.6 2005/11/01 21:26:24 arniml
-- operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3
--
-- Revision 1.5 2005/09/13 21:00:16 arniml
-- Fix bug reports:
-- "Target address of JMP to Program Memory Bank 1 corrupted by interrupt"
-- "Return address of CALL to Program Memory Bank 1 corrupted by interrupt"
-- int_in_progress_o was active one cycle before int_pending_o is
-- asserted. this confused the mb multiplexer which determines the state of
-- the memory bank selection flag
--
-- Revision 1.4 2005/06/11 10:08:43 arniml
-- introduce prefix 't48_' for all packages, entities and configurations
--
-- Revision 1.3 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.2 2004/06/30 21:18:28 arniml
-- Fix bug report:
-- "Program Memory bank can be switched during interrupt"
-- int module emits int_in_progress signal that is used inside the decoder
-- to hold mb low for JMP and CALL during interrupts
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 0de51061657d7581a9bf2f60d4680055 | 0.542398 | 3.941489 | false | false | false | false |
Raane/Term-Assigment-TFE4140-mod-anal-dig-sys | Project/liaison/src/TestBench/liaison_TB.vhd | 1 | 3,875 | library ieee;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity liaison_tb is
end liaison_tb;
architecture TB_ARCHITECTURE of liaison_tb is
-- Component declaration of the tested unit
component liaison
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
di_ready : in STD_LOGIC;
mp_data : in STD_LOGIC_VECTOR(3 downto 0);
do_ready : out STD_LOGIC;
voted_data : out STD_LOGIC );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal clk : STD_LOGIC;
signal reset : STD_LOGIC;
signal di_ready : STD_LOGIC;
signal mp_data : STD_LOGIC_VECTOR(3 downto 0);
-- Observed signals - signals mapped to the output ports of tested entity
signal do_ready : STD_LOGIC;
signal voted_data : STD_LOGIC;
-- Add your code here ...
begin
stim_proc: process
begin
-- Setup and reset
di_ready <= '0';
mp_data <= "1111";
reset <= '0';
wait for 10 ns;
reset <= '1';
wait for 10 ns;
reset <= '0';
wait for 10 ns;
-- Test with alternating output and no errors
di_ready <= '1';
mp_data <= "0000";
wait for 10 ns;
di_ready <= '0';
mp_data <= "1111";
wait for 10 ns;
mp_data <= "0000";
wait for 10 ns;
mp_data <= "1111";
wait for 10 ns;
mp_data <= "0000";
wait for 10 ns;
mp_data <= "1111";
wait for 10 ns;
mp_data <= "0000";
wait for 10 ns;
mp_data <= "1111";
-- Wait while data is transmited
wait for 80 ns;
-- Test with alternating output and a single errorous bit
di_ready <= '1';
mp_data <= "0000";
wait for 10 ns;
di_ready <= '0';
mp_data <= "1110";
wait for 10 ns;
mp_data <= "0000";
wait for 10 ns;
mp_data <= "1111";
wait for 10 ns;
mp_data <= "0000";
wait for 10 ns;
mp_data <= "1111";
wait for 10 ns;
mp_data <= "0000";
wait for 10 ns;
mp_data <= "1111";
-- Wait while data is transmited
wait for 80 ns;
-- Test with alternating output and a single errorous bit
di_ready <= '1';
mp_data <= "0000";
wait for 10 ns;
di_ready <= '0';
mp_data <= "1110";
wait for 10 ns;
mp_data <= "0010";
wait for 10 ns;
mp_data <= "1111";
wait for 10 ns;
mp_data <= "0000";
wait for 10 ns;
mp_data <= "1111";
wait for 10 ns;
mp_data <= "0000";
wait for 10 ns;
mp_data <= "1111";
-- Wait while data is transmited
wait for 80 ns;
-- Test with alternating output and a single errorous bit
di_ready <= '1';
mp_data <= "0000";
wait for 10 ns;
di_ready <= '0';
mp_data <= "1110";
wait for 10 ns;
mp_data <= "0000";
wait for 10 ns;
mp_data <= "0111";
wait for 10 ns;
mp_data <= "0000";
wait for 10 ns;
mp_data <= "1111";
wait for 10 ns;
mp_data <= "0000";
wait for 10 ns;
mp_data <= "1111";
-- Wait while data is transmited
wait for 80 ns;
reset <= '1';
wait for 10 ns;
reset <= '0';
-- Test with alternating output immediately
di_ready <= '1';
mp_data <= "0000";
wait for 10 ns;
di_ready <= '0';
mp_data <= "1111";
wait for 10 ns;
mp_data <= "0000";
wait for 10 ns;
mp_data <= "1111";
wait for 10 ns;
mp_data <= "0000";
wait for 10 ns;
mp_data <= "1111";
wait for 10 ns;
mp_data <= "0000";
wait for 10 ns;
mp_data <= "1111";
wait;
end process;
-- Unit Under Test port map
UUT : liaison
port map (
clk => clk,
reset => reset,
di_ready => di_ready,
mp_data => mp_data,
do_ready => do_ready,
voted_data => voted_data
);
-- This drive the clock
clk_process :process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_liaison of liaison_tb is
for TB_ARCHITECTURE
for UUT : liaison
use entity work.liaison(liaison);
end for;
end for;
end TESTBENCH_FOR_liaison;
| apache-2.0 | 81ae2fca55cc5457a01c31b4740c76cf | 0.593032 | 2.861891 | false | true | false | false |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/Test_Pattern_Generator_GN_Test_Pattern_Generator_CTRL_PAK_TRANSLATE.vhd | 2 | 30,854 | -- Test_Pattern_Generator_GN_Test_Pattern_Generator_CTRL_PAK_TRANSLATE.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:05:29
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_CTRL_PAK_TRANSLATE is
port (
ctrl_pak2 : out std_logic_vector(23 downto 0); -- ctrl_pak2.wire
dil : in std_logic_vector(3 downto 0) := (others => '0'); -- dil.wire
col : in std_logic_vector(31 downto 0) := (others => '0'); -- col.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
ctrl_pak1 : out std_logic_vector(23 downto 0); -- ctrl_pak1.wire
ctrl_pak3 : out std_logic_vector(23 downto 0); -- ctrl_pak3.wire
row : in std_logic_vector(31 downto 0) := (others => '0') -- row.wire
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_CTRL_PAK_TRANSLATE;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_CTRL_PAK_TRANSLATE is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GNTS3MQUMJ is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNTS3MQUMJ;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_cast_GNJ7VFHJ4A is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNJ7VFHJ4A;
component alt_dspbuilder_cast_GNMYKU6OLE is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNMYKU6OLE;
component alt_dspbuilder_cast_GN5VN2FCXZ is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN5VN2FCXZ;
component alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNAUBM7IRL;
component alt_dspbuilder_bus_concat_GNWZPLIVXS is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNWZPLIVXS;
component alt_dspbuilder_bus_concat_GNIIOZRPJD is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNIIOZRPJD;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_constant_GNPLBTTHPL is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNPLBTTHPL;
component alt_dspbuilder_port_GNCNBVQF75 is
port (
input : in std_logic_vector(3 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_port_GNCNBVQF75;
component alt_dspbuilder_bus_concat_GN55ETJ4VI is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GN55ETJ4VI;
component alt_dspbuilder_cast_GNMMXHT3UH is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(3 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNMMXHT3UH;
component alt_dspbuilder_cast_GNNZHXLS76 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNNZHXLS76;
signal bus_concatenation12_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation12:output -> Bus_Concatenation13:a
signal bus_concatenation10_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation10:output -> Bus_Concatenation14:a
signal bus_concatenation11_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation11:output -> Bus_Concatenation14:b
signal bus_concatenation15_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation15:output -> Bus_Concatenation16:a
signal bus_concatenation14_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation14:output -> Bus_Concatenation16:b
signal bus_concatenation5_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation5:output -> Bus_Concatenation13:b
signal bus_concatenation2_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation2:output -> Bus_Concatenation6:a
signal bus_concatenation3_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation3:output -> Bus_Concatenation6:b
signal bus_concatenation7_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation7:output -> Bus_Concatenation12:a
signal bus_concatenation6_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation6:output -> Bus_Concatenation8:a
signal bus_concatenation4_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation4:output -> Bus_Concatenation8:b
signal bus_concatenation9_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation9:output -> Bus_Concatenation12:b
signal bus_conversion_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion:output -> Bus_Concatenation3:b
signal bus_conversion2_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion2:output -> Bus_Concatenation2:b
signal bus_conversion3_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion3:output -> Bus_Concatenation5:b
signal bus_conversion4_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion4:output -> Bus_Concatenation4:b
signal bus_conversion5_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion5:output -> Bus_Concatenation9:b
signal bus_conversion6_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion6:output -> Bus_Concatenation7:b
signal bus_conversion7_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion7:output -> Bus_Concatenation11:b
signal bus_conversion8_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion8:output -> Bus_Concatenation10:b
signal bus_concatenation8_output_wire : std_logic_vector(23 downto 0); -- Bus_Concatenation8:output -> ctrl_pak1_0:input
signal bus_concatenation13_output_wire : std_logic_vector(23 downto 0); -- Bus_Concatenation13:output -> ctrl_pak2_0:input
signal bus_concatenation16_output_wire : std_logic_vector(23 downto 0); -- Bus_Concatenation16:output -> ctrl_pak3_0:input
signal dil_0_output_wire : std_logic_vector(3 downto 0); -- dil_0:output -> cast8:input
signal cast8_output_wire : std_logic_vector(3 downto 0); -- cast8:output -> Bus_Concatenation15:b
signal col_0_output_wire : std_logic_vector(31 downto 0); -- col_0:output -> [cast10:input, cast11:input, cast12:input, cast9:input]
signal cast9_output_wire : std_logic_vector(15 downto 0); -- cast9:output -> Bus_Conversion:input
signal cast10_output_wire : std_logic_vector(15 downto 0); -- cast10:output -> Bus_Conversion2:input
signal cast11_output_wire : std_logic_vector(15 downto 0); -- cast11:output -> Bus_Conversion3:input
signal cast12_output_wire : std_logic_vector(15 downto 0); -- cast12:output -> Bus_Conversion4:input
signal row_0_output_wire : std_logic_vector(31 downto 0); -- row_0:output -> [cast13:input, cast14:input, cast15:input, cast16:input]
signal cast13_output_wire : std_logic_vector(15 downto 0); -- cast13:output -> Bus_Conversion5:input
signal cast14_output_wire : std_logic_vector(15 downto 0); -- cast14:output -> Bus_Conversion6:input
signal cast15_output_wire : std_logic_vector(15 downto 0); -- cast15:output -> Bus_Conversion7:input
signal cast16_output_wire : std_logic_vector(15 downto 0); -- cast16:output -> Bus_Conversion8:input
signal constant10_output_wire : std_logic_vector(3 downto 0); -- Constant10:output -> cast17:input
signal cast17_output_wire : std_logic_vector(3 downto 0); -- cast17:output -> Bus_Concatenation2:a
signal constant19_output_wire : std_logic_vector(3 downto 0); -- Constant19:output -> cast18:input
signal cast18_output_wire : std_logic_vector(3 downto 0); -- cast18:output -> Bus_Concatenation3:a
signal constant21_output_wire : std_logic_vector(3 downto 0); -- Constant21:output -> cast19:input
signal cast19_output_wire : std_logic_vector(3 downto 0); -- cast19:output -> Bus_Concatenation4:a
signal constant22_output_wire : std_logic_vector(3 downto 0); -- Constant22:output -> cast20:input
signal cast20_output_wire : std_logic_vector(3 downto 0); -- cast20:output -> Bus_Concatenation5:a
signal constant23_output_wire : std_logic_vector(3 downto 0); -- Constant23:output -> cast21:input
signal cast21_output_wire : std_logic_vector(3 downto 0); -- cast21:output -> Bus_Concatenation7:a
signal constant24_output_wire : std_logic_vector(3 downto 0); -- Constant24:output -> cast22:input
signal cast22_output_wire : std_logic_vector(3 downto 0); -- cast22:output -> Bus_Concatenation9:a
signal constant25_output_wire : std_logic_vector(3 downto 0); -- Constant25:output -> cast23:input
signal cast23_output_wire : std_logic_vector(3 downto 0); -- cast23:output -> Bus_Concatenation10:a
signal constant26_output_wire : std_logic_vector(3 downto 0); -- Constant26:output -> cast24:input
signal cast24_output_wire : std_logic_vector(3 downto 0); -- cast24:output -> Bus_Concatenation11:a
signal constant27_output_wire : std_logic_vector(3 downto 0); -- Constant27:output -> cast25:input
signal cast25_output_wire : std_logic_vector(3 downto 0); -- cast25:output -> Bus_Concatenation15:a
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Bus_Concatenation10:aclr, Bus_Concatenation11:aclr, Bus_Concatenation12:aclr, Bus_Concatenation13:aclr, Bus_Concatenation14:aclr, Bus_Concatenation15:aclr, Bus_Concatenation16:aclr, Bus_Concatenation2:aclr, Bus_Concatenation3:aclr, Bus_Concatenation4:aclr, Bus_Concatenation5:aclr, Bus_Concatenation6:aclr, Bus_Concatenation7:aclr, Bus_Concatenation8:aclr, Bus_Concatenation9:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Bus_Concatenation10:clock, Bus_Concatenation11:clock, Bus_Concatenation12:clock, Bus_Concatenation13:clock, Bus_Concatenation14:clock, Bus_Concatenation15:clock, Bus_Concatenation16:clock, Bus_Concatenation2:clock, Bus_Concatenation3:clock, Bus_Concatenation4:clock, Bus_Concatenation5:clock, Bus_Concatenation6:clock, Bus_Concatenation7:clock, Bus_Concatenation8:clock, Bus_Concatenation9:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion2 : component alt_dspbuilder_cast_GNTS3MQUMJ
generic map (
round => 0,
saturate => 0
)
port map (
input => cast10_output_wire, -- input.wire
output => bus_conversion2_output_wire -- output.wire
);
col_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => col, -- input.wire
output => col_0_output_wire -- output.wire
);
bus_conversion3 : component alt_dspbuilder_cast_GNJ7VFHJ4A
generic map (
round => 0,
saturate => 0
)
port map (
input => cast11_output_wire, -- input.wire
output => bus_conversion3_output_wire -- output.wire
);
bus_conversion4 : component alt_dspbuilder_cast_GNMYKU6OLE
generic map (
round => 0,
saturate => 0
)
port map (
input => cast12_output_wire, -- input.wire
output => bus_conversion4_output_wire -- output.wire
);
bus_conversion : component alt_dspbuilder_cast_GN5VN2FCXZ
generic map (
round => 0,
saturate => 0
)
port map (
input => cast9_output_wire, -- input.wire
output => bus_conversion_output_wire -- output.wire
);
bus_concatenation7 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast21_output_wire, -- a.wire
b => bus_conversion6_output_wire, -- b.wire
output => bus_concatenation7_output_wire -- output.wire
);
bus_concatenation8 : component alt_dspbuilder_bus_concat_GNWZPLIVXS
generic map (
widthB => 8,
widthA => 16
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation6_output_wire, -- a.wire
b => bus_concatenation4_output_wire, -- b.wire
output => bus_concatenation8_output_wire -- output.wire
);
bus_concatenation5 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast20_output_wire, -- a.wire
b => bus_conversion3_output_wire, -- b.wire
output => bus_concatenation5_output_wire -- output.wire
);
bus_concatenation6 : component alt_dspbuilder_bus_concat_GNIIOZRPJD
generic map (
widthB => 8,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation2_output_wire, -- a.wire
b => bus_concatenation3_output_wire, -- b.wire
output => bus_concatenation6_output_wire -- output.wire
);
bus_concatenation3 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast18_output_wire, -- a.wire
b => bus_conversion_output_wire, -- b.wire
output => bus_concatenation3_output_wire -- output.wire
);
bus_concatenation4 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast19_output_wire, -- a.wire
b => bus_conversion4_output_wire, -- b.wire
output => bus_concatenation4_output_wire -- output.wire
);
bus_concatenation2 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast17_output_wire, -- a.wire
b => bus_conversion2_output_wire, -- b.wire
output => bus_concatenation2_output_wire -- output.wire
);
ctrl_pak2_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => bus_concatenation13_output_wire, -- input.wire
output => ctrl_pak2 -- output.wire
);
ctrl_pak3_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => bus_concatenation16_output_wire, -- input.wire
output => ctrl_pak3 -- output.wire
);
constant10 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant10_output_wire -- output.wire
);
ctrl_pak1_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => bus_concatenation8_output_wire, -- input.wire
output => ctrl_pak1 -- output.wire
);
constant19 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant19_output_wire -- output.wire
);
dil_0 : component alt_dspbuilder_port_GNCNBVQF75
port map (
input => dil, -- input.wire
output => dil_0_output_wire -- output.wire
);
constant27 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant27_output_wire -- output.wire
);
constant26 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant26_output_wire -- output.wire
);
constant23 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant23_output_wire -- output.wire
);
bus_concatenation13 : component alt_dspbuilder_bus_concat_GNWZPLIVXS
generic map (
widthB => 8,
widthA => 16
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation12_output_wire, -- a.wire
b => bus_concatenation5_output_wire, -- b.wire
output => bus_concatenation13_output_wire -- output.wire
);
constant22 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant22_output_wire -- output.wire
);
bus_concatenation12 : component alt_dspbuilder_bus_concat_GNIIOZRPJD
generic map (
widthB => 8,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation7_output_wire, -- a.wire
b => bus_concatenation9_output_wire, -- b.wire
output => bus_concatenation12_output_wire -- output.wire
);
constant25 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant25_output_wire -- output.wire
);
bus_concatenation11 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast24_output_wire, -- a.wire
b => bus_conversion7_output_wire, -- b.wire
output => bus_concatenation11_output_wire -- output.wire
);
constant24 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant24_output_wire -- output.wire
);
bus_concatenation10 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast23_output_wire, -- a.wire
b => bus_conversion8_output_wire, -- b.wire
output => bus_concatenation10_output_wire -- output.wire
);
bus_concatenation16 : component alt_dspbuilder_bus_concat_GN55ETJ4VI
generic map (
widthB => 16,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation15_output_wire, -- a.wire
b => bus_concatenation14_output_wire, -- b.wire
output => bus_concatenation16_output_wire -- output.wire
);
constant21 : component alt_dspbuilder_constant_GNPLBTTHPL
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000",
width => 4
)
port map (
output => constant21_output_wire -- output.wire
);
bus_concatenation15 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast25_output_wire, -- a.wire
b => cast8_output_wire, -- b.wire
output => bus_concatenation15_output_wire -- output.wire
);
row_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => row, -- input.wire
output => row_0_output_wire -- output.wire
);
bus_concatenation14 : component alt_dspbuilder_bus_concat_GNIIOZRPJD
generic map (
widthB => 8,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation10_output_wire, -- a.wire
b => bus_concatenation11_output_wire, -- b.wire
output => bus_concatenation14_output_wire -- output.wire
);
bus_concatenation9 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast22_output_wire, -- a.wire
b => bus_conversion5_output_wire, -- b.wire
output => bus_concatenation9_output_wire -- output.wire
);
bus_conversion8 : component alt_dspbuilder_cast_GNJ7VFHJ4A
generic map (
round => 0,
saturate => 0
)
port map (
input => cast16_output_wire, -- input.wire
output => bus_conversion8_output_wire -- output.wire
);
bus_conversion7 : component alt_dspbuilder_cast_GNTS3MQUMJ
generic map (
round => 0,
saturate => 0
)
port map (
input => cast15_output_wire, -- input.wire
output => bus_conversion7_output_wire -- output.wire
);
bus_conversion6 : component alt_dspbuilder_cast_GN5VN2FCXZ
generic map (
round => 0,
saturate => 0
)
port map (
input => cast14_output_wire, -- input.wire
output => bus_conversion6_output_wire -- output.wire
);
bus_conversion5 : component alt_dspbuilder_cast_GNMYKU6OLE
generic map (
round => 0,
saturate => 0
)
port map (
input => cast13_output_wire, -- input.wire
output => bus_conversion5_output_wire -- output.wire
);
cast8 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => dil_0_output_wire, -- input.wire
output => cast8_output_wire -- output.wire
);
cast9 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast9_output_wire -- output.wire
);
cast10 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast10_output_wire -- output.wire
);
cast11 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast11_output_wire -- output.wire
);
cast12 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast12_output_wire -- output.wire
);
cast13 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => row_0_output_wire, -- input.wire
output => cast13_output_wire -- output.wire
);
cast14 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => row_0_output_wire, -- input.wire
output => cast14_output_wire -- output.wire
);
cast15 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => row_0_output_wire, -- input.wire
output => cast15_output_wire -- output.wire
);
cast16 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => row_0_output_wire, -- input.wire
output => cast16_output_wire -- output.wire
);
cast17 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant10_output_wire, -- input.wire
output => cast17_output_wire -- output.wire
);
cast18 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant19_output_wire, -- input.wire
output => cast18_output_wire -- output.wire
);
cast19 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant21_output_wire, -- input.wire
output => cast19_output_wire -- output.wire
);
cast20 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant22_output_wire, -- input.wire
output => cast20_output_wire -- output.wire
);
cast21 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant23_output_wire, -- input.wire
output => cast21_output_wire -- output.wire
);
cast22 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant24_output_wire, -- input.wire
output => cast22_output_wire -- output.wire
);
cast23 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant25_output_wire, -- input.wire
output => cast23_output_wire -- output.wire
);
cast24 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant26_output_wire, -- input.wire
output => cast24_output_wire -- output.wire
);
cast25 : component alt_dspbuilder_cast_GNMMXHT3UH
generic map (
round => 0,
saturate => 0
)
port map (
input => constant27_output_wire, -- input.wire
output => cast25_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_CTRL_PAK_TRANSLATE
| mit | a4885c68f92d7eb5af2131ddcc9c6bd5 | 0.609289 | 3.250527 | false | false | false | false |
straywarrior/MadeCPUin21days | CPU_TEST.vhd | 1 | 6,386 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:37:46 11/22/2015
-- Design Name:
-- Module Name: Z:/Downloads/VMware Shared Files/ComputerOrganization/MadeCPUin21days/CPU_TEST.vhd
-- Project Name: MadeCPUin21days
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CPU_TOP
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY CPU_TEST IS
END CPU_TEST;
ARCHITECTURE behavior OF CPU_TEST IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CPU_TOP
PORT(
clock : IN std_logic;
reset : IN std_logic;
RAM1ADDR : OUT std_logic_vector(17 downto 0);
RAM1DATA : INOUT std_logic_vector(15 downto 0);
RAM1EN : OUT std_logic;
RAM1OE : OUT std_logic;
RAM1RW : OUT std_logic;
RAM2ADDR : OUT std_logic_vector(17 downto 0);
RAM2DATA : INOUT std_logic_vector(15 downto 0);
RAM2EN : OUT std_logic;
RAM2OE : OUT std_logic;
RAM2RW : OUT std_logic;
SERIAL_DATA_READY : IN std_logic;
SERIAL_RDN : OUT std_logic;
SERIAL_TBRE : IN std_logic;
SERIAL_TSRE : IN std_logic;
SERIAL_WRN : OUT std_logic;
SW : IN std_logic_vector (15 downto 0);
LED : OUT std_logic_vector(15 downto 0);
DLED_RIGHT : out STD_LOGIC_VECTOR (6 downto 0)
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal SERIAL_DATA_READY : std_logic := '0';
signal SERIAL_TBRE : std_logic := '1';
signal SERIAL_TSRE : std_logic := '1';
--BiDirs
signal RAM1DATA : std_logic_vector(15 downto 0);
signal RAM2DATA : std_logic_vector(15 downto 0);
--Outputs
signal RAM1ADDR : std_logic_vector(17 downto 0);
signal RAM1EN : std_logic;
signal RAM1OE : std_logic;
signal RAM1RW : std_logic;
signal RAM2ADDR : std_logic_vector(17 downto 0);
signal RAM2EN : std_logic;
signal RAM2OE : std_logic;
signal RAM2RW : std_logic;
signal SERIAL_RDN : std_logic;
signal SERIAL_WRN : std_logic;
signal LED : std_logic_vector(15 downto 0);
signal SW : std_logic_vector (15 downto 0);
signal DLED_RIGHT : std_logic_vector (6 downto 0);
-- Clock period definitions
constant clock_period : time := 20 ns;
constant clock_2t_period : time := 40 ns;
constant clock_4t_period : time := 80 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CPU_TOP PORT MAP (
clock => clock,
reset => reset,
RAM1ADDR => RAM1ADDR,
RAM1DATA => RAM1DATA,
RAM1EN => RAM1EN,
RAM1OE => RAM1OE,
RAM1RW => RAM1RW,
RAM2ADDR => RAM2ADDR,
RAM2DATA => RAM2DATA,
RAM2EN => RAM2EN,
RAM2OE => RAM2OE,
RAM2RW => RAM2RW,
SERIAL_DATA_READY => SERIAL_DATA_READY,
SERIAL_RDN => SERIAL_RDN,
SERIAL_TBRE => SERIAL_TBRE,
SERIAL_TSRE => SERIAL_TSRE,
SERIAL_WRN => SERIAL_WRN,
SW => SW,
LED => LED,
DLED_RIGHT => DLED_RIGHT
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state.
reset <= '0';
sw <= "0000000001000111";
wait for 10 ns;
reset <= '1';
-- NOP
RAM2DATA <= "0000100000000000";
wait for clock_4t_period;
RAM2DATA <= x"0800";
wait for clock_4t_period;
RAM2DATA <= x"0800";
wait for clock_4t_period;
RAM2DATA <= x"6D40";
wait for clock_4t_period;
RAM2DATA <= x"35A0";
wait for clock_4t_period;
RAM2DATA <= x"6880";
wait for clock_4t_period;
RAM2DATA <= x"3000";
wait for clock_4t_period;
RAM2DATA <= x"DD00";
wait for clock_4t_period;
RAM2DATA <= x"68EF";
wait for clock_4t_period;
RAM2DATA <= (others => 'Z');
wait for clock_4t_period;
RAM2DATA <= x"3000";
wait for clock_4t_period;
RAM2DATA <= x"DD01";
wait for clock_4t_period;
RAM2DATA <= x"0800";
wait for clock_4t_period;
RAM2DATA <= x"0800";
wait for clock_4t_period;
-- NOP
RAM2DATA <= "0000100000000000";
wait for clock_4t_period;
-- B 0x31
RAM2DATA <= "0001000001100001";
wait for clock_4t_period;
-- R0 <= x"FF"
RAM2DATA <= "0110100011111111";
wait for clock_4t_period;
-- SW R0 R1 1
RAM2DATA <= "1101100000100001";
wait for clock_4t_period;
-- SLL R0 R0
RAM2DATA <= "0011000000000000";
wait for clock_4t_period;
-- R1 <= x"0F"
RAM2DATA <= "0110100000001111";
wait for clock_4t_period;
-- NOP
RAM2DATA <= "0000100000000000";
wait for clock_4t_period;
-- SW R0 R1 1
RAM2DATA <= "1101100000100001";
wait for clock_4t_period;
-- SLL R0 R0
RAM2DATA <= "0011000000000000";
-- ADDU R0 R1 R2
RAM2DATA <= "1110000000101001";
wait for clock_4t_period;
-- NOP
RAM2DATA <= "0000100000000000";
wait for clock_4t_period;
-- SW R0 R1 0
RAM2DATA <= "1101100000100000";
wait for clock_4t_period;
-- insert stimulus here
wait;
end process;
END;
| gpl-2.0 | 380c5c1b39ea9e6dbe9cb8455b8e8bfe | 0.561697 | 3.644977 | false | false | false | false |
straywarrior/MadeCPUin21days | InstDecoder.vhd | 1 | 33,151 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 15:16:45 11/14/2015
-- Design Name:
-- Module Name: InstDecoder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InstDecoder is
Port ( pc : in STD_LOGIC_VECTOR (15 downto 0);
inst : in STD_LOGIC_VECTOR (15 downto 0);
RegAVal : in STD_LOGIC_VECTOR (15 downto 0);
RegBVal : in STD_LOGIC_VECTOR (15 downto 0);
RAVal : in STD_LOGIC_VECTOR (15 downto 0);
SPVal : in STD_LOGIC_VECTOR (15 downto 0);
IHVal : in STD_LOGIC_VECTOR (15 downto 0);
T_in : in STD_LOGIC;
T_out : out STD_LOGIC;
pc_imm : out STD_LOGIC_VECTOR (15 downto 0);
pc_sel : out STD_LOGIC_VECTOR (1 downto 0);
RegWE : out STD_LOGIC;
RegDest : out STD_LOGIC_VECTOR (3 downto 0);
MemRd : out STD_LOGIC;
MemDIn : out STD_LOGIC_VECTOR (15 downto 0);
RegMemDIn : out STD_LOGIC_VECTOR (3 downto 0);
MemWE : out STD_LOGIC;
opcode : out STD_LOGIC_VECTOR (3 downto 0);
RegOpA : out STD_LOGIC_VECTOR (3 downto 0);
RegOpB : out STD_LOGIC_VECTOR (3 downto 0);
CReg : out STD_LOGIC;
CRegA : out STD_LOGIC_VECTOR (3 downto 0);
CRegB : out STD_LOGIC_VECTOR (3 downto 0);
operandA : out STD_LOGIC_VECTOR (15 downto 0);
operandB : out STD_LOGIC_VECTOR (15 downto 0)
);
end InstDecoder;
architecture Behavioral of InstDecoder is
begin
-- Use Process firt. TODO: Rewrite to combinational logic circuit
process (inst, pc, RegAVal, RegBVal, T_in, IHVal, RAVal, SPVal)
begin
case inst(15 downto 11) is
-- R type instruction
when "11100" =>
case inst(1 downto 0) is
when "01" => opcode <= "0000";
when "11" => opcode <= "0001";
when others => opcode <= "1111"; -- 1111 means doing nothing
end case;
operandA <= RegAVal;
operandB <= RegBVal;
RegDest(2 downto 0) <= inst(4 downto 2);
RegDest(3) <= '0';
RegWE <= '1';
MemWE <= '0';
MemRd <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
RegOpA(2 downto 0) <= inst(10 downto 8);
RegOpA(3) <= '0';
RegOpB(2 downto 0) <= inst(7 downto 5);
RegOpB(3) <= '0';
pc_sel <= "00";
pc_imm <= (others => '0');
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
-- R type instruction & J type instruction (excpet INT & NOP)
when "11101" =>
case inst(4 downto 2) is
when "000" => -- SLT SLTU & MFPC JR JRRA JALR
RegOpA <= "1111";
RegOpB <= "1111";
case inst(1 downto 0) is
when "10" => -- SLT
if (signed(RegAVal) < signed(RegBVal)) then
T_out <= '1';
else
T_out <= '0';
end if;
RegDest <= "1111"; -- dummy number
operandA <= (others => '0');
operandB <= (others => '0');
pc_sel <= "00";
pc_imm <= (others => '0');
CReg <= '1';
CRegA(2 downto 0) <= inst(10 downto 8); CRegA(3) <= '0';
CRegB(2 downto 0) <= inst(7 downto 5); CRegB(3) <= '0';
when "11" => -- SLTU
if (unsigned(RegAVal) < unsigned(RegBVal)) then
T_out <= '1';
else
T_out <= '0';
end if;
RegDest <= "1111"; -- dummy number
operandA <= (others => '0');
operandB <= (others => '0');
pc_sel <= "00";
pc_imm <= (others => '0');
CReg <= '1';
CRegA(2 downto 0) <= inst(10 downto 8); CRegA(3) <= '0';
CRegB(2 downto 0) <= inst(7 downto 5); CRegB(3) <= '0';
when "00" => -- MFPC JR JRRA JALR
opcode <= "1111";
T_out <= T_in;
case inst(7 downto 5) is
when "010" => -- MFPC
operandA <= pc;
operandB <= (others => '0');
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
pc_sel <= "00";
pc_imm <= (others => '0');
CReg <= '0';
when "000" => -- JR
pc_sel <= "10";
pc_imm <= (others => '0');
operandA <= (others => '0');
operandB <= (others => '0');
RegDest <= "1111"; -- dummy number
CReg <= '1';
CRegA(2 downto 0) <= inst(10 downto 8); CRegA(3) <= '0';
CRegB <= "1111";
when "001" => -- JRRA
pc_sel <= "01";
pc_imm <= (others => '0');
operandA <= (others => '0');
operandB <= (others => '0');
RegDest <= "1111"; -- dummy number
CReg <= '1';
CRegA <= "1000";
CRegB <= "1111";
null;
when "110" => -- JALR
pc_sel <= "10";
pc_imm <= (others => '0');
operandA <= pc;
operandB <= (others => '0');
RegDest <= "1000";
CReg <= '1';
CRegA(2 downto 0) <= inst(10 downto 8); CRegA(3) <= '0';
CRegB <= "1111";
when others =>
pc_sel <= "00";
pc_imm <= (others => '0');
operandA <= (others => '0');
operandB <= (others => '0');
RegDest <= "1111";
end case;
when others =>
pc_sel <= "00";
pc_imm <= (others => '0');
operandA <= (others => '0');
operandB <= (others => '0');
RegDest <= "1111";
end case;
when "001" => -- SLLV SRLV SRAV
case inst(1 downto 0) is
when "00" => opcode <= "1000";
when "10" => opcode <= "1010";
when "11" => opcode <= "1011";
when others => null;
end case;
operandA <= RegBVal;
operandB <= RegAVal;
-- RegDest is ry
RegDest(2 downto 0) <= inst(7 downto 5);
RegDest(3) <= '0';
RegOpA(2 downto 0) <= inst(7 downto 5);
RegOpA(3) <= '0';
RegOpB(2 downto 0) <= inst(10 downto 8);
RegOpB(3) <= '0';
pc_sel <= "00";
pc_imm <= (others => '0');
CReg <= '0';
T_out <= T_in;
when "010" => -- CMP NEG
case inst(1 downto 0) is
when "10" => -- CMP
if (RegAVal = RegBVal) then
T_out <= '0';
else
T_out <= '1';
end if;
RegDest <= "1111";
RegOpA <= "1111";
RegOpB <= "1111";
operandA <= (others => '0');
operandB <= (others => '0');
CReg <= '1';
CRegA(2 downto 0) <= inst(10 downto 8); CRegA(3) <= '0';
CRegB(2 downto 0) <= inst(7 downto 5); CRegB(3) <= '0';
when "11" => -- NEG
opcode <= "0001";
operandA <= (others => '0');
operandB <= RegBVal;
RegDest(2 downto 0) <= inst(10 downto 8); RegDest(3) <= '0';
RegOpA <= "1111";
RegOpB(2 downto 0) <= inst(7 downto 5); RegOpB(3) <= '0';
CReg <= '0';
T_out <= T_in;
when others => null;
end case;
pc_sel <= "00";
pc_imm <= (others => '0');
when "011" => -- AND OR XOR NOT
case inst(1 downto 0) is
when "00" => opcode <= "0100";
when "01" => opcode <= "0101";
when "10" => opcode <= "0110";
when "11" => opcode <= "0111";
when others => null;
end case;
operandA <= RegAVal;
operandB <= RegBVal;
RegOpA(2 downto 0) <= inst(10 downto 8);
RegOpA(3) <= '0';
RegOpB(2 downto 0) <= inst(7 downto 5);
RegOpB(3) <= '0';
-- RegDest is rx
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
pc_sel <= "00";
pc_imm <= (others => '0');
CReg <= '0';
T_out <= T_in;
when others =>
pc_sel <= "00";
pc_imm <= (others => '0');
opcode <= "1111"; -- 1111 means doing nothing
RegOpA <= "1111";
RegOpA <= "1111";
operandA <= (others => '0');
operandB <= (others => '0');
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
end case;
RegWE <= '1';
MemWE <= '0';
MemRd <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
-- prefix "11101" ended
when "11110" => -- MFIH MTIH
case inst(1 downto 0) is
when "00" => --MFIH
operandA <= IHVal;
-- RegDest is rx
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
RegOpA <= "1010";
when "01" => --MTIH
operandA <= RegAVal;
RegDest <= "1010";
RegOpA(2 downto 0) <= inst(10 downto 8);
RegOpA(3) <= '0';
when others => null;
end case;
opcode <= "1111";
RegWE <= '1';
MemWE <= '0';
MemRd <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
RegOpB <= "1111";
operandB <= (others => '0');
pc_sel <= "00";
pc_imm <= (others => '0');
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "00110" => -- SRL SRA SLL
case inst(1 downto 0) is
when "00" => -- SLL
opcode <= "1000";
when "10" => -- SRL
opcode <= "1010";
when "11" => -- SRA
opcode <= "1011";
when others => null;
end case;
RegWE <= '1';
-- RegDest is rx
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
operandA <= RegBVal;
if (inst(4 downto 2) = "000") then
operandB(3) <= '1';
else
operandB(3) <= '0';
end if;
operandB(2 downto 0) <= inst(4 downto 2);
operandB(15 downto 4) <= (others => '0');
MemWE <= '0';
MemRd <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
RegOpA(2 downto 0) <= inst(7 downto 5);
RegOpA(3) <= '0';
RegOpB <= "1111";
pc_sel <= "00";
pc_imm <= (others => '0');
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "01111" => -- MOVE
opcode <= "1111";
operandA <= RegBVal;
operandB <= (others => '0');
RegWE <= '1';
-- RegDest is rx
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
MemWE <= '0';
MemRd <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
RegOpA(2 downto 0) <= inst(7 downto 5);
RegOpA(3) <= '0';
RegOpB <= "1111";
pc_sel <= "00";
pc_imm <= (others => '0');
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "01100" => -- MTSP SW_RS ADDSP BTEQZ BTNEZ
case inst(10 downto 8) is
when "100" => -- MTSP
opcode <= "1111";
operandA <= RegBVal; -- NOTE: ry here is "rx"
operandB <= (others => '0');
RegWE <= '1';
RegDest <= "1001";
MemWE <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
RegOpA(2 downto 0) <= inst(7 downto 5); RegOpA(3) <= '0';
RegOpB <= "1111";
pc_sel <= "00";
pc_imm <= (others => '0');
when "010" => -- SW_RS
RegWE <= '0';
MemDIn <= RAVal;
RegMemDIn <= "1000";
MemWE <= '1';
opcode <= "0000";
operandA <= SPVal;
operandB(7 downto 0) <= inst(7 downto 0);
operandB(15 downto 8) <= (others => inst(7)); -- FIXME? S_EXT OR Z_EXT?
RegOpA <= "1001";
RegOpB <= "1111";
pc_sel <= "00";
pc_imm <= (others => '0');
when "011" => -- ADDSP
RegWE <= '1';
MemWE <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
RegDest <= "1001";
opcode <= "0000";
operandA <= SPVal;
operandB(7 downto 0) <= inst(7 downto 0);
operandB(15 downto 8) <= (others => inst(7)); -- FIXME? S_EXT OR Z_EXT?
RegOpA <= "1001";
RegOpB <= "1111";
pc_sel <= "00";
pc_imm <= (others => '0');
when "000" => -- BTEQZ
RegWE <= '0';
MemWE <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
pc_imm(7 downto 0) <= inst(7 downto 0);
pc_imm(15 downto 8) <= (others => inst(7));
if (T_in = '0') then
pc_sel <= "11";
else
pc_sel <= "00";
end if;
RegOpA <= "1111";
RegOpB <= "1111";
operandA <= (others => '0');
operandB <= (others => '0');
when "001" => -- BTNEZ
RegWE <= '0';
MemWE <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
pc_imm(7 downto 0) <= inst(7 downto 0);
pc_imm(15 downto 8) <= (others => inst(7));
if (T_in /= '0') then
pc_sel <= "11";
else
pc_sel <= "00";
end if;
RegOpA <= "1111";
RegOpB <= "1111";
operandA <= (others => '0');
operandB <= (others => '0');
when others =>
pc_sel <= "00";
pc_imm <= (others => '0');
RegWE <= '0';
MemWE <= '0';
MemDIn <= (others => '0');
RegMemDIn <= "1111";
RegOpA <= "1111";
RegOpB <= "1111";
operandA <= (others => '0');
operandB <= (others => '0');
end case;
MemRd <= '0';
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "11111" => -- INT TODO!
-- FIXME!!!
RegWE <= '0';
MemWE <= '0';
MemRd <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
RegOpA <= "1111";
RegOpB <= "1111";
operandA <= (others => '0');
operandB <= (others => '0');
pc_sel <= "00";
pc_imm <= (others => '0');
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "00001" => -- NOP
pc_sel <= "00";
RegWE <= '0';
MemWE <= '0';
MemRd <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
pc_imm <= (others => '0');
RegOpA <= "1111";
RegOpB <= "1111";
operandA <= (others => '0');
operandB <= (others => '0');
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "00000" => -- ADDSP3
pc_sel <= "00";
pc_imm <= (others => '0');
RegWE <= '1';
-- RegDest is rx
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
MemWE <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
MemRd <= '0';
opcode <= "0000";
operandA <= SPVal;
operandB(7 downto 0) <= inst(7 downto 0);
operandB(15 downto 8) <= (others => inst(7));
RegOpA <= "1001";
RegOpB <= "1111";
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "01000" => -- ADDIU3
pc_sel <= "00";
pc_imm <= (others => '0');
RegWE <= '1';
-- RegDest is ry
RegDest(2 downto 0) <= inst(7 downto 5);
RegDest(3) <= '0';
MemWE <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
MemRd <= '0';
opcode <= "0000";
operandA <= RegAVal;
operandB(3 downto 0) <= inst(3 downto 0);
operandB(15 downto 4) <= (others => inst(3));
RegOpA(2 downto 0) <= inst(10 downto 8);
RegOpA(3) <= '0';
RegOpB <= "1111";
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "01001" => -- ADDIU
pc_sel <= "00";
pc_imm <= (others => '0');
RegWE <= '1';
-- RegDest is rx
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
opcode <= "0000";
MemWE <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
MemRd <= '0';
operandA <= RegAVal;
operandB(7 downto 0) <= inst(7 downto 0);
operandB(15 downto 8) <= (others => inst(7));
RegOpA(2 downto 0) <= inst(10 downto 8);
RegOpA(3) <= '0';
RegOpB <= "1111";
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "01010" => -- SLTI
pc_sel <= "00";
pc_imm <= (others => '0');
RegWE <= '1';
MemWE <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
MemRd <= '0';
RegOpA <= "1111";
RegOpB <= "1111";
operandA <= (others => '0');
operandB <= (others => '0');
CReg <= '1';
CRegA <= "1111";
CRegB <= "1111";
if (signed(RegAVal) < signed(inst(7 downto 0))) then
T_out <= '1';
else
T_out <= '0';
end if;
when "01011" => -- SLTUI
pc_sel <= "00";
pc_imm <= (others => '0');
RegWE <= '1';
MemWE <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
MemRd <= '0';
RegOpA <= "1111";
RegOpB <= "1111";
operandA <= (others => '0');
operandB <= (others => '0');
CReg <= '1';
CRegA <= "1111";
CRegB <= "1111";
if (unsigned(RegAVal) < unsigned(inst(7 downto 0))) then -- FIXME?
T_out <= '1';
else
T_out <= '0';
end if;
when "01101" => -- LI
pc_sel <= "00";
pc_imm <= (others => '0');
RegWE <= '1';
MemWE <= '0';
MemRd <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
RegOpA <= "1111";
RegOpB <= "1111";
operandA <= (others => '0');
operandB <= (others => '0');
-- RegDest is rx
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
opcode <= "1111";
operandA(7 downto 0) <= inst(7 downto 0);
operandA(15 downto 8) <= (others => '0');
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "01110" => -- CMPI
pc_sel <= "00";
pc_imm <= (others => '0');
RegWE <= '1';
RegDest <= "1111";
MemWE <= '0';
MemRd <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
RegOpA <= "1111";
RegOpB <= "1111";
operandA <= (others => '0');
operandB <= (others => '0');
CReg <= '1';
CRegA(2 downto 0) <= inst(10 downto 8); CRegA(3) <= '0';
CRegB <= "1111";
if (signed(RegAVal) = signed(inst(7 downto 0))) then -- FIXME?
T_out <= '0';
else
T_out <= '1';
end if;
when "10010" => -- LW_SP
pc_sel <= "00";
pc_imm <= (others => '0');
RegWE <= '1';
MemWE <= '0';
MemRd <= '1';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
RegOpA <= "1001";
RegOpB <= "1111";
-- RegDest is rx
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
opcode <= "0000";
operandA <= SPVal;
operandB(7 downto 0) <= inst(7 downto 0);
operandB(15 downto 8) <= (others => inst(7));
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "10011" => -- LW
pc_sel <= "00";
pc_imm <= (others => '0');
RegWE <= '1';
MemWE <= '0';
MemRd <= '1';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
RegOpA(2 downto 0) <= inst(10 downto 8);
RegOpA(3) <= '0';
RegOpB <= "1111";
-- RegDest is ry
RegDest(2 downto 0) <= inst(7 downto 5);
RegDest(3) <= '0';
opcode <= "0000";
operandA <= RegAVal;
operandB(4 downto 0) <= inst(4 downto 0);
operandB(15 downto 5) <= (others => inst(4));
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "11010" => -- SW_SP
pc_sel <= "00";
pc_imm <= (others => '0');
RegWE <= '0';
MemWE <= '1';
MemDIn <= RegAVal;
RegMemDIn(2 downto 0) <= inst(10 downto 8); RegMemDIn(3) <= '0';
MemRd <= '0';
RegOpA <= "1001";
RegOpB <= "1111";
opcode <= "0000";
operandA <= SPVal;
operandB(7 downto 0) <= inst(7 downto 0);
operandB(15 downto 8) <= (others => inst(7));
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "11011" => -- SW
pc_sel <= "00";
pc_imm <= (others => '0');
RegWE <= '0';
MemWE <= '1';
MemDIn <= RegBVal;
RegMemDIn(2 downto 0) <= inst(7 downto 5); RegMemDIn(3) <= '0';
MemRd <= '0';
RegOpA(2 downto 0) <= inst(10 downto 8);
RegOpA(3) <= '0';
RegOpB <= "1111";
opcode <= "0000";
operandA <= RegAVal;
operandB(4 downto 0) <= inst(4 downto 0);
operandB(15 downto 5) <= (others => inst(4));
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "00010" => -- B
RegWE <= '0';
MemWE <= '0';
MemRd <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
RegOpA <= "1111";
RegOpB <= "1111";
operandA <= (others => '0');
operandB <= (others => '0');
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
pc_imm(10 downto 0) <= inst(10 downto 0);
pc_imm(15 downto 11) <= (others => inst(10));
pc_sel <= "11";
T_out <= T_in;
when "00100" => -- BEQZ
RegWE <= '0';
MemWE <= '0';
MemRd <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
RegOpA <= "1111";
RegOpB <= "1111";
operandA <= (others => '0');
operandB <= (others => '0');
pc_imm(7 downto 0) <= inst(7 downto 0);
pc_imm(15 downto 8) <= (others => inst(7));
CReg <= '1';
CRegA(2 downto 0) <= inst(10 downto 8); CRegA(3) <= '0';
CRegB <= "1111";
T_out <= T_in;
if (RegAVal = "0000000000000000") then
pc_sel <= "11";
else
pc_sel <= "00";
end if;
when "00101" => -- BNEZ
RegWE <= '0';
MemWE <= '0';
MemRd <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
RegOpA <= "1111";
RegOpB <= "1111";
operandA <= (others => '0');
operandB <= (others => '0');
pc_imm(7 downto 0) <= inst(7 downto 0);
pc_imm(15 downto 8) <= (others => inst(7));
CReg <= '1';
CRegA(2 downto 0) <= inst(10 downto 8); CRegA(3) <= '0';
CRegB <= "1111";
T_out <= T_in;
if (RegAVal /= "0000000000000000") then
pc_sel <= "11";
else
pc_sel <= "00";
end if;
when others =>
RegWE <= '0';
MemWE <= '0';
MemRd <= '0';
RegMemDIn <= "1111";
MemDIn <= (others => '0');
RegOpA <= "1111";
RegOpB <= "1111";
operandA <= (others => '0');
operandB <= (others => '0');
pc_sel <= "00";
pc_imm <= (others => '0');
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
end case;
end process;
end Behavioral;
| gpl-2.0 | 091ebc15135389f9fd7039a912a5e818 | 0.309221 | 5.035085 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/StateMachineEditor_import.vhd | 2 | 1,225 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity StateMachineEditor_import is
port (
clock : in std_logic;
counter : in std_logic_vector(24-1 downto 0);
data_end : in std_logic;
ready : in std_logic;
reset : in std_logic;
state : out std_logic_vector(3-1 downto 0)
);
end entity StateMachineEditor_import;
architecture rtl of StateMachineEditor_import is
component StateMachineEditor_import_GN is
port (
clock : in std_logic;
counter : in std_logic_vector(24-1 downto 0);
data_end : in std_logic;
ready : in std_logic;
reset : in std_logic;
state : out std_logic_vector(3-1 downto 0)
);
end component StateMachineEditor_import_GN;
begin
StateMachineEditor_import_GN_0: if true generate
inst_StateMachineEditor_import_GN_0: StateMachineEditor_import_GN
port map(clock => clock, counter => counter, data_end => data_end, ready => ready, reset => reset, state => state);
end generate;
end architecture rtl;
| mit | 3f62991d8bd5f082e58b1386fb145709 | 0.733878 | 3.412256 | false | false | false | false |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_axi_iic_0_0/sim/tutorial_axi_iic_0_0.vhd | 1 | 9,257 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_iic:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_iic_v2_0;
USE axi_iic_v2_0.axi_iic;
ENTITY tutorial_axi_iic_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
iic2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
sda_i : IN STD_LOGIC;
sda_o : OUT STD_LOGIC;
sda_t : OUT STD_LOGIC;
scl_i : IN STD_LOGIC;
scl_o : OUT STD_LOGIC;
scl_t : OUT STD_LOGIC;
gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END tutorial_axi_iic_0_0;
ARCHITECTURE tutorial_axi_iic_0_0_arch OF tutorial_axi_iic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_axi_iic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_iic IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_IIC_FREQ : INTEGER;
C_TEN_BIT_ADR : INTEGER;
C_GPO_WIDTH : INTEGER;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_SCL_INERTIAL_DELAY : INTEGER;
C_SDA_INERTIAL_DELAY : INTEGER;
C_SDA_LEVEL : INTEGER;
C_SMBUS_PMBUS_HOST : INTEGER;
C_DEFAULT_VALUE : STD_LOGIC_VECTOR(7 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
iic2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
sda_i : IN STD_LOGIC;
sda_o : OUT STD_LOGIC;
sda_t : OUT STD_LOGIC;
scl_i : IN STD_LOGIC;
scl_o : OUT STD_LOGIC;
scl_t : OUT STD_LOGIC;
gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axi_iic;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF iic2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF sda_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_I";
ATTRIBUTE X_INTERFACE_INFO OF sda_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_O";
ATTRIBUTE X_INTERFACE_INFO OF sda_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_T";
ATTRIBUTE X_INTERFACE_INFO OF scl_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_I";
ATTRIBUTE X_INTERFACE_INFO OF scl_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_O";
ATTRIBUTE X_INTERFACE_INFO OF scl_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_T";
BEGIN
U0 : axi_iic
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_IIC_FREQ => 100000,
C_TEN_BIT_ADR => 0,
C_GPO_WIDTH => 1,
C_S_AXI_ACLK_FREQ_HZ => 76000000,
C_SCL_INERTIAL_DELAY => 0,
C_SDA_INERTIAL_DELAY => 0,
C_SDA_LEVEL => 1,
C_SMBUS_PMBUS_HOST => 0,
C_DEFAULT_VALUE => X"00"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
iic2intc_irpt => iic2intc_irpt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
sda_i => sda_i,
sda_o => sda_o,
sda_t => sda_t,
scl_i => scl_i,
scl_o => scl_o,
scl_t => scl_t,
gpo => gpo
);
END tutorial_axi_iic_0_0_arch;
| gpl-2.0 | 01fefe57edd5a3688ddeaf1ff2ebb074 | 0.678298 | 3.228811 | false | false | false | false |
adelapie/desl | key_schedule.vhd | 1 | 4,579 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity key_schedule is
port(clk : in std_logic;
rst : in std_logic;
mode : in std_logic; -- 0 encrypt, 1 decrypt
key : in std_logic_vector(55 downto 0);
key_out : out std_logic_vector(47 downto 0));
end key_schedule;
architecture Behavioral of key_schedule is
signal init_key_s : std_logic_vector(55 downto 0);
signal c_0_s : std_logic_vector(27 downto 0);
signal d_0_s : std_logic_vector(27 downto 0);
signal shift_s : std_logic_vector(15 downto 0);
signal key_pre_s : std_logic_vector(55 downto 0);
signal key_pre_delay_s : std_logic_vector(55 downto 0);
begin
pr_seq: process(clk, rst, key, shift_s(15), mode)
begin
if rst = '1' then
c_0_s <= key(55 downto 28);
d_0_s <= key(27 downto 0);
elsif rising_edge(clk) then
if shift_s(15) = '0' then
if mode = '0' then
c_0_s <= c_0_s(26 downto 0) & c_0_s(27);
d_0_s <= d_0_s(26 downto 0) & d_0_s(27);
else
c_0_s <= c_0_s(0) & c_0_s(27 downto 1);
d_0_s <= d_0_s(0) & d_0_s(27 downto 1);
end if;
else
if mode = '0' then
c_0_s <= c_0_s(25 downto 0) & c_0_s(27 downto 26);
d_0_s <= d_0_s(25 downto 0) & d_0_s(27 downto 26);
else
c_0_s <= c_0_s(1 downto 0) & c_0_s(27 downto 2);
d_0_s <= d_0_s(1 downto 0) & d_0_s(27 downto 2);
end if;
end if;
end if;
end process;
pr_shr: process(clk, rst, mode)
begin
if rst = '1' then
if mode = '0' then
shift_s <= "0011111101111110";
else
shift_s <= "0111111011111100";
end if;
elsif rising_edge(clk) then
shift_s <= shift_s(14 downto 0) & shift_s(15);
end if;
end process;
key_pre_s <= c_0_s & d_0_s;
pr_delay: process(clk, mode, key_pre_s)
begin
if rising_edge(clk) then
if mode = '1' then
key_pre_delay_s <= key_pre_s;
end if;
end if;
end process;
key_out <= (key_pre_s (42) & key_pre_s (39) & key_pre_s (45) & key_pre_s (32) & key_pre_s (55) & key_pre_s (51) & key_pre_s (53) & key_pre_s (28) &
key_pre_s (41) & key_pre_s (50) & key_pre_s (35) & key_pre_s (46) & key_pre_s (33) & key_pre_s (37) & key_pre_s (44) & key_pre_s (52) &
key_pre_s (30) & key_pre_s (48) & key_pre_s (40) & key_pre_s (49) & key_pre_s (29) & key_pre_s (36) & key_pre_s (43) & key_pre_s (54) &
key_pre_s (15) & key_pre_s (4) & key_pre_s (25) & key_pre_s (19) & key_pre_s (9) & key_pre_s (1) & key_pre_s (26) & key_pre_s (16) &
key_pre_s (5) & key_pre_s (11) & key_pre_s (23) & key_pre_s (8) & key_pre_s (12) & key_pre_s (7) & key_pre_s (17) & key_pre_s (0) &
key_pre_s (22) & key_pre_s (3) & key_pre_s (10) & key_pre_s (14) & key_pre_s (6) & key_pre_s (20) & key_pre_s (27) & key_pre_s (24))
when mode = '0' else
(key_pre_delay_s (42) & key_pre_delay_s (39) & key_pre_delay_s (45) & key_pre_delay_s (32) & key_pre_delay_s (55) & key_pre_delay_s (51) & key_pre_delay_s (53) & key_pre_delay_s (28) &
key_pre_delay_s (41) & key_pre_delay_s (50) & key_pre_delay_s (35) & key_pre_delay_s (46) & key_pre_delay_s (33) & key_pre_delay_s (37) & key_pre_delay_s (44) & key_pre_delay_s (52) &
key_pre_delay_s (30) & key_pre_delay_s (48) & key_pre_delay_s (40) & key_pre_delay_s (49) & key_pre_delay_s (29) & key_pre_delay_s (36) & key_pre_delay_s (43) & key_pre_delay_s (54) &
key_pre_delay_s (15) & key_pre_delay_s (4) & key_pre_delay_s (25) & key_pre_delay_s (19) & key_pre_delay_s (9) & key_pre_delay_s (1) & key_pre_delay_s (26) & key_pre_delay_s (16) &
key_pre_delay_s (5) & key_pre_delay_s (11) & key_pre_delay_s (23) & key_pre_delay_s (8) & key_pre_delay_s (12) & key_pre_delay_s (7) & key_pre_delay_s (17) & key_pre_delay_s (0) &
key_pre_delay_s (22) & key_pre_delay_s (3) & key_pre_delay_s (10) & key_pre_delay_s (14) & key_pre_delay_s (6) & key_pre_delay_s (20) & key_pre_delay_s (27) & key_pre_delay_s (24));
end Behavioral;
| gpl-3.0 | b50e92eda78e26dde686950b53ebd7bc | 0.59489 | 2.360309 | false | false | false | false |
freecores/t48 | rtl/vhdl/decoder_pack-p.vhd | 1 | 19,614 | -------------------------------------------------------------------------------
--
-- $Id: decoder_pack-p.vhd,v 1.4 2008-04-29 21:19:21 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
package t48_decoder_pack is
-----------------------------------------------------------------------------
-- The Mnemonics.
-----------------------------------------------------------------------------
type mnemonic_t is (MN_ADD,
MN_ADD_A_DATA,
MN_ANL,
MN_ANL_A_DATA,
MN_ANL_EXT,
MN_CALL,
MN_CLR_A,
MN_CLR_C,
MN_CLR_F,
MN_CPL_A,
MN_CPL_C,
MN_CPL_F,
MN_DA,
MN_DEC,
MN_DIS_EN_I,
MN_DIS_EN_TCNTI,
MN_DJNZ,
MN_ENT0_CLK,
MN_IN,
MN_INC,
MN_INS,
MN_JBB,
MN_JC,
MN_JF,
MN_JMP,
MN_JMPP,
MN_JNI,
MN_JT,
MN_JTF,
MN_JZ,
MN_MOV_A_DATA,
MN_MOV_A_PSW,
MN_MOV_A_RR,
MN_MOV_PSW_A,
MN_MOV_RR,
MN_MOV_RR_DATA,
MN_MOV_T,
MN_MOVD_A_PP,
MN_MOVP,
MN_MOVX,
MN_NOP,
MN_ORL,
MN_ORL_A_DATA,
MN_ORL_EXT,
MN_OUTD_PP_A,
MN_OUTL_EXT,
MN_RET,
MN_RL,
MN_RR,
MN_SEL_MB,
MN_SEL_RB,
MN_STOP_TCNT,
MN_STRT,
MN_SWAP,
MN_XCH,
MN_XRL,
MN_XRL_A_DATA);
type mnemonic_rec_t is
record
mnemonic : mnemonic_t;
multi_cycle : boolean;
end record;
function decode_opcode_f(opcode : in word_t) return
mnemonic_rec_t;
end t48_decoder_pack;
package body t48_decoder_pack is
function decode_opcode_f(opcode : in word_t) return
mnemonic_rec_t is
variable mnemonic_v : mnemonic_t;
variable multi_cycle_v : boolean;
variable result_v : mnemonic_rec_t;
begin
-- default assignment
mnemonic_v := MN_NOP;
multi_cycle_v := false;
case opcode is
-- Mnemonic ADD ---------------------------------------------------------
when "01101000" | "01101001" | "01101010" | "01101011" | -- ADD A, Rr
"01101100" | "01101101" | "01101110" | "01101111" | --
"01100000" | "01100001" | -- ADD A, @ Rr
"01111000" | "01111001" | "01111010" | "01111011" | -- ADDC A, Rr
"01111100" | "01111101" | "01111110" | "01111111" | --
"01110000" | "01110001" => -- ADDC A, @ Rr
mnemonic_v := MN_ADD;
-- Mnemonic ADD_A_DATA --------------------------------------------------
when "00000011" | -- ADD A, data
"00010011" => -- ADDC A, data
mnemonic_v := MN_ADD_A_DATA;
multi_cycle_v := true;
-- Mnemonic ANL ---------------------------------------------------------
when "01011000" | "01011001" | "01011010" | "01011011" | -- ANL A, Rr
"01011100" | "01011101" | "01011110" | "01011111" | --
"01010000" | "01010001" => -- ANL A, @ Rr
mnemonic_v := MN_ANL;
-- Mnemonic ANL_A_DATA --------------------------------------------------
when "01010011" => -- ANL A, data
mnemonic_v := MN_ANL_A_DATA;
multi_cycle_v := true;
-- Mnemonic ANL_EXT -----------------------------------------------------
when "10011000" | -- ANL BUS, data
"10011001" | "10011010" => -- ANL PP, data
mnemonic_v := MN_ANL_EXT;
multi_cycle_v := true;
-- Mnemonic CALL --------------------------------------------------------
when "00010100" | "00110100" | "01010100" | "01110100" | -- CALL addr
"10010100" | "10110100" | "11010100" | "11110100" => --
mnemonic_v := MN_CALL;
multi_cycle_v := true;
-- Mnemonic CLR_A -------------------------------------------------------
when "00100111" => -- CLR A
mnemonic_v := MN_CLR_A;
-- Mnemonic CLR_C -------------------------------------------------------
when "10010111" => -- CLR C
mnemonic_v := MN_CLR_C;
-- Mnemonic CLR_F -------------------------------------------------------
when "10000101" | -- CLR F0
"10100101" =>
mnemonic_v := MN_CLR_F;
-- Mnemonic CPL_A -------------------------------------------------------
when "00110111" => -- CPL A
mnemonic_v := MN_CPL_A;
-- Mnemonic CPL_C -------------------------------------------------------
when "10100111" => -- CPL C
mnemonic_v := MN_CPL_C;
-- Mnemonic CPL_F -------------------------------------------------------
when "10010101" | -- CPL F0
"10110101" => -- CPL F1
mnemonic_v := MN_CPL_F;
-- Mnemonic DA ----------------------------------------------------------
when "01010111" => -- DA D
mnemonic_v := MN_DA;
-- Mnemonic DEC ---------------------------------------------------------
when "11001000" | "11001001" | "11001010" | "11001011" | -- DEC Rr
"11001100" | "11001101" | "11001110" | "11001111" | --
"00000111" => -- DEC A
mnemonic_v := MN_DEC;
-- Mnemonic DIS_EN_I ----------------------------------------------------
when "00010101" | -- DIS I
"00000101" => -- EN I
mnemonic_v := MN_DIS_EN_I;
-- Mnemonic DIS_EN_TCNTI ------------------------------------------------
when "00110101" | -- DIS TCNTI
"00100101" => -- EN TCNTI
mnemonic_v := MN_DIS_EN_TCNTI;
-- Mnemonic DJNZ --------------------------------------------------------
when "11101000" | "11101001" | "11101010" | "11101011" | -- DJNZ Rr, addr
"11101100" | "11101101" | "11101110" | "11101111" => --
mnemonic_v := MN_DJNZ;
multi_cycle_v := true;
-- Mnemonic ENT0_CLK ----------------------------------------------------
when "01110101" => -- ENT0 CLK
mnemonic_v := MN_ENT0_CLK;
-- Mnemonic IN ----------------------------------------------------------
when "00001001" | "00001010" => -- IN A, Pp
mnemonic_v := MN_IN;
multi_cycle_v := true;
-- Mnemonic INC ---------------------------------------------------------
when "00010111" | -- INC A
"00011000" | "00011001" | "00011010" | "00011011" | -- INC Rr
"00011100" | "00011101" | "00011110" | "00011111" | --
"00010000" | "00010001" => -- INC @ Rr
mnemonic_v := MN_INC;
-- Mnemonic INS ---------------------------------------------------------
when "00001000" => -- INS A, BUS
mnemonic_v := MN_INS;
multi_cycle_v := true;
-- Mnemonic JBB ---------------------------------------------------------
when "00010010" | "00110010" | "01010010" | "01110010" | -- JBb addr
"10010010" | "10110010" | "11010010" | "11110010" => --
mnemonic_v := MN_JBB;
multi_cycle_v := true;
-- Mnemonic JC ----------------------------------------------------------
when "11110110" | -- JC addr
"11100110" => -- JNC addr
mnemonic_v := MN_JC;
multi_cycle_v := true;
-- Mnemonic JF ----------------------------------------------------------
when "10110110" | -- JF0 addr
"01110110" => -- JF1 addr
mnemonic_v := MN_JF;
multi_cycle_v := true;
-- Mnemonic JMP ---------------------------------------------------------
when "00000100" | "00100100" | "01000100" | "01100100" | -- JMP addr
"10000100" | "10100100" | "11000100" | "11100100" => --
mnemonic_v := MN_JMP;
multi_cycle_v := true;
-- Mnemonic JMPP --------------------------------------------------------
when "10110011" => -- JMPP @ A
mnemonic_v := MN_JMPP;
multi_cycle_v := true;
-- Mnemonic JNI ---------------------------------------------------------
when "10000110" => -- JNI addr
mnemonic_v := MN_JNI;
multi_cycle_v := true;
-- Mnemonic JT ----------------------------------------------------------
when "00100110" | -- JNT0 addr
"01000110" | -- JNT1 addr
"00110110" | -- JT0 addr
"01010110" => -- JT1 addr
mnemonic_v := MN_JT;
multi_cycle_v := true;
-- Mnemonic JTF ---------------------------------------------------------
when "00010110" => -- JTF addr
mnemonic_v := MN_JTF;
multi_cycle_v := true;
-- Mnemonic JZ ----------------------------------------------------------
when "10010110" | -- JNZ addr
"11000110" => -- JZ addr
mnemonic_v := MN_JZ;
multi_cycle_v := true;
-- Mnemonic MOV_A_DATA --------------------------------------------------
when "00100011" => -- MOV A, data
mnemonic_v := MN_MOV_A_DATA;
multi_cycle_v := true;
-- Mnemonic MOV_A_PSW ---------------------------------------------------
when "11000111" => -- MOV A, PSW
mnemonic_v := MN_MOV_A_PSW;
-- Mnemonic MOV_A_RR ----------------------------------------------------
when "11111000" | "11111001" | "11111010" | "11111011" | -- MOV A, Rr
"11111100" | "11111101" | "11111110" | "11111111" | --
"11110000" | "11110001" => -- MOV A, @ Rr
mnemonic_v := MN_MOV_A_RR;
-- Mnemonic MOV_PSW_A ---------------------------------------------------
when "11010111" => -- MOV PSW, A
mnemonic_v := MN_MOV_PSW_A;
-- Mnemonic MOV_RR ------------------------------------------------------
when "10101000" | "10101001" | "10101010" | "10101011" | -- MOV Rr, A
"10101100" | "10101101" | "10101110" | "10101111" | --
"10100000" | "10100001" => -- MOV @ Rr, A
mnemonic_v := MN_MOV_RR;
-- Mnemonic MOV_RR_DATA -------------------------------------------------
when "10111000" | "10111001" | "10111010" | "10111011" | -- MOV Rr, data
"10111100" | "10111101" | "10111110" | "10111111" | --
"10110000" | "10110001" => -- MOV @ Rr, data
mnemonic_v := MN_MOV_RR_DATA;
multi_cycle_v := true;
-- Mnemonic MOV_T -------------------------------------------------------
when "01100010" | -- MOV T, A
"01000010" => -- MOV A, T
mnemonic_v := MN_MOV_T;
-- Mnemonic MOVD_A_PP ---------------------------------------------------
when "00001100" | "00001101" | "00001110" | "00001111" => -- MOVD A, Pp
mnemonic_v := MN_MOVD_A_PP;
multi_cycle_v := true;
-- Mnemonic MOVP --------------------------------------------------------
when "10100011" | -- MOVP A, @ A
"11100011" => -- MOVP3 A, @ A
mnemonic_v := MN_MOVP;
multi_cycle_v := true;
-- Mnemonic MOVX --------------------------------------------------------
when "10000000" | "10000001" | -- MOVX A, @ Rr
"10010000" | "10010001" => -- MOVX @ Rr, A
mnemonic_v := MN_MOVX;
multi_cycle_v := true;
-- Mnemonic NOP ---------------------------------------------------------
when "00000000" => -- NOP
mnemonic_v := MN_NOP;
-- Mnemonic ORL ---------------------------------------------------------
when "01001000" | "01001001" | "01001010" | "01001011" | -- ORL A, Rr
"01001100" | "01001101" | "01001110" | "01001111" | --
"01000000" | "01000001" => -- ORL A, @ Rr
mnemonic_v := MN_ORL;
-- Mnemonic ORL_A_DATA --------------------------------------------------
when "01000011" => -- ORL A, data
mnemonic_v := MN_ORL_A_DATA;
multi_cycle_v := true;
-- Mnemonic ORL_EXT -----------------------------------------------------
when "10001000" | -- ORL BUS, data
"10001001" | "10001010" => -- ORL Pp, data
mnemonic_v := MN_ORL_EXT;
multi_cycle_v := true;
-- Mnemonic OUTD_PP_A ---------------------------------------------------
when "00111100" | "00111101" | "00111110" | "00111111" | -- MOVD Pp, A
"10011100" | "10011101" | "10011110" | "10011111" | -- ANLD PP, A
"10001100" | "10001101" | "10001110" | "10001111" => -- ORLD Pp, A
mnemonic_v := MN_OUTD_PP_A;
multi_cycle_v := true;
-- Mnemonic OUTL_EXT ----------------------------------------------------
when "00111001" | "00111010" | -- OUTL Pp, A
"00000010" => -- OUTL BUS, A
mnemonic_v := MN_OUTL_EXT;
multi_cycle_v := true;
-- Mnemonic RET ---------------------------------------------------------
when "10000011" | -- RET
"10010011" => -- RETR
mnemonic_v := MN_RET;
multi_cycle_v := true;
-- Mnemonic RL ----------------------------------------------------------
when "11100111" | -- RL A
"11110111" => -- RLC A
mnemonic_v := MN_RL;
-- Mnemonic RR ----------------------------------------------------------
when "01110111" | -- RR A
"01100111" => -- RRC A
mnemonic_v := MN_RR;
-- Mnemonic SEL_MB ------------------------------------------------------
when "11100101" | -- SEL MB0
"11110101" => -- SEL MB1
mnemonic_v := MN_SEL_MB;
-- Mnemonic SEL_RB ------------------------------------------------------
when "11000101" | -- SEL RB0
"11010101" => -- SEL RB1
mnemonic_v := MN_SEL_RB;
-- Mnemonic STOP_TCNT ---------------------------------------------------
when "01100101" => -- STOP TCNT
mnemonic_v := MN_STOP_TCNT;
-- Mnemonic START -------------------------------------------------------
when "01000101" | -- STRT CNT
"01010101" => -- STRT T
mnemonic_v := MN_STRT;
-- Mnemonic SWAP --------------------------------------------------------
when "01000111" => -- SWAP A
mnemonic_v := MN_SWAP;
-- Mnemonic XCH ---------------------------------------------------------
when "00101000" | "00101001" | "00101010" | "00101011" | -- XCH A, Rr
"00101100" | "00101101" | "00101110" | "00101111" | --
"00100000" | "00100001" | -- XCH A, @ Rr
"00110000" | "00110001" => -- XCHD A, @ Rr
mnemonic_v := MN_XCH;
-- Mnemonic XRL ---------------------------------------------------------
when "11011000" | "11011001" | "11011010" | "11011011" | -- XRL A, Rr
"11011100" | "11011101" | "11011110" | "11011111" | --
"11010000" | "11010001" => -- XRL A, @ Rr
mnemonic_v := MN_XRL;
-- Mnemonic XRL_A_DATA --------------------------------------------------
when "11010011" => -- XRL A, data
mnemonic_v := MN_XRL_A_DATA;
multi_cycle_v := true;
when others =>
-- pragma translate_off
assert now = 0 ns
report "Unknown opcode."
severity warning;
-- pragma translate_on
end case;
result_v.mnemonic := mnemonic_v;
result_v.multi_cycle := multi_cycle_v;
return result_v;
end;
end t48_decoder_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.3 2005/06/11 10:08:43 arniml
-- introduce prefix 't48_' for all packages, entities and configurations
--
-- Revision 1.2 2004/03/28 13:09:53 arniml
-- merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | cd036b9e5c87b3d0e00e1db09d4058a7 | 0.307943 | 5.161579 | false | false | false | false |
nulldozer/purisc | Compute_Group/CORE/read_instruction_stage.vhd | 1 | 1,599 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- This stage just updates the PC and requests the proper address from memory.
-- Memory sends the result directly to the next stage
entity read_instruction_stage is
port(
clk : in std_logic;
reset_n : in std_logic;
stall : in std_logic;
start_address : in std_logic_vector(31 downto 0);
cbranch : in std_logic;
cbranch_addr : in std_logic_vector(31 downto 0);
ubranch : in std_logic;
ubranch_addr : in std_logic_vector(31 downto 0);
--outputs
next_pc : out std_logic_vector(31 downto 0);
--memory
r_addr_inst : out std_logic_vector(31 downto 0)
);
end entity;
architecture a1 of read_instruction_stage is
signal pc : std_logic_vector(31 downto 0);
begin
with reset_n select
r_addr_inst <= pc when '1', start_address when others;
process(clk, reset_n, start_address) begin
if (reset_n = '0') then
pc <= start_address;
next_pc <= std_logic_vector(unsigned(start_address)+to_unsigned(3,32));
elsif (rising_edge(clk)) then
if(stall = '0') then
if (cbranch = '1') then
pc <= cbranch_addr;
next_pc <= std_logic_vector(unsigned(cbranch_addr) + to_unsigned(3,32));
elsif (ubranch = '1') then
pc <= ubranch_addr;
next_pc <= std_logic_vector(unsigned(ubranch_addr) + to_unsigned(3,32));
else
pc <= std_logic_vector(unsigned(pc) + to_unsigned(3,32));
next_pc <= std_logic_vector(unsigned(pc) + to_unsigned(6,32));
end if;
else
--hold previous value on stall (automatic)
end if;
end if;
end process;
end architecture; | gpl-2.0 | 8aa7f8f10d1160eac685452f821b59d4 | 0.665416 | 2.933945 | false | false | false | false |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_v_tpg_0_0/sim/tutorial_v_tpg_0_0.vhd | 1 | 11,780 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:v_tpg:6.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY v_tpg_v6_0;
USE v_tpg_v6_0.v_tpg;
ENTITY tutorial_v_tpg_0_0 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
irq : OUT STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
m_axis_video_tuser : OUT STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END tutorial_v_tpg_0_0;
ARCHITECTURE tutorial_v_tpg_0_0_arch OF tutorial_v_tpg_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_v_tpg_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT v_tpg IS
GENERIC (
C_S_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_S_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
C_S_AXIS_VIDEO_FORMAT : INTEGER;
C_M_AXIS_VIDEO_FORMAT : INTEGER;
C_S_AXIS_VIDEO_TUSER_WIDTH : INTEGER;
C_M_AXIS_VIDEO_TUSER_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_CLK_FREQ_HZ : INTEGER;
C_ACTIVE_ROWS : INTEGER;
C_ACTIVE_COLS : INTEGER;
C_PATTERN_CONTROL : INTEGER;
C_MOTION_SPEED : INTEGER;
C_CROSS_HAIRS : INTEGER;
C_ZPLATE_HOR_CONTROL : INTEGER;
C_ZPLATE_VER_CONTROL : INTEGER;
C_BOX_SIZE : INTEGER;
C_BOX_COLOR : INTEGER;
C_STUCK_PIXEL_THRESH : INTEGER;
C_NOISE_GAIN : INTEGER;
C_BAYER_PHASE : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_HAS_AXI4_LITE : INTEGER;
C_HAS_VTIMING : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
intc_if : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
irq : OUT STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
s_axis_video_tuser : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
m_axis_video_tuser : OUT STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
hblank_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
vblank_in : IN STD_LOGIC;
active_video_in : IN STD_LOGIC
);
END COMPONENT v_tpg;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF irq: SIGNAL IS "xilinx.com:signal:interrupt:1.0 irq_intf INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TUSER";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 s_axi_aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RREADY";
BEGIN
U0 : v_tpg
GENERIC MAP (
C_S_AXIS_VIDEO_DATA_WIDTH => 8,
C_M_AXIS_VIDEO_DATA_WIDTH => 8,
C_S_AXIS_VIDEO_TDATA_WIDTH => 16,
C_M_AXIS_VIDEO_TDATA_WIDTH => 8,
C_S_AXIS_VIDEO_FORMAT => 0,
C_M_AXIS_VIDEO_FORMAT => 12,
C_S_AXIS_VIDEO_TUSER_WIDTH => 0,
C_M_AXIS_VIDEO_TUSER_WIDTH => 1,
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_CLK_FREQ_HZ => 100000000,
C_ACTIVE_ROWS => 1080,
C_ACTIVE_COLS => 1920,
C_PATTERN_CONTROL => 4106,
C_MOTION_SPEED => 0,
C_CROSS_HAIRS => 6553700,
C_ZPLATE_HOR_CONTROL => 30,
C_ZPLATE_VER_CONTROL => 1,
C_BOX_SIZE => 50,
C_BOX_COLOR => 0,
C_STUCK_PIXEL_THRESH => 0,
C_NOISE_GAIN => 0,
C_BAYER_PHASE => 2,
C_HAS_INTC_IF => 0,
C_HAS_AXI4_LITE => 1,
C_HAS_VTIMING => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => aresetn,
irq => irq,
s_axis_video_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_video_tvalid => '0',
s_axis_video_tlast => '0',
s_axis_video_tuser => '0',
m_axis_video_tdata => m_axis_video_tdata,
m_axis_video_tvalid => m_axis_video_tvalid,
m_axis_video_tready => m_axis_video_tready,
m_axis_video_tlast => m_axis_video_tlast,
m_axis_video_tuser => m_axis_video_tuser,
s_axi_aclk => s_axi_aclk,
s_axi_aclken => s_axi_aclken,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
hsync_in => '0',
hblank_in => '0',
vsync_in => '1',
vblank_in => '0',
active_video_in => '0'
);
END tutorial_v_tpg_0_0_arch;
| gpl-2.0 | 12b8e4769d2da3baa99e1a546aa324c6 | 0.669015 | 3.227397 | false | false | false | false |
freecores/t48 | rtl/vhdl/p1.vhd | 1 | 5,101 | -------------------------------------------------------------------------------
--
-- The Port 1 unit.
-- Implements the Port 1 logic.
--
-- $Id: p1.vhd,v 1.5 2005-06-11 10:08:43 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
entity t48_p1 is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
write_p1_i : in boolean;
read_p1_i : in boolean;
read_reg_i : in boolean;
-- Port 1 Interface -------------------------------------------------------
p1_i : in word_t;
p1_o : out word_t;
p1_low_imp_o : out std_logic
);
end t48_p1;
use work.t48_pack.clk_active_c;
use work.t48_pack.res_active_c;
use work.t48_pack.bus_idle_level_c;
architecture rtl of t48_p1 is
-- the port output register
signal p1_q : word_t;
-- the low impedance marker
signal low_imp_q : std_logic;
begin
-----------------------------------------------------------------------------
-- Process p1_reg
--
-- Purpose:
-- Implements the port output register.
--
p1_reg: process (res_i, clk_i)
begin
if res_i = res_active_c then
p1_q <= (others => '1');
low_imp_q <= '0';
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
if write_p1_i then
p1_q <= data_i;
low_imp_q <= '1';
else
low_imp_q <= '0';
end if;
end if;
end if;
end process p1_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process p1_data
--
-- Purpose:
-- Generates the T48 bus data.
--
p1_data: process (read_p1_i,
p1_i,
read_reg_i,
p1_q)
begin
data_o <= (others => bus_idle_level_c);
if read_p1_i then
if read_reg_i then
data_o <= p1_q;
else
data_o <= p1_i;
end if;
end if;
end process p1_data;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
p1_o <= p1_q;
p1_low_imp_o <= low_imp_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.3 2004/05/17 14:37:53 arniml
-- reorder data_o generation
--
-- Revision 1.2 2004/03/29 19:39:58 arniml
-- rename pX_limp to pX_low_imp
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | cae51e62dbdbe2198d9476b6b07f5eaf | 0.516173 | 4.084067 | false | false | false | false |
nulldozer/purisc | Compute_Group/Compute_Group.vhd | 2 | 17,780 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Compute_Group is
PORT (
ADDRESS_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
IO_ENABLE : IN STD_LOGIC;
DATA_TO_W : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
GLOBAL_EN : OUT STD_LOGIC;
IDENT_IN : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
DATA_OUT_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
STALL_GLOB : IN STD_LOGIC
);
end;
architecture cg of Compute_Group is
component MAGIC
PORT (
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
HAZ_GLOB : IN STD_LOGIC;
DATA_OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
C0_STALL : OUT STD_LOGIC;
C1_STALL : OUT STD_LOGIC;
CORE_IDENT : OUT STD_LOGIC;
IO_ENABLE : IN STD_LOGIC
);
end component;
component LOAD_BALANCER
PORT (
CORE_ID : IN STD_LOGIC;
ADDRESS_A_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_C0 : IN STD_LOGIC;
ADDRESS_A_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_C1 : IN STD_LOGIC;
ADDRESS_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
IO_ENABLE : IN STD_LOGIC;
global_enable : IN STD_LOGIC_VECTOR (5 downto 0);
ADDRESS_A_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_MAG : OUT STD_LOGIC
);
end component;
component purisc_core
PORT (
clk, reset_n : in std_logic;
r_addr_a, r_addr_b, r_addr_c, r_addr_0, r_addr_1 : out std_logic_vector(31 downto 0);
w_data, w_addr : out std_logic_vector(31 downto 0);
we : out std_logic;
stall : in std_logic;
id : in std_logic_vector(2 downto 0);
r_data_a, r_data_b, r_data_c,
r_data_0, r_data_1 : in std_logic_vector(31 downto 0)
);
end component;
component BIST_core
PORT (
clk, reset_n : in std_logic;
r_addr_a, r_addr_b, r_addr_c, r_addr_0, r_addr_1 : out std_logic_vector(31 downto 0);
w_data, w_addr : out std_logic_vector(31 downto 0);
we : out std_logic;
stall : in std_logic;
id : in std_logic_vector(2 downto 0);
r_data_a, r_data_b, r_data_c,
r_data_0, r_data_1 : in std_logic_vector(31 downto 0)
);
end component;
signal address_a_sig : std_logic_vector(31 downto 0);
signal address_b_sig : std_logic_vector(31 downto 0);
signal address_c_sig : std_logic_vector(31 downto 0);
signal address_0_sig : std_logic_vector(31 downto 0);
signal address_1_sig : std_logic_vector(31 downto 0);
signal address_w_sig : std_logic_vector(31 downto 0);
signal data_to_w_sig : std_logic_vector(31 downto 0);
signal w_en_sig : std_logic;
signal w_en_local : std_logic;
signal w_en_global : std_logic;
signal address_a_sig_c0 : std_logic_vector(31 downto 0);
signal address_b_sig_c0 : std_logic_vector(31 downto 0);
signal address_c_sig_c0 : std_logic_vector(31 downto 0);
signal address_0_sig_c0 : std_logic_vector(31 downto 0);
signal address_1_sig_c0 : std_logic_vector(31 downto 0);
signal address_w_sig_c0 : std_logic_vector(31 downto 0);
signal data_to_w_sig_c0 : std_logic_vector(31 downto 0);
signal w_en_sig_c0 : std_logic;
signal address_a_sig_c1 : std_logic_vector(31 downto 0);
signal address_b_sig_c1 : std_logic_vector(31 downto 0);
signal address_c_sig_c1 : std_logic_vector(31 downto 0);
signal address_0_sig_c1 : std_logic_vector(31 downto 0);
signal address_1_sig_c1 : std_logic_vector(31 downto 0);
signal address_w_sig_c1 : std_logic_vector(31 downto 0);
signal data_to_w_sig_c1 : std_logic_vector(31 downto 0);
signal w_en_sig_c1 : std_logic;
signal data_a : std_logic_vector(31 downto 0);
signal data_b : std_logic_vector(31 downto 0);
signal data_c : std_logic_vector(31 downto 0);
signal data_0 : std_logic_vector(31 downto 0);
signal data_1 : std_logic_vector(31 downto 0);
signal data_a_final : std_logic_vector(31 downto 0);
signal data_b_final : std_logic_vector(31 downto 0);
signal data_c_final : std_logic_vector(31 downto 0);
signal data_0_final : std_logic_vector(31 downto 0);
signal data_1_final : std_logic_vector(31 downto 0);
signal data_a_c0_buff : std_logic_vector(31 downto 0);
signal data_b_c0_buff : std_logic_vector(31 downto 0);
signal data_c_c0_buff : std_logic_vector(31 downto 0);
signal data_0_c0_buff : std_logic_vector(31 downto 0);
signal data_1_c0_buff : std_logic_vector(31 downto 0);
signal data_a_c1 : std_logic_vector(31 downto 0);
signal data_b_c1 : std_logic_vector(31 downto 0);
signal data_c_c1 : std_logic_vector(31 downto 0);
signal data_0_c1 : std_logic_vector(31 downto 0);
signal data_1_c1 : std_logic_vector(31 downto 0);
signal data_a_c1_buff : std_logic_vector(31 downto 0);
signal data_b_c1_buff : std_logic_vector(31 downto 0);
signal data_c_c1_buff : std_logic_vector(31 downto 0);
signal data_0_c1_buff : std_logic_vector(31 downto 0);
signal data_1_c1_buff : std_logic_vector(31 downto 0);
signal stall_c0 : std_logic;
signal stall_c1 : std_logic;
signal stall_c0_io : std_logic;
signal stall_c1_io : std_logic;
signal core_id : std_logic;
signal io_buffer_en : std_logic;
signal flags_0 : std_logic_vector(2 downto 0);
signal flags_1 : std_logic_vector(2 downto 0);
signal global_enable : std_logic_vector(5 downto 0);
signal global_enable_delayed : std_logic_vector(5 downto 0);
signal global_enable_delayed_2 : std_logic_vector(5 downto 0);
signal global_data_buffer_flag_delay : std_logic;
signal global_data_buffer_flag : std_logic;
signal global_buffer_enable : std_logic;
signal global_data_feed_a : std_logic_vector(31 downto 0);
signal global_data_feed_b : std_logic_vector(31 downto 0);
signal global_data_feed_c : std_logic_vector(31 downto 0);
signal global_data_feed_0 : std_logic_vector(31 downto 0);
signal global_data_feed_1 : std_logic_vector(31 downto 0);
signal global_data_buffer_a : std_logic_vector(31 downto 0);
signal global_data_buffer_b : std_logic_vector(31 downto 0);
signal global_data_buffer_c : std_logic_vector(31 downto 0);
signal global_data_buffer_0 : std_logic_vector(31 downto 0);
signal global_data_buffer_1 : std_logic_vector(31 downto 0);
signal hold_local : std_logic;
signal hazard : std_logic;
signal override_global : std_logic;
signal startup_hold_1 : std_logic;
signal startup_hold_2 : std_logic;
signal startup_hold_3 : std_logic;
signal startup_hold_4 : std_logic;
signal startup_hold_5 : std_logic;
signal FUCK : std_logic;
signal dick : std_logic;
begin
core_0 : purisc_core PORT MAP(
clk => CLK,
reset_n => RESET_n,
r_addr_a => address_a_sig_c0,
r_addr_b => address_b_sig_c0,
r_addr_c => address_c_sig_c0,
r_addr_0 => address_0_sig_c0,
r_addr_1 => address_1_sig_c0,
w_addr => address_w_sig_c0,
we => w_en_sig_c0,
w_data => data_to_w_sig_c0,
stall => stall_c0_io,
id => flags_0,
r_data_a => data_a_final,
r_data_b => data_b_final,
r_data_c => data_c_final,
r_data_0 => data_0_final,
r_data_1 => data_1_final
);
core_1 : purisc_core PORT MAP(
clk => CLK,
reset_n => RESET_n,
r_addr_a => address_a_sig_c1,
r_addr_b => address_b_sig_c1,
r_addr_c => address_c_sig_c1,
r_addr_0 => address_0_sig_c1,
r_addr_1 => address_1_sig_c1,
w_addr => address_w_sig_c1,
we => w_en_sig_c1,
w_data => data_to_w_sig_c1,
stall => stall_c1_io,
id => flags_1,
r_data_a => data_a_final,
r_data_b => data_b_final,
r_data_c => data_c_final,
r_data_0 => data_0_final,
r_data_1 => data_1_final
);
cache : MAGIC PORT MAP (
ADDRESS_A => address_a_sig,
ADDRESS_B => address_b_sig,
ADDRESS_C => address_c_sig,
ADDRESS_0 => address_0_sig,
ADDRESS_1 => address_1_sig,
ADDRESS_W => address_w_sig,
DATA_TO_W => data_to_w_sig,
W_EN => w_en_local,
CLK => CLK,
RESET_n => RESET_n,
HAZ_GLOB => STALL_GLOB,
DATA_OUT_A => data_a,
DATA_OUT_B => data_b,
DATA_OUT_C => data_c,
DATA_OUT_0 => data_0,
DATA_OUT_1 => data_1,
C0_STALL => stall_c0,
C1_STALL => stall_c1,
CORE_IDENT => core_id,
IO_ENABLE => hold_local
);
balance : LOAD_BALANCER PORT MAP(
CORE_ID => core_id,
ADDRESS_A_C0 => address_a_sig_c0,
ADDRESS_B_C0 => address_b_sig_c0,
ADDRESS_C_C0 => address_c_sig_c0,
ADDRESS_0_C0 => address_0_sig_c0,
ADDRESS_1_C0 => address_1_sig_c0,
ADDRESS_W_C0 => address_w_sig_c0,
DATA_TO_W_C0 => data_to_w_sig_c0,
W_EN_C0 => w_en_sig_c0,
ADDRESS_A_C1 => address_a_sig_c1,
ADDRESS_B_C1 => address_b_sig_c1,
ADDRESS_C_C1 => address_c_sig_c1,
ADDRESS_0_C1 => address_0_sig_c1,
ADDRESS_1_C1 => address_1_sig_c1,
ADDRESS_W_C1 => address_w_sig_c1,
DATA_TO_W_C1 => data_to_w_sig_c1,
W_EN_C1 => w_en_sig_c1,
ADDRESS_IO => ADDRESS_IO,
DATA_IO => DATA_IO,
IO_ENABLE => IO_ENABLE,
global_enable => global_enable,
ADDRESS_A_MAG => address_a_sig,
ADDRESS_B_MAG => address_b_sig,
ADDRESS_C_MAG => address_c_sig,
ADDRESS_0_MAG => address_0_sig,
ADDRESS_1_MAG => address_1_sig,
ADDRESS_W_MAG => address_w_sig,
DATA_TO_W_MAG => data_to_w_sig,
W_EN_MAG => w_en_sig
);
process (CLK, RESET_n) begin
if (RESET_n = '0') then
startup_hold_1 <= '1';
startup_hold_2 <= '1';
startup_hold_3 <= '1';
startup_hold_4 <= '1';
startup_hold_5 <= '1';
elsif (rising_edge(CLK)) then
startup_hold_1 <= not RESET_n;
startup_hold_2 <= startup_hold_1;
startup_hold_3 <= startup_hold_2;
startup_hold_4 <= startup_hold_3;
startup_hold_5 <= startup_hold_4;
end if;
end process;
process (CLK, RESET_n) begin
if (RESET_n = '0') then
override_global <= '1';
elsif (rising_edge(CLK)) then
if ((STALL_GLOB = '0') and (hazard = '1')) then
override_global <= '0';
else
override_global <= '1';
end if;
end if;
end process;
process (CLK, RESET_n) begin
if (RESET_n = '0') then
global_enable_delayed <= "000000";
global_enable_delayed_2 <= "000000";
elsif (rising_edge(CLK)) then
global_enable_delayed_2 <= global_enable_delayed;
if ((stall_c0_io and stall_c1_io) = '0') then --OR STALL GLOBAL = 0
global_enable_delayed <= global_enable;
end if;
end if;
end process;
process (CLK, RESET_n) begin
if (RESET_n = '0') then
global_data_buffer_flag_delay <= '0';
--FUCK <= '0';
elsif (rising_edge(CLK)) then
global_data_buffer_flag_delay <= global_data_buffer_flag;
--FUCK <= dick;
end if;
end process;
global_buffer_enable <= (global_data_buffer_flag_delay xor global_data_buffer_flag) and global_data_buffer_flag;
process (CLK, RESET_n) begin
if (RESET_n = '0') then
global_data_buffer_a <= "00000000000000000000000000000000";
global_data_buffer_b <= "00000000000000000000000000000000";
global_data_buffer_c <= "00000000000000000000000000000000";
global_data_buffer_0 <= "00000000000000000000000000000000";
global_data_buffer_1 <= "00000000000000000000000000000000";
elsif (rising_edge(CLK)) then
if (global_buffer_enable = '1') then
global_data_buffer_a <= DATA_OUT_A;
global_data_buffer_b <= DATA_OUT_B;
global_data_buffer_c <= DATA_OUT_C;
global_data_buffer_0 <= DATA_OUT_0;
global_data_buffer_1 <= DATA_OUT_1;
end if;
end if;
end process;
process (global_enable, global_enable_delayed, global_enable_delayed_2, DATA_OUT_A, DATA_OUT_B, DATA_OUT_C,
DATA_OUT_0, DATA_OUT_1, global_data_buffer_a, global_data_buffer_b, global_data_buffer_c,
global_data_buffer_0, global_data_buffer_1, hazard) begin
if ((global_enable_delayed = global_enable_delayed_2) and
((global_enable(5) or global_enable(4) or global_enable(3) or global_enable(2) or
global_enable(1) or global_enable(0)) = '1')) then
global_data_buffer_flag <= hazard;
global_data_feed_a <= global_data_buffer_a;
global_data_feed_b <= global_data_buffer_b;
global_data_feed_c <= global_data_buffer_c;
global_data_feed_0 <= global_data_buffer_0;
global_data_feed_1 <= global_data_buffer_1;
else
global_data_buffer_flag <= '0';
global_data_feed_a <= DATA_OUT_A;
global_data_feed_b <= DATA_OUT_B;
global_data_feed_c <= DATA_OUT_C;
global_data_feed_0 <= DATA_OUT_0;
global_data_feed_1 <= DATA_OUT_1;
end if;
end process;
process (global_enable_delayed, data_a, data_b, data_c, data_0, data_1,
DATA_OUT_A, DATA_OUT_B, DATA_OUT_C, DATA_OUT_0, DATA_OUT_1, global_data_feed_a,
global_data_feed_b, global_data_feed_c, global_data_feed_0, global_data_feed_1) begin
if(global_enable_delayed(5) = '1') then
data_a_final <= global_data_feed_a;
else
data_a_final <= data_a;
end if;
if(global_enable_delayed(4) = '1') then
data_b_final <= global_data_feed_b;
else
data_b_final <= data_b;
end if;
if(global_enable_delayed(3) = '1') then
data_c_final <= global_data_feed_c;
else
data_c_final <= data_c;
end if;
if(global_enable_delayed(2) = '1') then
data_0_final <= global_data_feed_0;
else
data_0_final <= data_0;
end if;
if(global_enable_delayed(1) = '1') then
data_1_final <= global_data_feed_1;
else
data_1_final <= data_1;
end if;
end process;
flags_0 <= IDENT_IN & '0';
flags_1 <= IDENT_IN & '1';
ADDRESS_A <= address_a_sig;
ADDRESS_B <= address_b_sig;
ADDRESS_C <= address_c_sig;
ADDRESS_0 <= address_0_sig;
ADDRESS_1 <= address_1_sig;
ADDRESS_W <= address_w_sig;
DATA_TO_W <= data_to_w_sig;
W_EN <= w_en_global;
stall_c0_io <= (stall_c0 or IO_ENABLE or STALL_GLOB or startup_hold_5);
stall_c1_io <= (stall_c1 or IO_ENABLE or STALL_GLOB or startup_hold_5);
global_enable(5) <= address_a_sig(14) or address_a_sig(13) or address_a_sig(15); --a
global_enable(4) <= address_b_sig(14) or address_b_sig(13) or address_a_sig(15); --b
global_enable(3) <= address_c_sig(14) or address_c_sig(13) or address_a_sig(15); --c
global_enable(2) <= address_0_sig(14) or address_0_sig(13) or address_a_sig(15); --0
global_enable(1) <= address_1_sig(14) or address_1_sig(13) or address_a_sig(15); --1
global_enable(0) <= address_w_sig(14) or address_w_sig(13) or address_a_sig(15); --w
GLOBAL_EN <= dick;
dick <= (global_enable(5) or global_enable(4) or global_enable(3) or global_enable(2) or global_enable(1) or global_enable(0)) and override_global;
w_en_local <= w_en_sig and (not global_enable(0));
w_en_global <= w_en_sig and (global_enable(0));
hold_local <= IO_ENABLE or STALL_GLOB;
hazard <= stall_c0_io and stall_c1_io;
end; | gpl-2.0 | 711140e6f08f3dca9180390b30c5ecb4 | 0.604106 | 2.732442 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/altera_lnsim/common_28nm_ram_block/_primary.vhd | 5 | 9,979 | library verilog;
use verilog.vl_types.all;
entity common_28nm_ram_block is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
init_file_layout: string := "none";
ecc_pipeline_stage_enabled: string := "false";
enable_ecc : string := "false";
width_eccstatus : integer := 2;
port_a_first_address: integer := 0;
port_a_last_address: integer := 0;
port_a_data_out_clear: string := "none";
port_a_data_out_clock: string := "none";
port_a_data_width: integer := 1;
port_a_address_width: integer := 1;
port_a_byte_enable_mask_width: integer := 1;
port_b_first_address: integer := 0;
port_b_last_address: integer := 0;
port_b_address_clear: string := "none";
port_b_data_out_clear: string := "none";
port_b_data_in_clock: string := "clock1";
port_b_address_clock: string := "clock1";
port_b_write_enable_clock: string := "clock1";
port_b_read_enable_clock: string := "clock1";
port_b_byte_enable_clock: string := "clock1";
port_b_data_out_clock: string := "none";
port_b_data_width: integer := 1;
port_b_address_width: integer := 1;
port_b_byte_enable_mask_width: integer := 1;
power_up_uninitialized: string := "false";
mem_init0 : string := "";
mem_init1 : string := "";
mem_init2 : string := "";
mem_init3 : string := "";
mem_init4 : string := "";
mem_init5 : string := "";
mem_init6 : string := "";
mem_init7 : string := "";
mem_init8 : string := "";
mem_init9 : string := "";
clk0_input_clock_enable: string := "none";
clk0_core_clock_enable: string := "none";
clk0_output_clock_enable: string := "none";
clk1_input_clock_enable: string := "none";
clk1_core_clock_enable: string := "none";
clk1_output_clock_enable: string := "none";
bist_ena : string := "false";
port_a_address_clear: string := "none";
port_a_write_enable_clock: string := "clock0";
port_a_read_enable_clock: string := "clock0";
primary_port_is_a: vl_notype;
primary_port_is_b: vl_notype;
mode_is_dp : vl_notype;
mode_is_sp : vl_notype;
mode_is_rom : vl_notype;
mode_is_bdp : vl_notype;
mode_is_rom_or_sp: vl_notype;
mixed_port_rdw_is_dont_care: vl_notype;
out_a_is_reg : vl_notype;
out_b_is_reg : vl_notype;
data_width : vl_notype;
data_unit_width : vl_notype;
address_width : vl_notype;
address_unit_width: vl_notype;
wired_mode : vl_notype;
num_rows : vl_notype;
num_cols : vl_notype;
mask_width_prime: vl_notype;
mask_width_sec : vl_notype;
byte_size_a : vl_notype;
byte_size_b : vl_notype;
dual_clock : vl_notype;
hw_write_mode_a : vl_notype;
hw_write_mode_b : vl_notype;
delay_write_pulse_a: vl_notype;
delay_write_pulse_b: vl_notype
);
port(
portadatain : in vl_logic_vector;
portaaddr : in vl_logic_vector;
portawe : in vl_logic;
portare : in vl_logic;
portbdatain : in vl_logic_vector;
portbaddr : in vl_logic_vector;
portbwe : in vl_logic;
portbre : in vl_logic;
clk0 : in vl_logic;
clk1 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
ena3 : in vl_logic;
clr0 : in vl_logic;
clr1 : in vl_logic;
nerror : in vl_logic;
portabyteenamasks: in vl_logic_vector;
portbbyteenamasks: in vl_logic_vector;
portaaddrstall : in vl_logic;
portbaddrstall : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
eccstatus : out vl_logic_vector;
portadataout : out vl_logic_vector;
portbdataout : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1;
attribute mti_svvh_generic_type of init_file_layout : constant is 1;
attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1;
attribute mti_svvh_generic_type of enable_ecc : constant is 1;
attribute mti_svvh_generic_type of width_eccstatus : constant is 1;
attribute mti_svvh_generic_type of port_a_first_address : constant is 1;
attribute mti_svvh_generic_type of port_a_last_address : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_data_width : constant is 1;
attribute mti_svvh_generic_type of port_a_address_width : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_b_first_address : constant is 1;
attribute mti_svvh_generic_type of port_b_last_address : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_read_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_width : constant is 1;
attribute mti_svvh_generic_type of port_b_address_width : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
attribute mti_svvh_generic_type of mem_init1 : constant is 1;
attribute mti_svvh_generic_type of mem_init2 : constant is 1;
attribute mti_svvh_generic_type of mem_init3 : constant is 1;
attribute mti_svvh_generic_type of mem_init4 : constant is 1;
attribute mti_svvh_generic_type of mem_init5 : constant is 1;
attribute mti_svvh_generic_type of mem_init6 : constant is 1;
attribute mti_svvh_generic_type of mem_init7 : constant is 1;
attribute mti_svvh_generic_type of mem_init8 : constant is 1;
attribute mti_svvh_generic_type of mem_init9 : constant is 1;
attribute mti_svvh_generic_type of clk0_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of bist_ena : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_read_enable_clock : constant is 1;
attribute mti_svvh_generic_type of primary_port_is_a : constant is 3;
attribute mti_svvh_generic_type of primary_port_is_b : constant is 3;
attribute mti_svvh_generic_type of mode_is_dp : constant is 3;
attribute mti_svvh_generic_type of mode_is_sp : constant is 3;
attribute mti_svvh_generic_type of mode_is_rom : constant is 3;
attribute mti_svvh_generic_type of mode_is_bdp : constant is 3;
attribute mti_svvh_generic_type of mode_is_rom_or_sp : constant is 3;
attribute mti_svvh_generic_type of mixed_port_rdw_is_dont_care : constant is 3;
attribute mti_svvh_generic_type of out_a_is_reg : constant is 3;
attribute mti_svvh_generic_type of out_b_is_reg : constant is 3;
attribute mti_svvh_generic_type of data_width : constant is 3;
attribute mti_svvh_generic_type of data_unit_width : constant is 3;
attribute mti_svvh_generic_type of address_width : constant is 3;
attribute mti_svvh_generic_type of address_unit_width : constant is 3;
attribute mti_svvh_generic_type of wired_mode : constant is 3;
attribute mti_svvh_generic_type of num_rows : constant is 3;
attribute mti_svvh_generic_type of num_cols : constant is 3;
attribute mti_svvh_generic_type of mask_width_prime : constant is 3;
attribute mti_svvh_generic_type of mask_width_sec : constant is 3;
attribute mti_svvh_generic_type of byte_size_a : constant is 3;
attribute mti_svvh_generic_type of byte_size_b : constant is 3;
attribute mti_svvh_generic_type of dual_clock : constant is 3;
attribute mti_svvh_generic_type of hw_write_mode_a : constant is 3;
attribute mti_svvh_generic_type of hw_write_mode_b : constant is 3;
attribute mti_svvh_generic_type of delay_write_pulse_a : constant is 3;
attribute mti_svvh_generic_type of delay_write_pulse_b : constant is 3;
end common_28nm_ram_block;
| mit | 2ad2519e0b2a814ad555e5f607591969 | 0.627618 | 3.438663 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_delay_GNVJUPFOX3.vhd | 4 | 1,062 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNVJUPFOX3 is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "000000000000000000000000";
width : positive := 24);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNVJUPFOX3 is
Begin
-- Delay Element
Delay1i : alt_dspbuilder_SDelay generic map (
LPM_WIDTH => 24,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; | mit | 52c5a0736a48b00a4a37f049f59c84e6 | 0.635593 | 3.008499 | false | false | false | false |
Raane/Term-Assigment-TFE4140-mod-anal-dig-sys | Project/liaison/src/ECC.vhd | 1 | 924 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ECC is
port(
voted_data_out : in STD_LOGIC_VECTOR(7 downto 0);
status_out : in STD_LOGIC_VECTOR(2 downto 0);
ECC_signal : out STD_LOGIC_VECTOR(3 downto 0) := "0000"
);
end ECC;
architecture ECC of ECC is
-- Add aliases for easiers treatment of data
alias a is voted_data_out(0);
alias b is voted_data_out(1);
alias c is voted_data_out(2);
alias d is voted_data_out(3);
alias e is voted_data_out(4);
alias f is voted_data_out(5);
alias g is voted_data_out(6);
alias h is voted_data_out(7);
alias i is status_out(0);
alias j is status_out(1);
alias k is status_out(2);
begin
ECC_signal(0) <= a xor b xor d xor e xor g xor i xor k; --parity1
ECC_signal(1) <= a xor c xor d xor f xor g xor j xor k; --parity2
ECC_signal(2) <= b xor c xor d xor h xor i xor j xor k; --parity3
ECC_signal(3) <= e xor f xor g xor h xor i xor j xor k; --parity4
end ECC; | apache-2.0 | 13ca55e01a4324dd87f7ceea10dbb3b4 | 0.669913 | 2.733728 | false | false | false | false |
bobxiv/DispositivosLogicosProgramables-FICH | Practica/Contador binario vhdl/clock_synthesis.vhd | 1 | 1,935 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: H.42
-- \ \ Application: netgen
-- / / Filename: clock_synthesis.vhd
-- /___/ /\ Timestamp: Tue Sep 13 14:22:03 2011
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -ar Structure -w -ofmt vhdl -sim clock.ngc clock_synthesis.vhd
-- Device : xc3s200-5-ft256
-- Input file : clock.ngc
-- Output file : clock_synthesis.vhd
-- # of Entities : 1
-- Design Name : clock
-- Xilinx : C:/Xilinx
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Development System Reference Guide, Chapter 23
-- Synthesis and Verification Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clock is
port (
clk : in STD_LOGIC := 'X';
salida : out STD_LOGIC
);
end clock;
architecture Structure of clock is
signal clk_IBUF : STD_LOGIC;
signal salida_OBUF : STD_LOGIC;
begin
salida_OBUF_0 : OBUF
port map (
I => salida_OBUF,
O => salida
);
salida1_INV_0 : INV
port map (
I => clk_IBUF,
O => salida_OBUF
);
clk_IBUF_1 : IBUF
port map (
I => clk,
O => clk_IBUF
);
end Structure;
| gpl-3.0 | 61faae6d152633e40d0f4b0756e71b36 | 0.505426 | 3.981481 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/altera_lnsim/altera_cyclonev_pll/_primary.vhd | 5 | 37,707 | library verilog;
use verilog.vl_types.all;
entity altera_cyclonev_pll is
generic(
number_of_counters: integer := 9;
number_of_fplls : integer := 1;
number_of_extclks: integer := 2;
number_of_dlls : integer := 1;
number_of_lvds : integer := 2;
pll_auto_clk_sw_en_0: string := "false";
pll_clk_loss_edge_0: string := "both_edges";
pll_clk_loss_sw_en_0: string := "false";
pll_clk_sw_dly_0: integer := 0;
pll_clkin_0_src_0: string := "clk_0";
pll_clkin_1_src_0: string := "clk_0";
pll_manu_clk_sw_en_0: string := "false";
pll_sw_refclk_src_0: string := "clk_0";
pll_auto_clk_sw_en_1: string := "false";
pll_clk_loss_edge_1: string := "both_edges";
pll_clk_loss_sw_en_1: string := "false";
pll_clk_sw_dly_1: integer := 0;
pll_clkin_0_src_1: string := "clk_1";
pll_clkin_1_src_1: string := "clk_1";
pll_manu_clk_sw_en_1: string := "false";
pll_sw_refclk_src_1: string := "clk_1";
pll_output_clock_frequency_0: string := "700.0 MHz";
reference_clock_frequency_0: string := "700.0 MHz";
mimic_fbclk_type_0: string := "gclk";
dsm_accumulator_reset_value_0: integer := 0;
forcelock_0 : string := "false";
nreset_invert_0 : string := "false";
pll_atb_0 : integer := 0;
pll_bwctrl_0 : integer := 1000;
pll_cmp_buf_dly_0: string := "0 ps";
pll_cp_comp_0 : string := "true";
pll_cp_current_0: integer := 20;
pll_ctrl_override_setting_0: string := "true";
pll_dsm_dither_0: string := "disable";
pll_dsm_out_sel_0: string := "disable";
pll_dsm_reset_0 : string := "false";
pll_ecn_bypass_0: string := "false";
pll_ecn_test_en_0: string := "false";
pll_enable_0 : string := "true";
pll_fbclk_mux_1_0: string := "fb";
pll_fbclk_mux_2_0: string := "m_cnt";
pll_fractional_carry_out_0: integer := 24;
pll_fractional_division_0: integer := 1;
pll_fractional_value_ready_0: string := "true";
pll_lf_testen_0 : string := "false";
pll_lock_fltr_cfg_0: integer := 25;
pll_lock_fltr_test_0: string := "false";
pll_m_cnt_bypass_en_0: string := "false";
pll_m_cnt_coarse_dly_0: string := "0 ps";
pll_m_cnt_fine_dly_0: string := "0 ps";
pll_m_cnt_hi_div_0: integer := 3;
pll_m_cnt_in_src_0: string := "ph_mux_clk";
pll_m_cnt_lo_div_0: integer := 3;
pll_m_cnt_odd_div_duty_en_0: string := "false";
pll_m_cnt_ph_mux_prst_0: integer := 0;
pll_m_cnt_prst_0: integer := 256;
pll_n_cnt_bypass_en_0: string := "true";
pll_n_cnt_coarse_dly_0: string := "0 ps";
pll_n_cnt_fine_dly_0: string := "0 ps";
pll_n_cnt_hi_div_0: integer := 1;
pll_n_cnt_lo_div_0: integer := 1;
pll_n_cnt_odd_div_duty_en_0: string := "false";
pll_ref_buf_dly_0: string := "0 ps";
pll_reg_boost_0 : integer := 0;
pll_regulator_bypass_0: string := "false";
pll_ripplecap_ctrl_0: integer := 0;
pll_slf_rst_0 : string := "false";
pll_tclk_mux_en_0: string := "false";
pll_tclk_sel_0 : string := "n_src";
pll_test_enable_0: string := "false";
pll_testdn_enable_0: string := "false";
pll_testup_enable_0: string := "false";
pll_unlock_fltr_cfg_0: integer := 1;
pll_vco_div_0 : integer := 0;
pll_vco_ph0_en_0: string := "true";
pll_vco_ph1_en_0: string := "true";
pll_vco_ph2_en_0: string := "true";
pll_vco_ph3_en_0: string := "true";
pll_vco_ph4_en_0: string := "true";
pll_vco_ph5_en_0: string := "true";
pll_vco_ph6_en_0: string := "true";
pll_vco_ph7_en_0: string := "true";
pll_vctrl_test_voltage_0: integer := 750;
vccd0g_atb_0 : string := "disable";
vccd0g_output_0 : integer := 0;
vccd1g_atb_0 : string := "disable";
vccd1g_output_0 : integer := 0;
vccm1g_tap_0 : integer := 2;
vccr_pd_0 : string := "false";
vcodiv_override_0: string := "false";
sim_use_fast_model_0: string := "false";
output_clock_frequency_0: string := "100.0 MHz";
enable_output_counter_0: string := "true";
phase_shift_0 : string := "0 ps";
duty_cycle_0 : integer := 50;
c_cnt_coarse_dly_0: string := "0 ps";
c_cnt_fine_dly_0: string := "0 ps";
c_cnt_in_src_0 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_0: integer := 0;
c_cnt_prst_0 : integer := 1;
cnt_fpll_src_0 : string := "fpll_0";
dprio0_cnt_bypass_en_0: string := "true";
dprio0_cnt_hi_div_0: integer := 3;
dprio0_cnt_lo_div_0: integer := 3;
dprio0_cnt_odd_div_even_duty_en_0: string := "false";
dprio1_cnt_bypass_en_0: vl_notype;
dprio1_cnt_hi_div_0: vl_notype;
dprio1_cnt_lo_div_0: vl_notype;
dprio1_cnt_odd_div_even_duty_en_0: vl_notype;
output_clock_frequency_1: string := "0 ps";
enable_output_counter_1: string := "true";
phase_shift_1 : string := "0 ps";
duty_cycle_1 : integer := 50;
c_cnt_coarse_dly_1: string := "0 ps";
c_cnt_fine_dly_1: string := "0 ps";
c_cnt_in_src_1 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_1: integer := 0;
c_cnt_prst_1 : integer := 1;
cnt_fpll_src_1 : string := "fpll_0";
dprio0_cnt_bypass_en_1: string := "true";
dprio0_cnt_hi_div_1: integer := 2;
dprio0_cnt_lo_div_1: integer := 1;
dprio0_cnt_odd_div_even_duty_en_1: string := "true";
dprio1_cnt_bypass_en_1: vl_notype;
dprio1_cnt_hi_div_1: vl_notype;
dprio1_cnt_lo_div_1: vl_notype;
dprio1_cnt_odd_div_even_duty_en_1: vl_notype;
output_clock_frequency_2: string := "0 ps";
enable_output_counter_2: string := "true";
phase_shift_2 : string := "0 ps";
duty_cycle_2 : integer := 50;
c_cnt_coarse_dly_2: string := "0 ps";
c_cnt_fine_dly_2: string := "0 ps";
c_cnt_in_src_2 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_2: integer := 0;
c_cnt_prst_2 : integer := 1;
cnt_fpll_src_2 : string := "fpll_0";
dprio0_cnt_bypass_en_2: string := "true";
dprio0_cnt_hi_div_2: integer := 1;
dprio0_cnt_lo_div_2: integer := 1;
dprio0_cnt_odd_div_even_duty_en_2: string := "false";
dprio1_cnt_bypass_en_2: vl_notype;
dprio1_cnt_hi_div_2: vl_notype;
dprio1_cnt_lo_div_2: vl_notype;
dprio1_cnt_odd_div_even_duty_en_2: vl_notype;
output_clock_frequency_3: string := "0 ps";
enable_output_counter_3: string := "true";
phase_shift_3 : string := "0 ps";
duty_cycle_3 : integer := 50;
c_cnt_coarse_dly_3: string := "0 ps";
c_cnt_fine_dly_3: string := "0 ps";
c_cnt_in_src_3 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_3: integer := 0;
c_cnt_prst_3 : integer := 1;
cnt_fpll_src_3 : string := "fpll_0";
dprio0_cnt_bypass_en_3: string := "false";
dprio0_cnt_hi_div_3: integer := 1;
dprio0_cnt_lo_div_3: integer := 1;
dprio0_cnt_odd_div_even_duty_en_3: string := "false";
dprio1_cnt_bypass_en_3: vl_notype;
dprio1_cnt_hi_div_3: vl_notype;
dprio1_cnt_lo_div_3: vl_notype;
dprio1_cnt_odd_div_even_duty_en_3: vl_notype;
output_clock_frequency_4: string := "0 ps";
enable_output_counter_4: string := "true";
phase_shift_4 : string := "0 ps";
duty_cycle_4 : integer := 50;
c_cnt_coarse_dly_4: string := "0 ps";
c_cnt_fine_dly_4: string := "0 ps";
c_cnt_in_src_4 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_4: integer := 0;
c_cnt_prst_4 : integer := 1;
cnt_fpll_src_4 : string := "fpll_0";
dprio0_cnt_bypass_en_4: string := "false";
dprio0_cnt_hi_div_4: integer := 1;
dprio0_cnt_lo_div_4: integer := 1;
dprio0_cnt_odd_div_even_duty_en_4: string := "false";
dprio1_cnt_bypass_en_4: vl_notype;
dprio1_cnt_hi_div_4: vl_notype;
dprio1_cnt_lo_div_4: vl_notype;
dprio1_cnt_odd_div_even_duty_en_4: vl_notype;
output_clock_frequency_5: string := "0 ps";
enable_output_counter_5: string := "true";
phase_shift_5 : string := "0 ps";
duty_cycle_5 : integer := 50;
c_cnt_coarse_dly_5: string := "0 ps";
c_cnt_fine_dly_5: string := "0 ps";
c_cnt_in_src_5 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_5: integer := 0;
c_cnt_prst_5 : integer := 1;
cnt_fpll_src_5 : string := "fpll_0";
dprio0_cnt_bypass_en_5: string := "false";
dprio0_cnt_hi_div_5: integer := 1;
dprio0_cnt_lo_div_5: integer := 1;
dprio0_cnt_odd_div_even_duty_en_5: string := "false";
dprio1_cnt_bypass_en_5: vl_notype;
dprio1_cnt_hi_div_5: vl_notype;
dprio1_cnt_lo_div_5: vl_notype;
dprio1_cnt_odd_div_even_duty_en_5: vl_notype;
output_clock_frequency_6: string := "0 ps";
enable_output_counter_6: string := "true";
phase_shift_6 : string := "0 ps";
duty_cycle_6 : integer := 50;
c_cnt_coarse_dly_6: string := "0 ps";
c_cnt_fine_dly_6: string := "0 ps";
c_cnt_in_src_6 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_6: integer := 0;
c_cnt_prst_6 : integer := 1;
cnt_fpll_src_6 : string := "fpll_0";
dprio0_cnt_bypass_en_6: string := "false";
dprio0_cnt_hi_div_6: integer := 1;
dprio0_cnt_lo_div_6: integer := 1;
dprio0_cnt_odd_div_even_duty_en_6: string := "false";
dprio1_cnt_bypass_en_6: vl_notype;
dprio1_cnt_hi_div_6: vl_notype;
dprio1_cnt_lo_div_6: vl_notype;
dprio1_cnt_odd_div_even_duty_en_6: vl_notype;
output_clock_frequency_7: string := "0 ps";
enable_output_counter_7: string := "true";
phase_shift_7 : string := "0 ps";
duty_cycle_7 : integer := 50;
c_cnt_coarse_dly_7: string := "0 ps";
c_cnt_fine_dly_7: string := "0 ps";
c_cnt_in_src_7 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_7: integer := 0;
c_cnt_prst_7 : integer := 1;
cnt_fpll_src_7 : string := "fpll_0";
dprio0_cnt_bypass_en_7: string := "false";
dprio0_cnt_hi_div_7: integer := 1;
dprio0_cnt_lo_div_7: integer := 1;
dprio0_cnt_odd_div_even_duty_en_7: string := "false";
dprio1_cnt_bypass_en_7: vl_notype;
dprio1_cnt_hi_div_7: vl_notype;
dprio1_cnt_lo_div_7: vl_notype;
dprio1_cnt_odd_div_even_duty_en_7: vl_notype;
output_clock_frequency_8: string := "0 ps";
enable_output_counter_8: string := "true";
phase_shift_8 : string := "0 ps";
duty_cycle_8 : integer := 50;
c_cnt_coarse_dly_8: string := "0 ps";
c_cnt_fine_dly_8: string := "0 ps";
c_cnt_in_src_8 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_8: integer := 0;
c_cnt_prst_8 : integer := 1;
cnt_fpll_src_8 : string := "fpll_0";
dprio0_cnt_bypass_en_8: string := "false";
dprio0_cnt_hi_div_8: integer := 1;
dprio0_cnt_lo_div_8: integer := 1;
dprio0_cnt_odd_div_even_duty_en_8: string := "false";
dprio1_cnt_bypass_en_8: vl_notype;
dprio1_cnt_hi_div_8: vl_notype;
dprio1_cnt_lo_div_8: vl_notype;
dprio1_cnt_odd_div_even_duty_en_8: vl_notype;
dpa_output_clock_frequency_0: string := "0 ps";
pll_vcoph_div_0 : integer := 1;
enable_extclk_output_0: string := "false";
pll_extclk_cnt_src_0: string := "m0_cnt";
pll_extclk_enable_0: string := "true";
pll_extclk_invert_0: string := "false";
enable_extclk_output_1: string := "false";
pll_extclk_cnt_src_1: string := "vss";
pll_extclk_enable_1: string := "true";
pll_extclk_invert_1: string := "false";
enable_dll_output_0: string := "false";
pll_dll_src_value_0: string := "vss";
enable_lvds_output_0: string := "false";
pll_loaden_coarse_dly_0: string := "0 ps";
pll_loaden_enable_disable_0: string := "true";
pll_loaden_fine_dly_0: string := "0 ps";
pll_lvdsclk_coarse_dly_0: string := "0 ps";
pll_lvdsclk_enable_disable_0: string := "true";
pll_lvdsclk_fine_dly_0: string := "0 ps";
enable_lvds_output_1: string := "false";
pll_loaden_coarse_dly_1: string := "0 ps";
pll_loaden_enable_disable_1: string := "true";
pll_loaden_fine_dly_1: string := "0 ps";
pll_lvdsclk_coarse_dly_1: string := "0 ps";
pll_lvdsclk_enable_disable_1: string := "true";
pll_lvdsclk_fine_dly_1: string := "0 ps"
);
port(
phout_0 : out vl_logic_vector(7 downto 0);
adjpllin : in vl_logic_vector;
cclk : in vl_logic_vector;
coreclkin : in vl_logic_vector;
extswitch : in vl_logic_vector;
iqtxrxclkin : in vl_logic_vector;
plliqclkin : in vl_logic_vector;
rxiqclkin : in vl_logic_vector;
clkin : in vl_logic_vector(3 downto 0);
refiqclk_0 : in vl_logic_vector(1 downto 0);
refiqclk_1 : in vl_logic_vector(1 downto 0);
clk0bad : out vl_logic_vector;
clk1bad : out vl_logic_vector;
pllclksel : out vl_logic_vector;
atpgmode : in vl_logic_vector;
clk : in vl_logic_vector;
fpllcsrtest : in vl_logic_vector;
iocsrclkin : in vl_logic_vector;
iocsrdatain : in vl_logic_vector;
iocsren : in vl_logic_vector;
iocsrrstn : in vl_logic_vector;
mdiodis : in vl_logic_vector;
phaseen : in vl_logic_vector;
read : in vl_logic_vector;
rstn : in vl_logic_vector;
scanen : in vl_logic_vector;
sershiftload : in vl_logic_vector;
shiftdonei : in vl_logic_vector;
updn : in vl_logic_vector;
write : in vl_logic_vector;
addr_0 : in vl_logic_vector(5 downto 0);
byteen_0 : in vl_logic_vector(1 downto 0);
cntsel_0 : in vl_logic_vector(4 downto 0);
din_0 : in vl_logic_vector(15 downto 0);
blockselect : out vl_logic_vector;
iocsrdataout : out vl_logic_vector;
iocsrenbuf : out vl_logic_vector;
iocsrrstnbuf : out vl_logic_vector;
phasedone : out vl_logic_vector;
dout_0 : out vl_logic_vector(15 downto 0);
dprioout_0 : out vl_logic_vector(815 downto 0);
fbclkfpll : in vl_logic_vector;
lvdfbin : in vl_logic_vector;
nresync : in vl_logic_vector;
pfden : in vl_logic_vector;
shiften_fpll : in vl_logic_vector;
zdb : in vl_logic_vector;
fblvdsout : out vl_logic_vector;
lock : out vl_logic_vector;
mcntout : out vl_logic_vector;
plniotribuf : out vl_logic_vector;
clken : in vl_logic_vector;
extclk : out vl_logic_vector;
dll_clkin : in vl_logic_vector;
clkout : out vl_logic_vector;
loaden : out vl_logic_vector;
lvdsclk : out vl_logic_vector;
divclk : out vl_logic_vector;
cascade_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_counters : constant is 1;
attribute mti_svvh_generic_type of number_of_fplls : constant is 1;
attribute mti_svvh_generic_type of number_of_extclks : constant is 1;
attribute mti_svvh_generic_type of number_of_dlls : constant is 1;
attribute mti_svvh_generic_type of number_of_lvds : constant is 1;
attribute mti_svvh_generic_type of pll_auto_clk_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_edge_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_sw_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_0_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_1_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_manu_clk_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_sw_refclk_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_auto_clk_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_edge_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_sw_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_0_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_1_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_manu_clk_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_sw_refclk_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of mimic_fbclk_type_0 : constant is 1;
attribute mti_svvh_generic_type of dsm_accumulator_reset_value_0 : constant is 1;
attribute mti_svvh_generic_type of forcelock_0 : constant is 1;
attribute mti_svvh_generic_type of nreset_invert_0 : constant is 1;
attribute mti_svvh_generic_type of pll_atb_0 : constant is 1;
attribute mti_svvh_generic_type of pll_bwctrl_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cmp_buf_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_comp_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_current_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ctrl_override_setting_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_dither_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_out_sel_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_reset_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_bypass_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_test_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_1_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_2_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_carry_out_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_division_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_value_ready_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lf_testen_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_cfg_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_test_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_in_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_odd_div_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_ph_mux_prst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_prst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_odd_div_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ref_buf_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_reg_boost_0 : constant is 1;
attribute mti_svvh_generic_type of pll_regulator_bypass_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ripplecap_ctrl_0 : constant is 1;
attribute mti_svvh_generic_type of pll_slf_rst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_mux_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_sel_0 : constant is 1;
attribute mti_svvh_generic_type of pll_test_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_testdn_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_testup_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_unlock_fltr_cfg_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph0_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph1_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph2_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph3_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph4_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph5_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph6_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph7_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vctrl_test_voltage_0 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_atb_0 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_output_0 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_atb_0 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_output_0 : constant is 1;
attribute mti_svvh_generic_type of vccm1g_tap_0 : constant is 1;
attribute mti_svvh_generic_type of vccr_pd_0 : constant is 1;
attribute mti_svvh_generic_type of vcodiv_override_0 : constant is 1;
attribute mti_svvh_generic_type of sim_use_fast_model_0 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_0 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_0 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_0 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_0 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_1 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_1 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_1 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_1 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_2 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_2 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_2 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_2 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_2 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_2 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_3 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_3 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_3 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_3 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_3 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_3 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_4 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_4 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_4 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_4 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_4 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_4 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_5 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_5 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_5 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_5 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_5 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_5 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_6 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_6 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_6 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_6 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_6 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_6 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_7 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_7 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_7 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_7 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_7 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_7 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_8 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_8 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_8 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_8 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_8 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_8 : constant is 3;
attribute mti_svvh_generic_type of dpa_output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vcoph_div_0 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_0 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_1 : constant is 1;
attribute mti_svvh_generic_type of enable_dll_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dll_src_value_0 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_1 : constant is 1;
end altera_cyclonev_pll;
| mit | 9cdf4b3e7d5ec560f703c11743b974ae | 0.635903 | 3.067855 | false | false | false | false |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_zed_hdmi_out_0_0/sim/tutorial_zed_hdmi_out_0_0.vhd | 1 | 5,550 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: avnet:zedboard:zed_hdmi_out:2.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.zed_hdmi_out;
ENTITY tutorial_zed_hdmi_out_0_0 IS
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
audio_spdif : IN STD_LOGIC;
video_vsync : IN STD_LOGIC;
video_hsync : IN STD_LOGIC;
video_de : IN STD_LOGIC;
video_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
io_hdmio_spdif : OUT STD_LOGIC;
io_hdmio_video : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
io_hdmio_vsync : OUT STD_LOGIC;
io_hdmio_hsync : OUT STD_LOGIC;
io_hdmio_de : OUT STD_LOGIC;
io_hdmio_clk : OUT STD_LOGIC
);
END tutorial_zed_hdmi_out_0_0;
ARCHITECTURE tutorial_zed_hdmi_out_0_0_arch OF tutorial_zed_hdmi_out_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_zed_hdmi_out_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zed_hdmi_out IS
GENERIC (
C_DATA_WIDTH : INTEGER; -- Video Data Width
C_FAMILY : STRING
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
audio_spdif : IN STD_LOGIC;
video_vsync : IN STD_LOGIC;
video_hsync : IN STD_LOGIC;
video_de : IN STD_LOGIC;
video_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
io_hdmio_spdif : OUT STD_LOGIC;
io_hdmio_video : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
io_hdmio_vsync : OUT STD_LOGIC;
io_hdmio_hsync : OUT STD_LOGIC;
io_hdmio_de : OUT STD_LOGIC;
io_hdmio_clk : OUT STD_LOGIC
);
END COMPONENT zed_hdmi_out;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF video_vsync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 VID_IO_IN VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF video_hsync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 VID_IO_IN HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF video_de: SIGNAL IS "xilinx.com:interface:vid_io:1.0 VID_IO_IN ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO OF video_data: SIGNAL IS "xilinx.com:interface:vid_io:1.0 VID_IO_IN DATA";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_spdif: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO SPDIF";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_video: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO DATA";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_vsync: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_hsync: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_de: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO DE";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_clk: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO CLK";
BEGIN
U0 : zed_hdmi_out
GENERIC MAP (
C_DATA_WIDTH => 16,
C_FAMILY => "zynq"
)
PORT MAP (
clk => clk,
reset => reset,
audio_spdif => audio_spdif,
video_vsync => video_vsync,
video_hsync => video_hsync,
video_de => video_de,
video_data => video_data,
io_hdmio_spdif => io_hdmio_spdif,
io_hdmio_video => io_hdmio_video,
io_hdmio_vsync => io_hdmio_vsync,
io_hdmio_hsync => io_hdmio_hsync,
io_hdmio_de => io_hdmio_de,
io_hdmio_clk => io_hdmio_clk
);
END tutorial_zed_hdmi_out_0_0_arch;
| gpl-2.0 | 3a318eca3cbd39b94b5b242b875baf54 | 0.706486 | 3.589909 | false | false | false | false |
nulldozer/purisc | Global_memory/MAGIC_global/MAGIC_global.vhd | 2 | 24,029 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MAGIC_global is
PORT (
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
DATA_OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
C0_STALL : OUT STD_LOGIC;
C1_STALL : OUT STD_LOGIC;
CORE_IDENT : OUT STD_LOGIC;
IO_ENABLE : IN STD_LOGIC
);
end;
architecture magic of MAGIC_global is
component SETUP_global
PORT(
CLK : IN STD_LOGIC;
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
STALL : OUT STD_LOGIC;
HAZARD : IN STD_LOGIC;
ram_0_port_a : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_0_port_b : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_0_wren_a : OUT STD_LOGIC;
ram_0_wren_b : OUT STD_LOGIC;
ram_1_port_a : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_1_port_b : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_1_wren_a : OUT STD_LOGIC;
ram_1_wren_b : OUT STD_LOGIC;
ram_2_port_a : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_2_port_b : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_2_wren_a : OUT STD_LOGIC;
ram_2_wren_b : OUT STD_LOGIC;
ram_3_port_a : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_3_port_b : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_3_wren_a : OUT STD_LOGIC;
ram_3_wren_b : OUT STD_LOGIC;
ram_4_port_a : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_4_port_b : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_4_wren_a : OUT STD_LOGIC;
ram_4_wren_b : OUT STD_LOGIC;
ram_5_port_a : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_5_port_b : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_5_wren_a : OUT STD_LOGIC;
ram_5_wren_b : OUT STD_LOGIC;
ram_6_port_a : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_6_port_b : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_6_wren_a : OUT STD_LOGIC;
ram_6_wren_b : OUT STD_LOGIC;
ram_7_port_a : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_7_port_b : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_7_wren_a : OUT STD_LOGIC;
ram_7_wren_b : OUT STD_LOGIC;
ram_0_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_1_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_2_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_3_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_4_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_5_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_6_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_7_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end component;
component ROUTE_global
PORT(
hazard : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
ram_0_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_1_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_2_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_3_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_4_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_5_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_6_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_7_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
OUTPUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OUTPUT_B : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OUTPUT_C : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OUTPUT_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OUTPUT_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end component;
component RAM_0_global
PORT
(
aclr : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (11 downto 0);
address_b : IN STD_LOGIC_VECTOR (11 downto 0);
clock : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component RAM_1_global
PORT
(
aclr : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (11 downto 0);
address_b : IN STD_LOGIC_VECTOR (11 downto 0);
clock : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component RAM_2_global
PORT
(
aclr : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (11 downto 0);
address_b : IN STD_LOGIC_VECTOR (11 downto 0);
clock : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component RAM_3_global
PORT
(
aclr : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (11 downto 0);
address_b : IN STD_LOGIC_VECTOR (11 downto 0);
clock : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component RAM_4_global
PORT
(
aclr : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (11 downto 0);
address_b : IN STD_LOGIC_VECTOR (11 downto 0);
clock : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component RAM_5_global
PORT
(
aclr : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (11 downto 0);
address_b : IN STD_LOGIC_VECTOR (11 downto 0);
clock : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component RAM_6_global
PORT
(
aclr : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (11 downto 0);
address_b : IN STD_LOGIC_VECTOR (11 downto 0);
clock : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component RAM_7_global
PORT
(
aclr : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (11 downto 0);
address_b : IN STD_LOGIC_VECTOR (11 downto 0);
clock : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal address_a_sig : std_logic_vector (31 downto 0);
signal address_b_sig : std_logic_vector (31 downto 0);
signal address_c_sig : std_logic_vector (31 downto 0);
signal address_0_sig : std_logic_vector (31 downto 0);
signal address_1_sig : std_logic_vector (31 downto 0);
signal address_w_sig : std_logic_vector (31 downto 0);
signal data_to_w_sig : std_logic_vector (31 downto 0);
signal w_en_sig : std_logic;
signal RESET : std_logic;
signal stall_flag : std_logic;
signal hazard : std_logic;
signal hazard_w_io : std_logic;
signal io_buffer_en : std_logic;
signal ram_0_port_a : std_logic_vector (11 downto 0);
signal ram_0_port_b : std_logic_vector (11 downto 0);
signal ram_0_wren_a : std_logic;
signal ram_0_wren_b : std_logic;
signal ram_1_port_a : std_logic_vector (11 downto 0);
signal ram_1_port_b : std_logic_vector (11 downto 0);
signal ram_1_wren_a : std_logic;
signal ram_1_wren_b : std_logic;
signal ram_2_port_a : std_logic_vector (11 downto 0);
signal ram_2_port_b : std_logic_vector (11 downto 0);
signal ram_2_wren_a : std_logic;
signal ram_2_wren_b : std_logic;
signal ram_3_port_a : std_logic_vector (11 downto 0);
signal ram_3_port_b : std_logic_vector (11 downto 0);
signal ram_3_wren_a : std_logic;
signal ram_3_wren_b : std_logic;
signal ram_4_port_a : std_logic_vector (11 downto 0);
signal ram_4_port_b : std_logic_vector (11 downto 0);
signal ram_4_wren_a : std_logic;
signal ram_4_wren_b : std_logic;
signal ram_5_port_a : std_logic_vector (11 downto 0);
signal ram_5_port_b : std_logic_vector (11 downto 0);
signal ram_5_wren_a : std_logic;
signal ram_5_wren_b : std_logic;
signal ram_6_port_a : std_logic_vector (11 downto 0);
signal ram_6_port_b : std_logic_vector (11 downto 0);
signal ram_6_wren_a : std_logic;
signal ram_6_wren_b : std_logic;
signal ram_7_port_a : std_logic_vector (11 downto 0);
signal ram_7_port_b : std_logic_vector (11 downto 0);
signal ram_7_wren_a : std_logic;
signal ram_7_wren_b : std_logic;
signal ram_0_sel_vector : std_logic_vector(9 downto 0);
signal ram_1_sel_vector : std_logic_vector(9 downto 0);
signal ram_2_sel_vector : std_logic_vector(9 downto 0);
signal ram_3_sel_vector : std_logic_vector(9 downto 0);
signal ram_4_sel_vector : std_logic_vector(9 downto 0);
signal ram_5_sel_vector : std_logic_vector(9 downto 0);
signal ram_6_sel_vector : std_logic_vector(9 downto 0);
signal ram_7_sel_vector : std_logic_vector(9 downto 0);
signal ram_0_sel : std_logic_vector(9 downto 0);
signal ram_1_sel : std_logic_vector(9 downto 0);
signal ram_2_sel : std_logic_vector(9 downto 0);
signal ram_3_sel : std_logic_vector(9 downto 0);
signal ram_4_sel : std_logic_vector(9 downto 0);
signal ram_5_sel : std_logic_vector(9 downto 0);
signal ram_6_sel : std_logic_vector(9 downto 0);
signal ram_7_sel : std_logic_vector(9 downto 0);
signal ram_0_out_a : std_logic_vector (31 downto 0);
signal ram_0_out_b : std_logic_vector (31 downto 0);
signal ram_1_out_a : std_logic_vector (31 downto 0);
signal ram_1_out_b : std_logic_vector (31 downto 0);
signal ram_2_out_a : std_logic_vector (31 downto 0);
signal ram_2_out_b : std_logic_vector (31 downto 0);
signal ram_3_out_a : std_logic_vector (31 downto 0);
signal ram_3_out_b : std_logic_vector (31 downto 0);
signal ram_4_out_a : std_logic_vector (31 downto 0);
signal ram_4_out_b : std_logic_vector (31 downto 0);
signal ram_5_out_a : std_logic_vector (31 downto 0);
signal ram_5_out_b : std_logic_vector (31 downto 0);
signal ram_6_out_a : std_logic_vector (31 downto 0);
signal ram_6_out_b : std_logic_vector (31 downto 0);
signal ram_7_out_a : std_logic_vector (31 downto 0);
signal ram_7_out_b : std_logic_vector (31 downto 0);
signal output_a : std_logic_vector (31 downto 0);
signal output_b : std_logic_vector (31 downto 0);
signal output_c : std_logic_vector (31 downto 0);
signal output_0 : std_logic_vector (31 downto 0);
signal output_1 : std_logic_vector (31 downto 0);
signal stall : std_logic;
signal hold : std_logic;
signal core_id : std_logic;
signal c0_stall_sig : std_logic;
signal c1_stall_sig : std_logic;
signal hazard_advanced : std_logic;
--
begin
input_control : SETUP_global PORT MAP (
CLK => CLK,
ADDRESS_A => address_a_sig,
ADDRESS_B => address_b_sig,
ADDRESS_C => address_c_sig,
ADDRESS_0 => address_0_sig,
ADDRESS_1 => address_1_sig,
ADDRESS_W => address_w_sig,
W_EN => w_en_sig,
RESET_n => RESET_n,
STALL => stall_flag,
HAZARD => hazard,
ram_0_port_a => ram_0_port_a,
ram_0_port_b => ram_0_port_b,
ram_0_wren_a => ram_0_wren_a,
ram_0_wren_b => ram_0_wren_b,
ram_1_port_a => ram_1_port_a,
ram_1_port_b => ram_1_port_b,
ram_1_wren_a => ram_1_wren_a,
ram_1_wren_b => ram_1_wren_b,
ram_2_port_a => ram_2_port_a,
ram_2_port_b => ram_2_port_b,
ram_2_wren_a => ram_2_wren_a,
ram_2_wren_b => ram_2_wren_b,
ram_3_port_a => ram_3_port_a,
ram_3_port_b => ram_3_port_b,
ram_3_wren_a => ram_3_wren_a,
ram_3_wren_b => ram_3_wren_b,
ram_4_port_a => ram_4_port_a,
ram_4_port_b => ram_4_port_b,
ram_4_wren_a => ram_4_wren_a,
ram_4_wren_b => ram_4_wren_b,
ram_5_port_a => ram_5_port_a,
ram_5_port_b => ram_5_port_b,
ram_5_wren_a => ram_5_wren_a,
ram_5_wren_b => ram_5_wren_b,
ram_6_port_a => ram_6_port_a,
ram_6_port_b => ram_6_port_b,
ram_6_wren_a => ram_6_wren_a,
ram_6_wren_b => ram_6_wren_b,
ram_7_port_a => ram_7_port_a,
ram_7_port_b => ram_7_port_b,
ram_7_wren_a => ram_7_wren_a,
ram_7_wren_b => ram_7_wren_b,
ram_0_sel_vector => ram_0_sel_vector,
ram_1_sel_vector => ram_1_sel_vector,
ram_2_sel_vector => ram_2_sel_vector,
ram_3_sel_vector => ram_3_sel_vector,
ram_4_sel_vector => ram_4_sel_vector,
ram_5_sel_vector => ram_5_sel_vector,
ram_6_sel_vector => ram_6_sel_vector,
ram_7_sel_vector => ram_7_sel_vector
);
RAM_0_inst : RAM_0_global PORT MAP (
aclr => RESET,
address_a => ram_0_port_a,
address_b => ram_0_port_b,
clock => CLK,
data_a => data_to_w_sig,
data_b => data_to_w_sig,
wren_a => ram_0_wren_a,
wren_b => ram_0_wren_b,
q_a => ram_0_out_a,
q_b => ram_0_out_b
);
RAM_1_inst : RAM_1_global PORT MAP (
aclr => RESET,
address_a => ram_1_port_a,
address_b => ram_1_port_b,
clock => CLK,
data_a => data_to_w_sig,
data_b => data_to_w_sig,
wren_a => ram_1_wren_a,
wren_b => ram_1_wren_b,
q_a => ram_1_out_a,
q_b => ram_1_out_b
);
RAM_2_inst : RAM_2_global PORT MAP (
aclr => RESET,
address_a => ram_2_port_a,
address_b => ram_2_port_b,
clock => CLK,
data_a => data_to_w_sig,
data_b => data_to_w_sig,
wren_a => ram_2_wren_a,
wren_b => ram_2_wren_b,
q_a => ram_2_out_a,
q_b => ram_2_out_b
);
RAM_3_inst : RAM_3_global PORT MAP (
aclr => RESET,
address_a => ram_3_port_a,
address_b => ram_3_port_b,
clock => CLK,
data_a => data_to_w_sig,
data_b => data_to_w_sig,
wren_a => ram_3_wren_a,
wren_b => ram_3_wren_b,
q_a => ram_3_out_a,
q_b => ram_3_out_b
);
RAM_4_inst : RAM_4_global PORT MAP (
aclr => RESET,
address_a => ram_4_port_a,
address_b => ram_4_port_b,
clock => CLK,
data_a => data_to_w_sig,
data_b => data_to_w_sig,
wren_a => ram_4_wren_a,
wren_b => ram_4_wren_b,
q_a => ram_4_out_a,
q_b => ram_4_out_b
);
RAM_5_inst : RAM_5_global PORT MAP (
aclr => RESET,
address_a => ram_5_port_a,
address_b => ram_5_port_b,
clock => CLK,
data_a => data_to_w_sig,
data_b => data_to_w_sig,
wren_a => ram_5_wren_a,
wren_b => ram_5_wren_b,
q_a => ram_5_out_a,
q_b => ram_5_out_b
);
RAM_6_inst : RAM_6_global PORT MAP (
aclr => RESET,
address_a => ram_6_port_a,
address_b => ram_6_port_b,
clock => CLK,
data_a => data_to_w_sig,
data_b => data_to_w_sig,
wren_a => ram_6_wren_a,
wren_b => ram_6_wren_b,
q_a => ram_6_out_a,
q_b => ram_6_out_b
);
RAM_7_inst : RAM_7_global PORT MAP (
aclr => RESET,
address_a => ram_7_port_a,
address_b => ram_7_port_b,
clock => CLK,
data_a => data_to_w_sig,
data_b => data_to_w_sig,
wren_a => ram_7_wren_a,
wren_b => ram_7_wren_b,
q_a => ram_7_out_a,
q_b => ram_7_out_b
);
output_control : ROUTE_global PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
hazard => hazard_w_io,
hazard_advanced => hazard_advanced,
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
ram_0_sel_vector => ram_0_sel,
ram_1_sel_vector => ram_1_sel,
ram_2_sel_vector => ram_2_sel,
ram_3_sel_vector => ram_3_sel,
ram_4_sel_vector => ram_4_sel,
ram_5_sel_vector => ram_5_sel,
ram_6_sel_vector => ram_6_sel,
ram_7_sel_vector => ram_7_sel,
OUTPUT_A => output_a,
OUTPUT_B => output_b,
OUTPUT_C => output_c,
OUTPUT_0 => output_0,
OUTPUT_1 => output_1
);
-- latch_outputs : process (CLK, RESET_n) begin
-- if (RESET_n = '0') then
-- DATA_OUT_A <= "00000000000000000000000000000000";
-- DATA_OUT_B <= "00000000000000000000000000000000";
-- DATA_OUT_C <= "00000000000000000000000000000000";
-- DATA_OUT_0 <= "00000000000000000000000000000000";
-- DATA_OUT_1 <= "00000000000000000000000000000000";
-- elsif (rising_edge(CLK)) then
-- DATA_OUT_A <= output_a;
-- DATA_OUT_B <= output_b;
-- DATA_OUT_C <= output_c;
-- DATA_OUT_0 <= output_0;
-- DATA_OUT_1 <= output_1;
-- end if;
-- end process;
--********above latching used for testing************
DATA_OUT_A <= output_a;
DATA_OUT_B <= output_b;
DATA_OUT_C <= output_c;
DATA_OUT_0 <= output_0;
DATA_OUT_1 <= output_1;
latch_vectors : process (CLK, RESET_n) begin
if (RESET_n = '0') then
ram_0_sel <= "0000000000";
ram_1_sel <= "0000000000";
ram_2_sel <= "0000000000";
ram_3_sel <= "0000000000";
ram_4_sel <= "0000000000";
ram_5_sel <= "0000000000";
ram_6_sel <= "0000000000";
ram_7_sel <= "0000000000";
hazard <= '0';
elsif (rising_edge(CLK)) then
ram_0_sel <= ram_0_sel_vector;
ram_1_sel <= ram_1_sel_vector;
ram_2_sel <= ram_2_sel_vector;
ram_3_sel <= ram_3_sel_vector;
ram_4_sel <= ram_4_sel_vector;
ram_5_sel <= ram_5_sel_vector;
ram_6_sel <= ram_6_sel_vector;
ram_7_sel <= ram_7_sel_vector;
hazard <= stall_flag;
end if;
end process;
-- latch_inputs : process (CLK, RESET_n) begin
-- if (RESET_n = '0') then
-- address_a_sig <= "00000000000000000000000000000000";
-- address_b_sig <= "00000000000000000000000000000000";
-- address_c_sig <= "00000000000000000000000000000000";
-- address_0_sig <= "00000000000000000000000000000000";
-- address_1_sig <= "00000000000000000000000000000000";
-- address_w_sig <= "00000000000000000000000000000000";
-- data_to_w_sig <= "00000000000000000000000000000000";
-- w_en_sig <= '0';
-- elsif (rising_edge(CLK)) then
-- address_a_sig <= ADDRESS_A;
-- address_b_sig <= ADDRESS_B;
-- address_c_sig <= ADDRESS_C;
-- address_0_sig <= ADDRESS_0;
-- address_1_sig <= ADDRESS_1;
-- address_w_sig <= ADDRESS_W;
-- data_to_w_sig <= DATA_TO_W;
-- w_en_sig <= W_EN;
-- end if;
-- end process;
--********above latching used for testing***************
address_a_sig <= ADDRESS_A;
address_b_sig <= ADDRESS_B;
address_c_sig <= ADDRESS_C;
address_0_sig <= ADDRESS_0;
address_1_sig <= ADDRESS_1;
address_w_sig <= ADDRESS_W;
data_to_w_sig <= DATA_TO_W;
w_en_sig <= W_EN;
RESET <= not RESET_n;
stall <= stall_flag or hazard_w_io; --maybe without io
hold <= c0_stall_sig and c1_stall_sig;
C0_STALL <= (not core_id) or c0_stall_sig; --flipped not statement
C1_STALL <= (core_id) or c1_stall_sig; --between these two lines
CORE_IDENT <= core_id;
hazard_w_io <= hazard or io_buffer_en;
hazard_advanced <= hazard_w_io or stall_flag;
id_gen : process (CLK, RESET_n, hold) begin
if (RESET_n = '0') then
core_id <= '0';
elsif (rising_edge(CLK)) then
if (hold = '0' and IO_ENABLE = '0') then
core_id <= not core_id;
end if;
end if;
end process;
override_io : process (CLK, RESET_n) begin
if (RESET_n = '0') then
io_buffer_en <= '0';
elsif (rising_edge(CLK)) then
io_buffer_en <= IO_ENABLE;
end if;
end process;
stalling : process (core_id, stall_flag, stall) begin
if (core_id = '0' and stall = '1') then
c0_stall_sig <= stall;
c1_stall_sig <= stall_flag;
elsif (core_id = '1' and stall = '1') then
c0_stall_sig <= stall_flag;
c1_stall_sig <= stall;
else
c0_stall_sig <= '0';
c1_stall_sig <= '0';
end if;
end process;
end;
| gpl-2.0 | 6aa0219db3bab466fab3567089d5ebb5 | 0.555912 | 2.666334 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT.vhd | 2 | 45,577 | -- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.11.10:36:06
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT is
port (
eop : out std_logic; -- eop.wire
data_en : in std_logic := '0'; -- data_en.wire
ctrl_pak3 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak3.wire
ctrl_pak1 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak1.wire
ctrl_en : in std_logic := '0'; -- ctrl_en.wire
sop : out std_logic; -- sop.wire
data : out std_logic_vector(24 downto 0); -- data.wire
ctrl_pak2 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak2.wire
pixel_num : in std_logic_vector(47 downto 0) := (others => '0'); -- pixel_num.wire
colorbar : in std_logic_vector(23 downto 0) := (others => '0'); -- colorbar.wire
counter : in std_logic_vector(23 downto 0) := (others => '0'); -- counter.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0' -- .reset
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GN33BXJAZX is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN33BXJAZX;
component alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNTWZRTG4I;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_case_statement_GNWMX2GCN2 is
generic (
number_outputs : integer := 8;
hasDefault : natural := 0;
pipeline : natural := 0;
width : integer := 8
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
r0 : out std_logic; -- wire
r1 : out std_logic -- wire
);
end component alt_dspbuilder_case_statement_GNWMX2GCN2;
component alt_dspbuilder_case_statement_GNFTM45DFU is
generic (
number_outputs : integer := 8;
hasDefault : natural := 0;
pipeline : natural := 0;
width : integer := 8
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
r0 : out std_logic; -- wire
r1 : out std_logic -- wire
);
end component alt_dspbuilder_case_statement_GNFTM45DFU;
component alt_dspbuilder_multiplexer_GNLGLCKYZ5 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(23 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in2 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in3 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNLGLCKYZ5;
component alt_dspbuilder_port_GNEHYJMBQS is
port (
input : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEHYJMBQS;
component alt_dspbuilder_constant_GNNKZSYI73 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNKZSYI73;
component alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GN6E6AAQPZ;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_constant_GNZEH3JAKA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNZEH3JAKA;
component alt_dspbuilder_delay_GNIYBMGPQQ is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNIYBMGPQQ;
component alt_dspbuilder_constant_GNLJWFEWBD is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNLJWFEWBD;
component alt_dspbuilder_constant_GNQJ63TWA6 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNQJ63TWA6;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_if_statement_GNTVBNRAAT is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNTVBNRAAT;
component alt_dspbuilder_delay_GNNBTO2F3L is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNNBTO2F3L;
component alt_dspbuilder_port_GNUJT4YY5I is
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(47 downto 0) -- wire
);
end component alt_dspbuilder_port_GNUJT4YY5I;
component alt_dspbuilder_multiplexer_GNHQFFAUXQ is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(24 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in2 : in std_logic_vector(24 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNHQFFAUXQ;
component alt_dspbuilder_multiplexer_GN6ODCX3D4 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(24 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(24 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GN6ODCX3D4;
component alt_dspbuilder_delay_GNVJUPFOX3 is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNVJUPFOX3;
component alt_dspbuilder_cast_GN3ODVPHOL is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN3ODVPHOL;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
component alt_dspbuilder_cast_GNCPEUNC4M is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCPEUNC4M;
component alt_dspbuilder_cast_GNKDE2NVCC is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKDE2NVCC;
component alt_dspbuilder_cast_GNCCZ56SYK is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCCZ56SYK;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
signal pipelined_adder2user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder2user_aclrGND:output -> Pipelined_Adder2:user_aclr
signal pipelined_adder2enavcc_output_wire : std_logic; -- Pipelined_Adder2enaVCC:output -> Pipelined_Adder2:ena
signal multiplexeruser_aclrgnd_output_wire : std_logic; -- Multiplexeruser_aclrGND:output -> Multiplexer:user_aclr
signal multiplexerenavcc_output_wire : std_logic; -- MultiplexerenaVCC:output -> Multiplexer:ena
signal delaysclrgnd_output_wire : std_logic; -- DelaysclrGND:output -> Delay:sclr
signal delayenavcc_output_wire : std_logic; -- DelayenaVCC:output -> Delay:ena
signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr
signal delay5enavcc_output_wire : std_logic; -- Delay5enaVCC:output -> Delay5:ena
signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr
signal delay3enavcc_output_wire : std_logic; -- Delay3enaVCC:output -> Delay3:ena
signal multiplexer1user_aclrgnd_output_wire : std_logic; -- Multiplexer1user_aclrGND:output -> Multiplexer1:user_aclr
signal multiplexer1enavcc_output_wire : std_logic; -- Multiplexer1enaVCC:output -> Multiplexer1:ena
signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr
signal delay1enavcc_output_wire : std_logic; -- Delay1enaVCC:output -> Delay1:ena
signal multiplexer2user_aclrgnd_output_wire : std_logic; -- Multiplexer2user_aclrGND:output -> Multiplexer2:user_aclr
signal multiplexer2enavcc_output_wire : std_logic; -- Multiplexer2enaVCC:output -> Multiplexer2:ena
signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr
signal delay2enavcc_output_wire : std_logic; -- Delay2enaVCC:output -> Delay2:ena
signal counter_0_output_wire : std_logic_vector(23 downto 0); -- counter_0:output -> [Bus_Conversion1:input, If_Statement7:a, cast29:input, cast32:input]
signal constant1_output_wire : std_logic_vector(23 downto 0); -- Constant1:output -> Delay:input
signal ctrl_pak1_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak1_0:output -> Delay1:input
signal ctrl_pak2_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak2_0:output -> Delay2:input
signal ctrl_pak3_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak3_0:output -> Delay3:input
signal constant7_output_wire : std_logic_vector(23 downto 0); -- Constant7:output -> Delay5:input
signal if_statement7_true_wire : std_logic; -- If_Statement7:true -> [Logical_Bit_Operator10:data0, Logical_Bit_Operator9:data1]
signal data_en_0_output_wire : std_logic; -- data_en_0:output -> [Logical_Bit_Operator10:data1, Logical_Bit_Operator3:data1, cast34:input]
signal case_statement2_r1_wire : std_logic; -- Case_Statement2:r1 -> Logical_Bit_Operator3:data0
signal ctrl_en_0_output_wire : std_logic; -- ctrl_en_0:output -> [Logical_Bit_Operator4:data0, Logical_Bit_Operator9:data0, cast33:input]
signal case_statement2_r0_wire : std_logic; -- Case_Statement2:r0 -> Logical_Bit_Operator4:data1
signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Logical_Bit_Operator5:data0
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Logical_Bit_Operator5:data1
signal logical_bit_operator10_result_wire : std_logic; -- Logical_Bit_Operator10:result -> Logical_Bit_Operator6:data1
signal logical_bit_operator9_result_wire : std_logic; -- Logical_Bit_Operator9:result -> Logical_Bit_Operator6:data0
signal bus_conversion1_output_wire : std_logic_vector(1 downto 0); -- Bus_Conversion1:output -> Multiplexer:sel
signal delay_output_wire : std_logic_vector(23 downto 0); -- Delay:output -> Multiplexer:in0
signal delay1_output_wire : std_logic_vector(23 downto 0); -- Delay1:output -> Multiplexer:in1
signal delay2_output_wire : std_logic_vector(23 downto 0); -- Delay2:output -> Multiplexer:in2
signal delay3_output_wire : std_logic_vector(23 downto 0); -- Delay3:output -> Multiplexer:in3
signal bus_concatenation_output_wire : std_logic_vector(1 downto 0); -- Bus_Concatenation:output -> Multiplexer1:sel
signal bus_concatenation1_output_wire : std_logic_vector(1 downto 0); -- Bus_Concatenation1:output -> Multiplexer2:sel
signal multiplexer2_result_wire : std_logic_vector(24 downto 0); -- Multiplexer2:result -> Multiplexer1:in1
signal constant18_output_wire : std_logic_vector(23 downto 0); -- Constant18:output -> Pipelined_Adder2:datab
signal pipelined_adder2_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder2:result -> If_Statement7:c
signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> sop_0:input
signal logical_bit_operator6_result_wire : std_logic; -- Logical_Bit_Operator6:result -> eop_0:input
signal multiplexer1_result_wire : std_logic_vector(24 downto 0); -- Multiplexer1:result -> data_0:input
signal cast29_output_wire : std_logic_vector(15 downto 0); -- cast29:output -> Case_Statement1:input
signal case_statement1_r0_wire : std_logic; -- Case_Statement1:r0 -> cast30:input
signal cast30_output_wire : std_logic_vector(0 downto 0); -- cast30:output -> Bus_Concatenation1:a
signal case_statement1_r1_wire : std_logic; -- Case_Statement1:r1 -> cast31:input
signal cast31_output_wire : std_logic_vector(0 downto 0); -- cast31:output -> Bus_Concatenation1:b
signal cast32_output_wire : std_logic_vector(15 downto 0); -- cast32:output -> Case_Statement2:input
signal cast33_output_wire : std_logic_vector(0 downto 0); -- cast33:output -> Bus_Concatenation:a
signal cast34_output_wire : std_logic_vector(0 downto 0); -- cast34:output -> Bus_Concatenation:b
signal constant16_output_wire : std_logic_vector(15 downto 0); -- Constant16:output -> cast35:input
signal cast35_output_wire : std_logic_vector(23 downto 0); -- cast35:output -> If_Statement7:b
signal constant5_output_wire : std_logic_vector(23 downto 0); -- Constant5:output -> cast36:input
signal cast36_output_wire : std_logic_vector(24 downto 0); -- cast36:output -> Multiplexer1:in0
signal multiplexer_result_wire : std_logic_vector(23 downto 0); -- Multiplexer:result -> cast37:input
signal cast37_output_wire : std_logic_vector(24 downto 0); -- cast37:output -> Multiplexer1:in2
signal colorbar_0_output_wire : std_logic_vector(23 downto 0); -- colorbar_0:output -> cast38:input
signal cast38_output_wire : std_logic_vector(24 downto 0); -- cast38:output -> Multiplexer2:in0
signal delay5_output_wire : std_logic_vector(23 downto 0); -- Delay5:output -> cast39:input
signal cast39_output_wire : std_logic_vector(24 downto 0); -- cast39:output -> Multiplexer2:in1
signal pixel_num_0_output_wire : std_logic_vector(47 downto 0); -- pixel_num_0:output -> cast40:input
signal cast40_output_wire : std_logic_vector(23 downto 0); -- cast40:output -> Pipelined_Adder2:dataa
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Bus_Concatenation1:aclr, Bus_Concatenation:aclr, Case_Statement1:aclr, Case_Statement2:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Delay5:aclr, Delay:aclr, Multiplexer1:aclr, Multiplexer2:aclr, Multiplexer:aclr, Pipelined_Adder2:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Bus_Concatenation1:clock, Bus_Concatenation:clock, Case_Statement1:clock, Case_Statement2:clock, Delay1:clock, Delay2:clock, Delay3:clock, Delay5:clock, Delay:clock, Multiplexer1:clock, Multiplexer2:clock, Multiplexer:clock, Pipelined_Adder2:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion1 : component alt_dspbuilder_cast_GN33BXJAZX
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
pipelined_adder2 : component alt_dspbuilder_pipelined_adder_GNTWZRTG4I
generic map (
width => 24,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast40_output_wire, -- dataa.wire
datab => constant18_output_wire, -- datab.wire
result => pipelined_adder2_result_wire, -- result.wire
user_aclr => pipelined_adder2user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder2enavcc_output_wire -- ena.wire
);
pipelined_adder2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder2user_aclrgnd_output_wire -- output.wire
);
pipelined_adder2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder2enavcc_output_wire -- output.wire
);
case_statement1 : component alt_dspbuilder_case_statement_GNWMX2GCN2
generic map (
number_outputs => 2,
hasDefault => 1,
pipeline => 0,
width => 16
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
input => cast29_output_wire, -- input.wire
r0 => case_statement1_r0_wire, -- r0.wire
r1 => case_statement1_r1_wire -- r1.wire
);
case_statement2 : component alt_dspbuilder_case_statement_GNFTM45DFU
generic map (
number_outputs => 2,
hasDefault => 0,
pipeline => 0,
width => 16
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
input => cast32_output_wire, -- input.wire
r0 => case_statement2_r0_wire, -- r0.wire
r1 => case_statement2_r1_wire -- r1.wire
);
multiplexer : component alt_dspbuilder_multiplexer_GNLGLCKYZ5
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_conversion1_output_wire, -- sel.wire
result => multiplexer_result_wire, -- result.wire
ena => multiplexerenavcc_output_wire, -- ena.wire
user_aclr => multiplexeruser_aclrgnd_output_wire, -- user_aclr.wire
in0 => delay_output_wire, -- in0.wire
in1 => delay1_output_wire, -- in1.wire
in2 => delay2_output_wire, -- in2.wire
in3 => delay3_output_wire -- in3.wire
);
multiplexeruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexeruser_aclrgnd_output_wire -- output.wire
);
multiplexerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexerenavcc_output_wire -- output.wire
);
data_0 : component alt_dspbuilder_port_GNEHYJMBQS
port map (
input => multiplexer1_result_wire, -- input.wire
output => data -- output.wire
);
constant7 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant7_output_wire -- output.wire
);
constant5 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant5_output_wire -- output.wire
);
bus_concatenation1 : component alt_dspbuilder_bus_concat_GN6E6AAQPZ
generic map (
widthB => 1,
widthA => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast30_output_wire, -- a.wire
b => cast31_output_wire, -- b.wire
output => bus_concatenation1_output_wire -- output.wire
);
logical_bit_operator6 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator6_result_wire, -- result.wire
data0 => logical_bit_operator9_result_wire, -- data0.wire
data1 => logical_bit_operator10_result_wire -- data1.wire
);
logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator5_result_wire, -- result.wire
data0 => logical_bit_operator4_result_wire, -- data0.wire
data1 => logical_bit_operator3_result_wire -- data1.wire
);
ctrl_pak2_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak2, -- input.wire
output => ctrl_pak2_0_output_wire -- output.wire
);
logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator4_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => case_statement2_r0_wire -- data1.wire
);
ctrl_pak3_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak3, -- input.wire
output => ctrl_pak3_0_output_wire -- output.wire
);
bus_concatenation : component alt_dspbuilder_bus_concat_GN6E6AAQPZ
generic map (
widthB => 1,
widthA => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast33_output_wire, -- a.wire
b => cast34_output_wire, -- b.wire
output => bus_concatenation_output_wire -- output.wire
);
ctrl_pak1_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak1, -- input.wire
output => ctrl_pak1_0_output_wire -- output.wire
);
logical_bit_operator9 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator9_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => if_statement7_true_wire -- data1.wire
);
constant1 : component alt_dspbuilder_constant_GNZEH3JAKA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000001111",
width => 24
)
port map (
output => constant1_output_wire -- output.wire
);
delay : component alt_dspbuilder_delay_GNIYBMGPQQ
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000001111",
width => 24
)
port map (
input => constant1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay_output_wire, -- output.wire
sclr => delaysclrgnd_output_wire, -- sclr.wire
ena => delayenavcc_output_wire -- ena.wire
);
delaysclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delaysclrgnd_output_wire -- output.wire
);
delayenavcc : component alt_dspbuilder_vcc_GN
port map (
output => delayenavcc_output_wire -- output.wire
);
constant16 : component alt_dspbuilder_constant_GNLJWFEWBD
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000000000011",
width => 16
)
port map (
output => constant16_output_wire -- output.wire
);
constant18 : component alt_dspbuilder_constant_GNQJ63TWA6
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000100",
width => 24
)
port map (
output => constant18_output_wire -- output.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => case_statement2_r1_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => logical_bit_operator6_result_wire, -- input.wire
output => eop -- output.wire
);
colorbar_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => colorbar, -- input.wire
output => colorbar_0_output_wire -- output.wire
);
if_statement7 : component alt_dspbuilder_if_statement_GNTVBNRAAT
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b) or (a=c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement7_true_wire, -- true.wire
a => counter_0_output_wire, -- a.wire
b => cast35_output_wire, -- b.wire
c => pipelined_adder2_result_wire -- c.wire
);
counter_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter, -- input.wire
output => counter_0_output_wire -- output.wire
);
delay5 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => constant7_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay5_output_wire, -- output.wire
sclr => delay5sclrgnd_output_wire, -- sclr.wire
ena => delay5enavcc_output_wire -- ena.wire
);
delay5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay5sclrgnd_output_wire -- output.wire
);
delay5enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay5enavcc_output_wire -- output.wire
);
pixel_num_0 : component alt_dspbuilder_port_GNUJT4YY5I
port map (
input => pixel_num, -- input.wire
output => pixel_num_0_output_wire -- output.wire
);
delay3 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => ctrl_pak3_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay3_output_wire, -- output.wire
sclr => delay3sclrgnd_output_wire, -- sclr.wire
ena => delay3enavcc_output_wire -- ena.wire
);
delay3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay3sclrgnd_output_wire -- output.wire
);
delay3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay3enavcc_output_wire -- output.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => logical_bit_operator5_result_wire, -- input.wire
output => sop -- output.wire
);
logical_bit_operator10 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator10_result_wire, -- result.wire
data0 => if_statement7_true_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ctrl_en, -- input.wire
output => ctrl_en_0_output_wire -- output.wire
);
multiplexer1 : component alt_dspbuilder_multiplexer_GNHQFFAUXQ
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 25,
pipeline => 0,
number_inputs => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_concatenation_output_wire, -- sel.wire
result => multiplexer1_result_wire, -- result.wire
ena => multiplexer1enavcc_output_wire, -- ena.wire
user_aclr => multiplexer1user_aclrgnd_output_wire, -- user_aclr.wire
in0 => cast36_output_wire, -- in0.wire
in1 => multiplexer2_result_wire, -- in1.wire
in2 => cast37_output_wire -- in2.wire
);
multiplexer1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer1user_aclrgnd_output_wire -- output.wire
);
multiplexer1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer1enavcc_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => ctrl_pak1_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => delay1sclrgnd_output_wire, -- sclr.wire
ena => delay1enavcc_output_wire -- ena.wire
);
delay1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay1sclrgnd_output_wire -- output.wire
);
delay1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay1enavcc_output_wire -- output.wire
);
multiplexer2 : component alt_dspbuilder_multiplexer_GN6ODCX3D4
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 1,
width => 25,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_concatenation1_output_wire, -- sel.wire
result => multiplexer2_result_wire, -- result.wire
ena => multiplexer2enavcc_output_wire, -- ena.wire
user_aclr => multiplexer2user_aclrgnd_output_wire, -- user_aclr.wire
in0 => cast38_output_wire, -- in0.wire
in1 => cast39_output_wire -- in1.wire
);
multiplexer2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer2user_aclrgnd_output_wire -- output.wire
);
multiplexer2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer2enavcc_output_wire -- output.wire
);
delay2 : component alt_dspbuilder_delay_GNVJUPFOX3
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000000",
width => 24
)
port map (
input => ctrl_pak2_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay2_output_wire, -- output.wire
sclr => delay2sclrgnd_output_wire, -- sclr.wire
ena => delay2enavcc_output_wire -- ena.wire
);
delay2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay2sclrgnd_output_wire -- output.wire
);
delay2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay2enavcc_output_wire -- output.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => data_en, -- input.wire
output => data_en_0_output_wire -- output.wire
);
cast29 : component alt_dspbuilder_cast_GN3ODVPHOL
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => cast29_output_wire -- output.wire
);
cast30 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => case_statement1_r0_wire, -- input.wire
output => cast30_output_wire -- output.wire
);
cast31 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => case_statement1_r1_wire, -- input.wire
output => cast31_output_wire -- output.wire
);
cast32 : component alt_dspbuilder_cast_GN3ODVPHOL
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => cast32_output_wire -- output.wire
);
cast33 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => ctrl_en_0_output_wire, -- input.wire
output => cast33_output_wire -- output.wire
);
cast34 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => data_en_0_output_wire, -- input.wire
output => cast34_output_wire -- output.wire
);
cast35 : component alt_dspbuilder_cast_GNCPEUNC4M
generic map (
round => 0,
saturate => 0
)
port map (
input => constant16_output_wire, -- input.wire
output => cast35_output_wire -- output.wire
);
cast36 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => constant5_output_wire, -- input.wire
output => cast36_output_wire -- output.wire
);
cast37 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplexer_result_wire, -- input.wire
output => cast37_output_wire -- output.wire
);
cast38 : component alt_dspbuilder_cast_GNCCZ56SYK
generic map (
round => 0,
saturate => 0
)
port map (
input => colorbar_0_output_wire, -- input.wire
output => cast38_output_wire -- output.wire
);
cast39 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => delay5_output_wire, -- input.wire
output => cast39_output_wire -- output.wire
);
cast40 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => pixel_num_0_output_wire, -- input.wire
output => cast40_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT
| mit | 214fc599aa4dad649732ed9821aff7db | 0.565592 | 3.377325 | false | false | false | false |
Raane/Term-Assigment-TFE4140-mod-anal-dig-sys | Project/liaison/src/onebitvoter.vhd | 1 | 6,392 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity onebitvoter is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
y : out STD_LOGIC;
status : out STD_LOGIC_VECTOR(2 downto 0)
);
end onebitvoter;
architecture Behavioral of onebitvoter is
signal state_a: STD_LOGIC := '1';
signal state_b: STD_LOGIC := '1';
signal state_c: STD_LOGIC := '1';
signal state_d: STD_LOGIC := '1';
signal status_internal: STD_LOGIC_VECTOR(2 downto 0);
signal last_status: STD_LOGIC_VECTOR(2 downto 0) := "000";
signal voted_data: STD_LOGIC;
signal sum_of_inputs: STD_LOGIC_VECTOR(2 downto 0);
signal number_of_winning_votes: STD_LOGIC_VECTOR(2 downto 0);
signal extended_a: STD_LOGIC_VECTOR(2 downto 0);
signal extended_b: STD_LOGIC_VECTOR(2 downto 0);
signal extended_c: STD_LOGIC_VECTOR(2 downto 0);
signal extended_d: STD_LOGIC_VECTOR(2 downto 0);
signal extended_vote_a: STD_LOGIC_VECTOR(2 downto 0);
signal extended_vote_b: STD_LOGIC_VECTOR(2 downto 0);
signal extended_vote_c: STD_LOGIC_VECTOR(2 downto 0);
signal extended_vote_d: STD_LOGIC_VECTOR(2 downto 0);
begin
-- Start of state machine back end
-- Update outputs when the clock tick occur
process (clk)
begin
if (rising_edge(clk)) then
if(reset='1') then
state_a <= '1'; --default state on reset.
state_b <= '1'; --default state on reset.
state_c <= '1'; --default state on reset.
state_d <= '1'; --default state on reset.
last_status <= "000";
else
status <= status_internal;
last_status <= status_internal;
y <= voted_data;
state_a <= state_a and (voted_data xnor a);
state_b <= state_b and (voted_data xnor b);
state_c <= state_c and (voted_data xnor c);
state_d <= state_d and (voted_data xnor d);
end if;
end if;
end process;
-- End of state machine back end
-- Start of state machine front end
-- Filter out votes from failed micro controllers and extend the vote result to a 3 bit number
process (a, b, c, d, state_a, state_b, state_c, state_d)
begin
extended_a <= "00"&(a and state_a);
extended_b <= "00"&(b and state_b);
extended_c <= "00"&(c and state_c);
extended_d <= "00"&(d and state_d);
end process;
-- Calculate the sum of the inputs from all the non broken controllers
process (extended_a, extended_b, extended_c, extended_d)
begin
sum_of_inputs <= std_logic_vector(
unsigned(extended_a) +
unsigned(extended_b) +
unsigned(extended_c) +
unsigned(extended_d));
end process;
-- Set the voted data based on the status and the sum of the input data
-- This is the core of the state machine driving the system
process (sum_of_inputs, last_status)
begin
case last_status is
when "000" =>
case sum_of_inputs is
when "100" =>
voted_data <= '1';
when "011" =>
voted_data <= '1';
when "010" =>
voted_data <= '1'; -- in 2v2 votes the data doesn't matter, we are going to status 111 anyway
when "001" =>
voted_data <= '0';
when "000" =>
voted_data <= '0';
when others =>
voted_data <= 'X'; -- This is never reached
end case;
when "001" =>
case sum_of_inputs is
when "011" =>
voted_data <= '1';
when "010" =>
voted_data <= '1';
when "001" =>
voted_data <= '0';
when "000" =>
voted_data <= '0';
when others =>
voted_data <= 'X'; -- This is never reached
end case;
when "010" =>
case sum_of_inputs is
when "010" =>
voted_data <= '1';
when "001" =>
voted_data <= '1'; -- in 2v2 votes the data doesn't matter, we are going to status 111 anyway
when "000" =>
voted_data <= '0';
when others =>
voted_data <= 'X'; -- This is never reached
end case;
when "111" =>
voted_data <= '1';
when others =>
voted_data <= 'Z'; -- This is never reached, Z is used instead of X because it is more efficient here
end case;
end process;
-- Filter out the votes that did not match the winning vote and extend them to a 3 bit number
process(voted_data, a, b, c, d, state_a, state_b, state_c, state_d)
begin
extended_vote_a <= "00"&(state_a and (voted_data xnor a));
extended_vote_b <= "00"&(state_b and (voted_data xnor b));
extended_vote_c <= "00"&(state_c and (voted_data xnor c));
extended_vote_d <= "00"&(state_d and (voted_data xnor d));
end process;
-- Calculate the number of votes that matched the vote outcome which came from an input with state '1'
process(extended_vote_a, extended_vote_b, extended_vote_c, extended_vote_d)
begin
number_of_winning_votes <= std_logic_vector(
unsigned( extended_vote_a ) +
unsigned( extended_vote_b ) +
unsigned( extended_vote_c ) +
unsigned( extended_vote_d )
);
end process;
-- Calculate the internal status field based on the inputs matched with the voted data
process (number_of_winning_votes, last_status)
begin
if(number_of_winning_votes = "010" and last_status = "000") then
status_internal <= "111";
else
case number_of_winning_votes is
when "100"=>
status_internal <= "000";
when "011"=>
status_internal <= "001";
when "010"=>
status_internal <= "010";
when "001"=>
status_internal <= "111";
when "000"=>
status_internal <= "111";
when others =>
-- This should never be reached
status_internal <= "XXX";
end case;
end if;
end process;
-- End of state machine front end
end Behavioral; | apache-2.0 | d50e7f2f545576d6558c978cd131ef3e | 0.583385 | 3.611299 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/altera_lnsim/generic_device_pll/_primary.vhd | 5 | 3,272 | library verilog;
use verilog.vl_types.all;
entity generic_device_pll is
generic(
reference_clock_frequency: string := "0 ps";
output_clock_frequency: string := "0 ps";
forcelock : string := "false";
nreset_invert : string := "false";
pll_enable : string := "false";
pll_fbclk_mux_1 : string := "glb";
pll_fbclk_mux_2 : string := "fb_1";
pll_m_cnt_bypass_en: string := "false";
pll_m_cnt_hi_div: integer := 1;
pll_m_cnt_in_src: string := "ph_mux_clk";
pll_m_cnt_lo_div: integer := 1;
pll_n_cnt_bypass_en: string := "false";
pll_n_cnt_hi_div: integer := 1;
pll_n_cnt_lo_div: integer := 1;
pll_vco_ph0_en : string := "false";
pll_vco_ph1_en : string := "false";
pll_vco_ph2_en : string := "false";
pll_vco_ph3_en : string := "false";
pll_vco_ph4_en : string := "false";
pll_vco_ph5_en : string := "false";
pll_vco_ph6_en : string := "false";
pll_vco_ph7_en : string := "false"
);
port(
coreclkfb : in vl_logic;
fbclkfpll : in vl_logic;
lvdsfbin : in vl_logic;
nresync : in vl_logic;
pfden : in vl_logic;
refclkin : in vl_logic;
zdb : in vl_logic;
fbclk : out vl_logic;
fblvdsout : out vl_logic;
lock : out vl_logic;
vcoph : out vl_logic_vector(7 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of reference_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of forcelock : constant is 1;
attribute mti_svvh_generic_type of nreset_invert : constant is 1;
attribute mti_svvh_generic_type of pll_enable : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_2 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_bypass_en : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_hi_div : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_in_src : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_lo_div : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_bypass_en : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_hi_div : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_lo_div : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph0_en : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph1_en : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph2_en : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph3_en : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph4_en : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph5_en : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph6_en : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph7_en : constant is 1;
end generic_device_pll;
| mit | 02aaa72c338fc4027e72e2598bff2c47 | 0.600856 | 3.239604 | false | false | false | false |
frznchckn/polarbear | hw/cores/uart/hdl/vhdl/uart_bhv.vhd | 1 | 8,562 | --------------------------------------------------------------------------------
--|
--| Filename : uart_bhv
--| Author : Russell L Friesenhahn
--| Origin Date : 20130828
--|
--------------------------------------------------------------------------------
--|
--| Abstract
--|
--| Behavorial architecture of UART core
--|
--------------------------------------------------------------------------------
--|
--| Modification History
--|
--|
--|
--------------------------------------------------------------------------------
--|
--| References
--|
--|
--|
--------------------------------------------------------------------------------
architecture bhv of uart is
-----------------------------
-- Component Declarations
-----------------------------
component cntr is
generic (
CntrWidth : integer := 8
);
port (
Clk : in std_ulogic;
Rst : in std_ulogic;
En : in std_ulogic;
Clr : in std_ulogic;
CritValue : in std_ulogic_vector(CntrWidth-1 downto 0);
CntrValue : out std_ulogic_vector(CntrWidth-1 downto 0);
CntReached : out std_ulogic
);
end component;
-----------------------------
-- Constant Declarations
-----------------------------
-- constant clk16Gen : integer := SysClkRate / BaudRate / 16;
-----------------------------
-- Type Declarations
-----------------------------
type rxst is (
IDLE,
START,
RX,
PARITYCK,
STOP,
ERR
);
type txst is (
IDLE,
START,
TX,
TXPARITY,
STOP
);
-----------------------------
-- Signal Declarations
-----------------------------
signal clkCntr : unsigned(19 downto 0);
signal clkTxCntr : unsigned(23 downto 0);
-- signal clkTxGen : unsigned(23 downto 0);
signal clkTxGen : std_ulogic_vector(23 downto 0);
signal ClkTxPulse : std_ulogic;
signal startTxCntr : std_ulogic;
signal clk16Pulse : std_ulogic;
signal rxcs : rxst;
signal din_d0 : std_ulogic;
signal din_d1 : std_ulogic;
signal din_d2 : std_ulogic;
signal clk16Cnt : unsigned(3 downto 0);
-- signal dout_int : std_ulogic_vector(7 downto 0);
signal rxCnt : unsigned(3 downto 0);
signal dout_i : std_ulogic_vector(7 downto 0);
signal parity : std_ulogic;
signal txcs : txst;
signal bitTxParity : std_ulogic;
signal txCnt : unsigned(2 downto 0);
signal byteRx_d1 : std_ulogic_vector(7 downto 0);
signal byteRx_d2 : std_ulogic_vector(7 downto 0);
signal byteRxValid_d1 : std_ulogic;
signal txBusy_i : std_ulogic;
begin
ByteTx <= dout_i;
TxBusy <= txBusy_i;
clkTxGen <= BaudRateGen & X"0";
cntr_tx : cntr
generic map (
CntrWidth => 24
)
port map (
Clk => Clk,
Rst => Rst,
En => '1',
Clr => startTxCntr,
CritValue => clkTxGen,
CntrValue => open,
CntReached => ClkTxPulse
);
P_TX : process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
BitTx <= '1';
txBusy_i <= '1';
clkTxCntr <= (others => '0');
byteRxValid_d1 <= '0';
startTxCntr <= '0';
else
if ByteRxValid = '1' and txBusy_i = '0' then
byteRx_d1 <= ByteRx;
byteRxValid_d1 <= ByteRxValid;
txBusy_i <= '1';
end if;
C_TX : case txcs is
when IDLE =>
txBusy_i <= '0';
BitTx <= '1';
bitTxParity <= ParityType;
txCnt <= (others => '0');
if byteRxValid_d1 = '1' then
byteRx_d2 <= byteRx_d1;
startTxCntr <= '1';
txBusy_i <= '1';
txcs <= START;
byteRxValid_d1 <= '0';
end if;
when START =>
startTxCntr <= '0';
BitTx <= '0';
if ClkTxPulse = '1' then
txcs <= TX;
BitTx <= byteRx_d1(0);
bitTxParity <= bitTxParity xor byteRx_d1(0);
txCnt <= txCnt + 1;
end if;
when TX =>
if ClkTxPulse = '1' then
if txCnt = to_unsigned(0, txCnt'length) then
BitTx <= bitTxParity;
txcs <= TXPARITY;
else
BitTx <= byteRx_d1(to_integer(txCnt));
bitTxParity <= bitTxParity xor byteRx_d1(to_integer(txCnt));
txCnt <= txCnt + 1;
end if;
end if;
when TXPARITY =>
if ClkTxPulse = '1' then
BitTx <= '1';
txcs <= STOP;
end if;
when STOP =>
txBusy_i <= '0';
if ClkTxPulse = '1' then
BitTx <= '1';
txcs <= IDLE;
end if;
when others => null;
end case C_TX;
end if;
end if;
end process P_TX;
CLK16_PULSE_GEN : process (Clk)
begin
if Clk'event and Clk = '1'
then
if Rst = '1'
then
clkCntr <= (others => '0');
clk16Pulse <= '0';
else
-- if clkCntr = to_unsigned(clk16Gen, clkCntr'length)
if clkCntr = unsigned(BaudRateGen)
then
clkCntr <= (others => '0');
clk16Pulse <= '1';
else
clkCntr <= clkCntr + 1;
clk16Pulse <= '0';
end if;
end if;
end if;
end process CLK16_PULSE_GEN;
P_STABLE_DATA : process (Clk)
begin
if Clk'event and Clk = '1'
then
if Rst = '1'
then
din_d0 <= '0';
din_d1 <= '0';
din_d2 <= '0';
else
din_d2 <= din_d1;
din_d1 <= din_d0;
din_d0 <= BitRx;
end if;
end if;
end process P_STABLE_DATA;
P_CLK16_CNTR : process (Clk)
begin
if Clk'event and Clk = '1'
then
if Rst = '1'
then
clk16Cnt <= (others => '0');
else
if clk16Pulse = '1'
then
clk16Cnt <= clk16Cnt + 1;
end if;
if din_d1 /= din_d2
then
clk16Cnt <= (others => '0');
end if;
end if;
end if;
end process P_CLK16_CNTR;
P_RX : process (Clk)
begin
if Clk'event and Clk = '1'
then
if Rst = '1'
then
rxcs <= IDLE;
dout_i <= (others => '0');
ParErr <= '0';
StopErr <= '0';
else
CO_RX_SM : case rxcs is
when IDLE =>
ByteTxValid <= '0';
rxCnt <= (others => '0');
parity <= ParityType;
if din_d1 = '0'
and din_d2 = '1'
then
rxcs <= START;
end if;
when START =>
if clk16Pulse = '1'
and clk16Cnt = to_unsigned(7, 4)
then
if din_d2 = '0'
then
rxcs <= RX;
else
rxcs <= IDLE;
end if;
end if;
when RX =>
if clk16Pulse = '1'
and clk16Cnt = to_unsigned(7, 4)
then
rxCnt <= rxCnt + 1;
end if;
if clk16Pulse = '1'
and clk16Cnt = to_unsigned(7, 4)
then
dout_i <= din_d2 & dout_i(7 downto 1);
parity <= parity xor din_d2;
end if;
if rxCnt = to_unsigned(8, 4)
then
if UseParity = '1'
then
rxcs <= PARITYCK;
else
rxcs <= STOP;
end if;
end if;
when PARITYCK =>
if clk16Pulse = '1'
and clk16Cnt = to_unsigned(7, 4)
then
if parity /= din_d2
then
ParErr <= '1';
rxcs <= ERR;
assert false
report "ERROR: parity incorrect"
severity error;
else
rxcs <= STOP;
end if;
end if;
when STOP =>
if clk16Pulse = '1'
and clk16Cnt = to_unsigned(7, 4)
then
if din_d2 = '1'
then
ByteTxValid <= '1';
rxcs <= IDLE;
else
StopErr <= '1';
rxcs <= ERR;
end if;
end if;
when ERR =>
ParErr <= '0';
StopErr <= '0';
rxcs <= IDLE;
end case;
end if;
end if;
end process P_RX;
end architecture bhv;
| unlicense | c335d92f887fb92f33a21e7441399390 | 0.413688 | 4.098612 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_sImpulsennAltr.vhd | 8 | 3,602 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulsennAltr is
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulsennAltr ;
architecture syn of alt_dspbuilder_sImpulsennAltr is
type States_ImpulseAltr is (sclear, slow, shigh,slowend);
signal current_state : States_ImpulseAltr;
signal next_state : States_ImpulseAltr;
signal count : std_logic_vector(ToNatural(nbitnecessary(Impulsedelay)-1) downto 0);
signal countwidth : std_logic_vector(ToNatural(nbitnecessary(Impulsewidth)-1) downto 0);
signal enawidth : std_logic;
begin
rp:process(clock,aclr)
begin
if aclr='1' then
count <= (others=>'0');
countwidth <= (others=>'0');
current_state <= sclear;
elsif clock'event and clock='1' then
if (sclr='1') then
count <= (others=>'0');
countwidth <= (others=>'0');
current_state <= sclear;
elsif (ena='1') then
count <= count+int2ustd(1,nbitnecessary(Impulsedelay));
current_state <= next_state;
if (enawidth='1') then
countwidth <= countwidth+int2ustd(1,nbitnecessary(Impulsewidth));
end if;
end if;
end if;
end process;
cp:process(count, countwidth, current_state, sclr, ena)
begin
case current_state is
when sclear =>
q <= '0';
enawidth <='0';
if (ena='1') and (sclr='0') then
next_state <= slow;
else
next_state <= sclear;
end if;
when slow =>
q <= '0';
enawidth <='0';
if (sclr='1') then
next_state <= sclear;
elsif (count=int2ustd(Impulsedelay-1,nbitnecessary(Impulsedelay))) and (ena='1') then
next_state <= shigh;
else
next_state <= slow ;
end if;
when shigh =>
q <= '1';
enawidth <='1';
if (sclr='1') then
next_state <= sclear;
elsif (countwidth=int2ustd(Impulsewidth-1,nbitnecessary(Impulsewidth))) and (ena='1') then
next_state <= slowend ;
else
next_state <= shigh;
end if;
when slowend =>
q <= '0';
enawidth <='0';
if (sclr='1') then
next_state <= sclear;
else
next_state <= slowend ;
end if;
end case;
end process;
end syn;
| mit | c7c2219c19db10d826f8512f4d2e72fb | 0.615769 | 3.728778 | false | false | false | false |
freecores/t48 | rtl/vhdl/clock_ctrl.vhd | 1 | 12,708 | -------------------------------------------------------------------------------
--
-- The Clock Control unit.
-- Clock States and Machine Cycles are generated here.
--
-- $Id: clock_ctrl.vhd,v 1.12 2006-07-14 01:04:35 arniml Exp $
--
-- Copyright (c) 2004, 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.all;
entity t48_clock_ctrl is
generic (
-- divide XTAL1 by 3 to derive Clock States
xtal_div_3_g : integer := 1
);
port (
clk_i : in std_logic;
xtal_i : in std_logic;
xtal_en_i : in boolean;
res_i : in std_logic;
en_clk_i : in boolean;
xtal3_o : out boolean;
t0_o : out std_logic;
multi_cycle_i : in boolean;
assert_psen_i : in boolean;
assert_prog_i : in boolean;
assert_rd_i : in boolean;
assert_wr_i : in boolean;
mstate_o : out mstate_t;
second_cycle_o : out boolean;
ale_o : out boolean;
psen_o : out boolean;
prog_o : out boolean;
rd_o : out boolean;
wr_o : out boolean
);
end t48_clock_ctrl;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t48_clock_ctrl is
-- The three XTAL1 cycles.
signal xtal_q : unsigned(1 downto 0);
signal xtal1_s,
xtal2_s,
xtal3_s : boolean;
signal x1_s,
x2_s,
x3_s : std_logic;
signal t0_q : std_logic;
-- The five clock states.
signal mstate_q : mstate_t;
signal ale_q : boolean;
signal psen_q : boolean;
signal prog_q : boolean;
signal rd_q : boolean;
signal wr_q : boolean;
-- The Machine Cycle marker.
signal second_cycle_q : boolean;
signal multi_cycle_q : boolean;
begin
-----------------------------------------------------------------------------
-- Verify the generics
-----------------------------------------------------------------------------
-- pragma translate_off
-- XTAL1 divide by 3 --------------------------------------------------------
assert (xtal_div_3_g = 1) or (xtal_div_3_g = 0)
report "xtal_div_3_g must be either 1 or 0!"
severity failure;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Divide XTAL1 by 3 to derive Clock States.
-----------------------------------------------------------------------------
use_xtal_div: if xtal_div_3_g = 1 generate
xtal: process (res_i, xtal_i)
begin
if res_i = res_active_c then
xtal_q <= TO_UNSIGNED(0, 2);
t0_q <= '0';
elsif xtal_i'event and xtal_i = clk_active_c then
if xtal_en_i then
if xtal_q < 2 then
xtal_q <= xtal_q + 1;
else
xtal_q <= TO_UNSIGNED(0, 2);
end if;
if xtal3_s then
t0_q <= '1';
else
t0_q <= '0';
end if;
end if;
end if;
end process xtal;
x1_s <= '1'
when xtal_q = 0 and xtal_en_i else
'0';
x2_s <= '1'
when xtal_q = 1 and xtal_en_i else
'0';
x3_s <= '1'
when xtal_q = 2 and xtal_en_i else
'0';
t0_o <= t0_q;
end generate;
-----------------------------------------------------------------------------
-- XTAL1 is used directly for Clock States.
-----------------------------------------------------------------------------
no_xtal_div: if xtal_div_3_g = 0 generate
xtal_q <= TO_UNSIGNED(0, 2);
x1_s <= '1'
when xtal_en_i else
'0';
x2_s <= '1'
when xtal_en_i else
'0';
x3_s <= '1'
when xtal_en_i else
'0';
t0_o <= xtal_i;
end generate;
-- And finally the boolean flags --------------------------------------------
xtal1_s <= to_boolean(x1_s);
xtal2_s <= to_boolean(x2_s);
xtal3_s <= to_boolean(x3_s);
-----------------------------------------------------------------------------
-- Process external_signal
--
-- Purpose:
-- Control signals ALE, PSEN, PROG and RD/WR are generated here.
--
external_signals: process (res_i, xtal_i)
begin
if res_i = res_active_c then
ale_q <= false;
psen_q <= false;
prog_q <= false;
rd_q <= false;
wr_q <= false;
elsif xtal_i'event and xtal_i = clk_active_c then
case mstate_q is
when MSTATE5 =>
-- RD, WR are set at the end of XTAL2 of first machine cycle
if xtal2_s and not second_cycle_q then
if assert_rd_i then
rd_q <= true;
end if;
if assert_wr_i then
wr_q <= true;
end if;
end if;
when MSTATE1 =>
if xtal3_s then
psen_q <= false;
end if;
when MSTATE2 =>
if xtal3_s then
-- RD, WR are removed at the end of XTAL3 of second machine cycle
rd_q <= false;
wr_q <= false;
-- so is PROG
prog_q <= false;
end if;
when MSTATE3 =>
-- ALE is set at the end of XTAL3 of every machine cycle
if xtal3_s then
ale_q <= true;
end if;
when MSTATE4 =>
if xtal3_s then
-- PSEN is set at the end of XTAL3
if assert_psen_i then
psen_q <= true;
end if;
end if;
-- PROG is set at the end of XTAL3
if xtal3_s and
multi_cycle_q and not second_cycle_q and assert_prog_i then
prog_q <= true;
end if;
-- ALE is removed at the end of XTAL2 of every machine cycle
if xtal2_s then
ale_q <= false;
end if;
when others =>
-- recover when states are out of sync
ale_q <= false;
psen_q <= false;
prog_q <= false;
rd_q <= false;
wr_q <= false;
end case;
end if;
end process external_signals;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process states
--
-- Purpose:
-- The Clock State controller.
--
states: process (res_i, clk_i)
begin
if res_i = res_active_c then
-- Reset machine state to MSTATE3
-- This allows a proper instruction fetch for the first real instruction
-- after reset.
-- The MSTATE3 is part of a virtual NOP that has no MSTATE1 and MSTATE2.
mstate_q <= MSTATE3;
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
case mstate_q is
when MSTATE5 =>
mstate_q <= MSTATE1;
when MSTATE1 =>
mstate_q <= MSTATE2;
when MSTATE2 =>
mstate_q <= MSTATE3;
when MSTATE3 =>
mstate_q <= MSTATE4;
when MSTATE4 =>
mstate_q <= MSTATE5;
when others =>
-- recover when states are out of sync
mstate_q <= MSTATE1;
-- pragma translate_off
assert false
report "Encoding of Clock States failed!"
severity error;
-- pragma translate_on
end case;
end if;
end if;
end process states;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process machine_cycle
--
-- Purpose:
-- Keep track of machine cycles.
-- Basically, this means to differ between first and second cycle.
--
machine_cycle: process (res_i, clk_i)
variable state2_v, state5_v : boolean;
begin
if res_i = res_active_c then
multi_cycle_q <= false;
second_cycle_q <= false;
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
state2_v := mstate_q = MSTATE2;
state5_v := mstate_q = MSTATE5;
-- multi cycle information is delivered in State 2 from the decoder
if state2_v and multi_cycle_i then
multi_cycle_q <= true;
end if;
-- mark second machine cycle
if multi_cycle_q and state5_v then
second_cycle_q <= true;
end if;
-- reset at end of second machine cycle
if state5_v and
(multi_cycle_q and second_cycle_q) then
multi_cycle_q <= false;
second_cycle_q <= false;
end if;
end if;
end if;
end process machine_cycle;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output assignments
-----------------------------------------------------------------------------
xtal3_o <= xtal3_s;
mstate_o <= mstate_q;
second_cycle_o <= second_cycle_q;
ale_o <= ale_q;
psen_o <= psen_q;
prog_o <= prog_q;
rd_o <= rd_q;
wr_o <= wr_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.11 2006/06/20 00:46:38 arniml
-- new input xtal_en_i gates xtal_i base clock
--
-- Revision 1.10 2005/11/01 21:24:21 arniml
-- * shift assertion of ALE and PROG to xtal3
-- * correct change of revision 1.8
--
-- Revision 1.9 2005/06/11 10:08:43 arniml
-- introduce prefix 't48_' for all packages, entities and configurations
--
-- Revision 1.8 2005/06/09 22:15:10 arniml
-- Use en_clk_i instead of xtal3_s for generation of external signals.
-- This is required when the core runs with full xtal clock instead
-- of xtal/3 (xtal_div_3_g = 0).
--
-- Revision 1.7 2005/05/04 20:12:36 arniml
-- Fix bug report:
-- "Wrong clock applied to T0"
-- t0_o is generated inside clock_ctrl with a separate flip-flop running
-- with xtal_i
--
-- Revision 1.6 2004/10/25 20:31:12 arniml
-- remove PROG and end of XTAL2, see comment for details
--
-- Revision 1.5 2004/10/25 19:35:41 arniml
-- deassert rd_q, wr_q and prog_q at end of XTAL3
--
-- Revision 1.4 2004/04/24 23:44:25 arniml
-- move from std_logic_arith to numeric_std
--
-- Revision 1.3 2004/04/18 18:56:23 arniml
-- reset machine state to MSTATE3 to allow proper instruction fetch
-- after reset
--
-- Revision 1.2 2004/03/28 12:55:06 arniml
-- move code for PROG out of if-branch for xtal3_s
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 902fa00ddba36320b6ecd8eefcbd0541 | 0.503698 | 4.005043 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/altera_lnsim/altera_mult_add_rtl/_primary.vhd | 5 | 43,770 | library verilog;
use verilog.vl_types.all;
entity altera_mult_add_rtl is
generic(
extra_latency : integer := 0;
dedicated_multiplier_circuitry: string := "AUTO";
dsp_block_balancing: string := "AUTO";
selected_device_family: string := "Stratix V";
lpm_type : string := "altera_mult_add";
lpm_hint : string := "UNUSED";
width_a : integer := 1;
input_register_a0: string := "UNREGISTERED";
input_aclr_a0 : string := "NONE";
input_source_a0 : string := "DATAA";
input_register_a1: string := "UNREGISTERED";
input_aclr_a1 : string := "NONE";
input_source_a1 : string := "DATAA";
input_register_a2: string := "UNREGISTERED";
input_aclr_a2 : string := "NONE";
input_source_a2 : string := "DATAA";
input_register_a3: string := "UNREGISTERED";
input_aclr_a3 : string := "NONE";
input_source_a3 : string := "DATAA";
input_a0_latency_clock: string := "UNREGISTERED";
input_a0_latency_aclr: string := "NONE";
input_a1_latency_clock: string := "UNREGISTERED";
input_a1_latency_aclr: string := "NONE";
input_a2_latency_clock: string := "UNREGISTERED";
input_a2_latency_aclr: string := "NONE";
input_a3_latency_clock: string := "UNREGISTERED";
input_a3_latency_aclr: string := "NONE";
width_b : integer := 1;
input_register_b0: string := "UNREGISTERED";
input_aclr_b0 : string := "NONE";
input_source_b0 : string := "DATAB";
input_register_b1: string := "UNREGISTERED";
input_aclr_b1 : string := "NONE";
input_source_b1 : string := "DATAB";
input_register_b2: string := "UNREGISTERED";
input_aclr_b2 : string := "NONE";
input_source_b2 : string := "DATAB";
input_register_b3: string := "UNREGISTERED";
input_aclr_b3 : string := "NONE";
input_source_b3 : string := "DATAB";
input_b0_latency_clock: string := "UNREGISTERED";
input_b0_latency_aclr: string := "NONE";
input_b1_latency_clock: string := "UNREGISTERED";
input_b1_latency_aclr: string := "NONE";
input_b2_latency_clock: string := "UNREGISTERED";
input_b2_latency_aclr: string := "NONE";
input_b3_latency_clock: string := "UNREGISTERED";
input_b3_latency_aclr: string := "NONE";
width_c : integer := 1;
input_register_c0: string := "UNREGISTERED";
input_aclr_c0 : string := "NONE";
input_register_c1: string := "UNREGISTERED";
input_aclr_c1 : string := "NONE";
input_register_c2: string := "UNREGISTERED";
input_aclr_c2 : string := "NONE";
input_register_c3: string := "UNREGISTERED";
input_aclr_c3 : string := "NONE";
input_c0_latency_clock: string := "UNREGISTERED";
input_c0_latency_aclr: string := "NONE";
input_c1_latency_clock: string := "UNREGISTERED";
input_c1_latency_aclr: string := "NONE";
input_c2_latency_clock: string := "UNREGISTERED";
input_c2_latency_aclr: string := "NONE";
input_c3_latency_clock: string := "UNREGISTERED";
input_c3_latency_aclr: string := "NONE";
width_result : integer := 34;
output_register : string := "UNREGISTERED";
output_aclr : string := "NONE";
port_signa : string := "PORT_UNUSED";
representation_a: string := "UNSIGNED";
signed_register_a: string := "UNREGISTERED";
signed_aclr_a : string := "NONE";
signed_latency_clock_a: string := "UNREGISTERED";
signed_latency_aclr_a: string := "NONE";
port_signb : string := "PORT_UNUSED";
representation_b: string := "UNSIGNED";
signed_register_b: string := "UNREGISTERED";
signed_aclr_b : string := "NONE";
signed_latency_clock_b: string := "UNREGISTERED";
signed_latency_aclr_b: string := "NONE";
number_of_multipliers: integer := 1;
multiplier1_direction: string := "NONE";
multiplier3_direction: string := "NONE";
multiplier_register0: string := "UNREGISTERED";
multiplier_aclr0: string := "NONE";
multiplier_register1: string := "UNREGISTERED";
multiplier_aclr1: string := "NONE";
multiplier_register2: string := "UNREGISTERED";
multiplier_aclr2: string := "NONE";
multiplier_register3: string := "UNREGISTERED";
multiplier_aclr3: string := "NONE";
port_addnsub1 : string := "PORT_UNUSED";
addnsub_multiplier_register1: string := "UNREGISTERED";
addnsub_multiplier_aclr1: string := "NONE";
addnsub_multiplier_latency_clock1: string := "UNREGISTERED";
addnsub_multiplier_latency_aclr1: string := "NONE";
port_addnsub3 : string := "PORT_UNUSED";
addnsub_multiplier_register3: string := "UNREGISTERED";
addnsub_multiplier_aclr3: string := "NONE";
addnsub_multiplier_latency_clock3: string := "UNREGISTERED";
addnsub_multiplier_latency_aclr3: string := "NONE";
adder1_rounding : string := "NO";
addnsub1_round_register: string := "UNREGISTERED";
addnsub1_round_aclr: string := "NONE";
adder3_rounding : string := "NO";
addnsub3_round_register: string := "UNREGISTERED";
addnsub3_round_aclr: string := "NONE";
multiplier01_rounding: string := "NO";
mult01_round_register: string := "UNREGISTERED";
mult01_round_aclr: string := "NONE";
multiplier23_rounding: string := "NO";
mult23_round_register: string := "UNREGISTERED";
mult23_round_aclr: string := "NONE";
width_msb : integer := 17;
output_rounding : string := "NO";
output_round_type: string := "NEAREST_INTEGER";
output_round_register: string := "UNREGISTERED";
output_round_aclr: string := "NONE";
chainout_rounding: string := "NO";
chainout_round_register: string := "UNREGISTERED";
chainout_round_aclr: string := "NONE";
chainout_round_output_register: string := "UNREGISTERED";
chainout_round_output_aclr: string := "NONE";
multiplier01_saturation: string := "NO";
mult01_saturation_register: string := "UNREGISTERED";
mult01_saturation_aclr: string := "NONE";
multiplier23_saturation: string := "NO";
mult23_saturation_register: string := "UNREGISTERED";
mult23_saturation_aclr: string := "NONE";
port_mult0_is_saturated: string := "NONE";
port_mult1_is_saturated: string := "NONE";
port_mult2_is_saturated: string := "NONE";
port_mult3_is_saturated: string := "NONE";
width_saturate_sign: integer := 1;
output_saturation: string := "NO";
port_output_is_overflow: string := "PORT_UNUSED";
output_saturate_type: string := "ASYMMETRIC";
output_saturate_register: string := "UNREGISTERED";
output_saturate_aclr: string := "NONE";
chainout_saturation: string := "NO";
port_chainout_sat_is_overflow: string := "PORT_UNUSED";
chainout_saturate_register: string := "UNREGISTERED";
chainout_saturate_aclr: string := "NONE";
chainout_saturate_output_register: string := "UNREGISTERED";
chainout_saturate_output_aclr: string := "NONE";
scanouta_register: string := "UNREGISTERED";
scanouta_aclr : string := "NONE";
width_chainin : integer := 1;
chainout_adder : string := "NO";
chainout_register: string := "UNREGISTERED";
chainout_aclr : string := "NONE";
zero_chainout_output_register: string := "UNREGISTERED";
zero_chainout_output_aclr: string := "NONE";
shift_mode : string := "NO";
rotate_register : string := "UNREGISTERED";
rotate_aclr : string := "NONE";
rotate_output_register: string := "UNREGISTERED";
rotate_output_aclr: string := "NONE";
shift_right_register: string := "UNREGISTERED";
shift_right_aclr: string := "NONE";
shift_right_output_register: string := "UNREGISTERED";
shift_right_output_aclr: string := "NONE";
zero_loopback_register: string := "UNREGISTERED";
zero_loopback_aclr: string := "NONE";
zero_loopback_output_register: string := "UNREGISTERED";
zero_loopback_output_aclr: string := "NONE";
accumulator : string := "NO";
accum_direction : string := "ADD";
loadconst_value : integer := 0;
use_sload_accum_port: string := "NO";
accum_sload_register: string := "UNREGISTERED";
accum_sload_aclr: string := "NONE";
accum_sload_latency_clock: string := "UNREGISTERED";
accum_sload_latency_aclr: string := "NONE";
loadconst_control_register: string := "UNREGISTERED";
loadconst_control_aclr: string := "NONE";
double_accum : string := "NO";
systolic_delay1 : string := "UNREGISTERED";
systolic_delay3 : string := "UNREGISTERED";
systolic_aclr1 : string := "NONE";
systolic_aclr3 : string := "NONE";
preadder_mode : string := "SIMPLE";
preadder_direction_0: string := "ADD";
preadder_direction_1: string := "ADD";
preadder_direction_2: string := "ADD";
preadder_direction_3: string := "ADD";
width_coef : integer := 1;
coefsel0_register: string := "UNREGISTERED";
coefsel0_aclr : string := "NONE";
coefsel1_register: string := "UNREGISTERED";
coefsel1_aclr : string := "NONE";
coefsel2_register: string := "UNREGISTERED";
coefsel2_aclr : string := "NONE";
coefsel3_register: string := "UNREGISTERED";
coefsel3_aclr : string := "NONE";
coef0_0 : integer := 0;
coef0_1 : integer := 0;
coef0_2 : integer := 0;
coef0_3 : integer := 0;
coef0_4 : integer := 0;
coef0_5 : integer := 0;
coef0_6 : integer := 0;
coef0_7 : integer := 0;
coef1_0 : integer := 0;
coef1_1 : integer := 0;
coef1_2 : integer := 0;
coef1_3 : integer := 0;
coef1_4 : integer := 0;
coef1_5 : integer := 0;
coef1_6 : integer := 0;
coef1_7 : integer := 0;
coef2_0 : integer := 0;
coef2_1 : integer := 0;
coef2_2 : integer := 0;
coef2_3 : integer := 0;
coef2_4 : integer := 0;
coef2_5 : integer := 0;
coef2_6 : integer := 0;
coef2_7 : integer := 0;
coef3_0 : integer := 0;
coef3_1 : integer := 0;
coef3_2 : integer := 0;
coef3_3 : integer := 0;
coef3_4 : integer := 0;
coef3_5 : integer := 0;
coef3_6 : integer := 0;
coef3_7 : integer := 0;
coefsel0_latency_clock: string := "UNREGISTERED";
coefsel0_latency_aclr: string := "NONE";
coefsel1_latency_clock: string := "UNREGISTERED";
coefsel1_latency_aclr: string := "NONE";
coefsel2_latency_clock: string := "UNREGISTERED";
coefsel2_latency_aclr: string := "NONE";
coefsel3_latency_clock: string := "UNREGISTERED";
coefsel3_latency_aclr: string := "NONE";
latency : integer := 0;
signed_pipeline_register_a: string := "UNREGISTERED";
signed_pipeline_aclr_a: string := "NONE";
signed_pipeline_register_b: string := "UNREGISTERED";
signed_pipeline_aclr_b: string := "NONE";
addnsub_multiplier_pipeline_register1: string := "UNREGISTERED";
addnsub_multiplier_pipeline_aclr1: string := "NONE";
addnsub_multiplier_pipeline_register3: string := "UNREGISTERED";
addnsub_multiplier_pipeline_aclr3: string := "NONE";
addnsub1_round_pipeline_register: string := "UNREGISTERED";
addnsub1_round_pipeline_aclr: string := "NONE";
addnsub3_round_pipeline_register: string := "UNREGISTERED";
addnsub3_round_pipeline_aclr: string := "NONE";
output_round_pipeline_register: string := "UNREGISTERED";
output_round_pipeline_aclr: string := "NONE";
chainout_round_pipeline_register: string := "UNREGISTERED";
chainout_round_pipeline_aclr: string := "NONE";
output_saturate_pipeline_register: string := "UNREGISTERED";
output_saturate_pipeline_aclr: string := "NONE";
chainout_saturate_pipeline_register: string := "UNREGISTERED";
chainout_saturate_pipeline_aclr: string := "NONE";
rotate_pipeline_register: string := "UNREGISTERED";
rotate_pipeline_aclr: string := "NONE";
shift_right_pipeline_register: string := "UNREGISTERED";
shift_right_pipeline_aclr: string := "NONE";
zero_loopback_pipeline_register: string := "UNREGISTERED";
zero_loopback_pipeline_aclr: string := "NONE";
accum_sload_pipeline_register: string := "UNREGISTERED";
accum_sload_pipeline_aclr: string := "NONE";
width_clock_all_wire_msb: integer := 3;
width_aclr_all_wire_msb: integer := 3;
width_ena_all_wire_msb: integer := 3;
width_a_total_msb: vl_notype;
width_a_msb : vl_notype;
width_b_total_msb: vl_notype;
width_b_msb : vl_notype;
width_c_total_msb: vl_notype;
width_c_msb : vl_notype;
width_scanina : vl_notype;
width_scanina_msb: vl_notype;
width_scaninb : vl_notype;
width_scaninb_msb: vl_notype;
width_sourcea_msb: vl_notype;
width_sourceb_msb: vl_notype;
width_scanouta_msb: vl_notype;
width_scanoutb_msb: vl_notype;
width_chainin_msb: vl_notype;
width_result_msb: vl_notype;
width_coef_msb : vl_notype;
dataa_split_ext_require: vl_notype;
dataa_port_sign : vl_notype;
width_a_ext : vl_notype;
width_a_ext_msb : vl_notype;
datab_split_ext_require: vl_notype;
datab_port_sign : vl_notype;
width_b_ext : vl_notype;
width_b_ext_msb : vl_notype;
coef_ext_require: vl_notype;
coef_port_sign : vl_notype;
width_coef_ext : vl_notype;
width_coef_ext_msb: vl_notype;
datac_split_ext_require: vl_notype;
datac_port_sign : vl_notype;
width_c_ext : vl_notype;
width_c_ext_msb : vl_notype;
width_scanchain : vl_notype;
width_scanchain_msb: vl_notype;
scanchain_port_sign: vl_notype;
preadder_representation: vl_notype;
width_preadder_input_a: vl_notype;
width_preadder_input_a_msb: vl_notype;
width_preadder_adder_result: vl_notype;
width_preadder_output_a: vl_notype;
width_preadder_output_a_msb: vl_notype;
width_preadder_output_b: vl_notype;
width_preadder_output_b_msb: vl_notype;
multiplier_input_representation_a: vl_notype;
multiplier_input_representation_b: vl_notype;
width_mult_source_a: vl_notype;
width_mult_source_a_msb: vl_notype;
width_mult_source_b: vl_notype;
width_mult_source_b_msb: vl_notype;
width_mult_result: vl_notype;
width_mult_result_msb: vl_notype;
width_adder_source: vl_notype;
width_adder_source_msb: vl_notype;
width_adder_result: vl_notype;
width_adder_result_msb: vl_notype;
width_chainin_ext: vl_notype;
width_original_result: vl_notype;
width_original_result_msb: vl_notype;
result_ext_width: vl_notype;
width_result_output: vl_notype;
width_result_output_msb: vl_notype;
width_chainout_adder_output: vl_notype
);
port(
dataa : in vl_logic_vector;
datab : in vl_logic_vector;
datac : in vl_logic_vector;
scanina : in vl_logic_vector;
scaninb : in vl_logic_vector;
sourcea : in vl_logic_vector;
sourceb : in vl_logic_vector;
clock3 : in vl_logic;
clock2 : in vl_logic;
clock1 : in vl_logic;
clock0 : in vl_logic;
aclr3 : in vl_logic;
aclr2 : in vl_logic;
aclr1 : in vl_logic;
aclr0 : in vl_logic;
ena3 : in vl_logic;
ena2 : in vl_logic;
ena1 : in vl_logic;
ena0 : in vl_logic;
signa : in vl_logic;
signb : in vl_logic;
addnsub1 : in vl_logic;
addnsub3 : in vl_logic;
result : out vl_logic_vector;
scanouta : out vl_logic_vector;
scanoutb : out vl_logic_vector;
mult01_round : in vl_logic;
mult23_round : in vl_logic;
mult01_saturation: in vl_logic;
mult23_saturation: in vl_logic;
addnsub1_round : in vl_logic;
addnsub3_round : in vl_logic;
mult0_is_saturated: out vl_logic;
mult1_is_saturated: out vl_logic;
mult2_is_saturated: out vl_logic;
mult3_is_saturated: out vl_logic;
output_round : in vl_logic;
chainout_round : in vl_logic;
output_saturate : in vl_logic;
chainout_saturate: in vl_logic;
overflow : out vl_logic;
chainout_sat_overflow: out vl_logic;
chainin : in vl_logic_vector;
zero_chainout : in vl_logic;
rotate : in vl_logic;
shift_right : in vl_logic;
zero_loopback : in vl_logic;
accum_sload : in vl_logic;
sload_accum : in vl_logic;
coefsel0 : in vl_logic_vector(2 downto 0);
coefsel1 : in vl_logic_vector(2 downto 0);
coefsel2 : in vl_logic_vector(2 downto 0);
coefsel3 : in vl_logic_vector(2 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of extra_latency : constant is 1;
attribute mti_svvh_generic_type of dedicated_multiplier_circuitry : constant is 1;
attribute mti_svvh_generic_type of dsp_block_balancing : constant is 1;
attribute mti_svvh_generic_type of selected_device_family : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of width_a : constant is 1;
attribute mti_svvh_generic_type of input_register_a0 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_a0 : constant is 1;
attribute mti_svvh_generic_type of input_source_a0 : constant is 1;
attribute mti_svvh_generic_type of input_register_a1 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_a1 : constant is 1;
attribute mti_svvh_generic_type of input_source_a1 : constant is 1;
attribute mti_svvh_generic_type of input_register_a2 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_a2 : constant is 1;
attribute mti_svvh_generic_type of input_source_a2 : constant is 1;
attribute mti_svvh_generic_type of input_register_a3 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_a3 : constant is 1;
attribute mti_svvh_generic_type of input_source_a3 : constant is 1;
attribute mti_svvh_generic_type of input_a0_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_a0_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_a1_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_a1_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_a2_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_a2_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_a3_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_a3_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of width_b : constant is 1;
attribute mti_svvh_generic_type of input_register_b0 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_b0 : constant is 1;
attribute mti_svvh_generic_type of input_source_b0 : constant is 1;
attribute mti_svvh_generic_type of input_register_b1 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_b1 : constant is 1;
attribute mti_svvh_generic_type of input_source_b1 : constant is 1;
attribute mti_svvh_generic_type of input_register_b2 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_b2 : constant is 1;
attribute mti_svvh_generic_type of input_source_b2 : constant is 1;
attribute mti_svvh_generic_type of input_register_b3 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_b3 : constant is 1;
attribute mti_svvh_generic_type of input_source_b3 : constant is 1;
attribute mti_svvh_generic_type of input_b0_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_b0_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_b1_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_b1_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_b2_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_b2_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_b3_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_b3_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of width_c : constant is 1;
attribute mti_svvh_generic_type of input_register_c0 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_c0 : constant is 1;
attribute mti_svvh_generic_type of input_register_c1 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_c1 : constant is 1;
attribute mti_svvh_generic_type of input_register_c2 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_c2 : constant is 1;
attribute mti_svvh_generic_type of input_register_c3 : constant is 1;
attribute mti_svvh_generic_type of input_aclr_c3 : constant is 1;
attribute mti_svvh_generic_type of input_c0_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_c0_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_c1_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_c1_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_c2_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_c2_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of input_c3_latency_clock : constant is 1;
attribute mti_svvh_generic_type of input_c3_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of width_result : constant is 1;
attribute mti_svvh_generic_type of output_register : constant is 1;
attribute mti_svvh_generic_type of output_aclr : constant is 1;
attribute mti_svvh_generic_type of port_signa : constant is 1;
attribute mti_svvh_generic_type of representation_a : constant is 1;
attribute mti_svvh_generic_type of signed_register_a : constant is 1;
attribute mti_svvh_generic_type of signed_aclr_a : constant is 1;
attribute mti_svvh_generic_type of signed_latency_clock_a : constant is 1;
attribute mti_svvh_generic_type of signed_latency_aclr_a : constant is 1;
attribute mti_svvh_generic_type of port_signb : constant is 1;
attribute mti_svvh_generic_type of representation_b : constant is 1;
attribute mti_svvh_generic_type of signed_register_b : constant is 1;
attribute mti_svvh_generic_type of signed_aclr_b : constant is 1;
attribute mti_svvh_generic_type of signed_latency_clock_b : constant is 1;
attribute mti_svvh_generic_type of signed_latency_aclr_b : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of multiplier1_direction : constant is 1;
attribute mti_svvh_generic_type of multiplier3_direction : constant is 1;
attribute mti_svvh_generic_type of multiplier_register0 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr0 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register1 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr1 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register2 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr2 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register3 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr3 : constant is 1;
attribute mti_svvh_generic_type of port_addnsub1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_register1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_aclr1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_clock1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_aclr1 : constant is 1;
attribute mti_svvh_generic_type of port_addnsub3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_register3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_aclr3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_clock3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_aclr3 : constant is 1;
attribute mti_svvh_generic_type of adder1_rounding : constant is 1;
attribute mti_svvh_generic_type of addnsub1_round_register : constant is 1;
attribute mti_svvh_generic_type of addnsub1_round_aclr : constant is 1;
attribute mti_svvh_generic_type of adder3_rounding : constant is 1;
attribute mti_svvh_generic_type of addnsub3_round_register : constant is 1;
attribute mti_svvh_generic_type of addnsub3_round_aclr : constant is 1;
attribute mti_svvh_generic_type of multiplier01_rounding : constant is 1;
attribute mti_svvh_generic_type of mult01_round_register : constant is 1;
attribute mti_svvh_generic_type of mult01_round_aclr : constant is 1;
attribute mti_svvh_generic_type of multiplier23_rounding : constant is 1;
attribute mti_svvh_generic_type of mult23_round_register : constant is 1;
attribute mti_svvh_generic_type of mult23_round_aclr : constant is 1;
attribute mti_svvh_generic_type of width_msb : constant is 1;
attribute mti_svvh_generic_type of output_rounding : constant is 1;
attribute mti_svvh_generic_type of output_round_type : constant is 1;
attribute mti_svvh_generic_type of output_round_register : constant is 1;
attribute mti_svvh_generic_type of output_round_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_rounding : constant is 1;
attribute mti_svvh_generic_type of chainout_round_register : constant is 1;
attribute mti_svvh_generic_type of chainout_round_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_round_output_register : constant is 1;
attribute mti_svvh_generic_type of chainout_round_output_aclr : constant is 1;
attribute mti_svvh_generic_type of multiplier01_saturation : constant is 1;
attribute mti_svvh_generic_type of mult01_saturation_register : constant is 1;
attribute mti_svvh_generic_type of mult01_saturation_aclr : constant is 1;
attribute mti_svvh_generic_type of multiplier23_saturation : constant is 1;
attribute mti_svvh_generic_type of mult23_saturation_register : constant is 1;
attribute mti_svvh_generic_type of mult23_saturation_aclr : constant is 1;
attribute mti_svvh_generic_type of port_mult0_is_saturated : constant is 1;
attribute mti_svvh_generic_type of port_mult1_is_saturated : constant is 1;
attribute mti_svvh_generic_type of port_mult2_is_saturated : constant is 1;
attribute mti_svvh_generic_type of port_mult3_is_saturated : constant is 1;
attribute mti_svvh_generic_type of width_saturate_sign : constant is 1;
attribute mti_svvh_generic_type of output_saturation : constant is 1;
attribute mti_svvh_generic_type of port_output_is_overflow : constant is 1;
attribute mti_svvh_generic_type of output_saturate_type : constant is 1;
attribute mti_svvh_generic_type of output_saturate_register : constant is 1;
attribute mti_svvh_generic_type of output_saturate_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_saturation : constant is 1;
attribute mti_svvh_generic_type of port_chainout_sat_is_overflow : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_register : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_output_register : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_output_aclr : constant is 1;
attribute mti_svvh_generic_type of scanouta_register : constant is 1;
attribute mti_svvh_generic_type of scanouta_aclr : constant is 1;
attribute mti_svvh_generic_type of width_chainin : constant is 1;
attribute mti_svvh_generic_type of chainout_adder : constant is 1;
attribute mti_svvh_generic_type of chainout_register : constant is 1;
attribute mti_svvh_generic_type of chainout_aclr : constant is 1;
attribute mti_svvh_generic_type of zero_chainout_output_register : constant is 1;
attribute mti_svvh_generic_type of zero_chainout_output_aclr : constant is 1;
attribute mti_svvh_generic_type of shift_mode : constant is 1;
attribute mti_svvh_generic_type of rotate_register : constant is 1;
attribute mti_svvh_generic_type of rotate_aclr : constant is 1;
attribute mti_svvh_generic_type of rotate_output_register : constant is 1;
attribute mti_svvh_generic_type of rotate_output_aclr : constant is 1;
attribute mti_svvh_generic_type of shift_right_register : constant is 1;
attribute mti_svvh_generic_type of shift_right_aclr : constant is 1;
attribute mti_svvh_generic_type of shift_right_output_register : constant is 1;
attribute mti_svvh_generic_type of shift_right_output_aclr : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_register : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_aclr : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_output_register : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_output_aclr : constant is 1;
attribute mti_svvh_generic_type of accumulator : constant is 1;
attribute mti_svvh_generic_type of accum_direction : constant is 1;
attribute mti_svvh_generic_type of loadconst_value : constant is 1;
attribute mti_svvh_generic_type of use_sload_accum_port : constant is 1;
attribute mti_svvh_generic_type of accum_sload_register : constant is 1;
attribute mti_svvh_generic_type of accum_sload_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_sload_latency_clock : constant is 1;
attribute mti_svvh_generic_type of accum_sload_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of loadconst_control_register : constant is 1;
attribute mti_svvh_generic_type of loadconst_control_aclr : constant is 1;
attribute mti_svvh_generic_type of double_accum : constant is 1;
attribute mti_svvh_generic_type of systolic_delay1 : constant is 1;
attribute mti_svvh_generic_type of systolic_delay3 : constant is 1;
attribute mti_svvh_generic_type of systolic_aclr1 : constant is 1;
attribute mti_svvh_generic_type of systolic_aclr3 : constant is 1;
attribute mti_svvh_generic_type of preadder_mode : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_0 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_1 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_2 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_3 : constant is 1;
attribute mti_svvh_generic_type of width_coef : constant is 1;
attribute mti_svvh_generic_type of coefsel0_register : constant is 1;
attribute mti_svvh_generic_type of coefsel0_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel1_register : constant is 1;
attribute mti_svvh_generic_type of coefsel1_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel2_register : constant is 1;
attribute mti_svvh_generic_type of coefsel2_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel3_register : constant is 1;
attribute mti_svvh_generic_type of coefsel3_aclr : constant is 1;
attribute mti_svvh_generic_type of coef0_0 : constant is 1;
attribute mti_svvh_generic_type of coef0_1 : constant is 1;
attribute mti_svvh_generic_type of coef0_2 : constant is 1;
attribute mti_svvh_generic_type of coef0_3 : constant is 1;
attribute mti_svvh_generic_type of coef0_4 : constant is 1;
attribute mti_svvh_generic_type of coef0_5 : constant is 1;
attribute mti_svvh_generic_type of coef0_6 : constant is 1;
attribute mti_svvh_generic_type of coef0_7 : constant is 1;
attribute mti_svvh_generic_type of coef1_0 : constant is 1;
attribute mti_svvh_generic_type of coef1_1 : constant is 1;
attribute mti_svvh_generic_type of coef1_2 : constant is 1;
attribute mti_svvh_generic_type of coef1_3 : constant is 1;
attribute mti_svvh_generic_type of coef1_4 : constant is 1;
attribute mti_svvh_generic_type of coef1_5 : constant is 1;
attribute mti_svvh_generic_type of coef1_6 : constant is 1;
attribute mti_svvh_generic_type of coef1_7 : constant is 1;
attribute mti_svvh_generic_type of coef2_0 : constant is 1;
attribute mti_svvh_generic_type of coef2_1 : constant is 1;
attribute mti_svvh_generic_type of coef2_2 : constant is 1;
attribute mti_svvh_generic_type of coef2_3 : constant is 1;
attribute mti_svvh_generic_type of coef2_4 : constant is 1;
attribute mti_svvh_generic_type of coef2_5 : constant is 1;
attribute mti_svvh_generic_type of coef2_6 : constant is 1;
attribute mti_svvh_generic_type of coef2_7 : constant is 1;
attribute mti_svvh_generic_type of coef3_0 : constant is 1;
attribute mti_svvh_generic_type of coef3_1 : constant is 1;
attribute mti_svvh_generic_type of coef3_2 : constant is 1;
attribute mti_svvh_generic_type of coef3_3 : constant is 1;
attribute mti_svvh_generic_type of coef3_4 : constant is 1;
attribute mti_svvh_generic_type of coef3_5 : constant is 1;
attribute mti_svvh_generic_type of coef3_6 : constant is 1;
attribute mti_svvh_generic_type of coef3_7 : constant is 1;
attribute mti_svvh_generic_type of coefsel0_latency_clock : constant is 1;
attribute mti_svvh_generic_type of coefsel0_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel1_latency_clock : constant is 1;
attribute mti_svvh_generic_type of coefsel1_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel2_latency_clock : constant is 1;
attribute mti_svvh_generic_type of coefsel2_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel3_latency_clock : constant is 1;
attribute mti_svvh_generic_type of coefsel3_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of latency : constant is 1;
attribute mti_svvh_generic_type of signed_pipeline_register_a : constant is 1;
attribute mti_svvh_generic_type of signed_pipeline_aclr_a : constant is 1;
attribute mti_svvh_generic_type of signed_pipeline_register_b : constant is 1;
attribute mti_svvh_generic_type of signed_pipeline_aclr_b : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_register1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_aclr1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_register3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_aclr3 : constant is 1;
attribute mti_svvh_generic_type of addnsub1_round_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of addnsub1_round_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of addnsub3_round_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of addnsub3_round_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of output_round_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of output_round_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_round_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of chainout_round_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of output_saturate_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of output_saturate_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of chainout_saturate_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of rotate_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of rotate_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of shift_right_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of shift_right_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of zero_loopback_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_sload_pipeline_register : constant is 1;
attribute mti_svvh_generic_type of accum_sload_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of width_clock_all_wire_msb : constant is 1;
attribute mti_svvh_generic_type of width_aclr_all_wire_msb : constant is 1;
attribute mti_svvh_generic_type of width_ena_all_wire_msb : constant is 1;
attribute mti_svvh_generic_type of width_a_total_msb : constant is 3;
attribute mti_svvh_generic_type of width_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_b_total_msb : constant is 3;
attribute mti_svvh_generic_type of width_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_c_total_msb : constant is 3;
attribute mti_svvh_generic_type of width_c_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanina : constant is 3;
attribute mti_svvh_generic_type of width_scanina_msb : constant is 3;
attribute mti_svvh_generic_type of width_scaninb : constant is 3;
attribute mti_svvh_generic_type of width_scaninb_msb : constant is 3;
attribute mti_svvh_generic_type of width_sourcea_msb : constant is 3;
attribute mti_svvh_generic_type of width_sourceb_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanouta_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanoutb_msb : constant is 3;
attribute mti_svvh_generic_type of width_chainin_msb : constant is 3;
attribute mti_svvh_generic_type of width_result_msb : constant is 3;
attribute mti_svvh_generic_type of width_coef_msb : constant is 3;
attribute mti_svvh_generic_type of dataa_split_ext_require : constant is 3;
attribute mti_svvh_generic_type of dataa_port_sign : constant is 3;
attribute mti_svvh_generic_type of width_a_ext : constant is 3;
attribute mti_svvh_generic_type of width_a_ext_msb : constant is 3;
attribute mti_svvh_generic_type of datab_split_ext_require : constant is 3;
attribute mti_svvh_generic_type of datab_port_sign : constant is 3;
attribute mti_svvh_generic_type of width_b_ext : constant is 3;
attribute mti_svvh_generic_type of width_b_ext_msb : constant is 3;
attribute mti_svvh_generic_type of coef_ext_require : constant is 3;
attribute mti_svvh_generic_type of coef_port_sign : constant is 3;
attribute mti_svvh_generic_type of width_coef_ext : constant is 3;
attribute mti_svvh_generic_type of width_coef_ext_msb : constant is 3;
attribute mti_svvh_generic_type of datac_split_ext_require : constant is 3;
attribute mti_svvh_generic_type of datac_port_sign : constant is 3;
attribute mti_svvh_generic_type of width_c_ext : constant is 3;
attribute mti_svvh_generic_type of width_c_ext_msb : constant is 3;
attribute mti_svvh_generic_type of width_scanchain : constant is 3;
attribute mti_svvh_generic_type of width_scanchain_msb : constant is 3;
attribute mti_svvh_generic_type of scanchain_port_sign : constant is 3;
attribute mti_svvh_generic_type of preadder_representation : constant is 3;
attribute mti_svvh_generic_type of width_preadder_input_a : constant is 3;
attribute mti_svvh_generic_type of width_preadder_input_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_preadder_adder_result : constant is 3;
attribute mti_svvh_generic_type of width_preadder_output_a : constant is 3;
attribute mti_svvh_generic_type of width_preadder_output_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_preadder_output_b : constant is 3;
attribute mti_svvh_generic_type of width_preadder_output_b_msb : constant is 3;
attribute mti_svvh_generic_type of multiplier_input_representation_a : constant is 3;
attribute mti_svvh_generic_type of multiplier_input_representation_b : constant is 3;
attribute mti_svvh_generic_type of width_mult_source_a : constant is 3;
attribute mti_svvh_generic_type of width_mult_source_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_source_b : constant is 3;
attribute mti_svvh_generic_type of width_mult_source_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_result : constant is 3;
attribute mti_svvh_generic_type of width_mult_result_msb : constant is 3;
attribute mti_svvh_generic_type of width_adder_source : constant is 3;
attribute mti_svvh_generic_type of width_adder_source_msb : constant is 3;
attribute mti_svvh_generic_type of width_adder_result : constant is 3;
attribute mti_svvh_generic_type of width_adder_result_msb : constant is 3;
attribute mti_svvh_generic_type of width_chainin_ext : constant is 3;
attribute mti_svvh_generic_type of width_original_result : constant is 3;
attribute mti_svvh_generic_type of width_original_result_msb : constant is 3;
attribute mti_svvh_generic_type of result_ext_width : constant is 3;
attribute mti_svvh_generic_type of width_result_output : constant is 3;
attribute mti_svvh_generic_type of width_result_output_msb : constant is 3;
attribute mti_svvh_generic_type of width_chainout_adder_output : constant is 3;
end altera_mult_add_rtl;
| mit | 0e3747839bc331dce44d7c03656e1495 | 0.664451 | 3.687137 | false | false | false | false |
adelapie/desl | des_loop.vhd | 1 | 2,714 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity des_loop is
port(clk : in std_logic;
rst : in std_logic;
mode : in std_logic; -- 0 encrypt, 1 decrypt
key_in : in std_logic_vector(55 downto 0);
blk_in : in std_logic_vector(63 downto 0);
blk_out : out std_logic_vector(63 downto 0));
end des_loop;
architecture Behavioral of des_loop is
signal after_ip_s : std_logic_vector(63 downto 0);
signal after_ip_minus_one_s : std_logic_vector(63 downto 0);
signal after_f_s : std_logic_vector(31 downto 0);
signal final_s : std_logic_vector(63 downto 0);
component des_round is
port(clk : in std_logic;
l_0 : in std_logic_vector(31 downto 0);
r_0 : in std_logic_vector(31 downto 0);
k_i : in std_logic_vector(47 downto 0);
l_1 : out std_logic_vector(31 downto 0);
r_1 : out std_logic_vector(31 downto 0));
end component;
component key_schedule is
port(clk : in std_logic;
rst : in std_logic;
mode : in std_logic; -- 0 encrypt, 1 decrypt
key : in std_logic_vector(55 downto 0);
key_out : out std_logic_vector(47 downto 0));
end component;
signal key_s : std_logic_vector(47 downto 0);
signal l_0_s : std_logic_vector(31 downto 0);
signal l_1_s : std_logic_vector(31 downto 0);
signal r_0_s : std_logic_vector(31 downto 0);
signal r_1_s : std_logic_vector(31 downto 0);
signal rst_s : std_logic;
begin
pr_rst_delay : process(clk, rst)
begin
if rising_edge(clk) then
rst_s <= rst;
end if;
end process;
pr_seq: process(clk, rst_s, blk_in)
begin
if rst_s = '1' then
l_0_s <= blk_in(63 downto 32);
r_0_s <= blk_in(31 downto 0);
elsif rising_edge(clk) then
l_0_s <= l_1_s;
r_0_s <= r_1_s;
end if;
end process;
DES_ROUND_0 : des_round port map (clk, l_0_s, r_0_s, key_s, l_1_s, r_1_s);
blk_out <= r_1_s & l_1_s;
KEY_SCHEDULE_0 : key_schedule port map (clk, rst, mode, key_in, key_s);
end Behavioral;
| gpl-3.0 | 4bcb46d33b7f67a6e9e734a349a269f0 | 0.643331 | 2.992282 | false | false | false | false |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_updt_cmdsts_if.vhd | 1 | 13,847 | -------------------------------------------------------------------------------
-- axi_sg_updt_cmdsts_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_cmdsts_if.vhd
-- Description: This entity is the descriptor update command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Update command write interface from fetch sm --
updt_cmnd_wr : in std_logic ; --
updt_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
updt_done : out std_logic ; --
updt_error : out std_logic ; --
updt_interr : out std_logic ; --
updt_slverr : out std_logic ; --
updt_decerr : out std_logic --
);
end axi_sg_updt_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_slverr_i : std_logic := '0';
signal updt_decerr_i : std_logic := '0';
signal updt_interr_i : std_logic := '0';
signal s2mm_error : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_slverr <= updt_slverr_i;
updt_decerr <= updt_decerr_i;
updt_interr <= updt_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor update command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
elsif(updt_cmnd_wr = '1')then
s_axis_updt_cmd_tvalid <= '1';
s_axis_updt_cmd_tdata <= updt_cmnd_data;
elsif(s_axis_updt_cmd_tready = '1')then
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_updt_sts_tready <= '0';
else
m_axis_updt_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_slverr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
updt_decerr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT);
updt_interr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Transfer Done
-------------------------------------------------------------------------------
XFER_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_done <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_done <= m_axis_updt_sts_tdata(DATAMOVER_STS_CMDDONE_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_done <= '0';
end if;
end if;
end process XFER_DONE;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error <= updt_slverr_i or updt_decerr_i or updt_interr_i;
-- Log errors into a global error output
UPDATE_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error <= '0';
elsif(s2mm_error = '1')then
updt_error <= '1';
end if;
end if;
end process UPDATE_ERROR_PROCESS;
end implementation;
| gpl-2.0 | b790a97497636f7058a7b0891582b6e5 | 0.409981 | 4.860302 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_clock.vhd | 10 | 1,426 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_clock is
generic (
RESET : string := "ACTIVE_HIGH";
DOMAIN : string := "default"
);
port (
clock_out : out std_logic;
clock : in std_logic;
aclr_out : out std_logic;
aclr : in std_logic;
aclr_n : in std_logic
);
end entity alt_dspbuilder_clock;
architecture rtl of alt_dspbuilder_clock is
component alt_dspbuilder_clock_GNQFU4PUDH is
generic (
RESET : string := "ACTIVE_HIGH";
DOMAIN : string := "default"
);
port (
aclr : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
begin
alt_dspbuilder_clock_GNQFU4PUDH_0: if ((RESET = "ACTIVE_HIGH") and (DOMAIN = "default")) generate
inst_alt_dspbuilder_clock_GNQFU4PUDH_0: alt_dspbuilder_clock_GNQFU4PUDH
generic map(RESET => "ACTIVE_HIGH", DOMAIN => "default")
port map(aclr => aclr, aclr_out => aclr_out, clock => clock, clock_out => clock_out);
end generate;
assert not (((RESET = "ACTIVE_HIGH") and (DOMAIN = "default")))
report "Please run generate again" severity error;
end architecture rtl;
| mit | d36299238bc880e6d498683a81236a2e | 0.70547 | 3.240909 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_bus_concat.vhd | 2 | 1,510 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_bus_concat is
generic (
WIDTHB : natural := 8;
WIDTHA : natural := 8
);
port (
b : in std_logic_vector(widthB-1 downto 0);
clock : in std_logic;
a : in std_logic_vector(widthA-1 downto 0);
aclr : in std_logic;
output : out std_logic_vector(widthA+widthB-1 downto 0)
);
end entity alt_dspbuilder_bus_concat;
architecture rtl of alt_dspbuilder_bus_concat is
component alt_dspbuilder_bus_concat_GNWZPLIVXS is
generic (
WIDTHB : natural := 8;
WIDTHA : natural := 16
);
port (
a : in std_logic_vector(16-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector(8-1 downto 0);
clock : in std_logic;
output : out std_logic_vector(24-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GNWZPLIVXS;
begin
alt_dspbuilder_bus_concat_GNWZPLIVXS_0: if ((WIDTHB = 8) and (WIDTHA = 16)) generate
inst_alt_dspbuilder_bus_concat_GNWZPLIVXS_0: alt_dspbuilder_bus_concat_GNWZPLIVXS
generic map(WIDTHB => 8, WIDTHA => 16)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
assert not (((WIDTHB = 8) and (WIDTHA = 16)))
report "Please run generate again" severity error;
end architecture rtl;
| mit | 34af4963d5dd25f8217fac5760efcb80 | 0.704636 | 3.205945 | false | false | false | false |
frznchckn/polarbear | hw/cores/uart/hdl/vhdl/cntr_bhv.vhd | 1 | 1,312 | --------------------------------------------------------------------------------
--|
--| Filename : cntr_bhv
--| Author : R. Friesenhahn
--| Origin Date : 20130906
--|
--------------------------------------------------------------------------------
--|
--| Abstract
--|
--|
--|
--------------------------------------------------------------------------------
--|
--| Modification History
--|
--|
--|
--------------------------------------------------------------------------------
--|
--| References
--|
--|
--|
--------------------------------------------------------------------------------
architecture bhv of cntr is
signal cntr : unsigned(CntrWidth-1 downto 0);
begin
CntrValue <= std_ulogic_vector(cntr);
P_CNTR : process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
cntr <= (others => '0');
CntReached <= '0';
else
CntReached <= '0';
if En = '1' then
if Clr = '1' then
cntr <= (others => '0');
elsif cntr = (unsigned(CritValue) - to_unsigned(1, CritValue'length)) then
CntReached <= '1';
cntr <= (others => '0');
else
cntr <= cntr + 1;
end if;
end if;
end if;
end if;
end process P_CNTR;
end architecture bhv;
| unlicense | 8f3132b5b62e10ca5ee5c55318509d31 | 0.336128 | 4.859259 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GN5P6ORZXA.vhd | 4 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN5P6ORZXA is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN5P6ORZXA is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 + 1 ,
width_inr=> 0,
width_outl=> 24,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture; | mit | b694567e4792ae54beb5fdc08b565689 | 0.648803 | 3.034602 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_MultAddMF.vhd | 12 | 10,158 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAddMF is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
intended_device_family : string :="Stratix";
representation : string :="SIGNED";
nMult : positive := 2;
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAddMF;
architecture MultAddMF_synth of alt_dspbuilder_MultAddMF is
function GetFirstAdd(s: AddSubOperator) return string is
begin
if (s=AddAdd) then
return "ADD";
elsif (s=AddSub) then
return "ADD";
else
return "SUB";
end if;
end GetFirstAdd;
function GetSecAdd(s: AddSubOperator) return string is
begin
if (s=AddAdd) then
return "ADD";
elsif (s=SubAdd) then
return "ADD";
else
return "SUB";
end if;
end GetSecAdd;
function Getinput_register(s: registerstructure) return string is
begin
if (s=InputsOnly) or (s=InputsandMultiplier) or (s=InputsandAdder) or (s=InputsMultiplierandAdder) then
return "CLOCK0";
else
return "UNREGISTERED";
end if;
end Getinput_register;
function Getinput_aclr(s: registerstructure) return string is
begin
if (s=InputsOnly) or (s=InputsandMultiplier) or (s=InputsandAdder)or (s=InputsMultiplierandAdder) then
return "ACLR3";
else
return "UNUSED";
end if;
end Getinput_aclr;
function Getmultiplier_register(s: registerstructure) return string is
begin
if (s=MultiplierOnly) or (s=MultiplierandAdder) or (s=InputsMultiplierandAdder) or (s=InputsandMultiplier) then
return "CLOCK0";
else
return "UNREGISTERED";
end if;
end Getmultiplier_register;
function Getmultiplier_aclr(s: registerstructure) return string is
begin
if (s=MultiplierOnly) or (s=MultiplierandAdder) or (s=InputsMultiplierandAdder) or (s=InputsandMultiplier) then
return "ACLR3";
else
return "UNUSED";
end if;
end Getmultiplier_aclr;
function Getoutput_register(s: registerstructure) return string is
begin
if (s=AdderOnly) or (s=InputsandAdder) or (s=InputsMultiplierandAdder) or (s=MultiplierandAdder) then
return "CLOCK0";
else
return "UNREGISTERED";
end if;
end Getoutput_register;
function Getoutput_aclr(s: registerstructure) return string is
begin
if (s=AdderOnly) or (s=InputsandAdder) or (s=InputsMultiplierandAdder) or (s=MultiplierandAdder) then
return "ACLR3";
else
return "UNUSED";
end if;
end Getoutput_aclr;
signal dataa_mf : std_logic_vector(nMult*width_a-1 downto 0);
signal datab_mf : std_logic_vector(nMult*width_a-1 downto 0);
begin
gm2:if nMult=2 generate
dataa_mf <= dat2aa & dat1aa;
datab_mf <= dat2ab & dat1ab;
end generate gm2;
gm3:if nMult=3 generate
dataa_mf <= dat3aa & dat2aa & dat1aa;
datab_mf <= dat3ab & dat2ab & dat1ab;
end generate gm3;
gm4:if nMult=4 generate
dataa_mf <= dat4aa & dat3aa & dat2aa & dat1aa;
datab_mf <= dat4ab & dat3ab & dat2ab & dat1ab;
end generate gm4;
gr:if (regstruct/=NoRegister) generate
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
input_register_b2 => getinput_register(regstruct),
input_register_a1 => getinput_register(regstruct),
multiplier_register0 => getmultiplier_register(regstruct),
signed_pipeline_aclr_b => "ACLR3",
input_register_b3 => getinput_register(regstruct),
input_register_a2 => getinput_register(regstruct),
multiplier_register1 => getmultiplier_register(regstruct),
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
input_register_a3 => getinput_register(regstruct),
multiplier_register2 => getmultiplier_register(regstruct),
signed_aclr_a => "ACLR3",
signed_register_a => "CLOCK0",
number_of_multipliers => nMult,
multiplier_register3 => getmultiplier_register(regstruct),
multiplier_aclr0 => "ACLR3",
addnsub_multiplier_pipeline_aclr3 => "ACLR3",
signed_aclr_b => "ACLR3",
signed_register_b => "CLOCK0",
lpm_type => "altmult_add",
multiplier_aclr1 => getmultiplier_aclr(regstruct),
input_aclr_b0 => getinput_aclr(regstruct),
output_register => getoutput_register(regstruct),
width_result => width_r,
representation_a => representation,
signed_pipeline_register_a => "CLOCK0",
input_source_b0 => "DATAB",
multiplier_aclr2 => getmultiplier_aclr(regstruct),
input_aclr_b1 => getinput_aclr(regstruct),
input_aclr_a0 => getinput_aclr(regstruct),
multiplier3_direction => GetSecAdd(direction),
addnsub_multiplier_register1 => "CLOCK0",
representation_b => representation,
signed_pipeline_register_b => "CLOCK0",
input_source_b1 => "DATAB",
input_source_a0 => "DATAA",
multiplier_aclr3 => getmultiplier_aclr(regstruct),
input_aclr_b2 => getinput_aclr(regstruct),
input_aclr_a1 => getinput_aclr(regstruct),
dedicated_multiplier_circuitry => "AUTO",
input_source_b2 => "DATAB",
input_source_a1 => "DATAA",
input_aclr_b3 => getinput_aclr(regstruct),
input_aclr_a2 => getinput_aclr(regstruct),
addnsub_multiplier_register3 => "CLOCK0",
addnsub_multiplier_aclr1 => "ACLR3",
output_aclr => getoutput_aclr(regstruct),
input_source_b3 => "DATAB",
input_source_a2 => "DATAA",
input_aclr_a3 => getinput_aclr(regstruct),
input_source_a3 => "DATAA",
addnsub_multiplier_aclr3 => "ACLR3",
intended_device_family => intended_device_family,
addnsub_multiplier_pipeline_register1 => "CLOCK0",
width_a => width_a,
input_register_b0 => getinput_register(regstruct),
width_b => width_a,
input_register_b1 => getinput_register(regstruct),
input_register_a0 => getinput_register(regstruct),
addnsub_multiplier_pipeline_register3 => "CLOCK0",
multiplier1_direction => GetFirstAdd(direction),
signed_pipeline_aclr_a => "ACLR3",
port_addnsub1 => "PORT_UNUSED",
port_addnsub3 => "PORT_UNUSED",
systolic_delay1 => "UNREGISTERED",
systolic_delay3 => "UNREGISTERED"
)
PORT MAP (
dataa => dataa_mf,
datab => datab_mf,
clock0 => clock,
aclr3 => aclr,
ena0 => ena,
result => result
);
end generate gr;
gc:if (regstruct=NoRegister) generate
ALTMULT_ADD_component : altmult_add GENERIC MAP (
input_register_b2 => "UNREGISTERED",
input_register_a1 => "UNREGISTERED",
multiplier_register0 => "UNREGISTERED",
signed_pipeline_aclr_b => "UNUSED",
input_register_b3 => "UNREGISTERED",
input_register_a2 => "UNREGISTERED",
multiplier_register1 => "UNREGISTERED",
addnsub_multiplier_pipeline_aclr1 => "UNUSED",
input_register_a3 => "UNREGISTERED",
multiplier_register2 => "UNREGISTERED",
signed_aclr_a => "UNUSED",
signed_register_a => "CLOCK0",
number_of_multipliers => nMult,
multiplier_register3 => "UNREGISTERED",
addnsub_multiplier_pipeline_aclr3 => "UNUSED",
signed_aclr_b => "UNUSED",
signed_register_b => "CLOCK0",
lpm_type => "altmult_add",
output_register => "UNREGISTERED",
width_result => width_r,
representation_a => representation,
signed_pipeline_register_a => "CLOCK0",
input_source_b0 => "DATAB",
multiplier3_direction => GetSecAdd(direction),
addnsub_multiplier_register1 => "CLOCK0",
representation_b => representation,
signed_pipeline_register_b => "CLOCK0",
input_source_b1 => "DATAB",
input_source_a0 => "DATAA",
dedicated_multiplier_circuitry => "AUTO",
input_source_b2 => "DATAB",
input_source_a1 => "DATAA",
addnsub_multiplier_register3 => "CLOCK0",
addnsub_multiplier_aclr1 => "UNUSED",
input_source_b3 => "DATAB",
input_source_a2 => "DATAA",
input_source_a3 => "DATAA",
addnsub_multiplier_aclr3 => "UNUSED",
intended_device_family => intended_device_family,
addnsub_multiplier_pipeline_register1 => "CLOCK0",
width_a => width_a,
input_register_b0 => "UNREGISTERED",
width_b => width_a,
input_register_b1 => "UNREGISTERED",
input_register_a0 => "UNREGISTERED",
addnsub_multiplier_pipeline_register3 => "CLOCK0",
multiplier1_direction => GetFirstAdd(direction),
signed_pipeline_aclr_a => "UNUSED",
port_addnsub1 => "PORT_UNUSED",
port_addnsub3 => "PORT_UNUSED",
systolic_delay1 => "UNREGISTERED",
systolic_delay3 => "UNREGISTERED"
)
PORT MAP (
dataa => dataa_mf,
datab => datab_mf,
result => result
);
end generate gc;
end MultAddMF_synth;
| mit | 5404416795df93d57ea6d9ddb9c7b6d0 | 0.683796 | 3.328309 | false | false | false | false |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_v_cfa_0_0/synth/tutorial_v_cfa_0_0.vhd | 1 | 9,759 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:v_cfa:7.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY v_cfa_v7_0;
USE v_cfa_v7_0.v_cfa;
ENTITY tutorial_v_cfa_0_0 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
s_axis_video_tuser : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
m_axis_video_tuser : OUT STD_LOGIC
);
END tutorial_v_cfa_0_0;
ARCHITECTURE tutorial_v_cfa_0_0_arch OF tutorial_v_cfa_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_v_cfa_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT v_cfa IS
GENERIC (
c_s_axis_video_data_width : INTEGER;
c_m_axis_video_data_width : INTEGER;
c_s_axis_video_tdata_width : INTEGER;
c_m_axis_video_tdata_width : INTEGER;
c_s_axis_video_format : INTEGER;
c_m_axis_video_format : INTEGER;
c_s_axis_video_tuser_width : INTEGER;
c_m_axis_video_tuser_width : INTEGER;
c_s_axi_addr_width : INTEGER;
c_s_axi_data_width : INTEGER;
c_s_axi_clk_freq_hz : INTEGER;
c_bayer_phase : INTEGER;
c_active_rows : INTEGER;
c_active_cols : INTEGER;
c_max_cols : INTEGER;
c_has_intc_if : INTEGER;
c_has_axi4_lite : INTEGER;
c_has_debug : INTEGER;
c_hor_filt : INTEGER;
c_fringe_tol : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
intc_if : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
irq : OUT STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
s_axis_video_tuser : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
m_axis_video_tuser : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT v_cfa;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tutorial_v_cfa_0_0_arch: ARCHITECTURE IS "v_cfa,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tutorial_v_cfa_0_0_arch : ARCHITECTURE IS "tutorial_v_cfa_0_0,v_cfa,{v_cfa=hardware_evaluation}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tutorial_v_cfa_0_0_arch: ARCHITECTURE IS "tutorial_v_cfa_0_0,v_cfa,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=v_cfa,x_ipVersion=7.0,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,[email protected](hardware_evaluation),c_s_axis_video_data_width=8,c_m_axis_video_data_width=8,c_s_axis_video_tdata_width=8,c_m_axis_video_tdata_width=24,c_s_axis_video_format=12,c_m_axis_video_format=2,c_s_axis_video_tuser_width=1,c_m_axis_video_tuser_width=1,c_s_axi_addr_width=9,c_s_axi_data_width=32,c_s_axi_clk_freq_hz=100000000,c_bayer_phase=2,c_active_rows=1080,c_active_cols=1920,c_max_cols=1920,c_has_intc_if=0,c_has_axi4_lite=0,c_has_debug=0,c_hor_filt=1,c_fringe_tol=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TUSER";
BEGIN
U0 : v_cfa
GENERIC MAP (
c_s_axis_video_data_width => 8,
c_m_axis_video_data_width => 8,
c_s_axis_video_tdata_width => 8,
c_m_axis_video_tdata_width => 24,
c_s_axis_video_format => 12,
c_m_axis_video_format => 2,
c_s_axis_video_tuser_width => 1,
c_m_axis_video_tuser_width => 1,
c_s_axi_addr_width => 9,
c_s_axi_data_width => 32,
c_s_axi_clk_freq_hz => 100000000,
c_bayer_phase => 2,
c_active_rows => 1080,
c_active_cols => 1920,
c_max_cols => 1920,
c_has_intc_if => 0,
c_has_axi4_lite => 0,
c_has_debug => 0,
c_hor_filt => 1,
c_fringe_tol => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => aresetn,
s_axi_aclk => '0',
s_axi_aclken => '1',
s_axi_aresetn => '1',
s_axis_video_tdata => s_axis_video_tdata,
s_axis_video_tready => s_axis_video_tready,
s_axis_video_tvalid => s_axis_video_tvalid,
s_axis_video_tlast => s_axis_video_tlast,
s_axis_video_tuser => s_axis_video_tuser,
m_axis_video_tdata => m_axis_video_tdata,
m_axis_video_tvalid => m_axis_video_tvalid,
m_axis_video_tready => m_axis_video_tready,
m_axis_video_tlast => m_axis_video_tlast,
m_axis_video_tuser => m_axis_video_tuser,
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
s_axi_arvalid => '0',
s_axi_rready => '0'
);
END tutorial_v_cfa_0_0_arch;
| gpl-2.0 | b66de0d3f631306d456afbc9b93f7da5 | 0.678246 | 3.150097 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_sImpulse11Altr.vhd | 8 | 2,408 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulse11Altr is
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulse11Altr ;
architecture syn of alt_dspbuilder_sImpulse11Altr is
type States_ImpulseAltr is (sclear, shigh,slowend);
signal current_state : States_ImpulseAltr;
signal next_state : States_ImpulseAltr;
begin
rp:process(clock,aclr)
begin
if aclr='1' then
current_state <= sclear;
elsif clock'event and clock='1' then
if (sclr='1') then
current_state <= sclear;
elsif (ena='1') then
current_state <= next_state;
end if;
end if;
end process;
cp:process(current_state, sclr,ena)
begin
case current_state is
when sclear =>
q <= '0';
if (ena='1') and (sclr='0') then
next_state <= shigh;
else
next_state <= sclear;
end if;
when shigh =>
q <= '1';
if (sclr='1') then
next_state <= sclear;
else
next_state <= slowend ;
end if;
when slowend =>
q <= '0';
if (sclr='1') then
next_state <= sclear;
else
next_state <= slowend ;
end if;
end case;
end process;
end syn;
| mit | 417ff446b4934828f6a5190cab9add85 | 0.625415 | 3.84051 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP.vhd | 2 | 15,793 | -- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.11.10:36:06
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP is
port (
check_en : out std_logic; -- check_en.wire
ready : in std_logic := '0'; -- ready.wire
data_en : out std_logic; -- data_en.wire
counter : in std_logic_vector(23 downto 0) := (others => '0'); -- counter.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
pixel_num : in std_logic_vector(47 downto 0) := (others => '0'); -- pixel_num.wire
ctrl_en : out std_logic -- ctrl_en.wire
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component StateMachineEditor is
port (
clock : in std_logic := 'X'; -- clk
counter : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
data_end : in std_logic := 'X'; -- wire
ready : in std_logic := 'X'; -- wire
reset : in std_logic := 'X'; -- wire
state : out std_logic_vector(2 downto 0) -- wire
);
end component StateMachineEditor;
component alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNTWZRTG4I;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_case_statement_GN4KF5KLTA is
generic (
number_outputs : integer := 8;
hasDefault : natural := 0;
pipeline : natural := 0;
width : integer := 8
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
r0 : out std_logic; -- wire
r1 : out std_logic; -- wire
r2 : out std_logic; -- wire
r3 : out std_logic; -- wire
r4 : out std_logic -- wire
);
end component alt_dspbuilder_case_statement_GN4KF5KLTA;
component alt_dspbuilder_if_statement_GNIV4UP6ZO is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNIV4UP6ZO;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic (
delay : positive := 1;
signal_type : string := "Impulse";
impulse_width : positive := 1
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
result : out std_logic; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_single_pulse_GN2XGKTRR3;
component alt_dspbuilder_constant_GNQJ63TWA6 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNQJ63TWA6;
component alt_dspbuilder_port_GNUJT4YY5I is
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(47 downto 0) -- wire
);
end component alt_dspbuilder_port_GNUJT4YY5I;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
component alt_dspbuilder_cast_GN5P6ORZXA is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN5P6ORZXA;
component alt_dspbuilder_cast_GNLWRZWTQF is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNLWRZWTQF;
signal pipelined_adder1user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder1user_aclrGND:output -> Pipelined_Adder1:user_aclr
signal pipelined_adder1enavcc_output_wire : std_logic; -- Pipelined_Adder1enaVCC:output -> Pipelined_Adder1:ena
signal single_pulsesclrgnd_output_wire : std_logic; -- Single_PulsesclrGND:output -> Single_Pulse:sclr
signal single_pulseenavcc_output_wire : std_logic; -- Single_PulseenaVCC:output -> Single_Pulse:ena
signal counter_0_output_wire : std_logic_vector(23 downto 0); -- counter_0:output -> [If_Statement6:a, cast27:input]
signal constant15_output_wire : std_logic_vector(23 downto 0); -- Constant15:output -> Pipelined_Adder1:datab
signal pipelined_adder1_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder1:result -> If_Statement6:b
signal single_pulse_result_wire : std_logic; -- Single_Pulse:result -> State_Machine_Editor:reset
signal ready_0_output_wire : std_logic; -- ready_0:output -> State_Machine_Editor:ready
signal if_statement6_true_wire : std_logic; -- If_Statement6:true -> State_Machine_Editor:data_end
signal case_statement_r1_wire : std_logic; -- Case_Statement:r1 -> ctrl_en_0:input
signal case_statement_r2_wire : std_logic; -- Case_Statement:r2 -> data_en_0:input
signal case_statement_r3_wire : std_logic; -- Case_Statement:r3 -> check_en_0:input
signal pixel_num_0_output_wire : std_logic_vector(47 downto 0); -- pixel_num_0:output -> cast26:input
signal cast26_output_wire : std_logic_vector(23 downto 0); -- cast26:output -> Pipelined_Adder1:dataa
signal cast27_output_wire : std_logic_vector(23 downto 0); -- cast27:output -> State_Machine_Editor:counter
signal state_machine_editor_state_wire : std_logic_vector(2 downto 0); -- State_Machine_Editor:state -> cast28:input
signal cast28_output_wire : std_logic_vector(2 downto 0); -- cast28:output -> Case_Statement:input
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Case_Statement:clock, Pipelined_Adder1:clock, Single_Pulse:clock, State_Machine_Editor:clock]
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Case_Statement:aclr, Pipelined_Adder1:aclr, Single_Pulse:aclr]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => case_statement_r1_wire, -- input.wire
output => ctrl_en -- output.wire
);
state_machine_editor : component StateMachineEditor
port map (
clock => clock_0_clock_output_clk, -- clock.clk
reset => single_pulse_result_wire, -- reset.wire
ready => ready_0_output_wire, -- ready.wire
counter => cast27_output_wire, -- counter.wire
data_end => if_statement6_true_wire, -- data_end.wire
state => state_machine_editor_state_wire -- state.wire
);
pipelined_adder1 : component alt_dspbuilder_pipelined_adder_GNTWZRTG4I
generic map (
width => 24,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast26_output_wire, -- dataa.wire
datab => constant15_output_wire, -- datab.wire
result => pipelined_adder1_result_wire, -- result.wire
user_aclr => pipelined_adder1user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder1enavcc_output_wire -- ena.wire
);
pipelined_adder1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder1user_aclrgnd_output_wire -- output.wire
);
pipelined_adder1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder1enavcc_output_wire -- output.wire
);
case_statement : component alt_dspbuilder_case_statement_GN4KF5KLTA
generic map (
number_outputs => 5,
hasDefault => 1,
pipeline => 0,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
input => cast28_output_wire, -- input.wire
r0 => open, -- r0.wire
r1 => case_statement_r1_wire, -- r1.wire
r2 => case_statement_r2_wire, -- r2.wire
r3 => case_statement_r3_wire, -- r3.wire
r4 => open -- r4.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => case_statement_r2_wire, -- input.wire
output => data_en -- output.wire
);
if_statement6 : component alt_dspbuilder_if_statement_GNIV4UP6ZO
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a=b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement6_true_wire, -- true.wire
a => counter_0_output_wire, -- a.wire
b => pipelined_adder1_result_wire -- b.wire
);
counter_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter, -- input.wire
output => counter_0_output_wire -- output.wire
);
single_pulse : component alt_dspbuilder_single_pulse_GN2XGKTRR3
generic map (
delay => 1,
signal_type => "Step Down",
impulse_width => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
result => single_pulse_result_wire, -- result.wire
sclr => single_pulsesclrgnd_output_wire, -- sclr.wire
ena => single_pulseenavcc_output_wire -- ena.wire
);
single_pulsesclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => single_pulsesclrgnd_output_wire -- output.wire
);
single_pulseenavcc : component alt_dspbuilder_vcc_GN
port map (
output => single_pulseenavcc_output_wire -- output.wire
);
constant15 : component alt_dspbuilder_constant_GNQJ63TWA6
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000100",
width => 24
)
port map (
output => constant15_output_wire -- output.wire
);
check_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => case_statement_r3_wire, -- input.wire
output => check_en -- output.wire
);
pixel_num_0 : component alt_dspbuilder_port_GNUJT4YY5I
port map (
input => pixel_num, -- input.wire
output => pixel_num_0_output_wire -- output.wire
);
ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ready, -- input.wire
output => ready_0_output_wire -- output.wire
);
cast26 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => pixel_num_0_output_wire, -- input.wire
output => cast26_output_wire -- output.wire
);
cast27 : component alt_dspbuilder_cast_GN5P6ORZXA
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => cast27_output_wire -- output.wire
);
cast28 : component alt_dspbuilder_cast_GNLWRZWTQF
generic map (
round => 0,
saturate => 0
)
port map (
input => state_machine_editor_state_wire, -- input.wire
output => cast28_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP
| mit | 8e29033c2f2685f03cad7c89242ac435 | 0.552713 | 3.40293 | false | false | false | false |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_v_cfa_0_0/sim/tutorial_v_cfa_0_0.vhd | 1 | 8,663 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:v_cfa:7.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY v_cfa_v7_0;
USE v_cfa_v7_0.v_cfa;
ENTITY tutorial_v_cfa_0_0 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
s_axis_video_tuser : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
m_axis_video_tuser : OUT STD_LOGIC
);
END tutorial_v_cfa_0_0;
ARCHITECTURE tutorial_v_cfa_0_0_arch OF tutorial_v_cfa_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_v_cfa_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT v_cfa IS
GENERIC (
c_s_axis_video_data_width : INTEGER;
c_m_axis_video_data_width : INTEGER;
c_s_axis_video_tdata_width : INTEGER;
c_m_axis_video_tdata_width : INTEGER;
c_s_axis_video_format : INTEGER;
c_m_axis_video_format : INTEGER;
c_s_axis_video_tuser_width : INTEGER;
c_m_axis_video_tuser_width : INTEGER;
c_s_axi_addr_width : INTEGER;
c_s_axi_data_width : INTEGER;
c_s_axi_clk_freq_hz : INTEGER;
c_bayer_phase : INTEGER;
c_active_rows : INTEGER;
c_active_cols : INTEGER;
c_max_cols : INTEGER;
c_has_intc_if : INTEGER;
c_has_axi4_lite : INTEGER;
c_has_debug : INTEGER;
c_hor_filt : INTEGER;
c_fringe_tol : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
intc_if : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
irq : OUT STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
s_axis_video_tuser : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
m_axis_video_tuser : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT v_cfa;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TUSER";
BEGIN
U0 : v_cfa
GENERIC MAP (
c_s_axis_video_data_width => 8,
c_m_axis_video_data_width => 8,
c_s_axis_video_tdata_width => 8,
c_m_axis_video_tdata_width => 24,
c_s_axis_video_format => 12,
c_m_axis_video_format => 2,
c_s_axis_video_tuser_width => 1,
c_m_axis_video_tuser_width => 1,
c_s_axi_addr_width => 9,
c_s_axi_data_width => 32,
c_s_axi_clk_freq_hz => 100000000,
c_bayer_phase => 2,
c_active_rows => 1080,
c_active_cols => 1920,
c_max_cols => 1920,
c_has_intc_if => 0,
c_has_axi4_lite => 0,
c_has_debug => 0,
c_hor_filt => 1,
c_fringe_tol => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => aresetn,
s_axi_aclk => '0',
s_axi_aclken => '1',
s_axi_aresetn => '1',
s_axis_video_tdata => s_axis_video_tdata,
s_axis_video_tready => s_axis_video_tready,
s_axis_video_tvalid => s_axis_video_tvalid,
s_axis_video_tlast => s_axis_video_tlast,
s_axis_video_tuser => s_axis_video_tuser,
m_axis_video_tdata => m_axis_video_tdata,
m_axis_video_tvalid => m_axis_video_tvalid,
m_axis_video_tready => m_axis_video_tready,
m_axis_video_tlast => m_axis_video_tlast,
m_axis_video_tuser => m_axis_video_tuser,
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
s_axi_arvalid => '0',
s_axi_rready => '0'
);
END tutorial_v_cfa_0_0_arch;
| gpl-2.0 | 48d434e464d2523236ef6c48592bbf2a | 0.668244 | 3.267823 | false | false | false | false |
freecores/t48 | rtl/vhdl/t8243/t8243_async_notri.vhd | 1 | 4,898 | -------------------------------------------------------------------------------
--
-- The T8243 asynchronous toplevel without tri-state signals
--
-- $Id: t8243_async_notri.vhd,v 1.1 2006-07-13 22:53:56 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t8243_async_notri is
port (
-- System Interface -------------------------------------------------------
reset_n_i : in std_logic;
-- Control Interface ------------------------------------------------------
cs_n_i : in std_logic;
prog_n_i : in std_logic;
-- Port 2 Interface -------------------------------------------------------
p2_i : in std_logic_vector(3 downto 0);
p2_o : out std_logic_vector(3 downto 0);
p2_en_o : out std_logic;
-- Port 4 Interface -------------------------------------------------------
p4_i : in std_logic_vector(3 downto 0);
p4_o : out std_logic_vector(3 downto 0);
p4_en_o : out std_logic;
-- Port 5 Interface -------------------------------------------------------
p5_i : in std_logic_vector(3 downto 0);
p5_o : out std_logic_vector(3 downto 0);
p5_en_o : out std_logic;
-- Port 6 Interface -------------------------------------------------------
p6_i : in std_logic_vector(3 downto 0);
p6_o : out std_logic_vector(3 downto 0);
p6_en_o : out std_logic;
-- Port 7 Interface -------------------------------------------------------
p7_i : in std_logic_vector(3 downto 0);
p7_o : out std_logic_vector(3 downto 0);
p7_en_o : out std_logic
);
end t8243_async_notri;
use work.t8243_comp_pack.t8243_core;
architecture struct of t8243_async_notri is
signal vdd_s : std_logic;
begin
vdd_s <= '1';
-----------------------------------------------------------------------------
-- The T8243 Core
-----------------------------------------------------------------------------
t8243_core_b : t8243_core
generic map (
clk_fall_level_g => 0
)
port map (
clk_i => prog_n_i,
clk_rise_en_i => vdd_s,
clk_fall_en_i => vdd_s,
reset_n_i => reset_n_i,
cs_n_i => cs_n_i,
prog_n_i => prog_n_i,
p2_i => p2_i,
p2_o => p2_o,
p2_en_o => p2_en_o,
p4_i => p4_i,
p4_o => p4_o,
p4_en_o => p4_en_o,
p5_i => p5_i,
p5_o => p5_o,
p5_en_o => p5_en_o,
p6_i => p6_i,
p6_o => p6_o,
p6_en_o => p6_en_o,
p7_i => p7_i,
p7_o => p7_o,
p7_en_o => p7_en_o
);
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | 9ac61a17bc8b19e79d06250e21768a8a | 0.510821 | 3.937299 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_SBF.vhd | 20 | 8,869 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SBF is
generic (
width_inl : natural :=10;
width_inr : natural :=10;
width_outl : natural :=8;
width_outr : natural :=8;
round : natural :=1;
satur : natural :=1;
lpm_signed : BusArithm :=BusIsSigned
);
port (
xin : in std_logic_vector(width_inl+width_inr-1 downto 0);
yout : out std_logic_vector(width_outl+width_outr-1 downto 0)
);
end alt_dspbuilder_SBF;
architecture SBF_SYNTH of alt_dspbuilder_SBF is
signal youtround : std_logic_vector(width_inl+width_outr-1 downto 0);
signal youtroundc : std_logic_vector(width_outl+width_outr-1 downto 0);
signal xinextc : std_logic_vector(width_outl+width_inr-1 downto 0) ;
signal xin_int : std_logic_vector(width_inl+width_inr-1 downto 0);
begin
u0: alt_dspbuilder_sAltrPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion , width=> width_inl+width_inr)
port map (d => xin, r => xin_int);
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--(width_inl>=width_outl) and (width_inr>=width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_a:if (width_inl>=width_outl) and (width_inr>=width_outr) generate
gnsnr:if (round = 0) generate
gnsat:if (satur=0) generate
gl:for i in 0 to width_outl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
end generate gnsat;
gsat:if (satur>0) generate
gl:for i in 0 to width_inl+width_outr-1 generate
youtround(i) <= xin_int(i+width_inr-width_outr);
end generate ;
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout);
end generate gsat;
end generate ;
rnd:if (round>0)generate
ura:alt_dspbuilder_AROUND
generic map ( widthin => width_inl+width_inr,
widthout => width_inl+width_outr)
port map ( xin => xin_int,
yout => youtround);
gns:if satur=0 generate
yout(width_outl+width_outr-1 downto 0) <= youtround(width_outl+width_outr-1 downto 0);
end generate gns;
gs:if (satur>0) generate
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout
);
end generate gs;
end generate rnd;
end generate sbf_a;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl>width_outl) and (width_inr<width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_b:if (width_inl>=width_outl) and (width_inr<width_outr) generate
ns:if (satur=0) generate
gc:for i in 0 to width_outr-width_inr-1 generate
yout(i) <= '0';
end generate gc;
gl:for i in width_outr-width_inr to width_outl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
end generate ns ;
gs:if (satur>0) generate
gc:for i in 0 to width_outr-width_inr-1 generate
youtround(i) <= '0';
end generate gc;
gl:for i in width_outr-width_inr to width_inl+width_outr-1 generate
youtround(i) <= xin_int(i+width_inr-width_outr);
end generate ;
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout);
end generate gs ;
end generate sbf_b;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl<width_outl) and (width_inr>width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_c:if (width_inl<width_outl) and (width_inr>=width_outr) generate
gnsnr:if (round = 0) generate
gl:for i in 0 to width_inl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
gc:for i in width_inl+width_outr to width_outl+width_outr-1 generate
yout(i) <= xin_int( width_inl+width_inr-1);
end generate ;
end generate ;
rnd:if (round > 0) generate
xinextc(width_inl+width_inr-1 downto 0) <= xin_int(width_inl+width_inr-1 downto 0);
gxinextc:for i in width_inl+width_inr to width_outl+width_inr-1 generate
xinextc(i) <= xin_int(width_inl+width_inr-1);
end generate gxinextc;
urb:alt_dspbuilder_AROUND
generic map ( widthin => width_outl+width_inr,
widthout => width_outl+width_outr)
port map ( xin => xinextc,
yout => youtroundc);
yout <= youtroundc;
end generate rnd ;
end generate sbf_c;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl<width_outl) and (width_inr<width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_d:if (width_inl<width_outl) and (width_inr<width_outr) generate
gl:for i in width_outr-width_inr to width_inl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate gl;
gc:for i in 0 to width_outr-width_inr-1 generate
yout(i) <= '0';
end generate gc;
gcv:for i in width_inl+width_outr to width_outl+width_outr-1 generate
yout(i) <= xin_int( width_inl+width_inr-1);
end generate gcv;
end generate sbf_d;
end SBF_SYNTH;
| mit | 55f1b2950d874b130909af7d9956d9be | 0.448416 | 4.259846 | false | false | false | false |
michaelmiehling/A25_VME_TB | Testbench/M25P32/memory_access.vhd | 1 | 9,527 | -------------------------------------------------------
-- Author: Hugues CREUSY
--February 2004
-- VHDL model
-- project: M25P32 50 MHz,
-- release: 1.0
-----------------------------------------------------
-- Unit : Memory Access
-----------------------------------------------------
-------------------------------------------------------------
-- These VHDL models are provided "as is" without warranty
-- of any kind, included but not limited to, implied warranty
-- of merchantability and fitness for a particular purpose.
-------------------------------------------------------------
-----------------------------------------------------------
--
-- MEMORY ACCESS
--
-----------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY STD;
USE STD.textio.ALL;
LIBRARY work;
USE WORK.mem_util_pkg.ALL;
-----------------------------------------------------------
-- Entity
-----------------------------------------------------------
-- This entity modelizes the access to the memory array
-----------------------------------------------------------
ENTITY Memory_Access IS
GENERIC( init_file: string;
SIZE : positive;
Plength : positive;
SSIZE : positive;
NB_BIT_DATA: positive;
NB_BIT_ADD: positive;
NB_BIT_ADD_MEM: positive
);
PORT( add_mem: IN std_logic_vector(NB_BIT_ADD_MEM-1 downto 0);
BE_enable,SE_enable,add_pp_enable,PP_enable,read_enable,data_request: IN boolean;
p_prog: IN page (0 TO (Plength-1));
data_to_read: OUT std_logic_vector (NB_BIT_DATA-1 downto 0)
);
END Memory_Access;
-----------------------------------------------------------------
-- Architecture
-----------------------------------------------------------------
-- The architecture contains one process which executes
-- read and write instructions
-- on the content. This content is initialized and further
-- saved by two procedures
-- (write_to_file and read_from_file) in the convenient text file
-----------------------------------------------------------------
ARCHITECTURE Static_Alloc OF Memory_Access IS
CONSTANT bit_to_code_mem:natural:=TO_bit_code(size/NB_BIT_DATA);
CONSTANT top_mem:positive:=size/NB_BIT_DATA-1;
TYPE memoire IS array (0 TO top_mem) OF std_logic_vector(7 downto 0);
--------------------------- PROCEDURES ------------------------
------------------------- READ FROM FILE ----------------------
PROCEDURE read_from_file ( file_name:string;
memory: out memoire) IS
file data_file : text open read_mode is file_name;
VARIABLE L: line;
VARIABLE LSB,MSB:std_logic_vector(3 downto 0);
VARIABLE dr: string (1 to 2*Plength);
VARIABLE index_m: natural:=0;
BEGIN
WHILE NOT endfile(data_file) LOOP
readline(data_file,L);
READ(L,dr);
deallocate(L);
FOR i IN 1 TO Plength LOOP
CASE dr(2*(i-1)+1) IS
WHEN '0'=> MSB := "0000";
WHEN '1'=> MSB := "0001";
WHEN '2'=> MSB := "0010";
WHEN '3'=> MSB := "0011";
WHEN '4'=> MSB := "0100";
WHEN '5'=> MSB := "0101";
WHEN '6'=> MSB := "0110";
WHEN '7'=> MSB := "0111";
WHEN '8'=> MSB := "1000";
WHEN '9'=> MSB := "1001";
WHEN 'A'=> MSB := "1010";
WHEN 'B'=> MSB := "1011";
WHEN 'C'=> MSB := "1100";
WHEN 'D'=> MSB := "1101";
WHEN 'E'=> MSB := "1110";
WHEN 'F'=> MSB := "1111";
WHEN 'a'=> MSB := "1010";
WHEN 'b'=> MSB := "1011";
WHEN 'c'=> MSB := "1100";
WHEN 'd'=> MSB := "1101";
WHEN 'e'=> MSB := "1110";
WHEN 'f'=> MSB := "1111";
WHEN OTHERS => null;
END CASE;
CASE dr(2*(i-1)+2) IS
WHEN '0'=> LSB := "0000";
WHEN '1'=> LSB := "0001";
WHEN '2'=> LSB := "0010";
WHEN '3'=> LSB := "0011";
WHEN '4'=> LSB := "0100";
WHEN '5'=> LSB := "0101";
WHEN '6'=> LSB := "0110";
WHEN '7'=> LSB := "0111";
WHEN '8'=> LSB := "1000";
WHEN '9'=> LSB := "1001";
WHEN 'A'=> LSB := "1010";
WHEN 'B'=> LSB := "1011";
WHEN 'C'=> LSB := "1100";
WHEN 'D'=> LSB := "1101";
WHEN 'E'=> LSB := "1110";
WHEN 'F'=> LSB := "1111";
WHEN 'a'=> MSB := "1010";
WHEN 'b'=> MSB := "1011";
WHEN 'c'=> MSB := "1100";
WHEN 'd'=> MSB := "1101";
WHEN 'e'=> MSB := "1110";
WHEN 'f'=> MSB := "1111";
WHEN OTHERS => null;
END CASE;
memory(index_m):=(MSB(3),MSB(2),MSB(1),MSB(0),LSB(3),LSB(2),LSB(1),LSB(0));
index_m:=index_m+1;
END LOOP;
END LOOP;
END read_from_file;
----------------------------------------------------------
---------------- WRITE TO FILE --------------------
PROCEDURE write_to_file ( file_name:string;
memory:IN memoire) IS
file data_file : text open write_mode is file_name;
VARIABLE L: line;
VARIABLE LSB,MSB:std_logic_vector(3 downto 0);
VARIABLE dr: string (1 to 2*Plength);
VARIABLE index_m:natural:=0;
BEGIN
WHILE (index_m<TOP_MEM) LOOP
FOR i IN 1 TO Plength LOOP
FOR j IN 0 TO 3 LOOP
LSB(j):= memory(index_m)(j);
MSB(j):= memory(index_m)(j+4);
END LOOP;
index_m:=index_m+1;
CASE MSB IS
WHEN "0000" => dr(2*(i-1)+1):='0';
WHEN "0001" => dr(2*(i-1)+1):='1';
WHEN "0010" => dr(2*(i-1)+1):='2';
WHEN "0011" => dr(2*(i-1)+1):='3';
WHEN "0100" => dr(2*(i-1)+1):='4';
WHEN "0101" => dr(2*(i-1)+1):='5';
WHEN "0110" => dr(2*(i-1)+1):='6';
WHEN "0111" => dr(2*(i-1)+1):='7';
WHEN "1000" => dr(2*(i-1)+1):='8';
WHEN "1001" => dr(2*(i-1)+1):='9';
WHEN "1010" => dr(2*(i-1)+1):='A';
WHEN "1011" => dr(2*(i-1)+1):='B';
WHEN "1100" => dr(2*(i-1)+1):='C';
WHEN "1101" => dr(2*(i-1)+1):='D';
WHEN "1110" => dr(2*(i-1)+1):='E';
WHEN "1111" => dr(2*(i-1)+1):='F';
WHEN OTHERS => null;
END CASE;
CASE LSB IS
WHEN "0000" => dr(2*(i-1)+2):='0';
WHEN "0001" => dr(2*(i-1)+2):='1';
WHEN "0010" => dr(2*(i-1)+2):='2';
WHEN "0011" => dr(2*(i-1)+2):='3';
WHEN "0100" => dr(2*(i-1)+2):='4';
WHEN "0101" => dr(2*(i-1)+2):='5';
WHEN "0110" => dr(2*(i-1)+2):='6';
WHEN "0111" => dr(2*(i-1)+2):='7';
WHEN "1000" => dr(2*(i-1)+2):='8';
WHEN "1001" => dr(2*(i-1)+2):='9';
WHEN "1010" => dr(2*(i-1)+2):='A';
WHEN "1011" => dr(2*(i-1)+2):='B';
WHEN "1100" => dr(2*(i-1)+2):='C';
WHEN "1101" => dr(2*(i-1)+2):='D';
WHEN "1110" => dr(2*(i-1)+2):='E';
WHEN "1111" => dr(2*(i-1)+2):='F';
WHEN OTHERS => null;
END CASE;
END LOOP;
WRITE(L,dr);
writeline(data_file,L);
END LOOP;
END write_to_file;
----------------------------------------------------
BEGIN -- architecture body begins here
----------------------------------------------------
-- PROCESS MEMORY
----------------------------------------------------
memory: PROCESS
VARIABLE content:memoire;
VARIABLE deb_zone, int_add:natural:=0;
VARIABLE cut_add:std_logic_vector(bit_to_code_mem-1 downto 0);
VARIABLE int_add_mem:natural:=to_bit_code(size/NB_BIT_DATA);
VARIABLE first_run:boolean:=true;
VARIABLE message, my_file: LINE;
BEGIN
---------------------------------
-- initialisation of memory array
---------------------------------
IF (first_run) THEN
WRITE (message,string'("Trying to load "));
WRITE (message, init_file);
writeline(output, message);
read_from_file(init_file,content);
first_run:=false;
END IF;
WAIT ON add_pp_enable,pp_enable, be_enable, se_enable, data_request,read_enable;
-----------------------------------------------------------
-- To ignore don't care MSB of the address
-----------------------------------------------------------
IF ( (se_enable'event AND se_enable)
OR (add_pp_enable'event AND add_pp_enable)
OR (read_enable'event AND read_enable) ) THEN
FOR i IN 0 TO bit_to_code_mem-1 LOOP
cut_add(i):=add_mem(i);
END LOOP;
END IF;
-----------------------------------------------------------
-- Read instruction
-----------------------------------------------------------
IF (data_request'event AND data_request AND read_enable) THEN
int_add:=to_natural(cut_add);
IF (int_add>top_mem) THEN
FOR i IN 0 TO bit_to_code_mem-1 LOOP
cut_add(i):='0';
END LOOP;
int_add:=0;
END IF;
data_to_read<=content(int_add);
cut_add:=add_inc(cut_add); -- to increase the adress
END IF;
IF (READ_enable'event AND (NOT read_enable)) THEN
FOR i IN 0 TO NB_BIT_DATA-1 LOOP
data_to_read(i)<='0';
END LOOP;
END IF;
----------------------------------------------------------
-- Page program instruction
-- To find the first adress of the memory to be programmed
----------------------------------------------------------
IF (add_pp_enable'event AND add_pp_enable) THEN
int_add_mem:=to_natural(cut_add);
int_add:=top_mem+1;
WHILE int_add>int_add_mem LOOP
int_add:=int_add-Plength;
END LOOP;
END IF;
------------------------------------------------------
-- Sector erase instruction
-- To find the first adress of the sector to be erased
------------------------------------------------------
IF (se_enable'event AND se_enable) THEN
int_add:=add_sector(cut_add,SIZE/NB_BIT_DATA,SSIZE/NB_BIT_DATA);
END IF;
------------------------------------------------------
-- Write or erase cycle execution
------------------------------------------------------
IF (pp_enable'event AND (pp_enable)) THEN
FOR i IN 0 TO (Plength-1) LOOP
content (int_add+i):=p_prog(i) AND content(int_add+i);
END LOOP;
-- write_to_file(init_file,content);
END IF;
IF (be_enable'event AND (NOT be_enable)) THEN
FOR i IN 0 TO top_mem LOOP
content(i):="11111111";
END LOOP;
-- write_to_file(init_file,content);
END IF;
IF (se_enable'event AND (NOT se_enable)) THEN
FOR i IN int_add TO (int_add+SSIZE/NB_BIT_DATA-1) LOOP
content(i):="11111111";
END LOOP;
-- write_to_file(init_file,content);
END IF;
END PROCESS memory;
END static_alloc;
| gpl-3.0 | 5fa34703fae539611a0c37e40f2af000 | 0.490081 | 3.134913 | false | false | false | false |
freecores/t48 | rtl/vhdl/t8243/t8243_sync_notri.vhd | 1 | 5,798 | -------------------------------------------------------------------------------
--
-- The T8243 synchronous toplevel without tri-state signals
--
-- $Id: t8243_sync_notri.vhd,v 1.1 2006-07-13 22:53:56 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t8243_sync_notri is
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
clk_en_i : in std_logic;
reset_n_i : in std_logic;
-- Control Interface ------------------------------------------------------
cs_n_i : in std_logic;
prog_n_i : in std_logic;
-- Port 2 Interface -------------------------------------------------------
p2_i : in std_logic_vector(3 downto 0);
p2_o : out std_logic_vector(3 downto 0);
p2_en_o : out std_logic;
-- Port 4 Interface -------------------------------------------------------
p4_i : in std_logic_vector(3 downto 0);
p4_o : out std_logic_vector(3 downto 0);
p4_en_o : out std_logic;
-- Port 5 Interface -------------------------------------------------------
p5_i : in std_logic_vector(3 downto 0);
p5_o : out std_logic_vector(3 downto 0);
p5_en_o : out std_logic;
-- Port 6 Interface -------------------------------------------------------
p6_i : in std_logic_vector(3 downto 0);
p6_o : out std_logic_vector(3 downto 0);
p6_en_o : out std_logic;
-- Port 7 Interface -------------------------------------------------------
p7_i : in std_logic_vector(3 downto 0);
p7_o : out std_logic_vector(3 downto 0);
p7_en_o : out std_logic
);
end t8243_sync_notri;
use work.t8243_comp_pack.t8243_core;
architecture struct of t8243_sync_notri is
signal prog_n_q : std_logic;
signal clk_rise_en_s,
clk_fall_en_s : std_logic;
begin
-----------------------------------------------------------------------------
-- Process edge_detect
--
-- Purpose:
-- Implements the sequential element required for edge detection
-- on the PROG input.
--
edge_detect: process (clk_i, reset_n_i)
begin
if reset_n_i = '0' then
prog_n_q <= '1';
elsif rising_edge(clk_i) then
if clk_en_i = '1' then
prog_n_q <= prog_n_i;
end if;
end if;
end process edge_detect;
--
-----------------------------------------------------------------------------
-- clock enables to detect rising and falling edges of PROG
clk_rise_en_s <= clk_en_i and
not prog_n_q and prog_n_i;
clk_fall_en_s <= clk_en_i and
prog_n_q and not prog_n_i;
-----------------------------------------------------------------------------
-- The T8243 Core
-----------------------------------------------------------------------------
t8243_core_b : t8243_core
generic map (
clk_fall_level_g => 1
)
port map (
clk_i => clk_i,
clk_rise_en_i => clk_rise_en_s,
clk_fall_en_i => clk_fall_en_s,
reset_n_i => reset_n_i,
cs_n_i => cs_n_i,
prog_n_i => prog_n_i,
p2_i => p2_i,
p2_o => p2_o,
p2_en_o => p2_en_o,
p4_i => p4_i,
p4_o => p4_o,
p4_en_o => p4_en_o,
p5_i => p5_i,
p5_o => p5_o,
p5_en_o => p5_en_o,
p6_i => p6_i,
p6_o => p6_o,
p6_en_o => p6_en_o,
p7_i => p7_i,
p7_o => p7_o,
p7_en_o => p7_en_o
);
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | 4fb4546998939568215b3ee8a9cae7ad | 0.502415 | 3.875668 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_divider.vhd | 2 | 1,996 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_divider is
generic (
SIGNED : natural := 0;
WIDTH : natural := 8;
PIPELINE : natural := 0
);
port (
user_aclr : in std_logic := '0';
denom : in std_logic_vector(width-1 downto 0) := (others=>'0');
quotient : out std_logic_vector(width-1 downto 0);
remain : out std_logic_vector(width-1 downto 0);
numer : in std_logic_vector(width-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_divider;
architecture rtl of alt_dspbuilder_divider is
component alt_dspbuilder_divider_GNKAPZN5MO is
generic (
SIGNED : natural := 0;
WIDTH : natural := 24;
PIPELINE : natural := 0
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
denom : in std_logic_vector(24-1 downto 0) := (others=>'0');
ena : in std_logic := '0';
numer : in std_logic_vector(24-1 downto 0) := (others=>'0');
quotient : out std_logic_vector(24-1 downto 0);
remain : out std_logic_vector(24-1 downto 0);
user_aclr : in std_logic := '0'
);
end component alt_dspbuilder_divider_GNKAPZN5MO;
begin
alt_dspbuilder_divider_GNKAPZN5MO_0: if ((SIGNED = 0) and (WIDTH = 24) and (PIPELINE = 0)) generate
inst_alt_dspbuilder_divider_GNKAPZN5MO_0: alt_dspbuilder_divider_GNKAPZN5MO
generic map(SIGNED => 0, WIDTH => 24, PIPELINE => 0)
port map(aclr => aclr, clock => clock, denom => denom, ena => ena, numer => numer, quotient => quotient, remain => remain, user_aclr => user_aclr);
end generate;
assert not (((SIGNED = 0) and (WIDTH = 24) and (PIPELINE = 0)))
report "Please run generate again" severity error;
end architecture rtl;
| mit | f70c2bc3a07e213cd7d09f2558fad72b | 0.671844 | 3.153239 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_multiplexer_GNHQFFAUXQ.vhd | 4 | 1,302 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiplexer_GNHQFFAUXQ is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 25;
pipeline : natural := 0;
number_inputs : natural := 3);
port(
clock : in std_logic;
aclr : in std_logic;
sel : in std_logic_vector(1 downto 0);
result : out std_logic_vector(24 downto 0);
ena : in std_logic;
user_aclr : in std_logic;
in0 : in std_logic_vector(24 downto 0);
in1 : in std_logic_vector(24 downto 0);
in2 : in std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_multiplexer_GNHQFFAUXQ is
signal data_muxin : std_logic_vector(74 downto 0);
Begin
data_muxin <= in2 & in1 & in0 ;
nto1Multiplexeri : alt_dspbuilder_sMuxAltr generic map (
lpm_pipeline =>0,
lpm_size => 3,
lpm_widths => 2 ,
lpm_width => 25 ,
SelOneHot => 0 )
port map (
clock => clock,
ena => ena,
user_aclr => user_aclr,
aclr => aclr,
data => data_muxin,
sel => sel,
result => result);
end architecture;
| mit | 170493ba6f50ca5365d94b3c50e24391 | 0.639017 | 2.824295 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_SDelay.vhd | 20 | 3,612 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SDelay is
generic (
lpm_width : positive :=8;
lpm_delay : positive :=2;
SequenceLength : positive :=1;
SequenceValue : std_logic_vector :="1"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic ;
ena : in std_logic :='1';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
sclr : in std_logic :='0';
result : out std_logic_vector(lpm_width-1 downto 0) :=(others=>'0')
);
end alt_dspbuilder_SDelay;
architecture SDelay_SYNTH of alt_dspbuilder_SDelay is
type StdUArray is array (lpm_delay-1 downto 0) of std_logic_vector (lpm_width-1 downto 0);
signal DelayLine : StdUArray;
signal dataa_int : std_logic_vector(lpm_width-1 downto 0);
signal seqenable : std_logic ;
signal enadff : std_logic ;
signal aclr_i : std_logic ;
begin
aclr_i <= aclr or user_aclr;
u0: alt_dspbuilder_sAltrPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion , width=> lpm_width)
port map (d => dataa, r => dataa_int);
gnoseq: if ((SequenceLength=1) and (SequenceValue="1")) generate
enadff <= ena;
end generate gnoseq;
gseq: if not ((SequenceLength=1) and (SequenceValue="1")) generate
u:alt_dspbuilder_vecseq generic map (SequenceLength=>SequenceLength,SequenceValue=>SequenceValue)
port map (clock=>clock, ena=>ena, aclr=>aclr_i, sclr=>sclr, yout=> seqenable);
enadff <= seqenable and ena;
end generate gseq;
gen1:if lpm_delay=1 generate
process(clock, aclr_i)
begin
if aclr_i='1' then
result <=(others=>'0');
elsif clock'event and clock='1' then
if (sclr ='1') then
result <=(others=>'0');
elsif enadff ='1' then
result <= dataa_int;
end if ;
end if ;
end process ;
end generate ;
gen2:if lpm_delay>1 generate
process(clock, aclr_i)
begin
if aclr_i='1' then
DelayLine <= (others => (others => '0'));
elsif clock'event and clock='1' then
if (sclr='1') then
DelayLine <= (others => (others => '0'));
elsif (enadff='1') then
DelayLine(0) <= dataa_int;
for i in 1 to lpm_delay-1 loop
DelayLine(i) <= DelayLine(i-1);
end loop;
end if ;
end if ;
end process ;
result <= DelayLine(lpm_delay-1);
end generate ;
end SDelay_SYNTH;
| mit | 843bf3d33e00aa200f73b0bdd690ba5d | 0.634551 | 3.583333 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/db/alt_dspbuilder_single_pulse.vhd | 4 | 1,650 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_single_pulse is
generic (
DELAY : positive := 1;
SIGNAL_TYPE : string := "Impulse";
IMPULSE_WIDTH : positive := 1
);
port (
result : out std_logic;
clock : in std_logic := '0';
sclr : in std_logic := '0';
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_single_pulse;
architecture rtl of alt_dspbuilder_single_pulse is
component alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic (
DELAY : positive := 1;
SIGNAL_TYPE : string := "Step Down";
IMPULSE_WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
result : out std_logic;
sclr : in std_logic := '0'
);
end component alt_dspbuilder_single_pulse_GN2XGKTRR3;
begin
alt_dspbuilder_single_pulse_GN2XGKTRR3_0: if ((DELAY = 1) and (SIGNAL_TYPE = "Step Down") and (IMPULSE_WIDTH = 1)) generate
inst_alt_dspbuilder_single_pulse_GN2XGKTRR3_0: alt_dspbuilder_single_pulse_GN2XGKTRR3
generic map(DELAY => 1, SIGNAL_TYPE => "Step Down", IMPULSE_WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, result => result, sclr => sclr);
end generate;
assert not (((DELAY = 1) and (SIGNAL_TYPE = "Step Down") and (IMPULSE_WIDTH = 1)))
report "Please run generate again" severity error;
end architecture rtl;
| mit | 15df727e261ff5397359395f141b373a | 0.68303 | 3.16092 | false | false | false | false |
nulldozer/purisc | Compute_Group/MAGIC_clocked/RAM_4.vhd | 1 | 10,399 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM_4.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY RAM_4 IS
PORT
(
aclr : IN STD_LOGIC := '0';
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END RAM_4;
ARCHITECTURE SYN OF ram_4 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
init_file => "RAM_4.mif",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "CLEAR0",
outdata_aclr_b => "CLEAR0",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "OLD_DATA",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 10,
widthad_b => 10,
width_a => 32,
width_b => 32,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
aclr0 => aclr,
address_a => address_a,
address_b => address_b,
clock0 => clock,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "1"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "RAM_4.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INIT_FILE STRING "RAM_4.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
-- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
-- Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
-- Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
-- Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
-- Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_4.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_4.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_4.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_4.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_4_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | ffd6735fbb7098074919b4fce0b6e729 | 0.666314 | 3.290823 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT.vhd | 2 | 45,577 | -- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:05:29
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT is
port (
sop : out std_logic; -- sop.wire
pixel_num : in std_logic_vector(47 downto 0) := (others => '0'); -- pixel_num.wire
ctrl_en : in std_logic := '0'; -- ctrl_en.wire
counter : in std_logic_vector(23 downto 0) := (others => '0'); -- counter.wire
ctrl_pak1 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak1.wire
colorbar : in std_logic_vector(23 downto 0) := (others => '0'); -- colorbar.wire
data : out std_logic_vector(24 downto 0); -- data.wire
data_en : in std_logic := '0'; -- data_en.wire
ctrl_pak2 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak2.wire
eop : out std_logic; -- eop.wire
ctrl_pak3 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak3.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0' -- .reset
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GN33BXJAZX is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN33BXJAZX;
component alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNTWZRTG4I;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_case_statement_GNWMX2GCN2 is
generic (
number_outputs : integer := 8;
hasDefault : natural := 0;
pipeline : natural := 0;
width : integer := 8
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
r0 : out std_logic; -- wire
r1 : out std_logic -- wire
);
end component alt_dspbuilder_case_statement_GNWMX2GCN2;
component alt_dspbuilder_case_statement_GNFTM45DFU is
generic (
number_outputs : integer := 8;
hasDefault : natural := 0;
pipeline : natural := 0;
width : integer := 8
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
r0 : out std_logic; -- wire
r1 : out std_logic -- wire
);
end component alt_dspbuilder_case_statement_GNFTM45DFU;
component alt_dspbuilder_multiplexer_GNLGLCKYZ5 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(23 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in2 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in3 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNLGLCKYZ5;
component alt_dspbuilder_port_GNEHYJMBQS is
port (
input : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEHYJMBQS;
component alt_dspbuilder_constant_GNNKZSYI73 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNKZSYI73;
component alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GN6E6AAQPZ;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_constant_GNZEH3JAKA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNZEH3JAKA;
component alt_dspbuilder_delay_GNIYBMGPQQ is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNIYBMGPQQ;
component alt_dspbuilder_constant_GNLJWFEWBD is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNLJWFEWBD;
component alt_dspbuilder_constant_GNQJ63TWA6 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNQJ63TWA6;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_if_statement_GNTVBNRAAT is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNTVBNRAAT;
component alt_dspbuilder_delay_GNNBTO2F3L is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNNBTO2F3L;
component alt_dspbuilder_port_GNUJT4YY5I is
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(47 downto 0) -- wire
);
end component alt_dspbuilder_port_GNUJT4YY5I;
component alt_dspbuilder_multiplexer_GNHQFFAUXQ is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(24 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in2 : in std_logic_vector(24 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNHQFFAUXQ;
component alt_dspbuilder_multiplexer_GN6ODCX3D4 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(24 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(24 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GN6ODCX3D4;
component alt_dspbuilder_delay_GNVJUPFOX3 is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNVJUPFOX3;
component alt_dspbuilder_cast_GN3ODVPHOL is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN3ODVPHOL;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
component alt_dspbuilder_cast_GNCPEUNC4M is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCPEUNC4M;
component alt_dspbuilder_cast_GNKDE2NVCC is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKDE2NVCC;
component alt_dspbuilder_cast_GNCCZ56SYK is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCCZ56SYK;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
signal pipelined_adder2user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder2user_aclrGND:output -> Pipelined_Adder2:user_aclr
signal pipelined_adder2enavcc_output_wire : std_logic; -- Pipelined_Adder2enaVCC:output -> Pipelined_Adder2:ena
signal multiplexeruser_aclrgnd_output_wire : std_logic; -- Multiplexeruser_aclrGND:output -> Multiplexer:user_aclr
signal multiplexerenavcc_output_wire : std_logic; -- MultiplexerenaVCC:output -> Multiplexer:ena
signal delaysclrgnd_output_wire : std_logic; -- DelaysclrGND:output -> Delay:sclr
signal delayenavcc_output_wire : std_logic; -- DelayenaVCC:output -> Delay:ena
signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr
signal delay5enavcc_output_wire : std_logic; -- Delay5enaVCC:output -> Delay5:ena
signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr
signal delay3enavcc_output_wire : std_logic; -- Delay3enaVCC:output -> Delay3:ena
signal multiplexer1user_aclrgnd_output_wire : std_logic; -- Multiplexer1user_aclrGND:output -> Multiplexer1:user_aclr
signal multiplexer1enavcc_output_wire : std_logic; -- Multiplexer1enaVCC:output -> Multiplexer1:ena
signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr
signal delay1enavcc_output_wire : std_logic; -- Delay1enaVCC:output -> Delay1:ena
signal multiplexer2user_aclrgnd_output_wire : std_logic; -- Multiplexer2user_aclrGND:output -> Multiplexer2:user_aclr
signal multiplexer2enavcc_output_wire : std_logic; -- Multiplexer2enaVCC:output -> Multiplexer2:ena
signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr
signal delay2enavcc_output_wire : std_logic; -- Delay2enaVCC:output -> Delay2:ena
signal counter_0_output_wire : std_logic_vector(23 downto 0); -- counter_0:output -> [Bus_Conversion1:input, If_Statement7:a, cast29:input, cast32:input]
signal constant1_output_wire : std_logic_vector(23 downto 0); -- Constant1:output -> Delay:input
signal ctrl_pak1_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak1_0:output -> Delay1:input
signal ctrl_pak2_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak2_0:output -> Delay2:input
signal ctrl_pak3_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak3_0:output -> Delay3:input
signal constant7_output_wire : std_logic_vector(23 downto 0); -- Constant7:output -> Delay5:input
signal if_statement7_true_wire : std_logic; -- If_Statement7:true -> [Logical_Bit_Operator10:data0, Logical_Bit_Operator9:data1]
signal data_en_0_output_wire : std_logic; -- data_en_0:output -> [Logical_Bit_Operator10:data1, Logical_Bit_Operator3:data1, cast34:input]
signal case_statement2_r1_wire : std_logic; -- Case_Statement2:r1 -> Logical_Bit_Operator3:data0
signal ctrl_en_0_output_wire : std_logic; -- ctrl_en_0:output -> [Logical_Bit_Operator4:data0, Logical_Bit_Operator9:data0, cast33:input]
signal case_statement2_r0_wire : std_logic; -- Case_Statement2:r0 -> Logical_Bit_Operator4:data1
signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Logical_Bit_Operator5:data0
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Logical_Bit_Operator5:data1
signal logical_bit_operator10_result_wire : std_logic; -- Logical_Bit_Operator10:result -> Logical_Bit_Operator6:data1
signal logical_bit_operator9_result_wire : std_logic; -- Logical_Bit_Operator9:result -> Logical_Bit_Operator6:data0
signal bus_conversion1_output_wire : std_logic_vector(1 downto 0); -- Bus_Conversion1:output -> Multiplexer:sel
signal delay_output_wire : std_logic_vector(23 downto 0); -- Delay:output -> Multiplexer:in0
signal delay1_output_wire : std_logic_vector(23 downto 0); -- Delay1:output -> Multiplexer:in1
signal delay2_output_wire : std_logic_vector(23 downto 0); -- Delay2:output -> Multiplexer:in2
signal delay3_output_wire : std_logic_vector(23 downto 0); -- Delay3:output -> Multiplexer:in3
signal bus_concatenation_output_wire : std_logic_vector(1 downto 0); -- Bus_Concatenation:output -> Multiplexer1:sel
signal bus_concatenation1_output_wire : std_logic_vector(1 downto 0); -- Bus_Concatenation1:output -> Multiplexer2:sel
signal multiplexer2_result_wire : std_logic_vector(24 downto 0); -- Multiplexer2:result -> Multiplexer1:in1
signal constant18_output_wire : std_logic_vector(23 downto 0); -- Constant18:output -> Pipelined_Adder2:datab
signal pipelined_adder2_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder2:result -> If_Statement7:c
signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> sop_0:input
signal logical_bit_operator6_result_wire : std_logic; -- Logical_Bit_Operator6:result -> eop_0:input
signal multiplexer1_result_wire : std_logic_vector(24 downto 0); -- Multiplexer1:result -> data_0:input
signal cast29_output_wire : std_logic_vector(15 downto 0); -- cast29:output -> Case_Statement1:input
signal case_statement1_r0_wire : std_logic; -- Case_Statement1:r0 -> cast30:input
signal cast30_output_wire : std_logic_vector(0 downto 0); -- cast30:output -> Bus_Concatenation1:a
signal case_statement1_r1_wire : std_logic; -- Case_Statement1:r1 -> cast31:input
signal cast31_output_wire : std_logic_vector(0 downto 0); -- cast31:output -> Bus_Concatenation1:b
signal cast32_output_wire : std_logic_vector(15 downto 0); -- cast32:output -> Case_Statement2:input
signal cast33_output_wire : std_logic_vector(0 downto 0); -- cast33:output -> Bus_Concatenation:a
signal cast34_output_wire : std_logic_vector(0 downto 0); -- cast34:output -> Bus_Concatenation:b
signal constant16_output_wire : std_logic_vector(15 downto 0); -- Constant16:output -> cast35:input
signal cast35_output_wire : std_logic_vector(23 downto 0); -- cast35:output -> If_Statement7:b
signal constant5_output_wire : std_logic_vector(23 downto 0); -- Constant5:output -> cast36:input
signal cast36_output_wire : std_logic_vector(24 downto 0); -- cast36:output -> Multiplexer1:in0
signal multiplexer_result_wire : std_logic_vector(23 downto 0); -- Multiplexer:result -> cast37:input
signal cast37_output_wire : std_logic_vector(24 downto 0); -- cast37:output -> Multiplexer1:in2
signal colorbar_0_output_wire : std_logic_vector(23 downto 0); -- colorbar_0:output -> cast38:input
signal cast38_output_wire : std_logic_vector(24 downto 0); -- cast38:output -> Multiplexer2:in0
signal delay5_output_wire : std_logic_vector(23 downto 0); -- Delay5:output -> cast39:input
signal cast39_output_wire : std_logic_vector(24 downto 0); -- cast39:output -> Multiplexer2:in1
signal pixel_num_0_output_wire : std_logic_vector(47 downto 0); -- pixel_num_0:output -> cast40:input
signal cast40_output_wire : std_logic_vector(23 downto 0); -- cast40:output -> Pipelined_Adder2:dataa
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Bus_Concatenation1:aclr, Bus_Concatenation:aclr, Case_Statement1:aclr, Case_Statement2:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Delay5:aclr, Delay:aclr, Multiplexer1:aclr, Multiplexer2:aclr, Multiplexer:aclr, Pipelined_Adder2:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Bus_Concatenation1:clock, Bus_Concatenation:clock, Case_Statement1:clock, Case_Statement2:clock, Delay1:clock, Delay2:clock, Delay3:clock, Delay5:clock, Delay:clock, Multiplexer1:clock, Multiplexer2:clock, Multiplexer:clock, Pipelined_Adder2:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion1 : component alt_dspbuilder_cast_GN33BXJAZX
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
pipelined_adder2 : component alt_dspbuilder_pipelined_adder_GNTWZRTG4I
generic map (
width => 24,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast40_output_wire, -- dataa.wire
datab => constant18_output_wire, -- datab.wire
result => pipelined_adder2_result_wire, -- result.wire
user_aclr => pipelined_adder2user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder2enavcc_output_wire -- ena.wire
);
pipelined_adder2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder2user_aclrgnd_output_wire -- output.wire
);
pipelined_adder2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder2enavcc_output_wire -- output.wire
);
case_statement1 : component alt_dspbuilder_case_statement_GNWMX2GCN2
generic map (
number_outputs => 2,
hasDefault => 1,
pipeline => 0,
width => 16
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
input => cast29_output_wire, -- input.wire
r0 => case_statement1_r0_wire, -- r0.wire
r1 => case_statement1_r1_wire -- r1.wire
);
case_statement2 : component alt_dspbuilder_case_statement_GNFTM45DFU
generic map (
number_outputs => 2,
hasDefault => 0,
pipeline => 0,
width => 16
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
input => cast32_output_wire, -- input.wire
r0 => case_statement2_r0_wire, -- r0.wire
r1 => case_statement2_r1_wire -- r1.wire
);
multiplexer : component alt_dspbuilder_multiplexer_GNLGLCKYZ5
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_conversion1_output_wire, -- sel.wire
result => multiplexer_result_wire, -- result.wire
ena => multiplexerenavcc_output_wire, -- ena.wire
user_aclr => multiplexeruser_aclrgnd_output_wire, -- user_aclr.wire
in0 => delay_output_wire, -- in0.wire
in1 => delay1_output_wire, -- in1.wire
in2 => delay2_output_wire, -- in2.wire
in3 => delay3_output_wire -- in3.wire
);
multiplexeruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexeruser_aclrgnd_output_wire -- output.wire
);
multiplexerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexerenavcc_output_wire -- output.wire
);
data_0 : component alt_dspbuilder_port_GNEHYJMBQS
port map (
input => multiplexer1_result_wire, -- input.wire
output => data -- output.wire
);
constant7 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant7_output_wire -- output.wire
);
constant5 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant5_output_wire -- output.wire
);
bus_concatenation1 : component alt_dspbuilder_bus_concat_GN6E6AAQPZ
generic map (
widthB => 1,
widthA => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast30_output_wire, -- a.wire
b => cast31_output_wire, -- b.wire
output => bus_concatenation1_output_wire -- output.wire
);
logical_bit_operator6 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator6_result_wire, -- result.wire
data0 => logical_bit_operator9_result_wire, -- data0.wire
data1 => logical_bit_operator10_result_wire -- data1.wire
);
logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator5_result_wire, -- result.wire
data0 => logical_bit_operator4_result_wire, -- data0.wire
data1 => logical_bit_operator3_result_wire -- data1.wire
);
ctrl_pak2_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak2, -- input.wire
output => ctrl_pak2_0_output_wire -- output.wire
);
logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator4_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => case_statement2_r0_wire -- data1.wire
);
ctrl_pak3_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak3, -- input.wire
output => ctrl_pak3_0_output_wire -- output.wire
);
bus_concatenation : component alt_dspbuilder_bus_concat_GN6E6AAQPZ
generic map (
widthB => 1,
widthA => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast33_output_wire, -- a.wire
b => cast34_output_wire, -- b.wire
output => bus_concatenation_output_wire -- output.wire
);
ctrl_pak1_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak1, -- input.wire
output => ctrl_pak1_0_output_wire -- output.wire
);
logical_bit_operator9 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator9_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => if_statement7_true_wire -- data1.wire
);
constant1 : component alt_dspbuilder_constant_GNZEH3JAKA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000001111",
width => 24
)
port map (
output => constant1_output_wire -- output.wire
);
delay : component alt_dspbuilder_delay_GNIYBMGPQQ
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000001111",
width => 24
)
port map (
input => constant1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay_output_wire, -- output.wire
sclr => delaysclrgnd_output_wire, -- sclr.wire
ena => delayenavcc_output_wire -- ena.wire
);
delaysclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delaysclrgnd_output_wire -- output.wire
);
delayenavcc : component alt_dspbuilder_vcc_GN
port map (
output => delayenavcc_output_wire -- output.wire
);
constant16 : component alt_dspbuilder_constant_GNLJWFEWBD
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000000000011",
width => 16
)
port map (
output => constant16_output_wire -- output.wire
);
constant18 : component alt_dspbuilder_constant_GNQJ63TWA6
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000100",
width => 24
)
port map (
output => constant18_output_wire -- output.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => case_statement2_r1_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => logical_bit_operator6_result_wire, -- input.wire
output => eop -- output.wire
);
colorbar_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => colorbar, -- input.wire
output => colorbar_0_output_wire -- output.wire
);
if_statement7 : component alt_dspbuilder_if_statement_GNTVBNRAAT
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b) or (a=c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement7_true_wire, -- true.wire
a => counter_0_output_wire, -- a.wire
b => cast35_output_wire, -- b.wire
c => pipelined_adder2_result_wire -- c.wire
);
counter_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter, -- input.wire
output => counter_0_output_wire -- output.wire
);
delay5 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => constant7_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay5_output_wire, -- output.wire
sclr => delay5sclrgnd_output_wire, -- sclr.wire
ena => delay5enavcc_output_wire -- ena.wire
);
delay5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay5sclrgnd_output_wire -- output.wire
);
delay5enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay5enavcc_output_wire -- output.wire
);
pixel_num_0 : component alt_dspbuilder_port_GNUJT4YY5I
port map (
input => pixel_num, -- input.wire
output => pixel_num_0_output_wire -- output.wire
);
delay3 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => ctrl_pak3_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay3_output_wire, -- output.wire
sclr => delay3sclrgnd_output_wire, -- sclr.wire
ena => delay3enavcc_output_wire -- ena.wire
);
delay3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay3sclrgnd_output_wire -- output.wire
);
delay3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay3enavcc_output_wire -- output.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => logical_bit_operator5_result_wire, -- input.wire
output => sop -- output.wire
);
logical_bit_operator10 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator10_result_wire, -- result.wire
data0 => if_statement7_true_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ctrl_en, -- input.wire
output => ctrl_en_0_output_wire -- output.wire
);
multiplexer1 : component alt_dspbuilder_multiplexer_GNHQFFAUXQ
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 25,
pipeline => 0,
number_inputs => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_concatenation_output_wire, -- sel.wire
result => multiplexer1_result_wire, -- result.wire
ena => multiplexer1enavcc_output_wire, -- ena.wire
user_aclr => multiplexer1user_aclrgnd_output_wire, -- user_aclr.wire
in0 => cast36_output_wire, -- in0.wire
in1 => multiplexer2_result_wire, -- in1.wire
in2 => cast37_output_wire -- in2.wire
);
multiplexer1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer1user_aclrgnd_output_wire -- output.wire
);
multiplexer1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer1enavcc_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => ctrl_pak1_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => delay1sclrgnd_output_wire, -- sclr.wire
ena => delay1enavcc_output_wire -- ena.wire
);
delay1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay1sclrgnd_output_wire -- output.wire
);
delay1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay1enavcc_output_wire -- output.wire
);
multiplexer2 : component alt_dspbuilder_multiplexer_GN6ODCX3D4
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 1,
width => 25,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_concatenation1_output_wire, -- sel.wire
result => multiplexer2_result_wire, -- result.wire
ena => multiplexer2enavcc_output_wire, -- ena.wire
user_aclr => multiplexer2user_aclrgnd_output_wire, -- user_aclr.wire
in0 => cast38_output_wire, -- in0.wire
in1 => cast39_output_wire -- in1.wire
);
multiplexer2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer2user_aclrgnd_output_wire -- output.wire
);
multiplexer2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer2enavcc_output_wire -- output.wire
);
delay2 : component alt_dspbuilder_delay_GNVJUPFOX3
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000000",
width => 24
)
port map (
input => ctrl_pak2_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay2_output_wire, -- output.wire
sclr => delay2sclrgnd_output_wire, -- sclr.wire
ena => delay2enavcc_output_wire -- ena.wire
);
delay2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay2sclrgnd_output_wire -- output.wire
);
delay2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay2enavcc_output_wire -- output.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => data_en, -- input.wire
output => data_en_0_output_wire -- output.wire
);
cast29 : component alt_dspbuilder_cast_GN3ODVPHOL
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => cast29_output_wire -- output.wire
);
cast30 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => case_statement1_r0_wire, -- input.wire
output => cast30_output_wire -- output.wire
);
cast31 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => case_statement1_r1_wire, -- input.wire
output => cast31_output_wire -- output.wire
);
cast32 : component alt_dspbuilder_cast_GN3ODVPHOL
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => cast32_output_wire -- output.wire
);
cast33 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => ctrl_en_0_output_wire, -- input.wire
output => cast33_output_wire -- output.wire
);
cast34 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => data_en_0_output_wire, -- input.wire
output => cast34_output_wire -- output.wire
);
cast35 : component alt_dspbuilder_cast_GNCPEUNC4M
generic map (
round => 0,
saturate => 0
)
port map (
input => constant16_output_wire, -- input.wire
output => cast35_output_wire -- output.wire
);
cast36 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => constant5_output_wire, -- input.wire
output => cast36_output_wire -- output.wire
);
cast37 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplexer_result_wire, -- input.wire
output => cast37_output_wire -- output.wire
);
cast38 : component alt_dspbuilder_cast_GNCCZ56SYK
generic map (
round => 0,
saturate => 0
)
port map (
input => colorbar_0_output_wire, -- input.wire
output => cast38_output_wire -- output.wire
);
cast39 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => delay5_output_wire, -- input.wire
output => cast39_output_wire -- output.wire
);
cast40 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => pixel_num_0_output_wire, -- input.wire
output => cast40_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT
| mit | 104623ef1a9da5cd312b227842b5d908 | 0.565592 | 3.377325 | false | false | false | false |
freecores/t48 | rtl/vhdl/db_bus.vhd | 1 | 5,192 | -------------------------------------------------------------------------------
--
-- The BUS unit.
-- Implements the BUS port logic.
--
-- $Id: db_bus.vhd,v 1.5 2005-06-11 10:08:43 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
entity t48_db_bus is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
ea_i : in std_logic;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
write_bus_i : in boolean;
read_bus_i : in boolean;
-- BUS Interface ----------------------------------------------------------
output_pcl_i : in boolean;
bidir_bus_i : in boolean;
pcl_i : in word_t;
db_i : in word_t;
db_o : out word_t;
db_dir_o : out std_logic
);
end t48_db_bus;
use work.t48_pack.clk_active_c;
use work.t48_pack.res_active_c;
use work.t48_pack.bus_idle_level_c;
use work.t48_pack.to_stdLogic;
architecture rtl of t48_db_bus is
-- the BUS output register
signal bus_q : word_t;
-- BUS direction marker
signal db_dir_q,
db_dir_qq : std_logic;
begin
-----------------------------------------------------------------------------
-- Process bus_regs
--
-- Purpose:
-- Implements the BUS output register.
--
bus_regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
bus_q <= (others => '0');
db_dir_q <= '0';
db_dir_qq <= '0';
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
if write_bus_i then
db_dir_qq <= '1';
else
-- extend bus direction by one machine cycle
db_dir_qq <= db_dir_q;
end if;
if write_bus_i then
bus_q <= data_i;
db_dir_q <= '1';
elsif ea_i = '1' or bidir_bus_i then
db_dir_q <= '0';
end if;
end if;
end if;
end process bus_regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
db_o <= pcl_i
when output_pcl_i else
bus_q;
db_dir_o <= db_dir_qq or
to_stdLogic(output_pcl_i);
data_o <= (others => bus_idle_level_c)
when not read_bus_i else
db_i;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2005/06/09 22:16:26 arniml
-- Implement db_dir_o glitch-safe
--
-- Revision 1.3 2004/10/25 20:30:18 arniml
-- delay db_dir_o by one machine cycle
-- this fixes the timing relation between BUS data and WR'
--
-- Revision 1.2 2004/04/04 14:15:45 arniml
-- add dump_compare support
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 4a9cc06561a1fadd99787f055f4b42c2 | 0.537173 | 4.009266 | false | false | false | false |
freecores/t48 | rtl/vhdl/system/lpm_rom.vhd | 2 | 13,920 | --------------------------------------------------------------------------
-- This VHDL file was developed by Altera Corporation. It may be
-- freely copied and/or distributed at no cost. Any persons using this
-- file for any purpose do so at their own risk, and are responsible for
-- the results of such use. Altera Corporation does not guarantee that
-- this file is complete, correct, or fit for any particular purpose.
-- NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must
-- accompany any copy of this file.
--
--------------------------------------------------------------------------
-- LPM Synthesizable Models (Support string type generic)
--------------------------------------------------------------------------
-- Version 2.0 (lpm 220) Date 01/04/00
--
-- 1. Fixed LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO and LPM_ROM to correctly
-- read in values from LPM_FILE (*.hex) when the DATA width is greater
-- than 16 bits.
-- 2. Explicit sign conversions are added to standard logic vector
-- comparisons in LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO, LPM_ROM, and
-- LPM_COMPARE.
-- 3. LPM_FIFO_DC is rewritten to have correct outputs.
-- 4. LPM_FIFO outputs zeros when nothing has been read from it, and
-- outputs LPM_NUMWORDS mod exp(2, LPM_WIDTHU) when it is full.
-- 5. Fixed LPM_DIVIDE to divide correctly.
--------------------------------------------------------------------------
-- Version 1.9 (lpm 220) Date 11/30/99
--
-- 1. Fixed UNUSED file not found problem and initialization problem
-- with LPM_RAM_DP, LPM_RAM_DQ, and LPM_RAM_IO.
-- 2. Fixed LPM_MULT when SUM port is not used.
-- 3. Fixed LPM_FIFO_DC to enable read when rdclock and wrclock rise
-- at the same time.
-- 4. Fixed LPM_COUNTER comparison problem when signed library is loaded
-- and counter is incrementing.
-- 5. Got rid of "Illegal Character" error message at time = 0 ns when
-- simulating LPM_COUNTER.
--------------------------------------------------------------------------
-- Version 1.8 (lpm 220) Date 10/25/99
--
-- 1. Some LPM_PVALUE implementations were missing, and now implemented.
-- 2. Fixed LPM_COUNTER to count correctly without conversion overflow,
-- that is, when LPM_MODULUS = 2 ** LPM_WIDTH.
-- 3. Fixed LPM_RAM_DP sync process sensitivity list to detect wraddress
-- changes.
--------------------------------------------------------------------------
-- Version 1.7 (lpm 220) Date 07/13/99
--
-- Changed LPM_RAM_IO so that it can be used to simulate both MP2 and
-- Quartus behaviour and LPM220-compliant behaviour.
--------------------------------------------------------------------------
-- Version 1.6 (lpm 220) Date 06/15/99
--
-- 1. Fixed LPM_ADD_SUB sign extension problem and subtraction bug.
-- 2. Fixed LPM_COUNTER to use LPM_MODULUS value.
-- 3. Added CIN and COUT port, and discarded EQ port in LPM_COUNTER to
-- comply with the specfication.
-- 4. Included LPM_RAM_DP, LPM_RAM_DQ, LPM_RAM_IO, LPM_ROM, LPM_FIFO, and
-- LPM_FIFO_DC; they are all initialized to 0's.
--------------------------------------------------------------------------
-- Version 1.5 (lpm 220) Date 05/10/99
--
-- Changed LPM_MODULUS from string type to integer.
--------------------------------------------------------------------------
-- Version 1.4 (lpm 220) Date 02/05/99
--
-- 1. Added LPM_DIVIDE module.
-- 2. Added CLKEN port to LPM_MUX, LPM_DECODE, LPM_ADD_SUB, LPM_MULT
-- and LPM_COMPARE
-- 3. Replaced the constants holding string with the actual string.
--------------------------------------------------------------------------
-- Version 1.3 Date 07/30/96
--
-- Modification History
--
-- 1. Changed the DEFAULT value to "UNUSED" for LPM_SVALUE, LPM_AVALUE,
-- LPM_MODULUS, and LPM_NUMWORDS, LPM_HINT,LPM_STRENGTH, LPM_DIRECTION,
-- and LPM_PVALUE
--
-- 2. Added the two dimentional port components (AND, OR, XOR, and MUX).
--------------------------------------------------------------------------
-- Excluded Functions:
--
-- LPM_FSM and LPM_TTABLE
--
--------------------------------------------------------------------------
-- Assumptions:
--
-- 1. All ports and signal types are std_logic or std_logic_vector
-- from IEEE 1164 package.
-- 2. Synopsys std_logic_arith, std_logic_unsigned, and std_logic_signed
-- package are assumed to be accessible from IEEE library.
-- 3. lpm_component_package must be accessible from library work.
-- 4. The default value of LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, LPM_HINT,
-- LPM_NUMWORDS, LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE is
-- string "UNUSED".
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--use work.LPM_COMPONENTS.all;
use std.textio.all;
entity LPM_ROM is
generic (LPM_WIDTH : positive;
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string;
LPM_TYPE : string := "LPM_ROM";
LPM_HINT : string := "UNUSED");
port (ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
INCLOCK : in STD_LOGIC := '0';
OUTCLOCK : in STD_LOGIC := '0';
MEMENAB : in STD_LOGIC := '1';
Q : out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0));
function int_to_str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
while (ivalue > 0 ) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function hex_str_to_int( str : string ) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer;
begin
for i in len downto 1 loop
case str(i) is
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when 'A' =>
digit := 10;
when 'a' =>
digit := 10;
when 'B' =>
digit := 11;
when 'b' =>
digit := 11;
when 'C' =>
digit := 12;
when 'c' =>
digit := 12;
when 'D' =>
digit := 13;
when 'd' =>
digit := 13;
when 'E' =>
digit := 14;
when 'e' =>
digit := 14;
when 'F' =>
digit := 15;
when 'f' =>
digit := 15;
when others =>
ASSERT FALSE
REPORT "Illegal character "& str(i) & "in Intel Hex File! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 16 + digit;
end loop;
return ivalue;
end;
procedure Shrink_line(L : inout LINE; pos : in integer) is
subtype nstring is string(1 to pos);
variable stmp : nstring;
begin
if pos >= 1 then
read(l, stmp);
end if;
end;
end LPM_ROM;
architecture LPM_SYN of lpm_rom is
--type lpm_memory is array(lpm_numwords-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
type lpm_memory is array(integer range (2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
signal q2, q_tmp, q_reg : std_logic_vector(lpm_width-1 downto 0);
signal address_tmp, address_reg : std_logic_vector(lpm_widthad-1 downto 0);
begin
enable_mem: process(memenab, q2)
begin
if (memenab = '1') then
q <= q2;
else
q <= (OTHERS => 'Z');
end if;
end process;
sync: process(address, address_reg, q_tmp, q_reg)
begin
if (lpm_address_control = "REGISTERED") then
address_tmp <= address_reg;
else
address_tmp <= address;
end if;
if (lpm_outdata = "REGISTERED") then
q2 <= q_reg;
else
q2 <= q_tmp;
end if;
end process;
input_reg: process (inclock)
begin
if inclock'event and inclock = '1' then
address_reg <= address;
end if;
end process;
output_reg: process (outclock)
begin
if outclock'event and outclock = '1' then
q_reg <= q_tmp;
end if;
end process;
memory: process(memenab, address_tmp)
variable mem_data : lpm_memory;
variable mem_data_tmp : integer := 0;
variable mem_init: boolean := false;
variable i, j, k, lineno : integer := 0;
variable buf: line ;
variable booval: boolean ;
FILE mem_data_file: TEXT IS IN LPM_FILE;
variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1);
variable startadd: string(4 downto 1);
variable ibase: integer := 0;
variable ibyte: integer := 0;
variable istartadd: integer := 0;
variable check_sum_vec, check_sum_vec_tmp: unsigned(7 downto 0);
begin
-- INITIALIZE --
if NOT(mem_init) then
-- INITIALIZE TO 0 --
for i in mem_data'LOW to mem_data'HIGH loop
mem_data(i) := (OTHERS => '0');
end loop;
if (LPM_FILE = "UNUSED") then
ASSERT FALSE
REPORT "Initialization file not found!"
SEVERITY ERROR;
else
WHILE NOT ENDFILE(mem_data_file) loop
booval := true;
READLINE(mem_data_file, buf);
lineno := lineno + 1;
check_sum_vec := (OTHERS => '0');
if (buf(buf'LOW) = ':') then
i := 1;
shrink_line(buf, i);
READ(L=>buf, VALUE=>byte, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format!"
SEVERITY ERROR;
end if;
ibyte := hex_str_to_int(byte);
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(ibyte, 8);
READ(L=>buf, VALUE=>startadd, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
istartadd := hex_str_to_int(startadd);
addr(2) := startadd(4);
addr(1) := startadd(3);
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length);
addr(2) := startadd(2);
addr(1) := startadd(1);
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length);
READ(L=>buf, VALUE=>rec_type, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(rec_type), check_sum_vec'length);
else
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
case rec_type is
when "00"=> -- Data record
i := 0;
k := lpm_width / 8;
if ((lpm_width MOD 8) /= 0) then
k := k + 1;
end if;
-- k = no. of bytes per CAM entry.
while (i < ibyte) loop
mem_data_tmp := 0;
for j in 1 to k loop
READ(L=>buf, VALUE=>datain,good=>booval); -- read in data a byte (2 hex chars) at a time.
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(datain), check_sum_vec'length);
mem_data_tmp := mem_data_tmp * 256 + hex_str_to_int(datain);
end loop;
i := i + k;
mem_data(ibase + istartadd) := STD_LOGIC_VECTOR(to_unsigned(mem_data_tmp, lpm_width));
istartadd := istartadd + 1;
end loop;
when "01"=>
exit;
when "02"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format for record type 02! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := ibase * 256 + hex_str_to_int(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(base), check_sum_vec'length);
end loop;
ibase := ibase * 16;
when OTHERS =>
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal record type in Intel Hex File! "
SEVERITY ERROR;
end case;
READ(L=>buf, VALUE=>checksum,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Checksum is missing! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
check_sum_vec_tmp := to_unsigned(hex_str_to_int(checksum),8);
if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Incorrect checksum!"
SEVERITY ERROR;
end if;
end loop;
end if;
mem_init := TRUE;
end if;
-- MEMORY FUNCTION --
--if memenab = '1' then
q_tmp <= mem_data(to_integer(UNSIGNED(address_tmp)));
--else
-- q_tmp <= (OTHERS => 'Z');
--end if;
end process;
end LPM_SYN;
---------------------------------------------------------------------------
-- pragma translate_off
configuration lpm_rom_c0 of lpm_rom is
for lpm_syn
end for;
end lpm_rom_c0;
-- pragma translate_on
| gpl-2.0 | 9bd2dcb50ed28a959144cd252b7b8f8f | 0.563506 | 3.337329 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | Test_Pattern_Generator_dspbuilder/hdl/Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE.vhd | 2 | 34,606 | -- Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:05:29
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE is
port (
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
counter : in std_logic_vector(23 downto 0) := (others => '0'); -- counter.wire
col : in std_logic_vector(31 downto 0) := (others => '0'); -- col.wire
colorbar : out std_logic_vector(23 downto 0); -- colorbar.wire
data_en : in std_logic := '0'; -- data_en.wire
ctrl_en : in std_logic := '0' -- ctrl_en.wire
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNWEIMU3MK;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_bus_build_GNI6E4JZ66 is
generic (
width : natural := 8
);
port (
output : out std_logic_vector(2 downto 0); -- wire
in0 : in std_logic := 'X'; -- wire
in1 : in std_logic := 'X'; -- wire
in2 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_bus_build_GNI6E4JZ66;
component alt_dspbuilder_divider_GNKAPZN5MO is
generic (
Signed : natural := 0;
width : natural := 8;
pipeline : natural := 0
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
denom : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
numer : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
quotient : out std_logic_vector(width-1 downto 0); -- wire
remain : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_divider_GNKAPZN5MO;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNJ7D74ANQ;
component alt_dspbuilder_constant_GNKT7L5CDY is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNKT7L5CDY;
component alt_dspbuilder_if_statement_GNIV4UP6ZO is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNIV4UP6ZO;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_if_statement_GNMQPB5LUF is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNMQPB5LUF;
component alt_dspbuilder_if_statement_GNZR777PB6 is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNZR777PB6;
component alt_dspbuilder_constant_GNUWBUDS4L is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNUWBUDS4L;
component alt_dspbuilder_constant_GNJ2DIDH6N is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNJ2DIDH6N;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_constant_GNNCFWNIJI is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNCFWNIJI;
component alt_dspbuilder_if_statement_GNWHMBR6GA is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNWHMBR6GA;
component alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic (
delay : positive := 1;
signal_type : string := "Impulse";
impulse_width : positive := 1
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
result : out std_logic; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_single_pulse_GN2XGKTRR3;
component StateMachineEditor1 is
port (
clock : in std_logic := 'X'; -- clk
col_select : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
data : out std_logic_vector(23 downto 0); -- wire
data_en : in std_logic := 'X'; -- wire
reset : in std_logic := 'X' -- wire
);
end component StateMachineEditor1;
component alt_dspbuilder_counter_GNZKRIGTBB is
generic (
use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "0";
use_sload : string := "false";
use_sclr : string := "false";
use_cout : string := "false";
modulus : integer := 256;
use_cnt_ena : string := "false";
width : natural := 8;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0"
);
port (
aclr : in std_logic := 'X'; -- clk
aload : in std_logic := 'X'; -- wire
aset : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cnt_ena : in std_logic := 'X'; -- wire
cout : out std_logic; -- wire
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
direction : in std_logic := 'X'; -- wire
ena : in std_logic := 'X'; -- wire
q : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X'; -- wire
sload : in std_logic := 'X'; -- wire
sset : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_counter_GNZKRIGTBB;
component alt_dspbuilder_multiplier_GNEIWYOKUR is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "AUTO";
Signed : natural := 0;
OutputMsb : integer := 8;
aWidth : natural := 8;
bWidth : natural := 8;
OutputLsb : integer := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
dataa : in std_logic_vector(aWidth-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(bWidth-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(OutputMsb-OutputLsb+1-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_multiplier_GNEIWYOKUR;
component alt_dspbuilder_cast_GN7PRGDOVA is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN7PRGDOVA;
component alt_dspbuilder_cast_GNCPEUNC4M is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCPEUNC4M;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
component alt_dspbuilder_cast_GNLHWQIRQK is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNLHWQIRQK;
signal pipelined_adder3user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder3user_aclrGND:output -> Pipelined_Adder3:user_aclr
signal pipelined_adder3enavcc_output_wire : std_logic; -- Pipelined_Adder3enaVCC:output -> Pipelined_Adder3:ena
signal divideruser_aclrgnd_output_wire : std_logic; -- Divideruser_aclrGND:output -> Divider:user_aclr
signal dividerenavcc_output_wire : std_logic; -- DividerenaVCC:output -> Divider:ena
signal single_pulse1sclrgnd_output_wire : std_logic; -- Single_Pulse1sclrGND:output -> Single_Pulse1:sclr
signal single_pulse1enavcc_output_wire : std_logic; -- Single_Pulse1enaVCC:output -> Single_Pulse1:ena
signal multiplieruser_aclrgnd_output_wire : std_logic; -- Multiplieruser_aclrGND:output -> Multiplier:user_aclr
signal multiplierenavcc_output_wire : std_logic; -- MultiplierenaVCC:output -> Multiplier:ena
signal constant9_output_wire : std_logic_vector(23 downto 0); -- Constant9:output -> Counter1:data
signal constant8_output_wire : std_logic_vector(23 downto 0); -- Constant8:output -> Divider:denom
signal counter1_q_wire : std_logic_vector(23 downto 0); -- Counter1:q -> [If_Statement1:a, If_Statement2:a, If_Statement3:a, If_Statement:a]
signal divider_quotient_wire : std_logic_vector(23 downto 0); -- Divider:quotient -> [If_Statement1:b, If_Statement:b, Multiplier:dataa]
signal if_statement_true_wire : std_logic; -- If_Statement:true -> Bus_Builder:in0
signal if_statement1_true_wire : std_logic; -- If_Statement1:true -> Bus_Builder:in1
signal if_statement2_true_wire : std_logic; -- If_Statement2:true -> Bus_Builder:in2
signal counter_0_output_wire : std_logic_vector(23 downto 0); -- counter_0:output -> If_Statement5:a
signal if_statement3_true_wire : std_logic; -- If_Statement3:true -> Logical_Bit_Operator12:data0
signal data_en_0_output_wire : std_logic; -- data_en_0:output -> [Logical_Bit_Operator12:data1, Logical_Bit_Operator8:data0, State_Machine_Editor1:data_en]
signal ctrl_en_0_output_wire : std_logic; -- ctrl_en_0:output -> Logical_Bit_Operator7:data0
signal logical_bit_operator12_result_wire : std_logic; -- Logical_Bit_Operator12:result -> Logical_Bit_Operator7:data1
signal logical_bit_operator7_result_wire : std_logic; -- Logical_Bit_Operator7:result -> Counter1:sload
signal if_statement5_true_wire : std_logic; -- If_Statement5:true -> Logical_Bit_Operator8:data1
signal logical_bit_operator8_result_wire : std_logic; -- Logical_Bit_Operator8:result -> Counter1:cnt_ena
signal constant6_output_wire : std_logic_vector(23 downto 0); -- Constant6:output -> Multiplier:datab
signal constant13_output_wire : std_logic_vector(23 downto 0); -- Constant13:output -> Pipelined_Adder3:datab
signal pipelined_adder3_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder3:result -> If_Statement2:c
signal single_pulse1_result_wire : std_logic; -- Single_Pulse1:result -> State_Machine_Editor1:reset
signal state_machine_editor1_data_wire : std_logic_vector(23 downto 0); -- State_Machine_Editor1:data -> colorbar_0:input
signal col_0_output_wire : std_logic_vector(31 downto 0); -- col_0:output -> [cast0:input, cast1:input, cast2:input, cast6:input]
signal cast0_output_wire : std_logic_vector(23 downto 0); -- cast0:output -> Divider:numer
signal cast1_output_wire : std_logic_vector(23 downto 0); -- cast1:output -> If_Statement:c
signal cast2_output_wire : std_logic_vector(23 downto 0); -- cast2:output -> If_Statement3:b
signal constant11_output_wire : std_logic_vector(15 downto 0); -- Constant11:output -> cast3:input
signal cast3_output_wire : std_logic_vector(23 downto 0); -- cast3:output -> If_Statement5:b
signal multiplier_result_wire : std_logic_vector(47 downto 0); -- Multiplier:result -> [cast4:input, cast5:input]
signal cast4_output_wire : std_logic_vector(23 downto 0); -- cast4:output -> If_Statement1:c
signal cast5_output_wire : std_logic_vector(23 downto 0); -- cast5:output -> If_Statement2:b
signal cast6_output_wire : std_logic_vector(23 downto 0); -- cast6:output -> Pipelined_Adder3:dataa
signal bus_builder_output_wire : std_logic_vector(2 downto 0); -- Bus_Builder:output -> cast7:input
signal cast7_output_wire : std_logic_vector(2 downto 0); -- cast7:output -> State_Machine_Editor1:col_select
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Counter1:aclr, Divider:aclr, Multiplier:aclr, Pipelined_Adder3:aclr, Single_Pulse1:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Counter1:clock, Divider:clock, Multiplier:clock, Pipelined_Adder3:clock, Single_Pulse1:clock, State_Machine_Editor1:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
pipelined_adder3 : component alt_dspbuilder_pipelined_adder_GNWEIMU3MK
generic map (
width => 24,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast6_output_wire, -- dataa.wire
datab => constant13_output_wire, -- datab.wire
result => pipelined_adder3_result_wire, -- result.wire
user_aclr => pipelined_adder3user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder3enavcc_output_wire -- ena.wire
);
pipelined_adder3user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder3user_aclrgnd_output_wire -- output.wire
);
pipelined_adder3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder3enavcc_output_wire -- output.wire
);
col_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => col, -- input.wire
output => col_0_output_wire -- output.wire
);
bus_builder : component alt_dspbuilder_bus_build_GNI6E4JZ66
generic map (
width => 3
)
port map (
output => bus_builder_output_wire, -- output.wire
in0 => if_statement_true_wire, -- in0.wire
in1 => if_statement1_true_wire, -- in1.wire
in2 => if_statement2_true_wire -- in2.wire
);
divider : component alt_dspbuilder_divider_GNKAPZN5MO
generic map (
Signed => 0,
width => 24,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
numer => cast0_output_wire, -- numer.wire
denom => constant8_output_wire, -- denom.wire
quotient => divider_quotient_wire, -- quotient.wire
remain => open, -- remain.wire
user_aclr => divideruser_aclrgnd_output_wire, -- user_aclr.wire
ena => dividerenavcc_output_wire -- ena.wire
);
divideruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => divideruser_aclrgnd_output_wire -- output.wire
);
dividerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => dividerenavcc_output_wire -- output.wire
);
colorbar_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => state_machine_editor1_data_wire, -- input.wire
output => colorbar -- output.wire
);
if_statement5 : component alt_dspbuilder_if_statement_GNJ7D74ANQ
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a>b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement5_true_wire, -- true.wire
a => counter_0_output_wire, -- a.wire
b => cast3_output_wire -- b.wire
);
counter_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter, -- input.wire
output => counter_0_output_wire -- output.wire
);
constant6 : component alt_dspbuilder_constant_GNKT7L5CDY
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000010",
width => 24
)
port map (
output => constant6_output_wire -- output.wire
);
if_statement3 : component alt_dspbuilder_if_statement_GNIV4UP6ZO
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a=b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement3_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => cast2_output_wire -- b.wire
);
logical_bit_operator12 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator12_result_wire, -- result.wire
data0 => if_statement3_true_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
if_statement2 : component alt_dspbuilder_if_statement_GNMQPB5LUF
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>b) or (a=b)) and ((a<c) or (a=c))",
number_inputs => 3,
width => 24
)
port map (
true => if_statement2_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => cast5_output_wire, -- b.wire
c => pipelined_adder3_result_wire -- c.wire
);
if_statement1 : component alt_dspbuilder_if_statement_GNZR777PB6
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>b) or (a=b)) and (a<c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement1_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => divider_quotient_wire, -- b.wire
c => cast4_output_wire -- c.wire
);
constant8 : component alt_dspbuilder_constant_GNUWBUDS4L
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000011",
width => 24
)
port map (
output => constant8_output_wire -- output.wire
);
constant9 : component alt_dspbuilder_constant_GNJ2DIDH6N
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000001",
width => 24
)
port map (
output => constant9_output_wire -- output.wire
);
logical_bit_operator7 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator7_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => logical_bit_operator12_result_wire -- data1.wire
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ctrl_en, -- input.wire
output => ctrl_en_0_output_wire -- output.wire
);
constant11 : component alt_dspbuilder_constant_GNNCFWNIJI
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000000000100",
width => 16
)
port map (
output => constant11_output_wire -- output.wire
);
if_statement : component alt_dspbuilder_if_statement_GNWHMBR6GA
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>zero) and (a<b)) or (a=c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => divider_quotient_wire, -- b.wire
c => cast1_output_wire -- c.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => data_en, -- input.wire
output => data_en_0_output_wire -- output.wire
);
constant13 : component alt_dspbuilder_constant_GNJ2DIDH6N
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000001",
width => 24
)
port map (
output => constant13_output_wire -- output.wire
);
logical_bit_operator8 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator8_result_wire, -- result.wire
data0 => data_en_0_output_wire, -- data0.wire
data1 => if_statement5_true_wire -- data1.wire
);
single_pulse1 : component alt_dspbuilder_single_pulse_GN2XGKTRR3
generic map (
delay => 1,
signal_type => "Step Down",
impulse_width => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
result => single_pulse1_result_wire, -- result.wire
sclr => single_pulse1sclrgnd_output_wire, -- sclr.wire
ena => single_pulse1enavcc_output_wire -- ena.wire
);
single_pulse1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => single_pulse1sclrgnd_output_wire -- output.wire
);
single_pulse1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => single_pulse1enavcc_output_wire -- output.wire
);
state_machine_editor1 : component StateMachineEditor1
port map (
clock => clock_0_clock_output_clk, -- clock.clk
reset => single_pulse1_result_wire, -- reset.wire
col_select => cast7_output_wire, -- col_select.wire
data_en => data_en_0_output_wire, -- data_en.wire
data => state_machine_editor1_data_wire -- data.wire
);
counter1 : component alt_dspbuilder_counter_GNZKRIGTBB
generic map (
use_usr_aclr => "false",
use_ena => "false",
use_cin => "false",
use_sset => "false",
ndirection => 1,
svalue => "1",
use_sload => "true",
use_sclr => "false",
use_cout => "false",
modulus => 65536,
use_cnt_ena => "true",
width => 24,
use_aset => "false",
use_aload => "false",
avalue => "0"
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => constant9_output_wire, -- data.wire
cnt_ena => logical_bit_operator8_result_wire, -- cnt_ena.wire
sload => logical_bit_operator7_result_wire, -- sload.wire
q => counter1_q_wire, -- q.wire
cout => open -- cout.wire
);
multiplier : component alt_dspbuilder_multiplier_GNEIWYOKUR
generic map (
DEDICATED_MULTIPLIER_CIRCUITRY => "YES",
Signed => 0,
OutputMsb => 47,
aWidth => 24,
bWidth => 24,
OutputLsb => 0,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => divider_quotient_wire, -- dataa.wire
datab => constant6_output_wire, -- datab.wire
result => multiplier_result_wire, -- result.wire
user_aclr => multiplieruser_aclrgnd_output_wire, -- user_aclr.wire
ena => multiplierenavcc_output_wire -- ena.wire
);
multiplieruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplieruser_aclrgnd_output_wire -- output.wire
);
multiplierenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplierenavcc_output_wire -- output.wire
);
cast0 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast0_output_wire -- output.wire
);
cast1 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast1_output_wire -- output.wire
);
cast2 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast2_output_wire -- output.wire
);
cast3 : component alt_dspbuilder_cast_GNCPEUNC4M
generic map (
round => 0,
saturate => 0
)
port map (
input => constant11_output_wire, -- input.wire
output => cast3_output_wire -- output.wire
);
cast4 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplier_result_wire, -- input.wire
output => cast4_output_wire -- output.wire
);
cast5 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplier_result_wire, -- input.wire
output => cast5_output_wire -- output.wire
);
cast6 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast6_output_wire -- output.wire
);
cast7 : component alt_dspbuilder_cast_GNLHWQIRQK
generic map (
round => 0,
saturate => 0
)
port map (
input => bus_builder_output_wire, -- input.wire
output => cast7_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE
| mit | 1d7716aeb3683868acb0fcb53743c95c | 0.54661 | 3.361764 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GNJ7VFHJ4A.vhd | 4 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNJ7VFHJ4A is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNJ7VFHJ4A is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 16 + 1 ,
width_inr=> 0,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(15 downto 0) => input,
xin(16) => '0', yout => output
);
end architecture; | mit | 86b376910ec84f49be6c2c151503c6c7 | 0.648803 | 3.045139 | false | false | false | false |
bobxiv/DispositivosLogicosProgramables-FICH | Proyecto 1 DLP TP Calculadora/Src/ArithmeticModule.vhd | 1 | 1,483 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:00:40 10/08/2011
-- Design Name:
-- Module Name: ArithmeticModule - ArithmeticArchitecture
-- Project Name: DLP Proyecto Codename Calculadora
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity ArithmeticModule is
Port ( A : in STD_LOGIC_VECTOR(7 downto 0);--Primer operando(valor binario)
B : in STD_LOGIC_VECTOR(7 downto 0);--Segundo operando(valor binario)
Op : in STD_LOGIC_VECTOR(1 downto 0);--Operador
Res : out STD_LOGIC_VECTOR(15 downto 0));--Resultado de la operacion(valor binario)
end ArithmeticModule;
architecture ArithmeticArchitecture of ArithmeticModule is
begin
PROCESS(A, B, Op)
BEGIN
CASE Op IS
WHEN "00" => --Suma
Res(7 downto 0) <= A+B;
Res(15 downto 8) <= "00000000";
WHEN "01" => --Resta
Res(7 downto 0) <= A-B;
Res(15 downto 8) <= "00000000";
WHEN "10" =>--Multiplicacion
Res <= A*B;
WHEN "11" =>--Division NO IMPLEMENTADA TODAVIA
Res <= "1111111111111111";
when others =>
Res <= "1111111111111111";
END CASE;
END PROCESS;
end ArithmeticArchitecture;
| gpl-3.0 | 40b15dc1748327780d0c941582bc7b10 | 0.579906 | 3.689055 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | DSPBuilder_Test_Pattern_Generator_import/StateMachineEditor1.vhd | 1 | 3,820 | -- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 13.1.0 Build 162 10/23/2013 SJ Full Version
-- Created on Wed Feb 11 10:18:10 2015
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY StateMachineEditor1 IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
col_select : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
data_en : IN STD_LOGIC := '0';
data : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END StateMachineEditor1;
ARCHITECTURE BEHAVIOR OF StateMachineEditor1 IS
TYPE type_fstate IS (IDLE,BLOCKA,BLOCKB,BLOCKC);
SIGNAL fstate : type_fstate;
SIGNAL reg_fstate : type_fstate;
BEGIN
PROCESS (clock,reg_fstate)
BEGIN
IF (clock='1' AND clock'event) THEN
fstate <= reg_fstate;
END IF;
END PROCESS;
PROCESS (fstate,reset,col_select,data_en)
BEGIN
IF (reset='1') THEN
reg_fstate <= IDLE;
data <= "000000000000000000000000";
ELSE
data <= "000000000000000000000000";
CASE fstate IS
WHEN IDLE =>
IF (((col_select(2 DOWNTO 0) = "001") AND (data_en = '1'))) THEN
reg_fstate <= BLOCKA;
ELSIF ((col_select(2 DOWNTO 0) = "000")) THEN
reg_fstate <= IDLE;
-- Inserting 'else' block to prevent latch inference
ELSE
reg_fstate <= IDLE;
END IF;
data <= "000000000000000000000000";
WHEN BLOCKA =>
IF (((col_select(2 DOWNTO 0) = "010") AND (data_en = '1'))) THEN
reg_fstate <= BLOCKB;
-- Inserting 'else' block to prevent latch inference
ELSE
reg_fstate <= BLOCKA;
END IF;
data <= "000000000000000011111111";
WHEN BLOCKB =>
IF (((col_select(2 DOWNTO 0) = "100") AND (data_en = '1'))) THEN
reg_fstate <= BLOCKC;
-- Inserting 'else' block to prevent latch inference
ELSE
reg_fstate <= BLOCKB;
END IF;
data <= "000000001111111100000000";
WHEN BLOCKC =>
IF ((col_select(2 DOWNTO 0) = "000")) THEN
reg_fstate <= IDLE;
ELSIF (((col_select(2 DOWNTO 0) = "001") AND (data_en = '1'))) THEN
reg_fstate <= BLOCKA;
-- Inserting 'else' block to prevent latch inference
ELSE
reg_fstate <= BLOCKC;
END IF;
data <= "111111110000000000000000";
WHEN OTHERS =>
data <= "XXXXXXXXXXXXXXXXXXXXXXXX";
report "Reach undefined state";
END CASE;
END IF;
END PROCESS;
END BEHAVIOR;
| mit | fc889caf8c31d28db1d4852428caea99 | 0.535864 | 4.847716 | false | false | false | false |
michaelmiehling/A25_VME_TB | Testbench/mt58l512l18f.vhd | 1 | 12,169 | -------------------------------------------------------------------------------
--
-- File Name: MT58L512L18F.VHD
-- Revision: 2.0
-- Date: April 3rd, 2002
-- Model: Bus Functional
-- Simulator: Aldec, ModemSim, NCDesktop
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: [email protected]
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part #: MT58L512L18F
--
-- Description: Micron 8 Meg SyncBurst SRAM (Flow-through)
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1997 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Phone Date Changes
-- --- -------------- ------------ ---------- -----------------------------
-- 2.0 Son P. Huynh 208-368-3825 04/03/2002 - Fix Burst counter
-- Micron Technology, Inc.
--
-------------------------------------------------------------------------------
LIBRARY ieee, std, work;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.standard.ALL;
USE std.textio.all;
ENTITY MT58L512L18F IS
GENERIC (
-- Clock
tKC : TIME := 8.0 ns; -- Timing are for -6.8
tKH : TIME := 1.8 ns;
tKL : TIME := 1.8 ns;
-- Output Times
tKQHZ : TIME := 3.8 ns;
-- Setup Times
tAS : TIME := 1.8 ns;
tADSS : TIME := 1.8 ns;
tAAS : TIME := 1.8 ns;
tWS : TIME := 1.8 ns;
tDS : TIME := 1.8 ns;
tCES : TIME := 1.8 ns;
-- Hold Times
tAH : TIME := 0.5 ns;
tADSH : TIME := 0.5 ns;
tAAH : TIME := 0.5 ns;
tWH : TIME := 0.5 ns;
tDH : TIME := 0.5 ns;
tCEH : TIME := 0.5 ns;
-- Bus Width and Data Bus
addr_bits : INTEGER := 19;
data_bits : INTEGER := 16
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Mode : IN STD_LOGIC;
Adv_n : IN STD_LOGIC;
Clk : IN STD_LOGIC;
Adsc_n : IN STD_LOGIC;
Adsp_n : IN STD_LOGIC;
Bwa_n : IN STD_LOGIC;
Bwb_n : IN STD_LOGIC;
Bwe_n : IN STD_LOGIC;
Gw_n : IN STD_LOGIC;
Ce_n : IN STD_LOGIC;
Ce2 : IN STD_LOGIC;
Ce2_n : IN STD_LOGIC;
Oe_n : IN STD_LOGIC;
Zz : IN STD_LOGIC
);
END MT58L512L18F;
ARCHITECTURE behave OF MT58L512L18F IS
TYPE memory IS ARRAY (2 ** addr_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits / 2 - 1 DOWNTO 0);
SIGNAL doe : STD_LOGIC;
SIGNAL dout : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
SIGNAL bwan, bwbn, ce, clr : STD_LOGIC;
--FILE outfile: TEXT IS OUT "sram_outfile.txt";
BEGIN
bwan <= ((Bwa_n OR Bwe_n) AND Gw_n) OR (NOT(Ce_n) AND NOT(Adsp_n));
bwbn <= ((Bwb_n OR Bwe_n) AND Gw_n) OR (NOT(Ce_n) AND NOT(Adsp_n));
ce <= NOT(Ce_n) AND Ce2 AND NOT(Ce2_n);
clr <= NOT(Adsc_n) OR (NOT(Adsp_n) AND NOT(Ce_n));
main : PROCESS
-- Memory Array
VARIABLE bank0, bank1 : memory;
-- Address Registers
VARIABLE addr_reg_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE addr_reg_out : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
-- Burst Counter
VARIABLE bcount : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
VARIABLE baddr0 : STD_LOGIC;
VARIABLE baddr1 : STD_LOGIC;
-- Other Registers
VARIABLE din : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
VARIABLE ce_reg : STD_LOGIC;
VARIABLE bwa_reg : STD_LOGIC;
VARIABLE bwb_reg : STD_LOGIC;
VARIABLE write_line : line;
VARIABLE i,j : integer;
VARIABLE dat : STD_LOGIC_VECTOR (data_bits*2 - 1 DOWNTO 0);
BEGIN
i := 0;
j := 0;
LOOP
dat := conv_std_logic_vector(j,data_bits*2);
bank0(i) := dat(data_bits/2 -1 DOWNTO 0);
bank1(i) := dat(data_bits-1 DOWNTO data_bits/2);
bank0(i+1) := dat(3*data_bits/2 -1 DOWNTO data_bits);
bank1(i+1) := dat(2*data_bits-1 DOWNTO 3*data_bits/2);
i := i + 2;
j := j + 1;
IF i = 2 ** addr_bits THEN
exit;
END IF;
END LOOP;
LOOP
WAIT ON Clk;
IF Clk'EVENT AND Clk = '1' AND Zz = '0' THEN
-- Address Register
IF clr = '1' THEN
addr_reg_in := Addr;
END IF;
-- Binary Counter and Logic
IF Mode = '1' AND clr = '1' THEN
bcount := "00";
ELSIF Mode = '0' AND clr = '1' THEN
bcount := Addr(1 DOWNTO 0);
ELSIF Adv_n = '0' AND clr = '0' THEN
bcount(1) := bcount(0) XOR bcount(1);
bcount(0) := NOT(bcount(0));
END IF;
-- Burst Address Decode
IF Mode = '1' THEN
baddr0 := bcount(0) XOR addr_reg_in(0);
baddr1 := bcount(1) XOR addr_reg_in(1);
ELSE
baddr0 := bcount(0);
baddr1 := bcount(1);
END IF;
-- Output Address
addr_reg_out (addr_bits - 1 DOWNTO 2) := addr_reg_in (addr_bits - 1 DOWNTO 2);
addr_reg_out (1) := baddr1;
addr_reg_out (0) := baddr0;
-- Byte Write Register
bwa_reg := NOT(bwan);
bwb_reg := NOT(bwbn);
-- Enable Register
IF clr = '1' THEN
ce_reg := ce;
END IF;
-- Input Register
IF (ce_reg = '1' AND (bwa_reg = '1' OR bwb_reg = '1')) THEN
din := Dq;
ELSE
din := (OTHERS => 'Z');
END IF;
-- Byte Write Driver
IF ce_reg = '1' AND bwa_reg = '1' THEN
bank0 (CONV_INTEGER(addr_reg_out)) := din ( 7 DOWNTO 0);
-- WRITE(write_line, 'W');
-- WRITE(write_line, 'L');
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(addr_reg_out));
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(din(7 DOWNTO 0)));
-- WRITELINE(outfile, write_line);
END IF;
IF ce_reg = '1' AND bwb_reg = '1' THEN
bank1 (CONV_INTEGER(addr_reg_out)) := din (15 DOWNTO 8);
-- WRITE(write_line, 'W');
-- WRITE(write_line, 'H');
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(addr_reg_out));
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(din(15 DOWNTO 8)));
-- WRITELINE(outfile, write_line);
END IF;
-- Output Register
IF (NOT(bwa_reg = '1' OR bwb_reg = '1')) THEN
dout ( 7 DOWNTO 0) <= bank0 (CONV_INTEGER(addr_reg_out));
dout (15 DOWNTO 8) <= bank1 (CONV_INTEGER(addr_reg_out));
-- WRITE(write_line, 'R');
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(addr_reg_out));
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(bank1 (CONV_INTEGER(addr_reg_out))));
-- WRITE(write_line, TO_HEX_STRING(bank0 (CONV_INTEGER(addr_reg_out))));
-- WRITELINE(outfile, write_line);
END IF;
-- Data Out Enable
doe <= ce_reg AND (NOT(bwa_reg OR bwb_reg));
END IF;
END LOOP;
END PROCESS main;
-- Output buffer
WITH (NOT(Oe_n) AND NOT(Zz) AND doe) SELECT
Dq <= TRANSPORT dout AFTER tKQHZ WHEN '1',
(OTHERS => 'Z') AFTER tKQHZ WHEN '0',
(OTHERS => 'Z') AFTER tKQHZ WHEN OTHERS;
-- Checking for setup time violation
Setup_check : PROCESS
BEGIN
WAIT ON Clk;
IF Clk'EVENT AND Clk = '1' THEN
ASSERT(Addr'LAST_EVENT >= tAS)
REPORT "Addr Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Adsc_n'LAST_EVENT >= tADSS)
REPORT "Adsc_n Setup time violation -- tADSS"
SEVERITY WARNING;
ASSERT(Adsp_n'LAST_EVENT >= tADSS)
REPORT "Adsp_n Setup time violation -- tADSS"
SEVERITY WARNING;
ASSERT(Adv_n'LAST_EVENT >= tAAS)
REPORT "Adv_n Setup time violation -- tAAS"
SEVERITY WARNING;
ASSERT(Bwa_n'LAST_EVENT >= tWS)
REPORT "Bwa_n Setup time violation -- tWS"
SEVERITY WARNING;
ASSERT(Bwb_n'LAST_EVENT >= tWS)
REPORT "Bwb_n Setup time violation -- tWS"
SEVERITY WARNING;
ASSERT(Bwe_n'LAST_EVENT >= tWS)
REPORT "Bwe_n Setup time violation -- tWS"
SEVERITY WARNING;
ASSERT(Gw_n'LAST_EVENT >= tWS)
REPORT "Gw_n Setup time violation -- tWS"
SEVERITY WARNING;
ASSERT(Ce_n'LAST_EVENT >= tCES)
REPORT "Ce_n Setup time violation -- tCES"
SEVERITY WARNING;
ASSERT(Ce2_n'LAST_EVENT >= tCES)
REPORT "Ce2_n Setup time violation -- tCES"
SEVERITY WARNING;
ASSERT(Ce2'LAST_EVENT >= tCES)
REPORT "Ce2 Setup time violation -- tCES"
SEVERITY WARNING;
END IF;
END PROCESS;
-- Checking for hold time violation
Hold_check : PROCESS
BEGIN
WAIT ON Clk'DELAYED(tAH), Clk'DELAYED(tADSH), Clk'DELAYED(tAAH), Clk'DELAYED(tWH), Clk'DELAYED(tCEH);
IF Clk'DELAYED(tAH)'EVENT AND Clk'DELAYED(tAH) = '1' THEN
ASSERT(Addr'LAST_EVENT > tAH)
REPORT "Addr Hold time violation -- tAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED(tADSH)'EVENT AND Clk'DELAYED(tADSH) = '1' THEN
ASSERT(Adsc_n'LAST_EVENT > tADSH)
REPORT "Adsc_n Hold time violation -- tADSH"
SEVERITY WARNING;
ASSERT(Adsp_n'LAST_EVENT > tADSH)
REPORT "Adsp_n Hold time violation -- tADSH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED(tAAH)'EVENT AND Clk'DELAYED(tAAH) = '1' THEN
ASSERT(Adv_n'LAST_EVENT > tAAH)
REPORT "Adv_n Hold time violation -- tAAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED(tWH)'EVENT AND Clk'DELAYED(tWH) = '1' THEN
ASSERT(Bwa_n'LAST_EVENT > tWH)
REPORT "Bwa_n Hold time violation -- tWH"
SEVERITY WARNING;
ASSERT(Bwb_n'LAST_EVENT > tWH)
REPORT "Bwb_n Hold time violation -- tWH"
SEVERITY WARNING;
ASSERT(Bwe_n'LAST_EVENT > tWH)
REPORT "Bwe_n Hold time violation -- tWH"
SEVERITY WARNING;
ASSERT(Gw_n'LAST_EVENT > tWH)
REPORT "Gw_n Hold time violation -- tWH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED(tCEH)'EVENT AND Clk'DELAYED(tCEH) = '1' THEN
ASSERT(Ce_n'LAST_EVENT > tCEH)
REPORT "Ce_n Hold time violation -- tCEH"
SEVERITY WARNING;
ASSERT(Ce2_n'LAST_EVENT > tCEH)
REPORT "Ce2_n Hold time violation -- tCEH"
SEVERITY WARNING;
ASSERT(Ce2'LAST_EVENT > tCEH)
REPORT "Ce2 Hold time violation -- tCEH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
| gpl-3.0 | 1b6731addc20b0d10d7f432446c98481 | 0.485249 | 3.627124 | false | false | false | false |
michaelmiehling/A25_VME_TB | Testbench/terminal.vhd | 1 | 9,633 | ---------------------------------------------------------------
-- Title : Simulation Terminal
-- Project : -
---------------------------------------------------------------
-- File : terminal.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 10/11/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
-- Application Layer for simulation stimuli
---------------------------------------------------------------
-- Hierarchy:
--
-- testbench
-- terminal
-- wb_test
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: terminal.vhd,v $
-- Revision 1.3 2013/07/15 13:14:20 mmiehling
-- adopted testcases
--
-- Revision 1.2 2013/04/18 15:11:08 MMiehling
-- support of pcie model
--
-- Revision 1.1 2012/03/29 10:28:43 MMiehling
-- Initial Revision
--
-- Revision 1.2 2006/03/15 14:21:54 mmiehling
-- extended tga
-- removed "use work.vme_pkg.all"
--
-- Revision 1.1 2005/08/23 15:21:05 MMiehling
-- Initial Revision
--
-- Revision 1.3 2005/03/18 15:14:18 MMiehling
-- changed
--
-- Revision 1.2 2005/01/31 16:28:56 mmiehling
-- updated
--
-- Revision 1.1 2004/11/16 12:09:06 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.print_pkg.all;
USE work.terminal_pkg.ALL;
USE work.vme_sim_pack.all;
USE work.pcie_sim_pkg.ALL;
LIBRARY modelsim_lib;
USE modelsim_lib.util.all;
USE std.textio.all;
ENTITY terminal IS
PORT (
hreset_n : OUT std_logic;
slot1 : OUT boolean:=TRUE; -- if true dut is in slot1
en_clk : OUT boolean:=TRUE; -- if true dut is supplied with 16 mhz clk
terminal_in_0 : IN terminal_in_type; -- PCIe Master Model
terminal_out_0 : OUT terminal_out_type;
terminal_in_1 : IN terminal_in_type; -- VMEbus Master Model
terminal_out_1 : OUT terminal_out_type;
vme_slv_in : OUT vme_slv_in_type;
vme_slv_out : IN vme_slv_out_type;
vme_mon_out : IN vme_mon_out_type;
v2p_rstn : IN std_logic; -- connected to hreset_req1_n
vme_ga : OUT std_logic_vector(4 DOWNTO 0); -- geographical addresses
vme_gap : OUT std_logic -- geographical addresses
);
END terminal;
ARCHITECTURE terminal_arch OF terminal IS
SIGNAL terminal_err_0 : integer:=0;
SIGNAL end_of_tests : boolean;
SIGNAL vb_sysresn : std_logic;
SIGNAL irq_req : std_logic_vector(16 DOWNTO 0);
CONSTANT en_msg_0 : integer:= 2;
BEGIN
term_0: PROCESS
VARIABLE err : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
BEGIN
hreset_n <= '0';
en_clk <= TRUE;
vme_ga <= (OTHERS => '0');
vme_gap <= '0';
--init_signal_spy("/a25_tb/a25/pcie/irq_req","irq_req",1,1);
init_signal_spy("/a25_tb/vb_sysresn","vb_sysresn",1,1);
init(terminal_out_0);
init(terminal_out_1);
init_vme_slv(vme_slv_in);
-- powerup board
-- shorten reset time on vme bus
signal_force("/a25_tb/a25/vme/vmectrl/bustimer/pre_cnt_max_sig", "0000001000", 0 ns, freeze, -1 ns, 1);
signal_force("/a25_tb/a25/vme/vmectrl/bustimer/main_cnt_max_sig", "000000000000011", 0 ns, freeze, -1 ns, 1);
--signal_force("/a25_tb/a25/pcie/test_pcie_core", "0000000000000001", 0 ns, freeze, -1 ns, 1);
--signal_force("/a25_tb/a25/pcie/test_rs_serdes", "1", 0 ns, freeze, -1 ns, 1);
slot1 <= TRUE;
WAIT FOR 100 ns;
hreset_n <= '1';
WAIT FOR 2 us;
--! procedure to initialize the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be initialized
--! @param io_add start address for the BFM internal I/O space
--! @param mem32_addr start address for the BFM internal MEM32 space
--! @param mem64_addr start address for the BFM internal MEM64 space
--! @param requester_id defines the requester ID that is used for every BFM transfer
--! @param max_payloadsize defines the maximum payload size for every write request
init_bfm(0, x"0000_0000", SIM_BAR0, x"0000_0000_0000_0000", x"0000", 256);
--! procedure to configure the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be configured
--! @param max_payload_size maximum payload size for write requests
--! @param max_read_size maximum payload size for read requests
--! @param bar0 BAR0 settings
--! @param bar1 BAR1 settings
--! @param bar2 BAR2 settings
--! @param bar3 BAR3 settings
--! @param bar4 BAR4 settings
--! @param bar5 BAR5 settings
--! @param cmd_status_reg settings for the command status register
--! @param ctrl_status_reg settings for the control status register
configure_bfm(terminal_in => terminal_in_0, terminal_out => terminal_out_0, bar0_addr => BAR0, bar1_addr => BAR1, bar2_addr => BAR2, bar3_addr => BAR3, bar4_addr => BAR4, bar5_addr => BAR5, txt_out => en_msg_0);
WAIT FOR 3 us;
print("***************************************************");
print(" Start of Tests");
print("***************************************************");
-- Reset:
vme_reset(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, slot1, hreset_n, v2p_rstn, vb_sysresn, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
-- VME Buserror:
vme_buserror(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
-- chameleon
cham_test(terminal_in_0, terminal_out_0, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
-- geographical address test
vme_ga_test(terminal_in_0, terminal_out_0, vme_ga, vme_gap, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
-- VME Slave:
vme_slave_a242sram(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
vme_slave_a242pci(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
vme_slave_a322sram(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
vme_slave_a322pci(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
vme_slave_a162regs(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
-- VME Master:
vme_master_windows(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
-- VME Interrupt Handler:
vme_irq_rcv(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, vme_slv_in, vme_slv_out, irq_req, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
-- VME Interrupter:
vme_irq_trans(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, vme_slv_in, vme_slv_out, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
-- VME DMA:
vme_dma_boundaries(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
vme_dma_fifo(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
vme_dma_sram2a24d32(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
vme_dma_am(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, vme_slv_in, vme_slv_out, irq_req, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
vme_dma_sram2sram(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
vme_dma_sram2a32d32(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
vme_dma_sram2a32d64(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
vme_dma_sram2pci(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
vme_arbitration(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, hreset_n, slot1, en_clk, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
WAIT FOR 1 us;
print("***************************************************");
print(" Test Summary:");
print_s_i(" Number of errors: ", terminal_err_0);
print("***************************************************");
ASSERT FALSE REPORT "--- END OF SIMULATION ---" SEVERITY failure;
WAIT;
END PROCESS term_0;
END terminal_arch;
| gpl-3.0 | 3d02080b20113153accbcee8dd86f131 | 0.584449 | 3.291083 | false | false | false | false |
freecores/t48 | rtl/vhdl/system/generic_ram_ena.vhd | 1 | 3,242 | -------------------------------------------------------------------------------
--
-- Parametrizable, generic RAM with enable.
--
-- $Id: generic_ram_ena.vhd,v 1.1 2006-06-21 00:59:15 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity generic_ram_ena is
generic (
addr_width_g : integer := 10;
data_width_g : integer := 8
);
port (
clk_i : in std_logic;
a_i : in std_logic_vector(addr_width_g-1 downto 0);
we_i : in std_logic;
ena_i : in std_logic;
d_i : in std_logic_vector(data_width_g-1 downto 0);
d_o : out std_logic_vector(data_width_g-1 downto 0)
);
end generic_ram_ena;
library ieee;
use ieee.numeric_std.all;
architecture rtl of generic_ram_ena is
type mem_t is array (natural range 0 to 2**addr_width_g-1) of
std_logic_vector(d_i'range);
signal mem_q : mem_t
-- pragma translate_off
:= (others => (others => '0'))
-- pragma translate_on
;
signal a_q : std_logic_vector(a_i'range);
begin
mem: process (clk_i)
begin
if clk_i'event and clk_i = '1' then
if ena_i = '1' then
if we_i = '1' then
mem_q(to_integer(unsigned(a_i))) <= d_i;
end if;
a_q <= a_i;
end if;
end if;
end process mem;
d_o <= mem_q(to_integer(unsigned(a_q)));
end rtl;
| gpl-2.0 | 87aaa2f3f36ef33c51fc49e45631eb8c | 0.659778 | 3.800703 | false | false | false | false |
nulldozer/purisc | Compute_Group/MAGIC_clocked/SETUP.vhd | 2 | 12,679 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SETUP is
PORT(
CLK : IN STD_LOGIC;
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
STALL : OUT STD_LOGIC;
HAZARD : IN STD_LOGIC;
ram_0_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_0_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_0_wren_a : OUT STD_LOGIC;
ram_0_wren_b : OUT STD_LOGIC;
ram_1_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_1_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_1_wren_a : OUT STD_LOGIC;
ram_1_wren_b : OUT STD_LOGIC;
ram_2_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_2_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_2_wren_a : OUT STD_LOGIC;
ram_2_wren_b : OUT STD_LOGIC;
ram_3_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_3_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_3_wren_a : OUT STD_LOGIC;
ram_3_wren_b : OUT STD_LOGIC;
ram_4_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_4_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_4_wren_a : OUT STD_LOGIC;
ram_4_wren_b : OUT STD_LOGIC;
ram_5_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_5_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_5_wren_a : OUT STD_LOGIC;
ram_5_wren_b : OUT STD_LOGIC;
ram_6_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_6_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_6_wren_a : OUT STD_LOGIC;
ram_6_wren_b : OUT STD_LOGIC;
ram_7_port_a : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_7_port_b : OUT STD_LOGIC_VECTOR (9 downto 0);
ram_7_wren_a : OUT STD_LOGIC;
ram_7_wren_b : OUT STD_LOGIC;
ram_0_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_1_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_2_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_3_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_4_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_5_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_6_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_7_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end;
architecture control of SETUP is
component address_transcode
PORT (
ADDRESS : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ROW : OUT STD_LOGIC_VECTOR (9 downto 0);
COL : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
end component;
component create_opcode
PORT (
COL_A : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_B : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_C : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_D : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_E : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_W : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
W_EN : IN STD_LOGIC;
OPCODE_0 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_1 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_2 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_3 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_4 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_5 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_6 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_7 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component;
component FLOW
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
ROW_A : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_B : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_C : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_D : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_E : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_W : IN STD_LOGIC_VECTOR(9 downto 0);
HAZARD : IN STD_LOGIC;
EQUALITY : OUT STD_LOGIC;
ADDRESS_A : OUT STD_LOGIC_VECTOR(9 downto 0);
ADDRESS_B : OUT STD_LOGIC_VECTOR(9 downto 0);
SEL_VECTOR : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
WREN_A : OUT STD_LOGIC;
WREN_B : OUT STD_LOGIC
);
end component;
signal COL_A : std_logic_vector (2 downto 0);
signal COL_B : std_logic_vector (2 downto 0);
signal COL_C : std_logic_vector (2 downto 0);
signal COL_D : std_logic_vector (2 downto 0);
signal COL_E : std_logic_vector (2 downto 0);
signal COL_W : std_logic_vector (2 downto 0);
signal ROW_A : std_logic_vector (9 downto 0);
signal ROW_B : std_logic_vector (9 downto 0);
signal ROW_C : std_logic_vector (9 downto 0);
signal ROW_D : std_logic_vector (9 downto 0);
signal ROW_E : std_logic_vector (9 downto 0);
signal ROW_W : std_logic_vector (9 downto 0);
signal OPCODE_0 : std_logic_vector (5 downto 0);
signal OPCODE_1 : std_logic_vector (5 downto 0);
signal OPCODE_2 : std_logic_vector (5 downto 0);
signal OPCODE_3 : std_logic_vector (5 downto 0);
signal OPCODE_4 : std_logic_vector (5 downto 0);
signal OPCODE_5 : std_logic_vector (5 downto 0);
signal OPCODE_6 : std_logic_vector (5 downto 0);
signal OPCODE_7 : std_logic_vector (5 downto 0);
signal equality_0 : std_logic;
signal equality_1 : std_logic;
signal equality_2 : std_logic;
signal equality_3 : std_logic;
signal equality_4 : std_logic;
signal equality_5 : std_logic;
signal equality_6 : std_logic;
signal equality_7 : std_logic;
begin
transcode_a : address_transcode PORT MAP (
ADDRESS => ADDRESS_A,
ROW => ROW_A,
COL => COL_A
);
transcode_b : address_transcode PORT MAP (
ADDRESS => ADDRESS_B,
ROW => ROW_B,
COL => COL_B
);
transcode_c : address_transcode PORT MAP (
ADDRESS => ADDRESS_C,
ROW => ROW_C,
COL => COL_C
);
transcode_d : address_transcode PORT MAP (
ADDRESS => ADDRESS_0,
ROW => ROW_D,
COL => COL_D
);
transcode_e : address_transcode PORT MAP (
ADDRESS => ADDRESS_1,
ROW => ROW_E,
COL => COL_E
);
transcode_w : address_transcode PORT MAP (
ADDRESS => ADDRESS_W,
ROW => ROW_W,
COL => COL_W
);
opcodery : create_opcode PORT MAP (
COL_A => COL_A,
COL_B => COL_B,
COL_C => COL_C,
COL_D => COL_D,
COL_E => COL_E,
COL_W => COL_W,
W_EN => W_EN,
OPCODE_0 => OPCODE_0,
OPCODE_1 => OPCODE_1,
OPCODE_2 => OPCODE_2,
OPCODE_3 => OPCODE_3,
OPCODE_4 => OPCODE_4,
OPCODE_5 => OPCODE_5,
OPCODE_6 => OPCODE_6,
OPCODE_7 => OPCODE_7
);
RAM_0_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_0,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_0,
ADDRESS_A => ram_0_port_a,
ADDRESS_B => ram_0_port_b,
SEL_VECTOR => ram_0_sel_vector,
WREN_A => ram_0_wren_a,
WREN_B => ram_0_wren_b
);
RAM_1_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_1,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_1,
ADDRESS_A => ram_1_port_a,
ADDRESS_B => ram_1_port_b,
SEL_VECTOR => ram_1_sel_vector,
WREN_A => ram_1_wren_a,
WREN_B => ram_1_wren_b
);
RAM_2_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_2,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_2,
ADDRESS_A => ram_2_port_a,
ADDRESS_B => ram_2_port_b,
SEL_VECTOR => ram_2_sel_vector,
WREN_A => ram_2_wren_a,
WREN_B => ram_2_wren_b
);
RAM_3_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_3,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_3,
ADDRESS_A => ram_3_port_a,
ADDRESS_B => ram_3_port_b,
SEL_VECTOR => ram_3_sel_vector,
WREN_A => ram_3_wren_a,
WREN_B => ram_3_wren_b
);
RAM_4_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_4,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_4,
ADDRESS_A => ram_4_port_a,
ADDRESS_B => ram_4_port_b,
SEL_VECTOR => ram_4_sel_vector,
WREN_A => ram_4_wren_a,
WREN_B => ram_4_wren_b
);
RAM_5_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_5,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_5,
ADDRESS_A => ram_5_port_a,
ADDRESS_B => ram_5_port_b,
SEL_VECTOR => ram_5_sel_vector,
WREN_A => ram_5_wren_a,
WREN_B => ram_5_wren_b
);
RAM_6_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_6,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_6,
ADDRESS_A => ram_6_port_a,
ADDRESS_B => ram_6_port_b,
SEL_VECTOR => ram_6_sel_vector,
WREN_A => ram_6_wren_a,
WREN_B => ram_6_wren_b
);
RAM_7_CONTROL : FLOW PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_7,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_7,
ADDRESS_A => ram_7_port_a,
ADDRESS_B => ram_7_port_b,
SEL_VECTOR => ram_7_sel_vector,
WREN_A => ram_7_wren_a,
WREN_B => ram_7_wren_b
);
STALL <= not (equality_0 and equality_1 and equality_2 and equality_3 and equality_4 and equality_5 and equality_6 and equality_7);
end;
| gpl-2.0 | ef0b408b54bb3ada9246ec63c4e73722 | 0.510529 | 3.040528 | false | false | false | false |
straywarrior/MadeCPUin21days | Register_Files.vhd | 1 | 3,493 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 15:28:57 11/14/2015
-- Design Name:
-- Module Name: Register_Files - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Register_Files is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
ASel : in STD_LOGIC_VECTOR (3 downto 0);
BSel : in STD_LOGIC_VECTOR (3 downto 0);
WSel : in STD_LOGIC_VECTOR (3 downto 0);
WE : in STD_LOGIC;
WVal : in STD_LOGIC_VECTOR (15 downto 0);
AVal : out STD_LOGIC_VECTOR (15 downto 0);
BVal : out STD_LOGIC_VECTOR (15 downto 0);
RAVal : out STD_LOGIC_VECTOR (15 downto 0);
SPVal : out STD_LOGIC_VECTOR (15 downto 0);
IHVal : out STD_LOGIC_VECTOR (15 downto 0)
);
end Register_Files;
architecture Behavioral of Register_Files is
type regs is array (0 to 10) of STD_LOGIC_VECTOR(15 downto 0);
-- 8 universal regs (R0 ~ R7) and 3 special regs (RA 1000, SP 1001, IH 1010)
signal regfiles : regs := (others => (others => '0'));
begin
process (clk, reset)
begin
if (reset = '0') then
RAVal <= (others => '0');
SPVal <= (others => '0');
IHVal <= (others => '0');
AVal <= (others => '0');
BVal <= (others => '0');
regfiles <= (others => (others => '0'));
elsif (clk'event and clk = '1') then
if (WE = '1' and WSel /= "1111") then
regfiles(CONV_INTEGER(unsigned(WSel))) <= WVal;
if ("1000" = WSel) then
RAVal <= WVal;
else
RAVal <= regfiles(8);
end if;
if ("1001" = WSel) then
SPVal <= WVal;
else
SPVal <= regfiles(9);
end if;
if ("1010" = WSel) then
IHVal <= WVal;
else
IHVal <= regfiles(10);
end if;
if (ASel = WSel) then
AVal <= WVal;
else
AVal <= regfiles(CONV_INTEGER(unsigned(ASel(2 downto 0))));
end if;
if (BSel = WSel) then
BVal <= WVal;
else
BVal <= regfiles(CONV_INTEGER(unsigned(BSel(2 downto 0))));
end if;
else
RAVal <= regfiles(8);
SPVal <= regfiles(9);
IHVal <= regfiles(10);
AVal <= regfiles(CONV_INTEGER(unsigned(ASel(2 downto 0))));
BVal <= regfiles(CONV_INTEGER(unsigned(BSel(2 downto 0))));
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | be1e532b45f84f1a59924f45300ace1d | 0.477526 | 4.254568 | false | false | false | false |
cathalmccabe/PYNQ | boards/ip/rgb2dvi_v1_2/src/ClockGen.vhd | 9 | 8,885 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/03/2014 06:27:16 PM
-- Design Name:
-- Module Name: ClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ClockGen is
Generic (
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
kClkPrimitive : string := "MMCM"); -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
Port (
PixelClkIn : in STD_LOGIC;
PixelClkOut : out STD_LOGIC;
SerialClk : out STD_LOGIC;
aRst : in STD_LOGIC;
aLocked : out STD_LOGIC);
end ClockGen;
architecture Behavioral of ClockGen is
component SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end component SyncAsync;
component ResetBridge is
Generic (
kPolarity : std_logic := '1');
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
oRst : out STD_LOGIC);
end component ResetBridge;
signal PixelClkInX1, PixelClkInX5, FeedbackClk : std_logic;
signal aLocked_int, pLocked, pRst, pLockWasLost : std_logic;
signal pLocked_q : std_logic_vector(2 downto 0) := (others => '1');
begin
-- We need a reset bridge to use the asynchronous aRst signal to reset our circuitry
-- and decrease the chance of metastability. The signal pRst can be used as
-- asynchronous reset for any flip-flop in the PixelClkIn domain, since it will be de-asserted
-- synchronously.
LockLostReset: ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRst,
OutClk => PixelClkIn,
oRst => pRst);
PLL_LockSyncAsync: SyncAsync
port map (
aReset => '0',
aIn => aLocked_int,
OutClk => PixelClkIn,
oOut => pLocked);
PLL_LockLostDetect: process(PixelClkIn)
begin
if (pRst = '1') then
pLocked_q <= (others => '1');
pLockWasLost <= '1';
elsif Rising_Edge(PixelClkIn) then
pLocked_q <= pLocked_q(pLocked_q'high-1 downto 0) & pLocked;
pLockWasLost <= (not pLocked_q(0) or not pLocked_q(1)) and pLocked_q(2); --two-pulse
end if;
end process;
-- The TMDS Clk channel carries a character-rate frequency reference
-- In a single Clk period a whole character (10 bits) is transmitted
-- on each data channel. For deserialization of data channel a faster,
-- serial clock needs to be generated. In 7-series architecture an
-- OSERDESE2 primitive doing a 10:1 deserialization in DDR mode needs
-- a fast 5x clock and a slow 1x clock. These two clocks are generated
-- below with an MMCME2_ADV/PLLE2_ADV.
-- Caveats:
-- 1. The primitive uses a multiply-by-5 and divide-by-1 to generate
-- a 5x fast clock.
-- While changes in the frequency of the TMDS Clk are tracked by the
-- MMCM, for some TMDS Clk frequencies the datasheet specs for the VCO
-- frequency limits are not met. In other words, there is no single
-- set of MMCM multiply and divide values that can work for the whole
-- range of resolutions and pixel clock frequencies.
-- For example: MMCM_FVCOMIN = 600 MHz
-- MMCM_FVCOMAX = 1200 MHz for Artix-7 -1 speed grade
-- while FVCO = FIN * MULT_F
-- The TMDS Clk for 720p resolution in 74.25 MHz
-- FVCO = 74.25 * 10 = 742.5 MHz, which is between FVCOMIN and FVCOMAX
-- However, the TMDS Clk for 1080p resolution in 148.5 MHz
-- FVCO = 148.5 * 10 = 1480 MHZ, which is above FVCOMAX
-- In the latter case, MULT_F = 5, DIVIDE_F = 5, DIVIDE = 1 would result
-- in a correct VCO frequency, while still generating 5x and 1x clocks
-- 2. The MMCM+BUFIO+BUFR combination results in the highest possible
-- frequencies. PLLE2_ADV could work only with BUFGs, which limits
-- the maximum achievable frequency. The reason is that only the MMCM
-- has dedicated route to BUFIO.
-- If a PLLE2_ADV with BUFGs are used a second CLKOUTx can be used to
-- generate the 1x clock.
GenMMCM: if kClkPrimitive = "MMCM" generate
DVI_ClkGenerator: MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => real(kClkRange) * 5.0,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => real(kClkRange) * 1.0,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => kClkRange * 5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_PHASE => 0.0,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => real(kClkRange) * 6.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => FeedbackClk,
CLKFBOUTB => open,
CLKOUT0 => PixelClkInX5,
CLKOUT0B => open,
CLKOUT1 => PixelClkInX1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => FeedbackClk,
CLKIN1 => PixelClkIn,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => aLocked_int,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => pLockWasLost);
end generate;
GenPLL: if kClkPrimitive /= "MMCM" generate
DVI_ClkGenerator: PLLE2_ADV
generic map (
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => (kClkRange + 1) * 5,
CLKFBOUT_PHASE => 0.000,
CLKIN1_PERIOD => real(kClkRange) * 6.25,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
REF_JITTER1 => 0.010,
STARTUP_WAIT => "FALSE",
CLKOUT0_DIVIDE => (kClkRange + 1) * 1,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => (kClkRange + 1) * 5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_PHASE => 0.0)
port map
-- Output clocks
(
CLKFBOUT => FeedbackClk,
CLKOUT0 => PixelClkInX5,
CLKOUT1 => PixelClkInX1,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- Input clock control
CLKFBIN => FeedbackClk,
CLKIN1 => PixelClkIn,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Other control and status signals
LOCKED => aLocked_int,
PWRDWN => '0',
RST => pLockWasLost);
end generate;
--No buffering used
--These clocks will only drive the OSERDESE2 primitives
SerialClk <= PixelClkInX5;
PixelClkOut <= PixelClkInX1;
aLocked <= aLocked_int;
end Behavioral;
| bsd-3-clause | 2409f74ddbbcb2a14b83e0a1839bb433 | 0.557344 | 4.159644 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GN46N4UJ5S.vhd | 20 | 844 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN46N4UJ5S is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic;
output : out std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN46N4UJ5S is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 1 + 1 ,
width_inr=> 0,
width_outl=> 1,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(0) => input,
xin(1) => '0', yout => output
);
end architecture; | mit | bd8d254d846bd7f839cb916c7ccd3d36 | 0.64455 | 2.982332 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_multiplier_GNEIWYOKUR.vhd | 4 | 1,360 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiplier_GNEIWYOKUR is
generic ( DEDICATED_MULTIPLIER_CIRCUITRY : string := "YES";
Signed : natural := 0;
OutputMsb : integer := 47;
aWidth : natural := 24;
bWidth : natural := 24;
OutputLsb : integer := 0;
pipeline : integer := 0);
port(
aclr : in std_logic;
clock : in std_logic;
dataa : in std_logic_vector((aWidth)-1 downto 0);
datab : in std_logic_vector((bWidth)-1 downto 0);
ena : in std_logic;
result : out std_logic_vector((OutputMsb-OutputLsb+1)-1 downto 0);
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_multiplier_GNEIWYOKUR is
signal reset: STD_LOGIC;
Begin
-- DSP Builder Block - Simulink Block "Multiplier"
Multiplieri : alt_dspbuilder_sMultAltr Generic map (
pipeline => 0,
lpm_representation => "UNSIGNED",
OutputMsb => 47,
OutputLsb => 0,
lpm_widtha => 24,
lpm_widthb => 24,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES")
port map (
clock => clock,
aclr => aclr,
user_aclr => user_aclr,
ena => ena,
dataa => dataa,
datab => datab,
result => result);
end architecture;
| mit | 932edc1d4996116ea75f969cc2de11b9 | 0.660294 | 3.015521 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_AROUND.vhd | 20 | 2,588 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
| mit | 7c35146141199d1068f0be46a17c62db | 0.667697 | 3.665722 | false | false | false | false |
nulldozer/purisc | Global_memory/MAGIC_global/ROUTE_SIGNAL_global.vhd | 2 | 4,370 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ROUTE_SIGNAL_global is
PORT(
ram_0_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
select_vector : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
hazard : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OUTPUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end;
architecture signal_routing of ROUTE_SIGNAL_global is
component tristate_32
PORT(
my_in : in std_logic_vector(31 downto 0);
sel : in std_logic;
my_out : out std_logic_vector(31 downto 0)
);
end component;
component HAZARD_RESOLVE_global
PORT(
select_signal : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
hazard : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end component;
signal data : std_logic_vector(31 downto 0);
begin
a_0 : tristate_32 PORT MAP (
my_in => ram_0_out_a,
sel => select_vector(15),
my_out => data
);
b_0 : tristate_32 PORT MAP (
my_in => ram_0_out_b,
sel => select_vector(14),
my_out => data
);
a_1 : tristate_32 PORT MAP (
my_in => ram_1_out_a,
sel => select_vector(13),
my_out => data
);
b_1 : tristate_32 PORT MAP (
my_in => ram_1_out_b,
sel => select_vector(12),
my_out => data
);
a_2 : tristate_32 PORT MAP (
my_in => ram_2_out_a,
sel => select_vector(11),
my_out => data
);
b_2 : tristate_32 PORT MAP (
my_in => ram_2_out_b,
sel => select_vector(10),
my_out => data
);
a_3 : tristate_32 PORT MAP (
my_in => ram_3_out_a,
sel => select_vector(9),
my_out => data
);
b_3 : tristate_32 PORT MAP (
my_in => ram_3_out_b,
sel => select_vector(8),
my_out => data
);
a_4 : tristate_32 PORT MAP (
my_in => ram_4_out_a,
sel => select_vector(7),
my_out => data
);
b_4 : tristate_32 PORT MAP (
my_in => ram_4_out_b,
sel => select_vector(6),
my_out => data
);
a_5 : tristate_32 PORT MAP (
my_in => ram_5_out_a,
sel => select_vector(5),
my_out => data
);
b_5 : tristate_32 PORT MAP (
my_in => ram_5_out_b,
sel => select_vector(4),
my_out => data
);
a_6 : tristate_32 PORT MAP (
my_in => ram_6_out_a,
sel => select_vector(3),
my_out => data
);
b_6 : tristate_32 PORT MAP (
my_in => ram_6_out_b,
sel => select_vector(2),
my_out => data
);
a_7 : tristate_32 PORT MAP (
my_in => ram_7_out_a,
sel => select_vector(1),
my_out => data
);
b_7 : tristate_32 PORT MAP (
my_in => ram_7_out_b,
sel => select_vector(0),
my_out => data
);
resolve_hazard : HAZARD_RESOLVE_global PORT MAP (
select_signal => select_vector,
hazard => hazard,
data => data,
CLK => CLK,
RESET_n => RESET_n,
hazard_advanced => hazard_advanced,
data_out => OUTPUT
);
end; | gpl-2.0 | 828fd14e165249be1418a1f71db6c189 | 0.50389 | 2.964722 | false | false | false | false |
Bourgeoisie/ECE368-RISC16 | 368RISC/ipcore_dir/instruct_blk_mem_gen_v7_3/example_design/instruct_blk_mem_gen_v7_3_exdes.vhd | 1 | 5,074 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: instruct_blk_mem_gen_v7_3_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY instruct_blk_mem_gen_v7_3_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END instruct_blk_mem_gen_v7_3_exdes;
ARCHITECTURE xilinx OF instruct_blk_mem_gen_v7_3_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT instruct_blk_mem_gen_v7_3 IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : instruct_blk_mem_gen_v7_3
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
| mit | b320bc07c2c7979379b24e55ecb8ea1a | 0.56149 | 4.498227 | false | false | false | false |
nulldozer/purisc | Global_memory/MAGIC_global/MAGIC_tb.vhd | 2 | 6,542 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MAGIC_tb is
end;
architecture testing of MAGIC_tb is
component MAGIC
PORT (
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
DATA_OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
C0_STALL : OUT STD_LOGIC;
C1_STALL : OUT STD_LOGIC;
CORE_IDENT : OUT STD_LOGIC
);
end component;
signal ADDRESS_A : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ADDRESS_B : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ADDRESS_C : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ADDRESS_0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ADDRESS_1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ADDRESS_W : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal DATA_TO_W : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_EN : STD_LOGIC := '0';
signal CLK : STD_LOGIC := '1';
signal RESET_n : STD_LOGIC := '0';
signal DATA_OUT_A : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal DATA_OUT_B : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal DATA_OUT_C : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal DATA_OUT_0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal DATA_OUT_1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal C0_STALL : STD_LOGIC;
signal C1_STALL : STD_LOGIC;
signal CORE_IDENT : STD_LOGIC;
constant clk_period : time := 10ns;
begin
uut : MAGIC PORT MAP (
ADDRESS_A,
ADDRESS_B,
ADDRESS_C,
ADDRESS_0,
ADDRESS_1,
ADDRESS_W,
DATA_TO_W,
W_EN,
CLK,
RESET_n,
DATA_OUT_A,
DATA_OUT_B,
DATA_OUT_C,
DATA_OUT_0,
DATA_OUT_1,
C0_STALL,
C1_STALL,
CORE_IDENT
);
clk_process : process begin
CLK <= '1';
wait for clk_period/2;
CLK <= '0';
wait for clk_period/2;
end process;
-- id_process : process begin
-- CORE_ID <= '0';
-- wait for clk_period;
-- CORE_ID <= '1';
-- wait for clk_period;
-- end process;
stim_process : process begin
ADDRESS_A <= "00000000000000000000000000000000";
ADDRESS_B <= "00000000000000000000000000000001";
ADDRESS_C <= "00000000000000000000000000000010";
ADDRESS_0 <= "00000000000000000000000000000011";
ADDRESS_1 <= "00000000000000000000000000000100";
ADDRESS_W <= "00000000000000000000000000000000";
DATA_TO_W <= "00000000000000000000000000000000";
wait for clk_period;
RESET_n <= '1';
W_EN <= '1';
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000001";
DATA_TO_W <= "00000000000000000000000000000001";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000010";
DATA_TO_W <= "00000000000000000000000000000010";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000011";
DATA_TO_W <= "00000000000000000000000000000011";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000100";
DATA_TO_W <= "00000000000000000000000000000100";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000101";
DATA_TO_W <= "00000000000000000000000000000101";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000110";
DATA_TO_W <= "00000000000000000000000000000110";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000111";
DATA_TO_W <= "00000000000000000000000000000111";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001000";
DATA_TO_W <= "00000000000000000000000000001000";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001001";
DATA_TO_W <= "00000000000000000000000000001001";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001010";
DATA_TO_W <= "00000000000000000000000000001010";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001011";
DATA_TO_W <= "00000000000000000000000000001011";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001100";
DATA_TO_W <= "00000000000000000000000000001100";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001101";
DATA_TO_W <= "00000000000000000000000000001101";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001110";
DATA_TO_W <= "00000000000000000000000000001110";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000011000";
DATA_TO_W <= "00000000000000000000000000011000";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000010000";
DATA_TO_W <= "00000000000000000000000000010000";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000100000";
DATA_TO_W <= "00000000000000000000000000100000";
wait for clk_period;
--------------------------
ADDRESS_A <= "00000000000000000000000000000110";
ADDRESS_B <= "00000000000000000000000000001100";
ADDRESS_C <= "00000000000000000000000000000111";
ADDRESS_0 <= "00000000000000000000000000001000";
ADDRESS_1 <= "00000000000000000000000000001001";
W_EN <= '0';
wait for clk_period;
ADDRESS_A <= "00000000000000000000000000001000";
ADDRESS_B <= "00000000000000000000000000000000";
ADDRESS_C <= "00000000000000000000000000010000";
ADDRESS_0 <= "00000000000000000000000000011000";
ADDRESS_1 <= "00000000000000000000000000100000";
wait for clk_period*3;
ADDRESS_A <= "00000000000000000000000000000000";
ADDRESS_B <= "00000000000000000000000000000001";
ADDRESS_C <= "00000000000000000000000000000010";
ADDRESS_0 <= "00000000000000000000000000000011";
ADDRESS_1 <= "00000000000000000000000000000100";
wait for clk_period*2;
ADDRESS_A <= "00000000000000000000000000000000";
ADDRESS_B <= "00000000000000000000000000000000";
ADDRESS_C <= "00000000000000000000000000000000";
ADDRESS_0 <= "00000000000000000000000000000001";
ADDRESS_1 <= "00000000000000000000000000000010";
wait for clk_period*2;
ADDRESS_A <= "00000000000000000000000000000000";
ADDRESS_B <= "00000000000000000000000000000001";
ADDRESS_C <= "00000000000000000000000000000010";
ADDRESS_0 <= "00000000000000000000000000000011";
ADDRESS_1 <= "00000000000000000000000000000100";
wait;
end process;
end; | gpl-2.0 | ef8394a3dae4ef7113fb51be374b378e | 0.698257 | 3.687711 | false | false | false | false |
michaelmiehling/A25_VME_TB | 16x010-00_src/Source/conversions.vhd | 1 | 44,870 | --------------------------------------------------------------------------------
-- File Name: conversions.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1997-2008 Free Model Foundry; http://www.FreeModelFoundry.com
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- This package was originally written by SEVA Technologies, Inc. and donated
-- to the FMF.
-- www.seva.com
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 R. Steele 97 DEC 05 Added header and formatting to SEVA file
-- V1.1 R. Munden 98 NOV 28 Corrected some comments
-- Corrected function b
-- V1.2 R. Munden 01 MAY 27 Corrected function to_nat for weak values
-- and combined into a single file
-- V1.3 M.Radmanovic 03 Aug 18 Added signed conversion function to_int
-- V1.4 M.Radmanovic 03 Nov 10 Added signed conversion function
-- int_to_slv
-- V1.5 R. Munden 04 NOV 11 Added type conversion to t_hex_str
-- V1.6 D. Rheault 07 MAY 21 Corrected int_to_slv for value of 0
-- V1.7 V.Markovic 08 Apr 24 Changed condition for variable int (in
-- function int_to_slv) from > to >=
-- V1.8 R. Munden 08 MAY 21 Fixed default base for x=0 in to_int_str
--
--------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
--------------------------------------------------------------------------------
-- CONVERSION FUNCTION SELECTION TABLES
--------------------------------------------------------------------------------
--
-- FROM TO: std_logic_vector std_logic natural time string
-- -----------------|---------------|---------|---------|---------|-----------
-- std_logic_vector | N/A | N/A | to_nat | combine | see below
-- std_logic | N/A | N/A | to_nat | combine | see below
-- natural | to_slv | to_sl | N/A | to_time | see below
-- integer | to_slv | N/A | N/A | N/A | N/A
-- time | N/A | N/A | to_nat | N/A | to_time_str
-- hex string | h | N/A | h | combine | N/A
-- decimal string | d | N/A | d | combine | N/A
-- octal string | o | N/A | o | combine | N/A
-- binary string | b | N/A | b | combine | N/A
-- -----------------|---------------|---------|---------|---------|-----------
--
-- FROM TO: hex string decimal string octal string binary string
-- -----------------|------------|-------------|------------|----------------
-- std_logic_vector | to_hex_str | to_int_str | to_oct_str | to_bin_str
-- std_logic | N/A | N/A | N/A | to_bin_str
-- natural | to_hex_str | to_int_str | to_oct_str | to_bin_str
-- -----------------|------------|-------------|------------|----------------
--
-- FROM TO: integer
-- -----------------|---------------|
-- std_logic_vector | to_int |
--------------------------------------------------------------------------------
PACKAGE conversions IS
----------------------------------------------------------------------------
-- the conversions in this package are not intended to be synthesizable.
--
-- others functions available
-- fill creates a variable length string of the fill character
--
--
--
-- input parameters of type natural or integer can be in the form:
-- normal -> 8, 99, 4_237
-- base#value# -> 2#0101#, 16#fa4C#, 8#6_734#
-- with exponents(x10) -> 8e4, 16#2e#E4
--
-- input parameters of type string can be in the form:
-- "99", "4_237", "0101", "1010_1010"
--
-- for bit/bit_vector <-> std_logic/std_logic_vector conversions use
-- package std_logic_1164
-- to_bit(std_logic)
-- to_bitvector(std_logic_vector)
-- to_stdlogic(bit)
-- to_stdlogicvector(bit_vector)
--
-- for "synthesizable" signed/unsigned/std_logic_vector/integer
-- conversions use
-- package std_logic_arith
-- conv_integer(signed/unsigned)
-- conv_unsigned(integer/signed,size)
-- conv_signed(integer/unsigned,size)
-- conv_std_logic_vector(integer/signed/unsigned,size)
--
-- for "synthesizable" std_logic_vector -> integer conversions use
-- package std_logic_unsigned/std_logic_signed
-- <these packages are mutually exclusive>
-- conv_integer(std_logic_vector)
-- <except for this conversion, these packages are unnecessary)
-- to minimize compile problems write:
-- use std_logic_unsigned.conv_integer;
-- use std_logic_signed.conv_integer;
--
-- std_logic_vector, signed and unsigned types are "closely related"
-- no type conversion functions are needed, use type casting or qualified
-- expressions
--
-- type1(object of type2) <type casting>
-- type1'(expression of type2) <qualified expression>
--
-- most conversions have 4 parmeters:
-- x : value to be converted
-- rtn_len : size of the return value
-- justify : justify value 'left' or 'right', default is right
-- basespec : print the base of the value - 'yes'/'no', default is yes
--
-- Typical ways to call these functions:
-- simple, all defaults used
-- to_bin_str(x)
-- x will be converted to a string of minimum size with a
-- base specification appended for clarity
-- if x is 10101 then return is b"10101"
--
-- to control size of return string
-- to_hex_str(x,
-- 6)
-- length of string returned will be 6 characters
-- value will be right justified in the field
-- if x is 10101 then return is ....h"15"
-- where '.' represents a blank
-- if 'rtn_len' parm defaults or is set to 0 then
-- return string will always be minimum size
--
-- to left justify and suppress base specification
-- to_int_str(x,
-- 6,
-- justify => left,
-- basespec => yes)
-- length of return string will be 6 characters
-- the base specification will be suppressed
-- if x is 10101 then return is 21....
-- where '.' represents a blank
--
-- other usage notes
--
-- if rtn_len less than or equal to x'length then ignore
-- rtn_len and return string of x'length
-- the 'justify' parm is effectively ignored in this case
--
-- if rtn_len greater than x'length then return string
-- of rtn_len with blanks based on 'justify' parm
--
-- these routines do not handle negative numbers
----------------------------------------------------------------------------
type justify_side is (left, right);
type b_spec is (no , yes);
-- std_logic_vector to binary string
function to_bin_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- std_logic to binary string
function to_bin_str(x : std_logic;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to binary string
function to_bin_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to hex string
function to_hex_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to hex string
function to_hex_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to octal string
function to_oct_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to octal string
function to_oct_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- natural to integer string
function to_int_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to integer string
function to_int_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- time to string
function to_time_str (x : time)
return string;
-- add characters to a string
function fill (fill_char : character := '*';
rtn_len : integer := 1)
return string;
-- usage:
-- fill
-- returns *
-- fill(' ',10)
-- returns .......... when '.' represents a blank
-- fill(lf) or fill(ht)
-- returns line feed character or tab character respectively
-- std_logic_vector to natural
function to_nat (x : std_logic_vector)
return natural;
-- std_logic to natural
function to_nat (x : std_logic)
return natural;
-- time to natural
function to_nat (x : time)
return natural;
-- hex string to std_logic_vector
function h (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or a,A to f,F
-- or x,X,z,Z,u,U,-,w,W, result will be 0
-- decimal string to std_logic_vector
function d (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- octal string to std_logic_vector
function o (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 7 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- binary string to std_logic_vector
function b (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- hex string to natural
function h (x : string)
return natural;
-- if x is other than characters 0 to 9 or a,A to f,F, result will be 0
-- decimal string to natural
function d (x : string)
return natural;
-- if x is other than characters 0 to 9, result will be 0
-- octal string to natural
function o (x : string)
return natural;
-- if x is other than characters 0 to 7, result will be 0
-- binary string to natural
function b (x : string)
return natural;
-- if x is other than characters 0 to 1, result will be 0
-- natural to std_logic_vector
function to_slv (x : natural;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than sizeof(x), result will be truncated on the left
-- see note above regarding possible formats for x
-- integer to std_logic_vector
function int_to_slv (x : integer;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than sizeof(x), result will be truncated on the left
-- see note above regarding possible formats for x
-- natural to std_logic
function to_sl (x : natural)
return std_logic;
-- natural to time
function to_time (x : natural)
return time;
-- see note above regarding possible formats for x
-- std_logic_vector to integer
function to_int (x : std_logic_vector)
return integer;
END conversions;
--
--------------------------------------------------------------------------------
--
PACKAGE BODY conversions IS
-- private declarations for this package
type basetype is (binary, octal, decimal, hex);
function max(x,y: integer) return integer is
begin
if x > y then return x; else return y; end if;
end max;
function min(x,y: integer) return integer is
begin
if x < y then return x; else return y; end if;
end min;
-- consider function sizeof for string/slv/???, return natural
-- function size(len: natural) return natural is
-- begin
-- if len=0 then
-- return 31;
-- else return len;
-- end if;
-- end size;
function nextmultof (x : positive;
size : positive) return positive is
begin
case x mod size is
when 0 => return size * x/size;
when others => return size * (x/size + 1);
end case;
end nextmultof;
function rtn_base (base : basetype) return character is
begin
case base is
when binary => return 'b';
when octal => return 'o';
when decimal => return 'd';
when hex => return 'h';
end case;
end rtn_base;
function format (r : string;
base : basetype;
rtn_len : natural ;
justify : justify_side;
basespec : b_spec) return string is
variable int_rtn_len : integer;
begin
if basespec=yes then
int_rtn_len := rtn_len - 3;
else
int_rtn_len := rtn_len;
end if;
if int_rtn_len <= r'length then
case basespec is
when no => return r ;
when yes => return rtn_base(base) & '"' & r & '"';
end case;
else
case justify is
when left =>
case basespec is
when no =>
return r & fill(' ',int_rtn_len - r'length);
when yes =>
return rtn_base(base) & '"' & r & '"' &
fill(' ',int_rtn_len - r'length);
end case;
when right =>
case basespec is
when no =>
return fill(' ',int_rtn_len - r'length) & r ;
when yes =>
return fill(' ',int_rtn_len - r'length) &
rtn_base(base) & '"' & r & '"';
end case;
end case;
end if;
end format;
-- convert numeric string of any base to natural
function cnvt_base (x : string;
inbase : natural range 2 to 16) return natural is
-- assumes x is an unsigned number string of base 'inbase'
-- values larger than natural'high are not supported
variable r,t : natural := 0;
variable place : positive := 1;
begin
for i in x'reverse_range loop
case x(i) is
when '0' => t := 0;
when '1' => t := 1;
when '2' => t := 2;
when '3' => t := 3;
when '4' => t := 4;
when '5' => t := 5;
when '6' => t := 6;
when '7' => t := 7;
when '8' => t := 8;
when '9' => t := 9;
when 'a'|'A' => t := 10;
when 'b'|'B' => t := 11;
when 'c'|'C' => t := 12;
when 'd'|'D' => t := 13;
when 'e'|'E' => t := 14;
when 'f'|'F' => t := 15;
when '_' => t := 0; -- ignore these characters
place := place / inbase;
when others =>
assert false
report lf &
"CNVT_BASE found input value larger than base: " & lf &
"Input value: " & x(i) &
" Base: " & to_int_str(inbase) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
if t / inbase > 1 then -- invalid value for base
assert false
report lf &
"CNVT_BASE found input value larger than base: " & lf &
"Input value: " & x(i) &
" Base: " & to_int_str(inbase) & lf &
"converting input to integer 0"
severity warning;
return 0;
else
r := r + (t * place);
place := place * inbase;
end if;
end loop;
return r;
end cnvt_base;
function extend (x : std_logic;
len : positive) return std_logic_vector is
variable v : std_logic_vector(1 to len) := (others => x);
begin
return v;
end extend;
-- implementation of public declarations
function to_bin_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : std_logic_vector(1 to x'length):=x;
variable r : string(1 to x'length):=(others=>'$');
begin
for i in int'range loop
r(i to i) := to_bin_str(int(i),basespec=>no);
end loop;
return format (r,binary,rtn_len,justify,basespec);
end to_bin_str;
function to_bin_str(x : std_logic;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable r : string(1 to 1);
begin
case x is
when '0' => r(1) := '0';
when '1' => r(1) := '1';
when 'U' => r(1) := 'U';
when 'X' => r(1) := 'X';
when 'Z' => r(1) := 'Z';
when 'W' => r(1) := 'W';
when 'H' => r(1) := 'H';
when 'L' => r(1) := 'L';
when '-' => r(1) := '-';
end case;
return format (r,binary,rtn_len,justify,basespec);
end to_bin_str;
function to_bin_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 2 to 32 := 32;
variable r : string(2 to 32):=(others=>'$');
begin
if int = 0 then
return format ("0",binary,rtn_len,justify,basespec);
end if;
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & "TO_BIN_STR, shouldn't happen"
severity failure;
return "$";
null;
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 32),binary,rtn_len,justify,basespec);
end to_bin_str;
function to_hex_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
-- will return x'length/4
variable nxt : positive := nextmultof(x'length,4);
variable int : std_logic_vector(1 to nxt):= (others => '0');
variable ptr : positive range 1 to (nxt/4)+1 := 1;
variable r : string(1 to nxt/4):=(others=>'$');
subtype slv4 is std_logic_vector(1 to 4);
variable slv4_val : slv4;
begin
int(nxt-x'length+1 to nxt) := x;
if nxt-x'length > 0 and x(x'left) /= '1' then
int(1 to nxt-x'length) := extend(x(x'left),nxt-x'length);
end if;
for i in int'range loop
next when i rem 4 /= 1;
slv4_val := int(i to i+3);
case slv4_val is
when "0000" => r(ptr) := '0';
when "0001" => r(ptr) := '1';
when "0010" => r(ptr) := '2';
when "0011" => r(ptr) := '3';
when "0100" => r(ptr) := '4';
when "0101" => r(ptr) := '5';
when "0110" => r(ptr) := '6';
when "0111" => r(ptr) := '7';
when "1000" => r(ptr) := '8';
when "1001" => r(ptr) := '9';
when "1010" => r(ptr) := 'A';
when "1011" => r(ptr) := 'B';
when "1100" => r(ptr) := 'C';
when "1101" => r(ptr) := 'D';
when "1110" => r(ptr) := 'E';
when "1111" => r(ptr) := 'F';
when "ZZZZ" => r(ptr) := 'Z';
when "WWWW" => r(ptr) := 'W';
when "LLLL" => r(ptr) := 'L';
when "HHHH" => r(ptr) := 'H';
when "UUUU" => r(ptr) := 'U';
when "XXXX" => r(ptr) := 'X';
when "----" => r(ptr) := '-';
when others =>
assert false
report lf &
"TO_HEX_STR found illegal value: " &
to_bin_str(int(i to i+3)) & lf &
"converting input to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr + 1;
end loop;
return format (r,hex,rtn_len,justify,basespec);
end to_hex_str;
function to_hex_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 20 := 20;
variable r : string(1 to 20):=(others=>'$');
begin
if x=0 then return format ("0",hex,rtn_len,justify,basespec); end if;
while int > 0 loop
case int rem 16 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when 8 => r(ptr) := '8';
when 9 => r(ptr) := '9';
when 10 => r(ptr) := 'A';
when 11 => r(ptr) := 'B';
when 12 => r(ptr) := 'C';
when 13 => r(ptr) := 'D';
when 14 => r(ptr) := 'E';
when 15 => r(ptr) := 'F';
when others =>
assert false report lf & "TO_HEX_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 16;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 20),hex,rtn_len,justify,basespec);
end to_hex_str;
function to_oct_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
-- will return x'length/3
variable nxt : positive := nextmultof(x'length,3);
variable int : std_logic_vector(1 to nxt):= (others => '0');
variable ptr : positive range 1 to (nxt/3)+1 := 1;
variable r : string(1 to nxt/3):=(others=>'$');
subtype slv3 is std_logic_vector(1 to 3);
begin
int(nxt-x'length+1 to nxt) := x;
if nxt-x'length > 0 and x(x'left) /= '1' then
int(1 to nxt-x'length) := extend(x(x'left),nxt-x'length);
end if;
for i in int'range loop
next when i rem 3 /= 1;
case slv3'(int(i to i+2)) is
when "000" => r(ptr) := '0';
when "001" => r(ptr) := '1';
when "010" => r(ptr) := '2';
when "011" => r(ptr) := '3';
when "100" => r(ptr) := '4';
when "101" => r(ptr) := '5';
when "110" => r(ptr) := '6';
when "111" => r(ptr) := '7';
when "ZZZ" => r(ptr) := 'Z';
when "WWW" => r(ptr) := 'W';
when "LLL" => r(ptr) := 'L';
when "HHH" => r(ptr) := 'H';
when "UUU" => r(ptr) := 'U';
when "XXX" => r(ptr) := 'X';
when "---" => r(ptr) := '-';
when others =>
assert false
report lf &
"TO_OCT_STR found illegal value: " &
to_bin_str(int(i to i+2)) & lf &
"converting input to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr + 1;
end loop;
return format (r,octal,rtn_len,justify,basespec);
end to_oct_str;
function to_oct_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 20 := 20;
variable r : string(1 to 20):=(others=>'$');
begin
if x=0 then return format ("0",octal,rtn_len,justify,basespec); end if;
while int > 0 loop
case int rem 8 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when others =>
assert false report lf & "TO_OCT_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 8;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 20),octal,rtn_len,justify,basespec);
end to_oct_str;
function to_int_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 32 := 32;
variable r : string(1 to 32):=(others=>'$');
begin
if x=0 then return format ("0",decimal,rtn_len,justify,basespec);
else
while int > 0 loop
case int rem 10 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when 8 => r(ptr) := '8';
when 9 => r(ptr) := '9';
when others =>
assert false report lf & "TO_INT_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 10;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 32),decimal,rtn_len,justify,basespec);
end if;
end to_int_str;
function to_int_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string is
begin
return to_int_str(to_nat(x),rtn_len,justify,basespec);
end to_int_str;
function to_time_str (x : time)
return string is
begin
return to_int_str(to_nat(x),basespec=>no) & " ns";
end to_time_str;
function fill (fill_char : character := '*';
rtn_len : integer := 1)
return string is
variable r : string(1 to max(rtn_len,1)) := (others => fill_char);
variable len : integer;
begin
if rtn_len < 2 then -- always returns at least 1 fill char
len := 1;
else
len := rtn_len;
end if;
return r(1 to len);
end fill;
function to_nat(x : std_logic_vector) return natural is
-- assumes x is an unsigned number, lsb on right,
-- more than 31 bits are truncated on left
variable t : std_logic_vector(1 to x'length) := x;
variable int : std_logic_vector(1 to 31) := (others => '0');
variable r : natural := 0;
variable place : positive := 1;
begin
if x'length < 32 then
int(max(32-x'length,1) to 31) := t(1 to x'length);
else -- x'length >= 32
int(1 to 31) := t(x'length-30 to x'length);
end if;
for i in int'reverse_range loop
case int(i) is
when '1' | 'H' => r := r + place;
when '0' | 'L' => null;
when others =>
assert false
report lf &
"TO_NAT found illegal value: " & to_bin_str(int(i)) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
exit when i=1;
place := place * 2;
end loop;
return r;
end to_nat;
function to_nat (x : std_logic)
return natural is
begin
case x is
when '0' => return 0 ;
when '1' => return 1 ;
when others =>
assert false
report lf &
"TO_NAT found illegal value: " & to_bin_str(x) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
end to_nat;
function to_nat (x : time)
return natural is
begin
return x / 1 ns;
end to_nat;
function h(x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or a,A to f,F or
-- x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length*4,rtn_len);
variable ptr : integer range -3 to size := size;
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr-3 to ptr) := "0000";
when '1' => r(ptr-3 to ptr) := "0001";
when '2' => r(ptr-3 to ptr) := "0010";
when '3' => r(ptr-3 to ptr) := "0011";
when '4' => r(ptr-3 to ptr) := "0100";
when '5' => r(ptr-3 to ptr) := "0101";
when '6' => r(ptr-3 to ptr) := "0110";
when '7' => r(ptr-3 to ptr) := "0111";
when '8' => r(ptr-3 to ptr) := "1000";
when '9' => r(ptr-3 to ptr) := "1001";
when 'a'|'A' => r(ptr-3 to ptr) := "1010";
when 'b'|'B' => r(ptr-3 to ptr) := "1011";
when 'c'|'C' => r(ptr-3 to ptr) := "1100";
when 'd'|'D' => r(ptr-3 to ptr) := "1101";
when 'e'|'E' => r(ptr-3 to ptr) := "1110";
when 'f'|'F' => r(ptr-3 to ptr) := "1111";
when 'U' => r(ptr-3 to ptr) := "UUUU";
when 'X' => r(ptr-3 to ptr) := "XXXX";
when 'Z' => r(ptr-3 to ptr) := "ZZZZ";
when 'W' => r(ptr-3 to ptr) := "WWWW";
when 'H' => r(ptr-3 to ptr) := "HHHH";
when 'L' => r(ptr-3 to ptr) := "LLLL";
when '-' => r(ptr-3 to ptr) := "----";
when '_' => ptr := ptr + 4;
when others =>
assert false
report lf &
"O conversion found illegal input character: " &
int(i) & lf & "converting character to '----'"
severity warning;
r(ptr-3 to ptr) := "----";
end case;
ptr := ptr - 4;
end loop;
return r(size-rtn_len+1 to size);
end h;
function d (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than binary length of x, result will be truncated on
-- the left
-- if x is other than characters 0 to 9, result will be 0
begin
return to_slv(cnvt_base(x,10),rtn_len);
end d;
function o (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length*3, result will be truncated on the left
-- if x is other than characters 0 to 7 or or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length*3,rtn_len);
variable ptr : integer range -2 to size := size;
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr-2 to ptr) := "000";
when '1' => r(ptr-2 to ptr) := "001";
when '2' => r(ptr-2 to ptr) := "010";
when '3' => r(ptr-2 to ptr) := "011";
when '4' => r(ptr-2 to ptr) := "100";
when '5' => r(ptr-2 to ptr) := "101";
when '6' => r(ptr-2 to ptr) := "110";
when '7' => r(ptr-2 to ptr) := "111";
when 'U' => r(ptr-2 to ptr) := "UUU";
when 'X' => r(ptr-2 to ptr) := "XXX";
when 'Z' => r(ptr-2 to ptr) := "ZZZ";
when 'W' => r(ptr-2 to ptr) := "WWW";
when 'H' => r(ptr-2 to ptr) := "HHH";
when 'L' => r(ptr-2 to ptr) := "LLL";
when '-' => r(ptr-2 to ptr) := "---";
when '_' => ptr := ptr + 3;
when others =>
assert false
report lf &
"O conversion found illegal input character: " &
int(i) & lf & "converting character to '---'"
severity warning;
r(ptr-2 to ptr) := "---";
end case;
ptr := ptr - 3;
end loop;
return r(size-rtn_len+1 to size);
end o;
function b (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length, result will be truncated on the left
-- if x is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length,rtn_len);
variable ptr : integer range 0 to size+1 := size; -- csa
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr) := '0';
when '1' => r(ptr) := '1';
when 'U' => r(ptr) := 'U';
when 'X' => r(ptr) := 'X';
when 'Z' => r(ptr) := 'Z';
when 'W' => r(ptr) := 'W';
when 'H' => r(ptr) := 'H';
when 'L' => r(ptr) := 'L';
when '-' => r(ptr) := '-';
when '_' => ptr := ptr + 1;
when others =>
assert false
report lf &
"B conversion found illegal input character: " &
int(i) & lf & "converting character to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr - 1;
end loop;
return r(size-rtn_len+1 to size);
end b;
function h (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 9
-- a,A to f,F
-- blanks, underscore
begin
return cnvt_base(x,16);
end h;
function d (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 9
-- blanks, underscore
begin
return cnvt_base(x,10);
end d;
function o (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 7
-- blanks, underscore
begin
return cnvt_base(x,8);
end o;
function b (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 1
-- blanks, underscore
begin
return cnvt_base(x,2);
end b;
function to_slv(x : natural;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than sizeof(x), result will be truncated on the left
variable int : natural := x;
variable ptr : positive := 32;
variable r : std_logic_vector(1 to 32) := (others=>'0');
begin
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & "TO_SLV, shouldn't happen"
severity failure;
return "0";
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
return r(33-rtn_len to 32);
end to_slv;
function to_sl(x : natural)
return std_logic is
variable r : std_logic := '0';
begin
case x is
when 0 => null;
when 1 => r := '1';
when others =>
assert false
report lf &
"TO_SL found illegal input character: " &
to_int_str(x) & lf & "converting character to '-'"
severity warning;
return '-';
end case;
return r;
end to_sl;
function int_to_slv(x : integer;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than sizeof(x), result will be truncated on the left
variable int : integer := x;
variable ptr : positive := 32;
variable r : std_logic_vector(1 to 32) := (others=>'0');
begin
if int >= 0 or int = 0 then
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & " shouldn't happen"
severity failure;
return "0";
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
return r(33-rtn_len to 32);
else
int := 2**(rtn_len - 1) + int;
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & " shouldn't happen"
severity failure;
return "0";
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
r(33-rtn_len) := '1';
return r(33-rtn_len to 32);
end if;
end int_to_slv;
function to_time (x: natural) return time is
begin
return x * 1 ns;
end to_time;
function to_int(x : std_logic_vector) return integer is
-- assumes x is an signed number
-- more than 32 bits are truncated on left
variable t : std_logic_vector(x'length downto 1) := x;
variable int : std_logic_vector(32 downto 1) := (others => '0');
variable sign : std_logic := '0';
variable size : integer := 0;
variable inv : boolean := false;
variable r : integer := 0;
variable place : positive := 1;
begin
if x'length < 33 then
sign := t(x'length);
for i in t'reverse_range loop
if sign = '1' then
if inv = true then
t(i) := not(t(i));
elsif t(i) = '1' then
inv := true;
end if;
end if;
size := size +1;
end loop;
inv := false;
for i in 1 to size - 1 loop
case t(i) is
when '1' | 'H' => r := r + place;
when '0' | 'L' => null;
when others =>
assert false
report lf &
" TO_INT found illegal value "
severity warning;
return 0;
end case;
place := place * 2;
end loop;
if sign = '1' THEN
return (- r);
else
return r;
end if;
else -- x'length >= 33
int := t(32 downto 1);
sign := t(32);
for i in 1 to 31 loop
if sign = '1' then
if inv = true then
int(i) := not(int(i));
elsif int(i) = '1' then
inv := true;
end if;
end if;
end loop;
inv := false;
for i in 1 to 31 loop
case int(i) is
when '1' | 'H' => r := r + place;
when '0' | 'L' => null;
when others =>
assert false
report lf &
" TO_INT found illegal value "
severity warning;
return 0;
end case;
place := place * 2;
end loop;
if sign = '1' THEN
return (- r);
else
return r;
end if;
end if;
end to_int;
END conversions;
| gpl-3.0 | 71033cbc7139cf780d67a6fbbb2b7768 | 0.442166 | 3.98066 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/altera_lnsim/ama_coef_reg_ext_function/_primary.vhd | 5 | 7,119 | library verilog;
use verilog.vl_types.all;
entity ama_coef_reg_ext_function is
generic(
width_coef : integer := 1;
width_data_out : vl_notype;
register_clock_0: string := "UNREGISTERED";
register_aclr_0 : string := "NONE";
register_clock_1: string := "UNREGISTERED";
register_aclr_1 : string := "NONE";
register_clock_2: string := "UNREGISTERED";
register_aclr_2 : string := "NONE";
register_clock_3: string := "UNREGISTERED";
register_aclr_3 : string := "NONE";
number_of_multipliers: integer := 1;
port_sign : string := "PORT_UNUSED";
latency : integer := 0;
latency_clock_0 : string := "UNREGISTERED";
latency_aclr_0 : string := "NONE";
latency_clock_1 : string := "UNREGISTERED";
latency_aclr_1 : string := "NONE";
latency_clock_2 : string := "UNREGISTERED";
latency_aclr_2 : string := "NONE";
latency_clock_3 : string := "UNREGISTERED";
latency_aclr_3 : string := "NONE";
width_coef_msb : vl_notype;
width_data_out_msb: vl_notype;
width_coef_ext : vl_notype;
coef0_0 : vl_logic_vector;
coef0_1 : vl_logic_vector;
coef0_2 : vl_logic_vector;
coef0_3 : vl_logic_vector;
coef0_4 : vl_logic_vector;
coef0_5 : vl_logic_vector;
coef0_6 : vl_logic_vector;
coef0_7 : vl_logic_vector;
coef1_0 : vl_logic_vector;
coef1_1 : vl_logic_vector;
coef1_2 : vl_logic_vector;
coef1_3 : vl_logic_vector;
coef1_4 : vl_logic_vector;
coef1_5 : vl_logic_vector;
coef1_6 : vl_logic_vector;
coef1_7 : vl_logic_vector;
coef2_0 : vl_logic_vector;
coef2_1 : vl_logic_vector;
coef2_2 : vl_logic_vector;
coef2_3 : vl_logic_vector;
coef2_4 : vl_logic_vector;
coef2_5 : vl_logic_vector;
coef2_6 : vl_logic_vector;
coef2_7 : vl_logic_vector;
coef3_0 : vl_logic_vector;
coef3_1 : vl_logic_vector;
coef3_2 : vl_logic_vector;
coef3_3 : vl_logic_vector;
coef3_4 : vl_logic_vector;
coef3_5 : vl_logic_vector;
coef3_6 : vl_logic_vector;
coef3_7 : vl_logic_vector
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
sign : in vl_logic;
coefsel0 : in vl_logic_vector(2 downto 0);
coefsel1 : in vl_logic_vector(2 downto 0);
coefsel2 : in vl_logic_vector(2 downto 0);
coefsel3 : in vl_logic_vector(2 downto 0);
data_out_0 : out vl_logic_vector;
data_out_1 : out vl_logic_vector;
data_out_2 : out vl_logic_vector;
data_out_3 : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_coef : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 3;
attribute mti_svvh_generic_type of register_clock_0 : constant is 1;
attribute mti_svvh_generic_type of register_aclr_0 : constant is 1;
attribute mti_svvh_generic_type of register_clock_1 : constant is 1;
attribute mti_svvh_generic_type of register_aclr_1 : constant is 1;
attribute mti_svvh_generic_type of register_clock_2 : constant is 1;
attribute mti_svvh_generic_type of register_aclr_2 : constant is 1;
attribute mti_svvh_generic_type of register_clock_3 : constant is 1;
attribute mti_svvh_generic_type of register_aclr_3 : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of port_sign : constant is 1;
attribute mti_svvh_generic_type of latency : constant is 1;
attribute mti_svvh_generic_type of latency_clock_0 : constant is 1;
attribute mti_svvh_generic_type of latency_aclr_0 : constant is 1;
attribute mti_svvh_generic_type of latency_clock_1 : constant is 1;
attribute mti_svvh_generic_type of latency_aclr_1 : constant is 1;
attribute mti_svvh_generic_type of latency_clock_2 : constant is 1;
attribute mti_svvh_generic_type of latency_aclr_2 : constant is 1;
attribute mti_svvh_generic_type of latency_clock_3 : constant is 1;
attribute mti_svvh_generic_type of latency_aclr_3 : constant is 1;
attribute mti_svvh_generic_type of width_coef_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_coef_ext : constant is 3;
attribute mti_svvh_generic_type of coef0_0 : constant is 4;
attribute mti_svvh_generic_type of coef0_1 : constant is 4;
attribute mti_svvh_generic_type of coef0_2 : constant is 4;
attribute mti_svvh_generic_type of coef0_3 : constant is 4;
attribute mti_svvh_generic_type of coef0_4 : constant is 4;
attribute mti_svvh_generic_type of coef0_5 : constant is 4;
attribute mti_svvh_generic_type of coef0_6 : constant is 4;
attribute mti_svvh_generic_type of coef0_7 : constant is 4;
attribute mti_svvh_generic_type of coef1_0 : constant is 4;
attribute mti_svvh_generic_type of coef1_1 : constant is 4;
attribute mti_svvh_generic_type of coef1_2 : constant is 4;
attribute mti_svvh_generic_type of coef1_3 : constant is 4;
attribute mti_svvh_generic_type of coef1_4 : constant is 4;
attribute mti_svvh_generic_type of coef1_5 : constant is 4;
attribute mti_svvh_generic_type of coef1_6 : constant is 4;
attribute mti_svvh_generic_type of coef1_7 : constant is 4;
attribute mti_svvh_generic_type of coef2_0 : constant is 4;
attribute mti_svvh_generic_type of coef2_1 : constant is 4;
attribute mti_svvh_generic_type of coef2_2 : constant is 4;
attribute mti_svvh_generic_type of coef2_3 : constant is 4;
attribute mti_svvh_generic_type of coef2_4 : constant is 4;
attribute mti_svvh_generic_type of coef2_5 : constant is 4;
attribute mti_svvh_generic_type of coef2_6 : constant is 4;
attribute mti_svvh_generic_type of coef2_7 : constant is 4;
attribute mti_svvh_generic_type of coef3_0 : constant is 4;
attribute mti_svvh_generic_type of coef3_1 : constant is 4;
attribute mti_svvh_generic_type of coef3_2 : constant is 4;
attribute mti_svvh_generic_type of coef3_3 : constant is 4;
attribute mti_svvh_generic_type of coef3_4 : constant is 4;
attribute mti_svvh_generic_type of coef3_5 : constant is 4;
attribute mti_svvh_generic_type of coef3_6 : constant is 4;
attribute mti_svvh_generic_type of coef3_7 : constant is 4;
end ama_coef_reg_ext_function;
| mit | 1c0a0cd912eedd18919bde4f731391ba | 0.616098 | 3.472683 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_multiplexer_GN6ODCX3D4.vhd | 4 | 1,253 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiplexer_GN6ODCX3D4 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 1;
width : positive := 25;
pipeline : natural := 0;
number_inputs : natural := 2);
port(
clock : in std_logic;
aclr : in std_logic;
sel : in std_logic_vector(1 downto 0);
result : out std_logic_vector(24 downto 0);
ena : in std_logic;
user_aclr : in std_logic;
in0 : in std_logic_vector(24 downto 0);
in1 : in std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_multiplexer_GN6ODCX3D4 is
signal data_muxin : std_logic_vector(49 downto 0);
Begin
data_muxin <= in1 & in0 ;
nto1Multiplexeri : alt_dspbuilder_sMuxAltr generic map (
lpm_pipeline =>0,
lpm_size => 2,
lpm_widths => 2 ,
lpm_width => 25 ,
SelOneHot => 1 )
port map (
clock => clock,
ena => ena,
user_aclr => user_aclr,
aclr => aclr,
data => data_muxin,
sel => sel,
result => result);
end architecture;
| mit | d05d7a1c731bcdffb48e0ad12094a33c | 0.639266 | 2.790646 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/reports/Test_Pattern_Generator/Test_Pattern_Generator_example.vhd | 1 | 1,771 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Test_Pattern_Generator_example is
port(
Avalon_ST_Source_startofpacket : out STD_LOGIC;
Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(1 downto 0);
Avalon_ST_Source_valid : out STD_LOGIC;
Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0);
Clock : in STD_LOGIC;
Avalon_ST_Source_ready : in STD_LOGIC;
aclr : in STD_LOGIC;
Avalon_MM_Slave_write : in STD_LOGIC;
Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0);
Avalon_ST_Source_endofpacket : out STD_LOGIC);
end entity;
architecture rtl of Test_Pattern_Generator_example is
component Test_Pattern_Generator
port(
Avalon_ST_Source_startofpacket : out STD_LOGIC;
Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(1 downto 0);
Avalon_ST_Source_valid : out STD_LOGIC;
Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0);
Clock : in STD_LOGIC;
Avalon_ST_Source_ready : in STD_LOGIC;
aclr : in STD_LOGIC;
Avalon_MM_Slave_write : in STD_LOGIC;
Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0);
Avalon_ST_Source_endofpacket : out STD_LOGIC);
end component;
begin
Test_Pattern_Generator_instance :
component Test_Pattern_Generator
port map(
Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket,
Avalon_MM_Slave_address => Avalon_MM_Slave_address,
Avalon_ST_Source_valid => Avalon_ST_Source_valid,
Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata,
Clock => Clock,
Avalon_ST_Source_ready => Avalon_ST_Source_ready,
aclr => aclr,
Avalon_MM_Slave_write => Avalon_MM_Slave_write,
Avalon_ST_Source_data => Avalon_ST_Source_data,
Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket);
end architecture rtl;
| mit | d9479da42975982c612dae30ee2a81a7 | 0.724449 | 3.101576 | false | true | false | false |
freecores/t48 | rtl/vhdl/t48_core_comp_pack-p.vhd | 1 | 3,069 | -------------------------------------------------------------------------------
--
-- $Id: t48_core_comp_pack-p.vhd,v 1.5 2006-06-21 01:03:28 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package t48_core_comp_pack is
component t48_core
generic (
xtal_div_3_g : integer := 1;
register_mnemonic_g : integer := 1;
include_port1_g : integer := 1;
include_port2_g : integer := 1;
include_bus_g : integer := 1;
include_timer_g : integer := 1;
sample_t1_state_g : integer := 4
);
port (
xtal_i : in std_logic;
xtal_en_i : in std_logic;
reset_i : in std_logic;
t0_i : in std_logic;
t0_o : out std_logic;
t0_dir_o : out std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_i : in std_logic_vector( 7 downto 0);
db_o : out std_logic_vector( 7 downto 0);
db_dir_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 7 downto 0);
p2_o : out std_logic_vector( 7 downto 0);
p2l_low_imp_o : out std_logic;
p2h_low_imp_o : out std_logic;
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p1_low_imp_o : out std_logic;
prog_n_o : out std_logic;
clk_i : in std_logic;
en_clk_i : in std_logic;
xtal3_o : out std_logic;
dmem_addr_o : out std_logic_vector( 7 downto 0);
dmem_we_o : out std_logic;
dmem_data_i : in std_logic_vector( 7 downto 0);
dmem_data_o : out std_logic_vector( 7 downto 0);
pmem_addr_o : out std_logic_vector(11 downto 0);
pmem_data_i : in std_logic_vector( 7 downto 0)
);
end component;
component generic_ram_ena
generic (
addr_width_g : integer := 10;
data_width_g : integer := 8
);
port (
clk_i : in std_logic;
a_i : in std_logic_vector(addr_width_g-1 downto 0);
we_i : in std_logic;
ena_i : in std_logic;
d_i : in std_logic_vector(data_width_g-1 downto 0);
d_o : out std_logic_vector(data_width_g-1 downto 0)
);
end component;
component t48_rom
port (
clk_i : in std_logic;
rom_addr_i : in std_logic_vector(9 downto 0);
rom_data_o : out std_logic_vector(7 downto 0)
);
end component;
component t49_rom
port (
clk_i : in std_logic;
rom_addr_i : in std_logic_vector(10 downto 0);
rom_data_o : out std_logic_vector( 7 downto 0)
);
end component;
end t48_core_comp_pack;
| gpl-2.0 | 505743a212148acea4ab83f4d00cd6c1 | 0.492343 | 3.09375 | false | false | false | false |
freecores/t48 | bench/vhdl/if_timing.vhd | 1 | 16,202 | -------------------------------------------------------------------------------
--
-- Interface Timing Checker.
--
-- $Id: if_timing.vhd,v 1.6 2005-11-01 21:20:36 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity if_timing is
port (
xtal_i : in std_logic;
ale_i : in std_logic;
psen_n_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
prog_n_i : in std_logic;
db_bus_i : in std_logic_vector(7 downto 0);
p2_i : in std_logic_vector(7 downto 0)
);
end if_timing;
architecture behav of if_timing is
signal last_xtal_rise_s : time;
signal period_s : time;
signal last_ale_rise_s,
last_ale_fall_s : time;
signal last_psen_n_rise_s,
last_psen_n_fall_s : time;
signal last_rd_n_rise_s,
last_rd_n_fall_s : time;
signal last_wr_n_rise_s,
last_wr_n_fall_s : time;
signal last_prog_n_rise_s,
last_prog_n_fall_s : time;
signal last_bus_change_s,
bus_change_ale_s : time;
signal last_p2_change_s : time;
signal t_CY : time;
begin
t_CY <= 15 * period_s;
-----------------------------------------------------------------------------
-- Check RD
--
rd_check: process (rd_n_i)
begin
case rd_n_i is
-- RD active
when '0' =>
-- tLAFC1: ALE to Control RD
assert (now - last_ale_fall_s) > (t_CY / 5 - 75 ns)
report "Timing violation of tLAFC1 on RD!"
severity error;
-- tAFC1: Addr Float to RD
assert (now - last_bus_change_s) > (t_CY * 2/15 - 40 ns)
report "Timing violation of tAFC1 on RD!"
severity error;
-- RD inactive
when '1' =>
-- tCC1: Control Pulse Width RD
assert (now - last_rd_n_fall_s) > (t_CY / 2 - 200 ns)
report "Timing violation of tCC1 on RD!"
severity error;
when others =>
null;
end case;
end process rd_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Check WR
--
wr_check: process (wr_n_i)
begin
case wr_n_i is
-- WR active
when '0' =>
-- tLAFC1: ALE to Control WR
assert (now - last_ale_fall_s) > (t_CY / 5 - 75 ns)
report "Timing violation of tLAFC1 on WR!"
severity error;
-- tAW: Addr Setup to WR
assert (now - bus_change_ale_s) > (t_CY / 3 - 150 ns)
report "Timing violation of tAW on WR!"
severity error;
-- WR inactive
when '1' =>
-- tCC1: Control Pulse Width WR
assert (now - last_wr_n_fall_s) > (t_CY / 2 - 200 ns)
report "Timing violation of tCC1 on WR!"
severity error;
-- tDW: Data Setup before WR
assert (now - last_bus_change_s) > (t_CY * 13/30 - 200 ns)
report "Timing violation of tDW on WR!"
severity error;
when others =>
null;
end case;
end process wr_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Check BUS
--
bus_check: process (db_bus_i)
begin
-- RD access
-- tAD1 and tRD1 are not checked as they are constraints for the
-- external memory, not the t48!
-- WR access
if wr_n_i = '0' then
-- tDW: Data Hold after WR
assert (now - last_wr_n_rise_s) > (t_CY / 15 - 50 ns)
report "Timing violation of tDW on BUS vs. WR!"
severity error;
end if;
-- Address strobe
if ale_i = '0' then
-- tLA: Addr Hold from ALE
assert (now - last_ale_fall_s) > (t_CY / 15 - 40 ns)
report "Timing violation of tLA on BUS vs. ALE!"
severity error;
end if;
-- PSEN
if psen_n_i = '0' then
-- tRD2: PSEN to Data In
assert (now - last_psen_n_fall_s) < (t_CY * 4/15 - 170 ns)
report "Timing violation of tRD2 on BUS vs. PSEN!"
severity error;
end if;
end process bus_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Check ALE
--
ale_check: process (ale_i)
variable t_CA1 : time;
variable t_AL : time;
begin
case ale_i is
when '0' =>
t_AL := t_CY * 2/15 - 110 ns;
-- tAL: Addr Setup to ALE
assert (now - last_bus_change_s) > t_AL
report "Timing violation of tAL on BUS vs. ALE!"
severity error;
assert (now - last_p2_change_s) > t_AL
report "Timing violation of tAL on P2 vs. ALE!"
severity error;
when '1' =>
-- tCA1: Control to ALE (RD, WR, PROG)
t_CA1 := t_CY / 15 - 40 ns;
assert (now - last_rd_n_rise_s) > t_CA1
report "Timing violation of tCA1 on RD vs. ALE!"
severity error;
assert (now - last_wr_n_rise_s) > t_CA1
report "Timing violation of tCA1 on WR vs. ALE!"
severity error;
assert (now - last_prog_n_rise_s) > t_CA1
report "Timing violation of tCA1 on PROG vs. ALE!"
severity error;
-- tCA2: Control to ALE (PSEN)
assert (now - last_psen_n_rise_s) > (t_CY * 4/15 - 40 ns)
report "Timing violation of tCA2 on PSEN vs. ALE!"
severity error;
-- tPL: Port 2 I/O Setup to ALE
assert (now - last_p2_change_s) > (t_CY * 4/15 - 200 ns)
report "Timing violation of tPL on P2 vs. ALE!"
severity error;
when others =>
null;
end case;
end process ale_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Check P2
--
p2_check: process (p2_i)
begin
case ale_i is
when '0' =>
-- tLA: Addr Hold from ALE
assert ((now - last_ale_fall_s) > (t_CY / 15 - 40 ns)) or
now = 0 ns
report "Timing violation of tLA on P2 vs. ALE!"
severity error;
if last_ale_fall_s < last_ale_rise_s then
-- tPV: Port Output from ALE
assert (now - last_ale_fall_s) < (t_CY * 3/10 + 100 ns)
report "Timing violation of tPV on P2 vs. ALE!"
severity error;
end if;
if prog_n_i = '1' then
-- tPD: Output Data Hold
assert ((now - last_prog_n_rise_s) > (t_CY / 10 - 50 ns)) or
now = 0 ns
report "Timing violation of tPD on P2 vs. PROG!"
severity error;
end if;
when '1' =>
-- tLP: Port 2 I/O to ALE
assert (now - last_ale_rise_s) > (t_CY / 30 - 30 ns)
report "Timing violation of tLP on P2 vs. ALE!"
severity error;
when others =>
null;
end case;
end process p2_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Check PROG
--
prog_check: process (prog_n_i)
begin
case prog_n_i is
when '0' =>
-- tCP: Port Control Setup to PROG'
assert (now - last_p2_change_s) > (t_CY * 2/15 - 80 ns)
report "Timing violation of tCP on P2 vs PROG'!"
severity error;
when '1' =>
-- tPP: PROG Pulse Width
assert (now - last_prog_n_fall_s) > (t_CY * 7/10 - 250 ns)
report "Timing violation of tPP!"
severity error;
-- tDP: Output Data Setup
assert (now - last_p2_change_s) > (t_CY * 2/5 - 150 ns)
report "Timing violation of tDP on P2 vs. PROG!"
severity error;
when others =>
null;
end case;
end process prog_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Check PSEN
--
psen_check: process (psen_n_i)
begin
case psen_n_i is
when '1' =>
-- tCC2: Control Pulse Width PSEN
assert (now - last_psen_n_fall_s) > (t_CY * 2/5 - 200 ns)
report "Timing violation of tCC2 on PSEN!"
severity error;
when '0' =>
-- tLAFC2: ALE to Control PSEN
assert (now - last_ale_fall_s) > (t_CY / 10 - 75 ns)
report "Timing violation of tLAFC2 on PSEN vs. ALE!"
severity error;
when others =>
null;
end case;
end process psen_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Check cycle overlap
--
cycle_overlap_check: process (psen_n_i,
rd_n_i,
wr_n_i)
variable tmp_v : std_logic_vector(2 downto 0);
begin
tmp_v := psen_n_i & rd_n_i & wr_n_i;
case tmp_v is
when "001" |
"010" |
"100" |
"000" =>
assert false
report "Cycle overlap deteced on PSEN, RD and WR!"
severity error;
when others =>
null;
end case;
end process cycle_overlap_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Monitor XTAL
--
xtal_mon: process
begin
last_xtal_rise_s <= 0 ns;
period_s <= 90 ns;
while true loop
wait on xtal_i;
if xtal_i = '1' then
period_s <= now - last_xtal_rise_s;
last_xtal_rise_s <= now;
end if;
end loop;
end process xtal_mon;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Monitor ALE
--
ale_mon: process
begin
last_ale_rise_s <= 0 ns;
last_ale_fall_s <= 0 ns;
while true loop
wait on ale_i;
case ale_i is
when '0' =>
last_ale_fall_s <= now;
when '1' =>
last_ale_rise_s <= now;
when others =>
null;
end case;
end loop;
end process ale_mon;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Monitor PSEN
--
psen_mon: process
begin
last_psen_n_rise_s <= 0 ns;
last_psen_n_fall_s <= 0 ns;
while true loop
wait on psen_n_i;
case psen_n_i is
when '0' =>
last_psen_n_fall_s <= now;
when '1' =>
last_psen_n_rise_s <= now;
when others =>
null;
end case;
end loop;
end process psen_mon;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Monitor RD
--
rd_mon: process
begin
last_rd_n_rise_s <= 0 ns;
last_rd_n_fall_s <= 0 ns;
while true loop
wait on rd_n_i;
case rd_n_i is
when '0' =>
last_rd_n_fall_s <= now;
when '1' =>
last_rd_n_rise_s <= now;
when others =>
null;
end case;
end loop;
end process rd_mon;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Monitor WR
--
wr_mon: process
begin
last_wr_n_rise_s <= 0 ns;
last_wr_n_fall_s <= 0 ns;
while true loop
wait on wr_n_i;
case wr_n_i is
when '0' =>
last_wr_n_fall_s <= now;
when '1' =>
last_wr_n_rise_s <= now;
when others =>
null;
end case;
end loop;
end process wr_mon;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Monitor PROG
--
prog_mon: process
begin
last_prog_n_rise_s <= 0 ns;
last_prog_n_fall_s <= 0 ns;
while true loop
wait on prog_n_i;
case prog_n_i is
when '0' =>
last_prog_n_fall_s <= now;
when '1' =>
last_prog_n_rise_s <= now;
when others =>
null;
end case;
end loop;
end process prog_mon;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Monitor BUS
--
bus_mon: process
begin
last_bus_change_s <= 0 ns;
bus_change_ale_s <= 0 ns;
while true loop
wait on db_bus_i;
last_bus_change_s <= now;
if ale_i = '1' then
bus_change_ale_s <= now;
end if;
end loop;
end process bus_mon;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Monitor P2
--
p2_mon: process
begin
last_p2_change_s <= 0 ns;
while true loop
wait on p2_i;
last_p2_change_s <= now;
end loop;
end process p2_mon;
--
-----------------------------------------------------------------------------
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.5 2004/12/03 19:58:55 arniml
-- add others to case statement
--
-- Revision 1.4 2004/10/25 19:33:13 arniml
-- remove tAW sanity check
-- conflicts with OUTL A, BUS
--
-- Revision 1.3 2004/09/12 00:31:50 arniml
-- add checks for PSEN
--
-- Revision 1.2 2004/04/25 20:40:58 arniml
-- check expander timings
--
-- Revision 1.1 2004/04/25 16:24:10 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 8a0417858d0c112cc31b1ee5669547df | 0.450315 | 4.051513 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_MultAdd.vhd | 12 | 23,128 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAdd is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
nMult : positive := 2;
intended_device_family : string :="Stratix";
use_dedicated_circuitry : natural :=0;
representation : string :="SIGNED";
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
part_sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAdd;
architecture MultAdd_synth of alt_dspbuilder_MultAdd is
function RegStatus(r:registerstructure) return std_logic_vector is
variable res : std_logic_vector(2 downto 0) :=(others=>'0');
begin
if ((r=InputsMultiplierandAdder)or(r=InputsOnly)or(r=InputsandMultiplier)or(r=InputsandAdder)) then
res(0) := '1';
else
res(0) := '0';
end if;
if ((r=InputsMultiplierandAdder) or (r=MultiplierOnly) or (r=InputsandMultiplier) or (r=MultiplierandAdder)) then
res(1) := '1';
else
res(1) := '0';
end if;
if (r=InputsMultiplierandAdder) or
(r=AdderOnly) or
(r=InputsandAdder) or
(r=MultiplierandAdder) then
res(2) := '1';
else
res(2) := '0';
end if;
return res;
end ;
constant regstat : std_logic_vector(2 downto 0) := RegStatus(regstruct);
signal regdat1aa : std_logic_vector (width_a-1 downto 0);
signal regdat1ab : std_logic_vector (width_a-1 downto 0);
signal regdat2aa : std_logic_vector (width_a-1 downto 0);
signal regdat2ab : std_logic_vector (width_a-1 downto 0);
signal regdat3aa : std_logic_vector (width_a-1 downto 0);
signal regdat3ab : std_logic_vector (width_a-1 downto 0);
signal regdat4aa : std_logic_vector (width_a-1 downto 0);
signal regdat4ab : std_logic_vector (width_a-1 downto 0);
signal A1xB : std_logic_vector (2*width_a-1 downto 0);
signal A2xB : std_logic_vector (2*width_a-1 downto 0);
signal A3xB : std_logic_vector (2*width_a-1 downto 0);
signal A4xB : std_logic_vector (2*width_a-1 downto 0);
signal A1xBSExt : std_logic_vector (2*width_a downto 0);
signal A2xBSExt : std_logic_vector (2*width_a downto 0);
signal A3xBSExt : std_logic_vector (2*width_a downto 0);
signal A4xBSExt : std_logic_vector (2*width_a downto 0);
signal FirstAdd : std_logic_vector (2*width_a downto 0);
signal SecondAdd : std_logic_vector (2*width_a downto 0);
signal FirstAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal SecondAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal AllZero : std_logic_vector (2*width_a downto 0);
signal AddAll : std_logic_vector (width_r-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
geab: if use_dedicated_circuitry>0 or representation = "UNSIGNED" generate
U0:alt_dspbuilder_MultAddMF generic map (
width_a => width_a ,
width_r => width_r ,
direction => direction ,
nMult => nMult ,
intended_device_family => intended_device_family,
representation => representation ,
regstruct => regstruct )
port map (
clock => clock ,
ena => ena ,
aclr => aclr_i ,
dat1aa => dat1aa ,
dat1ab => dat1ab ,
dat2aa => dat2aa ,
dat2ab => dat2ab ,
dat3aa => dat3aa ,
dat3ab => dat3ab ,
dat4aa => dat4aa ,
dat4ab => dat4ab ,
result => result );
end generate geab;
gneab: if use_dedicated_circuitry=0 and representation /= "UNSIGNED" generate
AllZero <= (others=>'0');
gc:if (regstruct=NoRegister) generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
A1xB <= regdat1aa*regdat1ab;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xB <= regdat2aa*regdat2ab;
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
result <= AddAll;
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
AddAll <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g3x;
g4x:if (nMult=4) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xB <= regdat4aa*regdat4ab;
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g4x;
end generate gc;
gcr:if (regstruct/=NoRegister)and(regstruct/=InputsMultiplierandAdder) generate
result <= AddAll;
gci:if regstat(0)='0' generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end generate gci;
gcr:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
end generate gcr;
gmc: if regstat(1)='0' generate
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
end generate gmr;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt+A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g3x;
g4x:if (nMult=4) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g4x;
end generate gcr;
gr:if (regstruct=InputsMultiplierandAdder) generate
result <= AddAll;
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g3x;
g4x:if (nMult=4) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g4x;
end generate gr;
end generate gneab;
end MultAdd_synth;
| mit | 1319924cbbcc7b5556c52c1c02f8ee25 | 0.588248 | 2.925743 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_counter_GNZKRIGTBB.vhd | 4 | 1,649 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_counter_GNZKRIGTBB is
generic ( use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "1";
use_sload : string := "true";
use_sclr : string := "false";
use_cout : string := "false";
modulus : integer := 65536;
use_cnt_ena : string := "true";
width : natural := 24;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0");
port(
aclr : in std_logic;
aload : in std_logic;
aset : in std_logic;
cin : in std_logic;
clock : in std_logic;
cnt_ena : in std_logic;
cout : out std_logic;
data : in std_logic_vector((width)-1 downto 0);
direction : in std_logic;
ena : in std_logic;
q : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic;
sload : in std_logic;
sset : in std_logic;
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_counter_GNZKRIGTBB is
Begin
-- DSP Builder Block - Simulink Block "Counter"
Counteri : lpm_counter Generic map (
LPM_WIDTH => 24,
LPM_DIRECTION => "UP",
LPM_MODULUS => 65536,
LPM_AVALUE => "0",
LPM_SVALUE => "1",
LPM_TYPE => "LPM_COUNTER"
)
port map (
data => data,
clock => clock,
cnt_en => cnt_ena,
aclr => aclr,
sload => sload,
q => q);
end architecture;
| mit | bb6fcdcfa1125b243f5832c77401d440 | 0.606428 | 2.852941 | false | false | false | false |
straywarrior/MadeCPUin21days | DataMemoryControl.vhd | 1 | 11,161 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 21:17:00 11/15/2015
-- Design Name:
-- Module Name: DataMemoryControl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DataMemoryControl is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
MemRead : in STD_LOGIC;
MemWrite: in STD_LOGIC;
MemAddr : in STD_LOGIC_VECTOR (15 downto 0);
MemData : in STD_LOGIC_VECTOR (15 downto 0);
MemOut : out STD_LOGIC_VECTOR (15 downto 0);
SerialFinish : out STD_LOGIC;
RAM1Addr : out STD_LOGIC_VECTOR (17 downto 0);
RAM1Data : inout STD_LOGIC_VECTOR (15 downto 0);
RAM1EN : out STD_LOGIC;
RAM1OE : out STD_LOGIC;
RAM1RW : out STD_LOGIC;
Serial_dataready : in STD_LOGIC;
Serial_rdn : out STD_LOGIC;
Serial_tbre : in STD_LOGIC;
Serial_tsre : in STD_LOGIC;
Serial_wrn : out STD_LOGIC;
DLED_Right : out STD_LOGIC_VECTOR (6 downto 0)
);
end DataMemoryControl;
architecture Behavioral of DataMemoryControl is
type state_type is (s0, s1, s2, s3, sr0, sr1, sr2, sr3, sr4, sr5, sr6, sr7, sr8, sr9, sr10, sr11); -- sr1 - sr11 is state for serial write. 50 MHz is too fast for serial port.
signal state : state_type;
begin
RAM1Addr(17 downto 16) <= (others => '0');
RAM1Addr(15 downto 0) <= MemAddr - x"8000";
RAM1Data <=
(others => 'Z') when MemRead = '1' else
MemData when MemWrite = '1' else
(others => 'Z');
process (clk, reset)
begin
if (reset = '0') then
state <= s0;
elsif (clk'event and clk = '1') then
case state is
when s0 => state <= s1;
when s1 => state <= s2;
when s2 => state <= s3;
when s3 =>
if (MemAddr = x"BF00" and MemWrite = '1') then
state <= sr0;
else
state <= s0;
end if;
when sr0 => state <= sr1;
when sr1 => state <= sr2;
when sr2 => state <= sr3;
when sr3 => state <= sr4;
when sr4 => state <= sr5;
when sr5 => state <= sr6;
when sr6 => state <= sr7;
when sr7 => state <= sr8;
when sr8 => state <= sr9;
when sr9 => state <= sr10;
when sr10 => state <= sr11;
when sr11 =>
if (Serial_tbre = '1' and Serial_tsre = '1') then
state <= s0;
else
state <= sr0;
end if;
when others => state <= s0;
end case;
end if;
end process;
process (clk, reset)
begin
if (reset = '0') then
RAM1EN <= '1';
RAM1OE <= '1';
RAM1RW <= '1';
Serial_rdn <= '1';
Serial_wrn <= '1';
SerialFinish <= '1';
elsif (clk'event and clk = '1' and MemAddr >= x"8000" and MemAddr <= x"FFFF") then
case state is
when s0 =>
-- prepare for the control, data and address
RAM1EN <= '1';
RAM1OE <= '1';
RAM1RW <= '1';
SerialFinish <= '1';
Serial_rdn <= '1';
Serial_wrn <= '1';
when s1 =>
if (MemRead = '1') then
case MemAddr is
when x"BF00" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '0';
Serial_rdn <= '0';
Serial_wrn <= '1';
when x"BF01" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '0';
Serial_wrn <= '1';
Serial_rdn <= '1';
when others =>
RAM1EN <= '0';
RAM1OE <= '0';
RAM1RW <= '1';
SerialFinish <= '1'; Serial_rdn <= '1'; Serial_wrn <= '1';
end case;
end if;
if (MemWrite = '1') then
case MemAddr is
when x"BF00" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '0';
Serial_rdn <= '1';
Serial_wrn <= '0';
when x"BF01" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '0'; Serial_wrn <= '1'; Serial_rdn <= '1';
when others =>
RAM1EN <= '0';
RAM1OE <= '1';
RAM1RW <= '0';
SerialFinish <= '1'; Serial_rdn <= '1'; Serial_wrn <= '1';
end case;
end if;
when s2 =>
if (MemRead = '1') then
case MemAddr is
when x"BF00" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '0'; Serial_rdn <= '1'; Serial_wrn <= '1';
when x"BF01" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
MemOut <= (1 => Serial_dataready, 0 => (Serial_tsre and Serial_tbre), others => '0');
SerialFinish <= '1';
when others =>
RAM1EN <= '0';
RAM1OE <= '0';
RAM1RW <= '1';
SerialFinish <= '1';
MemOut <= RAM1Data;
end case;
end if;
if (MemWrite = '1') then
case MemAddr is
when x"BF00" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '0'; Serial_rdn <= '1'; Serial_wrn <= '1';
when x"BF01" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '1'; Serial_wrn <= '1'; Serial_rdn <= '1';
when others =>
RAM1EN <= '0'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '1'; Serial_wrn <= '1'; Serial_rdn <= '1';
end case;
end if;
when s3 =>
if (MemRead = '1') then
case MemAddr is
when x"BF00" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '1';
MemOut <= RAM1Data;
when x"BF01" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '1';
MemOut <= (1 => Serial_dataready, 0 => (Serial_tsre and Serial_tbre), others => '0');
when others =>
RAM1EN <= '0'; RAM1OE <= '0'; RAM1RW <= '1';
SerialFinish <= '1';
MemOut <= RAM1Data;
end case;
end if;
if (MemWrite = '1') then
case MemAddr is
when x"BF00" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when x"BF01" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1'; Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '1';
when others =>
RAM1EN <= '0'; RAM1OE <= '1'; RAM1RW <= '1'; Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '1';
end case;
end if;
when sr0 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr1 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr2 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr3 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr4 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr5 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr6 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr7 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr8 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr9 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr10 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '1';
when sr11 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
Serial_rdn <= '1'; Serial_wrn <= '1';
if (Serial_tsre = '1' and Serial_tbre = '1') then
SerialFinish <= '1';
else
SerialFinish <= '0';
end if;
when others =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '1';
end case;
end if;
end process;
DLED_Right <=
"1111110" when state = s0 else
"0110000" when state = s1 else
"1101101" when state = s2 else
"1111001" when state = s3 else
"0110011" when state = sr0 else
"1011011" when state = sr1 else
"0000000";
end Behavioral;
| gpl-2.0 | d1fd071eeb5abe869f4103516afd5b0b | 0.400681 | 3.998925 | false | false | false | false |
Ttl/bf_cpu | testbenches/cpu_rot13_tb.vhd | 1 | 2,610 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.all;
ENTITY cpu_rot13_tb IS
END cpu_rot13_tb;
ARCHITECTURE behavior OF cpu_rot13_tb IS
signal clk, reset, tx, rx : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
signal uart_tx_req, uart_tx_end, uart_rx_ready : std_logic;
signal uart_tx_data, uart_rx_data : std_logic_vector(7 downto 0);
BEGIN
-- Component Instantiation
uut: entity work.cpu
Generic map ( INSTRUCTIONS => "scripts/rot13.mif"
)
Port map(clk => clk,
reset => reset,
tx => rx,
rx => tx
);
uart1 : entity work.uart
Generic map(
CLK_FREQ => 100,
SER_FREQ => 1000000,
PARITY_BIT => false
)
Port map (
clk => clk,
rst => reset,
rx => rx,
tx => tx,
tx_req => uart_tx_req,
tx_end => uart_tx_end,
tx_data => uart_tx_data,
rx_ready => uart_rx_ready,
rx_data => uart_rx_data
);
-- Print received bytes
uart_process : process
begin
wait until uart_rx_ready = '1';
wait for clk_period;
if to_integer(unsigned(uart_rx_data)) > 31 and to_integer(unsigned(uart_rx_data)) < 127 then
report "Received ASCII: "&character'image(character'val(to_integer(unsigned(uart_rx_data))));
else
report "Received Dec: "&integer'image(to_integer(unsigned(uart_rx_data)));
end if;
end process;
-- Test received bytes
test_process : process
begin
wait until uart_rx_ready = '1';
wait for clk_period;
assert uart_rx_data = x"4E" report "First msg incorrect" severity failure;
wait until uart_rx_ready = '1';
assert false report "Received too many messages" severity failure;
end process;
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Test Bench Statements
tb : PROCESS
BEGIN
reset <= '1';
uart_tx_req <= '0';
wait for 100 ns; -- wait until global set/reset completes
reset <= '0';
-- Send character
uart_tx_req <= '1';
uart_tx_data <= x"41"; -- A
wait for clk_period;
uart_tx_req <= '0';
wait until uart_tx_end = '1';
wait for 1999us;
assert uart_rx_data /= x"4E" report "Completed succesfully" severity failure;
assert false report "Invalid rx_data" severity failure;
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
| lgpl-3.0 | bf2a9e3dec6b468b43a2348cc72b963e | 0.588889 | 3.508065 | false | false | false | false |
freecores/t48 | rtl/vhdl/system/wb_master.vhd | 1 | 8,909 | -------------------------------------------------------------------------------
--
-- The Wishbone master module.
--
-- $Id: wb_master.vhd,v 1.5 2005-06-11 10:16:05 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
--
-- Short description:
-- This design implements a simple Wishbone bus master. It connects to the
-- BUS interface of the T48 uController core.
--
-- The CPU clock is suppressed with en_clk_o to stall the CPU until the
-- acknowledge signal from the peripheral is detected.
--
-- The adr_i input selects between configuration and Wishbone address range:
-- 1 - configuration range
-- 0 - Wishbone range
--
-- When configuration range is selected, two address register are accessible.
-- 000h -> adr1
-- 001h -> adr2
-- These registers can be read and written with movx to their addresses.
--
-- When Wishbone range is selected, all movx generate Wishbone bus cycles
-- (either read or write) at following address:
-- Wishbone address = adr2 & adr1 & address of movx
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.all;
entity t48_wb_master is
port (
xtal_i : in std_logic;
res_i : in std_logic;
en_clk_o : out std_logic;
-- T48 Interface ----------------------------------------------------------
ale_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
adr_i : in std_logic;
db_bus_i : in std_logic_vector( 7 downto 0);
db_bus_o : out std_logic_vector( 7 downto 0);
-- Wishbone Interface -----------------------------------------------------
wb_cyc_o : out std_logic;
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_adr_o : out std_logic_vector(23 downto 0);
wb_ack_i : in std_logic;
wb_dat_i : in std_logic_vector( 7 downto 0);
wb_dat_o : out std_logic_vector( 7 downto 0)
);
end t48_wb_master;
architecture rtl of t48_wb_master is
-----------------------------------------------------------------------------
-- Controller FSM
-----------------------------------------------------------------------------
type state_t is (IDLE, CYC, WAIT_INACT);
signal state_s,
state_q : state_t;
-----------------------------------------------------------------------------
-- Select signals for each range
-----------------------------------------------------------------------------
signal sel_adr1_s,
sel_adr2_s,
sel_wb_s : boolean;
signal wr_s,
rd_s : boolean;
signal adr_q : std_logic_vector(23 downto 0);
signal wb_dat_q : std_logic_vector( 7 downto 0);
begin
-----------------------------------------------------------------------------
-- Select signal generation
-----------------------------------------------------------------------------
sel_adr1_s <= adr_i = '1' and adr_q(word_t'range) = "00000000";
sel_adr2_s <= adr_i = '1' and adr_q(word_t'range) = "00000001";
sel_wb_s <= adr_i = '0';
wr_s <= wr_n_i = '0';
rd_s <= rd_n_i = '0';
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the sequential elements.
--
seq: process (res_i, xtal_i)
begin
if res_i = res_active_c then
adr_q <= (others => '0');
wb_dat_q <= (others => '0');
state_q <= IDLE;
elsif xtal_i'event and xtal_i = clk_active_c then
-- Address register -----------------------------------------------------
-- update lowest address byte
if ale_i = '1' then
adr_q(word_t'range) <= db_bus_i;
end if;
-- set adr1 part
if wr_s and sel_adr1_s then
adr_q(word_t'length*2 - 1 downto word_t'length) <= db_bus_i;
end if;
-- set adr2 part
if wr_s and sel_adr2_s then
adr_q(word_t'length*3 - 1 downto word_t'length*2) <= db_bus_i;
end if;
-- Data from peripheral has to be saved ---------------------------------
if wb_ack_i = '1' then
wb_dat_q <= wb_dat_i;
end if;
-- FSM state ------------------------------------------------------------
state_q <= state_s;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process fsm
--
-- Purpose:
-- Implements the state transitions of the controller FSM.
--
fsm: process (state_q,
wr_s,
rd_s,
sel_wb_s,
wb_ack_i)
begin
-- default assignments
wb_cyc_o <= '0';
wb_stb_o <= '0';
en_clk_o <= '1';
state_s <= IDLE;
case state_q is
-- Idle State: Wait for read or write access ----------------------------
when IDLE =>
if sel_wb_s and (wr_s or rd_s) then
state_s <= CYC;
end if;
-- WB Cycle State: Start Wishbone cycle and wait for ack ----------------
when CYC =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
en_clk_o <= '0';
if wb_ack_i = '1' then
state_s <= WAIT_INACT;
else
state_s <= CYC;
end if;
-- Wait inact State: Wait for end of T48 access -------------------------
when WAIT_INACT =>
if not wr_s and not rd_s then
state_s <= IDLE;
else
state_s <= WAIT_INACT;
end if;
when others =>
null;
end case;
end process fsm;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output multiplexer
-----------------------------------------------------------------------------
db_bus_o <= adr_q(word_t'length*2 - 1 downto word_t'length)
when sel_adr1_s else
adr_q(word_t'length*3 - 1 downto word_t'length*2)
when sel_adr2_s else
wb_dat_q;
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
wb_adr_o <= adr_q;
wb_dat_o <= db_bus_i;
wb_we_o <= '1'
when wr_s and sel_wb_s else
'0';
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2005/05/10 22:36:23 arniml
-- save data from wishbone bus in register bank with wb_ack
-- necessary to hold data from peripheral/memory until it is read by T48
--
-- Revision 1.3 2005/05/08 10:36:07 arniml
-- simplify address range:
-- - configuration range
-- - Wishbone range
--
-- Revision 1.2 2005/05/06 18:54:03 arniml
-- assign default for state_s
--
-- Revision 1.1 2005/05/05 19:49:03 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 4ddd3a6b51ed580dfccc2b475e8d30b4 | 0.492199 | 4.155317 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GN3ODVPHOL.vhd | 4 | 879 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN3ODVPHOL is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN3ODVPHOL is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 + 1 ,
width_inr=> 0,
width_outl=> 16,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture; | mit | 896775e53bd0216aa7e1ae445d24e40f | 0.649602 | 3.09507 | false | false | false | false |
Bourgeoisie/ECE368-RISC16 | 368RISC/ipcore_dir/Instruct_Memory.vhd | 1 | 5,846 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file Instruct_Memory.vhd when simulating
-- the core, Instruct_Memory. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY Instruct_Memory IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END Instruct_Memory;
ARCHITECTURE Instruct_Memory_a OF Instruct_Memory IS
-- synthesis translate_off
COMPONENT wrapped_Instruct_Memory
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_Instruct_Memory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 5,
c_addrb_width => 5,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "Instruct_Memory.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 32,
c_read_depth_b => 32,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 32,
c_write_depth_b => 32,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_Instruct_Memory
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END Instruct_Memory_a;
| mit | e1b97d5c74ec66110c1afdf41fefb27c | 0.538317 | 3.96339 | false | false | false | false |
michel-castan/LILASHOME | doc/index_168.vhd | 1 | 1,453 | --------------------------------------------
-- généré par LILASV4 --
--------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.Numeric_Std.all;
use IEEE.std_logic_unsigned.all;
entity tst_code_logic_Memoire is
port(
adr : IN std_logic_vector(3 downto 0) := "UUUU";
we : IN std_logic := 'U';
clk : IN std_logic := 'U';
din : IN std_logic_vector(7 downto 0) := "UUUUUUUU";
dout : OUT std_logic_vector(7 downto 0) := "UUUUUUUU");
end entity tst_code_logic_Memoire;
architecture a_tst_code_logic_Memoire of tst_code_logic_Memoire is
-- déclaration des variables modules
-- déclaration des signaux internes
type mem_type is array (0 to 16-1) of std_logic_vector(8-1 downto 0);
signal mem : mem_type := (
0 => "11111111",
1 => "11111110",
2 => "11111101",
3 => "11111100",
4 => "11111011",
5 => "11111010",
6 => "11111001",
7 => "11111000",
8 => "11110111",
9 => "11110110",
10 => "11110101",
11 => "11110100",
12 => "11110011",
13 => "11110010",
14 => "11110001",
15 => "11110000",
others => (others => 'U'));
-- déclaration des variables locales
signal ldl1375940957581 : std_logic := '1';
begin
process (clk, we, adr)
begin
if (clk'EVENT and clk='1' and we=ldl1375940957581) then
mem(conv_integer(adr)) <= din;
end if;
dout <= mem(conv_integer(adr));
end process;
end architecture a_tst_code_logic_Memoire;
| apache-2.0 | 4b3a8200cc2fcc4acda7ab33e158ca70 | 0.583967 | 3.027197 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | DSPBuilder_Test_Pattern_Generator_import/StateMachineEditor.vhd | 1 | 4,038 | -- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 13.1.0 Build 162 10/23/2013 SJ Full Version
-- Created on Wed Feb 11 10:17:50 2015
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY StateMachineEditor IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
ready : IN STD_LOGIC := '0';
counter : IN STD_LOGIC_VECTOR(23 DOWNTO 0) := "000000000000000000000000";
data_end : IN STD_LOGIC := '0';
state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END StateMachineEditor;
ARCHITECTURE BEHAVIOR OF StateMachineEditor IS
TYPE type_fstate IS (CTRL,DATA,IDLE);
SIGNAL fstate : type_fstate;
SIGNAL reg_fstate : type_fstate;
BEGIN
PROCESS (clock,reg_fstate)
BEGIN
IF (clock='1' AND clock'event) THEN
fstate <= reg_fstate;
END IF;
END PROCESS;
PROCESS (fstate,reset,ready,counter,data_end)
BEGIN
IF (reset='1') THEN
reg_fstate <= IDLE;
state <= "000";
ELSE
state <= "000";
CASE fstate IS
WHEN CTRL =>
IF (((ready = '0') OR (counter(23 DOWNTO 0) = "000000000000000000000011"))) THEN
reg_fstate <= IDLE;
ELSIF (((ready = '1') AND (counter(23 DOWNTO 0) < "000000000000000000000011"))) THEN
reg_fstate <= CTRL;
-- Inserting 'else' block to prevent latch inference
ELSE
reg_fstate <= CTRL;
END IF;
state <= "001";
WHEN DATA =>
IF (((ready = '0') OR ((ready = '1') AND (data_end = '1')))) THEN
reg_fstate <= IDLE;
ELSIF (((ready = '1') AND (data_end = '0'))) THEN
reg_fstate <= DATA;
-- Inserting 'else' block to prevent latch inference
ELSE
reg_fstate <= DATA;
END IF;
state <= "010";
WHEN IDLE =>
IF (((ready = '1') AND (counter(23 DOWNTO 0) > "000000000000000000000011"))) THEN
reg_fstate <= DATA;
ELSIF (((ready = '1') AND (counter(23 DOWNTO 0) <= "000000000000000000000011"))) THEN
reg_fstate <= CTRL;
ELSIF ((ready = '0')) THEN
reg_fstate <= IDLE;
-- Inserting 'else' block to prevent latch inference
ELSE
reg_fstate <= IDLE;
END IF;
IF ((counter(23 DOWNTO 0) /= "000000000000000000000000")) THEN
state <= "000";
ELSIF ((counter(23 DOWNTO 0) = "000000000000000000000000")) THEN
state <= "100";
-- Inserting 'else' block to prevent latch inference
ELSE
state <= "000";
END IF;
WHEN OTHERS =>
state <= "XXX";
report "Reach undefined state";
END CASE;
END IF;
END PROCESS;
END BEHAVIOR;
| mit | 067dedde300579c0d80df432b5b1be8e | 0.521298 | 4.985185 | false | false | false | false |
nulldozer/purisc | top_level_tb.vhd | 2 | 1,450 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level_tb is
end;
architecture test of top_level_tb is
component top_level
PORT(
--ONLY PHY CONNECTIONS IN TOP LEVEL
CLOCK_50 : IN STD_LOGIC;
SW : IN STD_LOGIC_VECTOR(17 downto 0);
HEX0, HEX1, HEX2, HEX3,
HEX4, HEX5, HEX6, HEX7 : OUT std_logic_vector(6 downto 0)
);
end component;
constant clk_period : time := 20ns;
signal CLOCK_50 : std_logic;
signal SW : std_logic_vector(17 downto 0);
signal HEX0 : std_logic_vector(6 downto 0);
signal HEX1 : std_logic_vector(6 downto 0);
signal HEX2 : std_logic_vector(6 downto 0);
signal HEX3 : std_logic_vector(6 downto 0);
signal HEX4 : std_logic_vector(6 downto 0);
signal HEX5 : std_logic_vector(6 downto 0);
signal HEX6 : std_logic_vector(6 downto 0);
signal HEX7 : std_logic_vector(6 downto 0);
begin
uut : top_level PORT MAP(
CLOCK_50 => CLOCK_50,
SW => SW,
HEX0 => HEX0,
HEX1 => HEX1,
HEX2 => HEX2,
HEX3 => HEX3,
HEX4 => HEX4,
HEX5 => HEX5,
HEX6 => HEX6,
HEX7 => HEX7
);
clk_process : process begin
CLOCK_50 <= '1';
wait for clk_period/2;
CLOCK_50 <= '0';
wait for clk_period/2;
end process;
stim_process : process begin
SW(17) <= '0';
wait for clk_period*2;
SW(17) <= '1';
wait;
end process;
end; | gpl-2.0 | 8b59bfe783064139cdfe77d34739480c | 0.588276 | 2.859961 | false | false | false | false |
straywarrior/MadeCPUin21days | ALU.vhd | 1 | 2,250 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 11:18:33 11/14/2015
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port ( op : in STD_LOGIC_VECTOR (3 downto 0);
A : in STD_LOGIC_VECTOR (15 downto 0);
B : in STD_LOGIC_VECTOR (15 downto 0);
result : out STD_LOGIC_VECTOR (15 downto 0));
end ALU;
architecture Behavioral of ALU is
begin
process (A, B, op)
begin
case op is
when "0000" => --add
result <= A + B;
when "0001" => --sub
result <= A - B;
when "0100" => --AND
result <= A and B;
when "0101" => --OR
result <= A or B;
when "0110" => --XOR
result <= A xor B;
when "0111" => --NOT
result <= not B;
when "1000" => --SLL
result <= TO_STDLOGICVECTOR(TO_BITVECTOR(A) SLL CONV_INTEGER(unsigned(B)));
when "1010" => --SRL
result <= TO_STDLOGICVECTOR(TO_BITVECTOR(A) SRL CONV_INTEGER(unsigned(B)));
when "1011" => --SRA
result <= TO_STDLOGICVECTOR(TO_BITVECTOR(A) SRA CONV_INTEGER(unsigned(B)));
--when "1100" => --ROL
--result <= TO_STDLOGICVECTOR(TO_BITVECTOR(A) ROL CONV_INTEGER(unsigned(B)));
when others =>
result <= A;
end case;
end process;
end Behavioral;
| gpl-2.0 | d6c97c48ed810c60e04c59c8cd67db13 | 0.512889 | 4.105839 | false | false | false | false |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_v_cresample_0_0/sim/tutorial_v_cresample_0_0.vhd | 1 | 8,730 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:v_cresample:4.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY v_cresample_v4_0;
USE v_cresample_v4_0.v_cresample;
ENTITY tutorial_v_cresample_0_0 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tuser : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tuser : OUT STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC
);
END tutorial_v_cresample_0_0;
ARCHITECTURE tutorial_v_cresample_0_0_arch OF tutorial_v_cresample_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_v_cresample_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT v_cresample IS
GENERIC (
C_S_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_S_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
C_S_AXIS_VIDEO_FORMAT : INTEGER;
C_M_AXIS_VIDEO_FORMAT : INTEGER;
C_S_AXI_CLK_FREQ_HZ : INTEGER;
C_HAS_AXI4_LITE : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_HAS_DEBUG : INTEGER;
C_FAMILY : STRING;
C_MAX_COLS : INTEGER;
C_ACTIVE_COLS : INTEGER;
C_ACTIVE_ROWS : INTEGER;
C_CHROMA_PARITY : INTEGER;
C_FIELD_PARITY : INTEGER;
C_INTERLACED : INTEGER;
C_NUM_H_TAPS : INTEGER;
C_NUM_V_TAPS : INTEGER;
C_CONVERT_TYPE : INTEGER;
C_COEF_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
intc_if : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
irq : OUT STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tuser : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tuser : OUT STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT v_cresample;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TUSER";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TLAST";
BEGIN
U0 : v_cresample
GENERIC MAP (
C_S_AXIS_VIDEO_DATA_WIDTH => 8,
C_M_AXIS_VIDEO_DATA_WIDTH => 8,
C_S_AXIS_VIDEO_TDATA_WIDTH => 24,
C_M_AXIS_VIDEO_TDATA_WIDTH => 16,
C_S_AXIS_VIDEO_FORMAT => 1,
C_M_AXIS_VIDEO_FORMAT => 0,
C_S_AXI_CLK_FREQ_HZ => 100000000,
C_HAS_AXI4_LITE => 0,
C_HAS_INTC_IF => 0,
C_HAS_DEBUG => 0,
C_FAMILY => "zynq",
C_MAX_COLS => 1920,
C_ACTIVE_COLS => 1920,
C_ACTIVE_ROWS => 1080,
C_CHROMA_PARITY => 1,
C_FIELD_PARITY => 1,
C_INTERLACED => 0,
C_NUM_H_TAPS => 3,
C_NUM_V_TAPS => 0,
C_CONVERT_TYPE => 2,
C_COEF_WIDTH => 16
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => aresetn,
s_axi_aclk => '0',
s_axi_aclken => '1',
s_axi_aresetn => '1',
s_axis_video_tdata => s_axis_video_tdata,
s_axis_video_tvalid => s_axis_video_tvalid,
s_axis_video_tready => s_axis_video_tready,
s_axis_video_tuser => s_axis_video_tuser,
s_axis_video_tlast => s_axis_video_tlast,
m_axis_video_tdata => m_axis_video_tdata,
m_axis_video_tvalid => m_axis_video_tvalid,
m_axis_video_tready => m_axis_video_tready,
m_axis_video_tuser => m_axis_video_tuser,
m_axis_video_tlast => m_axis_video_tlast,
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
s_axi_arvalid => '0',
s_axi_rready => '0'
);
END tutorial_v_cresample_0_0_arch;
| gpl-2.0 | c15c9d8d670b192011a86da56e6c2755 | 0.669759 | 3.324448 | false | false | false | false |
pc2/PivPav | pivpav/misc/vhdl/test.vhdl | 1 | 36,302 | --------------------------------------------------------------------------------
-- FPAdder_32_32_32_32_32_32_DualSubClose
-- (IntDualSub_35)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- and is distributed under the terms of the GNU Lesser General Public Licence.
-- Authors: Bogdan Pasca (2008)
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
entity FPAdder_32_32_32_32_32_32_DualSubClose is
port ( clk, rst : in std_logic;
X : in std_logic_vector(34 downto 0);
Y : in std_logic_vector(34 downto 0);
RxMy : out std_logic_vector(34 downto 0);
RyMx : out std_logic_vector(34 downto 0) );
end entity;
architecture arch of FPAdder_32_32_32_32_32_32_DualSubClose is
signal X0 : std_logic_vector(29 downto 0);
signal Y0 : std_logic_vector(29 downto 0);
signal X1 : std_logic_vector(4 downto 0);
signal Y1 : std_logic_vector(4 downto 0);
signal xMycin1r0 : std_logic_vector(30 downto 0);
signal xMycin1r0_d : std_logic_vector(30 downto 0);
signal yMxcin1r0 : std_logic_vector(30 downto 0);
signal yMxcin1r0_d : std_logic_vector(30 downto 0);
signal xMyr0 : std_logic_vector(29 downto 0);
signal yMxr0 : std_logic_vector(29 downto 0);
signal xMyr1 : std_logic_vector(4 downto 0);
signal yMxr1 : std_logic_vector(4 downto 0);
signal sX0 : std_logic_vector(29 downto 0);
signal sY0 : std_logic_vector(29 downto 0);
signal cin0 : std_logic;
signal sX1 : std_logic_vector(4 downto 0);
signal sX1_d : std_logic_vector(4 downto 0);
signal sY1 : std_logic_vector(4 downto 0);
signal sY1_d : std_logic_vector(4 downto 0);
begin
X0 <= X(29 downto 0);
Y0 <= Y(29 downto 0);
X1 <= X(34 downto 30);
Y1 <= Y(34 downto 30);
sX0 <= X0;
sY0 <= Y0;
cin0 <= '1';
sX1 <= X1;
sY1 <= Y1;
xMycin1r0 <= ("0" & sX0) + ("0" & not(sY0)) + cin0;
yMxcin1r0 <= ("0" & not(sX0)) + ("0" & sY0) + cin0;
xMyr0 <= xMycin1r0_d(29 downto 0);
xMyr1 <= sX1_d + not(sY1_d) + xMycin1r0_d(30);
yMxr0 <= yMxcin1r0_d(29 downto 0);
yMxr1 <= not(sX1_d) + sY1_d + yMxcin1r0_d(30);
RxMy <= xMyr1 & xMyr0;
RyMx <= yMxr1 & yMxr0;
process(clk) begin
if clk'event and clk = '1' then
xMycin1r0_d <= xMycin1r0;
yMxcin1r0_d <= yMxcin1r0;
sX1_d <= sX1;
sY1_d <= sY1;
end if;
end process;
end architecture;
--------------------------------------------------------------------------------
-- FPAdder_32_32_32_32_32_32_LZCShifter
-- (LZCShifter_34_to_34_counting_64)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- and is distributed under the terms of the GNU Lesser General Public Licence.
-- Authors: Florent de Dinechin, Bogdan Pasca (2007)
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
entity FPAdder_32_32_32_32_32_32_LZCShifter is
port ( clk, rst : in std_logic;
I : in std_logic_vector(33 downto 0);
Count : out std_logic_vector(5 downto 0);
O : out std_logic_vector(33 downto 0) );
end entity;
architecture arch of FPAdder_32_32_32_32_32_32_LZCShifter is
signal level6, level6_d1 : std_logic_vector(33 downto 0);
signal count5, count5_d1, count5_d2, count5_d3, count5_d4, count5_d5, count5_d6 : std_logic;
signal level5, level5_d1 : std_logic_vector(33 downto 0);
signal count4, count4_d1, count4_d2, count4_d3, count4_d4, count4_d5 : std_logic;
signal level4, level4_d1 : std_logic_vector(33 downto 0);
signal count3, count3_d1, count3_d2, count3_d3, count3_d4 : std_logic;
signal level3, level3_d1 : std_logic_vector(33 downto 0);
signal count2, count2_d1, count2_d2, count2_d3 : std_logic;
signal level2, level2_d1 : std_logic_vector(33 downto 0);
signal count1, count1_d1, count1_d2 : std_logic;
signal level1, level1_d1 : std_logic_vector(33 downto 0);
signal count0, count0_d1 : std_logic;
signal level0 : std_logic_vector(33 downto 0);
signal sCount : std_logic_vector(5 downto 0);
begin
process(clk) begin
if clk'event and clk = '1' then
level6_d1 <= level6;
count5_d1 <= count5;
count5_d2 <= count5_d1;
count5_d3 <= count5_d2;
count5_d4 <= count5_d3;
count5_d5 <= count5_d4;
count5_d6 <= count5_d5;
level5_d1 <= level5;
count4_d1 <= count4;
count4_d2 <= count4_d1;
count4_d3 <= count4_d2;
count4_d4 <= count4_d3;
count4_d5 <= count4_d4;
level4_d1 <= level4;
count3_d1 <= count3;
count3_d2 <= count3_d1;
count3_d3 <= count3_d2;
count3_d4 <= count3_d3;
level3_d1 <= level3;
count2_d1 <= count2;
count2_d2 <= count2_d1;
count2_d3 <= count2_d2;
level2_d1 <= level2;
count1_d1 <= count1;
count1_d2 <= count1_d1;
level1_d1 <= level1;
count0_d1 <= count0;
end if;
end process;
level6 <= I ;
count5<= '1' when level6(33 downto 2) = (33 downto 2=>'0') else '0';
----------------Synchro barrier, entering cycle 1----------------
level5<= level6_d1(33 downto 0) when count5_d1='0' else level6_d1(1 downto 0) & (31 downto 0 => '0');
count4<= '1' when level5(33 downto 18) = (33 downto 18=>'0') else '0';
----------------Synchro barrier, entering cycle 2----------------
level4<= level5_d1(33 downto 0) when count4_d1='0' else level5_d1(17 downto 0) & (15 downto 0 => '0');
count3<= '1' when level4(33 downto 26) = (33 downto 26=>'0') else '0';
----------------Synchro barrier, entering cycle 3----------------
level3<= level4_d1(33 downto 0) when count3_d1='0' else level4_d1(25 downto 0) & (7 downto 0 => '0');
count2<= '1' when level3(33 downto 30) = (33 downto 30=>'0') else '0';
----------------Synchro barrier, entering cycle 4----------------
level2<= level3_d1(33 downto 0) when count2_d1='0' else level3_d1(29 downto 0) & (3 downto 0 => '0');
count1<= '1' when level2(33 downto 32) = (33 downto 32=>'0') else '0';
----------------Synchro barrier, entering cycle 5----------------
level1<= level2_d1(33 downto 0) when count1_d1='0' else level2_d1(31 downto 0) & (1 downto 0 => '0');
count0<= '1' when level1(33 downto 33) = (33 downto 33=>'0') else '0';
----------------Synchro barrier, entering cycle 6----------------
level0<= level1_d1(33 downto 0) when count0_d1='0' else level1_d1(32 downto 0) & (0 downto 0 => '0');
O <= level0;
sCount <= count5_d6 & count4_d5 & count3_d4 & count2_d3 & count1_d2 & count0_d1;
Count <= CONV_STD_LOGIC_VECTOR(34,6) when sCount=CONV_STD_LOGIC_VECTOR(63,6)
else sCount;
end architecture;
--------------------------------------------------------------------------------
-- FPAdder_32_32_32_32_32_32_RightShifter
-- (RightShifter_33_by_max_35)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- and is distributed under the terms of the GNU Lesser General Public Licence.
-- Authors: Florent de Dinechin, Bogdan Pasca (2007,2008,2009)
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
entity FPAdder_32_32_32_32_32_32_RightShifter is
port ( clk, rst : in std_logic;
X : in std_logic_vector(32 downto 0);
S : in std_logic_vector(5 downto 0);
R : out std_logic_vector(67 downto 0) );
end entity;
architecture arch of FPAdder_32_32_32_32_32_32_RightShifter is
signal level0 : std_logic_vector(32 downto 0);
signal ps, ps_d1, ps_d2 : std_logic_vector(5 downto 0);
signal level1 : std_logic_vector(33 downto 0);
signal level2, level2_d1 : std_logic_vector(35 downto 0);
signal level3 : std_logic_vector(39 downto 0);
signal level4 : std_logic_vector(47 downto 0);
signal level5, level5_d1 : std_logic_vector(63 downto 0);
signal level6 : std_logic_vector(95 downto 0);
begin
process(clk) begin
if clk'event and clk = '1' then
ps_d1 <= ps;
ps_d2 <= ps_d1;
level2_d1 <= level2;
level5_d1 <= level5;
end if;
end process;
level0<= X;
ps<= S;
level1<= (0 downto 0 => '0') & level0 when ps(0) = '1' else level0 & (0 downto 0 => '0');
level2<= (1 downto 0 => '0') & level1 when ps(1) = '1' else level1 & (1 downto 0 => '0');
----------------Synchro barrier, entering cycle 1----------------
level3<= (3 downto 0 => '0') & level2_d1 when ps_d1(2) = '1' else level2_d1 & (3 downto 0 => '0');
level4<= (7 downto 0 => '0') & level3 when ps_d1(3) = '1' else level3 & (7 downto 0 => '0');
level5<= (15 downto 0 => '0') & level4 when ps_d1(4) = '1' else level4 & (15 downto 0 => '0');
----------------Synchro barrier, entering cycle 2----------------
level6<= (31 downto 0 => '0') & level5_d1 when ps_d2(5) = '1' else level5_d1 & (31 downto 0 => '0');
R <= level6(95 downto 28);
end architecture;
--------------------------------------------------------------------------------
-- FPAdder_32_32_32_32_32_32_fracAddFar
-- (IntAdder_36)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- and is distributed under the terms of the GNU Lesser General Public Licence.
-- Authors: Florent de Dinechin, Bogdan Pasca (2007, 2008)
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
entity FPAdder_32_32_32_32_32_32_fracAddFar is
port ( clk, rst : in std_logic;
X : in std_logic_vector(35 downto 0);
Y : in std_logic_vector(35 downto 0);
Cin : in std_logic;
R : out std_logic_vector(35 downto 0) );
end entity;
architecture arch of FPAdder_32_32_32_32_32_32_fracAddFar is
signal X0 : std_logic_vector(29 downto 0);
signal Y0 : std_logic_vector(29 downto 0);
signal Carry : std_logic;
signal X1 : std_logic_vector(5 downto 0);
signal Y1 : std_logic_vector(5 downto 0);
signal cin1R0 : std_logic_vector(30 downto 0);
signal cin1R0_d : std_logic_vector(30 downto 0);
signal R0 : std_logic_vector(29 downto 0);
signal R1 : std_logic_vector(5 downto 0);
signal sX0 : std_logic_vector(29 downto 0);
signal sY0 : std_logic_vector(29 downto 0);
signal cin0 : std_logic;
signal sX1 : std_logic_vector(5 downto 0);
signal sX1_d : std_logic_vector(5 downto 0);
signal sY1 : std_logic_vector(5 downto 0);
signal sY1_d : std_logic_vector(5 downto 0);
begin
Carry <= Cin;
X0 <= X(29 downto 0);
Y0 <= Y(29 downto 0);
X1 <= X(35 downto 30);
Y1 <= Y(35 downto 30);
sX0 <= X0;
sY0 <= Y0;
cin0 <= Carry;
sX1 <= X1;
sY1 <= Y1;
cin1R0 <= ("0" & sX0) + ("0" & sY0) + cin0;
R0 <= cin1R0_d(29 downto 0);
R1 <= sX1_d + sY1_d + cin1R0_d(30);
R <= R1 & R0;
process(clk) begin
if clk'event and clk = '1' then
cin1R0_d <= cin1R0;
sX1_d <= sX1;
sY1_d <= sY1;
end if;
end process;
end architecture;
--------------------------------------------------------------------------------
-- FPAdder_32_32_32_32_32_32_finalRoundAdd
-- (IntAdder_66)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- and is distributed under the terms of the GNU Lesser General Public Licence.
-- Authors: Florent de Dinechin, Bogdan Pasca (2007, 2008)
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
entity FPAdder_32_32_32_32_32_32_finalRoundAdd is
port ( clk, rst : in std_logic;
X : in std_logic_vector(65 downto 0);
Y : in std_logic_vector(65 downto 0);
Cin : in std_logic;
R : out std_logic_vector(65 downto 0) );
end entity;
architecture arch of FPAdder_32_32_32_32_32_32_finalRoundAdd is
signal X0 : std_logic_vector(29 downto 0);
signal Y0 : std_logic_vector(29 downto 0);
signal Carry : std_logic;
signal X1 : std_logic_vector(28 downto 0);
signal Y1 : std_logic_vector(28 downto 0);
signal X2 : std_logic_vector(6 downto 0);
signal Y2 : std_logic_vector(6 downto 0);
signal cin1R0 : std_logic_vector(30 downto 0);
signal cin1R0_d : std_logic_vector(30 downto 0);
signal cin2R1 : std_logic_vector(29 downto 0);
signal cin2R1_d : std_logic_vector(29 downto 0);
signal R0 : std_logic_vector(29 downto 0);
signal R0_d : std_logic_vector(29 downto 0);
signal R1 : std_logic_vector(28 downto 0);
signal R2 : std_logic_vector(6 downto 0);
signal sX0 : std_logic_vector(29 downto 0);
signal sY0 : std_logic_vector(29 downto 0);
signal cin0 : std_logic;
signal sX1 : std_logic_vector(28 downto 0);
signal sX1_d : std_logic_vector(28 downto 0);
signal sY1 : std_logic_vector(28 downto 0);
signal sY1_d : std_logic_vector(28 downto 0);
signal sX2 : std_logic_vector(6 downto 0);
signal sX2_d : std_logic_vector(6 downto 0);
signal sX2_d_d : std_logic_vector(6 downto 0);
signal sY2 : std_logic_vector(6 downto 0);
signal sY2_d : std_logic_vector(6 downto 0);
signal sY2_d_d : std_logic_vector(6 downto 0);
begin
Carry <= Cin;
X0 <= X(29 downto 0);
Y0 <= Y(29 downto 0);
X1 <= X(58 downto 30);
Y1 <= Y(58 downto 30);
X2 <= X(65 downto 59);
Y2 <= Y(65 downto 59);
sX0 <= X0;
sY0 <= Y0;
cin0 <= Carry;
sX1 <= X1;
sY1 <= Y1;
sX2 <= X2;
sY2 <= Y2;
cin1R0 <= ("0" & sX0) + ("0" & sY0) + cin0;
cin2R1 <= ( "0" & sX1_d) + ( "0" & sY1_d) + cin1R0_d(30);
R0 <= cin1R0_d(29 downto 0);
R1 <= cin2R1_d(28 downto 0);
R2 <= sX2_d_d + sY2_d_d + cin2R1_d(29);
R <= R2 & R1 & R0_d;
process(clk) begin
if clk'event and clk = '1' then
cin1R0_d <= cin1R0;
cin2R1_d <= cin2R1;
R0_d <= R0;
sX1_d <= sX1;
sY1_d <= sY1;
sX2_d <= sX2;
sX2_d_d <= sX2_d;
sY2_d <= sY2;
sY2_d_d <= sY2_d;
end if;
end process;
end architecture;
--------------------------------------------------------------------------------
-- FPAdder_32_32_32_32_32_32
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- and is distributed under the terms of the GNU Lesser General Public Licence.
-- Authors: Bogdan Pasca, Florent de Dinechin (2008)
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
entity FPAdder_32_32_32_32_32_32 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(32+32+2 downto 0);
Y : in std_logic_vector(32+32+2 downto 0);
R : out std_logic_vector(32+32+2 downto 0) );
end entity;
architecture arch of FPAdder_32_32_32_32_32_32 is
component FPAdder_32_32_32_32_32_32_DualSubClose is
port ( clk, rst : in std_logic;
X : in std_logic_vector(34 downto 0);
Y : in std_logic_vector(34 downto 0);
RxMy : out std_logic_vector(34 downto 0);
RyMx : out std_logic_vector(34 downto 0) );
end component;
component FPAdder_32_32_32_32_32_32_LZCShifter is
port ( clk, rst : in std_logic;
I : in std_logic_vector(33 downto 0);
Count : out std_logic_vector(5 downto 0);
O : out std_logic_vector(33 downto 0) );
end component;
component FPAdder_32_32_32_32_32_32_RightShifter is
port ( clk, rst : in std_logic;
X : in std_logic_vector(32 downto 0);
S : in std_logic_vector(5 downto 0);
R : out std_logic_vector(67 downto 0) );
end component;
component FPAdder_32_32_32_32_32_32_finalRoundAdd is
port ( clk, rst : in std_logic;
X : in std_logic_vector(65 downto 0);
Y : in std_logic_vector(65 downto 0);
Cin : in std_logic;
R : out std_logic_vector(65 downto 0) );
end component;
component FPAdder_32_32_32_32_32_32_fracAddFar is
port ( clk, rst : in std_logic;
X : in std_logic_vector(35 downto 0);
Y : in std_logic_vector(35 downto 0);
Cin : in std_logic;
R : out std_logic_vector(35 downto 0) );
end component;
signal inX : std_logic_vector(66 downto 0);
signal inY : std_logic_vector(66 downto 0);
signal exceptionXSuperiorY : std_logic;
signal exceptionXEqualY : std_logic;
signal signedExponentX : std_logic_vector(32 downto 0);
signal signedExponentY : std_logic_vector(32 downto 0);
signal exponentDifferenceXY : std_logic_vector(32 downto 0);
signal exponentDifferenceYX : std_logic_vector(31 downto 0);
signal swap : std_logic;
signal newX, newX_d1, newX_d2, newX_d3, newX_d4, newX_d5, newX_d6, newX_d7, newX_d8, newX_d9, newX_d10, newX_d11, newX_d12, newX_d13, newX_d14 : std_logic_vector(66 downto 0);
signal newY, newY_d1 : std_logic_vector(66 downto 0);
signal exponentDifference, exponentDifference_d1 : std_logic_vector(31 downto 0);
signal shiftedOut : std_logic;
signal shiftVal, shiftVal_d1 : std_logic_vector(5 downto 0);
signal EffSub, EffSub_d1, EffSub_d2, EffSub_d3, EffSub_d4, EffSub_d5, EffSub_d6, EffSub_d7, EffSub_d8, EffSub_d9, EffSub_d10, EffSub_d11, EffSub_d12, EffSub_d13 : std_logic;
signal selectClosePath, selectClosePath_d1, selectClosePath_d2, selectClosePath_d3, selectClosePath_d4, selectClosePath_d5, selectClosePath_d6, selectClosePath_d7, selectClosePath_d8, selectClosePath_d9, selectClosePath_d10 : std_logic;
signal sdExnXY, sdExnXY_d1, sdExnXY_d2, sdExnXY_d3, sdExnXY_d4, sdExnXY_d5, sdExnXY_d6, sdExnXY_d7, sdExnXY_d8, sdExnXY_d9, sdExnXY_d10, sdExnXY_d11, sdExnXY_d12, sdExnXY_d13 : std_logic_vector(3 downto 0);
signal pipeSignY, pipeSignY_d1, pipeSignY_d2, pipeSignY_d3, pipeSignY_d4, pipeSignY_d5, pipeSignY_d6, pipeSignY_d7, pipeSignY_d8, pipeSignY_d9, pipeSignY_d10, pipeSignY_d11, pipeSignY_d12, pipeSignY_d13 : std_logic;
signal fracXClose1 : std_logic_vector(34 downto 0);
signal fracYClose1 : std_logic_vector(34 downto 0);
signal fracRClosexMy, fracRClosexMy_d1 : std_logic_vector(34 downto 0);
signal fracRCloseyMx, fracRCloseyMx_d1 : std_logic_vector(34 downto 0);
signal fracSignClose : std_logic;
signal fracRClose1 : std_logic_vector(33 downto 0);
signal resSign, resSign_d1, resSign_d2, resSign_d3, resSign_d4, resSign_d5, resSign_d6, resSign_d7, resSign_d8, resSign_d9, resSign_d10, resSign_d11 : std_logic;
signal nZerosNew, nZerosNew_d1 : std_logic_vector(5 downto 0);
signal shiftedFrac, shiftedFrac_d1, shiftedFrac_d2 : std_logic_vector(33 downto 0);
signal roundClose0, roundClose0_d1 : std_logic;
signal resultCloseIsZero0, resultCloseIsZero0_d1 : std_logic;
signal exponentResultClose, exponentResultClose_d1 : std_logic_vector(33 downto 0);
signal resultBeforeRoundClose : std_logic_vector(65 downto 0);
signal roundClose : std_logic;
signal resultCloseIsZero : std_logic;
signal fracNewY : std_logic_vector(32 downto 0);
signal shiftedFracY, shiftedFracY_d1, shiftedFracY_d2 : std_logic_vector(67 downto 0);
signal sticky, sticky_d1, sticky_d2, sticky_d3 : std_logic;
signal fracYfar : std_logic_vector(35 downto 0);
signal fracYfarXorOp : std_logic_vector(35 downto 0);
signal fracXfar : std_logic_vector(35 downto 0);
signal cInAddFar : std_logic;
signal fracResultfar0, fracResultfar0_d1 : std_logic_vector(35 downto 0);
signal fracResultFarNormStage : std_logic_vector(35 downto 0);
signal fracLeadingBits : std_logic_vector(1 downto 0);
signal fracResultFar1, fracResultFar1_d1 : std_logic_vector(31 downto 0);
signal fracResultRoundBit : std_logic;
signal fracResultStickyBit : std_logic;
signal roundFar1, roundFar1_d1 : std_logic;
signal expOperationSel : std_logic_vector(1 downto 0);
signal exponentUpdate : std_logic_vector(33 downto 0);
signal exponentResultfar0 : std_logic_vector(33 downto 0);
signal exponentResultFar1, exponentResultFar1_d1 : std_logic_vector(33 downto 0);
signal resultBeforeRoundFar, resultBeforeRoundFar_d1, resultBeforeRoundFar_d2, resultBeforeRoundFar_d3 : std_logic_vector(65 downto 0);
signal roundFar, roundFar_d1, roundFar_d2, roundFar_d3 : std_logic;
signal syncClose : std_logic;
signal resultBeforeRound : std_logic_vector(65 downto 0);
signal round : std_logic;
signal zeroFromClose, zeroFromClose_d1, zeroFromClose_d2, zeroFromClose_d3 : std_logic;
signal resultRounded, resultRounded_d1 : std_logic_vector(65 downto 0);
signal syncEffSub : std_logic;
signal syncX : std_logic_vector(66 downto 0);
signal syncSignY : std_logic;
signal syncResSign : std_logic;
signal UnderflowOverflow : std_logic_vector(1 downto 0);
signal resultNoExn : std_logic_vector(66 downto 0);
signal syncExnXY : std_logic_vector(3 downto 0);
signal exnR : std_logic_vector(1 downto 0);
signal sgnR : std_logic;
signal expsigR : std_logic_vector(63 downto 0);
begin
process(clk) begin
if clk'event and clk = '1' then
newX_d1 <= newX;
newX_d2 <= newX_d1;
newX_d3 <= newX_d2;
newX_d4 <= newX_d3;
newX_d5 <= newX_d4;
newX_d6 <= newX_d5;
newX_d7 <= newX_d6;
newX_d8 <= newX_d7;
newX_d9 <= newX_d8;
newX_d10 <= newX_d9;
newX_d11 <= newX_d10;
newX_d12 <= newX_d11;
newX_d13 <= newX_d12;
newX_d14 <= newX_d13;
newY_d1 <= newY;
exponentDifference_d1 <= exponentDifference;
shiftVal_d1 <= shiftVal;
EffSub_d1 <= EffSub;
EffSub_d2 <= EffSub_d1;
EffSub_d3 <= EffSub_d2;
EffSub_d4 <= EffSub_d3;
EffSub_d5 <= EffSub_d4;
EffSub_d6 <= EffSub_d5;
EffSub_d7 <= EffSub_d6;
EffSub_d8 <= EffSub_d7;
EffSub_d9 <= EffSub_d8;
EffSub_d10 <= EffSub_d9;
EffSub_d11 <= EffSub_d10;
EffSub_d12 <= EffSub_d11;
EffSub_d13 <= EffSub_d12;
selectClosePath_d1 <= selectClosePath;
selectClosePath_d2 <= selectClosePath_d1;
selectClosePath_d3 <= selectClosePath_d2;
selectClosePath_d4 <= selectClosePath_d3;
selectClosePath_d5 <= selectClosePath_d4;
selectClosePath_d6 <= selectClosePath_d5;
selectClosePath_d7 <= selectClosePath_d6;
selectClosePath_d8 <= selectClosePath_d7;
selectClosePath_d9 <= selectClosePath_d8;
selectClosePath_d10 <= selectClosePath_d9;
sdExnXY_d1 <= sdExnXY;
sdExnXY_d2 <= sdExnXY_d1;
sdExnXY_d3 <= sdExnXY_d2;
sdExnXY_d4 <= sdExnXY_d3;
sdExnXY_d5 <= sdExnXY_d4;
sdExnXY_d6 <= sdExnXY_d5;
sdExnXY_d7 <= sdExnXY_d6;
sdExnXY_d8 <= sdExnXY_d7;
sdExnXY_d9 <= sdExnXY_d8;
sdExnXY_d10 <= sdExnXY_d9;
sdExnXY_d11 <= sdExnXY_d10;
sdExnXY_d12 <= sdExnXY_d11;
sdExnXY_d13 <= sdExnXY_d12;
pipeSignY_d1 <= pipeSignY;
pipeSignY_d2 <= pipeSignY_d1;
pipeSignY_d3 <= pipeSignY_d2;
pipeSignY_d4 <= pipeSignY_d3;
pipeSignY_d5 <= pipeSignY_d4;
pipeSignY_d6 <= pipeSignY_d5;
pipeSignY_d7 <= pipeSignY_d6;
pipeSignY_d8 <= pipeSignY_d7;
pipeSignY_d9 <= pipeSignY_d8;
pipeSignY_d10 <= pipeSignY_d9;
pipeSignY_d11 <= pipeSignY_d10;
pipeSignY_d12 <= pipeSignY_d11;
pipeSignY_d13 <= pipeSignY_d12;
fracRClosexMy_d1 <= fracRClosexMy;
fracRCloseyMx_d1 <= fracRCloseyMx;
resSign_d1 <= resSign;
resSign_d2 <= resSign_d1;
resSign_d3 <= resSign_d2;
resSign_d4 <= resSign_d3;
resSign_d5 <= resSign_d4;
resSign_d6 <= resSign_d5;
resSign_d7 <= resSign_d6;
resSign_d8 <= resSign_d7;
resSign_d9 <= resSign_d8;
resSign_d10 <= resSign_d9;
resSign_d11 <= resSign_d10;
nZerosNew_d1 <= nZerosNew;
shiftedFrac_d1 <= shiftedFrac;
shiftedFrac_d2 <= shiftedFrac_d1;
roundClose0_d1 <= roundClose0;
resultCloseIsZero0_d1 <= resultCloseIsZero0;
exponentResultClose_d1 <= exponentResultClose;
shiftedFracY_d1 <= shiftedFracY;
shiftedFracY_d2 <= shiftedFracY_d1;
sticky_d1 <= sticky;
sticky_d2 <= sticky_d1;
sticky_d3 <= sticky_d2;
fracResultfar0_d1 <= fracResultfar0;
fracResultFar1_d1 <= fracResultFar1;
roundFar1_d1 <= roundFar1;
exponentResultFar1_d1 <= exponentResultFar1;
resultBeforeRoundFar_d1 <= resultBeforeRoundFar;
resultBeforeRoundFar_d2 <= resultBeforeRoundFar_d1;
resultBeforeRoundFar_d3 <= resultBeforeRoundFar_d2;
roundFar_d1 <= roundFar;
roundFar_d2 <= roundFar_d1;
roundFar_d3 <= roundFar_d2;
zeroFromClose_d1 <= zeroFromClose;
zeroFromClose_d2 <= zeroFromClose_d1;
zeroFromClose_d3 <= zeroFromClose_d2;
resultRounded_d1 <= resultRounded;
end if;
end process;
-- Exponent difference and swap --
inX <= X;
inY <= Y;
exceptionXSuperiorY <= '1' when inX(66 downto 65) >= inY(66 downto 65) else '0';
exceptionXEqualY <= '1' when inX(66 downto 65) = inY(66 downto 65) else '0';
signedExponentX <= "0" & inX(63 downto 32);
signedExponentY <= "0" & inY(63 downto 32);
exponentDifferenceXY <= signedExponentX - signedExponentY ;
exponentDifferenceYX <= signedExponentY(31 downto 0) - signedExponentX(31 downto 0);
swap <= (exceptionXEqualY and exponentDifferenceXY(32)) or (not(exceptionXSuperiorY));
newX <= inY when swap = '1' else inX;
newY <= inX when swap = '1' else inY;
exponentDifference <= exponentDifferenceYX when swap = '1' else exponentDifferenceXY(31 downto 0);
shiftedOut <= exponentDifference(31) or exponentDifference(30) or exponentDifference(29) or exponentDifference(28) or exponentDifference(27) or exponentDifference(26) or exponentDifference(25) or exponentDifference(24) or exponentDifference(23) or exponentDifference(22) or exponentDifference(21) or exponentDifference(20) or exponentDifference(19) or exponentDifference(18) or exponentDifference(17) or exponentDifference(16) or exponentDifference(15) or exponentDifference(14) or exponentDifference(13) or exponentDifference(12) or exponentDifference(11) or exponentDifference(10) or exponentDifference(9) or exponentDifference(8) or exponentDifference(7) or exponentDifference(6);
shiftVal <= exponentDifference(5 downto 0) when shiftedOut='0'
else CONV_STD_LOGIC_VECTOR(35,6) ;
----------------Synchro barrier, entering cycle 1----------------
EffSub <= newX_d1(64) xor newY_d1(64);
selectClosePath <= EffSub when exponentDifference_d1(31 downto 1) = (31 downto 1 => '0') else '0';
sdExnXY <= newX_d1(66 downto 65) & newY_d1(66 downto 65);
pipeSignY <= newY_d1(64);
-- Close Path --
fracXClose1 <= "01" & newX_d1(31 downto 0) & '0';
with exponentDifference_d1(0) select
fracYClose1 <= "01" & newY_d1(31 downto 0) & '0' when '0',
"001" & newY_d1(31 downto 0) when others;
DualSubO: FPAdder_32_32_32_32_32_32_DualSubClose -- pipelineDepth=1
port map ( clk => clk,
rst => rst,
RxMy => fracRClosexMy,
RyMx => fracRCloseyMx,
X => fracXClose1,
Y => fracYClose1);
----------------Synchro barrier, entering cycle 2----------------
----------------Synchro barrier, entering cycle 3----------------
fracSignClose <= fracRClosexMy_d1(34);
fracRClose1 <= fracRClosexMy_d1(33 downto 0) when fracSignClose='0' else fracRCloseyMx_d1(33 downto 0);
resSign <= '0' when selectClosePath_d2='1' and fracRClose1 = (33 downto 0 => '0') else
newX_d3(64) xor (selectClosePath_d2 and fracSignClose);
LZC_component: FPAdder_32_32_32_32_32_32_LZCShifter -- pipelineDepth=6
port map ( clk => clk,
rst => rst,
Count => nZerosNew,
I => fracRClose1,
O => shiftedFrac);
----------------Synchro barrier, entering cycle 9----------------
----------------Synchro barrier, entering cycle 10----------------
roundClose0 <= shiftedFrac_d1(0) and shiftedFrac_d1(1);
resultCloseIsZero0 <= '1' when nZerosNew_d1 = CONV_STD_LOGIC_VECTOR(34, 6) else '0';
exponentResultClose <= ("00" & newX_d10(63 downto 32)) - (CONV_STD_LOGIC_VECTOR(0,28) & nZerosNew_d1);
----------------Synchro barrier, entering cycle 11----------------
resultBeforeRoundClose <= exponentResultClose_d1(33 downto 0) & shiftedFrac_d2(32 downto 1);
roundClose <= roundClose0_d1;
resultCloseIsZero <= resultCloseIsZero0_d1;
-- Far Path --
fracNewY <= '1' & newY_d1(31 downto 0);
RightShifterComponent: FPAdder_32_32_32_32_32_32_RightShifter -- pipelineDepth=2
port map ( clk => clk,
rst => rst,
R => shiftedFracY,
S => shiftVal_d1,
X => fracNewY);
----------------Synchro barrier, entering cycle 3----------------
----------------Synchro barrier, entering cycle 4----------------
sticky <= '0' when (shiftedFracY_d1(32 downto 0)=CONV_STD_LOGIC_VECTOR(0,32)) else '1';
----------------Synchro barrier, entering cycle 5----------------
fracYfar <= "0" & shiftedFracY_d2(67 downto 33);
fracYfarXorOp <= fracYfar xor (35 downto 0 => EffSub_d4);
fracXfar <= "01" & (newX_d5(31 downto 0)) & "00";
cInAddFar <= EffSub_d4 and not sticky_d1;
fracAdderFar: FPAdder_32_32_32_32_32_32_fracAddFar -- pipelineDepth=1
port map ( clk => clk,
rst => rst,
Cin => cInAddFar,
R => fracResultfar0,
X => fracXfar,
Y => fracYfarXorOp);
----------------Synchro barrier, entering cycle 6----------------
----------------Synchro barrier, entering cycle 7----------------
-- 2-bit normalisation
fracResultFarNormStage <= fracResultfar0_d1;
fracLeadingBits <= fracResultFarNormStage(35 downto 34) ;
fracResultFar1 <=
fracResultFarNormStage(32 downto 1) when fracLeadingBits = "00"
else fracResultFarNormStage(33 downto 2) when fracLeadingBits = "01"
else fracResultFarNormStage(34 downto 3);
fracResultRoundBit <=
fracResultFarNormStage(0) when fracLeadingBits = "00"
else fracResultFarNormStage(1) when fracLeadingBits = "01"
else fracResultFarNormStage(2) ;
fracResultStickyBit <=
sticky_d3 when fracLeadingBits = "00"
else fracResultFarNormStage(0) or sticky_d3 when fracLeadingBits = "01"
else fracResultFarNormStage(1) or fracResultFarNormStage(0) or sticky_d3;
roundFar1 <= fracResultRoundBit and (fracResultStickyBit or fracResultFar1(0));
expOperationSel <= "11" when fracLeadingBits = "00" -- add -1 to exponent
else "00" when fracLeadingBits = "01" -- add 0
else "01"; -- add 1
exponentUpdate <= (33 downto 1 => expOperationSel(1)) & expOperationSel(0);
exponentResultfar0<="00" & (newX_d7(63 downto 32));
exponentResultFar1 <= exponentResultfar0 + exponentUpdate;
----------------Synchro barrier, entering cycle 8----------------
resultBeforeRoundFar <= exponentResultFar1_d1 & fracResultFar1_d1;
roundFar <= roundFar1_d1;
-- Synchronization of both paths --
----------------Synchro barrier, entering cycle 11----------------
syncClose <= selectClosePath_d10;
with syncClose select
resultBeforeRound <= resultBeforeRoundClose when '1',
resultBeforeRoundFar_d3 when others;
with syncClose select
round <= roundClose when '1',
roundFar_d3 when others;
zeroFromClose <= syncClose and resultCloseIsZero;
-- Rounding --
finalRoundAdder: FPAdder_32_32_32_32_32_32_finalRoundAdd -- pipelineDepth=2
port map ( clk => clk,
rst => rst,
Cin => round,
R => resultRounded,
X => resultBeforeRound,
Y => (65 downto 0 => '0') );
----------------Synchro barrier, entering cycle 13----------------
----------------Synchro barrier, entering cycle 14----------------
syncEffSub <= EffSub_d13;
syncX <= newX_d14;
syncSignY <= pipeSignY_d13;
syncResSign <= resSign_d11;
UnderflowOverflow <= resultRounded_d1(65 downto 64);
with UnderflowOverflow select
resultNoExn(66 downto 65) <= (not zeroFromClose_d3) & "0" when "01", -- overflow
"00" when "10" | "11", -- underflow
"0" & not zeroFromClose_d3 when others; -- normal
resultNoExn(64 downto 0) <= syncResSign & resultRounded_d1(63 downto 0);
syncExnXY <= sdExnXY_d13;
-- Exception bits of the result
with syncExnXY select -- remember that ExnX > ExnY
exnR <= resultNoExn(66 downto 65) when "0101",
"1" & syncEffSub when "1010",
"11" when "1110",
syncExnXY(3 downto 2) when others;
-- Sign bit of the result
with syncExnXY select
sgnR <= resultNoExn(64) when "0101",
syncX(64) and syncSignY when "0000",
syncX(64) when others;
-- Exponent and significand of the result
with syncExnXY select
expsigR <= resultNoExn(63 downto 0) when "0101" ,
syncX(63 downto 0) when others; -- 0100, or at least one NaN or one infty
R <= exnR & sgnR & expsigR;
end architecture;
--------------------------------------------------------------------------------
-- dupa
-- (FPAdder_32_32_32_32_32_32_Wrapper)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- and is distributed under the terms of the GNU Lesser General Public Licence.
-- Authors: Florent de Dinechin (2007)
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
entity dupa is
port ( clk, rst : in std_logic;
X : in std_logic_vector(32+32+2 downto 0);
Y : in std_logic_vector(32+32+2 downto 0);
R : out std_logic_vector(32+32+2 downto 0) );
end entity;
architecture arch of dupa is
component FPAdder_32_32_32_32_32_32 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(32+32+2 downto 0);
Y : in std_logic_vector(32+32+2 downto 0);
R : out std_logic_vector(32+32+2 downto 0) );
end component;
signal i_X : std_logic_vector(66 downto 0);
signal i_X_d : std_logic_vector(66 downto 0);
signal i_Y : std_logic_vector(66 downto 0);
signal i_Y_d : std_logic_vector(66 downto 0);
signal i_R : std_logic_vector(66 downto 0);
signal i_R_d : std_logic_vector(66 downto 0);
begin
--wrapper operator
i_X <= X;
i_Y <= Y;
test:FPAdder_32_32_32_32_32_32
port map ( clk => clk,
rst => rst,
X => i_X_d,
Y => i_Y_d,
R => i_R);
process(clk) begin
if clk'event and clk = '1' then
i_X_d <= i_X;
i_Y_d <= i_Y;
i_R_d <= i_R;
end if;
end process;
R <= i_R_d;
end architecture;
| gpl-3.0 | a26a4247ea3ddc273df59838e754dea1 | 0.594953 | 3.328321 | false | false | false | false |
bobxiv/DispositivosLogicosProgramables-FICH | Practica/testseg.vhd | 1 | 3,167 |
--------------------------------------------------------------------------------
-- Company: Universidad de Valencia
-- Engineer: Alfredo Rosado
--
-- Create Date: 10:58:12 10/16/2006
-- Design Name: segmentos
-- Module Name: C:/Xilinx/prac1/prac1b/testseg.vhd
-- Project Name: prac1b
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: segmentos
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY testseg_vhd IS
END testseg_vhd;
ARCHITECTURE behavior OF testseg_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT segmentos
PORT(
Reloj : IN std_logic;
Reset : IN std_logic;
interruptor : IN std_logic_vector(3 downto 0);
abcdefgdp : OUT std_logic_vector(7 downto 0);
anodos : BUFFER std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL Reloj : std_logic := '0';
SIGNAL Reset : std_logic := '0';
SIGNAL interruptor : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL abcdefgdp : std_logic_vector(7 downto 0);
SIGNAL anodos : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: segmentos PORT MAP(
Reloj => Reloj,
Reset => Reset,
interruptor => interruptor,
abcdefgdp => abcdefgdp,
anodos => anodos
);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
Reset <= '1';
wait for 15 ns;
reset <= '0';
wait; -- will wait forever
END PROCESS;
tb2 : PROCESS
BEGIN
Reloj <= '1';
wait for 10 ns;
Reloj <= '0';
wait for 10 ns;
END PROCESS;
tb3 : PROCESS
BEGIN
interruptor <= "0000";
wait for 1000 ns;
interruptor(0) <= '1';
wait for 1000 ns;
interruptor(0) <= '0';
interruptor(1) <= '1';
wait for 1000 ns;
interruptor(1) <= '0';
interruptor(2) <= '1';
wait for 1000 ns;
interruptor(2) <= '0';
interruptor(3) <= '1';
wait for 1000 ns;
interruptor(3) <= '0';
interruptor(0) <= '1';
wait for 1000 ns;
interruptor(0) <= '0';
interruptor(1) <= '1';
wait for 1000 ns;
interruptor(1) <= '0';
interruptor(2) <= '1';
wait for 1000 ns;
interruptor(2) <= '0';
interruptor(3) <= '1';
wait for 1000 ns;
interruptor(3) <= '0';
interruptor(0) <= '1';
wait for 1000 ns;
interruptor(0) <= '0';
interruptor(1) <= '1';
wait for 1000 ns;
interruptor(1) <= '0';
interruptor(2) <= '1';
wait for 1000 ns;
interruptor(2) <= '0';
interruptor(3) <= '1';
wait for 1000 ns;
interruptor(3) <= '0';
interruptor(0) <= '1';
wait;
END PROCESS;
END;
| gpl-3.0 | 5cd4b30ed59383f06ced386a86764bf8 | 0.603094 | 3.151244 | false | true | false | false |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_ftch_pntr.vhd | 1 | 21,428 | -------------------------------------------------------------------------------
-- axi_sg_ftch_pntr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_pntr.vhd
-- Description: This entity manages descriptor pointers and determine scatter
-- gather idle mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/20/10 v1_00_a
-- ^^^^^^
-- CR568950
-- Qualified reseting of sg_idle from axi_sg_ftch_pntr with associated channel's
-- flush control.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_pntr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
------------------------------- --
-- CHANNEL 1 --
------------------------------- --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch1_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch1_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_sg_idle : out std_logic ; --
--
------------------------------- --
-- CHANNEL 2 --
------------------------------- --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ;--CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch2_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch2_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_sg_idle : out std_logic --
);
end axi_sg_ftch_pntr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_pntr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_run_stop_d1 : std_logic := '0';
signal ch1_run_stop_re : std_logic := '0';
signal ch1_use_crntdesc : std_logic := '0';
signal ch1_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_run_stop_d1 : std_logic := '0';
signal ch2_run_stop_re : std_logic := '0';
signal ch2_use_crntdesc : std_logic := '0';
signal ch2_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Channel 1 is included therefore generate pointer logic
GEN_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 1 generate
begin
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_run_stop_d1 <= '0';
else
ch1_run_stop_d1 <= ch1_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch1_run_stop_re <= ch1_run_stop and not ch1_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_nxtdesc_wren = '1')then
ch1_use_crntdesc <= '0';
elsif(ch1_run_stop_re = '1')then
ch1_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch1_use_crntdesc = '1' and ch1_nxtdesc_wren = '0')then
ch1_fetch_address_i <= ch1_curdesc;
-- On desriptor fetch capture next pointer
elsif(ch1_nxtdesc_wren = '1')then
ch1_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
ch1_fetch_address <= ch1_fetch_address_i;
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0' or ch1_desc_flush = '1')then
ch1_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch1_taildesc_wren = '1' or ch1_tailpntr_enabled = '0')then
ch1_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch1_nxtdesc_wren = '1'
and ch1_taildesc = ch1_fetch_address_i)then
ch1_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH1;
-- Channel 1 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 0 generate
begin
ch1_fetch_address <= (others =>'0');
ch1_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH1;
-- Channel 2 is included therefore generate pointer logic
GEN_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 1 generate
begin
---------------------------------------------------------------------------
-- Create clock delay of run_stop in order to generate a rising edge pulse
---------------------------------------------------------------------------
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_run_stop_d1 <= '0';
else
ch2_run_stop_d1 <= ch2_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch2_run_stop_re <= ch2_run_stop and not ch2_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_nxtdesc_wren = '1')then
ch2_use_crntdesc <= '0';
elsif(ch2_run_stop_re = '1')then
ch2_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch2_use_crntdesc = '1' and ch2_nxtdesc_wren = '0')then
ch2_fetch_address_i <= ch2_curdesc;
-- On descirptor fetch capture next pointer
elsif(ch2_nxtdesc_wren = '1')then
ch2_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
ch2_fetch_address <= ch2_fetch_address_i;
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1')then
ch2_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
ch2_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
ch2_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH2;
-- Channel 2 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 0 generate
begin
ch2_fetch_address <= (others =>'0');
ch2_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH2;
end implementation;
| gpl-2.0 | 532690a0e7bf6bfd77b65ddbed58ab60 | 0.408204 | 4.912425 | false | false | false | false |
piliguori/Linear-Regression | Src/testbench/tb_LinearRegression.vhd | 1 | 3,590 | --! @file tb_LinearRegression.vhd
--!
--! @authors Salvatore Barone <[email protected]> <br>
--! Alfonso Di Martino <[email protected]> <br>
--! Sossio Fiorillo <[email protected]> <br>
--! Pietro Liguori <[email protected]> <br>
--!
--! @date 03 07 2017
--!
--! @copyright
--! Copyright 2017 Salvatore Barone <[email protected]> <br>
--! Alfonso Di Martino <[email protected]> <br>
--! Sossio Fiorillo <[email protected]> <br>
--! Pietro Liguori <[email protected]> <br>
--!
--!
--! This file is part of Linear-Regression.
--!
--! Linear-Regression is free software; you can redistribute it and/or modify it under the terms of
--! the GNU General Public License as published by the Free Software Foundation; either version 3 of
--! the License, or any later version.
--!
--! Linear-Regression is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
--! without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--! GNU General Public License for more details.
--!
--! You should have received a copy of the GNU General Public License along with this program; if not,
--! write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
--! USA.
--!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_LinearRegression is
end tb_LinearRegression;
architecture Behavioral of tb_LinearRegression is
component LinearRegression
Port ( clk : in std_logic;
load : in std_logic;
reset_n : in std_logic;
prim : in STD_LOGIC_VECTOR (5 downto 0);
Sum2 : in STD_LOGIC_VECTOR (23 downto 0);
B : in STD_LOGIC_VECTOR (23 downto 0);
Sum1 : in STD_LOGIC_VECTOR (23 downto 0);
C : in STD_LOGIC_VECTOR (23 downto 0);
A : in STD_LOGIC_VECTOR (23 downto 0);
m : out STD_LOGIC_VECTOR (23 downto 0);
q : out STD_LOGIC_VECTOR (23 downto 0));
end component;
constant clock_period : time := 10ns;
signal clk : std_logic := '0';
signal load : std_logic := '0';
signal reset_n : std_logic := '0';
signal prim : STD_LOGIC_VECTOR (5 downto 0) := (others => '0');
signal Sum2 : STD_LOGIC_VECTOR (23 downto 0):= (others => '0');
signal B : STD_LOGIC_VECTOR (23 downto 0):= (others => '0');
signal Sum1 : STD_LOGIC_VECTOR (23 downto 0):= (others => '0');
signal C : STD_LOGIC_VECTOR (23 downto 0):= (others => '0');
signal A : STD_LOGIC_VECTOR (23 downto 0):= (others => '0');
signal m : STD_LOGIC_VECTOR (23 downto 0):= (others => '0');
signal q : STD_LOGIC_VECTOR (23 downto 0):= (others => '0');
begin
clock_process : process
begin
clk <= not clk;
wait for clock_period / 2;
end process clock_process;
uut: LinearRegression
Port map ( clk => clk,
load => load,
reset_n => reset_n,
prim => prim,
Sum2 => Sum2,
B => B,
Sum1 => Sum1,
C => C,
A => A,
m => m,
q => q);
stim_proc: process
begin
wait for 10*clock_period;
reset_n <= '1';
load <= '1';
-- Test 1
prim <= b"011001"; -- 25
Sum2 <= b"001101011110110111001111"; -- 1.685279688780849
Sum1 <= b"001101000111011100011001"; -- 1.049304719064735e+02
B <= b"010011001100110011001100"; -- 0.3
C <= b"010100000100100000010110"; -- 0.0049
A <= b"011110110001001110110001"; -- 30.769230769230795
-- m 327.779907226562 -- 3.277800199255130e+02
-- q 0.263859272003174 -- 0.263858637152785
wait;
end process;
end Behavioral;
| gpl-3.0 | e73fd495f1670229b84c3ff0afb8cb34 | 0.640947 | 3.019344 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GN7PRGDOVA.vhd | 9 | 879 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN7PRGDOVA is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN7PRGDOVA is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 32 + 1 ,
width_inr=> 0,
width_outl=> 24,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(31 downto 0) => input,
xin(32) => '0', yout => output
);
end architecture; | mit | 9fea869b6f72b3c0d1ee5134840e54da | 0.649602 | 3.09507 | false | false | false | false |
nulldozer/purisc | Global_memory/global_memory.vhd | 2 | 31,843 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity global_memory is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
--compute group 0
ADDRESS_A_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_0_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_1_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_W_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_CG0 : IN STD_LOGIC;
ENABLE_CG0 : IN STD_LOGIC;
DATA_A_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_B_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_C_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_0_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_1_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
STALL_CG0 : OUT STD_LOGIC;
--compute group 1
ADDRESS_A_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_0_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_1_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_W_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_CG1 : IN STD_LOGIC;
ENABLE_CG1 : IN STD_LOGIC;
DATA_A_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_B_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_C_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_0_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_1_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
STALL_CG1 : OUT STD_LOGIC;
--compute group 2
ADDRESS_A_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_0_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_1_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_W_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_CG2 : IN STD_LOGIC;
ENABLE_CG2 : IN STD_LOGIC;
DATA_A_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_B_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_C_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_0_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_1_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
STALL_CG2 : OUT STD_LOGIC;
--compute group 3
ADDRESS_A_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_0_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_1_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_W_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_CG3 : IN STD_LOGIC;
ENABLE_CG3 : IN STD_LOGIC;
DATA_A_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_B_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_C_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_0_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_1_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
STALL_CG3 : OUT STD_LOGIC;
--IO controller
ADDRESS_IO : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_IO : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_IO : IN STD_LOGIC;
ENABLE_IO : IN STD_LOGIC;
DATA_RET_IO : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--DONE signals
DONE_C0 : OUT STD_LOGIC;
DONE_C1 : OUT STD_LOGIC;
DONE_C2 : OUT STD_LOGIC;
DONE_C3 : OUT STD_LOGIC;
DONE_C4 : OUT STD_LOGIC;
DONE_C5 : OUT STD_LOGIC;
DONE_C6 : OUT STD_LOGIC;
DONE_C7 : OUT STD_LOGIC;
RCC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end;
architecture global of global_memory is
component MAGIC_global
PORT (
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
DATA_OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
C0_STALL : OUT STD_LOGIC;
C1_STALL : OUT STD_LOGIC;
CORE_IDENT : OUT STD_LOGIC;
IO_ENABLE : IN STD_LOGIC
);
end component;
type state_type is (cg0, cg1, cg2, cg3);
signal state : state_type;
signal address_a_cg0_buffer : std_logic_vector(31 downto 0);
signal address_b_cg0_buffer : std_logic_vector(31 downto 0);
signal address_c_cg0_buffer : std_logic_vector(31 downto 0);
signal address_0_cg0_buffer : std_logic_vector(31 downto 0);
signal address_1_cg0_buffer : std_logic_vector(31 downto 0);
signal address_w_cg0_buffer : std_logic_vector(31 downto 0);
signal data_to_w_cg0_buffer : std_logic_vector(31 downto 0);
signal w_en_cg0_buffer : std_logic;
signal access_request_cg0 : std_logic;
signal data_a_to_cg0_buffer : std_logic_vector (31 downto 0);
signal data_b_to_cg0_buffer : std_logic_vector (31 downto 0);
signal data_c_to_cg0_buffer : std_logic_vector (31 downto 0);
signal data_0_to_cg0_buffer : std_logic_vector (31 downto 0);
signal data_1_to_cg0_buffer : std_logic_vector (31 downto 0);
signal address_a_cg1_buffer : std_logic_vector(31 downto 0);
signal address_b_cg1_buffer : std_logic_vector(31 downto 0);
signal address_c_cg1_buffer : std_logic_vector(31 downto 0);
signal address_0_cg1_buffer : std_logic_vector(31 downto 0);
signal address_1_cg1_buffer : std_logic_vector(31 downto 0);
signal address_w_cg1_buffer : std_logic_vector(31 downto 0);
signal data_to_w_cg1_buffer : std_logic_vector(31 downto 0);
signal w_en_cg1_buffer : std_logic;
signal access_request_cg1 : std_logic;
signal data_a_to_cg1_buffer : std_logic_vector (31 downto 0);
signal data_b_to_cg1_buffer : std_logic_vector (31 downto 0);
signal data_c_to_cg1_buffer : std_logic_vector (31 downto 0);
signal data_0_to_cg1_buffer : std_logic_vector (31 downto 0);
signal data_1_to_cg1_buffer : std_logic_vector (31 downto 0);
signal address_a_cg2_buffer : std_logic_vector(31 downto 0);
signal address_b_cg2_buffer : std_logic_vector(31 downto 0);
signal address_c_cg2_buffer : std_logic_vector(31 downto 0);
signal address_0_cg2_buffer : std_logic_vector(31 downto 0);
signal address_1_cg2_buffer : std_logic_vector(31 downto 0);
signal address_w_cg2_buffer : std_logic_vector(31 downto 0);
signal data_to_w_cg2_buffer : std_logic_vector(31 downto 0);
signal w_en_cg2_buffer : std_logic;
signal access_request_cg2 : std_logic;
signal data_a_to_cg2_buffer : std_logic_vector (31 downto 0);
signal data_b_to_cg2_buffer : std_logic_vector (31 downto 0);
signal data_c_to_cg2_buffer : std_logic_vector (31 downto 0);
signal data_0_to_cg2_buffer : std_logic_vector (31 downto 0);
signal data_1_to_cg2_buffer : std_logic_vector (31 downto 0);
signal address_a_cg3_buffer : std_logic_vector(31 downto 0);
signal address_b_cg3_buffer : std_logic_vector(31 downto 0);
signal address_c_cg3_buffer : std_logic_vector(31 downto 0);
signal address_0_cg3_buffer : std_logic_vector(31 downto 0);
signal address_1_cg3_buffer : std_logic_vector(31 downto 0);
signal address_w_cg3_buffer : std_logic_vector(31 downto 0);
signal data_to_w_cg3_buffer : std_logic_vector(31 downto 0);
signal w_en_cg3_buffer : std_logic;
signal access_request_cg3 : std_logic;
signal data_a_to_cg3_buffer : std_logic_vector (31 downto 0);
signal data_b_to_cg3_buffer : std_logic_vector (31 downto 0);
signal data_c_to_cg3_buffer : std_logic_vector (31 downto 0);
signal data_0_to_cg3_buffer : std_logic_vector (31 downto 0);
signal data_1_to_cg3_buffer : std_logic_vector (31 downto 0);
signal address_a_to_mem : std_logic_vector(31 downto 0);
signal address_b_to_mem : std_logic_vector(31 downto 0);
signal address_c_to_mem : std_logic_vector(31 downto 0);
signal address_0_to_mem : std_logic_vector(31 downto 0);
signal address_1_to_mem : std_logic_vector(31 downto 0);
signal address_w_to_mem : std_logic_vector(31 downto 0);
signal data_to_w_to_mem : std_logic_vector(31 downto 0);
signal w_en_to_mem : std_logic;
signal address_a_mem : std_logic_vector(31 downto 0);
signal address_b_mem : std_logic_vector(31 downto 0);
signal address_c_mem : std_logic_vector(31 downto 0);
signal address_0_mem : std_logic_vector(31 downto 0);
signal address_1_mem : std_logic_vector(31 downto 0);
signal address_w_mem : std_logic_vector(31 downto 0);
signal data_to_w_mem : std_logic_vector(31 downto 0);
signal w_en_mem : std_logic;
signal data_a : std_logic_vector(31 downto 0);
signal data_b : std_logic_vector(31 downto 0);
signal data_c : std_logic_vector(31 downto 0);
signal data_0 : std_logic_vector(31 downto 0);
signal data_1 : std_logic_vector(31 downto 0);
signal core_id : std_logic;
signal gnd : std_logic;
signal stall_c0 : std_logic;
signal stall_c1 : std_logic;
signal stall_c0_raw : std_logic;
signal stall_c1_raw : std_logic;
signal done_cg0 : std_logic;
signal done_cg1 : std_logic;
signal done_cg2 : std_logic;
signal done_cg3 : std_logic;
signal clear_stall_cg0 : std_logic;
signal clear_stall_cg1 : std_logic;
signal clear_stall_cg2 : std_logic;
signal clear_stall_cg3 : std_logic;
signal buffer_cg0 : std_logic;
signal buffer_cg1 : std_logic;
signal buffer_cg2 : std_logic;
signal buffer_cg3 : std_logic;
signal done_reg_c0 : std_logic;
signal done_reg_c1 : std_logic;
signal done_reg_c2 : std_logic;
signal done_reg_c3 : std_logic;
signal done_reg_c4 : std_logic;
signal done_reg_c5 : std_logic;
signal done_reg_c6 : std_logic;
signal done_reg_c7 : std_logic;
signal ready_clear_count : std_logic_vector(3 downto 0);
begin
gnd <= '0';
--immidiately stall the requesting core
STALL_CG0 <= ENABLE_CG0 and clear_stall_cg0;
STALL_CG1 <= ENABLE_CG1 and clear_stall_cg1;
STALL_CG2 <= ENABLE_CG2 and clear_stall_cg2;
STALL_CG3 <= ENABLE_CG3 and clear_stall_cg3;
--pass buffered values back to compute groups
DATA_A_TO_CG0 <= data_a_to_cg0_buffer;
DATA_B_TO_CG0 <= data_b_to_cg0_buffer;
DATA_C_TO_CG0 <= data_c_to_cg0_buffer;
DATA_0_TO_CG0 <= data_0_to_cg0_buffer;
DATA_1_TO_CG0 <= data_1_to_cg0_buffer;
DATA_A_TO_CG1 <= data_a_to_cg1_buffer;
DATA_B_TO_CG1 <= data_b_to_cg1_buffer;
DATA_C_TO_CG1 <= data_c_to_cg1_buffer;
DATA_0_TO_CG1 <= data_0_to_cg1_buffer;
DATA_1_TO_CG1 <= data_1_to_cg1_buffer;
DATA_A_TO_CG2 <= data_a_to_cg2_buffer;
DATA_B_TO_CG2 <= data_b_to_cg2_buffer;
DATA_C_TO_CG2 <= data_c_to_cg2_buffer;
DATA_0_TO_CG2 <= data_0_to_cg2_buffer;
DATA_1_TO_CG2 <= data_1_to_cg2_buffer;
DATA_A_TO_CG3 <= data_a_to_cg3_buffer;
DATA_B_TO_CG3 <= data_b_to_cg3_buffer;
DATA_C_TO_CG3 <= data_c_to_cg3_buffer;
DATA_0_TO_CG3 <= data_0_to_cg3_buffer;
DATA_1_TO_CG3 <= data_1_to_cg3_buffer;
buffer_input_lines : process (CLK, RESET_n) begin
if (RESET_n = '0') then
address_a_cg0_buffer <= "00000000000000000000000000000000";
address_b_cg0_buffer <= "00000000000000000000000000000001";
address_c_cg0_buffer <= "00000000000000000000000000000010";
address_0_cg0_buffer <= "00000000000000000000000000000011";
address_1_cg0_buffer <= "00000000000000000000000000000100";
address_w_cg0_buffer <= "00000000000000000000000000000101";
data_to_w_cg0_buffer <= "00000000000000000000000000000110";
w_en_cg0_buffer <= '0';
access_request_cg0 <= '0';
address_a_cg1_buffer <= "00000000000000000000000000000000";
address_b_cg1_buffer <= "00000000000000000000000000000001";
address_c_cg1_buffer <= "00000000000000000000000000000010";
address_0_cg1_buffer <= "00000000000000000000000000000011";
address_1_cg1_buffer <= "00000000000000000000000000000100";
address_w_cg1_buffer <= "00000000000000000000000000000101";
data_to_w_cg1_buffer <= "00000000000000000000000000000110";
w_en_cg1_buffer <= '0';
access_request_cg1 <= '0';
address_a_cg2_buffer <= "00000000000000000000000000000000";
address_b_cg2_buffer <= "00000000000000000000000000000001";
address_c_cg2_buffer <= "00000000000000000000000000000010";
address_0_cg2_buffer <= "00000000000000000000000000000011";
address_1_cg2_buffer <= "00000000000000000000000000000100";
address_w_cg2_buffer <= "00000000000000000000000000000101";
data_to_w_cg2_buffer <= "00000000000000000000000000000110";
w_en_cg2_buffer <= '0';
access_request_cg2 <= '0';
address_a_cg3_buffer <= "00000000000000000000000000000000";
address_b_cg3_buffer <= "00000000000000000000000000000001";
address_c_cg3_buffer <= "00000000000000000000000000000010";
address_0_cg3_buffer <= "00000000000000000000000000000011";
address_1_cg3_buffer <= "00000000000000000000000000000100";
address_w_cg3_buffer <= "00000000000000000000000000000101";
data_to_w_cg3_buffer <= "00000000000000000000000000000110";
w_en_cg3_buffer <= '0';
access_request_cg3 <= '0';
elsif (rising_edge(CLK)) then
address_a_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_A_CG0(14 downto 13)) - 1) & ADDRESS_A_CG0(12 downto 0);
address_b_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_B_CG0(14 downto 13)) - 1) & ADDRESS_B_CG0(12 downto 0);
address_c_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_C_CG0(14 downto 13)) - 1) & ADDRESS_C_CG0(12 downto 0);
address_0_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_0_CG0(14 downto 13)) - 1) & ADDRESS_0_CG0(12 downto 0);
address_1_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_1_CG0(14 downto 13)) - 1) & ADDRESS_1_CG0(12 downto 0);
address_w_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_W_CG0(14 downto 13)) - 1) & ADDRESS_W_CG0(12 downto 0);
data_to_w_cg0_buffer <= DATA_TO_W_CG0;
w_en_cg0_buffer <= W_EN_CG0;
access_request_cg0 <= ENABLE_CG0;
address_a_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_A_CG1(14 downto 13)) - 1) & ADDRESS_A_CG1(12 downto 0);
address_b_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_B_CG1(14 downto 13)) - 1) & ADDRESS_B_CG1(12 downto 0);
address_c_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_C_CG1(14 downto 13)) - 1) & ADDRESS_C_CG1(12 downto 0);
address_0_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_0_CG1(14 downto 13)) - 1) & ADDRESS_0_CG1(12 downto 0);
address_1_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_1_CG1(14 downto 13)) - 1) & ADDRESS_1_CG1(12 downto 0);
address_w_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_W_CG1(14 downto 13)) - 1) & ADDRESS_W_CG1(12 downto 0);
data_to_w_cg1_buffer <= DATA_TO_W_CG1;
w_en_cg1_buffer <= W_EN_CG1;
access_request_cg1 <= ENABLE_CG1;
address_a_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_A_CG2(14 downto 13)) - 1) & ADDRESS_A_CG2(12 downto 0);
address_b_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_B_CG2(14 downto 13)) - 1) & ADDRESS_B_CG2(12 downto 0);
address_c_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_C_CG2(14 downto 13)) - 1) & ADDRESS_C_CG2(12 downto 0);
address_0_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_0_CG2(14 downto 13)) - 1) & ADDRESS_0_CG2(12 downto 0);
address_1_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_1_CG2(14 downto 13)) - 1) & ADDRESS_1_CG2(12 downto 0);
address_w_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_W_CG2(14 downto 13)) - 1) & ADDRESS_W_CG2(12 downto 0);
data_to_w_cg2_buffer <= DATA_TO_W_CG2;
w_en_cg2_buffer <= W_EN_CG2;
access_request_cg2 <= ENABLE_CG2;
address_a_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_A_CG3(14 downto 13)) - 1) & ADDRESS_A_CG3(12 downto 0);
address_b_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_B_CG3(14 downto 13)) - 1) & ADDRESS_B_CG3(12 downto 0);
address_c_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_C_CG3(14 downto 13)) - 1) & ADDRESS_C_CG3(12 downto 0);
address_0_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_0_CG3(14 downto 13)) - 1) & ADDRESS_0_CG3(12 downto 0);
address_1_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_1_CG3(14 downto 13)) - 1) & ADDRESS_1_CG3(12 downto 0);
address_w_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_W_CG3(14 downto 13)) - 1) & ADDRESS_W_CG3(12 downto 0);
data_to_w_cg3_buffer <= DATA_TO_W_CG3;
w_en_cg3_buffer <= W_EN_CG3;
access_request_cg3 <= ENABLE_CG3;
end if;
end process;
buffer_enables: process (RESET_n, CLK) begin
if (RESET_n = '0') then
buffer_cg0 <= '0';
buffer_cg1 <= '0';
buffer_cg2 <= '0';
buffer_cg3 <= '0';
elsif (rising_edge(CLK)) then
clear_stall_cg0 <= not buffer_cg0;
clear_stall_cg1 <= not buffer_cg1;
clear_stall_cg2 <= not buffer_cg2;
clear_stall_cg3 <= not buffer_cg3;
buffer_cg0 <= done_cg0 and access_request_cg0;
buffer_cg1 <= done_cg1 and access_request_cg1;
buffer_cg2 <= done_cg2 and access_request_cg2;
buffer_cg3 <= done_cg3 and access_request_cg3;
end if;
end process;
buffer_data: process (RESET_n, CLK) begin
if (RESET_n = '0') then
data_a_to_cg0_buffer <= "00000000000000000000000000000000";
data_b_to_cg0_buffer <= "00000000000000000000000000000000";
data_c_to_cg0_buffer <= "00000000000000000000000000000000";
data_0_to_cg0_buffer <= "00000000000000000000000000000000";
data_1_to_cg0_buffer <= "00000000000000000000000000000000";
data_a_to_cg1_buffer <= "00000000000000000000000000000000";
data_b_to_cg1_buffer <= "00000000000000000000000000000000";
data_c_to_cg1_buffer <= "00000000000000000000000000000000";
data_0_to_cg1_buffer <= "00000000000000000000000000000000";
data_1_to_cg1_buffer <= "00000000000000000000000000000000";
data_a_to_cg2_buffer <= "00000000000000000000000000000000";
data_b_to_cg2_buffer <= "00000000000000000000000000000000";
data_c_to_cg2_buffer <= "00000000000000000000000000000000";
data_0_to_cg2_buffer <= "00000000000000000000000000000000";
data_1_to_cg2_buffer <= "00000000000000000000000000000000";
data_a_to_cg3_buffer <= "00000000000000000000000000000000";
data_b_to_cg3_buffer <= "00000000000000000000000000000000";
data_c_to_cg3_buffer <= "00000000000000000000000000000000";
data_0_to_cg3_buffer <= "00000000000000000000000000000000";
data_1_to_cg3_buffer <= "00000000000000000000000000000000";
elsif (rising_edge(CLK)) then
if (buffer_cg0 = '1') then
data_a_to_cg0_buffer <= data_a;
data_b_to_cg0_buffer <= data_b;
data_c_to_cg0_buffer <= data_c;
data_0_to_cg0_buffer <= data_0;
data_1_to_cg0_buffer <= data_1;
end if;
if (buffer_cg1 = '1') then
data_a_to_cg1_buffer <= data_a;
data_b_to_cg1_buffer <= data_b;
data_c_to_cg1_buffer <= data_c;
data_0_to_cg1_buffer <= data_0;
data_1_to_cg1_buffer <= data_1;
end if;
if (buffer_cg2 = '1') then
data_a_to_cg2_buffer <= data_a;
data_b_to_cg2_buffer <= data_b;
data_c_to_cg2_buffer <= data_c;
data_0_to_cg2_buffer <= data_0;
data_1_to_cg2_buffer <= data_1;
end if;
if (buffer_cg3 = '1') then
data_a_to_cg3_buffer <= data_a;
data_b_to_cg3_buffer <= data_b;
data_c_to_cg3_buffer <= data_c;
data_0_to_cg3_buffer <= data_0;
data_1_to_cg3_buffer <= data_1;
end if;
end if;
end process;
state_machine : process (RESET_n, CLK, done_cg0, done_cg1, done_cg2, done_cg3) begin
if (RESET_n = '0') then
state <= cg0;
elsif (rising_edge(CLK)) then
case state is
when cg0 =>
if (done_cg0 = '0') then
state <= cg0;
else
state <= cg1;
end if;
when cg1 =>
if (done_cg1 = '0') then
state <= cg1;
else
state <= cg2;
end if;
when cg2 =>
if (done_cg2 = '0') then
state <= cg2;
else
state <= cg3;
end if;
when cg3 =>
if (done_cg3 = '0') then
state <= cg3;
else
state <= cg0;
end if;
end case;
end if;
end process;
passing_adresses : process (state, stall_c0, stall_c1, access_request_cg0, access_request_cg1, access_request_cg2, access_request_cg3,
address_a_cg0_buffer, address_b_cg0_buffer, address_c_cg0_buffer, address_0_cg0_buffer, address_1_cg0_buffer,
address_a_cg1_buffer, address_b_cg1_buffer, address_c_cg1_buffer, address_0_cg1_buffer, address_1_cg1_buffer,
address_a_cg2_buffer, address_b_cg2_buffer, address_c_cg2_buffer, address_0_cg2_buffer, address_1_cg2_buffer,
address_a_cg3_buffer, address_b_cg3_buffer, address_c_cg3_buffer, address_0_cg3_buffer, address_1_cg3_buffer,
address_w_cg0_buffer, address_w_cg1_buffer, address_w_cg2_buffer, address_w_cg3_buffer,
data_to_w_cg0_buffer, data_to_w_cg1_buffer, data_to_w_cg2_buffer, data_to_w_cg3_buffer,
w_en_cg0_buffer, w_en_cg1_buffer, w_en_cg2_buffer, w_en_cg3_buffer) begin
case state is
when cg0 =>
--if access requested, pass adresses
if (access_request_cg0 = '1') then
address_a_to_mem <= address_a_cg0_buffer;
address_b_to_mem <= address_b_cg0_buffer;
address_c_to_mem <= address_c_cg0_buffer;
address_0_to_mem <= address_0_cg0_buffer;
address_1_to_mem <= address_1_cg0_buffer;
address_w_to_mem <= address_w_cg0_buffer;
data_to_w_to_mem <= data_to_w_cg0_buffer;
w_en_to_mem <= w_en_cg0_buffer;
--wait for memory to respond
if ((stall_c0 and stall_c1) = '1') then
done_cg0 <= '0';
else
done_cg0 <= '1';
end if;
--if access not requested, supply dummy adresses
else
address_a_to_mem <= "00000000000000000000000000000000";
address_b_to_mem <= "00000000000000000000000000000001";
address_c_to_mem <= "00000000000000000000000000000010";
address_0_to_mem <= "00000000000000000000000000000011";
address_1_to_mem <= "00000000000000000000000000000100";
address_w_to_mem <= "00000000000000000000000000000101";
data_to_w_to_mem <= "00000000000000000000000000000110";
w_en_to_mem <= '0';
--move on to next group
done_cg0 <= '1';
end if;
--all other compute groups not getting service yet
done_cg1 <= '0';
done_cg2 <= '0';
done_cg3 <= '0';
when cg1 =>
--if access requested, pass adresses
if (access_request_cg1 = '1') then
address_a_to_mem <= address_a_cg1_buffer;
address_b_to_mem <= address_b_cg1_buffer;
address_c_to_mem <= address_c_cg1_buffer;
address_0_to_mem <= address_0_cg1_buffer;
address_1_to_mem <= address_1_cg1_buffer;
address_w_to_mem <= address_w_cg1_buffer;
data_to_w_to_mem <= data_to_w_cg1_buffer;
w_en_to_mem <= w_en_cg1_buffer;
--wait for memory to respond
if ((stall_c0 and stall_c1) = '1') then
done_cg1 <= '0';
else
done_cg1 <= '1';
end if;
--if access not requested, supply dummy adresses
else
address_a_to_mem <= "00000000000000000000000000000000";
address_b_to_mem <= "00000000000000000000000000000001";
address_c_to_mem <= "00000000000000000000000000000010";
address_0_to_mem <= "00000000000000000000000000000011";
address_1_to_mem <= "00000000000000000000000000000100";
address_w_to_mem <= "00000000000000000000000000000101";
data_to_w_to_mem <= "00000000000000000000000000000110";
w_en_to_mem <= '0';
--move on to next group
done_cg1 <= '1';
end if;
--all other compute groups not getting service yet
done_cg0 <= '0';
done_cg2 <= '0';
done_cg3 <= '0';
when cg2 =>
--if access requested, pass adresses
if (access_request_cg2 = '1') then
address_a_to_mem <= address_a_cg2_buffer;
address_b_to_mem <= address_b_cg2_buffer;
address_c_to_mem <= address_c_cg2_buffer;
address_0_to_mem <= address_0_cg2_buffer;
address_1_to_mem <= address_1_cg2_buffer;
address_w_to_mem <= address_w_cg2_buffer;
data_to_w_to_mem <= data_to_w_cg2_buffer;
w_en_to_mem <= w_en_cg2_buffer;
--wait for memory to respond
if ((stall_c0 and stall_c1) = '1') then
done_cg2 <= '0';
else
done_cg2 <= '1';
end if;
--if access not requested, supply dummy adresses
else
address_a_to_mem <= "00000000000000000000000000000000";
address_b_to_mem <= "00000000000000000000000000000001";
address_c_to_mem <= "00000000000000000000000000000010";
address_0_to_mem <= "00000000000000000000000000000011";
address_1_to_mem <= "00000000000000000000000000000100";
address_w_to_mem <= "00000000000000000000000000000101";
data_to_w_to_mem <= "00000000000000000000000000000110";
w_en_to_mem <= '0';
--move on to next group
done_cg2 <= '1';
end if;
--all other compute groups not getting service yet
done_cg1 <= '0';
done_cg0 <= '0';
done_cg3 <= '0';
when cg3 =>
--if access requested, pass adresses
if (access_request_cg3 = '1') then
address_a_to_mem <= address_a_cg3_buffer;
address_b_to_mem <= address_b_cg3_buffer;
address_c_to_mem <= address_c_cg3_buffer;
address_0_to_mem <= address_0_cg3_buffer;
address_1_to_mem <= address_1_cg3_buffer;
address_w_to_mem <= address_w_cg3_buffer;
data_to_w_to_mem <= data_to_w_cg3_buffer;
w_en_to_mem <= w_en_cg3_buffer;
--wait for memory to respond
if ((stall_c0 and stall_c1) = '1') then
done_cg3 <= '0';
else
done_cg3 <= '1';
end if;
--if access not requested, supply dummy adresses
else
address_a_to_mem <= "00000000000000000000000000000000";
address_b_to_mem <= "00000000000000000000000000000001";
address_c_to_mem <= "00000000000000000000000000000010";
address_0_to_mem <= "00000000000000000000000000000011";
address_1_to_mem <= "00000000000000000000000000000100";
address_w_to_mem <= "00000000000000000000000000000101";
data_to_w_to_mem <= "00000000000000000000000000000110";
w_en_to_mem <= '0';
--move on to next group
done_cg3 <= '1';
end if;
--all other compute groups not getting service yet
done_cg1 <= '0';
done_cg2 <= '0';
done_cg0 <= '0';
end case;
end process;
global_cache : MAGIC_global PORT MAP (
ADDRESS_A => address_a_mem,
ADDRESS_B => address_b_mem,
ADDRESS_C => address_c_mem,
ADDRESS_0 => address_0_mem,
ADDRESS_1 => address_1_mem,
ADDRESS_W => address_w_mem,
DATA_TO_W => data_to_w_mem,
W_EN => w_en_mem,
CLK => CLK,
RESET_n => RESET_n,
DATA_OUT_A => data_a,
DATA_OUT_B => data_b,
DATA_OUT_C => data_c,
DATA_OUT_0 => data_0,
DATA_OUT_1 => data_1,
C0_STALL => stall_c0_raw,
C1_STALL => stall_c1_raw,
CORE_IDENT => core_id,
IO_ENABLE => gnd
);
--io override
stall_c0 <= stall_c0_raw or ENABLE_IO;
stall_c1 <= stall_c1_raw or ENABLE_IO;
DATA_RET_IO <= data_a;
process (ENABLE_IO, ADDRESS_IO, DATA_TO_W_IO, W_EN_IO, data_a, address_a_to_mem,
address_b_to_mem, address_c_to_mem, address_0_to_mem, address_1_to_mem,
data_to_w_to_mem, w_en_to_mem, address_w_to_mem) begin
if (ENABLE_IO = '1') then
if (W_EN_IO = '1') then
address_a_mem <= "00000000000000000000000000000000";
address_b_mem <= "00000000000000000000000000000001";
address_c_mem <= "00000000000000000000000000000010";
address_0_mem <= "00000000000000000000000000000011";
address_1_mem <= "00000000000000000000000000000100";
address_w_mem <= ADDRESS_IO;
data_to_w_mem <= DATA_TO_W_IO;
w_en_mem <= '1';
else
address_a_mem <= ADDRESS_IO;
address_b_mem <= "00000000000000000000000000000001";
address_c_mem <= "00000000000000000000000000000010";
address_0_mem <= "00000000000000000000000000000011";
address_1_mem <= "00000000000000000000000000000100";
address_w_mem <= "00000000000000000000000000000100";
data_to_w_mem <= data_to_w_to_mem;
w_en_mem <= '0';
end if;
else
address_a_mem <= address_a_to_mem;
address_b_mem <= address_b_to_mem;
address_c_mem <= address_c_to_mem;
address_0_mem <= address_0_to_mem;
address_1_mem <= address_1_to_mem;
address_w_mem <= address_w_to_mem;
data_to_w_mem <= data_to_w_to_mem;
w_en_mem <= w_en_to_mem;
end if;
end process;
process (address_w_mem, w_en_mem, data_to_w_mem, CLK, RESET_n) begin
if (RESET_n = '0') then
done_reg_c0 <= '0';
done_reg_c1 <= '0';
done_reg_c2 <= '0';
done_reg_c3 <= '0';
done_reg_c4 <= '0';
done_reg_c5 <= '0';
done_reg_c6 <= '0';
done_reg_c7 <= '0';
ready_clear_count <= "0000";
elsif (rising_edge(CLK)) then
if ((address_w_mem = "00000000000000000010000000000000") and (w_en_mem = '1')) then
done_reg_c0 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000001") and (w_en_mem = '1')) then
done_reg_c1 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000010") and (w_en_mem = '1')) then
done_reg_c2 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000011") and (w_en_mem = '1')) then
done_reg_c3 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000100") and (w_en_mem = '1')) then
done_reg_c4 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000101") and (w_en_mem = '1')) then
done_reg_c5 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000110") and (w_en_mem = '1')) then
done_reg_c6 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000111") and (w_en_mem = '1')) then
done_reg_c7 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000001000") and (w_en_mem = '1')) then
ready_clear_count <= std_logic_vector(unsigned(ready_clear_count) + 1);
end if;
end if;
end process;
DONE_C0 <= done_reg_c0;
DONE_C1 <= done_reg_c1;
DONE_C2 <= done_reg_c2;
DONE_C3 <= done_reg_c3;
DONE_C4 <= done_reg_c4;
DONE_C5 <= done_reg_c5;
DONE_C6 <= done_reg_c6;
DONE_C7 <= done_reg_c7;
RCC <= ready_clear_count;
end; | gpl-2.0 | 169131a595fd14abcb428ba080537f61 | 0.640894 | 2.865125 | false | false | false | false |
Raane/Term-Assigment-TFE4140-mod-anal-dig-sys | Project/liaison/src/registers.vhd | 1 | 1,955 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity registers is
port(
voted_data_bit : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
status : in STD_LOGIC_VECTOR(2 downto 0);
control_signals : in STD_LOGIC_VECTOR(9 downto 0);
ECC_signal : in STD_LOGIC_VECTOR(3 downto 0);
voted_data_out : out STD_LOGIC_VECTOR(7 downto 0);
status_out : out STD_LOGIC_VECTOR(2 downto 0);
ECC_out : out STD_LOGIC_VECTOR(3 downto 0)
);
end registers;
architecture registers of registers is
signal voted_data_reg: STD_LOGIC_VECTOR (7 downto 0);
signal status_reg: STD_LOGIC_VECTOR (2 downto 0);
signal ECC_reg: STD_LOGIC_VECTOR (3 downto 0);
begin
-- Connect the registers to the outputs
process(voted_data_reg, status_reg, ECC_reg)
begin
voted_data_out <= voted_data_reg;
status_out <= status_reg;
ECC_out <= ECC_reg;
end process;
-- Add registers for storage of data
process(clk)
begin
if rising_edge(clk) then
if(reset='1') then
voted_data_reg <= "00000000";
status_reg <= "000";
ECC_reg <= "0000";
else
if control_signals(0) = '1' then
voted_data_reg(0) <= voted_data_bit;
end if;
if control_signals(1) = '1' then
voted_data_reg(1) <= voted_data_bit;
end if;
if control_signals(2) = '1' then
voted_data_reg(2) <= voted_data_bit;
end if;
if control_signals(3) = '1' then
voted_data_reg(3) <= voted_data_bit;
end if;
if control_signals(4) = '1' then
voted_data_reg(4) <= voted_data_bit;
end if;
if control_signals(5) = '1' then
voted_data_reg(5) <= voted_data_bit;
end if;
if control_signals(6) = '1' then
voted_data_reg(6) <= voted_data_bit;
end if;
if control_signals(7) = '1' then
voted_data_reg(7) <= voted_data_bit;
end if;
if control_signals(8) = '1' then
status_reg <= status;
end if;
if control_signals(9) = '1' then
ECC_reg <= ECC_signal;
end if;
end if;
end if;
end process;
end registers; | apache-2.0 | b4840a0c3efdb80f9ff3841fbff0f0ba | 0.641944 | 2.749648 | false | false | false | false |
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`protect end_protected
| gpl-2.0 | 3845b881425e464d3aa276a23bdf886d | 0.955871 | 1.82887 | false | false | false | false |
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