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willprice/vhdl-computer | src/rtl/reg_shift.vhd | 1 | 3,374 | ------------------------------------------------------------------------------
-- @file reg_shift.vhd
-- @brief Implements a very simple shift register with serial input, parallel
-- load and output, and serial output.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--
-- @details
-- Generic width shift register with parallel load enable and asynchronous reset.
-- Different action is performed depending on the value of control:
-- 00 - stay the same
-- 01 - shift right
-- 10 - shift left
-- 11 - parallel load
entity reg_shift is
generic(
PORT_WIDTH : in natural := 8
);
port(
clk : in std_logic;
reset : in std_logic;
en : in std_logic;
serial_in : in std_logic;
serial_out : out std_logic;
parallel_in : in std_logic_vector(PORT_WIDTH -1 downto 0);
parallel_out : out std_logic_vector(PORT_WIDTH -1 downto 0);
control : in std_logic_vector(1 downto 0)
);
end entity reg_shift;
architecture arch_rtl of reg_shift is
-- D type flipflop referenced from ff_dtype.vhd
component ff_dtype is
port(
clk : in std_logic;
data : in std_logic;
reset : in std_logic;
q : buffer std_logic;
not_q : buffer std_logic
);
end component ff_dtype;
-- Four to one multiplexer referenced from mux_4to1.vhd
component mux_4to1 is
generic (
PORT_WIDTH : in natural := 1
);
port(
in_0 : in std_logic_vector(PORT_WIDTH - 1 downto 0);
in_1 : in std_logic_vector(PORT_WIDTH - 1 downto 0);
in_2 : in std_logic_vector(PORT_WIDTH - 1 downto 0);
in_3 : in std_logic_vector(PORT_WIDTH - 1 downto 0);
sel : in std_logic_vector(1 downto 0);
out_sig: out std_logic_vector(PORT_WIDTH - 1 downto 0)
);
end component mux_4to1;
signal flipflop_outputs : std_logic_vector(PORT_WIDTH downto -1);
signal mux_outputs : std_logic_vector(PORT_WIDTH downto 0);
begin
parallel_out <= flipflop_outputs(PORT_WIDTH -1 downto 0);
flipflop_outputs(-1) <= serial_in;
serial_out <= flipflop_outputs(PORT_WIDTH);
--
-- Performs the automatic creation of the multiplexers and flipflops that
-- form the internals of the register. Also handles connecting them up.
gen_components : for I in 0 to PORT_WIDTH - 1 generate
--
-- The I'th flipflop
ff : ff_dtype port map(
clk => clk,
reset => reset,
data => mux_outputs(I),
q => flipflop_outputs(I)
);
--
-- The I'th multiplexer
mux : mux_4to1
generic map(
PORT_WIDTH => 1
)
port map(
-- All mux's share the same control signal.
sel => control,
out_sig(0) => mux_outputs(I),
-- zeroth input is stay the same
in_0(0) => flipflop_outputs(I),
-- first input is the previous flipflop output
in_1(0) => flipflop_outputs(I-1),
-- second input is the next flipflop output
in_2(0) => flipflop_outputs(I+1),
-- third input is parallel load
in_3(0) => parallel_in(I)
);
end generate gen_components;
end architecture arch_rtl;
| gpl-3.0 | 81bbe9b9c54adf70337d65647f79b71c | 0.55572 | 3.856 | false | false | false | false |
nsauzede/cpu86 | testbench/uarttx.vhd | 1 | 8,643 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Design unit : Simple UART (transmitter) --
-------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY uarttx IS
PORT(
clk : IN std_logic;
enable : IN std_logic; -- 1 x bit_rate Transmit clock enable
resetn : IN std_logic;
dbus : IN std_logic_vector (7 DOWNTO 0); -- input to txshift register
tdre : OUT std_logic;
wrn : IN std_logic;
tx : OUT std_logic
);
-- Declarations
END uarttx ;
architecture rtl of uarttx is
signal txshift_s : std_logic_vector(9 downto 0); -- Transmit Shift Register
signal txreg_s : std_logic_vector(7 downto 0); -- Transmit Holding Register
signal bitcount_s : std_logic_vector(3 downto 0); -- 9 to 0 bit counter
signal tsrl_s : std_logic; -- latch Data (txclk strobe)
signal tdre_s : std_logic; -- Transmit Data Register Empty
signal shift_s : std_logic; -- Shift transmit register signal
TYPE STATE_TYPE IS (Sstart,Slatch,Swait,Sshift);
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE ;
SIGNAL next_state : STATE_TYPE ;
-- architecture declarations
type state_type2 is (s0,s1,s2);
-- declare current and next state signals
signal current_state2: state_type2 ;
signal next_state2 : state_type2 ;
begin
-------------------------------------------------------------------------------
-- Transmit Hold Register
-------------------------------------------------------------------------------
process (clk,resetn)
begin
if (resetn='0') then
txreg_s <= (others => '1');
elsif (rising_edge(clk)) then
if wrn='0' then
txreg_s <= dbus;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Shift out every enable pulse.
-------------------------------------------------------------------------------
process (resetn,clk)
begin
if resetn='0' then
txshift_s <= (others => '1'); -- init to all '1' (including start bit)
elsif (rising_edge(clk)) then
if tsrl_s='1' then
txshift_s <= '1'&txreg_s&'0'; -- latch data
elsif shift_s='1' then
txshift_s <= '1' & txshift_s(9 downto 1);-- shift right
end if;
end if;
end process;
tx <= txshift_s(0); -- transmit pin
-------------------------------------------------------------------------------
-- FSM1, control shift & tsrl_s signals
-------------------------------------------------------------------------------
process(clk,resetn)
begin
if (resetn = '0') then
current_state <= sstart;
bitcount_s <= "0000";
elsif (clk'event and clk = '1') then
current_state <= next_state;
case current_state is
when slatch =>
bitcount_s<="0000";
when sshift =>
bitcount_s<=bitcount_s+'1';
when others =>
null;
end case;
end if;
end process;
process (bitcount_s,current_state,tdre_s,enable)
begin
shift_s <= '0';
tsrl_s <= '0';
case current_state is
when sstart =>
if (tdre_s='0' and enable='1') then
next_state <= slatch;
else
next_state <= sstart;
end if;
when slatch =>
tsrl_s<='1';
next_state <= swait;
when swait =>
if (enable='1') then
next_state <= sshift;
elsif (bitcount_s="1001") then
next_state <= sstart;
else
next_state <= swait;
end if;
when sshift =>
shift_s<='1';
next_state <= swait;
when others =>
next_state <= sstart;
end case;
end process;
-------------------------------------------------------------------------------
-- FSM2, wait rising_edge(wrn) then assert tdre_s=0 until trsl=1
-------------------------------------------------------------------------------
process(clk,resetn)
begin
if (resetn = '0') then
current_state2 <= s0;
elsif (rising_edge(clk)) then
current_state2 <= next_state2;
end if;
end process;
process (current_state2,tsrl_s,wrn)
begin
case current_state2 is
when s0 =>
tdre_s <='1';
if (wrn='0') then next_state2 <= s1;
else next_state2 <= s0;
end if;
when s1 =>
tdre_s <='1';
if (wrn='1') then next_state2 <= s2;
else next_state2 <= s1;
end if;
when s2 =>
tdre_s <='0';
if (tsrl_s='1') then next_state2 <= s0;
else next_state2 <= s2;
end if;
when others =>
tdre_s <= '1';
next_state2 <= s0;
end case;
end process;
tdre <= tdre_s;
end rtl;
| gpl-2.0 | ff61a42b4c27ba4d07bb7f8ad020ba2d | 0.370705 | 5.244539 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/formatter_struct.vhd | 3 | 5,023 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY formatter IS
PORT(
lutbus : IN std_logic_vector (15 DOWNTO 0);
mux_addr : OUT std_logic_vector (2 DOWNTO 0);
mux_data : OUT std_logic_vector (3 DOWNTO 0);
mux_reg : OUT std_logic_vector (2 DOWNTO 0);
nbreq : OUT std_logic_vector (2 DOWNTO 0)
);
END formatter ;
ARCHITECTURE struct OF formatter IS
-- Architecture declarations
SIGNAL dout : std_logic_vector(15 DOWNTO 0);
SIGNAL dout4 : std_logic_vector(7 DOWNTO 0);
SIGNAL dout5 : std_logic_vector(7 DOWNTO 0);
SIGNAL muxout : std_logic_vector(7 DOWNTO 0);
SIGNAL mw_I1temp_din : std_logic_vector(15 DOWNTO 0);
-- Component Declarations
COMPONENT a_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT d_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (3 DOWNTO 0)
);
END COMPONENT;
COMPONENT m_table
PORT (
ireg : IN std_logic_vector (7 DOWNTO 0);
modrrm : IN std_logic_vector (7 DOWNTO 0);
muxout : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT n_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT r_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
BEGIN
dout <= dout4 & muxout;
mw_I1temp_din <= lutbus;
i1combo_proc: PROCESS (mw_I1temp_din)
VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);
BEGIN
temp_din := mw_I1temp_din(15 DOWNTO 0);
dout5 <= temp_din(7 DOWNTO 0);
dout4 <= temp_din(15 DOWNTO 8);
END PROCESS i1combo_proc;
-- Instance port mappings.
I2 : a_table
PORT MAP (
addr => dout,
dout => mux_addr
);
I3 : d_table
PORT MAP (
addr => dout,
dout => mux_data
);
I6 : m_table
PORT MAP (
ireg => dout4,
modrrm => dout5,
muxout => muxout
);
I4 : n_table
PORT MAP (
addr => dout,
dout => nbreq
);
I5 : r_table
PORT MAP (
addr => dout,
dout => mux_reg
);
END struct;
| gpl-2.0 | 03caac051ed2908de9cb99e2899dbd2a | 0.453514 | 4.500896 | false | false | false | false |
nsauzede/cpu86 | papilio2_vga/ipcore_dir/clk32to40.vhd | 2 | 6,202 | -- file: clk32to40.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____40.000______0.000______50.0______286.298____184.405
-- CLK_OUT2____50.526______0.000______50.0______265.785____184.405
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk32to40 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic
);
end clk32to40;
architecture xilinx of clk32to40 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk32to40,clk_wiz_v3_6,{component_name=clk32to40,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 30,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 24,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 19,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
end xilinx;
| gpl-2.0 | 4306d04d3e8abcce04e977f9bebd8bd6 | 0.596582 | 4.154052 | false | false | false | false |
CamelClarkson/MIPS | Register_File/sources/DFlipFlop.vhd | 2 | 843 | ----------------------------------------------------------------------------------
--D Flip Flop
--By: Kevin Mottler
--Camel Clarkson 32 Bit MIPS Design Group
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Declares the entity DFlipFlop
entity DFlipFlop is
Port (
iClk : in std_logic;
D : in std_logic;
iRst : in std_logic;
Q : out std_logic
);
end DFlipFlop;
architecture Behavioral of DFlipFlop is
begin
--This process statement models the behavior of a DFlipFlop
--This DFlipFLop design includes a asynchronous reset (Active High)
process(iRst, iClk, D)
begin
if (iRst = '1') then
Q <= '0';
elsif (rising_edge(iCLK) and (iCLK = '1') and (iRst = '0')) then
Q <= D;
end if;
end process;
end Behavioral;
| mit | 5f8da52a351697786828b3b7b3178be0 | 0.529063 | 4.173267 | false | false | false | false |
nsauzede/cpu86 | papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/blk_mem_40K_tb.vhd | 2 | 4,474 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: blk_mem_40K_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY blk_mem_40K_tb IS
END ENTITY;
ARCHITECTURE blk_mem_40K_tb_ARCH OF blk_mem_40K_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
blk_mem_40K_synth_inst:ENTITY work.blk_mem_40K_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-2.0 | f1a02c3e679c1340d44f82c509d2d319 | 0.600805 | 4.377691 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/winglcdsndbut.vhd | 2 | 2,546 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:54:20 09/12/2011
-- Design Name:
-- Module Name: winglcdsndbut - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity winglcdsndbut is
Port (
W1A : inout STD_LOGIC_VECTOR (15 downto 0);
W1B : inout STD_LOGIC_VECTOR (15 downto 0);
buttons : out std_logic_vector(5 downto 0);
audio_left : in STD_LOGIC;
audio_right : in STD_LOGIC;
ud : in STD_LOGIC;
rl : in STD_LOGIC;
enab : in STD_LOGIC;
vsync : in STD_LOGIC;
hsync : in STD_LOGIC;
ck : in STD_LOGIC;
r : in std_logic_vector(5 downto 0);
g : in std_logic_vector(5 downto 0);
b : in std_logic_vector(5 downto 0)
);
end winglcdsndbut;
architecture Behavioral of winglcdsndbut is
signal CLK_OUT, clki, clki_n : STD_LOGIC;
begin
w1b(14) <= 'Z';
w1b(15) <= 'Z';
w1a(0) <= 'Z';
w1a(1) <= 'Z';
w1b(0) <= 'Z';
w1b(1) <= 'Z';
buttons(5) <= w1b(14);
buttons(4) <= w1b(15);
buttons(3) <= w1a(0);
buttons(2) <= w1a(1);
buttons(1) <= w1b(0);
buttons(0) <= w1b(1);
w1a(14) <= audio_right;
w1a(15) <= audio_left;
w1a(2) <= ud;
w1b(13) <= rl;
w1a(3) <= enab;
w1b(3) <= vsync;
w1a(13) <= hsync;
-- w1b(2) <= ck;
w1a(10) <= r(5);
w1b(6) <= r(4);
w1a(11) <= r(3);
w1b(5) <= r(2);
w1a(12) <= r(1);
w1b(4) <= r(0);
w1b(9) <= g(5);
w1a(7) <= g(4);
w1b(8) <= g(3);
w1a(8) <= g(2);
w1b(7) <= g(1);
w1a(9) <= g(0);
w1a(4) <= b(5);
w1b(12) <= b(4);
w1a(5) <= b(3);
w1b(11) <= b(2);
w1a(6) <= b(1);
w1b(10) <= b(0);
clkout_oddr : ODDR2
port map
(Q => w1b(2),
C0 => clki,
C1 => clki_n,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
-- Connect the output clocks to the design
-------------------------------------------
clki <= ck;
clki_n <= not clki;
end Behavioral;
| gpl-2.0 | cf3e90d40d72327b4db1c7c5553b5998 | 0.497251 | 2.660397 | false | false | false | false |
CamelClarkson/MIPS | MIPS_Design/Src/ALU1Bit.vhd | 2 | 3,190 | ----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- Email : [email protected]
-- Instructor Name: Dr. Chen Liu
-- Date : 09-25-2016
--
-- Create Date: 09/25/2016 05:35:42 PM
-- Design Name:
-- Module Name: ALU1Bit - ALU1_Func
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU1Bit is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
CIN : in STD_LOGIC;
P3 : in STD_LOGIC; -- Control signal 3
P2 : in STD_LOGIC; -- Conrtol signal 2
P1 : in STD_LOGIC; -- Conrtol signal 1
P0 : in STD_LOGIC; -- Conrtol signal 0
F : out STD_LOGIC;
COUT : out STD_LOGIC);
end ALU1Bit;
architecture ALU1_Func of ALU1Bit is
component LE is --component declaration of Logic Extender
Port (
P3 : in STD_LOGIC;
P2 : in STD_LOGIC;
P1 : in STD_LOGIC;
P0 : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
X : out STD_LOGIC);
end component LE;
component AE is --component declaration of Arithmetic Extender
Port (
P3 : in STD_LOGIC;
P2 : in STD_LOGIC;
P1 : in STD_LOGIC;
P0 : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end component AE;
component FullAdder1Bit is --component declaration of 1 bit full adder
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
CIN : in STD_LOGIC;
SUM : out STD_LOGIC;
COUT : out STD_LOGIC);
end component FullAdder1Bit;
signal X_LE_Adder : STD_LOGIC;
signal Y_AE_Adder : STD_LOGIC;
begin
LE1 : LE port map(
P3 => P3,
P2 => P2,
P1 => P1,
P0 => P0,
A => A ,
B => B ,
X => X_LE_Adder);
AE1 : AE port map(
P3 => P3,
P2 => P2,
P1 => P1,
P0 => P0,
A => A ,
B => B ,
Y => Y_AE_Adder);
FA1 : FullAdder1Bit port map(
A => X_LE_Adder,
B => Y_AE_Adder,
CIN => CIN ,
SUM => F ,
COUT => COUT);
end ALU1_Func;
| mit | bb12086ac7e46caeaf581d945df89c99 | 0.475862 | 3.670886 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/n_table.vhd | 3 | 36,570 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity n_table is
port ( addr : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(2 downto 0));
end n_table;
architecture rtl of n_table is
begin
process(addr)
begin
case addr is
when "1110101100000000" => dout <= "010";
when "1110100100000000" => dout <= "011";
when "1111111111100000" => dout <= "010";
when "1111111100100110" => dout <= "100";
when "1111111100100000" => dout <= "010";
when "1111111101100000" => dout <= "011";
when "1111111110100000" => dout <= "100";
when "1110101000000000" => dout <= "101";
when "1111111100101110" => dout <= "100";
when "1111111100101000" => dout <= "010";
when "1111111101101000" => dout <= "011";
when "1111111110101000" => dout <= "100";
when "1110100000000000" => dout <= "011";
when "1111111111010000" => dout <= "010";
when "1111111100010110" => dout <= "100";
when "1111111100010000" => dout <= "010";
when "1111111101010000" => dout <= "011";
when "1111111110010000" => dout <= "100";
when "1001101000000000" => dout <= "101";
when "1111111100011110" => dout <= "100";
when "1111111100011000" => dout <= "010";
when "1111111101011000" => dout <= "011";
when "1111111110011000" => dout <= "100";
when "1100001100000000" => dout <= "001";
when "1100001000000000" => dout <= "011";
when "1100101100000000" => dout <= "001";
when "1100101000000000" => dout <= "011";
when "0111010000000000" => dout <= "010";
when "0111110000000000" => dout <= "010";
when "0111111000000000" => dout <= "010";
when "0111001000000000" => dout <= "010";
when "0111011000000000" => dout <= "010";
when "0111101000000000" => dout <= "010";
when "0111000000000000" => dout <= "010";
when "0111100000000000" => dout <= "010";
when "0111010100000000" => dout <= "010";
when "0111110100000000" => dout <= "010";
when "0111111100000000" => dout <= "010";
when "0111001100000000" => dout <= "010";
when "0111011100000000" => dout <= "010";
when "0111101100000000" => dout <= "010";
when "0111000100000000" => dout <= "010";
when "0111100100000000" => dout <= "010";
when "1110001100000000" => dout <= "010";
when "1110001000000000" => dout <= "010";
when "1110000100000000" => dout <= "010";
when "1110000000000000" => dout <= "010";
when "1100110100000000" => dout <= "010";
when "1100110000000000" => dout <= "001";
when "1100111000000000" => dout <= "001";
when "1100111100000000" => dout <= "001";
when "1111100000000000" => dout <= "001";
when "1111010100000000" => dout <= "001";
when "1111100100000000" => dout <= "001";
when "1111110000000000" => dout <= "001";
when "1111110100000000" => dout <= "001";
when "1111101000000000" => dout <= "001";
when "1111101100000000" => dout <= "001";
when "1111010000000000" => dout <= "001";
when "1001101100000000" => dout <= "001";
when "1111000000000000" => dout <= "001";
when "1001000000000000" => dout <= "001";
when "0010011000000000" => dout <= "001";
when "0010111000000000" => dout <= "001";
when "0011011000000000" => dout <= "001";
when "0011111000000000" => dout <= "001";
when "1000100011000000" => dout <= "010";
when "1000100000000000" => dout <= "010";
when "1000100001000000" => dout <= "011";
when "1000100010000000" => dout <= "100";
when "1000100000000110" => dout <= "100";
when "1000100111000000" => dout <= "010";
when "1000100100000000" => dout <= "010";
when "1000100101000000" => dout <= "011";
when "1000100110000000" => dout <= "100";
when "1000100100000110" => dout <= "100";
when "1000101011000000" => dout <= "010";
when "1000101000000000" => dout <= "010";
when "1000101001000000" => dout <= "011";
when "1000101010000000" => dout <= "100";
when "1000101000000110" => dout <= "100";
when "1000101111000000" => dout <= "010";
when "1000101100000000" => dout <= "010";
when "1000101101000000" => dout <= "011";
when "1000101110000000" => dout <= "100";
when "1000101100000110" => dout <= "100";
when "1100011000000000" => dout <= "011";
when "1100011001000000" => dout <= "100";
when "1100011010000000" => dout <= "101";
when "1100011000000110" => dout <= "101";
when "1100011100000000" => dout <= "100";
when "1100011101000000" => dout <= "101";
when "1100011110000000" => dout <= "110";
when "1100011100000110" => dout <= "110";
when "1011000000000000" => dout <= "010";
when "1011000100000000" => dout <= "010";
when "1011001000000000" => dout <= "010";
when "1011001100000000" => dout <= "010";
when "1011010000000000" => dout <= "010";
when "1011010100000000" => dout <= "010";
when "1011011000000000" => dout <= "010";
when "1011011100000000" => dout <= "010";
when "1011100000000000" => dout <= "011";
when "1011100100000000" => dout <= "011";
when "1011101000000000" => dout <= "011";
when "1011101100000000" => dout <= "011";
when "1011110000000000" => dout <= "011";
when "1011110100000000" => dout <= "011";
when "1011111000000000" => dout <= "011";
when "1011111100000000" => dout <= "011";
when "1010000000000000" => dout <= "011";
when "1010000100000000" => dout <= "011";
when "1010001000000000" => dout <= "011";
when "1010001100000000" => dout <= "011";
when "1000111011000000" => dout <= "010";
when "1000111000000000" => dout <= "010";
when "1000111001000000" => dout <= "011";
when "1000111010000000" => dout <= "100";
when "1000111000000110" => dout <= "100";
when "1000110011000000" => dout <= "010";
when "1000110000000000" => dout <= "010";
when "1000110001000000" => dout <= "011";
when "1000110010000000" => dout <= "100";
when "1000110000000110" => dout <= "100";
when "1111111100110000" => dout <= "010";
when "1111111101110000" => dout <= "011";
when "1111111110110000" => dout <= "100";
when "1111111100110110" => dout <= "100";
when "0101000000000000" => dout <= "001";
when "0101000100000000" => dout <= "001";
when "0101001000000000" => dout <= "001";
when "0101001100000000" => dout <= "001";
when "0101010000000000" => dout <= "001";
when "0101010100000000" => dout <= "001";
when "0101011000000000" => dout <= "001";
when "0101011100000000" => dout <= "001";
when "0000011000000000" => dout <= "001";
when "0000111000000000" => dout <= "001";
when "0001011000000000" => dout <= "001";
when "0001111000000000" => dout <= "001";
when "1000111100000000" => dout <= "010";
when "1000111101000000" => dout <= "011";
when "1000111110000000" => dout <= "100";
when "1000111100000110" => dout <= "100";
when "1000111111000000" => dout <= "010";
when "0101100000000000" => dout <= "001";
when "0101100100000000" => dout <= "001";
when "0101101000000000" => dout <= "001";
when "0101101100000000" => dout <= "001";
when "0101110000000000" => dout <= "001";
when "0101110100000000" => dout <= "001";
when "0101111000000000" => dout <= "001";
when "0101111100000000" => dout <= "001";
when "0000011100000000" => dout <= "001";
when "0001011100000000" => dout <= "001";
when "0001111100000000" => dout <= "001";
when "1000011011000000" => dout <= "010";
when "1000011000000000" => dout <= "010";
when "1000011001000000" => dout <= "011";
when "1000011010000000" => dout <= "100";
when "1000011000000110" => dout <= "100";
when "1000011111000000" => dout <= "010";
when "1000011100000000" => dout <= "010";
when "1000011101000000" => dout <= "011";
when "1000011110000000" => dout <= "100";
when "1000011100000110" => dout <= "100";
when "1001000100000000" => dout <= "001";
when "1001001000000000" => dout <= "001";
when "1001001100000000" => dout <= "001";
when "1001010000000000" => dout <= "001";
when "1001010100000000" => dout <= "001";
when "1001011000000000" => dout <= "001";
when "1001011100000000" => dout <= "001";
when "1110010000000000" => dout <= "010";
when "1110010100000000" => dout <= "010";
when "1110110000000000" => dout <= "001";
when "1110110100000000" => dout <= "001";
when "1110011000000000" => dout <= "010";
when "1110011100000000" => dout <= "010";
when "1110111100000000" => dout <= "001";
when "1110111000000000" => dout <= "001";
when "1101011100000000" => dout <= "001";
when "1001111100000000" => dout <= "001";
when "1001111000000000" => dout <= "001";
when "1001110000000000" => dout <= "001";
when "1001110100000000" => dout <= "001";
when "1000110100000110" => dout <= "100";
when "1000110111000000" => dout <= "010";
when "1000110100000000" => dout <= "010";
when "1000110101000000" => dout <= "011";
when "1000110110000000" => dout <= "100";
when "1100010100000110" => dout <= "100";
when "1100010100000000" => dout <= "010";
when "1100010101000000" => dout <= "011";
when "1100010110000000" => dout <= "100";
when "1100010000000110" => dout <= "100";
when "1100010000000000" => dout <= "010";
when "1100010001000000" => dout <= "011";
when "1100010010000000" => dout <= "100";
when "0000000011000000" => dout <= "010";
when "0000000000000110" => dout <= "100";
when "0000000000000000" => dout <= "010";
when "0000000001000000" => dout <= "011";
when "0000000010000000" => dout <= "100";
when "0000000111000000" => dout <= "010";
when "0000000100000110" => dout <= "100";
when "0000000100000000" => dout <= "010";
when "0000000101000000" => dout <= "011";
when "0000000110000000" => dout <= "100";
when "0000001011000000" => dout <= "010";
when "0000001000000110" => dout <= "100";
when "0000001000000000" => dout <= "010";
when "0000001001000000" => dout <= "011";
when "0000001010000000" => dout <= "100";
when "0000001111000000" => dout <= "010";
when "0000001100000110" => dout <= "100";
when "0000001100000000" => dout <= "010";
when "0000001101000000" => dout <= "011";
when "0000001110000000" => dout <= "100";
when "1000000011000000" => dout <= "011";
when "1000000000000110" => dout <= "101";
when "1000000000000000" => dout <= "011";
when "1000000001000000" => dout <= "100";
when "1000000010000000" => dout <= "101";
when "1000000111000000" => dout <= "100";
when "1000000100000110" => dout <= "110";
when "1000000100000000" => dout <= "100";
when "1000000101000000" => dout <= "101";
when "1000000110000000" => dout <= "110";
when "1000001111000000" => dout <= "011";
when "1000001100000110" => dout <= "101";
when "1000001100000000" => dout <= "011";
when "1000001101000000" => dout <= "100";
when "1000001110000000" => dout <= "101";
when "0000010000000000" => dout <= "010";
when "0000010100000000" => dout <= "011";
when "0001000011000000" => dout <= "010";
when "0001000000000110" => dout <= "100";
when "0001000000000000" => dout <= "010";
when "0001000001000000" => dout <= "011";
when "0001000010000000" => dout <= "100";
when "0001000111000000" => dout <= "010";
when "0001000100000110" => dout <= "100";
when "0001000100000000" => dout <= "010";
when "0001000101000000" => dout <= "011";
when "0001000110000000" => dout <= "100";
when "0001001011000000" => dout <= "010";
when "0001001000000110" => dout <= "100";
when "0001001000000000" => dout <= "010";
when "0001001001000000" => dout <= "011";
when "0001001010000000" => dout <= "100";
when "0001001111000000" => dout <= "010";
when "0001001100000110" => dout <= "100";
when "0001001100000000" => dout <= "010";
when "0001001101000000" => dout <= "011";
when "0001001110000000" => dout <= "100";
when "1000000011010000" => dout <= "011";
when "1000000000010110" => dout <= "101";
when "1000000000010000" => dout <= "011";
when "1000000001010000" => dout <= "100";
when "1000000010010000" => dout <= "101";
when "1000000111010000" => dout <= "100";
when "1000000100010110" => dout <= "110";
when "1000000100010000" => dout <= "100";
when "1000000101010000" => dout <= "101";
when "1000000110010000" => dout <= "110";
when "1000001111010000" => dout <= "011";
when "1000001100010110" => dout <= "101";
when "1000001100010000" => dout <= "011";
when "1000001101010000" => dout <= "100";
when "1000001110010000" => dout <= "101";
when "0001010000000000" => dout <= "010";
when "0001010100000000" => dout <= "011";
when "0010100011000000" => dout <= "010";
when "0010100000000110" => dout <= "100";
when "0010100000000000" => dout <= "010";
when "0010100001000000" => dout <= "011";
when "0010100010000000" => dout <= "100";
when "0010100111000000" => dout <= "010";
when "0010100100000110" => dout <= "100";
when "0010100100000000" => dout <= "010";
when "0010100101000000" => dout <= "011";
when "0010100110000000" => dout <= "100";
when "0010101011000000" => dout <= "010";
when "0010101000000110" => dout <= "100";
when "0010101000000000" => dout <= "010";
when "0010101001000000" => dout <= "011";
when "0010101010000000" => dout <= "100";
when "0010101111000000" => dout <= "010";
when "0010101100000110" => dout <= "100";
when "0010101100000000" => dout <= "010";
when "0010101101000000" => dout <= "011";
when "0010101110000000" => dout <= "100";
when "1000000011101000" => dout <= "011";
when "1000000000101110" => dout <= "101";
when "1000000000101000" => dout <= "011";
when "1000000001101000" => dout <= "100";
when "1000000010101000" => dout <= "101";
when "1000000111101000" => dout <= "100";
when "1000000100101110" => dout <= "110";
when "1000000100101000" => dout <= "100";
when "1000000101101000" => dout <= "101";
when "1000000110101000" => dout <= "110";
when "1000001111101000" => dout <= "011";
when "1000001100101110" => dout <= "101";
when "1000001100101000" => dout <= "011";
when "1000001101101000" => dout <= "100";
when "1000001110101000" => dout <= "101";
when "0010110000000000" => dout <= "010";
when "0010110100000000" => dout <= "011";
when "0001100011000000" => dout <= "010";
when "0001100000000110" => dout <= "100";
when "0001100000000000" => dout <= "010";
when "0001100001000000" => dout <= "011";
when "0001100010000000" => dout <= "100";
when "0001100111000000" => dout <= "010";
when "0001100100000110" => dout <= "100";
when "0001100100000000" => dout <= "010";
when "0001100101000000" => dout <= "011";
when "0001100110000000" => dout <= "100";
when "0001101011000000" => dout <= "010";
when "0001101000000110" => dout <= "100";
when "0001101000000000" => dout <= "010";
when "0001101001000000" => dout <= "011";
when "0001101010000000" => dout <= "100";
when "0001101111000000" => dout <= "010";
when "0001101100000110" => dout <= "100";
when "0001101100000000" => dout <= "010";
when "0001101101000000" => dout <= "011";
when "0001101110000000" => dout <= "100";
when "1000000011011000" => dout <= "011";
when "1000000000011110" => dout <= "101";
when "1000000000011000" => dout <= "011";
when "1000000001011000" => dout <= "100";
when "1000000010011000" => dout <= "101";
when "1000000111011000" => dout <= "100";
when "1000000100011110" => dout <= "110";
when "1000000100011000" => dout <= "100";
when "1000000101011000" => dout <= "101";
when "1000000110011000" => dout <= "110";
when "1000001111011000" => dout <= "011";
when "1000001100011110" => dout <= "101";
when "1000001100011000" => dout <= "011";
when "1000001101011000" => dout <= "100";
when "1000001110011000" => dout <= "101";
when "0001110000000000" => dout <= "010";
when "0001110100000000" => dout <= "011";
when "1111111011000000" => dout <= "010";
when "1111111000000110" => dout <= "100";
when "1111111000000000" => dout <= "010";
when "1111111001000000" => dout <= "011";
when "1111111010000000" => dout <= "100";
when "1111111100000110" => dout <= "100";
when "1111111100000000" => dout <= "010";
when "1111111101000000" => dout <= "011";
when "1111111110000000" => dout <= "100";
when "0100000000000000" => dout <= "001";
when "0100000100000000" => dout <= "001";
when "0100001000000000" => dout <= "001";
when "0100001100000000" => dout <= "001";
when "0100010000000000" => dout <= "001";
when "0100010100000000" => dout <= "001";
when "0100011000000000" => dout <= "001";
when "0100011100000000" => dout <= "001";
when "1111111011001000" => dout <= "010";
when "1111111000001110" => dout <= "100";
when "1111111000001000" => dout <= "010";
when "1111111001001000" => dout <= "011";
when "1111111010001000" => dout <= "100";
when "1111111100001110" => dout <= "100";
when "1111111100001000" => dout <= "010";
when "1111111101001000" => dout <= "011";
when "1111111110001000" => dout <= "100";
when "0100100000000000" => dout <= "001";
when "0100100100000000" => dout <= "001";
when "0100101000000000" => dout <= "001";
when "0100101100000000" => dout <= "001";
when "0100110000000000" => dout <= "001";
when "0100110100000000" => dout <= "001";
when "0100111000000000" => dout <= "001";
when "0100111100000000" => dout <= "001";
when "0011101011000000" => dout <= "010";
when "0011101000000110" => dout <= "100";
when "0011101000000000" => dout <= "010";
when "0011101001000000" => dout <= "011";
when "0011101010000000" => dout <= "100";
when "0011101111000000" => dout <= "010";
when "0011101100000110" => dout <= "100";
when "0011101100000000" => dout <= "010";
when "0011101101000000" => dout <= "011";
when "0011101110000000" => dout <= "100";
when "0011100000000110" => dout <= "100";
when "0011100000000000" => dout <= "010";
when "0011100001000000" => dout <= "011";
when "0011100010000000" => dout <= "100";
when "0011100011000000" => dout <= "010";
when "0011100100000110" => dout <= "100";
when "0011100100000000" => dout <= "010";
when "0011100101000000" => dout <= "011";
when "0011100110000000" => dout <= "100";
when "0011100111000000" => dout <= "010";
when "1000000011111000" => dout <= "011";
when "1000000000111110" => dout <= "101";
when "1000000000111000" => dout <= "011";
when "1000000001111000" => dout <= "100";
when "1000000010111000" => dout <= "101";
when "1000000111111000" => dout <= "100";
when "1000000100111110" => dout <= "110";
when "1000000100111000" => dout <= "100";
when "1000000101111000" => dout <= "101";
when "1000000110111000" => dout <= "110";
when "1000001111111000" => dout <= "011";
when "1000001100111110" => dout <= "101";
when "1000001100111000" => dout <= "011";
when "1000001101111000" => dout <= "100";
when "1000001110111000" => dout <= "101";
when "0011110000000000" => dout <= "010";
when "0011110100000000" => dout <= "011";
when "1111011011011000" => dout <= "010";
when "1111011000011110" => dout <= "100";
when "1111011000011000" => dout <= "010";
when "1111011001011000" => dout <= "011";
when "1111011010011000" => dout <= "100";
when "1111011111011000" => dout <= "010";
when "1111011100011110" => dout <= "100";
when "1111011100011000" => dout <= "010";
when "1111011101011000" => dout <= "011";
when "1111011110011000" => dout <= "100";
when "0011011100000000" => dout <= "001";
when "0010011100000000" => dout <= "001";
when "0011111100000000" => dout <= "001";
when "0010111100000000" => dout <= "001";
when "1111011011100000" => dout <= "010";
when "1111011000100110" => dout <= "100";
when "1111011000100000" => dout <= "010";
when "1111011001100000" => dout <= "011";
when "1111011010100000" => dout <= "100";
when "1111011111100000" => dout <= "010";
when "1111011100100110" => dout <= "100";
when "1111011100100000" => dout <= "010";
when "1111011101100000" => dout <= "011";
when "1111011110100000" => dout <= "100";
when "1111011011101000" => dout <= "010";
when "1111011000101110" => dout <= "100";
when "1111011000101000" => dout <= "010";
when "1111011001101000" => dout <= "011";
when "1111011010101000" => dout <= "100";
when "1111011111101000" => dout <= "010";
when "1111011100101110" => dout <= "100";
when "1111011100101000" => dout <= "010";
when "1111011101101000" => dout <= "011";
when "1111011110101000" => dout <= "100";
when "1111011011110000" => dout <= "010";
when "1111011000110110" => dout <= "100";
when "1111011000110000" => dout <= "010";
when "1111011001110000" => dout <= "011";
when "1111011010110000" => dout <= "100";
when "1111011111110000" => dout <= "010";
when "1111011100110110" => dout <= "100";
when "1111011100110000" => dout <= "010";
when "1111011101110000" => dout <= "011";
when "1111011110110000" => dout <= "100";
when "1111011011111000" => dout <= "010";
when "1111011000111110" => dout <= "100";
when "1111011000111000" => dout <= "010";
when "1111011001111000" => dout <= "011";
when "1111011010111000" => dout <= "100";
when "1111011111111000" => dout <= "010";
when "1111011100111110" => dout <= "100";
when "1111011100111000" => dout <= "010";
when "1111011101111000" => dout <= "011";
when "1111011110111000" => dout <= "100";
when "1101010000000000" => dout <= "010";
when "1101010100000000" => dout <= "010";
when "1001100000000000" => dout <= "001";
when "1001100100000000" => dout <= "001";
when "1101000011000000" => dout <= "010";
when "1101000000000110" => dout <= "100";
when "1101000000000000" => dout <= "010";
when "1101000001000000" => dout <= "011";
when "1101000010000000" => dout <= "100";
when "1101000111000000" => dout <= "010";
when "1101000100000110" => dout <= "100";
when "1101000100000000" => dout <= "010";
when "1101000101000000" => dout <= "011";
when "1101000110000000" => dout <= "100";
when "1101001011000000" => dout <= "010";
when "1101001000000110" => dout <= "100";
when "1101001000000000" => dout <= "010";
when "1101001001000000" => dout <= "011";
when "1101001010000000" => dout <= "100";
when "1101001111000000" => dout <= "010";
when "1101001100000110" => dout <= "100";
when "1101001100000000" => dout <= "010";
when "1101001101000000" => dout <= "011";
when "1101001110000000" => dout <= "100";
when "0010000011000000" => dout <= "010";
when "0010000000000110" => dout <= "100";
when "0010000000000000" => dout <= "010";
when "0010000001000000" => dout <= "011";
when "0010000010000000" => dout <= "100";
when "0010000111000000" => dout <= "010";
when "0010000100000110" => dout <= "100";
when "0010000100000000" => dout <= "010";
when "0010000101000000" => dout <= "011";
when "0010000110000000" => dout <= "100";
when "0010001011000000" => dout <= "010";
when "0010001000000110" => dout <= "100";
when "0010001000000000" => dout <= "010";
when "0010001001000000" => dout <= "011";
when "0010001010000000" => dout <= "100";
when "0010001111000000" => dout <= "010";
when "0010001100000110" => dout <= "100";
when "0010001100000000" => dout <= "010";
when "0010001101000000" => dout <= "011";
when "0010001110000000" => dout <= "100";
when "1000000011100000" => dout <= "011";
when "1000000000100110" => dout <= "101";
when "1000000000100000" => dout <= "011";
when "1000000001100000" => dout <= "100";
when "1000000010100000" => dout <= "101";
when "1000000111100000" => dout <= "100";
when "1000000100100110" => dout <= "110";
when "1000000100100000" => dout <= "100";
when "1000000101100000" => dout <= "101";
when "1000000110100000" => dout <= "110";
when "1000001111100000" => dout <= "011";
when "1000001100100110" => dout <= "101";
when "1000001100100000" => dout <= "011";
when "1000001101100000" => dout <= "100";
when "1000001110100000" => dout <= "101";
when "0010010000000000" => dout <= "010";
when "0010010100000000" => dout <= "011";
when "0000100000000110" => dout <= "100";
when "0000100000000000" => dout <= "010";
when "0000100001000000" => dout <= "011";
when "0000100010000000" => dout <= "100";
when "0000100011000000" => dout <= "010";
when "0000100100000110" => dout <= "100";
when "0000100100000000" => dout <= "010";
when "0000100101000000" => dout <= "011";
when "0000100110000000" => dout <= "100";
when "0000100111000000" => dout <= "010";
when "0000101011000000" => dout <= "010";
when "0000101000000110" => dout <= "100";
when "0000101000000000" => dout <= "010";
when "0000101001000000" => dout <= "011";
when "0000101010000000" => dout <= "100";
when "0000101111000000" => dout <= "010";
when "0000101100000110" => dout <= "100";
when "0000101100000000" => dout <= "010";
when "0000101101000000" => dout <= "011";
when "0000101110000000" => dout <= "100";
when "1000000011001000" => dout <= "011";
when "1000000000001110" => dout <= "101";
when "1000000000001000" => dout <= "011";
when "1000000001001000" => dout <= "100";
when "1000000010001000" => dout <= "101";
when "1000000111001000" => dout <= "100";
when "1000000100001110" => dout <= "110";
when "1000000100001000" => dout <= "100";
when "1000000101001000" => dout <= "101";
when "1000000110001000" => dout <= "110";
when "1000001111001000" => dout <= "011";
when "1000001100001110" => dout <= "101";
when "1000001100001000" => dout <= "011";
when "1000001101001000" => dout <= "100";
when "1000001110001000" => dout <= "101";
when "0000110000000000" => dout <= "010";
when "0000110100000000" => dout <= "011";
when "1000010000000110" => dout <= "100";
when "1000010000000000" => dout <= "010";
when "1000010001000000" => dout <= "011";
when "1000010010000000" => dout <= "100";
when "1000010100000110" => dout <= "100";
when "1000010100000000" => dout <= "010";
when "1000010101000000" => dout <= "011";
when "1000010110000000" => dout <= "100";
when "1000010011000000" => dout <= "010";
when "1000010111000000" => dout <= "010";
when "1111011011000000" => dout <= "011";
when "1111011000000110" => dout <= "101";
when "1111011000000000" => dout <= "011";
when "1111011001000000" => dout <= "100";
when "1111011010000000" => dout <= "101";
when "1111011111000000" => dout <= "100";
when "1111011100000110" => dout <= "110";
when "1111011100000000" => dout <= "100";
when "1111011101000000" => dout <= "101";
when "1111011110000000" => dout <= "110";
when "1010100000000000" => dout <= "010";
when "1010100100000000" => dout <= "011";
when "0011000000000110" => dout <= "100";
when "0011000000000000" => dout <= "010";
when "0011000001000000" => dout <= "011";
when "0011000010000000" => dout <= "100";
when "0011000011000000" => dout <= "010";
when "0011000100000110" => dout <= "100";
when "0011000100000000" => dout <= "010";
when "0011000101000000" => dout <= "011";
when "0011000110000000" => dout <= "100";
when "0011000111000000" => dout <= "010";
when "0011001011000000" => dout <= "010";
when "0011001000000110" => dout <= "100";
when "0011001000000000" => dout <= "010";
when "0011001001000000" => dout <= "011";
when "0011001010000000" => dout <= "100";
when "0011001111000000" => dout <= "010";
when "0011001100000110" => dout <= "100";
when "0011001100000000" => dout <= "010";
when "0011001101000000" => dout <= "011";
when "0011001110000000" => dout <= "100";
when "1000000011110000" => dout <= "011";
when "1000000000110110" => dout <= "101";
when "1000000000110000" => dout <= "011";
when "1000000001110000" => dout <= "100";
when "1000000010110000" => dout <= "101";
when "1000000111110000" => dout <= "100";
when "1000000100110110" => dout <= "110";
when "1000000100110000" => dout <= "100";
when "1000000101110000" => dout <= "101";
when "1000000110110000" => dout <= "110";
when "1000001111110000" => dout <= "011";
when "1000001100110110" => dout <= "101";
when "1000001100110000" => dout <= "011";
when "1000001101110000" => dout <= "100";
when "1000001110110000" => dout <= "101";
when "0011010000000000" => dout <= "010";
when "0011010100000000" => dout <= "011";
when "1111011011010000" => dout <= "010";
when "1111011000010110" => dout <= "100";
when "1111011000010000" => dout <= "010";
when "1111011001010000" => dout <= "011";
when "1111011010010000" => dout <= "100";
when "1111011111010000" => dout <= "010";
when "1111011100010110" => dout <= "100";
when "1111011100010000" => dout <= "010";
when "1111011101010000" => dout <= "011";
when "1111011110010000" => dout <= "100";
when "1010010000000000" => dout <= "001";
when "1010010100000000" => dout <= "001";
when "1010011000000000" => dout <= "001";
when "1010011100000000" => dout <= "001";
when "1010111000000000" => dout <= "001";
when "1010111100000000" => dout <= "001";
when "1010110000000000" => dout <= "001";
when "1010110100000000" => dout <= "001";
when "1010101000000000" => dout <= "001";
when "1010101100000000" => dout <= "001";
when "1111001000000000" => dout <= "001";
when "1111001100000000" => dout <= "001";
when "0110000000000000" => dout <= "001";
when "0110000100000000" => dout <= "001";
when "1100100000000000" => dout <= "001";
when "1100100100000000" => dout <= "001";
when "0110001000000000" => dout <= "001";
when "0110110000000000" => dout <= "010";
when "0110110100000000" => dout <= "001";
when "0110111000000000" => dout <= "001";
when "0110111100000000" => dout <= "001";
when "0000111100000000" => dout <= "001";
when "0110001100000000" => dout <= "001";
when "0110010000000000" => dout <= "001";
when "0110010100000000" => dout <= "001";
when "0110011000000000" => dout <= "001";
when "0110011100000000" => dout <= "001";
when "1000001000000000" => dout <= "001";
when "1101011000000000" => dout <= "001";
when "1111000100000000" => dout <= "001";
when "1100000000000000" => dout <= "001";
when "1100000100000000" => dout <= "001";
when others => dout <= "111";
end case;
end process;
end rtl; | gpl-2.0 | 9080b31869a66b1ddb17560a5f264a8a | 0.526524 | 4.301341 | false | false | false | false |
CamelClarkson/MIPS | Register_File/sources/W_Decoder.vhd | 1 | 3,389 | ----------------------------------------------------------------------------------
--MIPS Register File Test Bench
--By: Kevin Mottler
--Camel Clarkson 32 Bit MIPS Design Group
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decoder is
Port (
i_w_Addr : in std_logic_vector(4 downto 0);
o_w_Addr : out std_logic_vector(31 downto 0)
);
end Decoder;
architecture Behavioral of Decoder is
begin
process(i_w_Addr)
begin
case i_w_Addr is
when "00000" =>
o_w_Addr <= "00000000000000000000000000000001";
when "00001" =>
o_w_Addr <= "00000000000000000000000000000010";
when "00010" =>
o_w_Addr <= "00000000000000000000000000000100";
when "00011" =>
o_w_Addr <= "00000000000000000000000000001000";
when "00100" =>
o_w_Addr <= "00000000000000000000000000010000";
when "00101" =>
o_w_Addr <= "00000000000000000000000000100000";
when "00110" =>
o_w_Addr <= "00000000000000000000000001000000";
when "00111" =>
o_w_Addr <= "00000000000000000000000010000000";
when "01000" =>
o_w_Addr <= "00000000000000000000000100000000";
when "01001" =>
o_w_Addr <= "00000000000000000000001000000000";
when "01010" =>
o_w_Addr <= "00000000000000000000010000000000";
when "01011" =>
o_w_Addr <= "00000000000000000000100000000000";
when "01100" =>
o_w_Addr <= "00000000000000000001000000000000";
when "01101" =>
o_w_Addr <= "00000000000000000010000000000000";
when "01110" =>
o_w_Addr <= "00000000000000000100000000000000";
when "01111" =>
o_w_Addr <= "00000000000000001000000000000000";
when "10000" =>
o_w_Addr <= "00000000000000010000000000000000";
when "10001" =>
o_w_Addr <= "00000000000000100000000000000000";
when "10010" =>
o_w_Addr <= "00000000000001000000000000000000";
when "10011" =>
o_w_Addr <= "00000000000010000000000000000000";
when "10100" =>
o_w_Addr <= "00000000000100000000000000000000";
when "10101" =>
o_w_Addr <= "00000000001000000000000000000000";
when "10110" =>
o_w_Addr <= "00000000010000000000000000000000";
when "10111" =>
o_w_Addr <= "00000000100000000000000000000000";
when "11000" =>
o_w_Addr <= "00000001000000000000000000000000";
when "11001" =>
o_w_Addr <= "00000010000000000000000000000000";
when "11010" =>
o_w_Addr <= "00000100000000000000000000000000";
when "11011" =>
o_w_Addr <= "00001000000000000000000000000000";
when "11100" =>
o_w_Addr <= "00010000000000000000000000000000";
when "11101" =>
o_w_Addr <= "00100000000000000000000000000000";
when "11110" =>
o_w_Addr <= "01000000000000000000000000000000";
when "11111" =>
o_w_Addr <= "10000000000000000000000000000000";
when others =>
o_w_Addr <= "00000000000000000000000000000000";
end case;
end process;
end Behavioral;
| mit | 0c938105aa33fde3584ddb99da79f8dc | 0.612275 | 4.661623 | false | false | false | false |
mithro/vhdl-triple-buffer | hdl/triple_buffer_arbiter.vhd | 1 | 4,874 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:18:22 07/06/2014
-- Design Name:
-- Module Name: triple_buffer_arbiter - triple_buffer_arbiter_arch
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity triple_buffer_arbiter is
generic (
offset : integer;
size : integer;
addr : integer := 32);
port (
input_clk : in std_logic;
output_clk : in std_logic;
input_addr : out unsigned(addr-1 downto 0);
output_addr : out unsigned(addr-1 downto 0);
rst : in std_logic);
end triple_buffer_arbiter;
architecture triple_buffer_arbiter_arch of triple_buffer_arbiter is
constant lock_initial : unsigned(1 downto 0) := "11";
signal input_lock: unsigned(1 downto 0);
signal output_lock: unsigned(1 downto 0);
signal n0_buffer: unsigned(1 downto 0);
signal n1_buffer: unsigned(1 downto 0);
signal n2_buffer: unsigned(1 downto 0);
constant buffer0: unsigned(1 downto 0) := "00";
constant buffer1: unsigned(1 downto 0) := "01";
constant buffer2: unsigned(1 downto 0) := "10";
constant buffer0_addr : unsigned(addr-1 downto 0) := to_unsigned(offset, addr);
constant buffer1_addr : unsigned(addr-1 downto 0) := to_unsigned(offset + size, addr);
constant buffer2_addr : unsigned(addr-1 downto 0) := to_unsigned(offset + size * 2, addr);
signal okay: std_logic := '1';
begin
okay_process: process (input_lock) is
begin
case n2_buffer & n1_buffer & n0_buffer is
when buffer0 & buffer1 & buffer2 =>
okay <= '1';
when buffer2 & buffer0 & buffer1 =>
okay <= '1';
when buffer1 & buffer2 & buffer0 =>
okay <= '1';
when buffer0 & buffer2 & buffer1 =>
okay <= '1';
when buffer1 & buffer0 & buffer2 =>
okay <= '1';
when buffer2 & buffer1 & buffer0 =>
okay <= '1';
when others =>
okay <= '0';
end case;
end process okay_process;
-- Locking a buffer for input generates the address on input_addr
input_addr_process: process (input_lock) is
begin
case input_lock is
when buffer0 =>
input_addr <= buffer0_addr;
when buffer1 =>
input_addr <= buffer1_addr;
when buffer2 =>
input_addr <= buffer2_addr;
when others =>
input_addr <= "UUUUUUUU";
end case;
end process input_addr_process;
-- Locking a buffer for output generates the address on output_addr
output_addr_process: process (output_lock) is
begin
case output_lock is
when buffer0 =>
output_addr <= buffer0_addr;
when buffer1 =>
output_addr <= buffer1_addr;
when buffer2 =>
output_addr <= buffer2_addr;
when others =>
output_addr <= "UUUUUUUU";
end case;
end process output_addr_process;
input_process: process (input_clk, rst) is
begin
-- Reset
if rising_edge(rst) then
input_lock <= lock_initial;
n0_buffer <= buffer2;
n1_buffer <= buffer1;
n2_buffer <= buffer0;
end if;
-- On falling edge, update buffer ages and unlock.
if falling_edge(input_clk) then
-- Update buffer ages
if (n2_buffer /= output_lock) then
n2_buffer <= n1_buffer;
end if;
n1_buffer <= n0_buffer;
n0_buffer <= input_lock;
-- Unlock the buffers
input_lock <= lock_initial;
end if;
-- On falling edge, unlock buffers.
if rising_edge(input_clk) then
-- Figure out the oldest unlocked buffer to use.
if (n2_buffer /= output_lock) then
input_lock <= n2_buffer;
else
input_lock <= n1_buffer;
end if;
end if;
end process input_process;
output_process: process (output_clk, rst) is
begin
-- Reset
if rising_edge(rst) then
output_lock <= lock_initial;
end if;
-- On falling edge, unlock buffer.
if falling_edge(output_clk) then
output_lock <= lock_initial;
end if;
-- On rising edge, find the newest buffer and lock for reading.
if rising_edge(output_clk) then
-- Figure out the newest buffer to use.
if (n0_buffer /= input_lock) then
output_lock <= n0_buffer;
else
output_lock <= n1_buffer;
end if;
end if;
end process output_process;
end triple_buffer_arbiter_arch;
| apache-2.0 | 88565598d42c71ce9bfa504101ca0c78 | 0.606278 | 3.717773 | false | false | false | false |
Jawanga/ece385lab9 | lab9_soc/lab9_soc_inst.vhd | 1 | 2,880 | component lab9_soc is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
led_wire_export : out std_logic_vector(7 downto 0); -- export
sdram_wire_addr : out std_logic_vector(12 downto 0); -- addr
sdram_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_wire_cas_n : out std_logic; -- cas_n
sdram_wire_cke : out std_logic; -- cke
sdram_wire_cs_n : out std_logic; -- cs_n
sdram_wire_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- dq
sdram_wire_dqm : out std_logic_vector(3 downto 0); -- dqm
sdram_wire_ras_n : out std_logic; -- ras_n
sdram_wire_we_n : out std_logic; -- we_n
sdram_clk_clk : out std_logic; -- clk
to_hw_port_export : out std_logic_vector(7 downto 0); -- export
to_hw_sig_export : out std_logic_vector(1 downto 0); -- export
to_sw_port_export : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
to_sw_sig_export : in std_logic_vector(1 downto 0) := (others => 'X') -- export
);
end component lab9_soc;
u0 : component lab9_soc
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
led_wire_export => CONNECTED_TO_led_wire_export, -- led_wire.export
sdram_wire_addr => CONNECTED_TO_sdram_wire_addr, -- sdram_wire.addr
sdram_wire_ba => CONNECTED_TO_sdram_wire_ba, -- .ba
sdram_wire_cas_n => CONNECTED_TO_sdram_wire_cas_n, -- .cas_n
sdram_wire_cke => CONNECTED_TO_sdram_wire_cke, -- .cke
sdram_wire_cs_n => CONNECTED_TO_sdram_wire_cs_n, -- .cs_n
sdram_wire_dq => CONNECTED_TO_sdram_wire_dq, -- .dq
sdram_wire_dqm => CONNECTED_TO_sdram_wire_dqm, -- .dqm
sdram_wire_ras_n => CONNECTED_TO_sdram_wire_ras_n, -- .ras_n
sdram_wire_we_n => CONNECTED_TO_sdram_wire_we_n, -- .we_n
sdram_clk_clk => CONNECTED_TO_sdram_clk_clk, -- sdram_clk.clk
to_hw_port_export => CONNECTED_TO_to_hw_port_export, -- to_hw_port.export
to_hw_sig_export => CONNECTED_TO_to_hw_sig_export, -- to_hw_sig.export
to_sw_port_export => CONNECTED_TO_to_sw_port_export, -- to_sw_port.export
to_sw_sig_export => CONNECTED_TO_to_sw_sig_export -- to_sw_sig.export
);
| apache-2.0 | 74cb384a3418cefbbbfef43a95751323 | 0.487153 | 3.127036 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Key_Generation/rc5_key.vhd | 1 | 6,674 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
USE WORK.RC5_PKG.ALL;
entity rc5_key is
port( clr : in std_logic;
clk : in std_logic;
key : in std_logic_vector(127 downto 0);
key_vld : in std_logic;
skey : out rc5_rom_26;
key_rdy : out std_logic);
end rc5_key;
architecture key_exp of rc5_key is
signal i_cnt : std_logic_vector(04 downto 00); -- s_array counter
signal j_cnt : std_logic_vector(04 downto 00); -- l_array counter
signal r_cnt : std_logic_vector(06 downto 00); -- overall counterer; counts to 78
signal a : std_logic_vector(31 downto 00);
signal a_circ : std_logic_vector(31 downto 00);
signal a_reg : std_logic_vector(31 downto 00); -- register A
signal b : std_logic_vector(31 downto 00);
signal b_circ : std_logic_vector(31 downto 00);
signal b_reg : std_logic_vector(31 downto 00); -- register B
signal temp : std_logic_vector(31 downto 00);
--Key Expansion state machine has five states: idle, key in, expansion and ready
signal state : rc5_key_StateType;
signal l : rc5_rom_4;
signal s : rc5_rom_26;
begin
-- it is not a data-dependent rotation!
--A = S[i] = (S[i] + A + B) <<< 3;
a <= s(conv_integer(i_cnt)) + a_reg + b_reg; --S + A + B
a_circ <= a(28 downto 0) & a(31 downto 29); --rot by 3
-- this is a data-dependent rotation!
--B = L[j] = (L[j] + A + B) <<< (A + B);
b <= l(conv_integer(j_cnt)) + a_circ + b_reg; --L + A + B
-- rot by A + B
temp <= a_circ + b_reg;
with temp(4 downto 0) select
b_circ <= b(30 downto 0) & b(31) when "00001", --01
b(29 downto 0) & b(31 downto 30) when "00010", --02
b(28 downto 0) & b(31 downto 29) when "00011", --03
b(27 downto 0) & b(31 downto 28) when "00100", --04
b(26 downto 0) & b(31 downto 27) when "00101", --05
b(25 downto 0) & b(31 downto 26) when "00110", --06
b(24 downto 0) & b(31 downto 25) when "00111", --07
b(23 downto 0) & b(31 downto 24) when "01000", --08
b(22 downto 0) & b(31 downto 23) when "01001", --09
b(21 downto 0) & b(31 downto 22) when "01010", --10
b(20 downto 0) & b(31 downto 21) when "01011", --11
b(19 downto 0) & b(31 downto 20) when "01100", --12
b(18 downto 0) & b(31 downto 19) when "01101", --13
b(17 downto 0) & b(31 downto 18) when "01110", --14
b(16 downto 0) & b(31 downto 17) when "01111", --15
b(15 downto 0) & b(31 downto 16) when "10000", --16
b(14 downto 0) & b(31 downto 15) when "10001", --17
b(13 downto 0) & b(31 downto 14) when "10010", --18
b(12 downto 0) & b(31 downto 13) when "10011", --19
b(11 downto 0) & b(31 downto 12) when "10100", --20
b(10 downto 0) & b(31 downto 11) when "10101", --21
b(09 downto 0) & b(31 downto 10) when "10110", --22
b(08 downto 0) & b(31 downto 09) when "10111", --23
b(07 downto 0) & b(31 downto 08) when "11000", --24
b(06 downto 0) & b(31 downto 07) when "11001", --25
b(05 downto 0) & b(31 downto 06) when "11010", --26
b(04 downto 0) & b(31 downto 05) when "11011", --27
b(03 downto 0) & b(31 downto 04) when "11100", --28
b(02 downto 0) & b(31 downto 03) when "11101", --29
b(01 downto 0) & b(31 downto 02) when "11110", --30
b(0) & b(31 downto 01) when "11111", --31
b when others;
state_block:
process(clr, clk)
begin
if (clr = '0') then
state <= st_idle;
elsif (rising_edge(clk)) then
case state is
when st_idle =>
if(key_vld = '1') then
state <= st_key_in;
end if;
when st_key_in =>
state <= st_key_exp;
when st_key_exp =>
if (r_cnt = "1001101") then
state <= st_ready;
end if;
when st_ready =>
state <= st_idle;
end case;
end if;
end process;
a_reg_block:
process(clr, clk)
begin
if(clr = '0') then
a_reg <= (others => '0');
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
a_reg <= a_circ;
end if;
end if;
end process;
b_reg_block:
process(clr, clk)
begin
if(clr = '0') then
b_reg <= (others => '0');
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
b_reg <= b_circ;
end if;
end if;
end process;
s_array_counter_block:
process(clr, clk)
begin
if(clr='0') then i_cnt<=(others=>'0');
elsif(rising_edge(clk)) then
if(state=ST_KEY_EXP) then
if(i_cnt="11001") then i_cnt <= (others=>'0');
else i_cnt <= i_cnt + 1;
end if;
end if;
end if;
end process;
l_array_counter_block:
process(clr, clk)
begin
if(clr='0') then j_cnt<=(others=>'0');
elsif(rising_edge(clk)) then
if(j_cnt="00011") then j_cnt<=(others=>'0');
else j_cnt <= j_cnt + 1;
end if;
end if;
end process;
overall_counter_block:
process(clr, clk)
begin
if (clr = '0') then
r_cnt <= "0000000";
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
r_cnt <= r_cnt + 1;
end if;
end if;
end process;
--S[0] = 0xB7E15163 (Pw)
--for i=1 to 25 do S[i] = S[i-1]+ 0x9E3779B9 (Qw)
--array s
process(clr, clk)
begin
if (clr = '0') then
s(0) <= X"b7e15163"; s(1) <= X"5618cb1c";s(2) <= X"f45044d5";
s(3) <= X"9287be8e";s(4) <= X"30bf3847";s(5) <= X"cef6b200";
s(6) <= X"6d2e2bb9";s(7) <= X"0b65a572";s(8) <= X"a99d1f2b";
s(9) <= X"47d498e4";s(10) <= X"e60c129d";s(11) <= X"84438c56";
s(12) <= X"227b060f";s(13) <= X"c0b27fc8";s(14) <= X"5ee9f981";
s(15) <= X"fd21733a";s(16) <= X"9b58ecf3";s(17) <= X"399066ac";
s(18) <= X"d7c7e065";s(19) <= X"75ff5a1e";s(20) <= X"1436d3d7";
s(21) <= X"b26e4d90";s(22) <= X"50a5c749";s(23) <= X"eedd4102";
s(24) <= X"8d14babb";s(25) <= X"2b4c3474";
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
s(conv_integer(i_cnt)) <= a_circ;--i = (i + 1) mod 26;
end if;
end if;
end process;
--l array
process(clr, clk)
begin
if(clr = '0') then
l(0) <= (others=>'0');
l(1) <= (others=>'0');
l(2) <= (others=>'0');
l(3) <= (others=>'0');
elsif (rising_edge(clk)) then
if(state = st_key_in) then
l(0) <= key(31 downto 0);
l(1) <= key(63 downto 32);
l(2) <= key(95 downto 64);
l(3) <= key(127 downto 96);
elsif(state = st_key_exp) then
l(conv_integer(j_cnt)) <= b_circ; --j = (j + 1) mod 4;
end if;
end if;
end process;
skey <= s;
with state select
key_rdy <= '1' when st_ready,
'0' when others;
end key_exp; | lgpl-2.1 | 3c2df679b610242f4872b30dfff52aeb | 0.546149 | 2.52803 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/lcdctl.vhd | 1 | 4,588 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lcdctl is
Port ( clk,reset : in STD_LOGIC;
vramaddr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ud : out STD_LOGIC;
rl : out STD_LOGIC;
enab : out STD_LOGIC;
vsync : out STD_LOGIC;
hsync : out STD_LOGIC;
ck : out STD_LOGIC;
r : out std_logic_vector(5 downto 0);
g : out std_logic_vector(5 downto 0);
b : out std_logic_vector(5 downto 0)
);
end lcdctl;
architecture Behavioral of lcdctl is
signal clk_fast : std_logic := '0';
signal ired : std_logic_vector(5 downto 0) := "000000";
signal igreen : std_logic_vector(5 downto 0) := "000000";
signal iblue : std_logic_vector(5 downto 0) := "000000";
signal fg_r : std_logic_vector(5 downto 0) := "000000";
signal fg_g : std_logic_vector(5 downto 0) := "000000";
signal fg_b : std_logic_vector(5 downto 0) := "000000";
signal bg_r : std_logic_vector(5 downto 0) := "000000";
signal bg_g : std_logic_vector(5 downto 0) := "000000";
signal bg_b : std_logic_vector(5 downto 0) := "000000";
signal lcdvsync : STD_LOGIC;
signal lcdhsync : STD_LOGIC;
signal char_addr: std_logic_vector(6 downto 0);
signal char_attr: std_logic_vector(7 downto 0) := x"42";
signal attr_not_char: std_logic := '1';
signal rom_addr: std_logic_vector(10 downto 0);
signal row_addr: std_logic_vector(3 downto 0);
signal bit_addr: std_logic_vector(2 downto 0);
signal font_word: std_logic_vector(7 downto 0);
signal font_bit: std_logic;
signal video_on: std_logic;
signal dout: std_logic_vector(7 downto 0) := "01100010";
signal addr_read: std_logic_vector(12 downto 0);
signal pixel_x, pixel_y: std_logic_vector(9 downto 0);
signal ipixel_x, ipixel_y: std_logic_vector(9 downto 0);
begin
ud <= '1';
rl <= '1';
enab <= '0';
ck <= clk_fast;
r <= ired;
g <= igreen;
b <= iblue;
hsync<=lcdhsync;
vsync<=lcdvsync;
sync0: entity work.vga_sync
port map(
clock=>clk_fast,
reset=>reset,
hsync=>lcdhsync, vsync=>lcdvsync,
video_on=>video_on,
pixel_tick=>open,
pixel_x=>pixel_x, pixel_y=>pixel_y
);
-- instantiate frame buffer
-- frame_buffer_unit: entity work.blk_mem_gen_v7_3
-- port map (
-- clka => clk,
-- wea => (others => '0'),
-- addra => (others => '0'),
-- dina => (others => '0'),
-- clkb => clk,
-- addrb => addr_read,
-- doutb => dout
-- );
vramaddr <= "000" & addr_read;
dout <= vramdata;
-- instantiate font ROM
font_unit: entity work.font_rom
port map(
clock => clk_fast,
addr => rom_addr,
data => font_word
);
-- tile RAM read
-- addr_read <= ((pixel_y(9 downto 4) & "000000") + ("00" & pixel_y(9 downto 4) & "0000") + ("00000" & pixel_x(9 downto 3))) & attr_not_char;
addr_read <= ((pixel_y(9 downto 4) * "000101") + ("00000" & pixel_x(9 downto 3))) & attr_not_char;
process(clk,clk_fast,video_on)
begin
if rising_edge(clk) then
if video_on='0' then
attr_not_char <= '0';
clk_fast <= '0';
else
if clk_fast='0' then
char_attr <= dout(7 downto 0);
attr_not_char <= '1';
else
char_addr <= dout(6 downto 0);
attr_not_char <= '0';
end if;
end if;
clk_fast <= not clk_fast;
end if;
end process;
fg_r <= (others => '1') when char_attr(0)='1' else (others => '0');
fg_g <= (others => '1') when char_attr(1)='1' else (others => '0');
fg_b <= (others => '1') when char_attr(2)='1' else (others => '0');
bg_r <= (others => '1') when char_attr(3)='1' else (others => '0');
bg_g <= (others => '1') when char_attr(4)='1' else (others => '0');
bg_b <= (others => '1') when char_attr(5)='1' else (others => '0');
-- font ROM interface
row_addr <= pixel_y(3 downto 0);
rom_addr <= char_addr & row_addr;
-- bit_addr <= std_logic_vector(unsigned(pixel_x(2 downto 0)) - 1);
bit_addr <= std_logic_vector(unsigned(pixel_x(2 downto 0))-2);
font_bit <= font_word(to_integer(unsigned(not bit_addr)));
-- rgb multiplexing
process(font_bit,video_on,fg_r,fg_g,fg_b,bg_r,bg_g,bg_b)
begin
if video_on='0' then
ired <= (others => '0');
igreen <= (others => '0');
iblue <= (others => '0');
elsif font_bit = '1' then
ired <= fg_r;
igreen <= fg_g;
iblue <= fg_b;
-- ired <= (others => '1');
-- igreen <= (others => '1');
-- iblue <= (others => '1');
else
ired <= bg_r;
igreen <= bg_g;
iblue <= bg_b;
-- ired <= (others => '0');
-- igreen <= (others => '0');
-- iblue <= (others => '0');
end if;
end process;
end Behavioral;
| gpl-2.0 | ced42dc243a8f19322d933992dc121a9 | 0.592197 | 2.687756 | false | false | false | false |
CamelClarkson/MIPS | MIPS_Design/Src/ALU.vhd | 2 | 11,912 | ----------------------------------------------------------------------------------
-- Clarkson University
-- CAMEL INTEREST GROUP
-- Project Name: MIPS, 32-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- Email : [email protected]
-- Instructor Name: Dr. Chen Liu
-- Date : 09-25-2016
--
-- Create Date: 09/25/2016 04:25:05 PM
-- Design Name:
-- Module Name: ALU - ALU_Func
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port ( A : in STD_LOGIC_VECTOR (31 downto 0); -- operands 1
B : in STD_LOGIC_VECTOR (31 downto 0); -- operands 2
P3 : in STD_LOGIC; -- Control signal 3
P2 : in STD_LOGIC; -- Conrtol signal 2
P1 : in STD_LOGIC; -- Conrtol signal 1
P0 : in STD_LOGIC; -- Conrtol signal 0
F : out STD_LOGIC_VECTOR (31 downto 0); -- ALU result
COUT : out STD_LOGIC; -- carry out
Overflow : out STD_LOGIC; -- overflow flag, which masks the overflow caused by slt
ZERO : out STD_LOGIC); -- zero flag
end ALU;
architecture ALU_Func of ALU is
signal C : STD_LOGIC_VECTOR (32 downto 0);
signal F_pre : STD_LOGIC_VECTOR (31 downto 0);
signal F_wire : STD_LOGIC_VECTOR (31 downto 0);
signal Overflow_wire : STD_LOGIC; -- overflow before mask,used to connect with Overflow module and slt mux module
signal SltOpVal_wire : STD_LOGIC; -- from slt mux module to overflow module
component ALU1Bit is --component declaration of 1 bit ALU
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
P3 : in STD_LOGIC;
P2 : in STD_LOGIC;
P1 : in STD_LOGIC;
P0 : in STD_LOGIC;
CIN : in STD_LOGIC;
F : out STD_LOGIC;
COUT : out STD_LOGIC);
end component ALU1Bit;
component CarryinAnd is --component declaration of carry in
Port (
P2 : in STD_LOGIC;
P1 : in STD_LOGIC;
C0 : out STD_LOGIC);
end component CarryinAnd;
component Overflow_gen is --component declaration of overflow
Port (
C31 : in STD_LOGIC;
C32 : in STD_LOGIC;
SltOpVal : in STD_LOGIC;
Overflow_slt : out STD_LOGIC;
Overflow : out STD_LOGIC);
end component Overflow_gen;
component ConnectionBuffer1Bit is
Port ( A : in STD_LOGIC;
B : out STD_LOGIC);
end component ConnectionBuffer1Bit;
component ConnectionBuffer32Bit is
Port ( A : in STD_LOGIC_VECTOR (31 downto 0);
B : out STD_LOGIC_VECTOR (31 downto 0));
end component ConnectionBuffer32Bit;
component SLT_MUX is
Port ( F_pre : in STD_LOGIC_VECTOR (31 downto 0); -- before merge in the slt
P3 : in STD_LOGIC;
P2 : in STD_LOGIC;
P1 : in STD_LOGIC;
P0 : in STD_LOGIC;
Overflow : in STD_LOGIC;
SltOpVal : out STD_LOGIC;
F : out STD_LOGIC_VECTOR (31 downto 0)); --after merge in the slt
end component SLT_MUX;
component Zero_Flag_Gen is
Port ( F : in STD_LOGIC_VECTOR (31 downto 0);
ZERO : out STD_LOGIC);
end component Zero_Flag_Gen;
begin
ALU1_0 : ALU1Bit port map(
A => A(0),
B => B(0),
CIN => C(0),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(0),
COUT => C(1));
ALU1_1 : ALU1Bit port map(
A => A(1),
B => B(1),
CIN => C(1),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(1),
COUT => C(2));
ALU1_2 : ALU1Bit port map(
A => A(2),
B => B(2),
CIN => C(2),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(2),
COUT => C(3));
ALU1_3 : ALU1Bit port map(
A => A(3),
B => B(3),
CIN => C(3),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(3),
COUT => C(4));
ALU1_4 : ALU1Bit port map(
A => A(4),
B => B(4),
CIN => C(4),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(4),
COUT => C(5));
ALU1_5 : ALU1Bit port map(
A => A(5),
B => B(5),
CIN => C(5),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(5),
COUT => C(6));
ALU1_6 : ALU1Bit port map(
A => A(6),
B => B(6),
CIN => C(6),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(6),
COUT => C(7));
ALU1_7 : ALU1Bit port map(
A => A(7),
B => B(7),
CIN => C(7),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(7),
COUT => C(8));
ALU1_8 : ALU1Bit port map(
A => A(8),
B => B(8),
CIN => C(8),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(8),
COUT => C(9));
ALU1_9 : ALU1Bit port map(
A => A(9),
B => B(9),
CIN => C(9),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(9),
COUT => C(10));
ALU1_10 : ALU1Bit port map(
A => A(10),
B => B(10),
CIN => C(10),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(10),
COUT => C(11));
ALU1_11 : ALU1Bit port map(
A => A(11),
B => B(11),
CIN => C(11),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(11),
COUT => C(12));
ALU1_12 : ALU1Bit port map(
A => A(12),
B => B(12),
CIN => C(12),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(12),
COUT => C(13));
ALU1_13 : ALU1Bit port map(
A => A(13),
B => B(13),
CIN => C(13),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(13),
COUT => C(14));
ALU1_14 : ALU1Bit port map(
A => A(14),
B => B(14),
CIN => C(14),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(14),
COUT => C(15));
ALU1_15 : ALU1Bit port map(
A => A(15),
B => B(15),
CIN => C(15),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(15),
COUT => C(16));
ALU1_16 : ALU1Bit port map(
A => A(16),
B => B(16),
CIN => C(16),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(16),
COUT => C(17));
ALU1_17 : ALU1Bit port map(
A => A(17),
B => B(17),
CIN => C(17),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(17),
COUT => C(18));
ALU1_18 : ALU1Bit port map(
A => A(18),
B => B(18),
CIN => C(18),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(18),
COUT => C(19));
ALU1_19 : ALU1Bit port map(
A => A(19),
B => B(19),
CIN => C(19),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(19),
COUT => C(20));
ALU1_20 : ALU1Bit port map(
A => A(20),
B => B(20),
CIN => C(20),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(20),
COUT => C(21));
ALU1_21 : ALU1Bit port map(
A => A(21),
B => B(21),
CIN => C(21),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(21),
COUT => C(22));
ALU1_22 : ALU1Bit port map(
A => A(22),
B => B(22),
CIN => C(22),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(22),
COUT => C(23));
ALU1_23 : ALU1Bit port map(
A => A(23),
B => B(23),
CIN => C(23),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(23),
COUT => C(24));
ALU1_24 : ALU1Bit port map(
A => A(24),
B => B(24),
CIN => C(24),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(24),
COUT => C(25));
ALU1_25 : ALU1Bit port map(
A => A(25),
B => B(25),
CIN => C(25),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(25),
COUT => C(26));
ALU1_26 : ALU1Bit port map(
A => A(26),
B => B(26),
CIN => C(26),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(26),
COUT => C(27));
ALU1_27 : ALU1Bit port map(
A => A(27),
B => B(27),
CIN => C(27),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(27),
COUT => C(28));
ALU1_28 : ALU1Bit port map(
A => A(28),
B => B(28),
CIN => C(28),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(28),
COUT => C(29));
ALU1_29 : ALU1Bit port map(
A => A(29),
B => B(29),
CIN => C(29),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(29),
COUT => C(30));
ALU1_30 : ALU1Bit port map(
A => A(30),
B => B(30),
CIN => C(30),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(30),
COUT => C(31));
ALU1_31 : ALU1Bit port map(
A => A(31),
B => B(31),
CIN => C(31),
P3 => P3 ,
P2 => P2 ,
P1 => P1 ,
P0 => P0 ,
F => F_pre(31),
COUT => C(32));
CA : CarryinAnd port map(
P2 => P2 ,
P1 => P1 ,
C0 => C(0));
OFXS : Overflow_gen port map(
C31 => C(31),
C32 => C(32),
SltOpVal => SltOpVal_wire,
Overflow_slt => Overflow_wire, --connect between the overflow and slt
Overflow => Overflow); --output to outside of ALU
CBuffer1 : ConnectionBuffer1Bit port map(
A => C(32),
B => COUT);
SLTM : SLT_MUX Port map(
F_pre => F_pre(31 downto 0),
P3 => P3,
P2 => P2,
P1 => p1,
P0 => P0,
Overflow => Overflow_wire,
SltOpVal => SltOpVal_wire,
F => F_wire(31 downto 0));
ZFG :Zero_Flag_Gen Port map(
F => F_wire(31 downto 0), -- use F will be better.
ZERO => ZERO);
FBuffer32 : ConnectionBuffer32Bit port map(
A => F_wire(31 downto 0),
B => F(31 downto 0));
end ALU_Func;
| mit | 106d5d578c6719a996e4e89b8a96b341 | 0.390363 | 2.841603 | false | false | false | false |
nsauzede/cpu86 | top_rtl/cpu86_top_struct.vhd | 1 | 9,019 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Instantiate CPU86 + Opencores 16750 UART --
-- UART 16750 by Sebastian Witt --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all; -- Change to numeric packages...
USE IEEE.std_logic_unsigned.all;
ENTITY cpu86_top IS
PORT(
clock_40mhz : IN std_logic;
cts : IN std_logic := '1';
reset : IN std_logic;
rxd : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
rts : OUT std_logic;
txd : OUT std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
cpuerror : OUT std_logic;
led2n : OUT std_logic; -- Connected to 16750 OUT1 signal
led3n : OUT std_logic; -- Connected to 16750 OUT2 signal
csramn : OUT std_logic;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
rdn : OUT std_logic;
resoutn : OUT std_logic;
wrn : OUT std_logic
);
END cpu86_top ;
ARCHITECTURE struct OF cpu86_top IS
-- Architecture declarations
signal csromn : std_logic;
-- Internal signal declarations
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL clk : std_logic;
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0);
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL sel_s : std_logic_vector(1 DOWNTO 0);
SIGNAL resoutn_s : std_logic;
SIGNAL dbus_out_s : std_logic_vector (7 DOWNTO 0);
SIGNAL abus_s : std_logic_vector (19 DOWNTO 0);
SIGNAL wrn_s : std_logic;
SIGNAL rdn_s : std_logic;
SIGNAL rxclk_s : std_logic;
-- Component Declarations
COMPONENT cpu86
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END COMPONENT;
COMPONENT uart_top
PORT (
BR_clk : IN std_logic ;
CTSn : IN std_logic := '1';
DCDn : IN std_logic := '1';
DSRn : IN std_logic := '1';
RIn : IN std_logic := '1';
abus : IN std_logic_vector (2 DOWNTO 0);
clk : IN std_logic ;
csn : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic ;
resetn : IN std_logic ;
sRX : IN std_logic ;
wrn : IN std_logic ;
B_CLK : OUT std_logic ;
DTRn : OUT std_logic ;
IRQ : OUT std_logic ;
OUT1n : OUT std_logic ;
OUT2n : OUT std_logic ;
RTSn : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
stx : OUT std_logic
);
END COMPONENT;
COMPONENT bootstrap
PORT (
abus : IN std_logic_vector (7 DOWNTO 0);
dbus : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
process(sel_s,dbus_com1,dbus_in,dbus_rom)
begin
case sel_s is
when "01" => dbus_in_cpu <= dbus_com1; -- UART
when "10" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when others=> dbus_in_cpu <= dbus_in; -- Embedded SRAM
end case;
end process;
clk <= clock_40mhz;
-- por <= reset;
por <= NOT(reset);
abus <= abus_s;
resoutn <= resoutn_s;
dbus_out <= dbus_out_s;
wrn <= wrn_s;
rdn <= rdn_s;
-- wrcom <= not wrn_s;
sel_s <= cscom1 & csromn;
-- chip_select
-- Comport, uart_16750, address 0x3F8-0x3FF
cscom1 <= '0' when (abus_s(15 downto 3)="0000001111111" AND iom='1') else '1';
-- Bootstrap ROM 256 bytes, address FFFFF-FF=FFF00
csromn <= '0' when ((abus_s(19 downto 8)=X"FFF") AND iom='0') else '1';
-- SRAM 1MByte-256 bytes for the bootstrap
csramn <='0' when (csromn='1' AND iom='0') else '1';
nmi <= '0';
intr <= '0';
DCDn <= '0';
DSRn <= '0';
RIn <= '0';
-- Instance port mappings.
U_1 : cpu86
PORT MAP (
clk => clk,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus_s,
cpuerror => cpuerror,
dbus_out => dbus_out_s,
inta => OPEN,
iom => iom,
rdn => rdn_s,
resoutn => resoutn_s,
wran => OPEN,
wrn => wrn_s
);
U_0 : uart_top
PORT MAP (
BR_clk => rxclk_s,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
abus => abus_s(2 DOWNTO 0),
clk => clk,
csn => cscom1,
dbus_in => dbus_out_s,
rdn => rdn_s,
resetn => resoutn_s,
sRX => RXD,
wrn => wrn_s,
B_CLK => rxclk_s,
DTRn => OPEN,
IRQ => OPEN,
OUT1n => led2n,
OUT2n => led3n,
RTSn => RTS,
dbus_out => dbus_com1,
stx => TXD
);
U_11 : bootstrap
PORT MAP (
abus => abus_s(7 DOWNTO 0),
dbus => dbus_rom
);
END struct;
| gpl-2.0 | 170360762ad34788cd2cf13d5076ebcd | 0.417674 | 4.146667 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/uart_receiver.vhd | 3 | 12,675 | --
-- UART receiver
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART receiver
entity uart_receiver is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
RXCLK : in std_logic; -- Receiver clock (16x baudrate)
RXCLEAR : in std_logic; -- Reset receiver state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
SIN : in std_logic; -- Receiver input
PE : out std_logic; -- Parity error
FE : out std_logic; -- Framing error
BI : out std_logic; -- Break interrupt
DOUT : out std_logic_vector(7 downto 0); -- Output data
RXFINISHED : out std_logic -- Receiver operation finished
);
end uart_receiver;
architecture rtl of uart_receiver is
-- Majority voting logic
component slib_mv_filter is
generic (
WIDTH : natural := 4;
THRESHOLD : natural := 10
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
SAMPLE : in std_logic; -- Clock enable for sample process
CLEAR : in std_logic; -- Reset process
D : in std_logic; -- Signal input
Q : out std_logic -- Signal D was at least THRESHOLD samples high
);
end component;
-- Counter
component slib_counter is
generic (
WIDTH : natural := 4 -- Counter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear counter register
LOAD : in std_logic; -- Load counter register
ENABLE : in std_logic; -- Enable count operation
DOWN : in std_logic; -- Count direction down
D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input
Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output
OVERFLOW : out std_logic -- Counter overflow
);
end component;
-- FSM
type state_type is (IDLE, START, DATA, PAR, STOP, MWAIT);
signal CState, NState : state_type;
-- Signals
signal iBaudCountClear : std_logic; -- Baud counter clear
signal iBaudStep : std_logic; -- Next symbol pulse
signal iBaudStepD : std_logic; -- Next symbol pulse delayed by one clock
signal iFilterClear : std_logic; -- Reset input filter
signal iFSIN : std_logic; -- Filtered SIN
signal iParity : std_logic; -- Data parity
signal iParityReceived : std_logic; -- Parity received
signal iDataCount : integer range 0 to 8; -- Data bit counter
signal iDataCountInit : std_logic; -- Initialize data bit counter to word length
signal iDataCountFinish : std_logic; -- Data bit counter finished
signal iRXFinished : std_logic; -- Word received, output data valid
signal iFE : std_logic; -- Internal frame error
signal iBI : std_logic; -- Internal break interrupt
signal iNoStopReceived : std_logic; -- No valid stop bit received
signal iDOUT : std_logic_vector(7 downto 0); -- Data output
begin
-- Baudrate counter: RXCLK/16
RX_BRC: slib_counter generic map (
WIDTH => 4
) port map (
CLK => CLK,
RST => RST,
CLEAR => iBaudCountClear,
LOAD => '0',
ENABLE => RXCLK,
DOWN => '0',
D => x"0",
OVERFLOW => iBaudStep
);
-- Input filter
RX_MVF: slib_mv_filter generic map (
WIDTH => 4,
THRESHOLD => 10
) port map (
CLK => CLK,
RST => RST,
SAMPLE => RXCLK,
CLEAR => iFilterClear,
D => SIN,
Q => iFSIN
);
-- iBaudStepD
RX_IFC: process (CLK, RST)
begin
if (RST = '1') then
iBaudStepD <= '0';
elsif (CLK'event and CLK = '1') then
iBaudStepD <= iBaudStep;
end if;
end process;
iFilterClear <= iBaudStepD or iBaudCountClear;
-- Parity generation
RX_PAR: process (iDOUT, EPS)
begin
iParity <= iDOUT(7) xor iDOUT(6) xor iDOUT(5) xor iDOUT(4) xor iDOUT(3) xor iDOUT(2) xor iDOUT(1) xor iDOUT(0) xor not EPS;
end process;
-- Data bit capture
RX_DATACOUNT: process (CLK, RST)
begin
if (RST = '1') then
iDataCount <= 0;
iDOUT <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iDataCountInit = '1') then
iDataCount <= 0;
iDOUT <= (others => '0');
else
if (iBaudStep = '1' and iDataCountFinish = '0') then
iDOUT(iDataCount) <= iFSIN;
iDataCount <= iDataCount + 1;
end if;
end if;
end if;
end process;
iDataCountFinish <= '1' when (WLS = "00" and iDataCount = 5) or
(WLS = "01" and iDataCount = 6) or
(WLS = "10" and iDataCount = 7) or
(WLS = "11" and iDataCount = 8) else '0';
-- FSM update process
RX_FSMUPDATE: process (CLK, RST)
begin
if (RST = '1') then
CState <= IDLE;
elsif (CLK'event and CLK = '1') then
CState <= NState;
end if;
end process;
-- RX FSM
RX_FSM: process (CState, SIN, iFSIN, iBaudStep, iDataCountFinish, PEN, WLS, STB)
begin
-- Defaults
NState <= IDLE;
iBaudCountClear <= '0';
iDataCountInit <= '0';
iRXFinished <= '0';
case CState is
when IDLE => if (SIN = '0') then -- Start detected
NState <= START;
end if;
iBaudCountClear <= '1';
iDataCountInit <= '1';
when START => iDataCountInit <= '1';
if (iBaudStep = '1') then -- Wait for start bit end
if (iFSIN = '0') then
NState <= DATA;
end if;
else
NState <= START;
end if;
when DATA => if (iDataCountFinish = '1') then -- Received all data bits
if (PEN = '1') then
NState <= PAR; -- Parity enabled
else
NState <= STOP; -- No parity
end if;
else
NState <= DATA;
end if;
when PAR => if (iBaudStep = '1') then -- Wait for parity bit
NState <= STOP;
else
NState <= PAR;
end if;
when STOP => if (iBaudStep = '1') then -- Wait for stop bit
if (iFSIN = '0') then -- No stop bit received
iRXFinished <= '1';
NState <= MWAIT;
else
iRXFinished <= '1';
NState <= IDLE; -- Stop bit end
end if;
else
NState <= STOP;
end if;
when MWAIT => if (SIN = '0') then -- Wait for mark
NState <= MWAIT;
end if;
when others => null;
end case;
end process;
-- Check parity
RX_PARCHECK: process (CLK, RST)
begin
if (RST = '1') then
PE <= '0';
iParityReceived <= '0';
elsif (CLK'event and CLK = '1') then
if (CState = PAR and iBaudStep = '1') then
iParityReceived <= iFSIN; -- Received parity bit
end if;
-- Check parity
if (PEN = '1') then -- Parity enabled
PE <= '0';
if (SP = '1') then -- Sticky parity
if ((EPS xor iParityReceived) = '0') then
PE <= '1'; -- Parity error
end if;
else
if (iParity /= iParityReceived) then
PE <= '1'; -- Parity error
end if;
end if;
else
PE <= '0'; -- Parity disabled
iParityReceived <= '0';
end if;
end if;
end process;
-- Framing error and break interrupt
iNoStopReceived <= '1' when iFSIN = '0' and (CState = STOP) else '0';
iBI <= '1' when iDOUT = "00000000" and
iParityReceived = '0' and
iNoStopReceived = '1' else '0';
iFE <= '1' when iNoStopReceived = '1' else '0';
-- Output signals
DOUT <= iDOUT;
BI <= iBI;
FE <= iFE;
RXFINISHED <= iRXFinished;
end rtl;
| gpl-2.0 | 6b32380f79db221f260dc0603ff80563 | 0.391243 | 5.468076 | false | false | false | false |
CamelClarkson/MIPS | MIPS_Design/Sim/Top_Level_TB.vhd | 1 | 1,826 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/11/2016 01:36:23 PM
-- Design Name:
-- Module Name: Top_Level_TB - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Top_Level_TB is
-- Port ( );
end Top_Level_TB;
architecture Behavioral of Top_Level_TB is
component Top_Level is
Port (
iClk : in std_logic;
iRst : in std_logic;
iCommand32 : in std_logic_vector(31 downto 0);
oResult1 : out std_logic_vector(31 downto 0);
oResult2 : out std_logic_vector(31 downto 0)
);
end component;
signal s_Clk : std_logic := '1';
signal s_Rst : std_logic;
signal s_Command32 : std_logic_vector(31 downto 0);
signal s_Result1 : std_logic_vector(31 downto 0);
signal s_Result2 : std_logic_vector(31 downto 0);
begin
s_Clk <= not s_Clk after 10 ns;
DUT: Top_Level
port map(
iClk => s_Clk,
iRst => s_Rst,
iCommand32 => s_Command32,
oResult1 => s_Result1,
oResult2 => s_Result2
);
Test: process
begin
s_Rst <= '1';
wait for 10 ns;
s_Rst <= '0';
s_Command32 <= "00000010001100100100000000100000";
wait for 10 ns;
wait;
end process;
end Behavioral;
| mit | 12a70ea553942f256720566469869278 | 0.583242 | 3.566406 | false | false | false | false |
nsauzede/cpu86 | papilio2_drigmorn1/ipcore_dir/blk_mem_40K/example_design/blk_mem_40K_exdes.vhd | 2 | 4,790 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_40K_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_40K_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END blk_mem_40K_exdes;
ARCHITECTURE xilinx OF blk_mem_40K_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT blk_mem_40K IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : blk_mem_40K
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| gpl-2.0 | e68b979ff5de4d17197ba372810f3c6a | 0.547808 | 4.497653 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Basys2Encryption/ARCHIVE/rc5_enc_working.vhd | 1 | 6,685 | --RC5 Encryption
--A = A + S[0];
--B = B + S[1];
--for i=1 to 12 do
----A = ((A XOR B) <<< B) + S[2*i];
----B = ((B XOR A) <<< A) + S[2*1+1];
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
ENTITY rc5 IS
PORT (
-- Asynchronous reset and 25HzClock Signal
clr,clk_25 : IN STD_LOGIC;
--0 for encryption 1 for decryption
enc : IN STD_LOGIC;
-- 8-bit input
din_lower : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- Input is Valid
di_vld : IN STD_LOGIC;
-- 7 Segment Display-bit output
segment_a_i : OUT STD_LOGIC;
segment_b_i : OUT STD_LOGIC;
segment_c_i : OUT STD_LOGIC;
segment_d_i : OUT STD_LOGIC;
segment_e_i : OUT STD_LOGIC;
segment_f_i : OUT STD_LOGIC;
segment_g_i : OUT STD_LOGIC;
-- 7 Segment Control
--Control Which of the four 7-Segment Display is active
AN : OUT STD_LOGIC_VECTOR(3 downto 0);
--Output is Ready
do_rdy : OUT STD_LOGIC;
--In Decryption Mode
dec_mode : OUT STD_LOGIC
);
END rc5;
ARCHITECTURE rtl OF rc5 IS
SIGNAL din : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL i_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); -- round counter
SIGNAL ab_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_pre : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register A
SIGNAL ba_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_pre : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register B
type rc5_rom_26 is array (0 to 25) of std_logic_vector(31 downto 0);
CONSTANT skey :rc5_rom_26:=rc5_rom_26'(
X"9BBBD8C8", X"1A37F7FB", X"46F8E8C5", X"460C6085",
X"70F83B8A", X"284B8303", X"513E1454", X"F621ED22",
X"3125065D", X"11A83A5D", X"D427686B", X"713AD82D",
X"4B792F99", X"2799A4DD", X"A7901C49", X"DEDE871A",
X"36C03196", X"A7EFC249", X"61A78BB8", X"3B0A1D2B",
X"4DBFCA76", X"AE162167", X"30D76B0A", X"43192304",
X"F6CC1431", X"65046380");
-- RC5 state machine has five states: idle, pre_round, round and ready
TYPE StateType IS(
ST_IDLE, -- In this state RC5 is ready for input
ST_PRE_ROUND, -- In this state RC5 pre-round op is performed
ST_ROUND_OP, -- In this state RC5 round op is performed. 12 rounds
ST_POST_ROUND, -- In this state RC5 post-round op is performed
ST_READY -- In this state RC5 has completed encryption
);
SIGNAL state : StateType;
--LED Control
SIGNAL hex_digit_i : STD_LOGIC_VECTOR(3 DOWNTO 0);
--Count to flash the LED
SIGNAL LED_flash_cnt : STD_LOGIC_VECTOR(9 DOWNTO 0);
BEGIN
din <= X"00000000000000" & din_lower;
-- A=((A XOR B)<<<B) + S[2*i];
ab_xor <= a_reg XOR b_reg;
--A <<< B
ROT_A_LEFT : ENTITY work.rotLeft
PORT MAP(clr=>clr,clk=>clk_25, din=>ab_xor,amnt=>b_reg(4 DOWNTO 0),dout=>a_rot);
--A = A + S[0]
a_pre<=din(63 DOWNTO 32) + skey(0);
-- S[2*i]
a<=a_rot + skey(CONV_INTEGER(i_cnt & '0'));
-- B=((B XOR A) <<<A) + S[2*i+1]
ba_xor <= b_reg XOR a;
--B <<< A
ROT_B_LEFT : ENTITY work.rotLeft
PORT MAP(clr=>clr,clk=>clk_25, din=>ba_xor,amnt=>a(4 DOWNTO 0),dout=>b_rot);
--B = B + S[1]
b_pre<=din(31 DOWNTO 0) + skey(1);
-- S[2*i+1]
b<=b_rot + skey(CONV_INTEGER(i_cnt & '1'));
A_register:
PROCESS(clr, clk_25) BEGIN
IF(clr='1') THEN
a_reg<=din(63 DOWNTO 32);
ELSIF(rising_edge(clk_25)) THEN
IF(state=ST_PRE_ROUND) THEN
a_reg<=a_pre;
ELSIF(state=ST_ROUND_OP) THEN
a_reg<=a;
END IF;
END IF;
END PROCESS;
B_register:
PROCESS(clr, clk_25) BEGIN
IF(clr='1') THEN
b_reg<=din(31 DOWNTO 0);
ELSIF(rising_edge(clk_25)) THEN
IF(state=ST_PRE_ROUND) THEN
b_reg<=b_pre;
ELSIF(state=ST_ROUND_OP) THEN
b_reg<=b;
END IF;
END IF;
END PROCESS;
State_Control:
PROCESS(clr, clk_25)
BEGIN
IF(clr='1') THEN
state<=ST_IDLE;
ELSIF(rising_edge(clk_25)) THEN
CASE state IS
WHEN ST_IDLE=> IF(di_vld='1') THEN
state<=ST_PRE_ROUND;
END IF;
WHEN ST_PRE_ROUND=> state<=ST_ROUND_OP;
WHEN ST_ROUND_OP=> IF(i_cnt="1100") THEN
state<=ST_READY;
END IF;
WHEN ST_POST_ROUND=> state<=ST_READY;
WHEN ST_READY=> state<=ST_IDLE;
END CASE;
END IF;
END PROCESS;
round_counter:
PROCESS(clr, clk_25) BEGIN
IF(clr='1') THEN
i_cnt<="0001";
ELSIF(rising_edge(clk_25) AND state=ST_ROUND_OP) THEN
IF(i_cnt="1100") THEN
i_cnt<="0001";
ELSE
i_cnt<=i_cnt+'1';
END IF;
ELSIF(state=ST_PRE_ROUND)THEN
i_cnt<="0001";
END IF;
END PROCESS;
dout<=a_reg & b_reg;
WITH state SELECT
do_rdy<='1' WHEN ST_READY,
'0' WHEN OTHERS;
dec_mode <= enc;
-------------------------------------------------
-------------------LED CONTROL-------------------
-------------------------------------------------
--hex to 7 Segment Display
hex2_7seg : ENTITY work.hex_7seg
--This is a new effective way to instantiate
--Rolls component and port map together
PORT MAP(
hex_digit => hex_digit_i,
segment_a => segment_a_i,
segment_b => segment_b_i,
segment_c => segment_c_i,
segment_d => segment_d_i,
segment_e => segment_e_i,
segment_f => segment_f_i,
segment_g => segment_g_i
);
--Flash the LED with the last 4 bytes of dout
PROCESS(clr,clk_25)
BEGIN
IF(clr='1')THEN
hex_digit_i <= (others => '0');
LED_flash_cnt <= (others => '0');
AN <= (others => '1');--All LED OFF
ELSIF(rising_edge(clk_25)) THEN
LED_flash_cnt <= LED_flash_cnt + '1';
CASE LED_flash_cnt(9 downto 8) IS
when "00" =>
--First 7-Seg-LED
hex_digit_i <= dout(15 downto 12);--LED output
AN <= "0111"; --Enables LED
when "01" =>
--Second 7-Seg-LED
hex_digit_i <= dout(11 downto 8);
AN <= "1011";
when "10" =>
--Third 7-Seg-LED
hex_digit_i <= dout(7 downto 4);
AN <= "1101";
when "11" =>
--Fourth 7-Seg-LED
hex_digit_i <= dout(3 downto 0);
AN <= "1110";
when others => null;
END CASE;
END IF;
END PROCESS;
END rtl; | lgpl-2.1 | f7fe7f830a493ee7a5b7401fb6a40ba9 | 0.553328 | 2.786578 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_Trivium/hex2sevenseg.vhd | 1 | 2,152 | ------------ A
------------F B
------------ G
------------E C
------------ D
------------ABCDEFG
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
-- Hexadecimal to 7 Segment Decoder for LED Display
ENTITY hex_7seg IS
PORT(
hex_digit : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
segment_a,
segment_b,
segment_c,
segment_d,
segment_e,
segment_f,
segment_g : OUT std_logic);
END hex_7seg;
ARCHITECTURE behavioral OF hex_7seg IS
SIGNAL segment_data : STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
PROCESS (Hex_digit)
-- HEX to 7 Segment Decoder for LED Display
BEGIN
-- Hex-digit is the four bit binary value to display in hexadecimal
CASE Hex_digit IS
WHEN "00000" =>
segment_data <= "0000001";--0
WHEN "00001" =>
segment_data <= "1001111";--1
WHEN "00010" =>
segment_data <= "0010010";--2
WHEN "00011" =>
segment_data <= "0000110";--3
WHEN "00100" =>
segment_data <= "1001100";--4
WHEN "00101" =>
segment_data <= "0100100";--5
WHEN "00110" =>
segment_data <= "0100000";--6
WHEN "00111" =>
segment_data <= "0001111";--7
WHEN "01000" =>
segment_data <= "0000000";--8
WHEN "01001" =>
segment_data <= "0000100";--9
WHEN "01010" =>
segment_data <= "0001000";--10 - A
WHEN "01011" =>
segment_data <= "1100000";--11 - B
WHEN "01100" =>
segment_data <= "0110001";--12 - C
WHEN "01101" =>
segment_data <= "1000010";--13 - D
WHEN "01110" =>
segment_data <= "0110000";--14 - E
WHEN "01111" =>
segment_data <= "0111000";--15 - F
WHEN "10000" =>
segment_data <= "1110001";--L
WHEN "10001" =>
segment_data <= "1111110";--'-'
WHEN OTHERS =>
segment_data <= "1111111";
END CASE;
END PROCESS;
-- extract segment data bits
-- LED driver circuit
segment_a <= segment_data(6);
segment_b <= segment_data(5);
segment_c <= segment_data(4);
segment_d <= segment_data(3);
segment_e <= segment_data(2);
segment_f <= segment_data(1);
segment_g <= segment_data(0);
END behavioral; | lgpl-2.1 | 10a5d7b9788fdac0286088fedb04f235 | 0.563662 | 3.118841 | false | false | false | false |
nsauzede/cpu86 | papilio1_0_rom/top_drigmorn1/papilio1_top.vhd | 2 | 10,888 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Toplevel : CPU86, 256Byte ROM, 16550 UART, 40K8 SRAM (all blockrams used)--
-------------------------------------------------------------------------------
-- Revision History: --
-- --
-- Date: Revision Author --
-- --
-- 30 Dec 2007 0.1 H. Tiggeler First version --
-- 17 May 2008 0.75 H. Tiggeler Updated for CPU86 ver0.75 --
-- 27 Jun 2008 0.79 H. Tiggeler Changed UART to Opencores 16750 --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY papilio1_top IS
Port ( rx : in STD_LOGIC;
tx : out STD_LOGIC;
W1A : inout STD_LOGIC_VECTOR (15 downto 0);
W1B : inout STD_LOGIC_VECTOR (15 downto 0);
W2C : inout STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC);
END papilio1_top ;
ARCHITECTURE struct OF papilio1_top IS
signal CLOCK_40MHZ : std_logic;
signal CTS : std_logic := '1';
signal PIN3 : std_logic;
signal RXD : std_logic;
signal LED1 : std_logic;
signal LED2N : std_logic;
signal LED3N : std_logic;
signal PIN4 : std_logic;
signal RTS : std_logic;
signal TXD : std_logic;
signal IS_IRQ : std_logic := '0';
signal IRQ : std_logic;
-- Architecture declarations
signal csromn : std_logic;
-- Internal signal declarations
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL abus : std_logic_vector(19 DOWNTO 0);
SIGNAL clk_int : std_logic;
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0);
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL rdn : std_logic;
SIGNAL resoutn : std_logic;
SIGNAL sel_s : std_logic_vector(1 DOWNTO 0);
SIGNAL wea : std_logic_VECTOR(0 DOWNTO 0);
SIGNAL wran : std_logic;
SIGNAL wrcom : std_logic;
SIGNAL wrn : std_logic;
signal rxclk_s : std_logic;
-- Component Declarations
COMPONENT cpu86
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END COMPONENT;
COMPONENT blk_mem_40K
PORT (
addra : IN std_logic_VECTOR (15 DOWNTO 0);
clka : IN std_logic;
dina : IN std_logic_VECTOR (7 DOWNTO 0);
wea : IN std_logic_VECTOR (0 DOWNTO 0);
douta : OUT std_logic_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT bootstrap
PORT (
abus : IN std_logic_vector (7 DOWNTO 0);
dbus : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT uart_top
PORT (
BR_clk : IN std_logic ;
CTSn : IN std_logic := '1';
DCDn : IN std_logic := '1';
DSRn : IN std_logic := '1';
RIn : IN std_logic := '1';
abus : IN std_logic_vector (2 DOWNTO 0);
clk : IN std_logic ;
csn : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic ;
resetn : IN std_logic ;
sRX : IN std_logic ;
wrn : IN std_logic ;
B_CLK : OUT std_logic ;
DTRn : OUT std_logic ;
IRQ : OUT std_logic ;
OUT1n : OUT std_logic ;
OUT2n : OUT std_logic ;
RTSn : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
stx : OUT std_logic
);
END COMPONENT;
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 4 mux
-- dmux 1
process(sel_s,dbus_com1,dbus_in,dbus_rom)
begin
case sel_s is
when "01" => dbus_in_cpu <= dbus_com1; -- UART
when "10" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when others=> dbus_in_cpu <= dbus_in; -- Embedded SRAM
end case;
end process;
-- HDL Embedded Text Block 7 clogic
clk_int <= CLOCK_40MHZ;
-- CLOCK_40MHZ <= clk; -- XXX : should generate with DCM
-- NOTE !! out freq set to 20MHz (serial = 19200) to avoid possible 40 MHz non-reacheable on papilio1
Inst_dcm32to40: entity work.dcm32to40 PORT MAP(
CLKIN_IN => clk,
CLKFX_OUT => CLOCK_40MHZ,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open
);
w1b(1) <= 'Z';
PIN3 <= w1b(1); -- por
RXD <= rx;
tx <= TXD;
-- w1b(0) <= LED1; -- cpuerror
w1b(2) <= LED2N; -- UART OUT1n
w1b(4) <= LED3N; -- UART OUT2n
w1b(0) <= PIN4; -- resetout (debug)
w1b(6) <= IS_IRQ; -- UART IRQ
process(rx)
begin
if rx='0' then
IS_IRQ <= '1';
end if;
end process;
CTS <= '1';
-- w1b(4) <= RTS;
wrcom <= not wrn;
wea(0)<= not wrn;
PIN4 <= resoutn; -- For debug only
-- dbus_in_cpu multiplexer
sel_s <= cscom1 & csromn;
-- chip_select
-- Comport, uart_16550
-- COM1, 0x3F8-0x3FF
cscom1 <= '0' when (abus(15 downto 3)="0000001111111" AND iom='1') else '1';
-- Bootstrap ROM 256 bytes
-- FFFFF-FF=FFF00
csromn <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
nmi <= '0';
intr <= '0';
dout <= '0';
dout1 <= '0';
DCDn <= '0';
DSRn <= '0';
RIn <= '0';
por <= NOT(PIN3);
-- Instance port mappings.
U_1 : cpu86
PORT MAP (
clk => clk_int,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus,
cpuerror => LED1,
dbus_out => dbus_out,
inta => OPEN,
iom => iom,
rdn => rdn,
resoutn => resoutn,
wran => wran,
wrn => wrn
);
U_3 : blk_mem_40K
PORT MAP (
clka => clk_int,
dina => dbus_out,
addra => abus(15 DOWNTO 0),
wea => wea,
douta => dbus_in
);
U_2 : bootstrap
PORT MAP (
abus => abus(7 DOWNTO 0),
dbus => dbus_rom
);
U_0 : uart_top
PORT MAP (
BR_clk => rxclk_s,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
abus => abus(2 DOWNTO 0),
clk => clk_int,
csn => cscom1,
dbus_in => dbus_out,
rdn => rdn,
resetn => resoutn,
sRX => RXD,
wrn => wrn,
B_CLK => rxclk_s,
DTRn => OPEN,
IRQ => IRQ,
OUT1n => led2n,
OUT2n => led3n,
RTSn => RTS,
dbus_out => dbus_com1,
stx => TXD
);
END struct;
| gpl-2.0 | 4af50111860ad2b3435f2f9ff5bdab57 | 0.426341 | 4 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Basys2Encryption/rc5.vhd | 1 | 6,629 | --RC5 Encryption
--A = A + S[0];
--B = B + S[1];
--for i=1 to 12 do
----A = ((A XOR B) <<< B) + S[2*i];
----B = ((B XOR A) <<< A) + S[2*1+1];
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
ENTITY rc5 IS
PORT (
-- Asynchronous reset and 25HzClock Signal
clr,clk_25 : IN STD_LOGIC;
-- 8-bit input
din_lower : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- Input is Valid
di_vld : IN STD_LOGIC;
-- 7 Segment Display-bit output
segment_a_i : OUT STD_LOGIC;
segment_b_i : OUT STD_LOGIC;
segment_c_i : OUT STD_LOGIC;
segment_d_i : OUT STD_LOGIC;
segment_e_i : OUT STD_LOGIC;
segment_f_i : OUT STD_LOGIC;
segment_g_i : OUT STD_LOGIC;
-- 7 Segment Control
--Control Which of the four 7-Segment Display is active
AN : OUT STD_LOGIC_VECTOR(3 downto 0);
--Output is Ready
do_rdy : OUT STD_LOGIC;
--OUTPUT FOR DISPLAYING LED ON
swtch_led : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END rc5;
ARCHITECTURE rtl OF rc5 IS
SIGNAL din : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL i_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); -- round counter
SIGNAL ab_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_pre : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register A
SIGNAL ba_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_pre : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register B
type rc5_rom_26 is array (0 to 25) of std_logic_vector(31 downto 0);
CONSTANT skey :rc5_rom_26:=rc5_rom_26'(
X"9BBBD8C8", X"1A37F7FB", X"46F8E8C5", X"460C6085",
X"70F83B8A", X"284B8303", X"513E1454", X"F621ED22",
X"3125065D", X"11A83A5D", X"D427686B", X"713AD82D",
X"4B792F99", X"2799A4DD", X"A7901C49", X"DEDE871A",
X"36C03196", X"A7EFC249", X"61A78BB8", X"3B0A1D2B",
X"4DBFCA76", X"AE162167", X"30D76B0A", X"43192304",
X"F6CC1431", X"65046380");
-- RC5 state machine has five states: idle, pre_round, round and ready
TYPE StateType IS(
ST_IDLE, -- In this state RC5 is ready for input
ST_PRE_ROUND, -- In this state RC5 pre-round op is performed
ST_ROUND_OP, -- In this state RC5 round op is performed. 12 rounds
ST_POST_ROUND, -- In this state RC5 post-round op is performed
ST_READY -- In this state RC5 has completed encryption
);
SIGNAL state : StateType;
--LED Control
SIGNAL hex_digit_i : STD_LOGIC_VECTOR(3 DOWNTO 0);
--Count to flash the LED
SIGNAL LED_flash_cnt : STD_LOGIC_VECTOR(9 DOWNTO 0);
BEGIN
din <= X"00000000000000" & din_lower;
-- A=((A XOR B)<<<B) + S[2*i];
ab_xor <= a_reg XOR b_reg;
--A <<< B
ROT_A_LEFT : ENTITY work.rotLeft
PORT MAP(din=>ab_xor,amnt=>b_reg(4 DOWNTO 0),dout=>a_rot);
--A = A + S[0]
a_pre<=din(63 DOWNTO 32) + skey(0);
-- S[2*i]
a<=a_rot + skey(CONV_INTEGER(i_cnt & '0'));
-- B=((B XOR A) <<<A) + S[2*i+1]
ba_xor <= b_reg XOR a;
--B <<< A
ROT_B_LEFT : ENTITY work.rotLeft
PORT MAP(din=>ba_xor,amnt=>a(4 DOWNTO 0),dout=>b_rot);
--B = B + S[1]
b_pre<=din(31 DOWNTO 0) + skey(1);
-- S[2*i+1]
b<=b_rot + skey(CONV_INTEGER(i_cnt & '1'));
A_register:
PROCESS(clr, clk_25) BEGIN
IF(clr='1') THEN
a_reg<= (others=> '0');
ELSIF(rising_edge(clk_25)) THEN
IF(state=ST_PRE_ROUND) THEN
a_reg<=a_pre;
ELSIF(state=ST_ROUND_OP) THEN
a_reg<=a;
END IF;
END IF;
END PROCESS;
B_register:
PROCESS(clr, clk_25) BEGIN
IF(clr='1') THEN
b_reg<= (others=> '0');
ELSIF(rising_edge(clk_25)) THEN
IF(state=ST_PRE_ROUND) THEN
b_reg<=b_pre;
ELSIF(state=ST_ROUND_OP) THEN
b_reg<=b;
END IF;
END IF;
END PROCESS;
State_Control:
PROCESS(clr, clk_25)
BEGIN
IF(clr='1') THEN
state<=ST_IDLE;
ELSIF(rising_edge(clk_25)) THEN
CASE state IS
WHEN ST_IDLE=> IF(di_vld='1') THEN
state<=ST_PRE_ROUND;
END IF;
WHEN ST_PRE_ROUND=> state<=ST_ROUND_OP;
WHEN ST_ROUND_OP=> IF(i_cnt="1100") THEN
state<=ST_READY;
END IF;
WHEN ST_POST_ROUND=> state<=ST_READY;
WHEN ST_READY=> state<=ST_IDLE;
END CASE;
END IF;
END PROCESS;
round_counter:
PROCESS(clr, clk_25) BEGIN
IF(clr='1') THEN
i_cnt<="0001";
ELSIF(rising_edge(clk_25)) THEN
IF (state=ST_ROUND_OP) THEN
IF(i_cnt="1100") THEN
i_cnt<="0001";
ELSE
i_cnt<=i_cnt+'1';
END IF;
ELSIF(state=ST_PRE_ROUND)THEN
i_cnt<="0001";
END IF;
END IF;
END PROCESS;
dout<=a_reg & b_reg;
WITH state SELECT
do_rdy<='1' WHEN ST_READY,
'0' WHEN OTHERS;
swtch_led <= din_lower;
-------------------------------------------------
-------------------LED CONTROL-------------------
-------------------------------------------------
--hex to 7 Segment Display
hex2_7seg : ENTITY work.hex_7seg
--This is a new effective way to instantiate
--Rolls component and port map together
PORT MAP(
hex_digit => hex_digit_i,
segment_a => segment_a_i,
segment_b => segment_b_i,
segment_c => segment_c_i,
segment_d => segment_d_i,
segment_e => segment_e_i,
segment_f => segment_f_i,
segment_g => segment_g_i
);
--Flash the LED with the last 4 bytes of dout
PROCESS(clr,clk_25)
BEGIN
IF(clr='1')THEN
hex_digit_i <= (others => '0');
LED_flash_cnt <= (others => '0');
AN <= (others => '1');--All LED OFF
ELSIF(rising_edge(clk_25)) THEN
LED_flash_cnt <= LED_flash_cnt + '1';
CASE LED_flash_cnt(9 downto 8) IS
when "00" =>
--First 7-Seg-LED
hex_digit_i <= dout(15 downto 12);--LED output
AN <= "0111"; --Enables LED
when "01" =>
--Second 7-Seg-LED
hex_digit_i <= dout(11 downto 8);
AN <= "1011";
when "10" =>
--Third 7-Seg-LED
hex_digit_i <= dout(7 downto 4);
AN <= "1101";
when "11" =>
--Fourth 7-Seg-LED
hex_digit_i <= dout(3 downto 0);
AN <= "1110";
when others => null;
END CASE;
END IF;
END PROCESS;
END rtl; | lgpl-2.1 | 875d9dc647eb9f154cdf815cea2c2512 | 0.551516 | 2.780621 | false | false | false | false |
hacklabmikkeli/knobs-galore | synthesizer_sim.vhdl | 2 | 3,129 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.common.all;
entity synthesizer_sim is
port (CLK: in std_logic
;KEY_CODE: in keys_signal
;KEY_EVENT: in key_event_t
;AUDIO: out audio_signal
)
;
end entity;
architecture synthesizer_sim_impl of synthesizer_sim is
signal clk_even: std_logic := '0';
signal clk_odd: std_logic := '0';
signal clk_slow: std_logic := '0';
signal clk_divider: unsigned(4 downto 0) := (others => '0');
signal freq: time_signal := (others => '0');
signal gate: std_logic;
signal fifo_in: state_vector_t;
signal fifo_out: state_vector_t;
signal z_ampl: voice_signal;
signal audio_buf: audio_signal;
signal audio_buf_del: audio_signal;
begin
process(CLK)
begin
if rising_edge(CLK) then
clk_divider <= clk_divider + 1;
end if;
end process;
clk_even <= '1' when std_match(clk_divider, "0000-") else '0';
clk_odd <= '1' when std_match(clk_divider, "0001-") else '0';
clk_slow <= '1' when std_match(clk_divider, "1----") else '0';
voice_allocator:
entity
work.voice_allocator (voice_allocator_impl)
port map
('1'
,clk_odd
,voice_transform_oct
,key_code
,key_event
,freq
,gate
);
circular_buffer:
entity
work.circular_buffer (circular_buffer_impl)
port map
('1'
,clk_odd
,fifo_in
,fifo_out
);
voice_generator:
entity
work.voice_generator (voice_generator_impl)
port map
('1'
,clk_even
,clk_odd
,freq
,gate
,(mode_saw_fat
,voice_transform_oct
,x"00", x"A0", x"01", x"01", x"00", x"01"
,x"FF", x"01", x"FF", x"01"
)
,z_ampl
,fifo_in
,fifo_out
);
mixer:
entity
work.mixer (mixer_impl)
port map
('1'
,clk_odd
,z_ampl
,audio_buf
);
AUDIO <= audio_buf;
end architecture;
| gpl-3.0 | 4903bcdaac35aab4548ae3861449e29a | 0.539469 | 3.806569 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Key_Generation/rc5_key_expansion/netgen/par/rc5_key_timesim.vhd | 1 | 17,035 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: rc5_key_timesim.vhd
-- /___/ /\ Timestamp: Tue Mar 17 12:20:07 2015
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -s 4 -pcf rc5_key.pcf -rpw 100 -tpw 0 -ar Structure -tm rc5_key -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim rc5_key.ncd rc5_key_timesim.vhd
-- Device : 3s250eft256-4 (PRODUCTION 1.27 2013-10-13)
-- Input file : rc5_key.ncd
-- Output file : C:\SkyDrive\School\Polytechnic\EL6463_AdvancedHardwareDesign\Labs\Lab5\rc5_key_expansion\netgen\par\rc5_key_timesim.vhd
-- # of Entities : 1
-- Design Name : rc5_key
-- Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity rc5_key is
port (
clk : in STD_LOGIC := 'X';
clr : in STD_LOGIC := 'X';
key_vld : in STD_LOGIC := 'X';
key_rdy : out STD_LOGIC;
key : in STD_LOGIC_VECTOR ( 127 downto 0 )
);
end rc5_key;
architecture Structure of rc5_key is
signal clr_IBUF_96 : STD_LOGIC;
signal key_vld_IBUF_97 : STD_LOGIC;
signal clk_BUFGP : STD_LOGIC;
signal state_cmp_eq0001_0 : STD_LOGIC;
signal state_FSM_FFd2_109 : STD_LOGIC;
signal state_FSM_FFd2_In16_O : STD_LOGIC;
signal state_FSM_FFd2_In40_0 : STD_LOGIC;
signal state_FSM_FFd2_In4_0 : STD_LOGIC;
signal state_FSM_FFd1_113 : STD_LOGIC;
signal clk_INBUF : STD_LOGIC;
signal key_rdy_O : STD_LOGIC;
signal clr_INBUF : STD_LOGIC;
signal key_vld_INBUF : STD_LOGIC;
signal clk_BUFGP_BUFG_S_INVNOT : STD_LOGIC;
signal clk_BUFGP_BUFG_I0_INV : STD_LOGIC;
signal r_cnt_4_FFX_RST : STD_LOGIC;
signal r_cnt_4_DXMUX_175 : STD_LOGIC;
signal Mcount_r_cnt_cy_3_pack_2 : STD_LOGIC;
signal r_cnt_4_CLKINV_157 : STD_LOGIC;
signal r_cnt_4_CEINV_156 : STD_LOGIC;
signal r_cnt_3_DXMUX_221 : STD_LOGIC;
signal r_cnt_3_DYMUX_206 : STD_LOGIC;
signal r_cnt_3_SRINVNOT : STD_LOGIC;
signal r_cnt_3_CLKINV_196 : STD_LOGIC;
signal r_cnt_3_CEINV_195 : STD_LOGIC;
signal r_cnt_6_DXMUX_267 : STD_LOGIC;
signal r_cnt_6_DYMUX_252 : STD_LOGIC;
signal r_cnt_6_SRINVNOT : STD_LOGIC;
signal r_cnt_6_CLKINV_242 : STD_LOGIC;
signal r_cnt_6_CEINV_241 : STD_LOGIC;
signal state_FSM_FFd2_DXMUX_313 : STD_LOGIC;
signal state_FSM_FFd2_In : STD_LOGIC;
signal state_FSM_FFd2_DYMUX_299 : STD_LOGIC;
signal state_FSM_FFd2_In16_O_pack_3 : STD_LOGIC;
signal state_FSM_FFd2_SRINVNOT : STD_LOGIC;
signal state_FSM_FFd2_CLKINV_289 : STD_LOGIC;
signal state_cmp_eq0001 : STD_LOGIC;
signal state_FSM_FFd2_In40_332 : STD_LOGIC;
signal r_cnt_1_DXMUX_385 : STD_LOGIC;
signal r_cnt_1_DYMUX_368 : STD_LOGIC;
signal state_FSM_FFd2_In4_365 : STD_LOGIC;
signal r_cnt_1_SRINVNOT : STD_LOGIC;
signal r_cnt_1_CLKINV_357 : STD_LOGIC;
signal r_cnt_1_CEINV_356 : STD_LOGIC;
signal key_rdy_OBUF_402 : STD_LOGIC;
signal GND : STD_LOGIC;
signal VCC : STD_LOGIC;
signal r_cnt : STD_LOGIC_VECTOR ( 6 downto 0 );
signal Mcount_r_cnt_cy : STD_LOGIC_VECTOR ( 3 downto 3 );
signal Result : STD_LOGIC_VECTOR ( 6 downto 1 );
begin
clk_BUFGP_IBUFG : X_BUF
generic map(
LOC => "IPAD21",
PATHPULSE => 638 ps
)
port map (
I => clk,
O => clk_INBUF
);
key_rdy_OBUF : X_OBUF
generic map(
LOC => "PAD39"
)
port map (
I => key_rdy_O,
O => key_rdy
);
clr_IBUF : X_BUF
generic map(
LOC => "PAD43",
PATHPULSE => 638 ps
)
port map (
I => clr,
O => clr_INBUF
);
key_vld_IBUF : X_BUF
generic map(
LOC => "PAD42",
PATHPULSE => 638 ps
)
port map (
I => key_vld,
O => key_vld_INBUF
);
clk_BUFGP_BUFG : X_BUFGMUX
generic map(
LOC => "BUFGMUX_X2Y10"
)
port map (
I0 => clk_BUFGP_BUFG_I0_INV,
I1 => GND,
S => clk_BUFGP_BUFG_S_INVNOT,
O => clk_BUFGP
);
clk_BUFGP_BUFG_SINV : X_INV
generic map(
LOC => "BUFGMUX_X2Y10",
PATHPULSE => 638 ps
)
port map (
I => '1',
O => clk_BUFGP_BUFG_S_INVNOT
);
clk_BUFGP_BUFG_I0_USED : X_BUF
generic map(
LOC => "BUFGMUX_X2Y10",
PATHPULSE => 638 ps
)
port map (
I => clk_INBUF,
O => clk_BUFGP_BUFG_I0_INV
);
r_cnt_4_FFX_RSTOR : X_INV
generic map(
LOC => "SLICE_X40Y65",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_96,
O => r_cnt_4_FFX_RST
);
r_cnt_4 : X_FF
generic map(
LOC => "SLICE_X40Y65",
INIT => '0'
)
port map (
I => r_cnt_4_DXMUX_175,
CE => r_cnt_4_CEINV_156,
CLK => r_cnt_4_CLKINV_157,
SET => GND,
RST => r_cnt_4_FFX_RST,
O => r_cnt(4)
);
r_cnt_4_DXMUX : X_BUF
generic map(
LOC => "SLICE_X40Y65",
PATHPULSE => 638 ps
)
port map (
I => Result(4),
O => r_cnt_4_DXMUX_175
);
r_cnt_4_YUSED : X_BUF
generic map(
LOC => "SLICE_X40Y65",
PATHPULSE => 638 ps
)
port map (
I => Mcount_r_cnt_cy_3_pack_2,
O => Mcount_r_cnt_cy(3)
);
r_cnt_4_CLKINV : X_BUF
generic map(
LOC => "SLICE_X40Y65",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => r_cnt_4_CLKINV_157
);
r_cnt_4_CEINV : X_BUF
generic map(
LOC => "SLICE_X40Y65",
PATHPULSE => 638 ps
)
port map (
I => state_cmp_eq0001_0,
O => r_cnt_4_CEINV_156
);
Mcount_r_cnt_xor_4_11 : X_LUT4
generic map(
INIT => X"3C3C",
LOC => "SLICE_X40Y65"
)
port map (
ADR0 => VCC,
ADR1 => r_cnt(4),
ADR2 => Mcount_r_cnt_cy(3),
ADR3 => VCC,
O => Result(4)
);
r_cnt_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X41Y67",
PATHPULSE => 638 ps
)
port map (
I => Result(3),
O => r_cnt_3_DXMUX_221
);
r_cnt_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X41Y67",
PATHPULSE => 638 ps
)
port map (
I => Result(2),
O => r_cnt_3_DYMUX_206
);
r_cnt_3_SRINV : X_INV
generic map(
LOC => "SLICE_X41Y67",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_96,
O => r_cnt_3_SRINVNOT
);
r_cnt_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X41Y67",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => r_cnt_3_CLKINV_196
);
r_cnt_3_CEINV : X_BUF
generic map(
LOC => "SLICE_X41Y67",
PATHPULSE => 638 ps
)
port map (
I => state_cmp_eq0001_0,
O => r_cnt_3_CEINV_195
);
Mcount_r_cnt_xor_5_11 : X_LUT4
generic map(
INIT => X"3CF0",
LOC => "SLICE_X41Y64"
)
port map (
ADR0 => VCC,
ADR1 => Mcount_r_cnt_cy(3),
ADR2 => r_cnt(5),
ADR3 => r_cnt(4),
O => Result(5)
);
r_cnt_6_DXMUX : X_BUF
generic map(
LOC => "SLICE_X41Y64",
PATHPULSE => 638 ps
)
port map (
I => Result(6),
O => r_cnt_6_DXMUX_267
);
r_cnt_6_DYMUX : X_BUF
generic map(
LOC => "SLICE_X41Y64",
PATHPULSE => 638 ps
)
port map (
I => Result(5),
O => r_cnt_6_DYMUX_252
);
r_cnt_6_SRINV : X_INV
generic map(
LOC => "SLICE_X41Y64",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_96,
O => r_cnt_6_SRINVNOT
);
r_cnt_6_CLKINV : X_BUF
generic map(
LOC => "SLICE_X41Y64",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => r_cnt_6_CLKINV_242
);
r_cnt_6_CEINV : X_BUF
generic map(
LOC => "SLICE_X41Y64",
PATHPULSE => 638 ps
)
port map (
I => state_cmp_eq0001_0,
O => r_cnt_6_CEINV_241
);
state_FSM_FFd2_DXMUX : X_BUF
generic map(
LOC => "SLICE_X40Y67",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd2_In,
O => state_FSM_FFd2_DXMUX_313
);
state_FSM_FFd2_DYMUX : X_BUF
generic map(
LOC => "SLICE_X40Y67",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd2_109,
O => state_FSM_FFd2_DYMUX_299
);
state_FSM_FFd2_YUSED : X_BUF
generic map(
LOC => "SLICE_X40Y67",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd2_In16_O_pack_3,
O => state_FSM_FFd2_In16_O
);
state_FSM_FFd2_SRINV : X_INV
generic map(
LOC => "SLICE_X40Y67",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_96,
O => state_FSM_FFd2_SRINVNOT
);
state_FSM_FFd2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X40Y67",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => state_FSM_FFd2_CLKINV_289
);
state_cmp_eq0001_XUSED : X_BUF
generic map(
LOC => "SLICE_X40Y64",
PATHPULSE => 638 ps
)
port map (
I => state_cmp_eq0001,
O => state_cmp_eq0001_0
);
state_cmp_eq0001_YUSED : X_BUF
generic map(
LOC => "SLICE_X40Y64",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd2_In40_332,
O => state_FSM_FFd2_In40_0
);
r_cnt_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X41Y65",
PATHPULSE => 638 ps
)
port map (
I => Result(1),
O => r_cnt_1_DXMUX_385
);
r_cnt_1_DYMUX : X_INV
generic map(
LOC => "SLICE_X41Y65",
PATHPULSE => 638 ps
)
port map (
I => r_cnt(0),
O => r_cnt_1_DYMUX_368
);
r_cnt_1_YUSED : X_BUF
generic map(
LOC => "SLICE_X41Y65",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd2_In4_365,
O => state_FSM_FFd2_In4_0
);
r_cnt_1_SRINV : X_INV
generic map(
LOC => "SLICE_X41Y65",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_96,
O => r_cnt_1_SRINVNOT
);
r_cnt_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X41Y65",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => r_cnt_1_CLKINV_357
);
r_cnt_1_CEINV : X_BUF
generic map(
LOC => "SLICE_X41Y65",
PATHPULSE => 638 ps
)
port map (
I => state_cmp_eq0001_0,
O => r_cnt_1_CEINV_356
);
r_cnt_1 : X_FF
generic map(
LOC => "SLICE_X41Y65",
INIT => '0'
)
port map (
I => r_cnt_1_DXMUX_385,
CE => r_cnt_1_CEINV_356,
CLK => r_cnt_1_CLKINV_357,
SET => GND,
RST => r_cnt_1_SRINVNOT,
O => r_cnt(1)
);
state_FSM_FFd2 : X_FF
generic map(
LOC => "SLICE_X40Y67",
INIT => '0'
)
port map (
I => state_FSM_FFd2_DXMUX_313,
CE => VCC,
CLK => state_FSM_FFd2_CLKINV_289,
SET => GND,
RST => state_FSM_FFd2_SRINVNOT,
O => state_FSM_FFd2_109
);
clr_IFF_IMUX : X_BUF
generic map(
LOC => "PAD43",
PATHPULSE => 638 ps
)
port map (
I => clr_INBUF,
O => clr_IBUF_96
);
key_vld_IFF_IMUX : X_BUF
generic map(
LOC => "PAD42",
PATHPULSE => 638 ps
)
port map (
I => key_vld_INBUF,
O => key_vld_IBUF_97
);
Mcount_r_cnt_cy_3_11 : X_LUT4
generic map(
INIT => X"8000",
LOC => "SLICE_X40Y65"
)
port map (
ADR0 => r_cnt(3),
ADR1 => r_cnt(2),
ADR2 => r_cnt(0),
ADR3 => r_cnt(1),
O => Mcount_r_cnt_cy_3_pack_2
);
Mcount_r_cnt_xor_2_11 : X_LUT4
generic map(
INIT => X"5AAA",
LOC => "SLICE_X41Y67"
)
port map (
ADR0 => r_cnt(2),
ADR1 => VCC,
ADR2 => r_cnt(1),
ADR3 => r_cnt(0),
O => Result(2)
);
r_cnt_2 : X_FF
generic map(
LOC => "SLICE_X41Y67",
INIT => '0'
)
port map (
I => r_cnt_3_DYMUX_206,
CE => r_cnt_3_CEINV_195,
CLK => r_cnt_3_CLKINV_196,
SET => GND,
RST => r_cnt_3_SRINVNOT,
O => r_cnt(2)
);
Mcount_r_cnt_xor_3_11 : X_LUT4
generic map(
INIT => X"7F80",
LOC => "SLICE_X41Y67"
)
port map (
ADR0 => r_cnt(1),
ADR1 => r_cnt(0),
ADR2 => r_cnt(2),
ADR3 => r_cnt(3),
O => Result(3)
);
r_cnt_3 : X_FF
generic map(
LOC => "SLICE_X41Y67",
INIT => '0'
)
port map (
I => r_cnt_3_DXMUX_221,
CE => r_cnt_3_CEINV_195,
CLK => r_cnt_3_CLKINV_196,
SET => GND,
RST => r_cnt_3_SRINVNOT,
O => r_cnt(3)
);
r_cnt_5 : X_FF
generic map(
LOC => "SLICE_X41Y64",
INIT => '0'
)
port map (
I => r_cnt_6_DYMUX_252,
CE => r_cnt_6_CEINV_241,
CLK => r_cnt_6_CLKINV_242,
SET => GND,
RST => r_cnt_6_SRINVNOT,
O => r_cnt(5)
);
Mcount_r_cnt_xor_6_11 : X_LUT4
generic map(
INIT => X"6AAA",
LOC => "SLICE_X41Y64"
)
port map (
ADR0 => r_cnt(6),
ADR1 => Mcount_r_cnt_cy(3),
ADR2 => r_cnt(5),
ADR3 => r_cnt(4),
O => Result(6)
);
r_cnt_6 : X_FF
generic map(
LOC => "SLICE_X41Y64",
INIT => '0'
)
port map (
I => r_cnt_6_DXMUX_267,
CE => r_cnt_6_CEINV_241,
CLK => r_cnt_6_CLKINV_242,
SET => GND,
RST => r_cnt_6_SRINVNOT,
O => r_cnt(6)
);
state_FSM_FFd2_In16 : X_LUT4
generic map(
INIT => X"FF7F",
LOC => "SLICE_X40Y67"
)
port map (
ADR0 => r_cnt(3),
ADR1 => r_cnt(2),
ADR2 => r_cnt(6),
ADR3 => r_cnt(1),
O => state_FSM_FFd2_In16_O_pack_3
);
state_FSM_FFd1 : X_FF
generic map(
LOC => "SLICE_X40Y67",
INIT => '0'
)
port map (
I => state_FSM_FFd2_DYMUX_299,
CE => VCC,
CLK => state_FSM_FFd2_CLKINV_289,
SET => GND,
RST => state_FSM_FFd2_SRINVNOT,
O => state_FSM_FFd1_113
);
state_FSM_FFd2_In43 : X_LUT4
generic map(
INIT => X"FECC",
LOC => "SLICE_X40Y67"
)
port map (
ADR0 => state_FSM_FFd2_In4_0,
ADR1 => state_FSM_FFd2_In40_0,
ADR2 => state_FSM_FFd2_In16_O,
ADR3 => state_FSM_FFd2_109,
O => state_FSM_FFd2_In
);
state_FSM_FFd2_In40 : X_LUT4
generic map(
INIT => X"0F0C",
LOC => "SLICE_X40Y64"
)
port map (
ADR0 => VCC,
ADR1 => state_FSM_FFd2_109,
ADR2 => state_FSM_FFd1_113,
ADR3 => key_vld_IBUF_97,
O => state_FSM_FFd2_In40_332
);
state_FSM_Out01 : X_LUT4
generic map(
INIT => X"CC00",
LOC => "SLICE_X40Y64"
)
port map (
ADR0 => VCC,
ADR1 => state_FSM_FFd2_109,
ADR2 => VCC,
ADR3 => state_FSM_FFd1_113,
O => state_cmp_eq0001
);
state_FSM_FFd2_In4 : X_LUT4
generic map(
INIT => X"FFF3",
LOC => "SLICE_X41Y65"
)
port map (
ADR0 => VCC,
ADR1 => r_cnt(0),
ADR2 => r_cnt(5),
ADR3 => r_cnt(4),
O => state_FSM_FFd2_In4_365
);
r_cnt_0 : X_FF
generic map(
LOC => "SLICE_X41Y65",
INIT => '0'
)
port map (
I => r_cnt_1_DYMUX_368,
CE => r_cnt_1_CEINV_356,
CLK => r_cnt_1_CLKINV_357,
SET => GND,
RST => r_cnt_1_SRINVNOT,
O => r_cnt(0)
);
Mcount_r_cnt_xor_1_11 : X_LUT4
generic map(
INIT => X"5A5A",
LOC => "SLICE_X41Y65"
)
port map (
ADR0 => r_cnt(1),
ADR1 => VCC,
ADR2 => r_cnt(0),
ADR3 => VCC,
O => Result(1)
);
state_FSM_Out31 : X_LUT4
generic map(
INIT => X"0F00",
LOC => "SLICE_X45Y67"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => state_FSM_FFd2_109,
ADR3 => state_FSM_FFd1_113,
O => key_rdy_OBUF_402
);
key_rdy_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD39",
PATHPULSE => 638 ps
)
port map (
I => key_rdy_OBUF_402,
O => key_rdy_O
);
NlwBlock_rc5_key_GND : X_ZERO
port map (
O => GND
);
NlwBlock_rc5_key_VCC : X_ONE
port map (
O => VCC
);
NlwBlockROC : X_ROC
generic map (ROC_WIDTH => 100 ns)
port map (O => GSR);
NlwBlockTOC : X_TOC
port map (O => GTS);
end Structure;
| lgpl-2.1 | 514498ebb334d203d7fb620d31d2c5d9 | 0.502847 | 2.890718 | false | false | false | false |
da-steve101/binary_connect_cifar | src/main/vhdl/ternary_adder_xilinx.vhd | 1 | 17,993 | ---------------------------------------------------------------------------------------------
-- Author: Jens Willkomm, Martin Kumm
-- Contact: [email protected], [email protected]
-- License: LGPL
-- Date: 15.03.2013
-- Compatibility: Xilinx FPGAs of Virtex 5-7, Spartan 6 and Series 7 architectures
--
-- Description:
-- Low level implementation of a ternary adder according to U.S. Patent No 7274211
-- from Xilinx, which uses the same no of slices than a two input adder.
-- The output coresponds to sum_o = x_i + y_i + z_i, where the inputs have a word size of
-- 'input_word_size' while the output has a word size of input_word_size+2.
--
-- Flipflops at the outputs can be activated by setting 'use_output_ff' to true.
-- Signed operation is activated by using the 'is_signed' generic.
-- The inputs y_i and z_i can be negated by setting 'subtract_y' or 'subtract_z'
-- to realize sum_o = x_i +/- y_i +/- z_i. The negation requires no extra resources.
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ternary_add_sub_prim is
generic(
input_word_size : integer := 10;
subtract_y : boolean := false;
subtract_z : boolean := false;
use_output_ff : boolean := true;
is_signed : boolean := true
);
port(
clk_i : in std_logic;
x_i : in std_logic_vector((input_word_size - 1) downto 0);
y_i : in std_logic_vector((input_word_size - 1) downto 0);
z_i : in std_logic_vector((input_word_size - 1) downto 0);
sum_o : out std_logic_vector((input_word_size + 1) downto 0)
);
end entity;
architecture behavior of ternary_add_sub_prim is
-- this function calculates the initial carry bit for the bbus
function bbus_init
return std_logic is
variable result : std_logic;
begin
result := '0';
if subtract_y or subtract_z then
result := '1';
end if;
return result;
end function;
-- this function calculates the initial carry bit for the carry chain
function cc_init
return std_logic is
variable result : std_logic;
begin
result := '0';
if subtract_y and subtract_z then
result := '1';
end if;
return result;
end function;
component slice_setup
generic(
input_word_size : integer := 4;
use_output_ff : boolean := false;
is_initial_slice : boolean := true;
subtract_y : boolean := false;
subtract_z : boolean := false
);
port(
-- signals for a synchronous circuit
clock : in std_logic;
clock_enable : in std_logic;
clear : in std_logic;
-- the three addends
x_in : in std_logic_vector((input_word_size - 1) downto 0);
y_in : in std_logic_vector((input_word_size - 1) downto 0);
z_in : in std_logic_vector((input_word_size - 1) downto 0);
-- the upper entity is mapping the bbus correctly
-- in initial slice bbus(0) ^= sub / ~add
bbus_in : in std_logic_vector((input_word_size - 1) downto 0);
bbus_out : out std_logic_vector((input_word_size - 1) downto 0);
-- both carrys are for and from the carry chain
-- in the initial slice use carry_in <= '0' always
-- sub/add is done by the bbus(0) from the initial slice
carry_in : in std_logic;
carry_out : out std_logic;
-- the sum of the three addends (x_in + y_in + z_in)
sum_out : out std_logic_vector((input_word_size - 1) downto 0)
);
end component;
-- calculate the needed number of slices
constant num_slices : integer := ((input_word_size + 1) / 4) + 1;
-- defines the initial carry values
-- in the pure addition mode both constants are '0'
-- if one of the input signal is subtracted the carry_bbus is '1'
-- if two input signal are subtracted both constants are '1'
constant carry_bbus : std_logic := bbus_init;
constant carry_cc : std_logic := cc_init;
-- the input addends with sign extention
signal x : std_logic_vector((input_word_size + 1) downto 0);
signal y : std_logic_vector((input_word_size + 1) downto 0);
signal z : std_logic_vector((input_word_size + 1) downto 0);
-- the bbus that is routed around the slice
-- this bbus differs from the one in the xilinx paper,
-- per position the input is bbus(n) and the output is bbus(n + 1)
-- this is because of the sub/~add, which is bbus(0) and all the other
-- bbus signals are scrolled one position up
signal bbus : std_logic_vector(input_word_size + 2 downto 0);
-- the carry from every slice to the next one
-- the last slice gives the carry output for the adder
-- carry(n) is the carry of the carry chain of slice n
signal carry : std_logic_vector((num_slices - 1) downto 0);
begin
-- checking the parameter input_word_size
assert (input_word_size > 0) report "an adder with a bit width of "
& integer'image(input_word_size) & " is not possible." severity failure;
-- adding two bit sign extention to the input addends
extention_signed: if is_signed = true generate
x <= x_i(input_word_size - 1) & x_i(input_word_size - 1) & x_i;
y <= y_i(input_word_size - 1) & y_i(input_word_size - 1) & y_i;
z <= z_i(input_word_size - 1) & z_i(input_word_size - 1) & z_i;
end generate;
extention_unsigned: if is_signed = false generate
x <= '0' & '0' & x_i;
y <= '0' & '0' & y_i;
z <= '0' & '0' & z_i;
end generate;
-- the initial bbus carry signal
bbus(0) <= carry_bbus;
-- generating the slice setups
-- getting all signals into one slice
single_slice: if num_slices = 1 generate
slice_i: slice_setup
generic map(
input_word_size => input_word_size + 2,
use_output_ff => use_output_ff,
is_initial_slice => true,
subtract_y => subtract_y,
subtract_z => subtract_z
)
port map(
clock => clk_i,
clock_enable => '1',
clear => 0,
x_in => x,
y_in => y,
z_in => z,
bbus_in => bbus(input_word_size + 1 downto 0),
-- scrolling bbus_out one position up
bbus_out => bbus(input_word_size + 2 downto 1),
carry_in => carry_cc,
carry_out => carry(0),
sum_out => sum_o(input_word_size + 1 downto 0)
);
end generate;
-- make more slices to calculate all signals
multiple_slices: if num_slices > 1 generate
slices: for i in 0 to (num_slices - 1) generate
-- generate the first slice
first_slice: if i = 0 generate
slice_i: slice_setup
generic map(
input_word_size => 4,
use_output_ff => use_output_ff,
is_initial_slice => true,
subtract_y => subtract_y,
subtract_z => subtract_z
)
port map(
clock => clk_i,
clock_enable => '1',
clear => 0,
x_in => x(3 downto 0),
y_in => y(3 downto 0),
z_in => z(3 downto 0),
bbus_in => bbus(3 downto 0),
-- scrolling bbus_out one position upwards
bbus_out => bbus(4 downto 1),
carry_in => carry_cc,
carry_out => carry(0),
sum_out => sum_o(3 downto 0)
);
end generate;
-- generate all full slices
full_slice: if i > 0 and i < (num_slices - 1) generate
slice_i: slice_setup
generic map(
input_word_size => 4,
use_output_ff => use_output_ff,
is_initial_slice => false,
subtract_y => subtract_y,
subtract_z => subtract_z
)
port map(
clock => clk_i,
clock_enable => '1',
clear => 0,
x_in => x((4 * i) + 3 downto 4 * i),
y_in => y((4 * i) + 3 downto 4 * i),
z_in => z((4 * i) + 3 downto 4 * i),
bbus_in => bbus((4 * i) + 3 downto 4 * i),
-- scrolling bbus_out one position upwards
bbus_out => bbus((4 * i) + 4 downto (4 * i) + 1),
carry_in => carry(i - 1),
carry_out => carry(i),
sum_out => sum_o((4 * i) + 3 downto 4 * i)
);
end generate;
-- generate the last slice
last_slice: if i = (num_slices - 1) generate
slice_i: slice_setup
generic map(
input_word_size => (input_word_size + 2) - (i * 4),
use_output_ff => use_output_ff,
is_initial_slice => false,
subtract_y => subtract_y,
subtract_z => subtract_z
)
port map(
clock => clk_i,
clock_enable => '1',
clear => 0,
x_in => x(input_word_size + 1 downto 4 * i),
y_in => y(input_word_size + 1 downto 4 * i),
z_in => z(input_word_size + 1 downto 4 * i),
bbus_in => bbus(input_word_size + 1 downto 4 * i),
-- scrolling bbus_out one position up
bbus_out => bbus(input_word_size + 2 downto (4 * i) + 1),
carry_in => carry(i - 1),
carry_out => carry(i),
sum_out => sum_o(input_word_size + 1 downto 4 * i)
);
end generate;
end generate;
end generate;
end architecture;
--- Definition of the slice_setup component which configures a single slice ---
library unisim;
use unisim.vcomponents.all; -- loading xilinx primitives
library ieee;
use ieee.std_logic_1164.all; -- loading std_logic & std_logic_vector
entity slice_setup is
generic(
input_word_size : integer := 4;
use_output_ff : boolean := false;
is_initial_slice : boolean := true;
subtract_y : boolean := false;
subtract_z : boolean := false
);
port(
-- signals for a synchronous circuit
clock : in std_logic;
clock_enable : in std_logic;
clear : in std_logic;
-- the three addends
x_in : in std_logic_vector((input_word_size - 1) downto 0);
y_in : in std_logic_vector((input_word_size - 1) downto 0);
z_in : in std_logic_vector((input_word_size - 1) downto 0);
-- the upper entity is mapping the bbus correctly
-- in initial slice bbus(0) ^= sub / ~add
bbus_in : in std_logic_vector((input_word_size - 1) downto 0);
bbus_out : out std_logic_vector((input_word_size - 1) downto 0);
-- both carrys are for and from the carry chain
-- in the initial slice use carry_in <= '0' always
-- sub/add is done by the bbus(0) from the initial slice
carry_in : in std_logic;
carry_out : out std_logic;
-- the sum of the three addends (x_in + y_in + z_in)
sum_out : out std_logic_vector((input_word_size - 1) downto 0)
);
end entity;
architecture behavior of slice_setup is
-- this function returns the lut initialization
function get_lut_init
return bit_vector is
-- defines several lut configurations
-- for init calculation see "initializing_primitives.ods"
constant lut_init_no_sub : bit_vector(63 downto 0) := x"3cc3c33cfcc0fcc0";
constant lut_init_sub_y : bit_vector(63 downto 0) := x"c33c3cc3cf0ccf0c";
constant lut_init_sub_z : bit_vector(63 downto 0) := x"c33c3cc3f330f330";
constant lut_init_sub_yz : bit_vector(63 downto 0) := x"3cc3c33c3f033f03";
variable curr_lut : bit_vector(63 downto 0) := lut_init_no_sub;
begin
curr_lut := lut_init_no_sub;
if subtract_y then
curr_lut := lut_init_sub_y;
end if;
if subtract_z then
curr_lut := lut_init_sub_z;
end if;
if subtract_y and subtract_z then
curr_lut := lut_init_sub_yz;
end if;
return curr_lut;
end function;
-- calculate how many bits to fill up with zeros for the carry chain
constant fillup_width : integer := 4 - input_word_size;
-- holds the lut configuration used in this slice
constant current_lut_init : bit_vector := get_lut_init;
-- output o6 of the luts
signal lut_o6 : std_logic_vector((input_word_size - 1) downto 0);
-- the signals for and from the carry chain have to be wrapped into signals
-- with a width of four, to fill them up with zeros and prevent synthesis
-- warnings when doing this in the port map of the carry chain
-- input di of the carry chain (have to be four bits width)
signal cc_di : std_logic_vector(3 downto 0);
-- input s of the carry chain (have to be four bits width)
signal cc_s : std_logic_vector(3 downto 0);
-- output o of the carry chain (have to be four bits width)
signal cc_o : std_logic_vector(3 downto 0);
-- output co of the carry chain (have to be four bits width)
signal cc_co : std_logic_vector(3 downto 0);
begin
-- check the generic parameter
assert (input_word_size > 0 and input_word_size < 5) report "a slice with a bit width of "
& integer'image(input_word_size) & " is not possible." severity failure;
-- prepairing singals for the carry chain
full_slice_assignment: if input_word_size = 4 generate
cc_di <= bbus_in;
cc_s <= lut_o6;
end generate;
last_slice_assignment: if input_word_size < 4 generate
cc_di <= (fillup_width downto 1 => '0') & bbus_in;
cc_s <= (fillup_width downto 1 => '0') & lut_o6;
end generate;
-- creating the lookup tables
luts: for i in 0 to (input_word_size - 1) generate
-- lut6_2 primitive is described in virtex 6 user guide on page 215:
-- http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/virtex6_hdl.pdf
lut_bit_i: lut6_2
generic map(
init => current_lut_init
)
-------------------------------------------------------------------
-- table of names and connections
-- user guide us 7,274,211 usage in adder
-- ---------- ------------ --------------
-- i0 in1 gnd
-- i1 in2 z(n)
-- i2 in3 y(n)
-- i3 in4 x(n)
-- i4 in5 bbus(n-1)
-- i5 in6 vdd
-- o5 o5
-- o6 o6
-------------------------------------------------------------------
port map(
i0 => '0',
i1 => z_in(i),
i2 => y_in(i),
i3 => x_in(i),
i4 => bbus_in(i),
i5 => '1',
o5 => bbus_out(i),
o6 => lut_o6(i)
);
end generate;
-- creating the carry chain
-- carry4 primitive is described in virtex 6 user guide on page 108:
-- http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/virtex6_hdl.pdf
initial_slice: if is_initial_slice = true generate
init_cc: carry4
-------------------------------------------------------------------
-- table of names and connections
-- user guide usage in adder
-- ---------- --------------
-- co msb is carry out, rest is not connected
-- o sum
-- ci in the initial slice: not connected
-- cyinit in the initial slice: add / ~sub
-- di bbus(n-1)
-- s lut_o6(n)
-------------------------------------------------------------------
port map(
co => cc_co,
o => cc_o,
cyinit => '0',
ci => carry_in,
di => cc_di,
s => cc_s
);
end generate;
further_slice: if is_initial_slice = false generate
further_cc: carry4
-------------------------------------------------------------------
-- table of names and connections
-- user guide usage in adder
-- ---------- --------------
-- co msb is carry out, rest is not connected
-- o sum
-- ci carry from previous slice
-- cyinit in further slices: not connected
-- di bbus(n-1)
-- s lut_o6(n)
-------------------------------------------------------------------
port map(
co => cc_co,
o => cc_o,
cyinit => '0',
ci => carry_in,
di => cc_di,
s => cc_s
);
end generate;
-- connect the last used output of the carry chain to the slice output
carry_out <= cc_co(input_word_size - 1);
-- creating the flip flops
sum_register: if use_output_ff = true generate
ffs: for i in 0 to (input_word_size - 1) generate
ff_i: fdce
generic map(
-- initialize all flip flops with '0'
init => '0'
)
-------------------------------------------------------------------
-- table of names and connections
-- user guide usage in adder
-- ---------- --------------
-- clr clear
-- ce clock_enable, always '1'
-- d cc_o
-- c clock
-- q sum(n)
-------------------------------------------------------------------
port map(
clr => clear,
ce => clock_enable,
d => cc_o(i),
c => clock,
q => sum_out(i)
);
end generate;
end generate;
-- bypassing the flip flops in case of a asynchronous circuit
bypass: if use_output_ff = false generate
sum_out <= cc_o(input_word_size - 1 downto 0);
end generate;
end architecture;
| gpl-3.0 | 18912c145d0d74b9612db8c3806379e6 | 0.521758 | 3.693903 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/biu_struct.vhd | 3 | 23,856 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.cpu86pack.ALL;
ENTITY biu IS
PORT(
clk : IN std_logic;
csbus : IN std_logic_vector (15 DOWNTO 0);
dbus_in : IN std_logic_vector (7 DOWNTO 0);
dbusdp_in : IN std_logic_vector (15 DOWNTO 0);
decode_state : IN std_logic;
flush_coming : IN std_logic;
flush_req : IN std_logic;
intack : IN std_logic;
intr : IN std_logic;
iomem : IN std_logic;
ipbus : IN std_logic_vector (15 DOWNTO 0);
irq_block : IN std_logic;
nmi : IN std_logic;
opc_req : IN std_logic;
read_req : IN std_logic;
reset : IN std_logic;
status : IN status_out_type;
word : IN std_logic;
write_req : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
biu_error : OUT std_logic;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
flush_ack : OUT std_logic;
instr : OUT instruction_type;
inta : OUT std_logic;
inta1 : OUT std_logic;
iom : OUT std_logic;
irq_req : OUT std_logic;
latcho : OUT std_logic;
mdbus_out : OUT std_logic_vector (15 DOWNTO 0);
rdn : OUT std_logic;
rw_ack : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END biu ;
ARCHITECTURE struct OF biu IS
SIGNAL abus_s : std_logic_vector(19 DOWNTO 0);
SIGNAL abusdp_in : std_logic_vector(19 DOWNTO 0);
SIGNAL addrplus4 : std_logic;
SIGNAL biu_status : std_logic_vector(2 DOWNTO 0);
SIGNAL csbusbiu_s : std_logic_vector(15 DOWNTO 0);
SIGNAL halt_instr : std_logic;
SIGNAL inta2_s : std_logic; -- Second INTA pulse, used to latch 8 bist vector
SIGNAL ipbusbiu_s : std_logic_vector(15 DOWNTO 0);
SIGNAL ipbusp1_s : std_logic_vector(15 DOWNTO 0);
SIGNAL irq_ack : std_logic;
SIGNAL irq_clr : std_logic;
SIGNAL irq_type : std_logic_vector(1 DOWNTO 0);
SIGNAL latchabus : std_logic;
SIGNAL latchclr : std_logic;
SIGNAL latchm : std_logic;
SIGNAL latchrw : std_logic;
SIGNAL ldposplus1 : std_logic;
SIGNAL lutbus : std_logic_vector(15 DOWNTO 0);
SIGNAL mux_addr : std_logic_vector(2 DOWNTO 0);
SIGNAL mux_data : std_logic_vector(3 DOWNTO 0);
SIGNAL mux_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL muxabus : std_logic_vector(1 DOWNTO 0);
SIGNAL nbreq : std_logic_vector(2 DOWNTO 0);
SIGNAL rdcode_s : std_logic;
SIGNAL rddata_s : std_logic;
SIGNAL reg1freed : std_logic; -- Delayed version (1 clk) of reg1free
SIGNAL reg4free : std_logic;
SIGNAL regnbok : std_logic;
SIGNAL regplus1 : std_logic;
SIGNAL w_biufsm_s : std_logic;
SIGNAL wr_s : std_logic;
SIGNAL flush_ack_internal : std_logic;
SIGNAL inta1_internal : std_logic;
SIGNAL irq_req_internal : std_logic;
SIGNAL latcho_internal : std_logic;
signal nmi_s : std_logic;
signal nmipre_s : std_logic_vector(1 downto 0); -- metastability first FF for nmi
signal outbus_s : std_logic_vector(7 downto 0); -- used in out instr. bus streering
signal latchmd_s : std_logic; -- internal rdl_s signal
signal abusdp_inp1l_s: std_logic_vector(15 downto 0);
signal latchrw_d_s: std_logic; -- latchrw delayed 1 clk cycle
signal latchclr_d_s: std_logic; -- latchclr delayed 1 clk cycle
signal iom_s : std_logic;
signal instr_trace_s : std_logic; -- TF latched by exec_state pulse
signal irq_req_s : std_logic;
-- Component Declarations
COMPONENT biufsm
PORT (
clk : IN std_logic ;
flush_coming : IN std_logic ;
flush_req : IN std_logic ;
irq_req : IN std_logic ;
irq_type : IN std_logic_vector (1 DOWNTO 0);
opc_req : IN std_logic ;
read_req : IN std_logic ;
reg1freed : IN std_logic ;
reg4free : IN std_logic ;
regnbok : IN std_logic ;
reset : IN std_logic ;
w_biufsm_s : IN std_logic ;
write_req : IN std_logic ;
addrplus4 : OUT std_logic ;
biu_error : OUT std_logic ;
biu_status : OUT std_logic_vector (2 DOWNTO 0);
irq_ack : OUT std_logic ;
irq_clr : OUT std_logic ;
latchabus : OUT std_logic ;
latchclr : OUT std_logic ;
latchm : OUT std_logic ;
latcho : OUT std_logic ;
latchrw : OUT std_logic ;
ldposplus1 : OUT std_logic ;
muxabus : OUT std_logic_vector (1 DOWNTO 0);
rdcode_s : OUT std_logic ;
rddata_s : OUT std_logic ;
regplus1 : OUT std_logic ;
rw_ack : OUT std_logic ;
wr_s : OUT std_logic ;
flush_ack : BUFFER std_logic ;
inta1 : BUFFER std_logic
);
END COMPONENT;
COMPONENT formatter
PORT (
lutbus : IN std_logic_vector (15 DOWNTO 0);
mux_addr : OUT std_logic_vector (2 DOWNTO 0);
mux_data : OUT std_logic_vector (3 DOWNTO 0);
mux_reg : OUT std_logic_vector (2 DOWNTO 0);
nbreq : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT regshiftmux
PORT (
clk : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
flush_req : IN std_logic ;
latchm : IN std_logic ;
latcho : IN std_logic ;
mux_addr : IN std_logic_vector (2 DOWNTO 0);
mux_data : IN std_logic_vector (3 DOWNTO 0);
mux_reg : IN std_logic_vector (2 DOWNTO 0);
nbreq : IN std_logic_vector (2 DOWNTO 0);
regplus1 : IN std_logic ;
ldposplus1 : IN std_logic ;
reset : IN std_logic ;
irq : IN std_logic ;
inta1 : IN std_logic ; -- Added for ver 0.71
inta2_s : IN std_logic ;
irq_type : IN std_logic_vector (1 DOWNTO 0);
instr : OUT instruction_type ;
halt_instr : OUT std_logic ;
lutbus : OUT std_logic_vector (15 DOWNTO 0);
reg1free : BUFFER std_logic ;
reg1freed : BUFFER std_logic ; -- Delayed version (1 clk) of reg1free
regnbok : OUT std_logic
);
END COMPONENT;
BEGIN
-------------------------------------------------------------------------
-- Databus Latch
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
dbus_out <= DONTCARE(7 downto 0);
elsif rising_edge(clk) then
if latchrw='1' then -- Latch Data from DataPath
dbus_out <= outbus_s;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- OUT instruction bus steering
-- IO/~M & A[1:0]
---------------------------------------------------------------------------
process(dbusdp_in,abus_s)
begin
if abus_s(0)='0' then
outbus_s <= dbusdp_in(7 downto 0); -- D0
else
outbus_s <= dbusdp_in(15 downto 8); -- D1
end if;
end process;
---------------------------------------------------------------------------
-- Latch word for BIU FSM
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
w_biufsm_s<='0';
elsif rising_edge(clk) then
if latchrw='1' then
w_biufsm_s<=word;
end if;
end if;
end process;
-- metastability sync
process(reset,clk) -- ireg
begin
if reset='1' then
nmipre_s <= "00";
elsif rising_edge(clk) then
nmipre_s <= nmipre_s(0) & nmi;
end if;
end process;
-- set/reset FF
process(reset, clk) -- ireg
begin
if (reset='1') then
nmi_s <= '0';
elsif rising_edge(clk) then
if (irq_clr='1') then
nmi_s <= '0';
else
nmi_s <= nmi_s or ((not nmipre_s(1)) and nmipre_s(0));
end if;
end if;
end process;
-- Instruction trace flag, the trace flag is latched by the decode_state signal. This will
-- result in the instruction after setting the trace flag not being traced (required).
-- The instr_trace_s flag is not set if the current instruction is a HLT
process(reset, clk)
begin
if (reset='1') then
instr_trace_s <= '0';
elsif rising_edge(clk) then
if (decode_state='1' and halt_instr='0') then
instr_trace_s <= status.flag(8);
end if;
end if;
end process;
-- int0_req=Divider/0 error
-- status(8)=TF
-- status(9)=IF
irq_req_s <= '1' when ((status.div_err='1' or instr_trace_s='1' or nmi_s='1' or (status.flag(9)='1' and intr='1')) and irq_block='0') else '0';
-- set/reset FF
process(reset, clk) -- ireg
begin
if (reset='1') then
irq_req_internal <= '0';
elsif rising_edge(clk) then
if (irq_clr='1') then
irq_req_internal <= '0';
elsif irq_req_s='1' then
irq_req_internal <= '1';
end if;
end if;
end process;
--process (nmi_s,status,intr)
process (reset,clk)
begin
if reset='1' then
irq_type <= (others => '0'); -- Don't care value
elsif rising_edge(clk) then
if irq_req_internal='1' then
if nmi_s='1' then
irq_type <= "10"; -- NMI result in INT2
elsif status.flag(8)='1' then
irq_type <= "01"; -- TF result in INT1
else
irq_type <= "00"; -- INTR result in INT <DBUS>
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Delayed signals
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
latchrw_d_s <= '0';
latchclr_d_s <= '0';
elsif rising_edge(clk) then
latchrw_d_s <= latchrw;
latchclr_d_s <= latchclr;
end if;
end process;
---------------------------------------------------------------------------
-- IO/~M strobe latch
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
iom_s <= '0';
elsif rising_edge(clk) then
if latchrw='1' and muxabus/="00" then
iom_s <= iomem;
elsif latchrw='1' then
iom_s <= '0';
end if;
end if;
end process;
iom <= iom_s;
---------------------------------------------------------------------------
-- Shifted WR strobe latch, to add some address and data hold time the WR
-- strobe is negated .5 clock cycles before address and data changes. This
-- is implemented using the falling edge of the clock. Generally using
-- both edges of a clock is not recommended. If this is not desirable
-- use the latchclr signal with the rising edge of clk. This will result
-- in a full clk cycle for the data hold.
---------------------------------------------------------------------------
process(clk,reset) -- note wr should be 1 clk cycle after latchrw
begin
if reset='1' then
wran <= '1';
elsif falling_edge(clk) then -- wran is negated 0.5 cycle before data&address changes
if latchclr_d_s='1' then
wran <= '1';
elsif wr_s='1' then
wran<='0';
end if;
-- elsif rising_edge(clk) then -- wran negated 1 clk cycle before data&address changes
-- if latchclr='1' then
-- wran <= '1';
-- elsif wr_s='1' then
-- wran<='0';
-- end if;
end if;
end process;
---------------------------------------------------------------------------
-- WR strobe latch. This signal can be use to drive the tri-state drivers
-- and will result in a data hold time until the end of the write cycle.
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
wrn <= '1';
elsif rising_edge(clk) then
if latchclr_d_s='1' then -- Change wrn at the same time as addr changes
wrn <= '1';
elsif wr_s='1' then
wrn<='0';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- RD strobe latch
-- rd is active low and connected to top entity
-- Use 1 clk delayed latchrw_d_s signal
-- Original signals were rd_data_s and rd_code_s, new signals rddata_s and
-- rdcode_s.
-- Add flushreq_s, prevend rd signal from starting
---------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
rdn <= '1';
latchmd_s <= '0';
elsif rising_edge(clk) then
if latchclr_d_s='1' then
rdn <= '1';
latchmd_s <= '0';
elsif latchrw_d_s='1' then
latchmd_s <= rddata_s;
-- Bug reported by Rick Kilgore
-- ver 0.69, stops RD from being asserted during second inta
rdn <= not((rdcode_s or rddata_s) AND NOT intack);
-- The next second was added to create a updown pulse on the rd strobe
-- during a flush action. This will result in a dummy read cycle (unavoidable?)
elsif latchrw='1' then
latchmd_s <= rddata_s;
rdn <= not(rdcode_s or rddata_s);
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Second INTA strobe latch
---------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
inta2_s<= '0';
elsif rising_edge(clk) then
if latchclr_d_s='1' then
inta2_s <= '0';
elsif latchrw_d_s='1' then
inta2_s <= intack;
end if;
end if;
end process;
inta <= not (inta2_s OR inta1_internal);
---------------------------------------------------------------------------
-- Databus stearing for the datapath input
-- mdbus_out(31..16) is only used for "int x", the value si used to load
-- ipreg at the same time as loading cs.
-- Note mdbus must be valid (i.e. contain dbus value) before rising edge
-- of wrn/rdn
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
mdbus_out <= (others => '0');
elsif rising_edge(clk) then
if latchmd_s='1' then
if word='0' then -- byte read
mdbus_out <= X"00" & dbus_in;
else
if muxabus="00" then -- first cycle of word read
mdbus_out(15 downto 8) <= dbus_in;
else -- Second cycle
mdbus_out(7 downto 0) <= dbus_in;
end if;
end if;
end if;
end if;
end process;
process(reset,clk)
begin
if reset='1' then
ipbusbiu_s <= RESET_IP_C; -- start 0x0000, CS=FFFF
csbusbiu_s <= RESET_CS_C;
elsif rising_edge(clk) then
if latchabus='1' then
if (addrplus4='1') then
ipbusbiu_s <= ipbusbiu_s+'1';
else
ipbusbiu_s <= ipbus; -- get new address after flush
csbusbiu_s <= csbus;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- Latch datapath address+4 for mis-aligned R/W
-------------------------------------------------------------------------
ipbusp1_s <= ipbus+'1';
abusdp_inp1l_s <= ipbus when latchrw='0' else ipbusp1_s;
process(abusdp_inp1l_s,muxabus,csbusbiu_s,ipbusbiu_s,csbus,ipbus)
begin
case muxabus is
when "01" => abus_s <= (csbus&"0000") + ("0000"&ipbus); --abusdp_in;
when "10" => abus_s <= (csbus&"0000") + ("0000"&abusdp_inp1l_s); -- Add 1 if odd address and write word
when others => abus_s <= (csbusbiu_s&"0000") + ("0000"&ipbusbiu_s); -- default to BIU word address
end case;
end process;
-------------------------------------------------------------------------
-- Address/Databus Latch
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
abus <= RESET_VECTOR_C;
elsif rising_edge(clk) then
if latchrw='1' then -- Latch Address
abus <= abus_s;
end if;
end if;
end process;
-- Instance port mappings.
fsm : biufsm
PORT MAP (
clk => clk,
flush_coming => flush_coming,
flush_req => flush_req,
irq_req => irq_req_internal,
irq_type => irq_type,
opc_req => opc_req,
read_req => read_req,
reg1freed => reg1freed,
reg4free => reg4free,
regnbok => regnbok,
reset => reset,
w_biufsm_s => w_biufsm_s,
write_req => write_req,
addrplus4 => addrplus4,
biu_error => biu_error,
biu_status => biu_status,
irq_ack => irq_ack,
irq_clr => irq_clr,
latchabus => latchabus,
latchclr => latchclr,
latchm => latchm,
latcho => latcho_internal,
latchrw => latchrw,
ldposplus1 => ldposplus1,
muxabus => muxabus,
rdcode_s => rdcode_s,
rddata_s => rddata_s,
regplus1 => regplus1,
rw_ack => rw_ack,
wr_s => wr_s,
flush_ack => flush_ack_internal,
inta1 => inta1_internal
);
I4 : formatter
PORT MAP (
lutbus => lutbus,
mux_addr => mux_addr,
mux_data => mux_data,
mux_reg => mux_reg,
nbreq => nbreq
);
shift : regshiftmux
PORT MAP (
clk => clk,
dbus_in => dbus_in,
flush_req => flush_req,
latchm => latchm,
latcho => latcho_internal,
mux_addr => mux_addr,
mux_data => mux_data,
mux_reg => mux_reg,
nbreq => nbreq,
regplus1 => regplus1,
ldposplus1 => ldposplus1,
reset => reset,
irq => irq_ack,
inta1 => inta1_internal,
inta2_s => inta2_s,
irq_type => irq_type,
instr => instr,
halt_instr => halt_instr,
lutbus => lutbus,
reg1free => reg4free,
reg1freed => reg1freed,
regnbok => regnbok
);
flush_ack <= flush_ack_internal;
inta1 <= inta1_internal;
irq_req <= irq_req_internal;
latcho <= latcho_internal;
END struct;
| gpl-2.0 | cffcfb95f3c5d97ea97582f739c222ea | 0.430961 | 4.377248 | false | false | false | false |
CamelClarkson/MIPS | Register_File/sources/RFC.vhd | 2 | 1,440 | ----------------------------------------------------------------------------------
--MIPS Register File Test Bench
--By: Kevin Mottler
--Camel Clarkson 32 Bit MIPS Design Group
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RFC is
Port (
iClk : in std_logic;
i_Rst : in std_logic;
w_sel : in std_logic;
i_data : in std_logic;
R_sel_A : in std_logic;
R_sel_B : in std_logic;
A : out std_logic;
B : out std_logic
);
end RFC;
architecture Behavioral of RFC is
--Declares signals in processing the input logic
signal d_in : std_logic;
signal q_out : std_logic;
--Declares the D Flip Flop to be used
component DFlipFlop is
Port (
iClk : in std_logic;
D : in std_logic;
iRst : in std_logic;
Q : out std_logic
);
end component;
begin
--Instatiates the component D Flip Flop
inst_DFlipFlop: DFlipFlop
port map(
iClk => iClk,
D => d_in,
iRst => i_Rst,
Q => q_out
);
--Creates input logic to the D Flip Flop, which is the d_in for the flip flop
d_in <= (w_sel AND i_data) OR (not(w_sel) AND q_out);
--Creates a tri state buffer based on the select bit. If the either of the select bits are high, the entity outputs data
A <= q_out when (R_sel_A = '1') else 'Z';
B <= q_out when (R_sel_B = '1') else 'Z';
end Behavioral;
| mit | 0b6b7db4a47b25b24a8e2a1ea7c79c5a | 0.54375 | 3.453237 | false | false | false | false |
nsauzede/cpu86 | testbench/uartrx.vhd | 1 | 10,225 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Design unit : Simple UART (receiver) --
-------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY uartrx IS
PORT(
clk : IN std_logic;
enable : IN std_logic; -- 16 x bit_rate receive clock enable
resetn : IN std_logic;
dbus : OUT std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic;
rdrf : OUT std_logic;
ferror : OUT std_logic;
rx : IN std_logic
);
END uartrx ;
architecture rtl of uartrx is
type states is (s0,s1,s2,s3);
signal state,nextstate : states;
signal rxreg_s : std_logic_vector(7 downto 0); -- Receive Holding Register
signal rxshift_s : std_logic_vector(8 downto 0); -- Receive Shift Register (9 bits!)
signal sample_s : std_logic; -- Sample rx input
signal rsrl_s : std_logic; -- Receive Shift Register Latch (rxpulse_s)
signal synccnt_s : std_logic_vector(3 downto 0); -- 0..15
signal bitcount_s : std_logic_vector(3 downto 0); -- 0..9
type state_type is (st0,st1,st2,st3); -- RDRF flag FSM
signal current_state,next_state : state_type ;
begin
-------------------------------------------------------------------------------
-- Receive Data Register
-------------------------------------------------------------------------------
process (clk,resetn)
begin
if (resetn='0') then
rxreg_s <= (others => '1');
elsif (rising_edge(clk)) then
if (enable='1' and rsrl_s='1') then
rxreg_s <= rxshift_s(8 downto 1); -- connect to outside world
end if;
end if;
end process;
dbus <= rxreg_s; -- Connect to outside world
----------------------------------------------------------------------------
-- FSM1, sample input data
----------------------------------------------------------------------------
process (clk,resetn)
begin
if (resetn = '0') then -- Reset State
state <= s0;
elsif rising_edge(clk) then
if enable='1' then
state <= nextstate; -- Set Current state
end if;
end if;
end process;
process(state,rx,sample_s,bitcount_s)
begin
case state is
when s0 =>
if rx='1' then nextstate <= s1;
else nextstate <= s0; -- Wait
end if;
when s1 =>
if rx='0' then nextstate <= s2; -- falling edge
else nextstate <= s1; -- or s0??? Wait
end if;
when s2 => -- Falling edge detected, valid start bit? RXCLK=0,1
if (rx='0' and sample_s='1') then nextstate <= s3; -- so good so far
elsif (rx='1') then nextstate <= s1; -- oops 1 detected, must be noise
else nextstate <= s2; -- wait for sample pulse
end if;
when s3 => -- Start bit detected
if (sample_s='1' and bitcount_s="1000") -- Changed !!! from 1001
then nextstate <= s0;
else nextstate <= s3; -- wait
end if;
when others => nextstate <= s0;
end case;
end process;
-------------------------------------------------------------------------------
-- Sample clock
-------------------------------------------------------------------------------
process(clk,resetn)
begin
if (resetn='0') then
synccnt_s <= "1000"; -- sample clock
elsif (rising_edge(clk)) then
if enable='1' then
if (state=s0 or state=s1) then
synccnt_s <= "1000";
else
synccnt_s <= synccnt_s+'1';
end if;
end if;
end if;
end process;
sample_s <= '1' when synccnt_s="0000" else '0';
-------------------------------------------------------------------------------
-- Bit counter
-------------------------------------------------------------------------------
process(clk,resetn)
begin
if (resetn='0') then
bitcount_s <= (others => '0');
elsif rising_edge(clk) then
if enable='1' then
if (state=s0 or state=s1) then
bitcount_s <= (others => '1');
elsif (sample_s='1') then
bitcount_s <= bitcount_s + '1';
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Receive Shift Register
----------------------------------------------------------------------------
process(clk,resetn)
begin
if (resetn='0') then
rxshift_s <= (others => '1');
elsif rising_edge(clk) then
if enable='1' then
if (sample_s='1') then
rxshift_s <= rx & rxshift_s(8 downto 1);
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- RSRL strobe
----------------------------------------------------------------------------
rsrl_s <= '1' when (sample_s='1' and bitcount_s="1000" and rx='1') else '0';
----------------------------------------------------------------------------
-- Framing Error, low stop bit detected
----------------------------------------------------------------------------
ferror <= '1' when (sample_s='1' and bitcount_s="1000" and rx='0') else '0';
----------------------------------------------------------------------------
-- FSM2, if rsrl='1' then assert rdrf until rd strobe
----------------------------------------------------------------------------
process(clk,resetn)
begin
if (resetn = '0') then
current_state <= st0;
elsif (clk'event and clk = '1') then
current_state <= next_state;
end if;
end process;
process (current_state,rdn,rsrl_s,enable)
begin
case current_state is
when st0 =>
rdrf <= '0';
if (enable='1' and rsrl_s='1') then next_state <= st1;
else next_state <= st0;
end if;
when st1 =>
rdrf<='1';
if (rdn='0') then next_state <= st2;
else next_state <= st1;
end if;
when st2 =>
rdrf <= '1';
if (rdn='1') then next_state <= st0;
else next_state <= st2;
end if;
when others =>
rdrf <= '0';
next_state <= st0;
end case;
end process;
end rtl;
| gpl-2.0 | b3314da9bb652a0663de6c4fa88a02e2 | 0.353839 | 5.177215 | false | false | false | false |
nsauzede/cpu86 | mx_sdram/ram.vhd | 1 | 6,413 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY ram IS
PORT
(
address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram;
ARCHITECTURE SYN OF ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "mon88.mif",
intended_device_family => "MAX 10",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 32768,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "DONT_CARE",
widthad_a => 15,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "mon88.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "2"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "mon88.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | bbb3bc3e2d70e295a41b0ee024b9f7e5 | 0.675815 | 3.656214 | false | false | false | false |
nsauzede/cpu86 | testbench/utils.vhd | 1 | 6,838 | ---------------------------------------------------------------------------
-- Bits and pieces from Modelsim, http://www.stefanvhdl.com/ and Ben Cohen.
-- Some bits modified
-- ------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package utils is
attribute builtin_subprogram : string;
function to_std_logic_vector(c: character) return std_logic_vector;
function std_to_string (inp : std_logic_vector) return string;
function std_to_char (inp : std_logic_vector) return character;
function std_to_hex (Vec : std_logic_vector) return string; -- Std to hex string
procedure init_signal_spy (
source_signal : IN string ;
destination_signal : IN string ;
verbose : IN integer := 0) ;
attribute builtin_subprogram of init_signal_spy : procedure is "init_signal_spy_vhdl";
function to_real( time_val : IN time ) return real;
attribute builtin_subprogram of to_real: function is "util_to_real";
function to_time( real_val : IN real ) return time;
attribute builtin_subprogram of to_time: function is "util_to_time";
function get_resolution return real;
attribute builtin_subprogram of get_resolution: function is "util_get_resolution";
end;
package body utils is
-- converts a character into a std_logic_vector
function to_std_logic_vector(c: character) return std_logic_vector is
variable sl: std_logic_vector(7 downto 0);
begin
case c is
when ' ' => sl:=X"20";
when '0' => sl:=X"30";
when '1' => sl:=X"31";
when '2' => sl:=X"32";
when '3' => sl:=X"33";
when '4' => sl:=X"34";
when '5' => sl:=X"35";
when '6' => sl:=X"36";
when '7' => sl:=X"37";
when '8' => sl:=X"38";
when '9' => sl:=X"39";
when 'A' => sl:=X"41";
when 'B' => sl:=X"42";
when 'C' => sl:=X"43";
when 'D' => sl:=X"44";
when 'E' => sl:=X"45";
when 'F' => sl:=X"46";
when 'G' => sl:=X"47";
when 'H' => sl:=X"48";
when 'I' => sl:=X"49";
when 'J' => sl:=X"4A";
when 'K' => sl:=X"4B";
when 'L' => sl:=X"4C";
when 'M' => sl:=X"4D";
when 'N' => sl:=X"4E";
when 'O' => sl:=X"4F";
when 'P' => sl:=X"50";
when 'Q' => sl:=X"51";
when 'R' => sl:=X"52";
when 'S' => sl:=X"53";
when 'T' => sl:=X"54";
when 'U' => sl:=X"55";
when 'V' => sl:=X"56";
when 'W' => sl:=X"57";
when 'X' => sl:=X"58";
when 'Y' => sl:=X"59";
when 'Z' => sl:=X"5A";
when LF =>sl:=X"0A";
when CR =>sl:=X"0B";
when ESC=>sl:=X"1B";
when others =>
assert false
report "ERROR: to_std_logic_vector()-> failed to convert input character";
sl := X"00";
end case;
return sl;
end to_std_logic_vector;
procedure init_signal_spy (
source_signal : IN string ;
destination_signal : IN string ;
verbose : IN integer := 0) is
begin
assert false
report "ERROR: builtin subprogram not called"
severity note;
end;
function to_real( time_val : IN time ) return real is
begin
assert false
report "ERROR: builtin function not called"
severity note;
return 0.0;
end;
function to_time( real_val : IN real ) return time is
begin
assert false
report "ERROR: builtin function not called"
severity note;
return 0 ns;
end;
function get_resolution return real is
begin
assert false
report "ERROR: builtin function not called"
severity note;
return 0.0;
end;
function std_to_string(inp: std_logic_vector) return string is
variable temp: string(inp'left downto inp'right) := (others => 'X');
begin
for i in inp'left downto inp'right loop
if (inp(i) = '1') then
temp(i) := '1';
elsif (inp(i) = '0') then
temp(i) := '0';
end if;
end loop;
return temp;
end std_to_string;
function std_to_char(inp: std_logic_vector) return character is
constant ASCII_TABLE : string (1 to 256) :=
".......... .. .................. !" & '"' &
"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHI" &
"JKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnop" &
"qrstuvwxyz{|}~........................." &
"......................................." &
"......................................." &
"..........................";
variable temp : integer;
begin
-- if inp=X"0A" then
-- return LF;
-- elsif inp=X"0D" then
-- return CR;
-- else
temp:=CONV_INTEGER(inp)+1;
return ASCII_TABLE(temp);
-- end if;
end std_to_char;
function std_to_hex(Vec : std_logic_vector) return string is
constant L : natural := Vec'length;
alias MyVec : std_logic_vector(L - 1 downto 0) is Vec;
constant LVecFul : natural := ((L - 1)/4 + 1)*4;
variable VecFul : std_logic_vector(LVecFul - 1 downto 0)
:= (others => '0');
constant StrLgth : natural := LVecFul/4;
variable Res : string(1 to StrLgth) := (others => ' ');
variable TempVec : std_logic_vector(3 downto 0);
variable i : integer := LVecFul - 1;
variable Index : natural := 1;
begin
assert L > 1 report "(std_to_hex) requires a vector!" severity error;
VecFul(L - 1 downto 0) := MyVec(L -1 downto 0);
while (i - 3 >= 0) loop
TempVec(3 downto 0) := VecFul(i downto i - 3);
case TempVec(3 downto 0) is
when "0000" => Res(Index) := '0';
when "0001" => Res(Index) := '1';
when "0010" => Res(Index) := '2';
when "0011" => Res(Index) := '3';
when "0100" => Res(Index) := '4';
when "0101" => Res(Index) := '5';
when "0110" => Res(Index) := '6';
when "0111" => Res(Index) := '7';
when "1000" => Res(Index) := '8';
when "1001" => Res(Index) := '9';
when "1010" => Res(Index) := 'A';
when "1011" => Res(Index) := 'B';
when "1100" => Res(Index) := 'C';
when "1101" => Res(Index) := 'D';
when "1110" => Res(Index) := 'E';
when "1111" => Res(Index) := 'F';
when others => Res(Index) := 'x';
end case; -- TempVec(3 downto 0)
Index := Index + 1;
i := i - 4;
end loop;
return Res;
end std_to_hex;
end;
| gpl-2.0 | 253a4af7cc542b2f3d0d74e94e27311e | 0.482159 | 3.522926 | false | false | false | false |
AUT-CEIT/Arch101 | sample-rtl/register.vhd | 1 | 773 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 05-03-2017
-- Module Name: register.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity four_register is
port (d : in std_logic_vector(3 downto 0);
clk, load, shift : in std_logic;
qout : out std_logic);
end entity;
architecture behavior of four_register is
signal q : std_logic_vector(3 downto 0);
begin
process (clk)
begin
if clk = '1' and clk'event then
if load = '1' then
q <= d;
elsif shift='1' then
qout <= q(3);
q <= q(2 downto 0) & '0';
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 616e14aeeadb90a94c480cff76686dd4 | 0.505821 | 3.513636 | false | false | false | false |
CamelClarkson/MIPS | Register_File/sources/R_Decoder.vhd | 2 | 3,595 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/30/2016 02:38:42 PM
-- Design Name:
-- Module Name: W_Decoder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decoder is
Port (
i_w_Addr : in std_logic_vector(4 downto 0);
o_w_Addr : out std_logic_vector(31 downto 0)
);
end Decoder;
architecture Behavioral of Decoder is
begin
process(i_w_Addr)
begin
case i_w_Addr is
when "00000" =>
o_w_Addr <= "00000000000000000000000000000001";
when "00001" =>
o_w_Addr <= "00000000000000000000000000000010";
when "00010" =>
o_w_Addr <= "00000000000000000000000000000100";
when "00011" =>
o_w_Addr <= "00000000000000000000000000001000";
when "00100" =>
o_w_Addr <= "00000000000000000000000000010000";
when "00101" =>
o_w_Addr <= "00000000000000000000000000100000";
when "00110" =>
o_w_Addr <= "00000000000000000000000001000000";
when "00111" =>
o_w_Addr <= "00000000000000000000000010000000";
when "01000" =>
o_w_Addr <= "00000000000000000000000100000000";
when "01001" =>
o_w_Addr <= "00000000000000000000001000000000";
when "01010" =>
o_w_Addr <= "00000000000000000000010000000000";
when "01011" =>
o_w_Addr <= "00000000000000000000100000000000";
when "01100" =>
o_w_Addr <= "00000000000000000001000000000000";
when "01101" =>
o_w_Addr <= "00000000000000000010000000000000";
when "01110" =>
o_w_Addr <= "00000000000000000100000000000000";
when "01111" =>
o_w_Addr <= "00000000000000001000000000000000";
when "10000" =>
o_w_Addr <= "00000000000000010000000000000000";
when "10001" =>
o_w_Addr <= "00000000000000100000000000000000";
when "10010" =>
o_w_Addr <= "00000000000001000000000000000000";
when "10011" =>
o_w_Addr <= "00000000000010000000000000000000";
when "10100" =>
o_w_Addr <= "00000000000100000000000000000000";
when "10101" =>
o_w_Addr <= "00000000001000000000000000000000";
when "10110" =>
o_w_Addr <= "00000000010000000000000000000000";
when "10111" =>
o_w_Addr <= "00000000100000000000000000000000";
when "11000" =>
o_w_Addr <= "00000001000000000000000000000000";
when "11001" =>
o_w_Addr <= "00000010000000000000000000000000";
when "11010" =>
o_w_Addr <= "00000100000000000000000000000000";
when "11011" =>
o_w_Addr <= "00001000000000000000000000000000";
when "11100" =>
o_w_Addr <= "00010000000000000000000000000000";
when "11101" =>
o_w_Addr <= "00100000000000000000000000000000";
when "11110" =>
o_w_Addr <= "01000000000000000000000000000000";
when "11111" =>
o_w_Addr <= "10000000000000000000000000000000";
when others =>
o_w_Addr <= "00000000000000000000000000000000";
end case;
end process;
end Behavioral;
| mit | ca707efbf3850e5968bbd66b706dfd1b | 0.608901 | 4.482544 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Encryption_Decryption/bak/rc5.vhd | 1 | 1,788 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.RC5_PKG.ALL;
ENTITY rc5 IS
PORT (
clr, clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal
enc : IN STD_LOGIC; -- Encryption or decryption?
key_vld : IN STD_LOGIC; -- Indicate the input is user key
data_vld : IN STD_LOGIC; -- Indicate the input is user data
din : IN STD_LOGIC_VECTOR(63 downto 0);
dout : OUT STD_LOGIC_VECTOR(63 downto 0);
data_rdy : OUT STD_LOGIC -- Indicate the output data is ready
);
END rc5;
ARCHITECTURE struct OF rc5 IS -- Structural description
signal skey : rc5_rom_26;
signal key_rdy : std_logic;
signal dout_enc : std_logic_vector(63 downto 0);
signal dout_dec : std_logic_vector(63 downto 0);
signal dec_rdy : std_logic;
signal enc_rdy : std_logic;
signal enc_clr : std_logic;
signal dec_clr : std_logic;
--Key will be attached to din twice
signal key : std_logic_vector(127 downto 0);
BEGIN
enc_clr <= clr AND enc;
dec_clr <= clr AND NOT enc;
key(127 downto 64) <= din;
key( 63 downto 0) <= din;
U1: rc5_key
PORT MAP(clr=>clr, clk=>clk, key=>key, key_vld=>key_vld, --Input
skey=>skey, key_rdy=>key_rdy); --Output
U2: rc5_enc
PORT MAP(clr=>enc_clr, clk=>clk, din=>din, di_vld=>data_vld, key_rdy=>key_rdy, skey=>skey, --Input
dout=>dout_enc, do_rdy=>enc_rdy); --Output
U3: rc5_dec
PORT MAP(clr=>dec_clr, clk=>clk, din=>din, di_vld=>data_vld, key_rdy=>key_rdy, skey=>skey, --Input
dout=>dout_dec, do_rdy=>dec_rdy); --Output
WITH enc SELECT
dout<=dout_enc WHEN '1',
dout_dec WHEN OTHERS;
WITH enc SELECT
data_rdy<=enc_rdy WHEN '1',
dec_rdy WHEN OTHERS;
END struct;
| lgpl-2.1 | 00521f3d43b044208db1fc55ee0851f0 | 0.607383 | 2.9701 | false | false | false | false |
nsauzede/cpu86 | testbench/sram.vhd | 1 | 21,799 | -- ======================================================================================
-- A generic VHDL entity for a typical SRAM with complete timing parameters
--
-- Static memory, version 1.3 9. August 1996
--
-- ======================================================================================
--
-- (C) Andre' Klindworth, Dept. of Computer Science
-- University of Hamburg
-- Vogt-Koelln-Str. 30
-- 22527 Hamburg
-- [email protected]
--
-- This VHDL code may be freely copied as long as the copyright note isn't removed from
-- its header. Full affiliation of anybody modifying this file shall be added to the
-- header prior to further distribution.
-- The download procedure originates from DLX memory-behaviour.vhdl:
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
--
--
-- Features:
--
-- o generic memory size, width and timing parameters
--
-- o 18 typical SRAM timing parameters supported
--
-- o clear-on-power-up and/or download-on-power-up if requested by generic
--
-- o RAM dump into or download from an ASCII-file at any time possible
-- (requested by signal)
--
-- o pair of active-low and active-high Chip-Enable signals
--
-- o nWE-only memory access control
--
-- o many (but not all) timing and access control violations reported by assertions
--
--
--
-- RAM data file format:
--
-- The format of the ASCII-files for RAM download or dump is very simple:
-- Each line of the file consists of the memory address (given as a decimal number).
-- and the corresponding RAM data at this address (given as a binary number).
-- Any text in a line following the width-th digit of the binary number is ignored.
-- Please notice that address and data have to be seperated by a SINGLE blank,
-- that the binary number must have as many digits as specified by the generic width,
-- and that no additional blanks or blank lines are tolerated. Example:
--
-- 0 0111011010111101 This text is interpreted as a comment
-- 1 1011101010110010
-- 17 0010001001000100
--
--
-- Hints & traps:
--
-- If you have problems using this model, please feel free to to send me an e-mail.
-- Here are some potential problems which have been reported to me:
--
-- o There's a potential problem with passing the filenames for RAM download or
-- dump via port signals of type string. E.g. for Synopsys VSS, the string
-- assigned to a filename-port should have the same length as its default value.
-- If you are sure that you need a download or dump only once during a single
-- simulation run, you may remove the filename-ports from the interface list
-- and replace the constant string in the corresponding file declarations.
--
-- o Some simulators do not implement all of the standard TEXTIO-functions as
-- specified by the IEEE Std 1076-87 and IEEE Std 1076-93. Check it out.
-- If any of the (multiple overloaded) writeline, write, readline or
-- read functions that are used in this model is missing, you have to
-- write your own version and you should complain at your simulator tool
-- vendor for this deviation from the standard.
--
-- o If you are about to simulate a large RAM e.g. 4M * 32 Bit, representing
-- the RAM with a static array variable of 4 * 32 std_logic values uses a large
-- amount of memory and may result in an out-of-memory error. A potential remedy
-- for this is to use a dynamic data type, allocating memory for small blocks of
-- RAM data (e.g. a single word) only if they are actually referenced during a
-- simulation run. A version of the SRAM model with dynamic memory allocation
-- shall be available at the same WWW-site were you obtained this file or at:
-- http://tech-www.informatik.uni-hamburg.de/vhdl/models/sram/sram.html
--
--
-- Bugs:
--
-- No severe bugs have been found so far. Please report any bugs:
-- e-mail: [email protected]
--
library std;
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
ENTITY sram IS
GENERIC(
clear_on_power_up : boolean := TRUE;
download_on_power_up : boolean := TRUE;
trace_ram_load : boolean := FALSE;
enable_nWE_only_control : boolean := FALSE;
size : INTEGER := 262144;
adr_width : INTEGER := 18;
width : INTEGER := 8;
tAA_max : TIME := 20 NS;
tOHA_min : TIME := 3 NS;
tACE_max : TIME := 20 NS;
tDOE_max : TIME := 8 NS;
tLZOE_min : TIME := 0 NS;
tHZOE_max : TIME := 8 NS;
tLZCE_min : TIME := 3 NS;
tHZCE_max : TIME := 10 NS;
tWC_min : TIME := 20 NS;
tSCE_min : TIME := 18 NS;
tAW_min : TIME := 15 NS;
tHA_min : TIME := 0 NS;
tSA_min : TIME := 0 NS;
tPWE_min : TIME := 13 NS;
tSD_min : TIME := 10 NS;
tHD_min : TIME := 0 NS;
tHZWE_max : TIME := 10 NS;
tLZWE_min : TIME := 0 NS
);
-- if TRUE, RAM is initialized with zeroes at start of simulation
-- Clearing of RAM is carried out before download takes place
-- if TRUE, RAM is downloaded at start of simulation
-- Echoes the data downloaded to the RAM on the screen
-- (included for debugging purposes)
-- Read-/write access controlled by nWE only
-- nOE may be kept active all the time
--
--
--
-- Configuring RAM size
-- number of memory words
-- number of address bits
-- number of bits per memory word
-- READ-cycle timing parameters
-- Address Access Time
-- Output Hold Time
-- nCE/CE2 Access Time
-- nOE Access Time
-- nOE to Low-Z Output
-- OE to High-Z Output
-- nCE/CE2 to Low-Z Output
-- CE/nCE2 to High Z Output
-- WRITE-cycle timing parameters
-- Write Cycle Time
-- nCE/CE2 to Write End
-- tAW Address Set-up Time to Write End
-- tHA Address Hold from Write End
-- Address Set-up Time
-- nWE Pulse Width
-- Data Set-up to Write End
-- Data Hold from Write End
-- nWE Low to High-Z Output
-- nWE High to Low-Z Output
PORT(
-- in file specified by download_filename to the RAM
download_filename : IN string(1 to 13) := "loadfname.dat"; -- name of the download source file
nCE : IN std_logic := '1'; -- low-active Chip-Enable of the SRAM device; defaults to '1' (inactive)
nOE : IN std_logic := '1'; -- low-active Output-Enable of the SRAM device; defaults to '1' (inactive)
nWE : IN std_logic := '1'; -- low-active Write-Enable of the SRAM device; defaults to '1' (inactive)
A : IN std_logic_vector (adr_width-1 DOWNTO 0); -- address bus of the SRAM device
D : INOUT std_logic_vector (width-1 DOWNTO 0); -- bidirectional data bus to/from the SRAM device
CE2 : IN std_logic := '1'; -- high-active Chip-Enable of the SRAM device; defaults to '1' (active)
download : IN boolean := FALSE; -- A FALSE-to-TRUE transition on this signal downloads the data
-- Passing the filename via a port of type
-- ********** string may cause a problem with some
-- WATCH OUT! simulators. The string signal assigned
-- ********** to the port at least should have the
-- same length as the default value.
dump : IN boolean := FALSE; -- A FALSE-to-TRUE transition on this signal dumps
-- the current content of the memory to the file
-- specified by dump_filename.
dump_start : IN natural := 0; -- Written to the dump-file are the memory words from memory address
dump_end : IN natural := size-1; -- dump_start to address dump_end (default: all addresses)
dump_filename : IN string(1 to 13) := "dumpfname.dat" -- name of the dump destination file
-- (See note at port download_filename)
);
-- Declarations
END sram ;
-- hds interface_end
ARCHITECTURE behavior OF sram IS
FUNCTION Check_For_Valid_Data (a: std_logic_vector) RETURN BOOLEAN IS
VARIABLE result: BOOLEAN;
BEGIN
result := TRUE;
FOR i IN a'RANGE LOOP
result := (a(i) = '0') OR (a(i) = '1');
IF NOT result THEN EXIT;
END IF;
END LOOP;
RETURN result;
END Check_For_Valid_Data;
FUNCTION Check_For_Tristate (a: std_logic_vector) RETURN BOOLEAN IS
VARIABLE result: BOOLEAN;
BEGIN
result := TRUE;
FOR i IN a'RANGE LOOP
result := (a(i) = 'Z');
IF NOT result THEN EXIT;
END IF;
END LOOP;
RETURN result;
END Check_For_Tristate;
SIGNAL tristate_vec: std_logic_vector(D'RANGE); -- constant all-Z vector for data bus D
SIGNAL undef_vec: std_logic_vector(D'RANGE); -- constant all-X vector for data bus D
SIGNAL undef_adr_vec: std_logic_vector(A'RANGE); -- constant all-X vector for address bus
SIGNAL read_active: BOOLEAN := FALSE; -- Indicates whether the SRAM is sending on the D bus
SIGNAL read_valid: BOOLEAN := FALSE; -- If TRUE, the data output by the RAM is valid
SIGNAL read_data: std_logic_vector(D'RANGE); -- content of the memory location addressed by A
SIGNAL do_write: std_logic := '0'; -- A '0'->'1' transition on this signal marks
-- the moment when the data on D is stored in the
-- addressed memory location
SIGNAL adr_setup: std_logic_vector(A'RANGE); -- delayed value of A to model the Address Setup Time
SIGNAL adr_hold: std_logic_vector(A'RANGE); -- delayed value of A to model the Address Hold Time
SIGNAL valid_adr: std_logic_vector(A'RANGE); -- valid memory address derived from A after
-- considering Address Setup and Hold Times
BEGIN
PROCESS BEGIN -- static assignments to the variable length busses'
-- all-X and all-Z signal vectors
FOR i IN D'RANGE LOOP
tristate_vec(i) <= 'Z';
undef_vec(i) <= 'X';
END LOOP;
FOR i IN A'RANGE LOOP
undef_adr_vec(i) <= 'X';
END LOOP;
WAIT;
END PROCESS;
memory: PROCESS
CONSTANT low_address: natural := 0;
CONSTANT high_address: natural := size -1;
TYPE memory_array IS
ARRAY (natural RANGE low_address TO high_address) OF std_logic_vector(width-1 DOWNTO 0);
VARIABLE mem: memory_array;
VARIABLE address : natural;
VARIABLE write_data: std_logic_vector(width-1 DOWNTO 0);
VARIABLE outline : line;
PROCEDURE power_up (mem: inout memory_array; clear: boolean) IS
VARIABLE init_value: std_logic;
BEGIN
IF clear THEN
init_value := '0';
write(outline, string'("Initializing SRAM with zero ..."));
writeline(output, outline);
ELSE
init_value := 'X';
END IF;
FOR add IN low_address TO high_address LOOP
FOR j IN (width-1) DOWNTO 0 LOOP
mem(add)(j) := init_value;
END LOOP;
END LOOP;
END power_up;
PROCEDURE load (mem: INOUT memory_array; download_filename: IN string) IS
-- FILE source : text IS IN download_filename;
FILE source : text open READ_MODE is download_filename;
VARIABLE inline, outline : line;
VARIABLE add: natural;
VARIABLE c : character;
VARIABLE source_line_nr: integer := 1;
-- VARIABLE init_value: std_logic := 'U';
BEGIN
write(outline, string'("Loading SRAM from file ") & download_filename & string'(" ... ") );
writeline(output, outline);
WHILE NOT endfile(source) LOOP
readline(source, inline);
read(inline, add);
read(inline, c);
IF (c /= ' ') THEN
write(outline, string'("Syntax error in file '"));
write(outline, download_filename);
write(outline, string'("', line "));
write(outline, source_line_nr);
writeline(output, outline);
ASSERT FALSE
REPORT "RAM loader aborted."
SEVERITY FAILURE;
END IF;
FOR i IN (width -1) DOWNTO 0 LOOP
read(inline, c);
IF (c = '1') THEN
mem(add)(i) := '1';
ELSE
IF (c /= '0') THEN
write(outline, string'("-W- Invalid character '"));
write(outline, c);
write(outline, string'("' in Bitstring in '"));
write(outline, download_filename);
write(outline, '(');
write(outline, source_line_nr);
write(outline, string'(") is set to '0'"));
writeline(output, outline);
END IF;
mem(add)(i) := '0';
END IF;
END LOOP;
-- IF (trace_ram_load) THEN
-- write(outline, string'("RAM["));
-- write(outline, add);
-- write(outline, string'("] := "));
-- write(outline, mem(add));
-- writeline(output, outline );
-- END IF;
source_line_nr := source_line_nr +1;
END LOOP; -- WHILE
END load; -- PROCEDURE
PROCEDURE do_dump (mem: INOUT memory_array;
dump_start, dump_end: IN natural;
dump_filename: IN string) IS
-- FILE dest : text IS OUT dump_filename;
FILE dest : text open WRITE_MODE is dump_filename;
VARIABLE l : line;
-- VARIABLE c : character;
BEGIN
IF (dump_start > dump_end) OR (dump_end >= size) THEN
ASSERT FALSE
REPORT "Invalid addresses for memory dump. Cancelled."
SEVERITY ERROR;
ELSE
FOR add IN dump_start TO dump_end LOOP
write(l, add);
write(l, ' ');
-- FOR i IN (width-1) downto 0 LOOP
-- write(l, mem(add)(i));
-- END LOOP;
writeline(dest, l);
END LOOP;
END IF;
END do_dump; -- PROCEDURE
BEGIN
power_up(mem, clear_on_power_up);
IF download_on_power_up THEN
load(mem, download_filename);
END IF;
LOOP
IF do_write'EVENT and (do_write = '1') then
IF NOT Check_For_Valid_Data(D) THEN
IF D'EVENT AND Check_For_Valid_Data(D'DELAYED) THEN
-- commented out for RTL sims
-- write(outline, string'("-W- Data changes exactly at end-of-write to SRAM."));
-- writeline(output, outline);
write_data := D'delayed;
ELSE
write(outline, string'("-E- Data not valid at end-of-write to SRAM."));
writeline(output, outline);
write_data := undef_vec;
END IF;
ELSIF NOT D'DELAYED(tHD_min)'STABLE(tSD_min) THEN
write(outline, string'("-E- tSD violation: Data input changes within setup-time at end-of-write to SRAM."));
writeline(output, outline);
write_data := undef_vec;
ELSIF NOT D'STABLE(tHD_min) THEN
write(outline, string'("-E- tHD violation: Data input changes within hold-time at end-of-write to SRAM."));
writeline(output, outline);
write_data := undef_vec;
ELSIF nWE'DELAYED(tHD_min)'STABLE(tPWE_min) THEN
write(outline, string'("-E- tPWE violation: Pulse width of nWE too short at SRAM."));
writeline(output, outline);
write_data := undef_vec;
ELSE write_data := D;
END IF;
mem(CONV_INTEGER(valid_adr)) := write_data;
END IF;
IF Check_For_Valid_Data(valid_adr) THEN
read_data <= mem(CONV_INTEGER(valid_adr));
ELSE
read_data <= undef_vec;
END IF;
-- IF dump AND dump'EVENT THEN do_dump(mem, dump_start, dump_end, dump_filename);
-- END IF;
IF download AND download'EVENT THEN load(mem, download_filename);
END IF;
WAIT ON do_write, valid_adr, download;
END LOOP;
END PROCESS memory;
adr_setup <= TRANSPORT A AFTER tAA_max;
adr_hold <= TRANSPORT A AFTER tOHA_min;
valid_adr <= adr_setup WHEN Check_For_Valid_Data(adr_setup)
AND (adr_setup = adr_hold)
AND adr_hold'STABLE(tAA_max - tOHA_min) ELSE
undef_adr_vec;
read_active <= ( (nOE = '0') AND (nOE'DELAYED(tLZOE_min) = '0') AND nOE'STABLE(tLZOE_min)
AND ((nWE = '1') OR (nWE'DELAYED(tHZWE_max) = '0'))
AND (nCE = '0') AND (CE2 = '1') AND nCE'STABLE(tLZCE_min) AND CE2'STABLE(tLZCE_min))
OR (read_active AND (nOE'DELAYED(tHZOE_max) = '0')
AND (nWE'DELAYED(tHZWE_max) = '1')
AND (nCE'DELAYED(tHZCE_max) = '0') AND (CE2'DELAYED(tHZCE_max) = '1'));
read_valid <= ( (nOE = '0') AND nOE'STABLE(tDOE_max)
AND (nWE = '1') AND (nWE'DELAYED(tHZWE_max) = '1')
AND (nCE = '0') AND (CE2 = '1') AND nCE'STABLE(tACE_max) AND CE2'STABLE(tACE_max))
OR (read_valid AND read_active);
D <= read_data WHEN read_valid and read_active ELSE
undef_vec WHEN not read_valid and read_active ELSE
tristate_vec;
PROCESS (nWE, nCE, CE2)
BEGIN
IF ((nCE = '1') OR (nWE = '1') OR (CE2 = '0'))
AND (nCE'DELAYED = '0') AND (CE2'DELAYED = '1') AND (nWE'DELAYED = '0') -- End of Write
THEN
do_write <= '1' AFTER tHD_min;
ELSE
IF (Now > 10 NS) AND (nCE = '0') AND (CE2 = '1') AND (nWE = '0') -- Start of Write
THEN
ASSERT Check_For_Valid_Data(A)
REPORT "Address not valid at start-of-write to RAM."
SEVERITY FAILURE;
ASSERT A'STABLE(tSA_min)
REPORT "tSA violation: Address changed within setup-time at start-of-write to SRAM."
SEVERITY ERROR;
ASSERT enable_nWE_only_control OR ((nOE = '1') AND nOE'STABLE(tSA_min))
REPORT "tSA violation: nOE not inactive at start-of-write to RAM."
SEVERITY ERROR;
END IF;
do_write <= '0';
END IF;
END PROCESS;
-- The following processes check for validity of the control signals at the
-- SRAM interface. Removing them to speed up simulation will not affect the
-- functionality of the SRAM model.
PROCESS (A) -- Checks that an address change is allowed
BEGIN
IF (Now > 0 NS) THEN -- suppress obsolete error message at time 0
ASSERT (nCE = '1') OR (CE2 = '0') OR (nWE = '1')
REPORT "Address not stable while write-to-SRAM active"
SEVERITY FAILURE;
ASSERT (nCE = '1') OR (CE2 = '0') OR (nWE = '1')
OR (nCE'DELAYED(tHA_min) = '1') OR (CE2'DELAYED(tHA_min) = '0')
OR (nWE'DELAYED(tHA_min) = '1')
REPORT "tHA violation: Address changed within hold-time at end-of-write to SRAM."
SEVERITY FAILURE;
END IF;
END PROCESS;
PROCESS (nOE, nWE, nCE, CE2) -- Checks that control signals at RAM are valid all the time
BEGIN
IF (Now > 0 NS) AND (nCE /= '1') AND (CE2 /= '0') THEN
IF (nCE = '0') AND (CE2 = '1') THEN
ASSERT (nWE = '0') OR (nWE = '1')
REPORT "Invalid nWE-signal at SRAM while nCE is active"
SEVERITY WARNING;
ELSE
IF (nCE /= '0') THEN
ASSERT (nOE = '1')
REPORT "Invalid nCE-signal at SRAM while nOE not inactive"
SEVERITY WARNING;
ASSERT (nWE = '1')
REPORT "Invalid nCE-signal at SRAM while nWE not inactive"
SEVERITY ERROR;
END IF;
IF (CE2 /= '1') THEN
ASSERT (nOE = '1')
REPORT "Invalid CE2-signal at SRAM while nOE not inactive"
SEVERITY WARNING;
ASSERT (nWE = '1')
REPORT "Invalid CE2-signal at SRAM while nWE not inactive"
SEVERITY ERROR;
END IF;
END IF;
END IF;
END PROCESS;
END behavior;
| gpl-2.0 | 4a9b2d6dd6d6e787d4f47f26f9869f21 | 0.540896 | 4.036852 | false | false | false | false |
nsauzede/cpu86 | papilio2/ipcore_dir/blk_mem_40K/example_design/blk_mem_40K_prod.vhd | 1 | 10,370 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_40K_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : blk_mem_40K.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 90
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : READ_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 65536
-- C_READ_DEPTH_A : 65536
-- C_ADDRA_WIDTH : 16
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 65536
-- C_READ_DEPTH_B : 65536
-- C_ADDRB_WIDTH : 16
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_40K_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END blk_mem_40K_prod;
ARCHITECTURE xilinx OF blk_mem_40K_prod IS
COMPONENT blk_mem_40K_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_40K_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| gpl-2.0 | 429212df6f8529f82ee7b1aa594a339e | 0.480521 | 3.795754 | false | false | false | false |
willprice/vhdl-computer | src/rtl/mux_4to1.vhd | 1 | 1,195 | ------------------------------------------------------------------------------
-- @file mux_4to1.vhd
-- @brief Simple implementation of a generic 4 to 1 multiplexer that can be
-- easily scaled using the port generics.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity mux_4to1 is
generic (
PORT_WIDTH : in natural := 1
);
port(
in_0 : in std_logic_vector(PORT_WIDTH - 1 downto 0);
in_1 : in std_logic_vector(PORT_WIDTH - 1 downto 0);
in_2 : in std_logic_vector(PORT_WIDTH - 1 downto 0);
in_3 : in std_logic_vector(PORT_WIDTH - 1 downto 0);
sel : in std_logic_vector(1 downto 0);
out_sig: out std_logic_vector(PORT_WIDTH - 1 downto 0)
);
end entity mux_4to1;
architecture rtl of mux_4to1 is
begin
assign_output : process (sel, in_0, in_1, in_2, in_3)
begin
case sel is
when "00" => out_sig <= in_0;
when "01" => out_sig <= in_1;
when "10" => out_sig <= in_2;
when "11" => out_sig <= in_3;
when others => out_sig <= in_0;
end case;
end process;
end architecture rtl; | gpl-3.0 | 0c943b2390d283cc87299f21cdd43f11 | 0.504603 | 3.473837 | false | false | false | false |
mithro/vhdl-triple-buffer | hdl/triple_buffer_arbiter_tb.vhd | 1 | 8,306 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:39:58 07/06/2014
-- Design Name:
-- Module Name: /home/tansell/foss/buffer/hdl/triple_buffer_arbiter_tb.vhd
-- Project Name: buffer
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: triple_buffer_arbiter
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY triple_buffer_arbiter_tb IS
END triple_buffer_arbiter_tb;
ARCHITECTURE behavior OF triple_buffer_arbiter_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT triple_buffer_arbiter
generic (
offset : integer;
size : integer;
addr : integer := 32);
PORT(
input_clk : IN std_logic;
output_clk : IN std_logic;
input_addr : OUT unsigned(7 downto 0);
output_addr : OUT unsigned(7 downto 0);
rst : IN std_logic);
END COMPONENT;
--Inputs
signal input_clk : std_logic := '0';
signal output_clk : std_logic := '0';
signal rst : std_logic := '0';
signal evt : std_logic := '0';
--Outputs
signal input_addr : unsigned(7 downto 0);
signal expected_input_addr : unsigned(7 downto 0);
signal output_addr : unsigned(7 downto 0);
signal expected_output_addr : unsigned(7 downto 0);
-- Clock period definitions
constant addr_delay : time := 5 ns;
constant buffer0_addr : unsigned(7 downto 0) := to_unsigned(100, 8);
constant buffer1_addr : unsigned(7 downto 0) := to_unsigned(120, 8);
constant buffer2_addr : unsigned(7 downto 0) := to_unsigned(140, 8);
BEGIN
evt <= rst or input_clk or output_clk;
-- Instantiate the Unit Under Test (UUT)
uut: triple_buffer_arbiter
GENERIC MAP (
offset => 100,
size => 20,
addr => 8)
PORT MAP (
input_clk => input_clk,
output_clk => output_clk,
input_addr => input_addr,
output_addr => output_addr,
rst => rst);
-- Stimulus process
stim_proc: process
procedure Reset is
begin
wait for 35 ns;
expected_input_addr <= "UUUUUUUU";
expected_output_addr <= "UUUUUUUU";
rst <= '1';
wait for 1 ns;
rst <= '0';
wait for 35 ns;
end procedure;
procedure ExpectedInputAddr(
constant expected_value : unsigned(7 downto 0)) is
begin
wait for 5 ns;
input_clk <= '1';
wait for addr_delay;
expected_input_addr <= expected_value;
end procedure;
procedure ExpectedInputClear is
begin
wait for 5 ns;
input_clk <= '0';
expected_input_addr <= "UUUUUUUU";
end procedure;
procedure ExpectedOutputAddr(
constant expected_value : unsigned(7 downto 0)) is
begin
wait for 5 ns;
output_clk <= '1';
wait for addr_delay;
expected_output_addr <= expected_value;
end procedure;
procedure ExpectedOutputClear is
begin
wait for 5 ns;
output_clk <= '0';
expected_output_addr <= "UUUUUUUU";
end procedure;
begin
Reset;
-- Write starts, should go to buffer0
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
-- Write starts, should go to buffer1
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
-- Write starts, should go to buffer2
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
-- Write starts, should go to buffer0
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
-------------------------------------------------------------------
-- Finished the initial write tests
Reset;
-------------------------------------------------------------------
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
-- Read, should get the last input_addr
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
-- Make sure read keeps getting the same addr
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
-- Advance the input buffer
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
-- Read should have advanced to the next addr
ExpectedOutputAddr(buffer1_addr);
ExpectedOutputClear;
ExpectedOutputAddr(buffer1_addr);
ExpectedOutputClear;
-- Go around the buffer
----
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
--
ExpectedOutputAddr(buffer2_addr);
ExpectedOutputClear;
ExpectedOutputAddr(buffer2_addr);
ExpectedOutputClear;
----
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
--
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
----
Reset;
-- Write starts, should go to buffer0
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
ExpectedInputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedOutputAddr(buffer1_addr);
ExpectedOutputClear;
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedOutputAddr(buffer2_addr);
ExpectedOutputClear;
ExpectedOutputAddr(buffer2_addr);
ExpectedOutputClear;
ExpectedInputClear;
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
-------------------------------------------------------------------
-- Finished the initial read tests
Reset;
-------------------------------------------------------------------
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
-- Start reading from the first buffer, make sure the writer bounced
-- between the two remaining buffers
ExpectedOutputAddr(buffer0_addr);
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
-- Release the reader, should write to buffer0 now
ExpectedOutputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
-- Try again, except reading from buffer2
ExpectedOutputAddr(buffer2_addr);
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedOutputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
--
Reset;
wait;
end process;
END;
| apache-2.0 | f848f6e34c014e6de117e93bd2ce7204 | 0.605466 | 4.994588 | false | false | false | false |
nsauzede/cpu86 | papilio2_drigmorn1/ipcore_dir/clk32to40/simulation/clk32to40_tb.vhd | 2 | 6,322 | -- file: clk32to40_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clk32to40_tb is
end clk32to40_tb;
architecture test of clk32to40_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.25 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component clk32to40_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clk32to40_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
| gpl-2.0 | c1d4fa30c48b643fd3e77e76f4ca6d61 | 0.620531 | 4.220294 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/proc_rtl.vhd | 3 | 199,495 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Version : 1.0a 02/08/2009 Fixed CALL [REG] Instruction --
-- Version : 1.0b 09/07/2014 Fixed dual INTA pulse generation --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
USE work.cpu86instr.ALL;
ENTITY proc IS
PORT(
clk : IN std_logic;
flush_ack : IN std_logic;
instr : IN instruction_type;
inta1 : IN std_logic;
irq_req : IN std_logic;
latcho : IN std_logic;
reset : IN std_logic;
rw_ack : IN std_logic;
status : IN status_out_type;
clrop : OUT std_logic;
decode_state : OUT std_logic;
flush_coming : OUT std_logic;
flush_req : OUT std_logic;
intack : OUT std_logic;
iomem : OUT std_logic;
irq_blocked : OUT std_logic;
opc_req : OUT std_logic;
path : OUT path_in_type;
proc_error : OUT std_logic;
read_req : OUT std_logic;
word : OUT std_logic;
write_req : OUT std_logic;
wrpath : OUT write_in_type
);
END proc ;
architecture rtl of proc is
type state_type is (
Sopcode,Sdecode,
Sreadmem,Swritemem,
Sexecute,Sflush,Shalt);
-- Declare current and next state signals
signal current_state: state_type ;
signal next_state : state_type ;
signal second_pass : std_logic; -- if 1 go round the loop again
signal second_pass_s: std_logic; -- Comb version
signal rep_set_s : std_logic; -- Start of REP Instruction, check CX when set
signal rep_clear_s : std_logic; -- Signal end of REP Instruction
signal rep_flag : std_logic; -- REPEAT Flag
signal rep_z_s : std_logic; -- Z value of REP instruction
signal rep_zl_s : std_logic; -- Latched Z value of REP
signal flush_coming_s : std_logic; -- Signal that a flush is imminent (don't bother filling the queue)
signal irq_blocked_s: std_logic; -- Indicate that IRQ will be blocked during the next instruction
-- This is required for pop segment etc instructions.
signal intack_s : std_logic; -- Signal asserted during 8 bits vector read, this occurs during
-- the second INTA cycle
signal passcnt_s : std_logic_vector(7 downto 0); -- Copy of CL register
signal passcnt : std_logic_vector(7 downto 0);
signal wrpath_s : write_in_type; -- combinatorial
signal wrpathl_s : write_in_type; -- Latched version of wrpath_s
signal path_s : path_in_type; -- combinatorial
signal proc_error_s : std_logic; -- Processor decode error
signal proc_err_s : std_logic; -- Processor decode error latch signal
signal iomem_s : std_logic; -- IO/~M cycle
-- alias ZFLAG : std_logic is status.flag(6); -- doesn't work, why not??
signal flush_req_s : std_logic; -- Flush Prefetch queue request
signal flush_reql_s : std_logic; -- Latched version of Flush request
begin
proc_error <= proc_err_s; -- connect to outside world
flush_req <= flush_req_s;
----------------------------------------------------------------------------
clocked : process(clk,reset)
----------------------------------------------------------------------------
begin
if (reset = '1') then
current_state <= Sopcode;
path <= ((others =>'0'),(others =>'0'),(others =>'0'),(others =>'0'),
(others =>'0'));
wrpathl_s <= ('0','0','0','0','0','0','0');
word <= '0'; -- default to 8 bits
proc_err_s <= '0'; -- Processor decode error
iomem <= '0'; -- default to memory access
second_pass <= '0'; -- default 1 pass
flush_reql_s<= '0'; -- flush prefetch queue
passcnt <= X"01"; -- Copy of CL register used in rot/shft
rep_flag <= '0'; -- REP instruction running flag
rep_zl_s <= '0'; -- REP latched z bit
flush_coming<= '0'; -- flush approaching
irq_blocked <= '1'; -- IRQ blocking for next instruction
intack <= '0'; -- Second INTA cycle signal
elsif rising_edge(clk) then
current_state<= next_state;
proc_err_s <= proc_error_s or proc_err_s; -- Latch Processor error, cleared by reset only
flush_reql_s <= flush_req_s; -- Latch Flush_request signal
if current_state=Sdecode then -- Latch write pulse and path settings
second_pass <= second_pass_s; -- latch pass signal
word <= path_s.datareg_input(3); -- word <= w bit
path <= path_s;
wrpathl_s <= wrpath_s;
passcnt <= passcnt_s;
irq_blocked <=irq_blocked_s; -- Signal to block IRQ during next instruction
intack <= intack_s; -- Second INTA cycle signal
end if;
if ((current_state=Sdecode) or (current_state=Sexecute)) then--Latch IOMEM signal
iomem <= iomem_s; -- Latch IOM signal
flush_coming<=flush_coming_s; -- flush approaching
end if;
if rep_set_s='1' then -- Set/Reset REP flag
rep_flag <= '1';
elsif rep_clear_s='1' then
rep_flag <= '0';
end if;
if rep_set_s='1' then
rep_zl_s <= rep_z_s; -- Latch Z value of REP instruction
end if;
end if;
end process clocked;
----------------------------------------------------------------------------
nextstate : process (current_state, latcho, rw_ack, flush_ack, instr, status,wrpathl_s, second_pass,irq_req,
passcnt, flush_reql_s, rep_flag, rep_zl_s, inta1)
----------------------------------------------------------------------------
begin
-- Default Assignment
opc_req <= '0';
read_req <= '0';
write_req <= '0';
wrpath_s <= ('0','0','0','0','0','0','0'); -- Default all writes disabled
wrpath <= ('0','0','0','0','0','0','0'); -- Combinatorial
path_s <= ((others =>'0'),(others =>'0'),(others =>'0'),(others =>'0'),
(others =>'0'));
proc_error_s<= '0';
iomem_s <= '0'; -- IO/~M default to memory access
flush_req_s <= '0'; -- Flush Prefetch queue request
passcnt_s <= X"01"; -- init to 1
rep_set_s <= '0'; -- default no repeat
rep_clear_s <= '0'; -- default no clear
rep_z_s <= '0'; -- REP instruction Z bit
flush_coming_s<='0'; -- don't fill the instruction queue
irq_blocked_s<='0'; -- default, no block IRQ
clrop <= '0'; -- Clear Segment override flag
second_pass_s<='0'; -- HT0912,
intack_s <= '0'; -- Signal asserted during INT second INTA cycle
decode_state<= '0'; -- Decode stage for signal spy only
case current_state is
----------------------------------------------------------------------------
-- Get Opcode from BIU
----------------------------------------------------------------------------
when Sopcode =>
second_pass_s<='0';
opc_req <= '1';
if (latcho = '0') then
next_state <= Sopcode; -- Wait
else
next_state <= Sdecode; -- Decode instruction
end if;
----------------------------------------------------------------------------
-- Opcode received, decode instruction
-- Set Path (next state)
-- Set wrpath_s, lacthed as this stage, enabled only at Sexecute
----------------------------------------------------------------------------
when Sdecode =>
if second_pass='1' then
wrpath <= wrpathl_s; -- Assert write strobe(s) during first & second pass
else
decode_state <= '1'; -- Asserted during first decode stage
end if;
case instr.ireg is
---------------------------------------------------------------------------------
-- IN Port Instruction 0xE4..E5, 0xEC..ED
-- Use fake xmod and rm setting for fixed port number
---------------------------------------------------------------------------------
when INFIXED0 | INFIXED1 | INDX0 | INDX1 =>
second_pass_s <= '0';
iomem_s <= '1'; -- Select IO cycle
path_s.datareg_input<= MDBUS_IN & instr.ireg(0) & "000"; -- dimux & w & seldreg AX/AL=000
if instr.ireg(3)='0' then -- 0=Fixed, 1=DX
path_s.ea_output <= PORT_00_EA & DONTCARE(2 downto 0);-- dispmux & eamux(4) & segop 11=00:EA
else -- 1=DX
path_s.ea_output <= PORT_00_DX & DONTCARE(2 downto 0);-- dispmux & eamux(4) & segop 10=00:DX
end if;
wrpath_s.wrd <= '1'; -- Write to Data Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sreadmem; -- start read cycle
---------------------------------------------------------------------------------
-- XLAT Instruction
-- AL<= SEG:[BX+AL]
---------------------------------------------------------------------------------
when XLAT =>
second_pass_s <= '0';
path_s.datareg_input<= MDBUS_IN & '0' & REG_AX(2 downto 0); -- dimux & w & seldreg AX/AL=000
path_s.ea_output<= "0001111011"; -- EA=BX+AL, dispmux(2) & eamux(4) & [flag]&segop(2)
wrpath_s.wrd <= '1'; -- Write to Data Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sreadmem; -- start read cycle
---------------------------------------------------------------------------------
-- OUT Port Instruction 0xE6..E7, 0xEE..EF
-- Use fake xmod and rm setting for fixed port number
---------------------------------------------------------------------------------
when OUTFIXED0 | OUTFIXED1 | OUTDX0 | OUTDX1 =>
second_pass_s <= '0';
iomem_s <= '1'; -- Select IO cycle
path_s.datareg_input<= DONTCARE(2 downto 0) & instr.ireg(0) & DONTCARE(2 downto 0); -- dimux & w & seldreg Only need to set W
path_s.alu_operation<= "0000" & DONTCARE(3 downto 0) & ALU_PASSA; -- selalua & selalub & aluopr selalua=AX/AL
path_s.dbus_output <= ALUBUS_OUT; --{eabus(0)&} domux setting
if instr.ireg(3)='0' then -- 0=Fixed, 1=DX
path_s.ea_output <= PORT_00_EA & DONTCARE(2 downto 0);-- dispmux & eamux(4) & segop 11=00:EA
else -- 1=DX
path_s.ea_output <= PORT_00_DX & DONTCARE(2 downto 0);-- dispmux & eamux(4) & segop 10=00:DX
end if;
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Swritemem; -- start write cycle
---------------------------------------------------------------------------------
-- Increment/Decrement Register, word only!
---------------------------------------------------------------------------------
when INCREG0 |INCREG1 |INCREG2 |INCREG3 | INCREG4 |INCREG5 |INCREG6 |INCREG7 |
DECREG0 |DECREG1 |DECREG2 |DECREG3 | DECREG4 |DECREG5 |DECREG6 |DECREG7 =>
second_pass_s <= '0';
path_s.datareg_input<= ALUBUS_IN & '1' & instr.reg; -- dimux & w & seldreg
-- instr.ireg(5..3) contains the required operation, ALU_INBUSB=X"0001"
-- Note ALU_INC is generic for INC/DEC
path_s.alu_operation<= '0'&instr.reg & REG_CONST1 & ALU_INC(6 downto 3)&instr.ireg(5 downto 3); -- selalua & selalub & aluopr
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
wrpath_s.wrd <= '1'; -- Update register
wrpath_s.wrcc <= '1'; -- Update Flag register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
-----------------------------------------------------------------------------
-- Shift/Rotate Instructions
-- Operation define in MODRM REG bits
-- Use MODRM reg bits
-- bit 0=b/w, bit1=0 then count=1 else count=cl
-- if cl=00 then don't write to CC register
-----------------------------------------------------------------------------
when SHFTROT0 | SHFTROT1 | SHFTROT2 | SHFTROT3 =>
if instr.reg="110" then -- Not supported/defined
proc_error_s<='1'; -- Assert Bus Error Signal
-- pragma synthesis_off
assert not (now > 0 ns) report "**** Illegal SHIFT/ROTATE instruction (proc) ***" severity warning;
-- pragma synthesis_on
end if;
if instr.xmod="11" then -- Immediate to Register r/m=reg field
path_s.datareg_input<= ALUBUS_IN & instr.ireg(0) & instr.rm; -- dimux & w & seldreg Note RM=Destination!!
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
if (second_pass='0') then -- first pass, load reg into alureg
if (instr.ireg(1)='1' and status.cl=X"00") then
second_pass_s <= '0'; -- No second pass if cl=0
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute; -- terminate
else
second_pass_s <= '1'; -- need another pass
next_state <= Sdecode; -- round the loop again
end if;
-- Load instr.rm register into ALUREG
path_s.alu_operation<= DONTCARE(3 downto 0) & '0'&instr.rm & ALU_REGL; -- selalua(4) & selalub(4) & aluopr(7)
wrpath_s.wralu <= '1';
if (instr.ireg(1)='1') then
passcnt_s <= status.cl; -- Load CL loop counter
end if; -- else passcnt_s=1;
else -- second pass, terminate or go around the loop again
-- selalua & selalu are dontcare, instruction is V+001+instr.reg
-- ALU_ROL(6 downto 4) is generic for all shift/rotate
-- Instruction=Constant & V_Bit & modrm.reg(5 downto 3)
path_s.alu_operation<= DONTCARE(3 downto 0) & '0'&instr.rm & ALU_ROL(6 downto 4)& instr.ireg(1) & instr.reg; -- selalua(4) & selalub(4) & aluopr(7)
if (passcnt=X"00") then -- Check if end of shift/rotate
second_pass_s <= '0'; -- clear
wrpath_s.wrcc <= '1'; -- Update Status Register after last shift/rot
wrpath_s.wrd <= '1'; -- Write shift/rotate results to Data Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute; -- terminate
else
second_pass_s <= '1'; -- need another pass
wrpath_s.wralu <= '1';
wrpath_s.wrcc <= '1';
passcnt_s <= passcnt - '1';
next_state <= Sdecode; -- round the loop again
end if;
end if;
else -- Destination and source is memory, use ALUREG
path_s.datareg_input<= MDBUS_IN & instr.ireg(0) & DONTCARE(2 downto 0); -- ver 0.69, path& w! seldreg=don'tcare
path_s.dbus_output <= ALUBUS_OUT; -- {eabus(0)&} domux setting
path_s.ea_output <= NB_DS_EA; -- dispmux & eamux & segop
if (second_pass='0') then -- first pass, load memory operand into alureg
if (instr.ireg(1)='1' and status.cl=X"00") then
second_pass_s <= '0'; -- No second pass if cl=0
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute; -- terminate
else
second_pass_s <= '1'; -- need another pass
next_state <= Sreadmem; -- start read cycle
end if;
-- Load memory into ALUREG
path_s.alu_operation<= DONTCARE(3 downto 0) & REG_MDBUS & ALU_REGL; -- selalua(4) & selalub(4) & aluopr(7)
wrpath_s.wralu <= '1'; -- ver 0.69, write MDBUS to ALUREG
if (instr.ireg(1)='1') then
passcnt_s <= status.cl; -- Load CL loop counter
end if; -- else passcnt_s=1;
else -- second pass, MDBUS contains memory byte
-- selalua & selalu are dontcare
-- ALU_ROL(6 downto 4) is generic for all shift/rotate
path_s.alu_operation<= DONTCARE(3 downto 0) & '0'&instr.rm & ALU_ROL(6 downto 4)& instr.ireg(1) & instr.reg; -- selalua(4) & selalub(4) & aluopr(7)
wrpath_s.wrcc <= '1'; -- Update Status Register after each shift/rot
--if (passcnt=X"01") then -- Check if end of shift/rotate
if (passcnt=X"00") then -- ver 0.69, Check if end of shift/rotate
second_pass_s <= '0'; -- clear
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Swritemem; -- write result to memory & terminate
else
passcnt_s <= passcnt - '1';
second_pass_s <= '1';
wrpath_s.wralu<= '1'; -- Update ALUREG
next_state <= Sdecode; -- round the loop again
end if;
end if;
end if;
---------------------------------------------------------------------------------
-- Immediate to Register
---------------------------------------------------------------------------------
when MOVI2R0 | MOVI2R1 |MOVI2R2 |MOVI2R3 |MOVI2R4 | MOVI2R5 | MOVI2R6 | MOVI2R7 |
MOVI2R8 | MOVI2R9 |MOVI2R10|MOVI2R11|MOVI2R12| MOVI2R13| MOVI2R14| MOVI2R15 =>
second_pass_s <= '0';
path_s.datareg_input<= DATAIN_IN & instr.ireg(3) & instr.reg; -- dimux & w & seldreg
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
wrpath_s.wrd <= '1'; -- Write to Data Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
---------------------------------------------------------------------------------
-- Immediate to Register/Memory 0xC6, 0xC7
-- Data is routed from drmux->dibus->dbusdp_out
---------------------------------------------------------------------------------
when MOVI2RM0 | MOVI2RM1 =>
second_pass_s <= '0';
path_s.datareg_input<= DATAIN_IN & instr.ireg(0) & DONTCARE(2 downto 0); -- dimux & w & seldreg (only dimux, the rest is don't care)
-- change to instr.ireg(0) & instr.reg ???
path_s.dbus_output <= DIBUS_OUT; --{eabus(0)&} domux setting
path_s.ea_output <= NB_DS_EA; -- dispmux & eamux & segop (unless Segment OP flag is set)
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Swritemem; -- start write cycle
---------------------------------------------------------------------------------
-- Memory to Accu and Accu to Memory AL, AX, not AH! 0xA0..0xA3
-- Use fake xmod and rm setting
-- Use instruction but (4..3)=000 as register selector
---------------------------------------------------------------------------------
when MOVM2A0 | MOVM2A1 | MOVA2M0 | MOVA2M1 =>
second_pass_s <= '0';
path_s.datareg_input<= MDBUS_IN & instr.ireg(0) & instr.reg; -- dimux & w & seldreg (don't care for write cycle)
path_s.alu_operation<= '0'&instr.reg & DONTCARE(3 downto 0) & ALU_PASSA; -- selalua & selalub & aluopr (don't care for read cycle)
path_s.dbus_output <= ALUBUS_OUT; --{eabus(0)&} domux setting (don't care for read cycle)
path_s.ea_output <= NB_DS_EA; -- dispmux & eamux & segop (unless Segment OP flag is set)
if instr.ireg(1)='0' then -- 0= memory to Accu, Read Cycle
wrpath_s.wrd <= '1'; -- Write Memory to Data Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sreadmem; -- start read cycle
else -- 1=Accu to Memory, Write cycle
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Swritemem; -- start write cycle
end if;
---------------------------------------------------------------------------------
-- Move Register/Memory to/from Register 0x88..0x8B
---------------------------------------------------------------------------------
when MOVRM2R0 | MOVRM2R1 | MOVRM2R2 | MOVRM2R3 =>
second_pass_s <= '0';
if instr.xmod="11" then -- Register to Register rm=reg field
if instr.ireg(1)='0' then -- Check 'd' bit, 0-> SRC=Reg, DEST=rm
path_s.datareg_input<= ALUBUS_IN & instr.ireg(0) & instr.rm; -- dimux & w & seldreg
path_s.alu_operation<= '0'&instr.reg & DONTCARE(3 downto 0) & ALU_PASSA; -- selalua & selalub & aluopr
else -- 'd'=1 SRC=rm, DEST=Reg
path_s.datareg_input<= ALUBUS_IN & instr.ireg(0) & instr.reg; -- dimux & w & seldreg
path_s.alu_operation<= '0'&instr.rm & DONTCARE(3 downto 0) & ALU_PASSA; -- selalua & selalub & aluopr
end if;
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
wrpath_s.wrd <= '1'; -- Write Data Register to Data Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
else -- Source is memory
if instr.ireg(1)='0' then -- Check 'd' bit, 0-> SRC=Reg, DEST=rm, Write Cycle
path_s.alu_operation<= '0'&instr.reg & DONTCARE(3 downto 0) & ALU_PASSA; -- selalua & selalub & aluopr
path_s.dbus_output <= ALUBUS_OUT; --{eabus(0)&} domux setting
path_s.datareg_input<= DONTCARE(2 downto 0) & instr.ireg(0) & DONTCARE(2 downto 0); -- dimux & w & seldreg
-- (only need w, the reset don't care)
path_s.ea_output <= NB_DS_EA; -- dispmux & eamux & segop (unless Segment OP flag is set)
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Swritemem; -- start write cycle
else -- 'd'=1 SRC=rm, DEST=Reg, Read Cycle
path_s.datareg_input<= MDBUS_IN & instr.ireg(0) & instr.reg; -- dimux & w & seldreg
path_s.alu_operation<= '0'&instr.rm & DONTCARE(3 downto 0) & ALU_PASSA; -- selalua & selalub & aluopr
path_s.ea_output <= NB_DS_EA; -- dispmux & eamux & segop (unless Segment OP flag is set)
wrpath_s.wrd <= '1'; -- Write Memory to Data Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sreadmem; -- start read cycle
end if;
end if;
---------------------------------------------------------------------------------
-- Move Segment register to data register or memory
---------------------------------------------------------------------------------
when MOVS2RM =>
second_pass_s <= '0';
if instr.xmod="11" then -- Segment Register to Data Register , rm=reg field
path_s.datareg_input<= '1'& instr.reg(1 downto 0) & '1' & instr.rm; -- dimux & w & seldreg
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
wrpath_s.wrd <= '1'; -- Write Seg to Data Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
else -- Segment Register to memory indexed by rm
path_s.datareg_input<= '1'& instr.reg(1 downto 0) & '1' & DONTCARE(2 downto 0); -- dimux only -- [dimux(3) & w & seldreg(3)]
path_s.dbus_output <= DIBUS_OUT; --(Odd/Even) domux setting
path_s.ea_output <= NB_DS_EA; -- dispmux & eamux & segop (unless Segment OP flag is set)
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Swritemem; -- start write cycle
end if;
---------------------------------------------------------------------------------
-- Register or Memory to Segment Register
-- In case of memory, stalls until operand is read from memory
---------------------------------------------------------------------------------
when MOVRM2S =>
irq_blocked_s <= '1'; -- Block IRQ if asserted during next instr.
second_pass_s <= '0';
if instr.reg(1 downto 0)="01" then
proc_error_s<='1'; -- if segment register = CS report error
-- pragma synthesis_off
report "MOVRM2S : MOV CS,REG/Memory not valid" severity warning;
-- pragma synthesis_on
end if;
path_s.datareg_input<= DONTCARE(2 downto 0)& '1' & DONTCARE(2 downto 0); -- dimux & w=1 & seldreg
if instr.xmod="11" then -- Register to Segment Register , rm=reg field
path_s.alu_operation<= '0'&instr.rm & DONTCARE(3 downto 0) & ALU_PASSA; --selalua & selalub & aluopr
path_s.segreg_input <= SALUBUS_IN & instr.reg(1 downto 0); -- simux & selsreg
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
wrpath_s.wrs <= '1'; -- Write Data Register to Segment Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
else -- Memory to Segment Register
path_s.segreg_input <= SMDBUS_IN & instr.reg(1 downto 0); -- simux & selsreg
path_s.ea_output <= NB_DS_EA; -- dispmux & eamux & segop (unless Segment OP flag is set)
wrpath_s.wrs <= '1'; -- Write Memory to Segment Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sreadmem; -- start read cycle
end if;
---------------------------------------------------------------------------------
-- Load Effective Address in Data Register
-- mod=11 result in proc_error
---------------------------------------------------------------------------------
when LEA =>
second_pass_s <= '0';
if instr.xmod="11" then -- Register to Register rm=reg field
proc_error_s<='1'; -- Assert Bus Error Signal
-- pragma synthesis_off
assert not (now > 0 ns) report "**** Illegal LEA operand (mod=11) (proc) ***" severity warning;
-- pragma synthesis_on
end if; -- Transfer Effective addresss (EABUS) to data register
path_s.datareg_input<= EABUS_IN & '1' & instr.reg; -- dimux & w & seldreg
path_s.ea_output <= NB_DS_EA; -- dispmux & eamux & segop
wrpath_s.wrd <= '1'; -- Write EABUS to Data Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
---------------------------------------------------------------------------------
-- Load Effective Address in ES/DS:DEST_REGISTER
-- mod=11 result in proc_error
-- TEMP <= readmem(ea) ; PASS1 (required for cases like LES SI,[SI] )
-- REG <= TEMP ; PASS2
-- ES/DS<= readmem(ea+2)
---------------------------------------------------------------------------------
when LES | LDS =>
if instr.xmod="11" then -- Register to Register rm=reg field
proc_error_s<='1'; -- Assert Bus Error Signal
-- pragma synthesis_off
assert not (now > 0 ns) report "**** Illegal LES/LDS operand (mod=11) (proc) ***" severity warning;
-- pragma synthesis_on
end if;
path_s.alu_operation<= DONTCARE(3 downto 0) & REG_MDBUS & ALU_TEMP;-- selalua(4) & selalub(4) & aluopr
if (second_pass='0') then -- first pass reg<=mem(ea)
second_pass_s <= '1'; -- need another pass
path_s.datareg_input<= MDBUS_IN & '1' & instr.reg;-- dimux & w & seldreg
path_s.ea_output<="0000001001"; -- dispmux(3) & eamux(4)=EA & dis_opflag & segop[1:0]
wrpath_s.wrtemp <= '1'; -- Write reg value to alu_temp first
next_state <= Sreadmem; -- start read to read temp<=EA
else
second_pass_s <= '0'; -- clear
path_s.datareg_input<= ALUBUS_IN & '1' & instr.reg;-- dimux & w & seldreg
path_s.ea_output<="0000011001"; -- dispmux(3) & eamux(4)=EA+2 & dis_opflag & segop[1:0]
-- Second Pass ES/DS<=mem(ea+2)
if instr.ireg(0)='0' then -- C4=LES
path_s.segreg_input <= SMDBUS_IN & ES_IN(1 downto 0); -- simux & selsreg=ES
else -- C5=LDS
path_s.segreg_input <= SMDBUS_IN & DS_IN(1 downto 0); -- simux & selsreg=DS
end if;
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
wrpath_s.wrd <= '1'; -- Update Reg<=temp
wrpath_s.wrs <= '1'; -- Update ES/DS Register
next_state <= Sreadmem;
end if;
---------------------------------------------------------------------------------
-- Convert AL to AX, AX -> DX:AX
-- Flags are not affected
---------------------------------------------------------------------------------
when CBW | CWD =>
second_pass_s <= '0';
-- Note ALU_SEXT(6 downto 4) is generic for CBW and CWD
path_s.alu_operation<= REG_AX & DONTCARE(3 downto 0) & ALU_SEXT(6 downto 4) & instr.ireg(3 downto 0) ;-- selalua & selalub & aluopr
if (instr.ireg(0)='0') then -- if 0 then CBW else CWD
path_s.datareg_input<= ALUBUS_IN & '1' & REG_AX(2 downto 0);-- dimux & w & seldreg Note RM=Destination!!
else
path_s.datareg_input<= ALUBUS_IN & '1' & REG_DX(2 downto 0);-- dimux & w & seldreg Note RM=Destination!!
end if;
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
wrpath_s.wrd <= '1'; -- Write Data Register to Data Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
---------------------------------------------------------------------------------
-- Convert AL
-- Use bit 4 of instruction to drive W bit
---------------------------------------------------------------------------------
when AAS | DAS | AAA | DAA | AAM | AAD =>
passcnt_s <= passcnt - '1';
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
path_s.datareg_input<= ALUBUS_IN & instr.ireg(4) & REG_AX(2 downto 0);-- dimux & w & seldreg Note RM=Destination!!
path_s.alu_operation<= REG_AX & DONTCARE(3 downto 0) & ALU_DAA(6 downto 4)&instr.ireg(0)&instr.ireg(5 downto 3);-- selalua & selalub & aluopr
if (second_pass='0') then -- first pass
if (instr.ireg=AAM) then -- AAM instruction only
second_pass_s <= '1'; -- need another pass
wrpath_s.wralu <= '1'; -- Write Data to ALUREG, only used for AAM (uses divider)
passcnt_s <= "000"&DIV_MCD_C; -- Serial delay
next_state <= Sdecode; -- round the loop again
else
second_pass_s <= '0';
wrpath_s.wrcc <= '1'; -- Update Status Register
wrpath_s.wrd <= '1'; -- Write Data Register to Data Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute; -- terminate
end if;
else
second_pass_s <= '1';
if (passcnt=X"00") then -- Divider Done?
second_pass_s <= '0';
wrpath_s.wrcc <= '1'; -- Update Status Register
wrpath_s.wrd <= '1'; -- Write Data Register to Data Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute; -- terminate
else
next_state <= Sdecode; -- Version 0.78
end if;
end if;
---------------------------------------------------------------------------------
-- Segment Override Prefix
---------------------------------------------------------------------------------
when SEGOPES | SEGOPCS | SEGOPSS | SEGOPDS =>
irq_blocked_s <= '1'; -- Block IRQ if asserted during next instr.
second_pass_s <= '0';
path_s.datareg_input<= DONTCARE(2 downto 0) & instr.ireg(0) & DONTCARE(2 downto 0); -- dimux & w & seldreg
path_s.ea_output <= "000"&DONTCARE(3 downto 0) & '0' & instr.ireg(4 downto 3); -- dispmux & eamux(4) & [flag]&segop[1:0]
wrpath_s.wrop <= '1'; -- Write to Override Prefix Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
---------------------------------------------------------------------------------
-- Halt Instruction, wait for NMI, INTR, Reset
---------------------------------------------------------------------------------
when HLT =>
second_pass_s <= '0';
path_s.ea_output<= NB_CS_IP;
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
---------------------------------------------------------------------------------
-- ADD/ADC/SUB/SBB/CMP/AND/OR/XOR Register/Memory <- Register/Memory
-- TEST same as AND without returning any result (wrpath_s.wrd is not asserted)
---------------------------------------------------------------------------------
when ADDRM2R0 | ADDRM2R1 | ADDRM2R2 | ADDRM2R3 | ADCRM2R0 | ADCRM2R1 | ADCRM2R2 | ADCRM2R3 |
SUBRM2R0 | SUBRM2R1 | SUBRM2R2 | SUBRM2R3 | SBBRM2R0 | SBBRM2R1 | SBBRM2R2 | SBBRM2R3 |
CMPRM2R0 | CMPRM2R1 | CMPRM2R2 | CMPRM2R3 | ANDRM2R0 | ANDRM2R1 | ANDRM2R2 | ANDRM2R3 |
ORRM2R0 | ORRM2R1 | ORRM2R2 | ORRM2R3 | XORRM2R0 | XORRM2R1 | XORRM2R2 | XORRM2R3 |
TESTRMR0 | TESTRMR1 =>
if instr.xmod="11" then -- Register to Register rm=reg field
second_pass_s <= '0';
if (instr.ireg(1)='1') then -- Check 'd' bit, if 1 dest=reg else r/m
path_s.datareg_input<= ALUBUS_IN & instr.ireg(0) & instr.reg; -- dimux & w & seldreg Note REG=Destination!
-- Note aluopr = bit 5 to 3 of opcode
-- Note ALU_ADD(6 downto 4) is generic for all sub types
-- Note the selalua and selalub values are important for the SUB and CMP instructions!
-- It would have been nice if the position was fixed in the opcode!
path_s.alu_operation<= '0'&instr.reg & '0'&instr.rm & ALU_ADD(6 downto 4)&instr.ireg(7)&instr.ireg(5 downto 3);-- selalua & selalub & aluopr
else
path_s.datareg_input<= ALUBUS_IN & instr.ireg(0) & instr.rm; -- dimux & w & seldreg Note RM=Destination!
path_s.alu_operation<= '0'&instr.rm & '0'&instr.reg & ALU_ADD(6 downto 4)&instr.ireg(7)&instr.ireg(5 downto 3);-- selalua & selalub & aluopr
end if;
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
if ((instr.ireg(5 downto 3)/="111") and (instr.ireg(7)='0')) then -- Check if not CMP or TEST Instruction
wrpath_s.wrd <= '1'; -- Write Data Register to Data Register
end if;
wrpath_s.wrcc <= '1'; -- Update Status Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
else -- Source/dest is memory
if instr.ireg(1)='0' then -- Check 'd' bit ->0 SRC=Reg, DEST=rm, Read & Write Cycle (mem<- mem, reg, AND)
path_s.datareg_input<= DONTCARE(2 downto 0) & instr.ireg(0) & DONTCARE(2 downto 0); -- dimux & w & seldreg (only w)
path_s.alu_operation<= REG_MDBUS & '0'&instr.reg & ALU_ADD(6 downto 4)&instr.ireg(7)&instr.ireg(5 downto 3); -- selalua & selalub & aluopr Path for ALU
path_s.dbus_output <= ALUBUS_OUT; --{eabus(0)&} domux setting
path_s.ea_output <= NB_DS_EA; -- dispmux & eamux & segop (unless Segment OP flag is set)
if (second_pass='0') then -- first pass read operand
second_pass_s <= '1'; -- need another pass
next_state <= Sreadmem; -- start read cycle
else
second_pass_s <= '0'; -- clear
wrpath_s.wrcc <= '1'; -- Update Status Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
if ((instr.ireg(5 downto 3)/="111") and (instr.ireg(7)='0')) then-- Check if not CMP or TEST Instruction
next_state <= Swritemem; -- start write cycle
else
next_state <= Sexecute;
end if;
end if;
else -- 'd'=1 SRC=rm, DEST=Reg, Read Cycle (reg<- reg, mem, AND)
second_pass_s <= '0';
-- Select Data for result path
path_s.datareg_input<= ALUBUS_IN & instr.ireg(0) & instr.reg; -- dimux & w & seldreg
-- Select Path for ALU
path_s.alu_operation<= '0'&instr.reg & REG_MDBUS & ALU_ADD(6 downto 4)&instr.ireg(7)&instr.ireg(5 downto 3);-- selalua & selalub & aluopr
path_s.ea_output <= NB_DS_EA; -- dispmux & eamux & segop (unless Segment OP flag is set)
if ((instr.ireg(5 downto 3)/="111") and (instr.ireg(7)='0')) then-- Check if not CMP or TEST Instruction
wrpath_s.wrd <= '1'; -- Write Data Register to Data Register
end if;
wrpath_s.wrcc <= '1'; -- Update Status Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sreadmem; -- start read cycle
end if;
end if;
---------------------------------------------------------------------------------
-- OPCODE 80,81,82,83, ADD/ADC/SUB/SBB/CMP/AND/OR/XOR Immediate to Reg/Mem
-- ALU operation is defined in reg field (3 bits) and not in bit 5-3 of opcode
-- Data is routed from drmux->dibus->dbusdp_out
-- If instr(1)=1 then signextend the data byte (SW=11)
---------------------------------------------------------------------------------
when O80I2RM | O81I2RM | O83I2RM =>
if instr.xmod="11" then -- Immediate to Register r/m=reg field
second_pass_s <= '0';
path_s.datareg_input<= ALUBUS_IN & instr.ireg(0) & instr.rm; -- dimux & w & seldreg Note RM=Destination!!
-- instr.reg contains the required operation (Reg AND Constant)
-- If s-bit=0 then 000+REG else 110+REG, s-bit is bit 1 of instr.reg
path_s.alu_operation<= '0'&instr.rm & REG_DATAIN &instr.ireg(1)&instr.ireg(1)&"00"&instr.reg; -- selalua & selalub & aluopr
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
if (instr.reg/="111") then -- Check if not CMP Instruction
wrpath_s.wrd <= '1'; -- Write Data Register to Data Register
end if;
wrpath_s.wrcc <= '1'; -- Update Status Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
else -- Destination and source is memory (no wrpath_s.wrd)
-- This is nearly the same as AND with d=0, see above
-- only need W bit
path_s.datareg_input<= DONTCARE(2 downto 0) & instr.ireg(0) & DONTCARE(2 downto 0); -- dimux & w & seldreg (only dimux, the rest is don't care)
-- Memory AND Constant, need to read memory first
path_s.alu_operation<= REG_MDBUS & REG_DATAIN&instr.ireg(1)&instr.ireg(1)&"00"&instr.reg; -- selalua & selalub & aluopr
path_s.dbus_output <= ALUBUS_OUT; --{eabus(0)&} domux setting
path_s.ea_output <= NB_DS_EA; -- dispmux & eamux & segop (unless Segment OP flag is set)
if (second_pass='0') then -- first pass read operand
second_pass_s <= '1'; -- need another pass
next_state <= Sreadmem; -- start read cycle
else
second_pass_s <= '0'; -- clear
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
wrpath_s.wrcc <= '1'; -- Update Status Register
if (instr.reg/="111") then -- Check if not CMP Instruction
next_state <= Swritemem; -- start write cycle
else
next_state <= Sexecute; -- CMP, do not write results
end if;
end if;
end if;
-----------------------------------------------------------------------------
-- NOT/TEST F6/F7 Shared Instructions
-- TEST regfield=000
-- NOT regfield=010
-- NEG regfield=011
-- MUL regfield=100
-- IMUL regfield=101
-- DIV regfield=110
-- IDIV regfield=111
-- ALU operation is defined in bits 5-3 of modrm.reg
-- Same sequence as OPC80..83 instruction?
-- Note for NOT instruction DATAIN must be zero!!
-----------------------------------------------------------------------------
when F6INSTR | F7INSTR =>
-- case instr.reg(2 downto 0) is
case instr.reg is
when "000" => -- TEST instruction, Combine with NEG/NOT Instruction ?????????????
if instr.xmod="11" then -- Immediate to Register r/m=reg field
second_pass_s <= '0';
path_s.datareg_input<= ALUBUS_IN & instr.ireg(0) & instr.rm; -- dimux & w & seldreg
-- instr.reg contains the required operation
-- Note ALU_TEST2 is generic for all sub types
path_s.alu_operation<= '0'&instr.rm & REG_DATAIN & ALU_TEST2(6 downto 3)&instr.reg; -- selalua & selalub & aluopr
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
wrpath_s.wrcc <= '1'; -- Update Status Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
else -- Destination and source is memory (no wrpath_s.wrd)
-- This is nearly the same as AND with d=0, see above
-- only need W bit
path_s.datareg_input<= DONTCARE(2 downto 0) & instr.ireg(0) & DONTCARE(2 downto 0); -- dimux & w & seldreg (only dimux, the rest is don't care)
-- Memory AND Constant, need to read memory first
path_s.alu_operation<= REG_MDBUS & REG_DATAIN & ALU_TEST2(6 downto 3)&instr.reg; -- selalua & selalub & aluopr
path_s.dbus_output <= ALUBUS_OUT; --{eabus(0)&} domux setting
path_s.ea_output <= NB_DS_EA; -- dispmux & eamux & segop (unless Segment OP flag is set)
if (second_pass='0') then -- first pass read operand
second_pass_s <= '1'; -- need another pass
next_state <= Sreadmem; -- start read cycle
else
second_pass_s <= '0'; -- clear
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
wrpath_s.wrcc <= '1'; -- Update Status Register
next_state <= Sexecute; -- TEST, do not write results
end if;
end if;
when "010" | "011" => -- Invert NOT and 2s complement NEG
-- Check with others to see if can be combined!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
if instr.xmod="11" then -- Negate Register r/m=reg field
second_pass_s <= '0';
path_s.datareg_input<= ALUBUS_IN & instr.ireg(0) & instr.rm; -- dimux & w & seldreg
-- Note ALU_TEST2 is generic for all sub types
if (instr.reg(0)='1') then -- NEG instruction
path_s.alu_operation<= '0'&instr.rm & REG_CONST1 & ALU_TEST2(6 downto 3)&instr.reg; -- selalua & selalub & aluopr
else -- NOT instruction, note DATAIN must be zero!
path_s.alu_operation<= '0'&instr.rm & REG_DATAIN & ALU_TEST2(6 downto 3)&instr.reg; -- selalua & selalub & aluopr
end if;
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
if (instr.reg(0)='1') then -- NEG instruction
wrpath_s.wrcc <= '1'; -- Update Status Register
end if;
wrpath_s.wrd <= '1'; -- Write Data Register to Data Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
else -- Destination and source is memory
-- only need W bit
path_s.datareg_input<= DONTCARE(2 downto 0) & instr.ireg(0) & DONTCARE(2 downto 0); -- dimux & w & seldreg (only dimux, the rest is don't care)
-- need to read memory first
if (instr.reg(0)='1') then -- NEG instruction
path_s.alu_operation<= REG_MDBUS & REG_CONST1 & ALU_TEST2(6 downto 3)&instr.reg; -- selalua & selalub & aluopr
else -- NOT instruction, note DATAIN must be zero!
path_s.alu_operation<= REG_MDBUS & REG_DATAIN & ALU_TEST2(6 downto 3)&instr.reg; -- selalua & selalub & aluopr
end if;
path_s.dbus_output <= ALUBUS_OUT; --{eabus(0)&} domux setting
path_s.ea_output <= NB_DS_EA; -- dispmux & eamux & segop (unless Segment OP flag is set)
if (second_pass='0') then -- first pass read operand
second_pass_s <= '1'; -- need another pass
next_state <= Sreadmem; -- start read cycle
else
second_pass_s <= '0'; -- clear
if (instr.reg(0)='1') then -- NEG instruction
wrpath_s.wrcc <= '1'; -- Update Status Register
end if;
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Swritemem; -- write results
end if;
end if;
when "100" | "101" | "110" | "111" => -- DIV/IDIV/MUL/IMUL instruction
if (second_pass='0') then -- Set up multiply parameters
second_pass_s <= '1';
if (instr.reg(1)='1') then -- Only assert for DIV and IDIV, not for MUL/IMUL
passcnt_s <= "000"&DIV_MCD_C; -- Serial delay
else
passcnt_s <= "000"&MUL_MCD_C; -- Multiplier MCP
end if;
-- only need W bit
path_s.datareg_input<= DONTCARE(2 downto 0) & instr.ireg(0) & DONTCARE(2 downto 0); -- dimux & w & seldreg
-- Note ALU_TEST is generic for all sub types
if instr.xmod="11" then -- Immediate to Register, result to AX or DX:AX
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
path_s.alu_operation<= REG_AX & '0'&instr.rm & ALU_TEST2(6 downto 4)&'0'&instr.reg; -- selalua & selalub & aluopr
next_state <= Sdecode; -- Next write remaining AX
else -- get byte/word from memory
path_s.ea_output <= NB_DS_EA;
path_s.alu_operation<= REG_AX & REG_MDBUS & ALU_TEST2(6 downto 4)&'0'&instr.reg; -- selalua & selalub & aluopr
next_state <= Sreadmem; -- Next write remaining AX
end if;
wrpath_s.wralu <= '1'; -- latch AX/AL and Byte/Word
else
passcnt_s <= passcnt - '1';
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP (required???????????)
if (passcnt=X"01") then --
path_s.datareg_input<= ALUBUS_IN & '1' & REG_AX(2 downto 0); -- dimux & w & seldreg
path_s.alu_operation<= REG_AX & '0'&instr.rm & ALU_TEST2(6 downto 4)&'0'&instr.reg; -- selalua & selalub & aluopr
wrpath_s.wrd <= '1'; -- Write AX
if (instr.ireg(0)='1') then
second_pass_s <= '1'; -- HT0912
next_state <= Sdecode; -- Continue, next cycle to write DX
else
second_pass_s <= '0';
wrpath_s.wrcc <= '1'; -- Update Status Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute; -- terminate
end if;
elsif (passcnt=X"00") then
path_s.datareg_input<= ALUBUS_IN & '1' & REG_DX(2 downto 0); -- dimux & w & seldreg
path_s.alu_operation<= REG_AX & '0'&instr.rm & ALU_TEST2(6 downto 4)&'1'&instr.reg; -- selalua & selalub & aluopr
second_pass_s <= '0';
wrpath_s.wrd <= '1'; -- Write DX
wrpath_s.wrcc <= '1'; -- Update Status Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute; -- terminate
else
second_pass_s <= '1'; -- HT0912
path_s.datareg_input<= ALUBUS_IN & '1' & REG_DX(2 downto 0); -- dimux & w & seldreg
path_s.alu_operation<= REG_AX & '0'&instr.rm & ALU_TEST2(6 downto 4)&'1'&instr.reg; -- selalua & selalub & aluopr
next_state <= Sdecode; -- round the loop again
end if;
end if;
when others =>
second_pass_s <= '0'; -- To avoid latch HT0912
proc_error_s <='1'; -- Assert Bus Error Signal
-- pragma synthesis_off
assert not (now > 0 ns) report "**** Illegal F7/F6 modrm field (proc) ***" severity warning;
-- pragma synthesis_on
next_state <= Sdecode; -- Reset State????
end case;
---------------------------------------------------------------------------------
-- ADD/ADC/SUB/SBB/CMP/AND/OR/XOR Immediate to ACCU
-- ALU operation is defined in bits 5-3 of opcode
---------------------------------------------------------------------------------
when ADDI2AX0 | ADDI2AX1 | ADCI2AX0 | ADCI2AX1 | SUBI2AX0 | SUBI2AX1 | SBBI2AX0 | SBBI2AX1 |
CMPI2AX0 | CMPI2AX1 | ANDI2AX0 | ANDI2AX1 | ORI2AX0 | ORI2AX1 | XORI2AX0 | XORI2AX1 |
TESTI2AX0| TESTI2AX1 =>
second_pass_s <= '0';
-- Note Destination reg is fixed to AX/AL/AH
path_s.datareg_input<= ALUBUS_IN & instr.ireg(0) & REG_AX(2 downto 0); -- dimux & w & seldreg(3)
-- note aluopr = bit 5 to 3 of opcode
path_s.alu_operation<= REG_AX & REG_DATAIN & ALU_ADD(6 downto 4)&instr.ireg(7)&instr.ireg(5 downto 3);-- selalua & selalub & aluopr
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
if ((instr.ireg(5 downto 3)/="111") and (instr.ireg(7)='0')) then-- Check if not CMP or TEST Instruction
wrpath_s.wrd <= '1'; -- Write Data Register to Data Register
end if;
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
wrpath_s.wrcc <= '1'; -- Update Status Register
next_state <= Sexecute;
---------------------------------------------------------------------------------
-- Exchange Register with Accu
---------------------------------------------------------------------------------
when XCHGAX | XCHGCX | XCHGDX | XCHGBX | XCHGSP | XCHGBP | XCHGSI | XCHGDI =>
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
if (second_pass='0') then -- first pass read operand
second_pass_s <= '1'; -- need another pass
-- First pass copy AX to reg and reg to ALUREG
path_s.datareg_input<= ALUBUS_IN & '1' & instr.ireg(2 downto 0); -- dimux & w & seldreg
path_s.alu_operation<= REG_AX & '0' & instr.ireg(2 downto 0) & ALU_PASSA; -- selalua(4) & selalub(4) & aluopr
wrpath_s.wrd <= '1'; -- Update AX & write reg to ALUREG
wrpath_s.wralu<= '1'; -- Write INBUSB to ALUREG
next_state <= Sdecode; -- second pass
else
second_pass_s <= '0'; -- clear
-- Second Pass, write ALU register to AX
path_s.datareg_input<= ALUBUS_IN & '1' & REG_AX(2 downto 0); -- dimux & w & seldreg
-- selalua and selalub are don't care, use previous values to reduce synth
path_s.alu_operation<= REG_AX & '0' & instr.ireg(2 downto 0) & ALU_REGL;-- selalua(4) & selalub(4) & aluopr
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
wrpath_s.wrd <= '1'; -- Write ALUREG to AX
next_state <= Sexecute;
end if;
---------------------------------------------------------------------------------
-- Exchange Register with Register/Memory
---------------------------------------------------------------------------------
when XCHGW | XCHGB =>
if instr.xmod="11" then -- Register to Register rm=reg field
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
if (second_pass='0') then -- first pass read operand
second_pass_s <= '1'; -- need another pass
-- First pass copy rm to ireg and ireg to ALUREG
path_s.datareg_input<= ALUBUS_IN & instr.ireg(0) & instr.reg; -- dimux & w & seldreg
path_s.alu_operation<= '0'&instr.rm & '0'&instr.reg & ALU_PASSA; -- selalua(4) & selalub(4) & aluopr
wrpath_s.wrd <= '1'; -- Update AX & write reg to ALUREG
wrpath_s.wralu<= '1'; -- Write INBUSB to ALUREG (instr.reg)
next_state <= Sdecode; -- second pass
else
second_pass_s <= '0'; -- clear
-- Second Pass, write ALUREG(ireg) to rm
path_s.datareg_input<= ALUBUS_IN & instr.ireg(0) & instr.rm; -- dimux & w & seldreg
-- selalua and selalub are don't care
path_s.alu_operation<= DONTCARE(3 downto 0) & '0'&instr.reg & ALU_REGL; -- selalua(4) & selalub(4) & aluopr
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
wrpath_s.wrd <= '1'; -- Write ALUREG to AX
next_state <= Sexecute;
end if;
else
path_s.ea_output <= NB_DS_EA; -- dispmux & eamux & segop (unless Segment OP flag is set)
if (second_pass='0') then -- first pass read operand from memory
second_pass_s <= '1'; -- need another pass
-- First pass copy rm to ireg and ireg to ALUREG
path_s.datareg_input<= MDBUS_IN & instr.ireg(0) & instr.reg; -- dimux & w & seldreg
path_s.alu_operation<= '0'&instr.rm & '0'&instr.reg & ALU_PASSA; -- selalua(4) & selalub(4) & aluopr
wrpath_s.wrd <= '1'; -- Update AX & write reg to ALUREG
wrpath_s.wralu<= '1'; -- Write INBUSB to ALUREG (instr.reg)
next_state <= Sreadmem; -- get memory operand
else
second_pass_s <= '0'; -- clear
path_s.datareg_input<= DONTCARE(2 downto 0) & instr.ireg(0) & DONTCARE(2 downto 0); -- dimux & w & seldreg
-- selalua and selalub are don't care, use previous values to reduce synth?????
path_s.alu_operation<= '0'&instr.rm & '0'&instr.reg & ALU_REGL; -- selalua(4) & selalub(4) & aluopr
path_s.dbus_output <= ALUBUS_OUT; --{eabus(0)&} domux setting
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Swritemem;
end if;
end if;
---------------------------------------------------------------------------------
-- Processor Control Instructions
-- ALU operation is defined in bits 5-0 of opcode
---------------------------------------------------------------------------------
when CLC | CMC | STC | CLD | STDx | CLI | STI =>
second_pass_s <= '0';
path_s.datareg_input<= DONTCARE(6 downto 0) ; -- dimux(3) & w & seldreg(3)
-- Note aluopr = bit 3 to 0 of opcode
-- Note ALU_CMC(6 downto 4) is generic for all sub types
path_s.alu_operation<= DONTCARE(7 downto 0) & ALU_CMC(6 downto 4)&instr.ireg(3 downto 0);-- selalua(4) & selalub(4) & aluopr(7)
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
wrpath_s.wrcc <= '1'; -- Update Status Register
next_state <= Sexecute;
---------------------------------------------------------------------------------
-- Load AH with flags (7 downto 0)
-- Note orginal instruction only loads bit 7,6,4,2,0 (easy change if required)
-- ALU operation is defined in bits 6-0 of opcode
---------------------------------------------------------------------------------
when LAHF =>
second_pass_s <= '0';
path_s.datareg_input<= ALUBUS_IN & REG_AH; -- dimux & w & seldreg(3)
-- note aluopr = bit 6 to 0 of opcode
path_s.alu_operation<= DONTCARE(7 downto 0) & ALU_LAHF(6 downto 4)&instr.ireg(3 downto 0);-- selalua & selalub & aluopr
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
wrpath_s.wrd <= '1'; -- Write Result to AH
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
---------------------------------------------------------------------------------
-- Store AH into flags (7 downto 0)
-- Note orginal instruction only stores bit 7,6,4,2,0
-- ALU operation is defined in bits 6-0 of opcode
---------------------------------------------------------------------------------
when SAHF =>
second_pass_s <= '0';
path_s.datareg_input<= DONTCARE(2 downto 0)&'0'& DONTCARE(2 downto 0); -- dimux(3) & w & seldreg(3)
-- note aluopr = bit 6 to 0 of opcode
path_s.alu_operation<= REG_AH & DONTCARE(3 downto 0) & ALU_SAHF(6 downto 4)&instr.ireg(3 downto 0);-- selalua & selalub & aluopr
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
wrpath_s.wrcc <= '1'; -- Update Status Register with contents AH
next_state <= Sexecute;
---------------------------------------------------------------------------------
-- PUSH Data Register
---------------------------------------------------------------------------------
when PUSHAX | PUSHCX | PUSHDX | PUSHBX | PUSHSP | PUSHBP | PUSHSI | PUSHDI =>
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
path_s.dbus_output <= ALUBUS_OUT; --{eabus(0)&} domux setting
path_s.ea_output <= NB_SS_SP & DONTCARE(2 downto 0); -- SS:SP+2
if (second_pass='0') then -- first pass SP-2
second_pass_s <= '1'; -- need another pass
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_PUSH;-- selalua(4) & selalub(4) & aluopr
wrpath_s.wrd <= '1'; -- Update SP
wrpath_s.wralu <= '1'; -- Save reg in alureg (required for PUSH SP)
next_state <= Sdecode; -- second pass
else
second_pass_s <= '0'; -- clear
path_s.alu_operation<= '0'&instr.reg & REG_CONST2 & ALU_PASSA;-- selalua(4) & selalub(4) & aluopr
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Swritemem; -- start write cycle
end if;
---------------------------------------------------------------------------------
-- PUSH Flag Register
---------------------------------------------------------------------------------
when PUSHF => -- Push flag register
path_s.dbus_output <= CCBUS_OUT; --{eabus(0)&} domux setting
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_PUSH;-- selalua(4) & selalub(4) & aluopr
if (second_pass='0') then -- first pass SP-2
second_pass_s <= '1'; -- need another pass
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
path_s.ea_output <= NB_DS_EA; -- dispmux & eamux & segop (unless Segment OP flag is set)
wrpath_s.wrd <= '1'; -- Update SP
--next_state <= Sreadmem; -- start read cycle
next_state <= Sdecode; -- second pass
else
second_pass_s <= '0'; -- clear
-- Second Pass, write memory operand to stack
path_s.datareg_input<= MDBUS_IN & '1' & DONTCARE(2 downto 0); -- dimux & w & seldreg
path_s.ea_output <= NB_SS_SP & DONTCARE(2 downto 0); -- dispmux(2) & eamux(4) & [flag]&segop(2)
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Swritemem; -- start write cycle
end if;
---------------------------------------------------------------------------------
-- POP Flag Register
---------------------------------------------------------------------------------
when POPF => -- POP Flags
-- Setup datapath for SP<=SP-2, ea=SS:SP
-- Note datareg_input is don't care during second pass
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
path_s.ea_output <= NB_SS_SP &DONTCARE(2 downto 0); -- SS:SP+2
if (second_pass='0') then -- first pass read operand
second_pass_s <= '1'; -- need another pass
-- First pass, start read and update SP
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_POP;-- selalua(4) & selalub(4) & aluopr
wrpath_s.wrd <= '1'; -- Update SP
next_state <= Sreadmem; -- start read cycle to get [SS:SP]
else
second_pass_s <= '0'; -- clear
-- Second Pass, write memory operand to CC register
path_s.alu_operation<= REG_MDBUS & REG_CONST2 & ALU_POP;-- selalua(4) & selalub(4) & aluopr
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
wrpath_s.wrcc <= '1'; -- Update Status Register
next_state <= Sexecute;
end if;
---------------------------------------------------------------------------------
-- POP Data Register
---------------------------------------------------------------------------------
when POPAX | POPCX | POPDX | POPBX | POPSP | POPBP | POPSI | POPDI =>
path_s.ea_output <= NB_SS_SP & DONTCARE(2 downto 0); -- SS:SP
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_POP;-- selalua(4) & selalub(4) & aluopr
if (second_pass='0') then -- first pass read operand
second_pass_s <= '1'; -- need another pass
-- First pass, start read and update SP
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
wrpath_s.wrd <= '1'; -- Update SP
next_state <= Sreadmem; -- start read cycle to get [SS:SP]
else
second_pass_s <= '0'; -- clear
-- Second Pass, write memory operand to data register
path_s.datareg_input<= MDBUS_IN & '1' & instr.ireg(2 downto 0); -- dimux & w & seldreg
wrpath_s.wrd <= '1'; -- Update DataReg
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
end if;
---------------------------------------------------------------------------------
-- POP TOS to Memory or Register
--
---------------------------------------------------------------------------------
when POPRM =>
if (second_pass='0') then -- first pass read operand
second_pass_s <= '1'; -- need another pass
path_s.ea_output <= NB_SS_SP & DONTCARE(2 downto 0); -- SS:SP
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_POP;-- selalua(4) & selalub(4) & aluopr
-- First pass, start read and update SP
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
wrpath_s.wrd <= '1'; -- Update SP
next_state <= Sreadmem; -- start read cycle to get [SS:SP]
else -- second pass, write to memory or register
second_pass_s <= '0'; -- no more passes
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
-- Next are only used when xmod/=11, for xmod=11 they are don't care
path_s.dbus_output <= DIBUS_OUT; --{eabus(0)&} domux setting
path_s.ea_output <= NB_DS_EA; -- dispmux=000,eamux=0001, dis_opflag=0, segop=11
-- For xmod/=11 the last 3 bits are DONTCARE
path_s.datareg_input<= MDBUS_IN & '1' & instr.rm; -- dimux & w & seldreg ireg-> r=4, rm->r=1
if instr.xmod="11" then -- POP Register r/m=reg field
-- This is the same as POPAX, POPCX etc
wrpath_s.wrd <= '1'; -- Update DataReg
next_state <= Sexecute;
else
next_state <= Swritemem; -- Update memory location pointed to by EA
end if;
end if;
---------------------------------------------------------------------------------
-- POP Segment Register
-- Note POP CS is illegal, result unknown instruction, assert bus error
-- Interrupts are disabled until the next instruction
---------------------------------------------------------------------------------
when POPES | POPSS | POPDS =>
irq_blocked_s <= '1'; -- Block IRQ if asserted during next instr.
second_pass_s <= '0';
irq_blocked_s <= '1'; -- Block IRQ if asserted during next instr.
path_s.ea_output <= NB_SS_SP & DONTCARE(2 downto 0); -- SS:SP+2
-- Path to update SP
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_POP;-- selalua(4) & selalub(4) & aluopr
-- Path to write operand to segment register
path_s.segreg_input <= SMDBUS_IN & instr.ireg(4 downto 3); -- simux(2) & selsreg(2)
wrpath_s.wrd <= '1'; -- Update SP
wrpath_s.wrs <= '1'; -- Update Segment Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sreadmem; -- start read cycle to get [SS:SP]
---------------------------------------------------------------------------------
-- PUSH Segment Register
-- PUSH CS is legal
---------------------------------------------------------------------------------
when PUSHES | PUSHCS | PUSHSS | PUSHDS =>
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_PUSH;-- selalua(4) & selalub(4) & aluopr
path_s.dbus_output <= DIBUS_OUT; --{eabus(0)&} domux setting
path_s.ea_output <= NB_SS_SP & DONTCARE(2 downto 0); -- SS:SP+2
if (second_pass='0') then -- first pass SP-2
second_pass_s <= '1'; -- need another pass
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
wrpath_s.wrd <= '1'; -- Update SP
next_state <= Sdecode; -- second pass
else
second_pass_s <= '0'; -- clear
path_s.datareg_input<= '1' & instr.ireg(4 downto 3) & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Swritemem; -- start write cycle
end if;
---------------------------------------------------------------------------------
-- Unconditional Jump
-- Short Jump within segment, SignExt DISPL
-- Long Jump within segment, No SignExt DISPL
-- Direct within segment (JMPDIS, new CS,IP on data_in and disp)
---------------------------------------------------------------------------------
when JMPS| JMP | JMPDIS=>
second_pass_s <= '0';
flush_req_s <= '1'; -- Flush Prefetch queue, asserted during execute cycle
path_s.segreg_input <= SDATAIN_IN & CS_IN(1 downto 0);-- simux & selsreg, only for JMPDIS
if (instr.ireg(1 downto 0)="10") then -- JMPDIS Instruction
path_s.ea_output <= LD_CS_IP; -- dispmux & eamux & segop Load new CS:IP from memory
wrpath_s.wrs <= '1'; -- Update CS register
else
path_s.ea_output <= DISP_CS_IP; -- CS:IPREG+DISPL
end if;
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
---------------------------------------------------------------------------------
-- LOOP Instruction
-- No flags are affected
-- Note: JCXZ can be speeded up by 1 clk cycle since the first pass is not
-- required!!
---------------------------------------------------------------------------------
when LOOPCX | LOOPZ | LOOPNZ | JCXZ =>
path_s.datareg_input<= ALUBUS_IN & '1' & REG_CX(2 downto 0); -- dimux & w & seldreg
path_s.alu_operation<= REG_CX & REG_CONST1 & ALU_DEC;-- selalua(4) & selalub(4) & aluopr
if (second_pass='0') then -- first pass CX <= CX-1
second_pass_s <= '1'; -- need another pass
if (instr.ireg(1 downto 0)/="11") then
wrpath_s.wrd <= '1'; -- Update CX unless instr=JCXZ
end if;
next_state <= Sdecode; -- Next check CX value
else -- Next check CX and flag value
second_pass_s <= '0';
-- path ALU is don't care
-- ver 0.70 fixed loop!! status.cx_zero ro cx_one
if (((instr.ireg(1 downto 0)="00") and (status.flag(6)='0') and (status.cx_one='0')) or -- loopnz, jump if cx/=0 && zf=0
((instr.ireg(1 downto 0)="01") and (status.flag(6)='1') and (status.cx_one='0')) or-- loopz, jump if cx/=0 && zf=1
((instr.ireg(1 downto 0)="10") and (status.cx_one='0')) or -- loop, jump if cx/=0
((instr.ireg(1 downto 0)="11") and (status.cx_zero='1'))) then -- jcxz jump if cx=0
flush_req_s <= '1';
path_s.ea_output <= DISP_CS_IP; -- jump
else
path_s.ea_output <= NB_CS_IP; -- Do not jump
end if;
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
end if;
-----------------------------------------------------------------------------
-- FF/FE Instructions. Use regfield to decode operation
-- INC reg=000 (FF/FE)
-- DEC reg=001 (FF/FE)
-- CALL reg=010 (FF) Indirect within segment
-- CALL reg=011 (FF) Indirect Intersegment
-- JMP reg=100 (FF) Indirect within segment
-- JMP reg=101 (FF) Indirect Intersegment
-- PUSH reg=110 (FF)
-----------------------------------------------------------------------------
when FEINSTR | FFINSTR =>
case instr.reg is
when "000" | "001" => -- INC or DEC instruction
if instr.xmod="11" then -- Immediate to Register r/m=reg field
second_pass_s <= '0';
path_s.datareg_input<= ALUBUS_IN & instr.ireg(0) & instr.rm; -- dimux & w & seldreg Note RM=Destination
-- instr.reg(5..3) contains the required operation, ALU_INBUSB=X"0001"
-- note ALU_INC(6 downto 3) is generic for both INC and DEC
path_s.alu_operation<= '0'&instr.rm & REG_CONST1 & ALU_INC(6 downto 3)&instr.reg; -- selalua & selalub & aluopr
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
wrpath_s.wrd <= '1'; -- Write Data Register to Data Register
wrpath_s.wrcc <= '1'; -- Update Status Register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
else -- Destination and source is memory (no wrpath_s.wrd)
-- This is nearly the same as AND with d=0, see above
-- only need W bit
path_s.datareg_input<= DONTCARE(2 downto 0) & instr.ireg(0) & DONTCARE(2 downto 0); -- dimux & w & seldreg (only dimux, the rest is don't care)
-- INC/DEC Memory, need to read memory first
path_s.alu_operation<= REG_MDBUS & REG_CONST1 & ALU_INC(6 downto 3)&instr.reg; -- selalua & selalub & aluopr
path_s.dbus_output <= ALUBUS_OUT; --{eabus(0)&} domux setting
path_s.ea_output <= NB_DS_EA; -- dispmux & eamux & segop (unless Segment OP flag is set)
if (second_pass='0') then -- first pass read operand
second_pass_s <= '1'; -- need another pass
next_state <= Sreadmem; -- start read cycle
else
second_pass_s <= '0'; -- clear
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
wrpath_s.wrcc <= '1'; -- Update Status Register
next_state <= Swritemem; -- start write cycle
end if;
end if;
---------------------------------------------------------------------------------
-- CALL Indirect within Segment
-- SP<=SP-2
-- Mem(SP)<=IP
-- IP<=EA
---------------------------------------------------------------------------------
when "010" =>
flush_coming_s<= '1'; -- signal to the BIU that a flush is coming,
-- this will stop the BIU from filling the queue.
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_PUSH;-- selalua(4) & selalub(4) & aluopr
path_s.dbus_output <= IPBUS_OUT; --{eabus(0)&} domux setting
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
if (second_pass='0') then -- first pass SP-2
second_pass_s <= '1';
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0); -- SS:SP+2
passcnt_s <= X"02";
wrpath_s.wrd <= '1'; -- Update SP
next_state <= Sdecode; -- second pass
else -- Second pass Mem
passcnt_s <= passcnt - '1';
if (passcnt=X"00") then
second_pass_s <= '0'; -- clear
flush_req_s <= '1'; -- Flush Prefetch queue, asserted during execute cycle
path_s.ea_output<=NB_CS_IP; -- select CS:IP before Flush;
next_state <= Sexecute;
elsif (passcnt=X"01") then -- Third pass
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
if instr.xmod="11" then
second_pass_s <= '0'; -- clear
flush_req_s <= '1'; -- Flush Prefetch queue, asserted during execute cycle
path_s.ea_output<= "1001001001";-- fix version 1.0a 02/08/09 EA_CS_IP;
next_state <= Sexecute;
else
second_pass_s <= '1'; -- need another pass
-- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
path_s.ea_output<= "0100001011"; -- Get indirect value
next_state <= Sreadmem;
end if;
else -- Second pass write MEM(SS:SP)<=IP
second_pass_s <= '1';
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0);-- ADDR=SS:SP
next_state <= Swritemem; -- start write cycle, MEM(SP)<=IP
end if;
end if;
---------------------------------------------------------------------------------
-- CALL IntraSegment Indirect
-- SP<=SP-2
-- Mem(SP)<=CS
-- SP<=SP-2
-- Mem(SP)<=IP
-- CS<=DS:EA
-- IP<=DS:EA+2
-- Flush
---------------------------------------------------------------------------------
when "011" =>
flush_coming_s<= '1'; -- signal to the BIU that a flush is coming,
-- this will stop the BIU from filling the queue.
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_PUSH;-- selalua(4) & selalub(4) & aluopr
if (second_pass='0') then -- first pass SP<=SP-2
second_pass_s <= '1';
path_s.dbus_output<=DONTCARE(1 downto 0);
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0); -- SS:SP+2 (DONTCARE)
passcnt_s <= X"05";
wrpath_s.wrd <= '1'; -- Update SP
next_state <= Sdecode;
else
passcnt_s <= passcnt - '1';
if (passcnt=X"05") then -- Second pass write CS to ss:sp
second_pass_s <= '1';
path_s.segreg_input <= DONTCARE(1 downto 0) & CS_IN(1 downto 0); -- simux & selsreg
path_s.datareg_input<= CS_IN & '1' & DONTCARE(2 downto 0); -- dimux & w & seldreg
path_s.dbus_output <= DIBUS_OUT; --{eabus(0)&} domux setting CS out
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0);-- ADDR=SS:SP
next_state <= Swritemem; -- start write cycle, MEM(SP)<=CS
elsif (passcnt=X"04") then -- Third pass SP<=SP-2
second_pass_s <= '1';
path_s.dbus_output<=DONTCARE(1 downto 0);
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0); -- SS:SP+2
wrpath_s.wrd <= '1'; -- Update SP
next_state <= Sdecode;
elsif (passcnt=X"03") then -- fourth pass, write IP
second_pass_s <= '1';
path_s.segreg_input <= DONTCARE(3 downto 0); -- simux & selsreg
path_s.datareg_input<= DONTCARE(2 downto 0)& '1' &DONTCARE(2 downto 0); -- dimux & w & seldreg
path_s.dbus_output <= IPBUS_OUT; --{eabus(0)&} domux setting CS out
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0);-- ADDR=SS:SP
next_state <= Swritemem; -- start write cycle, MEM(SP)<=CS
elsif (passcnt=X"02") then -- fifth pass, CS<=Mem(EA+2)
second_pass_s <= '1'; -- need another pass
path_s.segreg_input <= SMDBUS_IN & CS_IN(1 downto 0); -- simux & selsreg
path_s.datareg_input<= DONTCARE(2 downto 0)& '1' &DONTCARE(2 downto 0); -- dimux & w & seldreg
wrpath_s.wrs <= '1'; -- update cs
-- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
path_s.ea_output<= MD_EA2_DS; --"010110011"; -- Get indirect value EA+2
next_state <= Sreadmem; -- Get CS value from memory
elsif (passcnt=X"01") then -- sixth pass, IP<=Mem(EA)
second_pass_s <= '1'; -- need another pass
path_s.datareg_input<= DONTCARE(2 downto 0)& '1' &DONTCARE(2 downto 0); -- dimux & w & seldreg
wrpath_s.wrip <= '1'; -- update ip
-- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
path_s.ea_output<= "0100001011"; -- Get indirect value EA
next_state <= Sreadmem; -- Get CS value from memory
else -- Final pass, update IP & CS
second_pass_s <= '0'; -- clear
path_s.dbus_output <= IPBUS_OUT; --{eabus(0)&} domux setting
path_s.datareg_input<= DONTCARE(2 downto 0)& '1' &DONTCARE(2 downto 0); -- dimux & w & seldreg
flush_req_s <= '1'; -- Flush Prefetch queue, asserted during execute cycle
path_s.ea_output<=NB_CS_IP; -- dispmux & eamux & segop
next_state <= Sexecute;
end if;
end if;
---------------------------------------------------------------------------------
-- JMP Indirect within Segment
-- IP<=EA
---------------------------------------------------------------------------------
when "100" =>
path_s.datareg_input<= DONTCARE(2 downto 0)& '1' &DONTCARE(2 downto 0); -- dimux & w & seldreg
if instr.xmod="11" then -- Immediate to Register r/m=reg field
second_pass_s <= '0';
flush_req_s <= '1'; -- Flush Prefetch queue, asserted during execute cycle
path_s.ea_output<= "1001001001"; -- Select eabus with eamux(0)=0 (dispmux(3) & eamux(4) & segop(2)
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
else -- source is memory
if (second_pass='0') then -- first pass read operand
second_pass_s <= '1'; -- need another pass
path_s.ea_output<= "0100001011"; -- Get indirect value
wrpath_s.wrip <= '1'; -- Update IP register
next_state <= Sreadmem; -- start read cycle
else
second_pass_s <= '0'; -- clear
flush_req_s <= '1'; -- Flush Prefetch queue, asserted during execute cycle
path_s.ea_output<= "0100000011"; -- select CS:IPreg before Flush
next_state <= Sexecute;
end if;
end if;
---------------------------------------------------------------------------------
-- JMP Indirect Inter Segment
-- IP<=EA
-- CS<=EA+2
---------------------------------------------------------------------------------
when "101" =>
path_s.datareg_input<= DONTCARE(2 downto 0)& '1' &DONTCARE(2 downto 0); -- dimux & w & seldreg
path_s.segreg_input <= SMDBUS_IN & CS_IN(1 downto 0); -- simux & selsreg
if (second_pass='0') then -- first pass read IP
second_pass_s <= '1'; -- need another pass
passcnt_s <= X"01"; -- need extra pass
path_s.ea_output<= "0100001011"; -- Get indirect value
wrpath_s.wrip <= '1'; -- Update IP register
next_state <= Sreadmem; -- start read cycle
else
passcnt_s <= passcnt - '1';
if (passcnt=X"01") then
second_pass_s <= '1'; -- need another pass (HT0912)
-- path_s.segreg_input <= SMDBUS_IN & CS_IN(1 downto 0); -- simux & selsreg
-- path_s.datareg_input<= DONTCARE(2 downto 0)& '1' &DONTCARE(2 downto 0); -- dimux & w & seldreg
-- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
path_s.ea_output<= MD_EA2_DS; -- Get indirect value EA+2
wrpath_s.wrs <= '1'; -- update cs
next_state <= Sreadmem; -- Get CS value from memory
else
second_pass_s <= '0'; -- clear
flush_req_s <= '1'; -- Flush Prefetch queue, asserted during execute cycle
path_s.ea_output<= "0100000011"; -- select CS:IPreg before Flush
next_state <= Sexecute;
end if;
end if;
---------------------------------------------------------------------------------
-- PUSH reg/memory
---------------------------------------------------------------------------------
when "110" => -- PUSH MEM Instuction
path_s.dbus_output <= DIBUS_OUT; --{eabus(0)&} domux setting
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_PUSH;-- selalua(4) & selalub(4) & aluopr
-- change ALU_Push???
if (second_pass='0') then -- first pass read operand and execute SP-2
second_pass_s <= '1'; -- need another pass
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
path_s.ea_output <= NB_DS_EA; -- dispmux & eamux & segop (unless Segment OP flag is set)
wrpath_s.wrd <= '1'; -- Update SP
next_state <= Sreadmem; -- start read cycle
else
second_pass_s <= '0'; -- clear
-- Second Pass, write memory operand to stack
path_s.datareg_input<= MDBUS_IN & '1' & DONTCARE(2 downto 0); -- dimux & w & seldreg
path_s.ea_output <= NB_SS_SP & DONTCARE(2 downto 0); -- dispmux(2) & eamux(4) & [flag]&segop(2)
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Swritemem; -- start write cycle
end if;
when others =>
next_state <= Sdecode; -- To avoid latches
-- pragma synthesis_off
assert not (now > 0 ns) report "**** FF/FE REGField=111 Illegal Instuction ***" severity warning;
-- pragma synthesis_on
end case;
---------------------------------------------------------------------------------
-- CALL Direct within Segment
-- SP<=SP-2
-- Mem(SP)<=IP
-- IP<=IP+/-Disp
---------------------------------------------------------------------------------
when CALL =>
flush_coming_s<= '1'; -- signal to the BIU that a flush is coming,
-- this will stop the BIU from filling the queue.
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_PUSH;-- selalua(4) & selalub(4) & aluopr
path_s.dbus_output <= IPBUS_OUT; --{eabus(0)&} domux setting
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
if (second_pass='0') then -- first pass SP-2
second_pass_s <= '1';
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0); -- SS:SP+2
passcnt_s <= X"01";
wrpath_s.wrd <= '1'; -- Update SP
next_state <= Sdecode; -- second pass
else -- Second pass Mem
passcnt_s <= passcnt - '1';
if (passcnt=X"00") then
second_pass_s <= '0'; -- clear
flush_req_s <= '1'; -- Flush Prefetch queue, asserted during execute cycle
path_s.ea_output<= DISP_CS_IP; -- CS: IPREG+DISPL
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
else
second_pass_s <= '1';
path_s.ea_output <= NB_SS_SP & DONTCARE(2 downto 0);-- ADDR=SS:SP
next_state <= Swritemem; -- start write cycle, MEM(SP)<=IP
end if;
end if;
---------------------------------------------------------------------------------
-- CALL Direct InterSegment
-- SP<=SP-2,
-- Mem(SP)<=CS, CS<=SEGMh/l
-- SP<=SP-2
-- Mem(SP)<=IP, IP<=OFFSETh/l & Flush
---------------------------------------------------------------------------------
when CALLDIS =>
flush_coming_s<= '1'; -- signal to the BIU that a flush is coming,
-- this will stop the BIU from filling the queue.
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_PUSH;-- selalua(4) & selalub(4) & aluopr
if (second_pass='0') then -- first pass SP<=SP-2
second_pass_s <= '1';
path_s.dbus_output<=DONTCARE(1 downto 0);
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0); -- SS:SP+2 (DONTCARE)
passcnt_s <= X"03";
wrpath_s.wrd <= '1'; -- Update SP
next_state <= Sdecode;
else
passcnt_s <= passcnt - '1';
if (passcnt=X"03") then -- Second pass write CS to ss:sp
second_pass_s <= '1';
path_s.segreg_input <= DONTCARE(1 downto 0) & CS_IN(1 downto 0); -- simux & selsreg
path_s.datareg_input<= CS_IN & '1' & DONTCARE(2 downto 0); -- dimux & w & seldreg
path_s.dbus_output <= DIBUS_OUT; --{eabus(0)&} domux setting CS out
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0);-- ADDR=SS:SP
next_state <= Swritemem; -- start write cycle, MEM(SP)<=CS
elsif (passcnt=X"02") then -- Third pass SP<=SP-2
second_pass_s <= '1';
path_s.dbus_output<=DONTCARE(1 downto 0);
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0); -- SS:SP+2
wrpath_s.wrd <= '1'; -- Update SP
next_state <= Sdecode;
elsif (passcnt=X"01") then -- fourth pass, write IP
second_pass_s <= '1';
path_s.segreg_input <= DONTCARE(3 downto 0); -- simux & selsreg
path_s.datareg_input<= DONTCARE(6 downto 0); -- dimux & w & seldreg
path_s.dbus_output <= IPBUS_OUT; --{eabus(0)&} domux setting CS out
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0);-- ADDR=SS:SP
next_state <= Swritemem; -- start write cycle, MEM(SP)<=CS
else -- Final pass, update IP & CS
second_pass_s <= '0'; -- clear
path_s.dbus_output<=DONTCARE(1 downto 0);
flush_req_s <= '1'; -- Flush Prefetch queue, asserted during execute cycle
path_s.segreg_input <= SDATAIN_IN & CS_IN(1 downto 0); -- simux & selsreg
path_s.ea_output<=LD_CS_IP; -- dispmux & eamux & segop Load new IP from memory
wrpath_s.wrs <= '1'; -- Update CS register
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
end if;
end if;
---------------------------------------------------------------------------------
-- RET Instructions
-- IP<=Mem(SS:SP),
-- SP<=SP+2 (RET)
-- CS<=Mem(SS:SP),
-- SP<=SP+2 (RETDIS)
---------------------------------------------------------------------------------
when RET | RETDIS | RETO | RETDISO =>
flush_coming_s<= '1'; -- signal to the BIU that a flush is coming,
-- this will stop the BIU from filling the queue.
if (second_pass='1' and passcnt=X"00") then -- last stage, add data_in to SP
path_s.alu_operation<= REG_SP & REG_DATAIN & ALU_ADD;-- selalua(4) & selalub(4) & aluopr
else
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_POP;-- selalua(4) & selalub(4) & aluopr
end if;
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
path_s.dbus_output <= IPBUS_OUT; --{eabus(0)&} domux setting
-- required to write to abusreg!!
if (second_pass='0') then -- first pass IP<=MEM(SS:SP)
second_pass_s <= '1';
path_s.ea_output<=LD_SS_SP&DONTCARE(2 downto 0);-- dispmux & eamux & segop, POP IP, SS:SP
passcnt_s <= X"03"; -- 4 cycles
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sreadmem; -- Read Stack
else
if (passcnt=X"03") then -- Second pass Mem SP=SP+2
wrpath_s.wrd <= '1'; -- Update SP
if (instr.ireg(3 downto 0)="0011") then -- RET Instruction?
passcnt_s <= X"00"; -- Dontcare
second_pass_s <= '0'; -- clear
flush_req_s <= '1'; -- Flush Prefetch queue
path_s.ea_output<=NB_CS_IP; -- select CS:IP before Flush;
next_state <= Sexecute;
elsif (instr.ireg(3 downto 0)="0010") then -- RETO Instruction?
passcnt_s <= X"00"; -- Jump to last stage
second_pass_s <= '1';
path_s.ea_output<= DONTCARE(9 downto 0);-- dispmux & eamux & segop, ADDR=SS:SP
next_state <= Sdecode;
else -- else RETDIS, RETDISO, update CS
passcnt_s <= passcnt - '1'; -- Jump to 010
second_pass_s <= '1';
path_s.ea_output<= DONTCARE(9 downto 0);-- dispmux & eamux & segop, ADDR=SS:SP
next_state <= Sdecode;
end if;
elsif (passcnt=X"02") then -- Third pass, get CS from SS:SP
passcnt_s <= passcnt - '1'; -- Jump to 01
second_pass_s <= '1';
path_s.segreg_input <= SMDBUS_IN & CS_IN(1 downto 0); -- simux & selsreg
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0);-- ADDR=SS:SP
wrpath_s.wrs <= '1'; -- update cs
next_state <= Sreadmem; -- start write cycle, MEM(SP)<=CS
elsif (passcnt=X"01") then -- SP=SP+2
wrpath_s.wrd <= '1'; -- Update SPReg
passcnt_s <= passcnt - '1';
if (instr.ireg(3 downto 0)="1010") then -- RETDISO Instruction?
second_pass_s <= '1';
path_s.ea_output<= IPB_CS_IP; -- need ipbus
next_state <= Sdecode;
else
second_pass_s <= '0'; -- clear
flush_req_s <= '1'; -- Flush Prefetch queue, asserted during execute cycle
path_s.ea_output<= IPB_CS_IP; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
next_state <= Sexecute;
end if;
else -- Final pass, Add offset to SP
second_pass_s <= '0'; -- clear
flush_req_s <= '1'; -- Flush Prefetch queue, asserted during execute cycle
path_s.ea_output<=NB_CS_IP; -- select CS:IP for Flush;"100000000"; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrd <= '1'; -- Update SPReg
next_state <= Sexecute;
end if;
end if;
---------------------------------------------------------------------------------
-- Software/Hardware Interrupts
-- SP<=SP-2
-- MEM(SS:SP)<=FLAGS
-- SP<=SP-2
-- MEM(SS:SP)<=CS
-- SP<=SP-2
-- MEM(SS:SP)<=IP
-- CS<=MEM(type*4) IF=TF=0
-- IP<=MEM(type*4)+2
-- Note save 1 cycle by adding type*4+2 to dispmux, IP and CS can be updated at
-- the same time
---------------------------------------------------------------------------------
when INT | INT3 | INTO =>
irq_blocked_s <= '1'; -- Block IRQ if asserted during next instr.
if (second_pass='0') then -- first pass SP<=SP-2
if (instr.ireg(1 downto 0)="10" and status.flag(11)='0') then -- if int0 & no Overflow then do nothing
second_pass_s <='0';
path_s.ea_output<= NB_CS_IP;
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute; -- no nothing
else
second_pass_s <= '1';
flush_coming_s <= '1'; -- Signal to the BIU that a flush is coming,
-- this will stop the BIU from filling the queue.
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0); -- SS:SP+2
wrpath_s.wrd <= '1'; -- Update SP
next_state <= Sdecode;
end if;
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_PUSH;-- selalua(4) & selalub(4) & aluopr
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
passcnt_s <= X"07";
else
passcnt_s <= passcnt - '1';
flush_coming_s<= '1'; -- Signal to the BIU that a flush is coming,
-- this will stop the BIU from filling the queue.
if (passcnt=X"07") then -- Second pass write Flags to SS:SP
second_pass_s <= '1';
path_s.datareg_input<= DONTCARE(2 downto 0)& '1' &DONTCARE(2 downto 0); -- dimux & w & seldreg
path_s.dbus_output <= CCBUS_OUT; --{eabus(0)&} domux setting
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0);-- ADDR=SS:SP
next_state <= Swritemem; -- start write cycle, MEM(SP)<=CS
elsif (passcnt=X"06") then -- Third pass SP<=SP-2
second_pass_s <= '1';
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_PUSH;-- selalua(4) & selalub(4) & aluopr
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0); -- SS:SP+2
wrpath_s.wrd <= '1'; -- Update SP
next_state <= Sdecode;
elsif (passcnt=X"05") then -- Fourth pass write CS to SS:SP
second_pass_s <= '1';
path_s.segreg_input <= DONTCARE(1 downto 0) & CS_IN(1 downto 0); -- simux & selsreg
path_s.alu_operation<= DONTCARE(7 downto 0) & ALU_CLRTIF;-- selalua(4) & selalub(4) & aluopr
path_s.datareg_input<= CS_IN & '1' & DONTCARE(2 downto 0); -- dimux & w & seldreg
path_s.dbus_output <= DIBUS_OUT; --{eabus(0)&} domux setting CS out
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0);-- ADDR=SS:SP
wrpath_s.wrcc <= '1'; -- Clear IF and TF flag
next_state <= Swritemem; -- start write cycle, MEM(SP)<=CS
elsif (passcnt=X"04") then -- Fifth pass SP<=SP-2
second_pass_s <= '1';
path_s.dbus_output<=DONTCARE(1 downto 0); -- make same as previous??????????
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_PUSH;-- selalua(4) & selalub(4) & aluopr
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0); -- SS:SP+2
wrpath_s.wrd <= '1'; -- Update SP
next_state <= Sdecode;
elsif (passcnt=X"03") then -- Sixth pass, write IP
second_pass_s <= '1';
path_s.segreg_input <= DONTCARE(3 downto 0); -- simux & selsreg
path_s.datareg_input<= DONTCARE(2 downto 0)& '1' &DONTCARE(2 downto 0); -- dimux & w & seldreg
path_s.dbus_output <= IPBUS_OUT; --{eabus(0)&} domux setting CS out
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0);-- ADDR=SS:SP
next_state <= Swritemem; -- start write cycle, MEM(SP)<=CS
elsif (passcnt=X"02") then -- Seventh pass, CS<=Mem(EA*4+2)
second_pass_s <= '1'; -- need another pass
path_s.segreg_input <= SMDBUS_IN & CS_IN(1 downto 0); -- simux & selsreg read mem
path_s.datareg_input<= DONTCARE(2 downto 0)& '1' &DONTCARE(2 downto 0); -- dimux & w & seldreg
wrpath_s.wrs <= '1'; -- Update CS, NOTE THIS CHANGES SEGBUS THUS AFFECTING
-- THE NEXT READ ADDRESS, TO PREVEND THIS SEGBUS
-- IS FORCED TO ZERO.
path_s.ea_output<= "1100111001"; -- Get indirect value EA*4+2, ip<-mdbus_in
next_state <= Sreadmem; -- get CS value from MEM(type*4)
elsif (passcnt=X"01") then -- Eigth pass, IP<=MEM(EA*4+2)
second_pass_s <= '1'; -- need another pass
path_s.datareg_input<= DONTCARE(2 downto 0)& '1' &DONTCARE(2 downto 0); -- dimux & w & seldreg
path_s.dbus_output <= IPBUS_OUT; --{eabus(0)&} domux setting
wrpath_s.wrip <= '1'; -- update ip
-- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
path_s.ea_output<= "0100110001"; -- Get indirect value mem(EA*4)
next_state <= Sreadmem;
else -- Ninth pass, update IP & CS
second_pass_s <= '0'; -- clear
path_s.dbus_output <= IPBUS_OUT; --{eabus(0)&} domux setting
path_s.datareg_input<= DONTCARE(2 downto 0)& '1' &DONTCARE(2 downto 0); -- dimux & w & seldreg
flush_req_s <= '1'; -- Flush Prefetch queue, asserted during execute cycle
path_s.ea_output<=NB_CS_IP; -- dispmux & eamux & segop
next_state <= Sexecute;
end if;
end if;
---------------------------------------------------------------------------------
-- IRET, Interrupt Return
-- IP <=MEM(SS:SP)
-- SP<=SP+2
-- CS<=MEM(SS:SP)
-- SP<=SP+2
-- FLAGS<=MEM(SS:SP)
-- SP<=SP+2
-- Flush
---------------------------------------------------------------------------------
when IRET =>
flush_coming_s<= '1'; -- signal to the BIU that a flush is coming,
-- this will stop the BIU from filling the queue.
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SP(2 downto 0); -- dimux & w & seldreg
path_s.dbus_output <= IPBUS_OUT; --{eabus(0)&} domux setting
-- required to write to abusreg!!
if (second_pass='0') then -- first pass IP<=MEM(SS:SP)
second_pass_s <= '1';
path_s.ea_output<=LD_SS_SP&DONTCARE(2 downto 0);-- dispmux & eamux & segop, POP IP, SS:SP
passcnt_s <= X"04"; -- 4 cycles
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sreadmem; -- Read Stack
else
passcnt_s <= passcnt - '1';
if (passcnt=X"04") then -- Second pass Mem SP=SP+2
second_pass_s <= '1';
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_POP;-- selalua(4) & selalub(4) & aluopr
path_s.ea_output<= DONTCARE(9 downto 0); -- dispmux & eamux & segop, ADDR=SS:SP
wrpath_s.wrd <= '1'; -- Update SP
next_state <= Sdecode;
elsif (passcnt=X"03") then -- Third pass, get CS from SS:SP
second_pass_s <= '1';
path_s.segreg_input <= SMDBUS_IN & CS_IN(1 downto 0); -- simux & selsreg
path_s.ea_output<= NB_SS_SP & DONTCARE(2 downto 0);-- ADDR=SS:SP
wrpath_s.wrs <= '1'; -- update cs
next_state <= Sreadmem; -- start write cycle, MEM(SP)<=CS
elsif (passcnt=X"02") then -- SP=SP+2
second_pass_s <= '1';
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_POP;-- selalua(4) & selalub(4) & aluopr
wrpath_s.wrd <= '1'; -- Update SP
path_s.ea_output<= IPB_CS_IP; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
next_state <= Sdecode;
elsif (passcnt=X"01") then -- get FLAGS from memory
second_pass_s <= '1';
path_s.alu_operation<= REG_MDBUS & REG_CONST2 & ALU_POP;-- selalua(4) & selalub(4) & aluopr
path_s.ea_output <= NB_SS_SP &DONTCARE(2 downto 0); -- SS:SP+2
wrpath_s.wrcc <= '1'; -- Update FLAGS register
next_state <= Sreadmem;
else -- Final pass, SP<=SP+2
second_pass_s <= '0'; -- clear
path_s.alu_operation<= REG_SP & REG_CONST2 & ALU_POP;-- selalua(4) & selalub(4) & aluopr
wrpath_s.wrd <= '1'; -- Update SP
flush_req_s <= '1'; -- Flush Prefetch queue, asserted during execute cycle
path_s.ea_output<=NB_CS_IP; -- select CS:IP for Flush;"100000000";-- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrd <= '1'; -- Update SPReg
next_state <= Sexecute;
end if;
end if;
---------------------------------------------------------------------------------
-- Load String
-- AL/AX<=DS:[SI] SI++/--
-- if REP flag is set, then CX-1, check ZF,
-- for REP if zf=1 then exit
-- for REPZ if zf=0 then exit
-- NOTE: Debug does not seem to be able to handle this instruction on REPZ
-- To be compatable Z flag checking is removed, thus only depended on CX
---------------------------------------------------------------------------------
when LODSB | LODSW =>
if (second_pass='0') then -- First pass, load AL/AX<=DS:[SI]
passcnt_s <= X"01"; -- jump to extra pass 1 (skip 10 first round)
path_s.datareg_input<= MDBUS_IN & instr.ireg(0) & REG_AX(2 downto 0); -- dimux & w & seldreg
path_s.alu_operation<= DONTCARE(14 downto 0); -- selalua(4) & selalub(4) & aluopr(7)
-- DS:[SI]
if (rep_flag='1' and status.cx_zero='1') then -- if CX=0 then skip instruction
second_pass_s <= '0';
rep_clear_s <= '1'; -- Clear Repeat flag
path_s.ea_output<=NB_CS_IP;
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
else
second_pass_s <= '1'; -- Need another pass
path_s.ea_output<="0001011001"; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrd <= '1'; -- Update AX
next_state <= Sreadmem; -- start read cycle
end if;
else
if (passcnt=X"02") then -- load al/ax<= DS:[SI]
second_pass_s <= '1'; -- Need another pass
passcnt_s <= passcnt - '1';
path_s.datareg_input<= MDBUS_IN & instr.ireg(0) & REG_AX(2 downto 0); -- dimux & w & seldreg
path_s.alu_operation<= DONTCARE(14 downto 0);-- selalua(4) & selalub(4) & aluopr(7)
-- DS:[SI]
path_s.ea_output<="0001011001"; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrd <= '1'; -- Update AX
next_state <= Sreadmem; -- start read cycle
elsif (passcnt=X"01") then -- Second PASS update SI
second_pass_s <= '1';
passcnt_s <= passcnt - '1';
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SI(2 downto 0);-- dimux & w & seldreg
path_s.alu_operation<= REG_SI & -- selalua(4) & selalub(4) & aluopr
REG_CONST1(3 downto 2)&instr.ireg(0)&(not instr.ireg(0))& -- w selects 1 or 2
ALU_INC(6 downto 1)&status.flag(10); -- df flag select inc/dec
path_s.ea_output<=NB_CS_IP; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrd <= '1'; -- Update SI
if rep_flag='1' then -- If repeat set, check CX-1
second_pass_s <= '1';
next_state <= Sdecode;
else -- no repeat end cycle
second_pass_s <= '0';
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
end if;
else -- third pass (only when rep_flag=1) CX-1
path_s.datareg_input<= ALUBUS_IN & '1' & REG_CX(2 downto 0);-- dimux & w & seldreg
path_s.alu_operation<= REG_CX & REG_CONST1 & ALU_DEC; -- selalua(4) & selalub(4) & aluopr
path_s.ea_output <= NB_CS_IP; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrd <= '1'; -- Update CX
--if (status.cx_one='1' or rep_zl_s/=status.flag(6)) then -- quit on CX=1 or ZF=z_repeat_intr
if (status.cx_one='1') then -- quit on CX=1 IGNORE ZFLAG!!!!
second_pass_s <= '0';
rep_clear_s <= '1'; -- Clear Repeat flag
passcnt_s <= passcnt - '1'; -- not required, change to DONTCARE???????????????????????????????
wrpath_s.wrip <= '1';
next_state <= Sexecute;
else
second_pass_s <= '1';
passcnt_s <= X"02"; -- Next another read mem pass
next_state <= Sdecode;
end if;
end if;
end if;
---------------------------------------------------------------------------------
-- Store String
-- ES:[DI] <=AL/AX DI++/--
-- if REP/REPZ then repeat on CX value only!
---------------------------------------------------------------------------------
when STOSB | STOSW =>
if (second_pass='0') then -- First pass, load ES:[DI]<=AL/AX
passcnt_s <= X"01"; -- jump to extra pass 1 (skip 10 first round)
path_s.datareg_input<= DONTCARE(2 downto 0) & instr.ireg(0) & DONTCARE(2 downto 0);-- dimux & w & seldreg
path_s.alu_operation<= REG_AX&DONTCARE(3 downto 0)&ALU_PASSA;-- selalua(4) & selalub(4) & aluopr(7)
path_s.dbus_output <= ALUBUS_OUT; --{eabus(0)&} domux setting
if (rep_flag='1' and status.cx_zero='1') then -- if CX=0 then skip instruction
second_pass_s <= '0';
rep_clear_s <= '1'; -- Clear Repeat flag
path_s.ea_output<=NB_CS_IP;
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
else
second_pass_s <= '1'; -- Need another pass
path_s.ea_output<="0001000001"; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
next_state <= Swritemem; -- start write cycle
end if;
else
if (passcnt=X"02") then -- load ES:[DI]<=AL/AX
second_pass_s <= '1'; -- Need another pass
passcnt_s <= passcnt - '1';
path_s.datareg_input<= DONTCARE(2 downto 0) & instr.ireg(0) & DONTCARE(2 downto 0);-- dimux & w & seldreg
path_s.alu_operation<= REG_AX&DONTCARE(3 downto 0)&ALU_PASSA;-- selalua(4) & selalub(4) & aluopr(7)
path_s.dbus_output <= ALUBUS_OUT; --{eabus(0)&} domux setting
path_s.ea_output<="0001000001"; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
next_state <= Swritemem; -- start write cycle
elsif (passcnt=X"01") then -- Second PASS update DI
second_pass_s <= '1';
passcnt_s <= passcnt - '1';
path_s.datareg_input<= ALUBUS_IN & '1' & REG_DI(2 downto 0);-- dimux & w & seldreg
path_s.alu_operation<= REG_DI & -- selalua(4) & selalub(4) & aluopr
REG_CONST1(3 downto 2)&instr.ireg(0)&(not instr.ireg(0))& -- w selects 1 or 2
ALU_INC(6 downto 1)&status.flag(10); -- df flag select inc/dec
path_s.ea_output<=NB_CS_IP; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrd <= '1'; -- Update DI
if rep_flag='1' then -- If repeat set, check CX-1
second_pass_s <= '1';
next_state <= Sdecode;
else -- no repeat end cycle
second_pass_s <= '0';
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
end if;
else -- third pass (only when rep_flag=1) CX-1
path_s.datareg_input<= ALUBUS_IN & '1' & REG_CX(2 downto 0);-- dimux & w & seldreg
path_s.alu_operation<= REG_CX & REG_CONST1 & ALU_DEC; -- selalua(4) & selalub(4) & aluopr
path_s.ea_output <= NB_CS_IP; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrd <= '1'; -- Update CX
--if (status.cx_one='1' or rep_zl_s/=status.flag(6)) then -- quit on CX=1 or ZF=z_repeat_intr
if (status.cx_one='1') then -- quit on CX=1 IGNORE ZFLAG!!!!
second_pass_s <= '0';
rep_clear_s <= '1'; -- Clear Repeat flag
passcnt_s <= passcnt - '1'; -- not required, change to DONTCARE???????????????????????????????
wrpath_s.wrip <= '1';
next_state <= Sexecute;
else
second_pass_s <= '1';
passcnt_s <= X"02"; -- Next another read mem pass
next_state <= Sdecode;
end if;
end if;
end if;
---------------------------------------------------------------------------------
-- MOV String
-- ES:[DI] <=SEG:[SI], SEG default to DS
-- DI++/-- ,SI++/--
---------------------------------------------------------------------------------
when MOVSB | MOVSW =>
if (second_pass='0') then -- First pass, load ALUREG<=SEG:[SI]
passcnt_s <= X"03"; -- Jump to state 3
path_s.datareg_input<= MDBUS_IN & instr.ireg(0) & DONTCARE(2 downto 0); -- dimux & w & seldreg
-- Load memory into ALUREG
path_s.alu_operation<= DONTCARE(3 downto 0) & REG_MDBUS & ALU_REGL; -- selalua(4) & selalub(4) & aluopr(7)
wrpath_s.wralu <= '1'; -- Don't care if instruction is not executed
if (rep_flag='1' and status.cx_zero='1') then -- if CX=0 then skip instruction
second_pass_s <= '0';
rep_clear_s <= '1'; -- Clear Repeat flag
path_s.ea_output<=NB_CS_IP;
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
else
second_pass_s <= '1'; -- Need another pass
path_s.ea_output<="0001011001"; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
next_state <= Sreadmem; -- start read cycle
end if;
else
if (passcnt=X"04") then -- Same operation as second_pass=0, load ALUREG<=SEG:[SI]
second_pass_s <= '1'; -- Need another pass
passcnt_s <= passcnt - '1';
path_s.datareg_input<= MDBUS_IN & instr.ireg(0) & DONTCARE(2 downto 0); -- dimux & w & seldreg
-- Load memory into ALUREG
path_s.alu_operation<= DONTCARE(3 downto 0) & REG_MDBUS & ALU_REGL; -- selalua(4) & selalub(4) & aluopr(7)
wrpath_s.wralu <= '1'; -- Don't care if instruction is not executed
path_s.ea_output<="0001011001"; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
next_state <= Sreadmem; -- start read cycle
elsif (passcnt=X"03") then -- second pass write ALUREG to ES:DI
second_pass_s <= '1';
passcnt_s <= passcnt - '1';
path_s.datareg_input<= DONTCARE(2 downto 0) & instr.ireg(0) & DONTCARE(2 downto 0);-- dimux & w & seldreg
path_s.alu_operation<= DONTCARE(7 downto 0)&ALU_REGL;-- selalua(4) & selalub(4) & aluopr(7) ALUREG=>output
path_s.dbus_output <= ALUBUS_OUT; --{eabus(0)&} domux setting
-- ES:[DI]
path_s.ea_output<="0001000101"; -- dispmux(3) & eamux(4) & dis_opflag=1 & segop[1:0]
next_state <= Swritemem; -- start write cycle
elsif (passcnt=X"02") then -- Next update DI
second_pass_s <= '1';
passcnt_s <= passcnt - '1';
path_s.datareg_input<= ALUBUS_IN & '1' & REG_DI(2 downto 0);-- dimux & w & seldreg
path_s.alu_operation<= REG_DI & -- selalua(4) & selalub(4) & aluopr
REG_CONST1(3 downto 2)&instr.ireg(0)&(not instr.ireg(0))& -- w selects 1 or 2
ALU_INC(6 downto 1)&status.flag(10); -- df flag select inc/dec
path_s.ea_output<=DONTCARE(9 downto 0); -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrd <= '1'; -- Update DI
next_state <= Sdecode;
elsif (passcnt=X"01") then -- Final pass if no repeat update SI
second_pass_s <= '0'; -- clear
passcnt_s <= passcnt - '1';
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SI(2 downto 0);-- dimux & w & seldreg
path_s.alu_operation<= REG_SI & -- selalua(4) & selalub(4) & aluopr
REG_CONST1(3 downto 2)&instr.ireg(0)&(not instr.ireg(0))& -- w selects 1 or 2
ALU_INC(6 downto 1)&status.flag(10); -- df flag select inc/dec
path_s.ea_output<=NB_CS_IP; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrd <= '1'; -- Update SI
if rep_flag='1' then -- If repeat set, check CX-1
second_pass_s <= '1';
next_state <= Sdecode;
else -- no repeat end cycle
second_pass_s <= '0';
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
end if;
else -- third pass (only when rep_flag=1) CX-1
path_s.datareg_input<= ALUBUS_IN & '1' & REG_CX(2 downto 0);-- dimux & w & seldreg
path_s.alu_operation<= REG_CX & REG_CONST1 & ALU_DEC; -- selalua(4) & selalub(4) & aluopr
path_s.ea_output <= NB_CS_IP; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrd <= '1'; -- Update CX
if (status.cx_one='1') then -- quit on CX=1 IGNORE ZFLAG!!!!
second_pass_s <= '0';
rep_clear_s <= '1'; -- Clear Repeat flag
passcnt_s <= passcnt - '1'; -- not required, change to DONTCARE???????????????????????????????
wrpath_s.wrip <= '1';
next_state <= Sexecute;
else
second_pass_s <= '1';
passcnt_s <= X"04"; -- Next another R/W mem pass
next_state <= Sdecode;
end if;
end if;
end if;
---------------------------------------------------------------------------------
-- CMPS Destination, source
-- note source - destination
-- SEGM:[SI] - ES:[DI]
--
-- SEGM defaults to DS, can be overwritten
-- Destination is ALWAYS ES:[DI] (dis_opflag is asserted during the read cycle)
-- DI++/--, SI++/--
-- Note no signextend on operands (compared to the CMP instruction)
---------------------------------------------------------------------------------
when CMPSB | CMPSW =>
if (second_pass='0') then -- First pass, load ALUREG<=ES:[DI] (fixed!)
passcnt_s <= X"03"; -- Jump to state 3
path_s.datareg_input<= MDBUS_IN & instr.ireg(0) & DONTCARE(2 downto 0); -- dimux & w & seldreg
-- Load memory into ALUREG
path_s.alu_operation<= DONTCARE(3 downto 0) & REG_MDBUS & ALU_REGL; -- selalua(4) & selalub(4) & aluopr(7)
wrpath_s.wralu <= '1'; -- Don't care if instruction is not executed
if (rep_flag='1' and status.cx_zero='1') then -- if CX=0 then skip instruction
second_pass_s <= '0';
rep_clear_s <= '1'; -- Clear Repeat flag
path_s.ea_output<=NB_CS_IP;
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
else
second_pass_s <= '1'; -- Need another pass, note dis_opflag=1
path_s.ea_output<="0001000101"; -- dispmux(3) & eamux(4) & dis_opflag=1 & segop[1:0]
next_state <= Sreadmem; -- start read cycle
end if;
else
if (passcnt=X"04") then -- Same operation as second_pass=0, load ALUREG<=SEG:[SI]
second_pass_s <= '1'; -- Need another pass
passcnt_s <= passcnt - '1';
path_s.datareg_input<= MDBUS_IN & instr.ireg(0) & DONTCARE(2 downto 0); -- dimux & w & seldreg
-- for CMPS load memory into ALUREG
path_s.alu_operation<= DONTCARE(3 downto 0) & REG_MDBUS & ALU_REGL; -- selalua(4) & selalub(4) & aluopr(7)
path_s.ea_output<="0001000101"; -- dispmux(3) & eamux(4) & dis_opflag=1 & segop[1:0]
wrpath_s.wralu <= '1';
next_state <= Sreadmem; -- start read cycle
elsif (passcnt="0011") then -- second pass read SEG:[SI], ALUREG-SEG:[SI]
second_pass_s <= '1';
passcnt_s <= passcnt - '1';
path_s.datareg_input<= DONTCARE(2 downto 0) & instr.ireg(0) & DONTCARE(2 downto 0);-- dimux & w & seldreg
path_s.alu_operation<= REG_MDBUS & DONTCARE(3 downto 0)&ALU_CMPS;-- selalua(4) & selalub(4) & aluopr(7) ALUREG=>output
-- ES:[DI]
path_s.ea_output<="0001011001"; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrcc <= '1'; -- update flag register
next_state <= Sreadmem;
elsif (passcnt=X"02") then -- Next update DI
second_pass_s <= '1';
passcnt_s <= passcnt - '1';
path_s.datareg_input<= ALUBUS_IN & '1' & REG_DI(2 downto 0);-- dimux & w & seldreg
path_s.alu_operation<= REG_DI & -- selalua(4) & selalub(4) & aluopr
REG_CONST1(3 downto 2)&instr.ireg(0)&(not instr.ireg(0))& -- w selects 1 or 2
ALU_INC(6 downto 1)&status.flag(10); -- df flag select inc/dec
path_s.ea_output<=DONTCARE(9 downto 0); -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrd <= '1'; -- Update DI
next_state <= Sdecode;
elsif (passcnt=X"01") then -- Final pass if no repeat update SI
passcnt_s <= passcnt - '1';
path_s.datareg_input<= ALUBUS_IN & '1' & REG_SI(2 downto 0);-- dimux & w & seldreg
path_s.alu_operation<= REG_SI & -- selalua(4) & selalub(4) & aluopr
REG_CONST1(3 downto 2)&instr.ireg(0)&(not instr.ireg(0))& -- w selects 1 or 2
ALU_INC(6 downto 1)&status.flag(10); -- df flag select inc/dec
path_s.ea_output<=NB_CS_IP; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrd <= '1'; -- yes, then update SI
if rep_flag='1' then -- If repeat set, check CX-1
second_pass_s <= '1';
next_state <= Sdecode;
else -- no repeat end cycle
second_pass_s <= '0';
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
end if;
else -- third pass (only when rep_flag=1) CX-1
path_s.datareg_input<= ALUBUS_IN & '1' & REG_CX(2 downto 0);-- dimux & w & seldreg
path_s.alu_operation<= REG_CX & REG_CONST1 & ALU_DEC; -- selalua(4) & selalub(4) & aluopr
path_s.ea_output <= NB_CS_IP; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrd <= '1'; -- Update CX
if (status.cx_one='1' or rep_zl_s/=status.flag(6)) then -- quit on CX=1 or ZF=z_repeat_intr
second_pass_s <= '0';
rep_clear_s <= '1'; -- Clear Repeat flag
passcnt_s <= passcnt - '1'; -- not required, change to DONTCARE?
wrpath_s.wrip <= '1';
next_state <= Sexecute;
else
second_pass_s <= '1';
passcnt_s <= X"04"; -- Next another R/W mem pass
next_state <= Sdecode;
end if;
end if;
end if;
---------------------------------------------------------------------------------
-- SCAS
-- SCAS -> AX/AL-ES[DI]
-- DI++/--
-- Note no signextend on operands (compared to the CMP instruction)
---------------------------------------------------------------------------------
when SCASB | SCASW =>
if (second_pass='0') then -- First pass, AX-ES:[DI]
passcnt_s <= X"01"; -- Jump to state 1
path_s.datareg_input<= MDBUS_IN & instr.ireg(0) & DONTCARE(2 downto 0); -- dimux & w & seldreg
path_s.alu_operation<= REG_AX & REG_MDBUS & ALU_SCAS; -- selalua(4) & selalub(4) & aluopr(7)
if (rep_flag='1' and status.cx_zero='1') then -- if CX=0 then skip instruction
second_pass_s <= '0';
rep_clear_s <= '1'; -- Clear Repeat flag
path_s.ea_output<= NB_CS_IP;
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
else
second_pass_s <= '1'; -- Need another pass
path_s.ea_output<= "0001000001"; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrcc <= '1'; -- update flag register
next_state <= Sreadmem; -- start read cycle
end if;
else
if (passcnt=X"02") then -- Same operation as second_pass=0, AX/AL-SEG:[SI]
second_pass_s <= '1'; -- Need another pass
passcnt_s <= passcnt - '1';
path_s.datareg_input<= MDBUS_IN & instr.ireg(0) & DONTCARE(2 downto 0); -- dimux & w & seldreg
path_s.alu_operation<= REG_AX & REG_MDBUS & ALU_SCAS; -- selalua(4) & selalub(4) & aluopr(7)
path_s.ea_output<= "0001000001"; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrcc <= '1'; -- update flag register
next_state <= Sreadmem; -- start read cycle
elsif (passcnt=X"01") then -- Final pass if no repeat update DI
second_pass_s <= '0'; -- clear
passcnt_s <= passcnt - '1';
path_s.datareg_input<= ALUBUS_IN & '1' & REG_DI(2 downto 0);-- dimux & w & seldreg
path_s.alu_operation<= REG_DI & -- selalua(4) & selalub(4) & aluopr
REG_CONST1(3 downto 2)&instr.ireg(0)&(not instr.ireg(0))& -- w selects 1 or 2
ALU_INC(6 downto 1)&status.flag(10); -- df flag select inc/dec
path_s.ea_output<=NB_CS_IP; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrd <= '1'; -- yes, then update DI
if rep_flag='1' then -- If repeat set, check CX-1
second_pass_s <= '1';
next_state <= Sdecode;
else -- no repeat end cycle
second_pass_s <= '0';
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
end if;
else -- third pass (only when rep_flag=1) CX-1
path_s.datareg_input<= ALUBUS_IN & '1' & REG_CX(2 downto 0);-- dimux & w & seldreg
path_s.alu_operation<= REG_CX & REG_CONST1 & ALU_DEC; -- selalua(4) & selalub(4) & aluopr
path_s.ea_output <= NB_CS_IP; -- dispmux(3) & eamux(4) & dis_opflag & segop[1:0]
wrpath_s.wrd <= '1'; -- Update CX
if (status.cx_one='1' or rep_zl_s/=status.flag(6)) then -- quit on CX=1 or ZF=z_repeat_intr
second_pass_s <= '0';
rep_clear_s <= '1'; -- Clear Repeat flag
passcnt_s <= passcnt - '1'; -- not required, change to DONTCARE???????????????????????????????
wrpath_s.wrip <= '1';
next_state <= Sexecute;
else
second_pass_s <= '1';
passcnt_s <= X"02"; -- Next another Read mem pass
next_state <= Sdecode;
end if;
end if;
end if;
---------------------------------------------------------------------------------
-- REP/REPz Instruction
-- Set REPEAT Flag
---------------------------------------------------------------------------------
when REPNE | REPE =>
irq_blocked_s <= '1'; -- Block IRQ if asserted during next instr.
second_pass_s <= '0';
rep_set_s <= '1';
rep_z_s <= instr.ireg(0); -- REPNE or REPE
path_s.ea_output<= NB_CS_IP;
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
---------------------------------------------------------------------------------
-- Conditional Jump
---------------------------------------------------------------------------------
when JZ | JL | JLE | JB | JBE| JP | JO | JS | JNE | JNL | JNLE | JNB| JNBE | JNP | JNO | JNS =>
second_pass_s <= '0';
if (((instr.ireg(3 downto 0)="0000") and (status.flag(11)='1')) or -- Jump on Overflow (OF=1)
((instr.ireg(3 downto 0)="0001") and (status.flag(11)='0')) or -- Jump on not overflow (OF=0)
((instr.ireg(3 downto 0)="0010") and (status.flag(0)='1')) or -- Jump on Below (CF=1)
((instr.ireg(3 downto 0)="0011") and (status.flag(0)='0')) or -- Jump on not below (CF=0)
((instr.ireg(3 downto 0)="0100") and (status.flag(6)='1')) or -- Jump on Zero ZF=1;
((instr.ireg(3 downto 0)="0101") and (status.flag(6)='0')) or -- Jump on not zero ZF=0
((instr.ireg(3 downto 0)="0110") and (status.flag(0)='1' or status.flag(6)='1')) or -- JBE, Jump on below or equal CF or ZF=1
((instr.ireg(3 downto 0)="0111") and (status.flag(0)='0' and status.flag(6)='0')) or -- JNBE, Jump on not below or equal CF&ZF=0
((instr.ireg(3 downto 0)="1000") and (status.flag(7)='1')) or -- JS, Jump on ZF=1
((instr.ireg(3 downto 0)="1001") and (status.flag(7)='0')) or -- JNS, Jump on ZF=0
((instr.ireg(3 downto 0)="1010") and (status.flag(2)='1')) or -- JP, Jump on Parity PF=1
((instr.ireg(3 downto 0)="1011") and (status.flag(2)='0')) or -- JNP, Jump on not parity PF=0
((instr.ireg(3 downto 0)="1100") and (status.flag(7)/=status.flag(11))) or -- JL, Jump on less or equal SF!=OF
((instr.ireg(3 downto 0)="1101") and (status.flag(7)=status.flag(11))) or -- JNL, Jump on not less, SF=OF
((instr.ireg(3 downto 0)="1110") and ((status.flag(7)/=status.flag(11)) or status.flag(6)='1')) or -- JLE, Jump on less or equal
((instr.ireg(3 downto 0)="1111") and ((status.flag(7)=status.flag(11)) and status.flag(6)='0'))) -- JNLE, Jump on not less or equal SF=OF & zf=0
then
flush_req_s <= '1'; -- Flush Prefetch queue, asserted during execute cycle
path_s.ea_output <= DISP_CS_IP; -- CS: IPREG+DISPL
else
path_s.ea_output <= NB_CS_IP; -- IPREG+NB ADDR=CS:IP
end if;
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
next_state <= Sexecute;
when others =>
proc_error_s<='1'; -- Assert Bus Error Signal
wrpath_s.wrip <= '1'; -- Update IP+nbreq register
path_s.ea_output<= NB_CS_IP; -- Go to next opcode
next_state <= Sexecute; -- Ignore opcode, fetch next one
-- pragma synthesis_off
assert not (now > 0 ns) report "**** Unknown Instruction to decode (proc) ***" severity warning;
-- pragma synthesis_on
end case;
----------------------------------------------------------------------------
-- Get Operand/Data from Memory
-- if second_pass=0 then execute else go for second pass
----------------------------------------------------------------------------
when Sreadmem =>
read_req <= '1'; -- Request Read Cycle
if rw_ack='1' then -- read cycle completed?
if second_pass='0' then
next_state <= Sexecute; -- execute instruction
else
next_state <= Sdecode; -- second pass
end if;
else
next_state <= Sreadmem; -- Wait ack from BIU
end if;
----------------------------------------------------------------------------
-- Write Data to Memory
-- if second_pass=0 then execute else go for second pass
----------------------------------------------------------------------------
when Swritemem =>
write_req <= '1'; -- Request Write Cycle
if rw_ack='1' then -- read cycle completed?
if second_pass='0' then
next_state <= Sexecute; -- execute instruction
else
next_state <= Sdecode; -- second pass
end if;
else
next_state <= Swritemem; -- Wait ack from BIU
end if;
----------------------------------------------------------------------------
-- Execute
-- wrpath get wrpathl_s signal
----------------------------------------------------------------------------
when Sexecute =>
wrpath <= wrpathl_s; -- Assert write strobe(s)
iomem_s <= '0'; -- Clear IOMEM cycle
-- Do not clear if REP or LOCK is used as a prefix
if ((instr.ireg/=SEGOPES) and (instr.ireg/=SEGOPCS) and (instr.ireg/=SEGOPSS) and
(instr.ireg/=SEGOPDS) and (instr.ireg/=REPNE) and
(instr.ireg/=REPE)) then
clrop <= '1'; -- clear Segment Override Flag
end if;
if instr.ireg=HLT then -- If instr=HLT then wait for interrupt
next_state <= Shalt;
elsif (flush_reql_s='1' AND flush_ack='1') then -- Flush Request & ACK
next_state <= Sopcode;
elsif (flush_reql_s='1' AND flush_ack='0') then -- Flush request and no ack yet
flush_req_s <= '1';
next_state <= Sflush; -- wait for ack flush
else
next_state <= Sopcode;
end if;
----------------------------------------------------------------------------
-- Flush State, wait until flush_ack is asserted
----------------------------------------------------------------------------
when Sflush =>
if flush_ack='0' then
flush_req_s <= '1'; -- Continue asserting flush req
next_state <= Sflush; -- Wait until req is removed
else
next_state <= Sopcode; -- Next Opcode
end if;
when Shalt =>
if irq_req='1' then
next_state <= Sopcode; -- Next Opcode
else
next_state <= Shalt; -- wait for interrupt
end if;
when others =>
next_state <= Sopcode;
end case;
end process nextstate;
end rtl;
| gpl-2.0 | 80ebab9c4cbce04a5dacf79f87c695ff | 0.325707 | 5.604894 | false | false | false | false |
os-cillation/easyfpga-sdk-java | templates/templates/tle_template.vhd | 1 | 3,997 | -- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- easyFPGA T O P L E V E L E N T I T Y
-- (tle.vhd)
--
-- Structural
--
-- Integrates SoC Bridge, Intercon, Syscon and needed cores
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;
use work.interfaces.all;
--------------------------------------------------------------------------------
ENTITY %name is
--------------------------------------------------------------------------------
port (
-- user gpios
%user_gpios
-- MCU interface
clk_i : in std_logic;
fpga_active_i : in std_logic;
mcu_active_o : out std_logic;
-- FIFO
fifo_data_io : inout std_logic_vector(7 downto 0);
fifo_rxf_n_i : in std_logic;
fifo_txe_n_i : in std_logic;
fifo_rd_n_o : out std_logic;
fifo_wr_o : out std_logic
);
end %name;
--------------------------------------------------------------------------------
ARCHITECTURE structural of %name is
--------------------------------------------------------------------------------
----------------------------------------------
-- signals
----------------------------------------------
-- clock from syscon
signal gclk_s : std_logic;
signal grst_s : std_logic;
-- wishbone master
signal wbm_i_s : wbm_in_type;
signal wbm_o_s : wbm_out_type;
-- wishbone slaves
%wbslaves
--custom signals
%customsignals
-------------------------------------------------------------------------------
begin -- architecture structural
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
SOC_BRIDGE : entity work.soc_bridge
-------------------------------------------------------------------------------
port map (
-- mcu
fpga_active_i => fpga_active_i,
mcu_active_o => mcu_active_o,
-- fifo interface
fifo_data_io => fifo_data_io,
fifo_rxf_n_i => fifo_rxf_n_i,
fifo_txe_n_i => fifo_txe_n_i,
fifo_rd_n_o => fifo_rd_n_o,
fifo_wr_o => fifo_wr_o,
-- wishbone master
wbm_i => wbm_i_s,
wbm_o => wbm_o_s
);
--------------------------------------------------------------------------------
INTERCON : entity work.intercon
--------------------------------------------------------------------------------
port map (
clk_in => gclk_s,
rst_in => grst_s,
-- wisbone master
wbm_out => wbm_o_s,
wbm_in => wbm_i_s,
-- wishbone slaves
%wbslavesintercon
);
-------------------------------------------------------------------------------
SYSCON : entity work.syscon
-------------------------------------------------------------------------------
port map (
clk_in => clk_i,
clk_out => gclk_s,
rst_out => grst_s
);
-------------------------------------------------------------------------------
-- Cores
-------------------------------------------------------------------------------
%cores
end structural;
| gpl-3.0 | 5ba0b14e8ee0994ba091f3e255f2b0d7 | 0.391043 | 4.850728 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/datapath_struct.vhd | 3 | 20,813 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.cpu86pack.ALL;
ENTITY datapath IS
PORT(
clk : IN std_logic;
clrop : IN std_logic;
instr : IN instruction_type;
iomem : IN std_logic;
mdbus_in : IN std_logic_vector (15 DOWNTO 0);
path : IN path_in_type;
reset : IN std_logic;
wrpath : IN write_in_type;
dbusdp_out : OUT std_logic_vector (15 DOWNTO 0);
eabus : OUT std_logic_vector (15 DOWNTO 0);
segbus : OUT std_logic_vector (15 DOWNTO 0);
status : OUT status_out_type
);
END datapath ;
ARCHITECTURE struct OF datapath IS
-- Internal signal declarations
SIGNAL alu_inbusa : std_logic_vector(15 DOWNTO 0);
SIGNAL alu_inbusb : std_logic_vector(15 DOWNTO 0);
SIGNAL alubus : std_logic_vector(15 DOWNTO 0);
SIGNAL aluopr : std_logic_vector(6 DOWNTO 0);
SIGNAL ax_s : std_logic_vector(15 DOWNTO 0);
SIGNAL bp_s : std_logic_vector(15 DOWNTO 0);
SIGNAL bx_s : std_logic_vector(15 DOWNTO 0);
SIGNAL ccbus : std_logic_vector(15 DOWNTO 0);
SIGNAL cs_s : std_logic_vector(15 DOWNTO 0);
SIGNAL cx_s : std_logic_vector(15 DOWNTO 0);
SIGNAL data_in : std_logic_vector(15 DOWNTO 0);
SIGNAL di_s : std_logic_vector(15 DOWNTO 0);
SIGNAL dibus : std_logic_vector(15 DOWNTO 0);
SIGNAL dimux : std_logic_vector(2 DOWNTO 0);
SIGNAL disp : std_logic_vector(15 DOWNTO 0);
SIGNAL dispmux : std_logic_vector(2 DOWNTO 0);
SIGNAL div_err : std_logic;
SIGNAL domux : std_logic_vector(1 DOWNTO 0);
SIGNAL ds_s : std_logic_vector(15 DOWNTO 0);
SIGNAL dx_s : std_logic_vector(15 DOWNTO 0);
SIGNAL ea : std_logic_vector(15 DOWNTO 0);
SIGNAL eamux : std_logic_vector(3 DOWNTO 0);
SIGNAL es_s : std_logic_vector(15 DOWNTO 0);
SIGNAL ipbus : std_logic_vector(15 DOWNTO 0);
SIGNAL ipreg : std_logic_vector(15 DOWNTO 0);
SIGNAL nbreq : std_logic_vector(2 DOWNTO 0);
SIGNAL opmux : std_logic_vector(1 DOWNTO 0);
SIGNAL rm : std_logic_vector(2 DOWNTO 0);
SIGNAL sdbus : std_logic_vector(15 DOWNTO 0);
SIGNAL segop : std_logic_vector(2 DOWNTO 0);
SIGNAL selalua : std_logic_vector(3 DOWNTO 0);
SIGNAL selalub : std_logic_vector(3 DOWNTO 0);
SIGNAL seldreg : std_logic_vector(2 DOWNTO 0);
SIGNAL selds : std_logic;
SIGNAL selsreg : std_logic_vector(1 DOWNTO 0);
SIGNAL si_s : std_logic_vector(15 DOWNTO 0);
SIGNAL sibus : std_logic_vector(15 DOWNTO 0);
SIGNAL simux : std_logic_vector(1 DOWNTO 0);
SIGNAL sp_s : std_logic_vector(15 DOWNTO 0);
SIGNAL ss_s : std_logic_vector(15 DOWNTO 0);
SIGNAL w : std_logic;
SIGNAL wralu : std_logic;
SIGNAL wrcc : std_logic;
SIGNAL wrd : std_logic;
SIGNAL wrip : std_logic;
SIGNAL wrop : std_logic;
SIGNAL wrs : std_logic;
SIGNAL wrtemp : std_logic;
SIGNAL xmod : std_logic_vector(1 DOWNTO 0);
-- Implicit buffer signal declarations
SIGNAL eabus_internal : std_logic_vector (15 DOWNTO 0);
signal domux_s : std_logic_vector(2 downto 0);
signal opreg_s : std_logic_vector(1 downto 0); -- Override Segment Register
signal opflag_s : std_logic; -- set if segment override in progress
signal eam_s : std_logic_vector(15 downto 0);
signal segsel_s : std_logic_vector(5 downto 0); -- segbus select
signal int0cs_s : std_logic;
-- Component Declarations
COMPONENT ALU
PORT (
alu_inbusa : IN std_logic_vector (15 DOWNTO 0);
alu_inbusb : IN std_logic_vector (15 DOWNTO 0);
aluopr : IN std_logic_vector (6 DOWNTO 0);
ax_s : IN std_logic_vector (15 DOWNTO 0);
clk : IN std_logic ;
cx_s : IN std_logic_vector (15 DOWNTO 0);
dx_s : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic ;
w : IN std_logic ;
wralu : IN std_logic ;
wrcc : IN std_logic ;
wrtemp : IN std_logic ;
alubus : OUT std_logic_vector (15 DOWNTO 0);
ccbus : OUT std_logic_vector (15 DOWNTO 0);
div_err : OUT std_logic
);
END COMPONENT;
COMPONENT dataregfile
PORT (
dibus : IN std_logic_vector (15 DOWNTO 0);
selalua : IN std_logic_vector (3 DOWNTO 0);
selalub : IN std_logic_vector (3 DOWNTO 0);
seldreg : IN std_logic_vector (2 DOWNTO 0);
w : IN std_logic ;
wrd : IN std_logic ;
alu_inbusa : OUT std_logic_vector (15 DOWNTO 0);
alu_inbusb : OUT std_logic_vector (15 DOWNTO 0);
bp_s : OUT std_logic_vector (15 DOWNTO 0);
bx_s : OUT std_logic_vector (15 DOWNTO 0);
di_s : OUT std_logic_vector (15 DOWNTO 0);
si_s : OUT std_logic_vector (15 DOWNTO 0);
reset : IN std_logic ;
clk : IN std_logic ;
data_in : IN std_logic_vector (15 DOWNTO 0);
mdbus_in : IN std_logic_vector (15 DOWNTO 0);
sp_s : OUT std_logic_vector (15 DOWNTO 0);
ax_s : OUT std_logic_vector (15 DOWNTO 0);
cx_s : OUT std_logic_vector (15 DOWNTO 0);
dx_s : OUT std_logic_vector (15 DOWNTO 0)
);
END COMPONENT;
COMPONENT ipregister
PORT (
clk : IN std_logic ;
ipbus : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic ;
wrip : IN std_logic ;
ipreg : OUT std_logic_vector (15 DOWNTO 0)
);
END COMPONENT;
COMPONENT segregfile
PORT (
selsreg : IN std_logic_vector (1 DOWNTO 0);
sibus : IN std_logic_vector (15 DOWNTO 0);
wrs : IN std_logic ;
reset : IN std_logic ;
clk : IN std_logic ;
sdbus : OUT std_logic_vector (15 DOWNTO 0);
dimux : IN std_logic_vector (2 DOWNTO 0);
es_s : OUT std_logic_vector (15 DOWNTO 0);
cs_s : OUT std_logic_vector (15 DOWNTO 0);
ss_s : OUT std_logic_vector (15 DOWNTO 0);
ds_s : OUT std_logic_vector (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
dimux <= path.datareg_input(6 downto 4); -- Data Register Input Path
w <= path.datareg_input(3);
seldreg <= path.datareg_input(2 downto 0);
selalua <= path.alu_operation(14 downto 11); -- ALU Path
selalub <= path.alu_operation(10 downto 7);
aluopr <= path.alu_operation(6 downto 0);
domux <= path.dbus_output; -- Data Output Path
simux <= path.segreg_input(3 downto 2); -- Segment Register Input Path
selsreg <= path.segreg_input(1 downto 0);
dispmux <= path.ea_output(9 downto 7); -- select ipreg addition
eamux <= path.ea_output(6 downto 3); -- 4 bits
segop <= path.ea_output(2 downto 0); -- segop(2)=override flag
wrd <= wrpath.wrd;
wralu <= wrpath.wralu;
wrcc <= wrpath.wrcc;
wrs <= wrpath.wrs;
wrip <= wrpath.wrip;
wrop <= wrpath.wrop;
wrtemp<= wrpath.wrtemp;
status.ax <= ax_s;
status.cx_one <= '1' when (cx_s=X"0001") else '0';
status.cx_zero <= '1' when (cx_s=X"0000") else '0';
status.cl <= cx_s(7 downto 0); -- used for shift/rotate
status.flag <= ccbus;
status.div_err <= div_err; -- Divider overflow
disp <= instr.disp;
data_in <= instr.data;
nbreq <= instr.nb;
rm <= instr.rm;
xmod <= instr.xmod;
----------------------------------------------------------------------------
-- Determine effective address
----------------------------------------------------------------------------
process (rm, ax_s,bx_s,cx_s,dx_s,bp_s,sp_s,si_s,di_s,disp,xmod)
begin
case rm is
when "000" => if xmod="11" then eam_s <= ax_s;
else eam_s <= bx_s + si_s + disp;
end if;
selds<='1';
when "001" => if xmod="11" then eam_s <= cx_s;
else eam_s <= bx_s + di_s + disp;
end if;
selds<='1';
when "010" => if xmod="11" then eam_s <= dx_s;
else eam_s <= bp_s + si_s + disp;
end if;
selds<='0';
when "011" => if xmod="11" then eam_s <= bx_s;
else eam_s <= bp_s + di_s + disp;
end if;
selds<='0';
when "100" => if xmod="11" then eam_s <= sp_s;
else eam_s <= si_s + disp;
end if;
selds<='1';
when "101" => if xmod="11" then eam_s <= bp_s;
else eam_s <= di_s + disp;
end if;
selds<='1';
when "110" => if xmod="00" then
eam_s <= disp;
selds <='1';
elsif xmod="11" then
eam_s <= si_s;
selds <='1';
else
eam_s <= bp_s + disp;
selds <='0'; -- Use SS
end if;
when others=> if xmod="11" then eam_s <= di_s;
else eam_s <= bx_s + disp;
end if;
selds<='1';
end case;
end process;
ea<=eam_s;
process(data_in,eabus_internal,alubus,mdbus_in,simux)
begin
case simux is
when "00" => sibus <= data_in;
when "01" => sibus <= eabus_internal;
when "10" => sibus <= alubus;
when others => sibus <= mdbus_in;
end case;
end process;
process(dispmux,nbreq,disp,mdbus_in,ipreg,eabus_internal)
begin
case dispmux is
when "000" => ipbus <= ("0000000000000"&nbreq) + ipreg;
when "001" => ipbus <= (("0000000000000"&nbreq)+disp) + ipreg;
when "011" => ipbus <= disp; -- disp contains new IP value
when "100" => ipbus <= eabus_internal; -- ipbus=effective address
when "101" => ipbus <= ipreg; -- bodge to get ipreg onto ipbus
when others => ipbus <= mdbus_in;
end case;
end process;
domux_s <= eabus_internal(0) & domux;
process(domux_s, alubus,ccbus, dibus, ipbus)
begin
case domux_s is
when "000" => dbusdp_out <= alubus; -- Even
when "001" => dbusdp_out <= ccbus;
when "010" => dbusdp_out <= dibus;
when "011" => dbusdp_out <= ipbus; -- CALL Instruction
when "100" => dbusdp_out <= alubus(7 downto 0)& alubus(15 downto 8); -- Odd
when "101" => dbusdp_out <= ccbus(7 downto 0) & ccbus(15 downto 8);
when "110" => dbusdp_out <= dibus(7 downto 0) & dibus(15 downto 8);
when others => dbusdp_out <= ipbus(7 downto 0) & ipbus(15 downto 8);
end case;
end process;
-- Write Prefix Register
process(clk,reset)
begin
if (reset = '1') then
opreg_s <= "01"; -- Default CS Register
opflag_s<= '0'; -- Clear Override Prefix Flag
elsif rising_edge(clk) then
if wrop='1' then
opreg_s <= segop(1 downto 0); -- Set override register
opflag_s<= '1'; -- segop(2); -- Set flag
elsif clrop='1' then
opreg_s <= "11"; -- Default Data Segment Register
opflag_s<= '0';
end if;
end if;
end process;
process (opflag_s,opreg_s,selds,eamux,segop)
begin
if opflag_s='1' and segop(2)='0' then -- Prefix register set and disable override not set?
opmux <= opreg_s(1 downto 0); -- Set mux to override prefix reg
elsif eamux(3)='1' then
opmux <= eamux(1 downto 0);
elsif eamux(0)='0' then
opmux <= "01"; -- Select CS for IP
else
opmux <= '1'&selds; -- DS if selds=1 else SS
end if;
end process;
process(dimux, data_in,alubus,mdbus_in,sdbus,eabus_internal)
begin
case dimux is
when "000" => dibus <= data_in; -- Operand
when "001" => dibus <= eabus_internal;-- Offset
when "010" => dibus <= alubus; -- Output ALU
when "011" => dibus <= mdbus_in; -- Memory Bus
when others => dibus <= sdbus; -- Segment registers
end case;
end process;
int0cs_s <= '1' when eamux(3 downto 1)="011" else '0';
segsel_s <= iomem & int0cs_s & eamux(2 downto 1) & opmux; -- 5 bits
process(segsel_s,es_s,cs_s,ss_s,ds_s) -- Segment Output Mux
begin
case segsel_s is
when "000000" => segbus <= es_s; -- 00**, opmux select register
when "000001" => segbus <= cs_s;
when "000010" => segbus <= ss_s;
when "000011" => segbus <= ds_s;
when "000100" => segbus <= es_s; -- 01**, opmux select register
when "000101" => segbus <= cs_s;
when "000110" => segbus <= ss_s;
when "000111" => segbus <= ds_s;
when "001000" => segbus <= ss_s; -- 10**=SS, used for PUSH& POP
when "001001" => segbus <= ss_s;
when "001010" => segbus <= ss_s;
when "001011" => segbus <= ss_s;
when "001100" => segbus <= es_s; -- 01**, opmux select register
when "001101" => segbus <= cs_s;
when "001110" => segbus <= ss_s;
when "001111" => segbus <= ds_s;
when others => segbus <= ZEROVECTOR_C(15 downto 0);-- IN/OUT instruction 0x0000:PORT/DX
end case;
end process;
-- Offset Mux
-- Note ea*4 required if non-32 bits memory access is used(?)
-- Currently CS &IP are read in one go (fits 32 bits)
process(ipreg,ea,sp_s,dx_s,eamux,si_s,di_s,bx_s,ax_s)
begin
case eamux is
when "0000" => eabus_internal <= ipreg;--ipbus;--ipreg;
when "0001" => eabus_internal <= ea;
when "0010" => eabus_internal <= dx_s;
when "0011" => eabus_internal <= ea + "10"; -- for call mem32/int
when "0100" => eabus_internal <= sp_s; -- 10* select SP_S
when "0101" => eabus_internal <= sp_s;
when "0110" => eabus_internal <= ea(13 downto 0)&"00";
when "0111" => eabus_internal <=(ea(13 downto 0)&"00") + "10"; -- for int
when "1000" => eabus_internal <= di_s; -- Select ES:DI
when "1011" => eabus_internal <= si_s; -- Select DS:SI
when "1001" => eabus_internal <= ea; -- added for JMP SI instruction
when "1111" => eabus_internal <= bx_s + (X"00"&ax_s(7 downto 0)); -- XLAT instruction
when others => eabus_internal <= DONTCARE(15 downto 0);
end case;
end process;
-- Instance port mappings.
I6 : ALU
PORT MAP (
alu_inbusa => alu_inbusa,
alu_inbusb => alu_inbusb,
aluopr => aluopr,
ax_s => ax_s,
clk => clk,
cx_s => cx_s,
dx_s => dx_s,
reset => reset,
w => w,
wralu => wralu,
wrcc => wrcc,
wrtemp => wrtemp,
alubus => alubus,
ccbus => ccbus,
div_err => div_err
);
I0 : dataregfile
PORT MAP (
dibus => dibus,
selalua => selalua,
selalub => selalub,
seldreg => seldreg,
w => w,
wrd => wrd,
alu_inbusa => alu_inbusa,
alu_inbusb => alu_inbusb,
bp_s => bp_s,
bx_s => bx_s,
di_s => di_s,
si_s => si_s,
reset => reset,
clk => clk,
data_in => data_in,
mdbus_in => mdbus_in,
sp_s => sp_s,
ax_s => ax_s,
cx_s => cx_s,
dx_s => dx_s
);
I9 : ipregister
PORT MAP (
clk => clk,
ipbus => ipbus,
reset => reset,
wrip => wrip,
ipreg => ipreg
);
I15 : segregfile
PORT MAP (
selsreg => selsreg,
sibus => sibus,
wrs => wrs,
reset => reset,
clk => clk,
sdbus => sdbus,
dimux => dimux,
es_s => es_s,
cs_s => cs_s,
ss_s => ss_s,
ds_s => ds_s
);
eabus <= eabus_internal;
END struct;
| gpl-2.0 | 8f2aacefddb054140748be205caad10b | 0.449238 | 4.032746 | false | false | false | false |
CamelClarkson/MIPS | MIPS_Design/Src/ALU_Ctrl_top.vhd | 2 | 1,935 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ALU_Ctrl_top is
Port (
Op5 : in STD_LOGIC; -- input of the ALU ctrl module
Op4 : in STD_LOGIC; -- input of the ALU ctrl module
Op3 : in STD_LOGIC; -- input of the ALU ctrl module
Op2 : in STD_LOGIC; -- input of the ALU ctrl module
Op1 : in STD_LOGIC; -- input of the ALU ctrl module
Op0 : in STD_LOGIC; -- input of the ALU ctrl module
RegDst : out STD_LOGIC; -- output the ALU ctrl module
ALUSrc : out STD_LOGIC; -- output the ALU ctrl module
MemtoReg : out STD_LOGIC; -- output the ALU ctrl module
RegWrite : out STD_LOGIC; -- output the ALU ctrl module
MemRead : out STD_LOGIC; -- output the ALU ctrl module
MemWrite : out STD_LOGIC; -- output the ALU ctrl module
Branch : out STD_LOGIC; -- output the ALU ctrl module
ALUOp1 : out STD_LOGIC; -- output the ALU ctrl module
ALUOp0 : out STD_LOGIC -- output the ALU ctrl module
);
end ALU_Ctrl_top;
architecture Behavioral of ALU_Ctrl_top is
signal R_format : std_logic;
signal lw : std_logic;
signal sw : std_logic;
signal beq : std_logic;
begin
R_format <= ( (not(Op5)) and (not(Op4)) and (not(Op3)) and (not(Op2)) and (not(Op1)) and (not(Op0)) );
lw <= ( (Op5) and (not(Op4)) and (not(Op3)) and (not(Op2)) and (Op1) and (Op0) );
sw <= ( (Op5) and (not(Op4)) and (Op3) and (not(Op2)) and (Op1) and (Op0) );
beq <= ( (not(Op5)) and (not(Op4)) and (not(Op3)) and (Op2) and (not(Op1)) and (not(Op0)) );
RegDst <= R_format;
ALUSrc <= lw or sw;
MemtoReg <= lw;
RegWrite <= R_format or lw;
MemRead <= lw;
MemWrite <= sw;
Branch <= beq;
ALUOp1 <= R_format;
ALUOp0 <= beq;
end Behavioral; | mit | 6272f139c3ec82a9e3419cf05cb142a0 | 0.549871 | 3.376963 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/slib_mv_filter.vhd | 3 | 2,656 | --
-- Majority voting filter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_mv_filter is
generic (
WIDTH : natural := 4;
THRESHOLD : natural := 10
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
SAMPLE : in std_logic; -- Clock enable for sample process
CLEAR : in std_logic; -- Reset process
D : in std_logic; -- Signal input
Q : out std_logic -- Signal D was at least THRESHOLD samples high
);
end slib_mv_filter;
architecture rtl of slib_mv_filter is
-- Signals
signal iCounter : unsigned(WIDTH downto 0); -- Sample counter
signal iQ : std_logic; -- Internal Q
begin
-- Main process
MV_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= (others => '0');
iQ <= '0';
elsif (CLK'event and CLK='1') then
if (iCounter >= THRESHOLD) then -- Compare with threshold
iQ <= '1';
else
if (SAMPLE = '1' and D = '1') then -- Take sample
iCounter <= iCounter + 1;
end if;
end if;
if (CLEAR = '1') then -- Reset logic
iCounter <= (others => '0');
iQ <= '0';
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
| gpl-2.0 | e4630012dbca95848ba7226cb2511780 | 0.492093 | 4.426667 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Encryption_Decryption/rc5.vhd | 1 | 5,496 | --RC5 Encryption
--A = A + S[0];
--B = B + S[1];
--for i=1 to 12 do
----A = ((A XOR B) <<< B) + S[2*i];
----B = ((B XOR A) <<< A) + S[2*1+1];
--RC5 Decryption
--for i=12 to 1 do
----B = ((B - S[2×i +1]) >>> A) xor A;
----A = ((A - S[2×i]) >>> B) xor B;
--B = B - S[1];
--A = A - S[0];
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
USE WORK.RC5_PKG.ALL;
ENTITY rc5 IS
PORT (
clr,clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal
enc : IN STD_LOGIC; --1 for encryption 0 for decryption
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit input
di_vld : IN STD_LOGIC; -- Valid Input
key_rdy : IN STD_LOGIC;
skey : IN rc5_rom_26;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit output
do_rdy : OUT STD_LOGIC --Output is Ready
);
END rc5;
ARCHITECTURE rtl OF rc5 IS
SIGNAL i_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); -- round counter
SIGNAL ab_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_rot_left : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_rot_right : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_round : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register A
SIGNAL ba_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_rot_left : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_rot_right : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_round : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register B
-- RC5 state machine has five states: idle, pre_round, round and ready
SIGNAL state : StateType;
BEGIN
WITH enc SELECT
a_round <= din(63 DOWNTO 32) + skey(0) WHEN '1',--A = A + S[0]
a_reg - skey(0) WHEN OTHERS; --A = A - S[0]
WITH enc SELECT
b_round <= din(31 DOWNTO 0) + skey(1) WHEN '1', --B = B + S[1]
b_reg - skey(1) WHEN OTHERS; --B = B - S[1]
WITH enc SELECT --A XOR B
ab_xor<=a_reg XOR b_reg WHEN '1',
a_rot_right XOR ba_xor WHEN OTHERS;
WITH enc SELECT --B XOR A
ba_xor <= b_reg XOR a WHEN '1',
b_rot_right XOR a_reg WHEN OTHERS;
WITH enc SELECT --B XOR A
a <= a_rot_left + skey(CONV_INTEGER(i_cnt & '0')) WHEN '1', --A + S[2*i]
a_reg - skey(CONV_INTEGER(i_cnt & '0')) WHEN OTHERS; -- A - S[2*i]
WITH enc SELECT --B XOR A
b <= b_rot_left + skey(CONV_INTEGER(i_cnt & '1')) WHEN '1', --B + S[2*i+1]
b_reg - skey(CONV_INTEGER(i_cnt & '1')) WHEN OTHERS; --B - S[2*i+1]
ROT_A_LEFT: rotLeft
PORT MAP(din=>ab_xor,amnt=>b_reg(4 DOWNTO 0),dout=>a_rot_left);--A <<< B
ROT_B_LEFT: rotLeft
PORT MAP(din=>ba_xor,amnt=>a(4 DOWNTO 0),dout=>b_rot_left);--B <<< A
ROT_B_RIGHT: rotRight
PORT MAP(din=>b,amnt=>a_reg(4 DOWNTO 0),dout=>b_rot_right);--B >>> A
ROT_A_RIGHT: rotRight
PORT MAP(din=>a,amnt=>ba_xor(4 DOWNTO 0),dout=>a_rot_right);--A >>> B
A_register:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
a_reg<=din(63 DOWNTO 32);
ELSIF(rising_edge(clk)) THEN --clk'EVENT AND clk='1' can introduce error
IF(state=ST_PRE_ROUND OR state=ST_POST_ROUND) THEN
a_reg<=a_round;
ELSIF(state=ST_ROUND_OP) THEN
if(enc = '1')then
a_reg<=a;
else
a_reg<=ab_xor;
end if;
END IF;
END IF;
END PROCESS;
B_register:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
b_reg<=din(31 DOWNTO 0);
ELSIF(rising_edge(clk)) THEN
IF(state=ST_PRE_ROUND OR state=ST_POST_ROUND) THEN
b_reg<=b_round;
ELSIF(state=ST_ROUND_OP) THEN
if(enc = '1')then
b_reg<=b;
else
b_reg<=ba_xor;
end if;
END IF;
END IF;
END PROCESS;
State_Control:
PROCESS(clr, clk)
BEGIN
IF(clr='0') THEN
state<=ST_IDLE;
ELSIF(rising_edge(clk)) THEN
CASE state IS
WHEN ST_IDLE=> IF(di_vld='1' and key_rdy='1') THEN
IF(enc = '1') THEN
state<=ST_PRE_ROUND;
ELSE
state<=ST_ROUND_OP;
END IF;
END IF;
WHEN ST_PRE_ROUND=> state<=ST_ROUND_OP;--Left because makes sense
WHEN ST_ROUND_OP=> IF(enc = '1') THEN
IF(i_cnt="1100") THEN
state<=ST_READY;
END IF;
ELSE
IF(i_cnt="0001") THEN
state<=ST_POST_ROUND;
END IF;
END IF;
WHEN ST_POST_ROUND=> state<=ST_READY; --Left because makes sense
WHEN ST_READY=> IF(di_vld='1' and key_rdy='1') THEN
state<=ST_IDLE;
END IF;
END CASE;
END IF;
END PROCESS;
round_counter:
PROCESS(clk, enc) BEGIN
IF(clr='0') THEN
i_cnt<="0001";
ELSIF(rising_edge(clk)) THEN
IF (state=ST_ROUND_OP) THEN
if(enc='1')then
IF(i_cnt="1100") THEN
i_cnt<="0001";
ELSE
i_cnt<=i_cnt+'1';
END IF;
else
IF(i_cnt="0001") THEN
i_cnt<="1100";
ELSE
i_cnt<=i_cnt-'1';
END IF;
END IF;
ELSIF(state=ST_PRE_ROUND)THEN
i_cnt<="0001";
ELSIF(state=ST_IDLE OR state = ST_READY)THEN
i_cnt<="1100";
END IF;
END IF;
END PROCESS;
dout<=a_reg & b_reg;
WITH state SELECT
do_rdy<='1' WHEN ST_READY,
'0' WHEN OTHERS;
END rtl;
| lgpl-2.1 | 730a535e0014f88adfccc79017039b0e | 0.537118 | 2.774356 | false | false | false | false |
VenturaSolutionsInc/VHDL | igmp/igmp_wrapper_tb.vhd | 1 | 4,124 | -------------------------------------------------------------------------------
-- Title : Testbench for design "igmp_wrapper"
-- Project :
-------------------------------------------------------------------------------
-- File : igmp_wrapper_tb.vhd
-- Author : Colin Shea <[email protected]>
-- Company :
-- Created : 2010-06-27
-- Last update: 2010-08-13
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-06-27 1.0 colinshea Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity igmp_wrapper_tb is
end igmp_wrapper_tb;
-------------------------------------------------------------------------------
architecture testbench of igmp_wrapper_tb is
-- component generics
constant gen_dataWidth : integer := 8;
signal srcMAC : std_logic_vector(47 downto 0):=X"010040506660";
signal destMAC : std_logic_vector(47 downto 0):=X"01005E1C1901";
signal vlanEn : std_logic := '0';
signal vlanId : std_logic_vector(11 downto 0):=X"06A";
signal srcIP : std_logic_vector(31 downto 0):=X"C0A80164";
signal destIP : std_logic_vector(31 downto 0):=X"EF9C1901";
signal tx_ready_n : std_logic;
signal tx_sof : std_logic;
signal tx_eof : std_logic;
signal tx_vld : std_logic;
signal tx_data : std_logic_vector(7 downto 0);
signal igmp_sof : std_logic;
signal igmp_eof : std_logic;
signal igmp_vld : std_logic;
signal igmp_data : std_logic_vector(7 downto 0);
-- component ports
signal dataClk : std_logic;
signal reset : std_logic;
signal join : std_logic;
signal leave : std_logic;
signal respond : std_logic;
signal rspTime : std_logic_vector(7 downto 0);
-- signal destIP : std_logic_vector(31 downto 0);
-- signal destMAC : std_logic_vector(47 downto 0);
-- signal messageSent : std_logic;
-- signal out_join : std_logic;
-- signal out_leave : std_logic;
-- signal out_destMAC_o : std_logic_vector(47 downto 0);
-- signal out_destIP_o : std_logic_vector(31 downto 0);
signal out_enProc : std_logic;
signal out_enCommand : std_logic;
begin -- testbench
igmp_wrapper_1: entity work.igmp_wrapper
port map (
dataClk => dataClk,
reset => reset,
join => join,
leave => leave,
srcMAC => srcMAC,
srcIP => srcIP,
destMAC => destMAC,
destIP => destIP,
vlanEn => vlanEn,
vlanId => vlanId,
tx_ready_n => tx_ready_n,
tx_data => tx_data,
tx_vld => tx_vld,
tx_sof => tx_sof,
tx_eof => tx_eof,
igmp_data => igmp_data,
igmp_vld => igmp_vld,
igmp_sof => igmp_sof,
igmp_eof => igmp_eof,
out_enProc => out_enProc,
out_enCommand => out_enCommand
);
process
begin
dataClk <= '1';
wait for 4 ns;
dataClk <= '0';
wait for 4 ns;
end process;
process
begin
reset <= '1';
rspTime <= (others => '0');
leave <= '0';
join <= '0';
respond <= '0';
tx_ready_n <= '1';
wait for 24 ns;
reset <= '0';
join <= '1';
tx_ready_n <= '0';
wait for 8 ns;
join <= '0';
wait for 1 ms;
-- respond <= '1';
-- rspTime <= X"0A";
-- wait for 8 ns;
-- respond <= '0';
-- wait for 1 sec;
wait for 750 ns;
leave <= '1';
wait for 8 ns;
leave <= '0';
wait;
end process;
end testbench;
| gpl-2.0 | 1b2ab2df2ab14bdf930f495e16a01671 | 0.458293 | 3.923882 | false | false | false | false |
nsauzede/cpu86 | testbench/tester_behaviour.vhd | 1 | 7,824 | -------------------------------------------------------------------------------
-- --
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2005 HT-LAB --
-- --
-- Contact : mailto:[email protected] --
-- Web: http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on the CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.STD_LOGIC_UNSIGNED.all;
LIBRARY std;
USE std.TEXTIO.all;
USE work.utils.all;
ENTITY tester IS
PORT(
resoutn : IN std_logic;
CTS : OUT std_logic;
RESET : OUT std_logic;
rxenable : OUT std_logic;
CLOCK_40MHZ : BUFFER std_logic:='0';
txenable : BUFFER std_logic;
txcmd : OUT std_logic
);
END tester ;
--
ARCHITECTURE behaviour OF tester IS
constant DIVIDER_c : std_logic_vector(7 downto 0):="01000001"; -- 65, baudrate divider 40MHz
signal divtx_s : std_logic_vector(3 downto 0);
signal divreg_s : std_logic_vector(7 downto 0);
signal divcnt_s : std_logic_vector(7 downto 0);
signal rxclk16_s : std_logic;
signal tdre_s : std_logic;
signal wrn_s : std_logic;
signal char_s : std_logic_vector(7 downto 0);
component uarttx
port (
clk : in std_logic ;
enable : in std_logic ; -- 1 x bit_rate transmit clock enable
resetn : in std_logic ;
dbus : in std_logic_vector (7 downto 0); -- input to txshift register
tdre : out std_logic ;
wrn : in std_logic ;
tx : out std_logic);
end component;
BEGIN
CLOCK_40MHZ <= not CLOCK_40MHZ after 12.5 ns; -- 40MHz
process
variable L : line;
procedure write_to_uart (char_in : IN character) is
begin
char_s <=to_std_logic_vector(char_in);
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '0';
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '1';
wait until rising_edge(CLOCK_40MHZ);
wait until rising_edge(tdre_s);
end;
begin
CTS <= '1';
RESET <= '0'; -- PIN3 on Drigmorn1 connected to PIN2
wait for 100 ns;
RESET <= '1';
wrn_s <= '1'; -- Active low write strobe to TX UART
char_s <= (others => '1');
wait for 25.1 ms; -- wait for > prompt before issuing commands
write_to_uart('R');
wait for 47 ms; -- wait for > prompt before issuing commands
write_to_uart('D'); -- Issue Fill Memory command
write_to_uart('M');
write_to_uart('0');
write_to_uart('1');
write_to_uart('0');
write_to_uart('0');
wait for 1 ms;
write_to_uart('0');
write_to_uart('1');
write_to_uart('2');
write_to_uart('4');
wait for 50 ms; -- wait for > prompt before issuing commands
wait;
end process;
------------------------------------------------------------------------------
-- 8 bits divider
-- Generate rxenable clock
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resoutn) -- First divider
begin
if (resoutn='0') then
divcnt_s <= (others => '0');
rxclk16_s <= '0'; -- Receive clock (x16, pulse)
elsif (rising_edge(CLOCK_40MHZ)) then
if divcnt_s=DIVIDER_c then
divcnt_s <= (others => '0');
rxclk16_s <= '1';
else
rxclk16_s <= '0';
divcnt_s <= divcnt_s + '1';
end if;
end if;
end process;
rxenable <= rxclk16_s;
------------------------------------------------------------------------------
-- divider by 16
-- rxclk16/16=txclk
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resoutn)
begin
if (resoutn='0') then
divtx_s <= (others => '0');
elsif (rising_edge(CLOCK_40MHZ)) then
if rxclk16_s='1' then
divtx_s <= divtx_s + '1';
if divtx_s="0000" then
txenable <= '1';
end if;
else
txenable <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX Uart
------------------------------------------------------------------------------
I0 : uarttx
port map (
clk => CLOCK_40MHZ,
enable => txenable,
resetn => resoutn,
dbus => char_s,
tdre => tdre_s,
wrn => wrn_s,
tx => txcmd
);
END ARCHITECTURE behaviour;
| gpl-2.0 | b50e6cc402eb8d5a1d233720dd9df96f | 0.372955 | 5.077223 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/m_table.vhd | 3 | 6,631 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity m_table is
port ( ireg : in std_logic_vector(7 downto 0);
modrrm: in std_logic_vector(7 downto 0);
muxout: out std_logic_vector(7 downto 0));
end m_table;
architecture rtl of m_table is
signal lutout_s: std_logic_vector(1 downto 0);
signal ea_s : std_logic; -- Asserted if mod=00 and rm=110
signal m11_s : std_logic; -- Asserted if mod=11
signal mux_s : std_logic_vector(3 downto 0);
begin
ea_s <= '1' when (modrrm(7 downto 6)="00" and modrrm(2 downto 0)="110") else '0';
m11_s<= '1' when modrrm(7 downto 6)="11" else '0';
mux_s <= lutout_s & m11_s & ea_s;
process (mux_s,modrrm)
begin
case mux_s is
when "1000" => muxout <= modrrm(7 downto 6)&"000000";
when "1010" => muxout <= modrrm(7 downto 6)&"000000";
when "1001" => muxout <= "00000110";
when "1011" => muxout <= "00000110";
when "1100" => muxout <= modrrm(7 downto 3)&"000";
when "1101" => muxout <= "00"&modrrm(5 downto 3)&"110";
when "1110" => muxout <= "11"&modrrm(5 downto 3)&"000";
when others => muxout <= (others => '0');
end case;
end process;
process(ireg)
begin
case ireg is
when "11111111" => lutout_s <= "11";
when "10001000" => lutout_s <= "10";
when "10001001" => lutout_s <= "10";
when "10001010" => lutout_s <= "10";
when "10001011" => lutout_s <= "10";
when "11000110" => lutout_s <= "11";
when "11000111" => lutout_s <= "11";
when "10001110" => lutout_s <= "10";
when "10001100" => lutout_s <= "10";
when "10001111" => lutout_s <= "11";
when "10000110" => lutout_s <= "10";
when "10000111" => lutout_s <= "10";
when "10001101" => lutout_s <= "10";
when "11000101" => lutout_s <= "10";
when "11000100" => lutout_s <= "10";
when "00000000" => lutout_s <= "10";
when "00000001" => lutout_s <= "10";
when "00000010" => lutout_s <= "10";
when "00000011" => lutout_s <= "10";
when "10000000" => lutout_s <= "11";
when "10000001" => lutout_s <= "11";
when "10000011" => lutout_s <= "11";
when "00010000" => lutout_s <= "10";
when "00010001" => lutout_s <= "10";
when "00010010" => lutout_s <= "10";
when "00010011" => lutout_s <= "10";
when "00101000" => lutout_s <= "10";
when "00101001" => lutout_s <= "10";
when "00101010" => lutout_s <= "10";
when "00101011" => lutout_s <= "10";
when "00011000" => lutout_s <= "10";
when "00011001" => lutout_s <= "10";
when "00011010" => lutout_s <= "10";
when "00011011" => lutout_s <= "10";
when "11111110" => lutout_s <= "11";
when "00111010" => lutout_s <= "10";
when "00111011" => lutout_s <= "10";
when "00111000" => lutout_s <= "10";
when "00111001" => lutout_s <= "10";
when "11110110" => lutout_s <= "11";
when "11110111" => lutout_s <= "11";
when "11010000" => lutout_s <= "10";
when "11010001" => lutout_s <= "10";
when "11010010" => lutout_s <= "10";
when "11010011" => lutout_s <= "10";
when "00100000" => lutout_s <= "10";
when "00100001" => lutout_s <= "10";
when "00100010" => lutout_s <= "10";
when "00100011" => lutout_s <= "10";
when "00001000" => lutout_s <= "10";
when "00001001" => lutout_s <= "10";
when "00001010" => lutout_s <= "10";
when "00001011" => lutout_s <= "10";
when "10000100" => lutout_s <= "10";
when "10000101" => lutout_s <= "10";
when "00110000" => lutout_s <= "10";
when "00110001" => lutout_s <= "10";
when "00110010" => lutout_s <= "10";
when "00110011" => lutout_s <= "10";
when "10000010" => lutout_s <= "01";
when others => lutout_s <= "00";
end case;
end process;
end rtl; | gpl-2.0 | e225348288dd9a1c8a1aad5cc5b70ed3 | 0.448198 | 4.065604 | false | false | false | false |
VenturaSolutionsInc/VHDL | igmp/igmp_controller.vhd | 1 | 9,305 | -------------------------------------------------------------------------------
-- Title : IGMP Controller
-- Project :
-------------------------------------------------------------------------------
--! @file : igmp_controller.vhd
-- Author : Colin W. Shea
-- Company
-- Last update : 2010-03-15
-- Platform : Virtex 4/5/6
-------------------------------------------------------------------------------
--
--* @brief Control the production of the IGMP Packet
--
--! @details: This module controls and manages the IGMP packet for the join, report, and leave.
--!
--!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity igmp_controller is
generic (
gen_dataWidth : integer := 8;
simulation : boolean := false
);
port (
dataClk : in std_logic;
reset : in std_logic;
----------------------------------------------------------
join : in std_logic;
leave : in std_logic;
-- comes from igmp processor
respond : in std_logic;
-- tell the controller of gen query typoe by response time
rspTime : in std_logic_vector(7 downto 0);
---------------------------------------------------------
destIP : in std_logic_vector(31 downto 0);
destMAC : in std_logic_vector(47 downto 0);
messageSent : in std_logic;
out_join : out std_logic;
out_leave : out std_logic;
out_destMAC_o : out std_logic_vector(47 downto 0);
out_destIP_o : out std_logic_vector(31 downto 0);
-- enable processing of packets
out_enProc : out std_logic;
-- enable new commands to be accepted
out_enCommand : out std_logic
);
end igmp_controller;
architecture rtl of igmp_controller is
signal stateEn : std_logic_vector(2 downto 0) := (others => '0');
-- signal start_timer : std_logic := '0';
signal resetTimer : std_logic := '0';
signal resetOverride : std_logic := '0';
signal waitTime : std_logic_vector(7 downto 0) := (others => '0');
signal timerDone : std_logic := '0';
signal join_r : std_logic := '0';
signal join_r2 : std_logic := '0';
signal rsp_r : std_logic := '0';
signal rsp_r2 : std_logic := '0';
signal leave_r : std_logic := '0';
signal leave_r2 : std_logic := '0';
signal rspToggle : std_logic := '0';
type igmpController_type is (wait_s, join_s, respond_s, leave_s);
signal controllerState : igmpController_type := wait_s;
signal enableProcessing : std_logic := '0';
-- signal joinSignal : std_logic;
-- signal leaveSignal : std_logic;
signal destMAC_t : std_logic_vector(47 downto 0) := (others => '0');
signal destIP_t : std_logic_vector(31 downto 0) := (others => '0');
signal grpRQ : std_logic := '0';
signal brdRQ : std_logic := '0';
-- signal stateEn_r : std_logic_vector(2 downto 0);
--signal waitTime_r : std_logic_vector(7 downto 0);
signal newRsp : std_logic := '0';
begin -- trl
-- monitor input of a new request
-- i.e. the only over riding response is a leave during response
-- joins via joins ignored
register_command_input : process(dataClk, reset)
begin
if(rising_edge(dataClk))then
if(reset = '1')then
join_r <= '0';
join_r2 <= '0';
rsp_r <= '0';
rsp_r2 <= '0';
leave_r <= '0';
leave_r2 <= '0';
waitTime <= (others => '0');
-- waitTime_r <= (others => '0');
rspToggle <= '0';
stateEn <= (others => '0');
else
join_r <= join;
join_r2 <= join_r;
rsp_r <= respond;
rsp_r2 <= rsp_r;
leave_r <= leave;
leave_r2 <= leave_r;
--catch rising edges
if(join_r = '1' and join_r2 = '0')then
stateEn <= "100";
elsif(rsp_r = '1' and rsp_r2 = '0')then
stateEn <= "010";
waitTime <= rspTime;
rspToggle <= not rspToggle;
-- waitTime_r <= waitTime;
elsif(leave_r = '1' and leave_r2 = '0')then
stateEn <= "001";
elsif(messageSent = '1')then
stateEn <= "000";
else
stateEn <= stateEn;
end if;
-- stateEn_r <= stateEn;
end if;
end if;
end process;
process_input_requests : process(dataClk, reset)
begin
if(rising_edge(dataClk))then
if(reset = '1')then
resetOverride <= '0';
controllerState <= wait_s;
out_enCommand <= '0';
out_enProc <= '0';
out_join <= '0';
out_leave <= '0';
grpRQ <= '0';
brdRQ <= '0';
out_destIP_o <= (others => '0');
out_destMAC_o <= (others => '0');
destMAC_t <= (others => '0');
destIP_t <= (others => '0');
else
case controllerState is
when wait_s =>
if(stateEn = "100")then
controllerState <= join_s;
--joinSignal <= '1';
--leaveSignal <= '0';
destMAC_t <= destMAC;
destIP_t <= destIP;
out_enCommand <= '1';
out_join <= '1';
elsif(stateEn = "010")then
if(waitTime = X"0A")then
grpRQ <= '1';
elsif(waitTime = X"64")then
brdRQ <= '1';
end if;
controllerState <= respond_s;
-- if in top level simulation mode, don't wait for the timer.
-- just send the join immediately.
if simulation then
out_join <= '1';
end if;
-- joinSignal <= '1';
out_enCommand <= '1';
elsif(stateEn = "001")then
out_leave <= '1';
out_enCommand <= '0';
-- joinSignal <= '0';
-- leaveSignal <= '1';
controllerState <= leave_s;
destMAC_t <= X"01005E000002";
destIP_t <= destIP;
else
out_enCommand <= '1';
end if;
when join_s =>
out_destMAC_o <= destMAC_t;
out_destIP_o <= destIP_t;
if(messageSent = '1')then
out_enProc <= '1';
out_enCommand <= '1';
controllerState <= wait_s;
-- out_join <= '0';
else
-- out_join <= '1';
out_enProc <= '0';
out_enCommand <= '0';
controllerState <= join_s;
end if;
out_join <= '0';
when respond_s =>
if(messageSent = '1')then
grpRQ <= '0';
brdRQ <= '0';
out_enCommand <= '1';
controllerState <= wait_s;
out_join <= '0';
else
-- while we are waiting for the timer, if we get a leave,
-- suppress the keep alive and send a leave.
if(stateEn = "001")then
resetOverride <= '1';
out_leave <= '1';
controllerState <= leave_s;
destMAC_t <= X"01005E000002";
destIP_t <= destIP;
else
if (timerDone = '1')then
out_join <= '1';
else
out_join <= '0';
end if;
out_enCommand <= '0';
controllerState <= respond_s;
end if;
end if;
when leave_s =>
grpRQ <= '0';
brdRQ <= '0';
resetOverride <= '0';
if(messageSent = '1')then
out_destMAC_o <= (others => '0');
out_destIP_o <= (others => '0');
out_enProc <= '0';
out_enCommand <= '1';
controllerState <= wait_s;
-- out_leave <= '0';
else
-- out_leave <= '1';
out_destMAC_o <= destMAC_t;
out_destIP_o <= destIP_t;
out_enCommand <= '0';
controllerState <= leave_s;
out_destIP_o <= destIP_t;
out_destMAC_o <= destMAC_t;
end if;
out_leave <= '0';
-- when others => null;
end case;
end if;
end if;
end process;
resetTimer <= reset or resetOverride;
timer_generation_general : entity work.lfsr_delay
port map (
dataClk => dataClk,
reset => resetTimer,
grpRQ => grpRQ,
brdRQ => brdRQ,
done => timerDone
);
end rtl;
| gpl-2.0 | 04e8d22a849581c5867be1d76e7d305f | 0.420634 | 4.180144 | false | false | false | false |
nsauzede/cpu86 | mx_sdram/pll12to40.vhd | 1 | 18,260 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll12to40.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll12to40 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll12to40;
ARCHITECTURE SYN OF pll12to40 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire2_bv(0 DOWNTO 0) <= "0";
sub_wire2 <= To_stdlogicvector(sub_wire2_bv);
sub_wire0 <= inclk0;
sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0;
sub_wire6 <= sub_wire3(2);
sub_wire5 <= sub_wire3(1);
sub_wire4 <= sub_wire3(0);
c0 <= sub_wire4;
c1 <= sub_wire5;
c2 <= sub_wire6;
locked <= sub_wire7;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 12,
clk0_duty_cycle => 50,
clk0_multiply_by => 5,
clk0_phase_shift => "0",
clk1_divide_by => 3,
clk1_duty_cycle => 50,
clk1_multiply_by => 25,
clk1_phase_shift => "0",
clk2_divide_by => 3,
clk2_duty_cycle => 50,
clk2_multiply_by => 25,
clk2_phase_shift => "-2500",
compensate_clock => "CLK0",
inclk0_input_frequency => 83333,
intended_device_family => "MAX 10",
lpm_hint => "CBX_MODULE_PREFIX=pll12to40",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire1,
clk => sub_wire3,
locked => sub_wire7
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "5.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "5.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-90.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll12to40.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "12"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2500"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll12to40.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll12to40.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll12to40.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll12to40.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll12to40.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll12to40_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-2.0 | 7472a8fcc36904b0f9b0873d2ca2bedf | 0.701041 | 3.285946 | false | false | false | false |
nsauzede/cpu86 | papilio2_vga/drigmorn1_top.vhd | 1 | 11,745 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Toplevel : CPU86, 256Byte ROM, 16550 UART, 40K8 SRAM (all blockrams used)--
-------------------------------------------------------------------------------
-- Revision History: --
-- --
-- Date: Revision Author --
-- --
-- 30 Dec 2007 0.1 H. Tiggeler First version --
-- 17 May 2008 0.75 H. Tiggeler Updated for CPU86 ver0.75 --
-- 27 Jun 2008 0.79 H. Tiggeler Changed UART to Opencores 16750 --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY drigmorn1_top IS
PORT(
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
vramaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END drigmorn1_top ;
ARCHITECTURE struct OF drigmorn1_top IS
-- Architecture declarations
signal csromn : std_logic;
signal csesramn : std_logic;
signal csisramn : std_logic;
-- Internal signal declarations
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL abus : std_logic_vector(19 DOWNTO 0);
SIGNAL clk : std_logic;
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_esram : std_logic_vector(7 DOWNTO 0);
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL rdn : std_logic;
SIGNAL resoutn : std_logic;
SIGNAL sel_s : std_logic_vector(2 DOWNTO 0);
SIGNAL wea : std_logic_VECTOR(0 DOWNTO 0);
SIGNAL wran : std_logic;
SIGNAL wrcom : std_logic;
SIGNAL wrn : std_logic;
signal rxclk_s : std_logic;
-- Component Declarations
COMPONENT cpu86
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END COMPONENT;
-- COMPONENT blk_mem_40K
-- PORT (
-- addra : IN std_logic_VECTOR (15 DOWNTO 0);
-- clka : IN std_logic;
-- dina : IN std_logic_VECTOR (7 DOWNTO 0);
-- wea : IN std_logic_VECTOR (0 DOWNTO 0);
-- douta : OUT std_logic_VECTOR (7 DOWNTO 0)
-- );
-- END COMPONENT;
component blk_mem_40K
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END component;
COMPONENT bootstrap
PORT (
abus : IN std_logic_vector (7 DOWNTO 0);
dbus : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT uart_top
PORT (
BR_clk : IN std_logic ;
CTSn : IN std_logic := '1';
DCDn : IN std_logic := '1';
DSRn : IN std_logic := '1';
RIn : IN std_logic := '1';
abus : IN std_logic_vector (2 DOWNTO 0);
clk : IN std_logic ;
csn : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic ;
resetn : IN std_logic ;
sRX : IN std_logic ;
wrn : IN std_logic ;
B_CLK : OUT std_logic ;
DTRn : OUT std_logic ;
IRQ : OUT std_logic ;
OUT1n : OUT std_logic ;
OUT2n : OUT std_logic ;
RTSn : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
stx : OUT std_logic
);
END COMPONENT;
BEGIN
sram_addr <= '0' & abus;
---- sram_data <= dbus_.
-- dbus_esram <= sram_data;
-- sram_data <= (others => 'Z') when rdn='0' else sram_data;
-- sram_ce <= csesramn;
-- sram_we <= wrn;
-- sram_oe <= rdn;
process(csesramn,wrn,rdn,dbus_out,sram_data)
begin
sram_ce <= '1';
sram_we <= '1';
sram_oe <= '1';
sram_data <= (others => 'Z');
if csesramn='0' then
sram_ce <= '0';
if wrn='0' then
sram_data <= dbus_out;
sram_we <= '0';
else
if rdn='0' then
dbus_esram <= sram_data;
sram_oe <= '0';
end if;
end if;
end if;
end process;
-- Architecture concurrent statements
-- HDL Embedded Text Block 4 mux
-- dmux 1
process(sel_s,dbus_com1,dbus_in,dbus_rom,dbus_esram)
begin
case sel_s is
when "011" => dbus_in_cpu <= dbus_com1; -- UART
when "101" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when "110" => dbus_in_cpu <= dbus_in; -- Embedded SRAM
when others => dbus_in_cpu <= dbus_esram; -- External SRAM
end case;
end process;
-- HDL Embedded Text Block 7 clogic
clk <= CLOCK_40MHZ;
wrcom <= not wrn;
wea(0)<= not wrn;
PIN4 <= resoutn; -- For debug only
-- dbus_in_cpu multiplexer
sel_s <= cscom1 & csromn & csisramn;
-- chip_select
-- Comport, uart_16550
-- COM1, 0x3F8-0x3FF
cscom1 <= '0' when (abus(15 downto 3)="0000001111111" AND iom='1') else '1';
-- Bootstrap ROM 256 bytes
-- FFFFF-FF=FFF00
csromn <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
-- external SRAM
-- 0x5F8-0x5FF
csesramn <= '0' when (csromn='1' and csisramn='1' AND iom='0') else '1';
-- csesramn <= not (cscom1 and csromnn and csiramn);
-- internal SRAM
-- below 0x4000
csisramn <= '0' when (abus(19 downto 14)="000000" AND iom='0') else '1';
nmi <= '0';
intr <= '0';
dout <= '0';
dout1 <= '0';
DCDn <= '0';
DSRn <= '0';
RIn <= '0';
por <= NOT(PIN3);
-- Instance port mappings.
U_1 : cpu86
PORT MAP (
clk => clk,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus,
cpuerror => LED1,
dbus_out => dbus_out,
inta => OPEN,
iom => iom,
rdn => rdn,
resoutn => resoutn,
wran => wran,
wrn => wrn
);
-- U_3 : blk_mem_40K
-- PORT MAP (
-- clka => clk,
-- dina => dbus_out,
-- addra => abus(15 DOWNTO 0),
-- wea => wea,
-- douta => dbus_in
-- );
U_3 : blk_mem_40K
PORT MAP (
clka => clk,
dina => dbus_out,
addra => abus(15 DOWNTO 0),
wea => wea,
douta => dbus_in
,
clkb => clk,
dinb => (others => '0'),
addrb => vramaddr,
web => (others => '0'),
doutb => vramdata
);
U_2 : bootstrap
PORT MAP (
abus => abus(7 DOWNTO 0),
dbus => dbus_rom
);
U_0 : uart_top
PORT MAP (
BR_clk => rxclk_s,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
abus => abus(2 DOWNTO 0),
clk => clk,
csn => cscom1,
dbus_in => dbus_out,
rdn => rdn,
resetn => resoutn,
sRX => RXD,
wrn => wrn,
B_CLK => rxclk_s,
DTRn => OPEN,
IRQ => OPEN,
OUT1n => led2n,
OUT2n => led3n,
RTSn => RTS,
dbus_out => dbus_com1,
stx => TXD
);
END struct;
| gpl-2.0 | 84def705a8569b744d622b284103ddf6 | 0.448361 | 3.873681 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/regshiftmux_regshift.vhd | 3 | 14,800 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.cpu86pack.ALL;
USE work.cpu86instr.ALL;
ENTITY regshiftmux IS
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
flush_req : IN std_logic;
latchm : IN std_logic;
latcho : IN std_logic;
mux_addr : IN std_logic_vector (2 DOWNTO 0);
mux_data : IN std_logic_vector (3 DOWNTO 0);
mux_reg : IN std_logic_vector (2 DOWNTO 0);
nbreq : IN std_logic_vector (2 DOWNTO 0);
regplus1 : IN std_logic;
ldposplus1 : IN std_logic;
reset : IN std_logic;
irq : IN std_logic;
inta1 : IN std_logic; -- Added for ver 0.71
inta2_s : IN std_logic;
irq_type : IN std_logic_vector (1 DOWNTO 0);
instr : OUT instruction_type;
halt_instr : OUT std_logic;
lutbus : OUT std_logic_vector (15 DOWNTO 0);
reg1free : BUFFER std_logic;
reg1freed : BUFFER std_logic; -- Delayed version (1 clk) of reg1free
regnbok : OUT std_logic
);
END regshiftmux ;
architecture regshift of regshiftmux is
signal reg72_s : std_logic_vector(71 downto 0);
signal regcnt_s : std_logic_vector(3 downto 0); -- Note need possible 9 byte positions
signal ldpos_s : std_logic_vector(3 downto 0); -- redundant signal (=regcnt_s)
signal ireg_s : std_logic_vector(7 downto 0);
signal mod_s : std_logic_vector(1 downto 0);
signal rm_s : std_logic_vector(2 downto 0);
signal opcreg_s : std_logic_vector(2 downto 0);
signal opcdata_s: std_logic_vector(15 downto 0);
signal opcaddr_s: std_logic_vector(15 downto 0);
signal nbreq_s : std_logic_vector(2 downto 0); -- latched nbreq only for instr
signal flush_req1_s : std_logic; -- Delayed version of flush_req
signal flush_req2_s : std_logic; -- Delayed version of flush_req (address setup requires 2 clk cycle)
begin
instr.ireg <= ireg_s;
instr.xmod <= mod_s;
instr.rm <= rm_s;
instr.reg <= opcreg_s;
instr.data <= opcdata_s(7 downto 0)&opcdata_s(15 downto 8);
instr.disp <= opcaddr_s(7 downto 0)&opcaddr_s(15 downto 8);
instr.nb <= nbreq_s; -- use latched version
halt_instr <= '1' when ireg_s=HLT else '0';
-------------------------------------------------------------------------
-- reg counter (how many bytes available in pre-fetch queue)
-- ldpos (load position in queue, if MSB=1 then ignore parts of word)
-- Don't forget resource sharing during synthesis :-)
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
regcnt_s <= (others => '0'); -- wrap around after first pulse!
ldpos_s <= (others => '1');
flush_req1_s <= '0';
flush_req2_s <= '0';
elsif rising_edge(clk) then
flush_req1_s <= flush_req; -- delay 1 cycle
flush_req2_s <= flush_req1_s; -- delay 2 cycles
if flush_req2_s='1' then
regcnt_s <= (others => '0'); -- Update during Smaxws state
elsif latcho='1' then
regcnt_s <= regcnt_s - ('0'&nbreq);
elsif regplus1='1' and reg1freed='1' then
regcnt_s <= regcnt_s + '1';
end if;
if flush_req2_s='1' then
ldpos_s <= (others => '1'); -- Result in part of dbus loaded into queue
elsif latcho='1' then
ldpos_s <= ldpos_s - ('0'&nbreq);
elsif ldposplus1='1' and reg1freed='1' then
ldpos_s <= ldpos_s + '1';
end if;
end if;
end process;
reg1free <= '1' when ldpos_s/="1000" else '0'; -- Note maxcnt=9!!
process(reset,clk)
begin
if reset='1' then
reg1freed <= '1';
elsif rising_edge(clk) then
reg1freed <= reg1free;
end if;
end process;
regnbok <= '1' when (regcnt_s>='0'&nbreq) else '0'; -- regcnt must be >= nb required
lutbus <= reg72_s(71 downto 56); -- Only for opcode LUT decoder
-------------------------------------------------------------------------
-- Load 8 bits instruction into 72 bits prefetch queue (9 bytes)
-- Latched by latchm signal (from biufsm)
-- ldpos=0 means loading at 71 downto 64 etc
-- Shiftn is connected to nbreq
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
reg72_s <= NOP & X"0000000000000000"; --(others => '0');
elsif rising_edge(clk) then
if latchm='1' then
case ldpos_s is -- Load new data, shift in lsb byte first
when "0000" => reg72_s(71 downto 64) <= dbus_in;
when "0001" => reg72_s(63 downto 56) <= dbus_in;
when "0010" => reg72_s(55 downto 48) <= dbus_in;
when "0011" => reg72_s(47 downto 40) <= dbus_in;
when "0100" => reg72_s(39 downto 32) <= dbus_in;
when "0101" => reg72_s(31 downto 24) <= dbus_in;
when "0110" => reg72_s(23 downto 16) <= dbus_in;
when "0111" => reg72_s(15 downto 8) <= dbus_in;
when "1000" => reg72_s(7 downto 0) <= dbus_in;
when others => reg72_s <= reg72_s;
end case;
end if;
if latcho='1' then
case nbreq is -- remove nb byte(s) when latcho is active
when "001" => reg72_s <= reg72_s(63 downto 0) & "--------"; -- smaller synth results than "00000000"
when "010" => reg72_s <= reg72_s(55 downto 0) & "----------------";
when "011" => reg72_s <= reg72_s(47 downto 0) & "------------------------";
when "100" => reg72_s <= reg72_s(39 downto 0) & "--------------------------------";
when "101" => reg72_s <= reg72_s(31 downto 0) & "----------------------------------------";
when "110" => reg72_s <= reg72_s(23 downto 0) & "------------------------------------------------";
when others => reg72_s <= reg72_s;
end case;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- Opcode Data
-- Note format LSB-MSB
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
opcdata_s <= (others => '0');
elsif rising_edge(clk) then
if latcho='1' then
case mux_data is
when "0000" => opcdata_s <= (others => '0'); -- Correct???
when "0001" => opcdata_s <= reg72_s(63 downto 56) & X"00";
when "0010" => opcdata_s <= reg72_s(63 downto 48);
when "0011" => opcdata_s <= reg72_s(55 downto 48) & X"00";
when "0100" => opcdata_s <= reg72_s(55 downto 40);
when "0101" => opcdata_s <= reg72_s(47 downto 40) & X"00";
when "0110" => opcdata_s <= reg72_s(47 downto 32);
when "0111" => opcdata_s <= reg72_s(39 downto 32) & X"00";
when "1000" => opcdata_s <= reg72_s(39 downto 24);
when others => opcdata_s <= "----------------"; -- generate Error?
end case;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- Opcode Address/Offset/Displacement
-- Format LSB, MSB!
-- Single Displacement byte sign extended
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
opcaddr_s <= (others => '0');
elsif rising_edge(clk) then
if inta2_s='1' then
opcaddr_s <= dbus_in & X"00"; -- Read 8 bits vector
elsif latcho='1' then
--if irq='1' then
if irq='1' or inta1='1' then -- added for ver 0.71
opcaddr_s <= "000000" & irq_type & X"00";
else
case mux_addr is
when "000" => opcaddr_s <= (others => '0'); -- Correct ????
when "001" => opcaddr_s <= reg72_s(63 downto 56) & reg72_s(63)& reg72_s(63)& reg72_s(63)& reg72_s(63)&
reg72_s(63)& reg72_s(63)& reg72_s(63)& reg72_s(63); -- MSB Sign extended
when "010" => opcaddr_s <= reg72_s(63 downto 48);
when "011" => opcaddr_s <= reg72_s(55 downto 48) & reg72_s(55)& reg72_s(55)& reg72_s(55)& reg72_s(55)&
reg72_s(55)& reg72_s(55)& reg72_s(55)& reg72_s(55); -- MSB Sign Extended
when "100" => opcaddr_s <= reg72_s(55 downto 40);
when "101" => opcaddr_s <= reg72_s(63 downto 56) & X"00"; -- No sign extend, MSB=0
when "110" => opcaddr_s <= X"0300"; -- INT3 type=3
when others => opcaddr_s <= X"0400"; -- INTO type=4
end case;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- Opcode Register
-- Note : "11" is push segment reg[2]=0 reg[1..0]=reg
-- : Note reg[2]=0 if mux_reg=011
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
opcreg_s <= (others => '0');
elsif rising_edge(clk) then
if latcho='1' then
case mux_reg is
when "000" => opcreg_s <= (others => '0'); -- Correct ??
when "001" => opcreg_s <= reg72_s(61 downto 59);
when "010" => opcreg_s <= reg72_s(66 downto 64);
when "011" => opcreg_s <= '0' & reg72_s(68 downto 67); -- bit2 forced to 0
when "100" => opcreg_s <= reg72_s(58 downto 56);
when others => opcreg_s <= "---";
--assert FALSE report "**** Incorrect mux_reg in Opcode Regs Register" severity error;
end case;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- Opcode, Mod R/M Register, and latched nbreq!
-- Create fake xmod and rm if offset (addr_mux) is 1,2,5,6,7. In this case
-- there is no second opcode byte. The fake xmod and rm result in an
-- EA=Displacement.
-------------------------------------------------------------------------
process(reset,clk) -- ireg
begin
if reset='1' then
ireg_s <= NOP; -- default instr
mod_s <= (others => '0'); -- default mod
rm_s <= (others => '0'); -- default rm
nbreq_s <= "001"; -- single NOP
elsif rising_edge(clk) then
if latcho='1' then
if irq='1' or inta1='1' then -- force INT instruction, added for ver 0.71
ireg_s <= INT;
nbreq_s<= "000"; -- used in datapath to add to IP address
mod_s <= "00"; -- Fake mod (select displacement for int type
rm_s <= "110"; -- Fake rm
else
ireg_s <= reg72_s(71 downto 64);
nbreq_s<= nbreq;
if (mux_addr= "001" or mux_addr= "010" or mux_addr= "101"
or mux_addr= "110" or mux_addr= "111") then
mod_s <= "00"; -- Fake mod
rm_s <= "110"; -- Fake rm
else
mod_s <= reg72_s(63 downto 62);
rm_s <= reg72_s(58 downto 56);
end if;
end if;
end if;
end if;
end process;
end regshift;
| gpl-2.0 | c3348fa4b6f9040eccb37858a435b895 | 0.433311 | 4.060357 | false | false | false | false |
willprice/vhdl-computer | src/rtl/ff_dtype.vhd | 1 | 1,194 | ------------------------------------------------------------------------------
-- @file ff_dtype.vhd
-- @brief Implements a simple dtype flipflop
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--
-- @details On the rising edge of clk, whatever value present on data is reflected on
-- q, while its inverse is refelected on not_q.
-- if reset is high then q is put low. reset is asynchronous.
--
entity ff_dtype is
port(
clk : in std_logic;
data : in std_logic;
reset : in std_logic;
q : buffer std_logic;
not_q : buffer std_logic
);
end entity ff_dtype;
architecture rtl of ff_dtype is
begin
-- @details
-- This process is responsible for the updating of the output's q and not_q based
-- on rising edge clock events and asynchonous reset.
update_output : process(clk, reset)
begin
if(reset = '1') then
q <= '0';
not_q <= '1';
elsif (rising_edge(clk)) then
q <= data;
not_q <= not data;
else
q <= q;
not_q <= not_q;
end if;
end process;
end architecture rtl; | gpl-3.0 | 2b5d734febee09b77e9487504c57a256 | 0.515913 | 4.033784 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/multiplier_rtl.vhd | 3 | 4,121 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY multiplier IS
GENERIC(
WIDTH : integer := 16
);
PORT(
multiplicant : IN std_logic_vector (WIDTH-1 DOWNTO 0);
multiplier : IN std_logic_vector (WIDTH-1 DOWNTO 0);
product : OUT std_logic_vector (WIDTH+WIDTH-1 DOWNTO 0); -- result
twocomp : IN std_logic
);
END multiplier ;
architecture rtl of multiplier is
function rectify (r : in std_logic_vector (WIDTH-1 downto 0); -- Rectifier for signed multiplication
twoc : in std_logic) -- Signed/Unsigned
return std_logic_vector is
variable rec_v : std_logic_vector (WIDTH-1 downto 0);
begin
if ((r(WIDTH-1) and twoc)='1') then
rec_v := not(r);
else
rec_v := r;
end if;
return (rec_v + (r(WIDTH-1) and twoc));
end;
signal multiplicant_s : std_logic_vector (WIDTH-1 downto 0);
signal multiplier_s : std_logic_vector (WIDTH-1 downto 0);
signal product_s : std_logic_vector (WIDTH+WIDTH-1 downto 0); -- Result
signal sign_s : std_logic;
begin
multiplicant_s <= rectify(multiplicant,twocomp);
multiplier_s <= rectify(multiplier,twocomp);
sign_s <= multiplicant(WIDTH-1) xor multiplier(WIDTH-1); -- sign product
product_s <= multiplicant_s * multiplier_s;
product <= ((not(product_s)) + '1') when (sign_s and twocomp)='1' else product_s;
end rtl;
| gpl-2.0 | d016c8ce9478f93093af44a3364d1a78 | 0.445523 | 4.747696 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/cpu86_struct.vhd | 3 | 10,627 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.cpu86pack.ALL;
USE work.cpu86instr.ALL;
ENTITY cpu86 IS
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END cpu86 ;
ARCHITECTURE struct OF cpu86 IS
SIGNAL biu_error : std_logic;
SIGNAL clrop : std_logic;
SIGNAL dbusdp_out : std_logic_vector(15 DOWNTO 0);
SIGNAL decode_state : std_logic;
SIGNAL eabus : std_logic_vector(15 DOWNTO 0);
SIGNAL flush_ack : std_logic;
SIGNAL flush_coming : std_logic;
SIGNAL flush_req : std_logic;
SIGNAL instr : instruction_type;
SIGNAL inta1 : std_logic;
SIGNAL intack : std_logic;
SIGNAL iomem : std_logic;
SIGNAL irq_blocked : std_logic;
SIGNAL irq_req : std_logic;
SIGNAL latcho : std_logic;
SIGNAL mdbus_out : std_logic_vector(15 DOWNTO 0);
SIGNAL opc_req : std_logic;
SIGNAL path : path_in_type;
SIGNAL proc_error : std_logic;
SIGNAL read_req : std_logic;
SIGNAL reset : std_logic;
SIGNAL rw_ack : std_logic;
SIGNAL segbus : std_logic_vector(15 DOWNTO 0);
SIGNAL status : status_out_type;
SIGNAL word : std_logic;
SIGNAL write_req : std_logic;
SIGNAL wrpath : write_in_type;
-- Component Declarations
COMPONENT biu
PORT (
clk : IN std_logic ;
csbus : IN std_logic_vector (15 DOWNTO 0);
dbus_in : IN std_logic_vector (7 DOWNTO 0);
dbusdp_in : IN std_logic_vector (15 DOWNTO 0);
decode_state : IN std_logic ;
flush_coming : IN std_logic ;
flush_req : IN std_logic ;
intack : IN std_logic ;
intr : IN std_logic ;
iomem : IN std_logic ;
ipbus : IN std_logic_vector (15 DOWNTO 0);
irq_block : IN std_logic ;
nmi : IN std_logic ;
opc_req : IN std_logic ;
read_req : IN std_logic ;
reset : IN std_logic ;
status : IN status_out_type ;
word : IN std_logic ;
write_req : IN std_logic ;
abus : OUT std_logic_vector (19 DOWNTO 0);
biu_error : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
flush_ack : OUT std_logic ;
instr : OUT instruction_type ;
inta : OUT std_logic ;
inta1 : OUT std_logic ;
iom : OUT std_logic ;
irq_req : OUT std_logic ;
latcho : OUT std_logic ;
mdbus_out : OUT std_logic_vector (15 DOWNTO 0);
rdn : OUT std_logic ;
rw_ack : OUT std_logic ;
wran : OUT std_logic ;
wrn : OUT std_logic
);
END COMPONENT;
COMPONENT datapath
PORT (
clk : IN std_logic ;
clrop : IN std_logic ;
instr : IN instruction_type ;
iomem : IN std_logic ;
mdbus_in : IN std_logic_vector (15 DOWNTO 0);
path : IN path_in_type ;
reset : IN std_logic ;
wrpath : IN write_in_type ;
dbusdp_out : OUT std_logic_vector (15 DOWNTO 0);
eabus : OUT std_logic_vector (15 DOWNTO 0);
segbus : OUT std_logic_vector (15 DOWNTO 0);
status : OUT status_out_type
);
END COMPONENT;
COMPONENT proc
PORT (
clk : IN std_logic ;
flush_ack : IN std_logic ;
instr : IN instruction_type ;
inta1 : IN std_logic ;
irq_req : IN std_logic ;
latcho : IN std_logic ;
reset : IN std_logic ;
rw_ack : IN std_logic ;
status : IN status_out_type ;
clrop : OUT std_logic ;
decode_state : OUT std_logic ;
flush_coming : OUT std_logic ;
flush_req : OUT std_logic ;
intack : OUT std_logic ;
iomem : OUT std_logic ;
irq_blocked : OUT std_logic ;
opc_req : OUT std_logic ;
path : OUT path_in_type ;
proc_error : OUT std_logic ;
read_req : OUT std_logic ;
word : OUT std_logic ;
write_req : OUT std_logic ;
wrpath : OUT write_in_type
);
END COMPONENT;
BEGIN
-- synchronous reset
-- Internal use active high, external use active low
-- Async Asserted, sync negated
process (clk, por)
begin
if por='1' then
reset <= '1';
resoutn <= '0';
elsif rising_edge(clk) then
reset <= '0';
resoutn <= '1';
end if;
end process;
cpuerror <= proc_error OR biu_error;
cpubiu : biu
PORT MAP (
clk => clk,
csbus => segbus,
dbus_in => dbus_in,
dbusdp_in => dbusdp_out,
decode_state => decode_state,
flush_coming => flush_coming,
flush_req => flush_req,
intack => intack,
intr => intr,
iomem => iomem,
ipbus => eabus,
irq_block => irq_blocked,
nmi => nmi,
opc_req => opc_req,
read_req => read_req,
reset => reset,
status => status,
word => word,
write_req => write_req,
abus => abus,
biu_error => biu_error,
dbus_out => dbus_out,
flush_ack => flush_ack,
instr => instr,
inta => inta,
inta1 => inta1,
iom => iom,
irq_req => irq_req,
latcho => latcho,
mdbus_out => mdbus_out,
rdn => rdn,
rw_ack => rw_ack,
wran => wran,
wrn => wrn
);
cpudpath : datapath
PORT MAP (
clk => clk,
clrop => clrop,
instr => instr,
iomem => iomem,
mdbus_in => mdbus_out,
path => path,
reset => reset,
wrpath => wrpath,
dbusdp_out => dbusdp_out,
eabus => eabus,
segbus => segbus,
status => status
);
cpuproc : proc
PORT MAP (
clk => clk,
flush_ack => flush_ack,
instr => instr,
inta1 => inta1,
irq_req => irq_req,
latcho => latcho,
reset => reset,
rw_ack => rw_ack,
status => status,
clrop => clrop,
decode_state => decode_state,
flush_coming => flush_coming,
flush_req => flush_req,
intack => intack,
iomem => iomem,
irq_blocked => irq_blocked,
opc_req => opc_req,
path => path,
proc_error => proc_error,
read_req => read_req,
word => word,
write_req => write_req,
wrpath => wrpath
);
END struct;
| gpl-2.0 | 181ea3d8da85993b8595103e5c701774 | 0.425708 | 4.292003 | false | false | false | false |
AUT-CEIT/Arch101 | mux/mux.vhd | 1 | 934 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 26-02-2017
-- Module Name: mux.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is
port (sel : in std_logic_vector(1 downto 0);
i : in std_logic_vector(3 downto 0);
o : out std_logic);
end entity mux;
architecture beh_arch_mux of mux is
begin
with sel select
o <= i(0) when "00",
i(1) when "01",
i(2) when "10",
i(3) when "11",
'X' when others;
end architecture beh_arch_mux;
architecture seq_arch_mux of mux is
begin
process (sel)
begin
if sel = "00" then
o <= i(0);
elsif sel = "01" then
o <= i(1);
elsif sel = "10" then
o <= i(2);
elsif sel = "11" then
o <= i(3);
end if;
end process
end architecture seq_arch_mux;
| gpl-3.0 | e4271678e688bcc06ee0d2f45dae229f | 0.498929 | 3.22069 | false | false | false | false |
nsauzede/cpu86 | papilio1/kcuart_rx.vhd | 1 | 10,376 | -- Constant (K) Compact UART Receiver
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 16th October 2002
--
-- Start of design entry : 16th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for KCUART_RX
--
entity kcuart_rx is
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
data_strobe : out std_logic;
en_16_x_baud : in std_logic;
clk : in std_logic);
end kcuart_rx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for KCUART_RX
--
architecture low_level_definition of kcuart_rx is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in KCUART_RX
--
------------------------------------------------------------------------------------
--
signal sync_serial : std_logic;
signal stop_bit : std_logic;
signal data_int : std_logic_vector(7 downto 0);
signal data_delay : std_logic_vector(7 downto 0);
signal start_delay : std_logic;
signal start_bit : std_logic;
signal edge_delay : std_logic;
signal start_edge : std_logic;
signal decode_valid_char : std_logic;
signal valid_char : std_logic;
signal decode_purge : std_logic;
signal purge : std_logic;
signal valid_srl_delay : std_logic_vector(8 downto 0);
signal valid_reg_delay : std_logic_vector(8 downto 0);
signal decode_data_strobe : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of start_srl : label is "0000";
attribute INIT of edge_srl : label is "0000";
attribute INIT of valid_lut : label is "0040";
attribute INIT of purge_lut : label is "54";
attribute INIT of strobe_lut : label is "8";
--
------------------------------------------------------------------------------------
--
-- Start of KCUART_RX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- Synchronise input serial data to system clock
sync_reg: FD
port map ( D => serial_in,
Q => sync_serial,
C => clk);
stop_reg: FD
port map ( D => sync_serial,
Q => stop_bit,
C => clk);
-- Data delays to capture data at 16 time baud rate
-- Each SRL16E is followed by a flip-flop for best timing
data_loop: for i in 0 to 7 generate
begin
lsbs: if i<7 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(i+1),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate lsbs;
msb: if i=7 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => stop_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate msb;
data_reg: FDE
port map ( D => data_delay(i),
Q => data_int(i),
CE => en_16_x_baud,
C => clk);
end generate data_loop;
-- Assign internal signals to outputs
data_out <= data_int;
-- Data delays to capture start bit at 16 time baud rate
start_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(0),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => start_delay );
start_reg: FDE
port map ( D => start_delay,
Q => start_bit,
CE => en_16_x_baud,
C => clk);
-- Data delays to capture start bit leading edge at 16 time baud rate
-- Delay ensures data is captured at mid-bit position
edge_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => start_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
Q => edge_delay );
edge_reg: FDE
port map ( D => edge_delay,
Q => start_edge,
CE => en_16_x_baud,
C => clk);
-- Detect a valid character
valid_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0040")
--synthesis translate_on
port map( I0 => purge,
I1 => stop_bit,
I2 => start_edge,
I3 => edge_delay,
O => decode_valid_char );
valid_reg: FDE
port map ( D => decode_valid_char,
Q => valid_char,
CE => en_16_x_baud,
C => clk);
-- Purge of data status
purge_lut: LUT3
--synthesis translate_off
generic map (INIT => X"54")
--synthesis translate_on
port map( I0 => valid_reg_delay(8),
I1 => valid_char,
I2 => purge,
O => decode_purge );
purge_reg: FDE
port map ( D => decode_purge,
Q => purge,
CE => en_16_x_baud,
C => clk);
-- Delay of valid_char pulse of length equivalent to the time taken
-- to purge data shift register of all data which has been used.
-- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with
-- up to 16 delays and utilising the dedicated flip flop in each stage.
valid_loop: for i in 0 to 8 generate
begin
lsb: if i=0 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_char,
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate lsb;
msbs: if i>0 generate
--
attribute INIT : string;
attribute INIT of delay16_srl : label is "0000";
--
begin
delay16_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_reg_delay(i-1),
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate msbs;
data_reg: FDE
port map ( D => valid_srl_delay(i),
Q => valid_reg_delay(i),
CE => en_16_x_baud,
C => clk);
end generate valid_loop;
-- Form data strobe
strobe_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => valid_char,
I1 => en_16_x_baud,
O => decode_data_strobe );
strobe_reg: FD
port map ( D => decode_data_strobe,
Q => data_strobe,
C => clk);
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE KCUART_RX.VHD
--
------------------------------------------------------------------------------------
| gpl-2.0 | b94f00505386ab574c910b99ac4453c3 | 0.467521 | 4.162054 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/ipregister_rtl.vhd | 3 | 3,549 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY ipregister IS
PORT(
clk : IN std_logic;
ipbus : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
wrip : IN std_logic;
ipreg : OUT std_logic_vector (15 DOWNTO 0)
);
END ipregister ;
architecture rtl of ipregister is
signal ipreg_s : std_logic_vector(15 downto 0);
begin
----------------------------------------------------------------------------
-- Instructon Pointer Register
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
ipreg_s <= RESET_IP_C; -- See cpu86pack
elsif rising_edge(clk) then
if (wrip='1') then
ipreg_s<= ipbus;
end if;
end if;
end process;
ipreg <= ipreg_s;
end rtl;
| gpl-2.0 | c64275f4dc1c8a9ba524116dfab09b5f | 0.39335 | 5.219118 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/alu_rtl.vhd | 3 | 46,054 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Ver 0.82 Fixed RCR X,CL --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY ALU IS
PORT(
alu_inbusa : IN std_logic_vector (15 DOWNTO 0);
alu_inbusb : IN std_logic_vector (15 DOWNTO 0);
aluopr : IN std_logic_vector (6 DOWNTO 0);
ax_s : IN std_logic_vector (15 DOWNTO 0);
clk : IN std_logic;
cx_s : IN std_logic_vector (15 DOWNTO 0);
dx_s : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
w : IN std_logic;
wralu : IN std_logic;
wrcc : IN std_logic;
wrtemp : IN std_logic;
alubus : OUT std_logic_vector (15 DOWNTO 0);
ccbus : OUT std_logic_vector (15 DOWNTO 0);
div_err : OUT std_logic
);
END ALU ;
architecture rtl of alu is
component divider is -- Generic Divider
generic(
WIDTH_DIVID : Integer := 32; -- Width Dividend
WIDTH_DIVIS : Integer := 16; -- Width Divisor
WIDTH_SHORT : Integer := 8); -- Check Overflow against short Byte/Word
port(
clk : in std_logic; -- System Clock, not used in this architecture
reset : in std_logic; -- Active high, not used in this architecture
dividend : in std_logic_vector (WIDTH_DIVID-1 DOWNTO 0);
divisor : in std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
quotient : out std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0); -- changed to 16 bits!! (S not D)
remainder : out std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
twocomp : in std_logic; -- '1' = 2's Complement, '0' = Unsigned
w : in std_logic; -- '0'=byte, '1'=word (cpu processor)
overflow : out std_logic; -- '1' if div by 0 or overflow
start : in std_logic; -- not used in this architecture
done : out std_logic); -- not used in this architecture
end component divider;
component multiplier is -- Generic Multiplier
generic (WIDTH : integer := 16);
port (multiplicant : in std_logic_vector (WIDTH-1 downto 0);
multiplier : in std_logic_vector (WIDTH-1 downto 0);
product : out std_logic_vector (WIDTH+WIDTH-1 downto 0);-- result
twocomp : in std_logic);
end component multiplier;
signal product_s : std_logic_vector(31 downto 0); -- result multiplier
signal dividend_s : std_logic_vector(31 downto 0); -- Input divider
signal remainder_s : std_logic_vector(15 downto 0); -- Divider result
signal quotient_s : std_logic_vector(15 downto 0); -- Divider result
signal divresult_s : std_logic_vector(31 DOWNTO 0); -- Output divider to alubus
signal div_err_s : std_logic; -- Divide by 0
signal twocomp_s : std_logic; -- Sign Extend for IMUL and IDIV
signal wl_s : std_logic; -- Latched w signal, used for muliplier/divider
signal alubus_s : std_logic_vector (15 DOWNTO 0);
signal abus_s : std_logic_vector(15 downto 0);
signal bbus_s : std_logic_vector(15 downto 0);
signal dxbus_s : std_logic_vector(15 downto 0); -- DX register
signal addbbus_s : std_logic_vector(15 downto 0); -- bbus connected to full adder
signal cbus_s : std_logic_vector(16 downto 0); -- Carry Bus
signal outbus_s : std_logic_vector(15 downto 0); -- outbus=abus+bbus
signal sign16a_s : std_logic_vector(15 downto 0); -- sign extended alu_busa(7 downto 0)
signal sign16b_s : std_logic_vector(15 downto 0); -- sign extended alu_busb(7 downto 0)
signal sign32a_s : std_logic_vector(15 downto 0); -- 16 bits alu_busa(15) vector (CWD)
signal aasbus_s : std_logic_vector(15 downto 0); -- used for AAS instruction
signal aas1bus_s : std_logic_vector(15 downto 0);
signal daabus_s : std_logic_vector(7 downto 0); -- used for DAA instruction
signal dasbus_s : std_logic_vector(7 downto 0); -- used for DAS instruction
signal aaabus_s : std_logic_vector(15 downto 0); -- used for AAA instruction
signal aaa1bus_s : std_logic_vector(15 downto 0);
signal aadbus_s : std_logic_vector(15 downto 0); -- used for AAD instruction
signal aad1bus_s : std_logic_vector(10 downto 0);
signal aad2bus_s : std_logic_vector(10 downto 0);
signal setaas_s : std_logic; -- '1' set CF & AF else both 0
signal setaaa_s : std_logic; -- '1' set CF & AF else both 0
signal setdaa_s : std_logic_vector(1 downto 0); -- "11" set CF & AF
signal setdas_s : std_logic_vector(1 downto 0); -- "11" set CF & AF
signal bit4_s : std_logic; -- used for AF flag
signal cout_s : std_logic;
signal psrreg_s : std_logic_vector(15 downto 0); -- 16 bits flag register
signal zflaglow_s : std_logic; -- low byte zero flag (w=0)
signal zflaghigh_s : std_logic; -- high byte zero flag (w=1)
signal zeroflag_s : std_logic; -- zero flag, asserted when zero
signal c1flag_s : std_logic; -- Asserted when CX=1(w=1) or CL=1(w=0)
signal zflagdx_s : std_logic; -- Result (DX) zero flag, asserted when not zero (used for mul/imul)
signal zflagah_s : std_logic; -- '1' if IMUL(15..8)/=0
signal hflagah_s : std_logic; -- Used for IMUL
signal hflagdx_s : std_logic; -- Used for IMUL
signal overflow_s : std_logic;
signal parityflag_s: std_logic;
signal signflag_s : std_logic;
alias OFLAG : std_logic is psrreg_s(11);
alias DFLAG : std_logic is psrreg_s(10);
alias IFLAG : std_logic is psrreg_s(9);
alias TFLAG : std_logic is psrreg_s(8);
alias SFLAG : std_logic is psrreg_s(7);
alias ZFLAG : std_logic is psrreg_s(6);
alias AFLAG : std_logic is psrreg_s(4);
alias PFLAG : std_logic is psrreg_s(2);
alias CFLAG : std_logic is psrreg_s(0);
signal alureg_s : std_logic_vector(31 downto 0); -- 31 bits temp register for alu_inbusa & alu_inbusb
signal alucout_s : std_logic; -- ALUREG Carry Out signal
signal alu_temp_s : std_logic_vector(15 downto 0); -- Temp/scratchpad register, use ALU_TEMP to select
signal done_s : std_logic; -- Serial divider conversion done
signal startdiv_s : std_logic; -- Serial divider start pulse
begin
ALUU1 : divider
generic map (WIDTH_DIVID => 32, WIDTH_DIVIS => 16, WIDTH_SHORT => 8)
port map (clk => clk,
reset => reset,
dividend => dividend_s, -- DX:AX
divisor => alureg_s(15 downto 0), -- 0&byte/word
--divisor => bbus_s, -- byte/word
quotient => quotient_s, -- 16 bits
remainder => remainder_s, -- 16 bits
twocomp => twocomp_s,
w => wl_s, -- Byte/Word
overflow => div_err_s, -- Divider Overflow. generate int0
start => startdiv_s, -- start conversion, generated by proc
done => done_s); -- conversion done, latch results
ALUU2 : multiplier
generic map (WIDTH => 16) -- Result is 2*WIDTH bits
port map (multiplicant=> alureg_s(31 downto 16),
multiplier => alureg_s(15 downto 0),
product => product_s, -- 32 bits!
twocomp => twocomp_s);
dividend_s <= X"000000"&alureg_s(23 downto 16) when aluopr=ALU_AAM else dxbus_s & alureg_s(31 downto 16);-- DX is sign extended for byte IDIV
-- start serial divider 1 cycle after wralu pulse received. The reason is that the dividend is loaded into the
-- accumulator thus the data must be valid when this happens.
process (clk, reset)
begin
if reset='1' then
startdiv_s <= '0';
elsif rising_edge(clk) then
if (wralu='1' and (aluopr=ALU_DIV or aluopr=ALU_IDIV OR aluopr=ALU_AAM)) then
startdiv_s <= '1';
else
startdiv_s <= '0';
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Create Full adder
----------------------------------------------------------------------------
fulladd: for bit_nr in 0 to 15 generate
outbus_s(bit_nr) <= abus_s(bit_nr) xor addbbus_s(bit_nr) xor cbus_s(bit_nr);
cbus_s(bit_nr+1) <= (abus_s(bit_nr) and addbbus_s(bit_nr)) or
(abus_s(bit_nr) and cbus_s(bit_nr)) or
(addbbus_s(bit_nr) and cbus_s(bit_nr));
end generate fulladd;
bit4_s <= cbus_s(4);
sign16a_s <= alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7)&alu_inbusa(7)&
alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7 downto 0);
sign16b_s <= alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7)&alu_inbusb(7)&
alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7 downto 0);
sign32a_s <= alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15);
-- Invert bus for subtract instructions
addbbus_s <= not bbus_s when ((aluopr=ALU_CMP) or (aluopr=ALU_CMP_SE) or (aluopr=ALU_CMPS) or (aluopr=ALU_DEC)
or (aluopr=ALU_SBB) or (aluopr=ALU_SBB_SE) or (aluopr=ALU_PUSH) or (aluopr=ALU_SUB)
or (aluopr=ALU_SUB_SE) or (aluopr=ALU_SCAS)) else bbus_s;
-- sign extend for IDIV and IMUL instructions
twocomp_s <= '1' when ((aluopr=ALU_IDIV) or (aluopr=ALU_IMUL) or
(aluopr=ALU_IDIV2)or (aluopr=ALU_IMUL2)) else '0';
----------------------------------------------------------------------------
-- Sign Extend Logic abus & bbus & dxbus
----------------------------------------------------------------------------
process (w, alu_inbusa, alu_inbusb, sign16a_s, sign16b_s, aluopr, ax_s, alureg_s)
begin
if (w='1') then -- Word, no sign extend, unless signextend is specified
case aluopr is
when ALU_CMPS =>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= alureg_s(15 downto 0); -- previous read ES:[DI]
when ALU_NEG | ALU_NOT =>
abus_s <= not(alu_inbusa); -- NEG instruction, not(operand)+1
bbus_s <= alu_inbusb; -- 0001 (0000 for NOT)
when ALU_ADD_SE | ALU_ADC_SE | ALU_SBB_SE | ALU_SUB_SE | ALU_CMP_SE |
ALU_OR_SE | ALU_AND_SE | ALU_XOR_SE=>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= sign16b_s; -- Sign extend on 8 bits immediate values (see O80I2RM)
when others =>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= alu_inbusb;
end case;
else
case aluopr is
when ALU_CMPS =>
abus_s <= alu_inbusa;
bbus_s <= alureg_s(15 downto 0);
when ALU_DIV | ALU_DIV2 =>
abus_s <= ax_s;
bbus_s <= alu_inbusb;
when ALU_IDIV| ALU_IDIV2 =>
abus_s <= ax_s;
bbus_s <= sign16b_s;
when ALU_MUL | ALU_MUL2 | ALU_SCAS =>
abus_s <= alu_inbusa;
bbus_s <= alu_inbusb;
when ALU_NEG | ALU_NOT =>
abus_s <= not(alu_inbusa); -- NEG instruction, not(operand)+1
bbus_s <= alu_inbusb; -- 0001 (0000 for NOT)
when others =>
abus_s <= sign16a_s;
bbus_s <= sign16b_s;
end case;
end if;
end process;
process (wl_s, aluopr, dx_s, alu_inbusa) -- dxbus for DIV/IDIV only
begin
if (wl_s='1') then -- Word, no sign extend
dxbus_s <= dx_s;
else -- Byte
if (((aluopr=ALU_IDIV) or (aluopr=ALU_IDIV2)) and (alu_inbusa(15)='1')) then -- signed DX<-SE(AX)/bbus<-SE(byte)
dxbus_s <= X"FFFF"; -- DX=FFFF (ignored for mul)
else
dxbus_s <= X"0000"; -- DX=0000 (ignored for mul)
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Carry In logic
----------------------------------------------------------------------------
process (aluopr, psrreg_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_INC | ALU_POP | ALU_NEG | ALU_NOT
=> cbus_s(0) <= '0';
when ALU_SBB | ALU_SBB_SE
=> cbus_s(0) <= not CFLAG;
when ALU_SUB | ALU_SUB_SE | ALU_DEC | ALU_PUSH | ALU_CMP | ALU_CMP_SE
| ALU_CMPS | ALU_SCAS
=> cbus_s(0) <= '1';
when others => cbus_s(0) <= CFLAG; -- ALU_ADC, ALU_SUB, ALU_SBB
end case;
end process;
----------------------------------------------------------------------------
-- Carry Out logic
-- cout is inverted for ALU_SUB and ALU_SBB before written to psrreg_s
----------------------------------------------------------------------------
process (aluopr, w, psrreg_s, cbus_s, alu_inbusa)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_SUB | ALU_SUB_SE | ALU_SBB | ALU_SBB_SE |
ALU_CMP | ALU_CMP_SE | ALU_CMPS| ALU_SCAS =>
if (w='1') then cout_s <= cbus_s(16);
else cout_s <= cbus_s(8);
end if;
when ALU_NEG => -- CF=0 if operand=0, else 1
if (alu_inbusa=X"0000") then
cout_s <= '1'; -- Note CFLAG=NOT(cout_s)
else
cout_s <= '0'; -- Note CFLAG=NOT(cout_s)
end if;
when others =>
cout_s <= CFLAG; -- Keep previous value
end case;
end process;
----------------------------------------------------------------------------
-- Overflow Logic
----------------------------------------------------------------------------
process (aluopr, w, psrreg_s, cbus_s, alureg_s, alucout_s, zflaghigh_s, zflagdx_s,hflagdx_s,zflagah_s,
hflagah_s, wl_s, product_s, c1flag_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_INC | ALU_DEC | ALU_SUB | ALU_SUB_SE |
ALU_SBB | ALU_SBB_SE | ALU_CMP | ALU_CMP_SE | ALU_CMPS | ALU_SCAS | ALU_NEG =>
if w='1' then -- 16 bits
overflow_s <= cbus_s(16) xor cbus_s(15);
else
overflow_s <= cbus_s(8) xor cbus_s(7);
end if;
when ALU_ROL1 | ALU_RCL1 | ALU_SHL1 => -- count=1 using constants as in rcl bx,1
if (((w='1') and (alureg_s(15)/=alucout_s)) or
((w='0') and (alureg_s(7) /=alucout_s))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROL | ALU_RCL | ALU_SHL => -- cl/cx=1
if (( c1flag_s='1' and w='1' and (alureg_s(15)/=alucout_s)) or
( c1flag_s='1' and w='0' and (alureg_s(7) /=alucout_s))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROR1 | ALU_RCR1 | ALU_SHR1 | ALU_SAR1 =>
if (((w='1') and (alureg_s(15)/=alureg_s(14))) or
((w='0') and (alureg_s(7) /=alureg_s(6)))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROR | ALU_RCR | ALU_SHR | ALU_SAR => -- if cl/cx=1
if ((c1flag_s='1' and w='1' and (alureg_s(15)/=alureg_s(14))) or
(c1flag_s='1' and w='0' and (alureg_s(7) /=alureg_s(6)))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_MUL | ALU_MUL2 =>
if (wl_s='0') then
overflow_s <= zflaghigh_s;
else
overflow_s <= zflagdx_s; -- MSW multiply/divide result
end if;
when ALU_IMUL | ALU_IMUL2 => -- if MSbit(1)='1' & AH=FF/DX=FFFF
if ((wl_s='0' and product_s(7)='1' and hflagah_s='1') or
(wl_s='0' and product_s(7)='0' and zflagah_s='0') or
(wl_s='1' and product_s(15)='1' and hflagdx_s='1') or
(wl_s='1' and product_s(15)='0' and zflagdx_s='0')) then
overflow_s <= '0';
else
overflow_s <= '1';
end if;
when others =>
overflow_s <= OFLAG; -- Keep previous value
end case;
end process;
----------------------------------------------------------------------------
-- Zeroflag set if result=0, zflagdx_s=1 when dx/=0, zflagah_s=1 when ah/=0
----------------------------------------------------------------------------
zflaglow_s <= alubus_s(7) or alubus_s(6) or alubus_s(5) or alubus_s(4) or
alubus_s(3) or alubus_s(2) or alubus_s(1) or alubus_s(0);
zflaghigh_s <= alubus_s(15) or alubus_s(14) or alubus_s(13) or alubus_s(12) or
alubus_s(11) or alubus_s(10) or alubus_s(9) or alubus_s(8);
zeroflag_s <= not(zflaghigh_s or zflaglow_s) when w='1' else not(zflaglow_s);
zflagdx_s <= product_s(31) or product_s(30) or product_s(29) or product_s(28) or
product_s(27) or product_s(26) or product_s(25) or product_s(24) or
product_s(23) or product_s(22) or product_s(21) or product_s(20) or
product_s(19) or product_s(18) or product_s(17) or product_s(16);
zflagah_s <= product_s(15) or product_s(14) or product_s(13) or product_s(12) or
product_s(11) or product_s(10) or product_s(09) or product_s(08);
----------------------------------------------------------------------------
-- hflag set if IMUL result AH=FF or DX=FFFF
----------------------------------------------------------------------------
hflagah_s <= product_s(15) and product_s(14) and product_s(13) and product_s(12) and
product_s(11) and product_s(10) and product_s(9) and product_s(8);
hflagdx_s <= product_s(31) and product_s(30) and product_s(29) and product_s(28) and
product_s(27) and product_s(26) and product_s(25) and product_s(24) and
product_s(23) and product_s(22) and product_s(21) and product_s(20) and
product_s(19) and product_s(18) and product_s(17) and product_s(16);
----------------------------------------------------------------------------
-- Parity flag set if even number of bits in LSB
----------------------------------------------------------------------------
parityflag_s <=not(alubus_s(7) xor alubus_s(6) xor alubus_s(5) xor alubus_s(4) xor
alubus_s(3) xor alubus_s(2) xor alubus_s(1) xor alubus_s(0));
----------------------------------------------------------------------------
-- Sign flag
----------------------------------------------------------------------------
signflag_s <= alubus_s(15) when w='1' else alubus_s(7);
----------------------------------------------------------------------------
-- c1flag asserted if CL or CX=1, used to update the OF flags during
-- rotate/shift instructions
----------------------------------------------------------------------------
c1flag_s <= '1' when (cx_s=X"0001" and w='1') OR (cx_s(7 downto 0)=X"01" and w='0') else '0';
----------------------------------------------------------------------------
-- Temp/ScratchPad Register
-- alureg_s can also be used as temp storage
-- temp<=bbus;
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
alu_temp_s<= (others => '0');
elsif rising_edge(clk) then
if (wrtemp='1') then
alu_temp_s <= bbus_s;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- ALU Register used for xchg and rotate/shift instruction
-- latch Carry Out alucout_s signal
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
alureg_s <= (others => '0');
alucout_s<= '0';
wl_s <= '0';
elsif rising_edge(clk) then
if (wralu='1') then
alureg_s(31 downto 16) <= abus_s; -- alu_inbusa;
wl_s <= w; -- Latched w version
if w='1' then -- word operation
case aluopr is
when ALU_ROL | ALU_ROL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & alureg_s(15);
alucout_s<= alureg_s(15);
when ALU_ROR | ALU_ROR1 => alureg_s(15 downto 0) <= alureg_s(0) & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_RCL | ALU_RCL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & alucout_s; -- shift carry in
alucout_s<= alureg_s(15);
when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_SHL | ALU_SHL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & '0';
alucout_s<= alureg_s(15);
when ALU_SHR | ALU_SHR1 => alureg_s(15 downto 0) <= '0' & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_SAR | ALU_SAR1 => alureg_s(15 downto 0) <= alureg_s(15) & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_TEMP => alureg_s(15 downto 0) <= bbus_s;
alucout_s<= '-'; -- Don't care!
when ALU_AAM => alureg_s(15 downto 0) <= X"000A";
alucout_s<= '-'; -- Don't care!
when others => alureg_s(15 downto 0) <= bbus_s ;--alu_inbusb; -- ALU_PASSB
alucout_s<= CFLAG;
end case;
else
case aluopr is -- To aid resource sharing add MSB byte as above
when ALU_ROL | ALU_ROL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & alureg_s(7));
alucout_s<= alureg_s(7);
when ALU_ROR | ALU_ROR1 => alureg_s(15 downto 0) <= alureg_s(0) & alureg_s(15 downto 9) & (alureg_s(0) & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_RCL | ALU_RCL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & alucout_s); -- shift carry in
alucout_s<= alureg_s(7);
-- when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 9) & (psrreg_s(0) & alureg_s(7 downto 1));
when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 9) & (alucout_s & alureg_s(7 downto 1)); -- Ver 0.82
alucout_s<= alureg_s(0);
when ALU_SHL | ALU_SHL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & '0');
alucout_s<= alureg_s(7);
when ALU_SHR | ALU_SHR1 => alureg_s(15 downto 0) <= '0' & alureg_s(15 downto 9) & ('0' & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_SAR | ALU_SAR1 => alureg_s(15 downto 0) <= alureg_s(15) & alureg_s(15 downto 9)& (alureg_s(7) & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_TEMP => alureg_s(15 downto 0) <= bbus_s;
alucout_s<= '-'; -- Don't care!
when ALU_AAM => alureg_s(15 downto 0) <= X"000A";
alucout_s<= '-'; -- Don't care!
when others => alureg_s(15 downto 0) <= bbus_s ;--alu_inbusb -- ALU_PASSB
alucout_s<= CFLAG;
end case;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- AAS Instruction 3F
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,aas1bus_s)
begin
aas1bus_s<=alu_inbusa-X"0106";
if ((alu_inbusa(3 downto 0) > "1001") or (psrreg_s(4)='1')) then
aasbus_s <= aas1bus_s(15 downto 8)&X"0"&aas1bus_s(3 downto 0);
setaas_s <= '1'; -- Set CF and AF flag
else
aasbus_s(7 downto 0) <= X"0"&(alu_inbusa(3 downto 0)); -- AL=AL&0Fh
aasbus_s(15 downto 8)<= alu_inbusa(15 downto 8); -- leave AH unchanged
setaas_s <= '0'; -- Clear CF and AF flag
end if;
end process;
----------------------------------------------------------------------------
-- AAA Instruction 37
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,aaa1bus_s)
begin
aaa1bus_s<=alu_inbusa+X"0106";
if ((alu_inbusa(3 downto 0) > "1001") or (psrreg_s(4)='1')) then
aaabus_s <= aaa1bus_s(15 downto 8)&X"0"&aaa1bus_s(3 downto 0);
setaaa_s <= '1'; -- Set CF and AF flag
else
aaabus_s(7 downto 0) <= X"0"&alu_inbusa(3 downto 0); -- AL=AL&0Fh
aaabus_s(15 downto 8)<= alu_inbusa(15 downto 8); -- AH Unchanged
setaaa_s <= '0'; -- Clear CF and AF flag
end if;
end process;
----------------------------------------------------------------------------
-- DAA Instruction 27
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,setdaa_s)
begin
if ((alu_inbusa(3 downto 0) > X"9") or (psrreg_s(4)='1')) then
setdaa_s(0) <= '1'; -- set AF
else
setdaa_s(0) <= '0'; -- clr AF
end if;
if ((alu_inbusa(7 downto 0) > X"9F") or (psrreg_s(0)='1') or (alu_inbusa(7 downto 0) > X"99")) then
setdaa_s(1) <= '1'; -- set CF
else
setdaa_s(1) <= '0'; -- clr CF
end if;
case setdaa_s is
when "00" => daabus_s <= alu_inbusa(7 downto 0);
when "01" => daabus_s <= alu_inbusa(7 downto 0) + X"06";
when "10" => daabus_s <= alu_inbusa(7 downto 0) + X"60";
when others => daabus_s <= alu_inbusa(7 downto 0) + X"66";
end case;
end process;
----------------------------------------------------------------------------
-- DAS Instruction 2F
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,setdas_s)
begin
if ((alu_inbusa(3 downto 0) > X"9") or (psrreg_s(4)='1')) then
setdas_s(0) <= '1'; -- set AF
else
setdas_s(0) <= '0'; -- clr AF
end if;
if ((alu_inbusa(7 downto 0) > X"9F") or (psrreg_s(0)='1') or (alu_inbusa(7 downto 0) > X"99")) then
setdas_s(1) <= '1'; -- set CF
else
setdas_s(1) <= '0'; -- clr CF
end if;
case setdas_s is
when "00" => dasbus_s <= alu_inbusa(7 downto 0);
when "01" => dasbus_s <= alu_inbusa(7 downto 0) - X"06";
when "10" => dasbus_s <= alu_inbusa(7 downto 0) - X"60";
when others => dasbus_s <= alu_inbusa(7 downto 0) - X"66";
end case;
end process;
----------------------------------------------------------------------------
-- AAD Instruction 5D 0A
----------------------------------------------------------------------------
process (alu_inbusa,aad1bus_s,aad2bus_s)
begin
aad1bus_s <= ("00" & alu_inbusa(15 downto 8) & '0') + (alu_inbusa(15 downto 8) & "000"); -- AH*2 + AH*8
aad2bus_s <= aad1bus_s + ("000" & alu_inbusa(7 downto 0)); -- + AL
aadbus_s<= "00000000" & aad2bus_s(7 downto 0);
end process;
----------------------------------------------------------------------------
-- ALU Operation
----------------------------------------------------------------------------
process (aluopr,abus_s,bbus_s,outbus_s,psrreg_s,alureg_s,aasbus_s,aaabus_s,daabus_s,sign16a_s,
sign16b_s,sign32a_s,dasbus_s,product_s,divresult_s,alu_temp_s,aadbus_s,quotient_s,remainder_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_INC | ALU_POP | ALU_SUB | ALU_SUB_SE | ALU_DEC | ALU_PUSH | ALU_CMP | ALU_CMP_SE |
ALU_CMPS | ALU_ADC | ALU_ADC_SE | ALU_SBB | ALU_SBB_SE | ALU_SCAS | ALU_NEG | ALU_NOT
=> alubus_s <= outbus_s;
when ALU_OR | ALU_OR_SE
=> alubus_s <= abus_s OR bbus_s;
when ALU_AND | ALU_AND_SE | ALU_TEST0 | ALU_TEST1 | ALU_TEST2
=> alubus_s <= abus_s AND bbus_s;
when ALU_XOR | ALU_XOR_SE
=> alubus_s <= abus_s XOR bbus_s;
when ALU_LAHF => alubus_s <= psrreg_s(15 downto 2)&'1'&psrreg_s(0);-- flags onto ALUBUS, note reserved bit1=1
when ALU_MUL | ALU_IMUL
=> alubus_s <= product_s(15 downto 0); -- AX of Multiplier
when ALU_MUL2| ALU_IMUL2
=> alubus_s <= product_s(31 downto 16); -- DX of Multiplier
when ALU_DIV | ALU_IDIV
=> alubus_s <= divresult_s(15 downto 0);-- AX of Divider (quotient)
when ALU_DIV2| ALU_IDIV2
=> alubus_s <= divresult_s(31 downto 16);-- DX of Divider (remainder)
when ALU_SEXT => alubus_s <= sign16a_s; -- Used for CBW Instruction
when ALU_SEXTW => alubus_s <= sign32a_s; -- Used for CWD Instruction
when ALU_AAS => alubus_s <= aasbus_s; -- Used for AAS Instruction
when ALU_AAA => alubus_s <= aaabus_s; -- Used for AAA Instruction
when ALU_DAA => alubus_s <= abus_s(15 downto 8) & daabus_s;-- Used for DAA Instruction
when ALU_DAS => alubus_s <= abus_s(15 downto 8) & dasbus_s;-- Used for DAS Instruction
when ALU_AAD => alubus_s <= aadbus_s; -- Used for AAD Instruction
when ALU_AAM => alubus_s <= quotient_s(7 downto 0) & remainder_s(7 downto 0); -- Used for AAM Instruction
when ALU_ROL | ALU_ROL1 | ALU_ROR | ALU_ROR1 | ALU_RCL | ALU_RCL1 | ALU_RCR | ALU_RCR1 |
ALU_SHL | ALU_SHL1 | ALU_SHR | ALU_SHR1 | ALU_SAR | ALU_SAR1 | ALU_REGL
=> alubus_s <= alureg_s(15 downto 0); -- alu_inbusb to output
when ALU_REGH => alubus_s <= alureg_s(31 downto 16); -- alu_inbusa to output
when ALU_PASSA => alubus_s <= abus_s;
--when ALU_PASSB => alubus_s <= bbus_s;
when ALU_TEMP => alubus_s <= alu_temp_s;
when others => alubus_s <= DONTCARE(15 downto 0);
end case;
end process;
alubus <= alubus_s; -- Connect to entity
----------------------------------------------------------------------------
-- Processor Status Register (Flags)
-- bit Flag
-- 15 Reserved
-- 14 Reserved
-- 13 Reserved Set to 1?
-- 12 Reserved Set to 1?
-- 11 Overflow Flag OF
-- 10 Direction Flag DF
-- 9 Interrupt Flag IF
-- 8 Trace Flag TF
-- 7 Sign Flag SF
-- 6 Zero Flag ZF
-- 5 Reserved
-- 4 Auxiliary Carry AF
-- 3 Reserved
-- 2 Parity Flag PF
-- 1 Reserved Set to 1 ????
-- 0 Carry Flag
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
psrreg_s <= "1111000000000010";
elsif rising_edge(clk) then
if (wrcc='1') then
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_INC =>
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= bit4_s;
PFLAG <= parityflag_s;
CFLAG <= cout_s;
when ALU_DEC => -- Same as for ALU_SUB exclusing the CFLAG :-(
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= not bit4_s;
PFLAG <= parityflag_s;
when ALU_SUB | ALU_SUB_SE | ALU_SBB | ALU_SBB_SE | ALU_CMP |
ALU_CMP_SE | ALU_CMPS | ALU_SCAS | ALU_NEG =>
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= not bit4_s;
PFLAG <= parityflag_s;
CFLAG <= not cout_s;
when ALU_OR | ALU_OR_SE | ALU_AND | ALU_AND_SE | ALU_XOR | ALU_XOR_SE | ALU_TEST0 | ALU_TEST1 | ALU_TEST2 =>
OFLAG <= '0';
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= '0'; -- None defined, set to 0 to be compatible with debug
PFLAG <= parityflag_s;
CFLAG <= '0';
when ALU_SHL | ALU_SHR | ALU_SAR |
ALU_SHR1 | ALU_SAR1 | ALU_SHL1 =>
OFLAG <= overflow_s;
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
CFLAG <= alucout_s;
when ALU_CLC =>
CFLAG <= '0';
when ALU_CMC =>
CFLAG <= not CFLAG;
when ALU_STC =>
CFLAG <= '1';
when ALU_CLD =>
DFLAG <= '0';
when ALU_STD =>
DFLAG <= '1';
when ALU_CLI =>
IFLAG <= '0';
when ALU_STI =>
IFLAG <= '1';
when ALU_POP => -- Note only POPF executes a WRCC command, thus save for other pops
psrreg_s <= "1111" & alu_inbusa(11 downto 0);
when ALU_SAHF => -- Write all AH bits (not compatible!)
psrreg_s(7 downto 0) <= alu_inbusa(7 downto 6) & '0' & alu_inbusa(4) & '0' &
alu_inbusa(2) & '0' & alu_inbusa(0);-- SAHF only writes bits 7,6,4,2,0
when ALU_AAS =>
AFLAG <= setaas_s; -- set or clear CF/AF flag
CFLAG <= setaas_s;
SFLAG <= '0';
when ALU_AAA =>
AFLAG <= setaaa_s; -- set or clear CF/AF flag
CFLAG <= setaaa_s;
when ALU_DAA =>
AFLAG <= setdaa_s(0); -- set or clear CF/AF flag
CFLAG <= setdaa_s(1);
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
when ALU_AAD =>
SFLAG <= alubus_s(7); --signflag_s;
PFLAG <= parityflag_s;
ZFLAG <= zeroflag_s;
when ALU_AAM =>
SFLAG <= signflag_s;
PFLAG <= parityflag_s;
ZFLAG <= not(zflaglow_s); -- signflag on AL only
when ALU_DAS =>
AFLAG <= setdas_s(0); -- set or clear CF/AF flag
CFLAG <= setdas_s(1);
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
-- Shift Rotate Instructions
when ALU_ROL | ALU_ROR | ALU_RCL | ALU_RCR |
ALU_ROL1 | ALU_RCL1 | ALU_ROR1 | ALU_RCR1 =>
CFLAG <= alucout_s;
OFLAG <= overflow_s;
when ALU_MUL | ALU_MUL2 | ALU_IMUL | ALU_IMUL2 => -- Multiply affects CF&OF only
CFLAG <= overflow_s;
OFLAG <= overflow_s;
when ALU_CLRTIF => -- Clear TF and IF flag
IFLAG <= '0';
TFLAG <= '0';
when others =>
psrreg_s <= psrreg_s;
end case;
end if;
end if;
end process;
ccbus <= psrreg_s; -- Connect to entity
-- Latch Divide by 0 error flag & latched divresult.
-- Requires a MCP from all registers to these endpoint registers!
process (clk, reset)
begin
if reset='1' then
div_err <= '0';
divresult_s <= (others => '0');
elsif rising_edge(clk) then
if done_s='1' then -- Latched pulse generated by serial divider
div_err <= div_err_s; -- Divide Overflow
-- pragma synthesis_off
assert div_err_s='0' report "**** Divide Overflow ***" severity note;
-- pragma synthesis_on
if wl_s='1' then -- Latched version required?
divresult_s <= remainder_s & quotient_s;
else
divresult_s <= remainder_s & remainder_s(7 downto 0) & quotient_s(7 downto 0);
end if;
else
div_err <= '0';
end if;
end if;
end process;
end rtl;
| gpl-2.0 | 9a9796e72ced377d70e0c1d04eb0a141 | 0.404569 | 4.185586 | false | false | false | false |
hacklabmikkeli/knobs-galore | phase_distort.vhdl | 2 | 6,530 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.common.all;
entity phase_distort is
port (EN: in std_logic
;CLK_EVEN: in std_logic
;CLK_ODD: in std_logic
;WAVEFORM: in waveform_t
;CUTOFF: in ctl_signal
;THETA_IN: in ctl_signal
;THETA_OUT: out ctl_signal
;GAIN_IN: in ctl_signal
;GAIN_THRU: out ctl_signal
)
;
end entity;
architecture phase_distort_impl of phase_distort is
function transfer_saw
(cutoff: integer
;x: integer
)
return integer is
variable log_cutoff : integer;
variable y0 : integer;
variable y : integer;
variable k : integer;
begin
log_cutoff := integer(log2(real(cutoff+1)) * 32.0);
if log_cutoff > 255 then
log_cutoff := 255;
end if;
k := (ctl_max - log_cutoff) / 2;
y0 := (ctl_max / 2) - k;
if x < k then
y := (x * y0) / k;
else
y := y0 - ((x-k) * y0) / (ctl_max - k);
end if;
y := y + x;
if y > ctl_max - 1 then
return ctl_max - 1;
else
return y;
end if;
end function;
function transfer_sq
(cutoff: integer
;x: integer
)
return integer is
variable log_cutoff : integer;
variable k : integer;
variable y0 : integer;
variable y : integer;
begin
log_cutoff := integer(log2(real(cutoff+1)) * 32.0);
if log_cutoff > 255 then
log_cutoff := 255;
end if;
k := (ctl_max - log_cutoff) / 4;
y0 := ctl_max / 4;
if x < k then
y := (x * y0) / k;
elsif x < (ctl_max / 2) - k then
y := y0;
elsif x < (ctl_max / 2) + k then
y := y0 + (x + k - (ctl_max / 2)) * y0 / k;
elsif x < ctl_max - k then
y := (ctl_max / 2) + y0;
else
y := (ctl_max / 2) + y0 + (x + k - ctl_max) * y0 / k;
end if;
if y > ctl_max - 1 then
return ctl_max - 1;
else
return y;
end if;
end function;
function make_lut_saw return ctl_lut_t is
variable result : ctl_lut_t;
begin
for j in ctl_lut_t'low(1) to ctl_lut_t'high(1) loop
for i in ctl_lut_t'low(2) to ctl_lut_t'high(2) loop
result(j,i) := to_unsigned(transfer_saw(i*16, j),ctl_bits);
end loop;
end loop;
return result;
end function;
function make_lut_sq return ctl_lut_t is
variable result : ctl_lut_t;
begin
for j in ctl_lut_t'low(1) to ctl_lut_t'high(1) loop
for i in ctl_lut_t'low(2) to ctl_lut_t'high(2) loop
result(j,i) := to_unsigned(transfer_sq(i*16, j),ctl_bits);
end loop;
end loop;
return result;
end function;
constant lut_saw: ctl_lut_t := make_lut_saw;
constant lut_sq: ctl_lut_t := make_lut_sq;
constant zero: ctl_signal := (others => '0');
signal s1_waveform: waveform_t := waveform_saw;
signal s1_gain: ctl_signal := (others => '0');
signal s2_waveform: waveform_t := waveform_saw;
signal s2_gain: ctl_signal := (others => '0');
signal s3_waveform: waveform_t := waveform_saw;
signal s3_theta_saw: ctl_signal;
signal s3_theta_sq: ctl_signal;
signal s3_gain: ctl_signal := (others => '0');
signal s4_theta_out_buf: ctl_signal := (others => '0');
signal s4_gain_pass_buf: ctl_signal := (others => '0');
signal s5_theta_out_buf: ctl_signal := (others => '0');
signal s5_gain_pass_buf: ctl_signal := (others => '0');
begin
lookup_saw:
entity
work.lookup(lookup_impl)
generic map
(lut_saw)
port map
(EN
,CLK_EVEN
,CLK_ODD
,THETA_IN
,CUTOFF
,s3_theta_saw
);
lookup_sq:
entity
work.lookup(lookup_impl)
generic map
(lut_sq)
port map
(EN
,CLK_EVEN
,CLK_ODD
,THETA_IN
,CUTOFF
,s3_theta_sq
);
process (CLK_EVEN)
begin
if EN = '1' and rising_edge(CLK_EVEN) then
s1_waveform <= WAVEFORM;
s1_gain <= GAIN_IN;
end if;
end process;
process (CLK_ODD)
begin
if EN = '1' and rising_edge(CLK_ODD) then
s2_waveform <= s1_waveform;
s2_gain <= s1_gain;
end if;
end process;
process (CLK_EVEN)
begin
if EN = '1' and rising_edge(CLK_EVEN) then
s3_waveform <= s2_waveform;
s3_gain <= s2_gain;
end if;
end process;
process (CLK_ODD)
begin
if EN = '1' and rising_edge(CLK_ODD) then
case s3_waveform is
when waveform_saw =>
s4_theta_out_buf <= s3_theta_saw;
when waveform_sq =>
s4_theta_out_buf <= s3_theta_sq;
when others =>
s4_theta_out_buf <= (others => '0');
end case;
s4_gain_pass_buf <= s3_gain;
end if;
end process;
process (CLK_EVEN)
begin
if EN = '1' and rising_edge(CLK_EVEN) then
s5_theta_out_buf <= s4_theta_out_buf;
s5_gain_pass_buf <= s4_gain_pass_buf;
end if;
end process;
THETA_OUT <= s5_theta_out_buf;
GAIN_THRU <= s5_gain_pass_buf;
end architecture;
| gpl-3.0 | 2d21ee41ecd01bddfd216310b41fdb53 | 0.511639 | 3.482667 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_Trivium/trivium.vhd | 1 | 5,119 | --This software is provided 'as-is', without any express or implied warranty.
--In no event will the authors be held liable for any damages arising from the use of this software.
--
--Permission is granted to anyone to use this software for any purpose,
--excluding commercial applications, and to alter it and redistribute
--it freely except for commercial applications.
--File: trivium.vhd
--Original Author: Richard Stern ([email protected])
--Author : Kyle D. Williams ([email protected])
--Organization: Polytechnic University
--------------------------------------------------------
--Description: Trivium encryption algorithm
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity trivium is
port(
clk, rst : in std_logic;
hld : in std_logic; --active low if this is true then output is delayed until high again
key : in std_logic_vector(79 downto 0); --Secret 80-bit key input port
IV : in std_logic_vector(79 downto 0); --80-bit Initialization vector input port
o_vld : out std_logic; --Cipher Ready
z : out std_logic_vector(15 downto 0) --Cipher stream output
);
end trivium;
--key = 0x00000000000000000000
--IV = 0x00000000000000000000
--stream = 0xFBE0BF265859051B517A...
architecture rtl of trivium is
signal z_reg : std_logic_vector(15 downto 0);
signal z_reg_Buf : std_logic_vector(15 downto 0);
type state_type is (setup, run,hold);
signal state : state_type; --Current State
signal s, s_reg : std_logic_vector(288 downto 1);--Cipher's LFSR
signal count : integer; --Main Counter
signal count2 : integer; --buffer Counter
signal dat_rdy_buf : std_logic;
--Cipher requires bigendian so flip bits
signal key_flip :std_logic_vector(79 downto 0); --Secret 80-bit key input port
signal IV_flip :std_logic_vector(79 downto 0); --80-bit Initialization vector input port
function little_endian (b: std_logic_vector) return std_logic_vector is -- 80-bit Big Endian to Little Endian Convert (bit reverses each byte)
variable result : std_logic_vector(79 downto 0); --ex 0x0123456789 -> 0x084C2A6E19
begin
for i in 0 to 9 loop
result(((i*8)+7) downto (i*8)) :=
b(i*8) &
b((i*8) + 1) &
b((i*8) + 2) &
b((i*8) + 3) &
b((i*8) + 4) &
b((i*8) + 5) &
b((i*8) + 6) &
b((i*8) + 7);
end loop;
return result;
end;
begin
z<=z_reg;
--z <= s_reg(66) xor s_reg(93) xor s_reg(162) xor s_reg(177) xor s_reg(243) xor s_reg(288);
s(93 downto 1) <= s_reg(92 downto 1) & (s_reg(243) xor s_reg(288) xor (s_reg(286) and s_reg(287)) xor s_reg(69));
s(177 downto 94) <= s_reg(176 downto 94) & (s_reg(66) xor s_reg(93) xor (s_reg(91) and s_reg(92)) xor s_reg(171));
s(288 downto 178) <= s_reg(287 downto 178) & (s_reg(162) xor s_reg(177) xor (s_reg(175) and s_reg(176)) xor s_reg(264));
z_reg_process:
process(rst, clk) begin
if(rst = '1') then
z_reg <= (others => '0');
z_reg_Buf <= (others => '0');
count2 <= 0;
dat_rdy_buf <= '0';
elsif(rising_edge(clk)) then
if(state = run)then
if(count2 = 15)then--shift in 16 at a time
count2 <= 0;
dat_rdy_buf <= '1';
--in little endian form switch to little endian
z_reg(7 downto 0) <= ((s_reg(66) xor s_reg(93) xor s_reg(162) xor s_reg(177) xor s_reg(243) xor s_reg(288)) & z_reg_Buf(15 downto 9));
z_reg(15 downto 8)<= z_reg_Buf(8 downto 1);
else
count2 <= count2 + 1;
dat_rdy_buf <= '0';
end if;
--Bits are in little endian reverse nibbles
z_reg_Buf <= (s_reg(66) xor s_reg(93) xor s_reg(162) xor s_reg(177) xor s_reg(243) xor s_reg(288)) & z_reg_Buf(15 downto 1);
end if;
end if;
end process;
s_reg_process:
process(rst, clk) begin
if(rst = '1') then
s_reg(80 downto 1) <= key_flip(79 downto 0);
s_reg(93 downto 81) <= (others => '0');
s_reg(173 downto 94) <= IV_flip(79 downto 0);
s_reg(285 downto 174) <= (others => '0');
s_reg(288 downto 286) <= (others => '1');
elsif(rising_edge(clk)) then
if(state /= hold)then
s_reg <= s;
end if;
end if;
end process;
state_machine_process:
process(rst, clk) begin
if (rst = '1') then
state <= setup;
count <= 1;
o_vld <= '0';
elsif(rising_edge(clk)) then
case state is
when setup =>
if(count >= 1152) then --4 Cycles on 288 bits i.e. 4*288= 1152 passes
state <= run;
o_vld <= '1';
else
count <= count + 1;
state <= setup;
o_vld <= '0';
end if;
when run =>
if(count2 = 15)then
state <= hold;
else
state <= run;
end if;
when hold =>--this stops the data for the board to cycle
if(hld = '0')then --button press
state <= run;
else
state <= hold;
end if;
end case;
end if;
end process;
--Change input values to "little endian" so output matches offical test vectors
key_flip <= little_endian(key);
IV_flip <= little_endian(iv);
end rtl;
| lgpl-2.1 | c33db792599eb93cba6cd058dc621528 | 0.591717 | 2.906871 | false | false | false | false |
CamelClarkson/MIPS | MIPS_Design/Src/W_Decoder.vhd | 1 | 3,441 | ----------------------------------------------------------------------------------
--MIPS Register File Test Bench
--By: Kevin Mottler
--Camel Clarkson 32 Bit MIPS Design Group
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity W_Decoder is
Port (
i_w_Addr : in std_logic_vector(5 downto 0);
o_w_Addr : out std_logic_vector(31 downto 0)
);
end W_Decoder;
architecture Behavioral of W_Decoder is
begin
process(i_w_Addr)
begin
case i_w_Addr is
when "100000" =>
o_w_Addr <= "00000000000000000000000000000001";
when "100001" =>
o_w_Addr <= "00000000000000000000000000000010";
when "100010" =>
o_w_Addr <= "00000000000000000000000000000100";
when "100011" =>
o_w_Addr <= "00000000000000000000000000001000";
when "100100" =>
o_w_Addr <= "00000000000000000000000000010000";
when "100101" =>
o_w_Addr <= "00000000000000000000000000100000";
when "100110" =>
o_w_Addr <= "00000000000000000000000001000000";
when "100111" =>
o_w_Addr <= "00000000000000000000000010000000";
when "101000" =>
o_w_Addr <= "00000000000000000000000100000000";
when "101001" =>
o_w_Addr <= "00000000000000000000001000000000";
when "101010" =>
o_w_Addr <= "00000000000000000000010000000000";
when "101011" =>
o_w_Addr <= "00000000000000000000100000000000";
when "101100" =>
o_w_Addr <= "00000000000000000001000000000000";
when "101101" =>
o_w_Addr <= "00000000000000000010000000000000";
when "101110" =>
o_w_Addr <= "00000000000000000100000000000000";
when "101111" =>
o_w_Addr <= "00000000000000001000000000000000";
when "110000" =>
o_w_Addr <= "00000000000000010000000000000000";
when "110001" =>
o_w_Addr <= "00000000000000100000000000000000";
when "110010" =>
o_w_Addr <= "00000000000001000000000000000000";
when "110011" =>
o_w_Addr <= "00000000000010000000000000000000";
when "110100" =>
o_w_Addr <= "00000000000100000000000000000000";
when "110101" =>
o_w_Addr <= "00000000001000000000000000000000";
when "110110" =>
o_w_Addr <= "00000000010000000000000000000000";
when "110111" =>
o_w_Addr <= "00000000100000000000000000000000";
when "111000" =>
o_w_Addr <= "00000001000000000000000000000000";
when "111001" =>
o_w_Addr <= "00000010000000000000000000000000";
when "111010" =>
o_w_Addr <= "00000100000000000000000000000000";
when "111011" =>
o_w_Addr <= "00001000000000000000000000000000";
when "111100" =>
o_w_Addr <= "00010000000000000000000000000000";
when "111101" =>
o_w_Addr <= "00100000000000000000000000000000";
when "111110" =>
o_w_Addr <= "01000000000000000000000000000000";
when "111111" =>
o_w_Addr <= "10000000000000000000000000000000";
when others =>
o_w_Addr <= "00000000000000000000000000000000";
end case;
end process;
end Behavioral;
| mit | f28e0a9d50fcb337b2fb57de9dbd84ca | 0.613484 | 4.694407 | false | false | false | false |
CamelClarkson/MIPS | ALU_Control/sim/ALU_Ctrl_top_Testbench.vhd | 1 | 2,672 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity and_or_top_Testbench is
end and_or_top_Testbench;
architecture behavior of and_or_top_Testbench is
component ALU_Ctrl_top is
Port (
Op5 : in STD_LOGIC;
Op4 : in STD_LOGIC;
Op3 : in STD_LOGIC;
Op2 : in STD_LOGIC;
Op1 : in STD_LOGIC;
Op0 : in STD_LOGIC;
RegDst : out STD_LOGIC;
ALUSrc : out STD_LOGIC;
MemtoReg : out STD_LOGIC;
RegWrite : out STD_LOGIC;
MemRead : out STD_LOGIC;
MemWrite : out STD_LOGIC;
Branch : out STD_LOGIC;
ALUOp1 : out STD_LOGIC;
ALUOp0 : out STD_LOGIC
);
end component;
signal Op5: std_logic := '0';
signal Op4: std_logic := '0';
signal Op3: std_logic := '0';
signal Op2: std_logic := '0';
signal Op1: std_logic := '0';
signal Op0: std_logic := '0';
signal RegDst : STD_LOGIC;
signal ALUSrc : STD_LOGIC;
signal MemtoReg : STD_LOGIC;
signal RegWrite : STD_LOGIC;
signal MemRead : STD_LOGIC;
signal MemWrite : STD_LOGIC;
signal Branch : STD_LOGIC;
signal ALUOp1 : STD_LOGIC;
signal ALUOp0 : STD_LOGIC;
begin
-- Component Instantiation
UUT : ALU_Ctrl_top port map(Op5 => Op5,
Op4 => Op4,
Op3 => Op3,
Op2 => Op2,
Op1 => Op1,
Op0 => Op0,
RegDst => RegDst,
ALUSrc => ALUSrc,
MemtoReg => MemtoReg,
RegWrite => RegWrite,
MemRead => MemRead,
MemWrite => MemWrite,
Branch => Branch,
ALUOp1 => ALUOp1,
ALUOp0 => ALUOp0);
-- Cycle through test vectors and evaluate the results
-- the four cases in the Truth Table
process
begin
Op5 <= '0';
Op4 <= '0';
Op3 <= '0';
Op2 <= '0';
Op1 <= '0';
Op0 <= '0';
wait for 10 ns;
Op5 <= '1';
Op4 <= '0';
Op3 <= '0';
Op2 <= '0';
Op1 <= '1';
Op0 <= '1';
wait for 10 ns;
Op5 <= '1';
Op4 <= '0';
Op3 <= '1';
Op2 <= '0';
Op1 <= '1';
Op0 <= '1';
wait for 10 ns;
Op5 <= '0';
Op4 <= '0';
Op3 <= '0';
Op2 <= '1';
Op1 <= '0';
Op0 <= '0';
wait for 10 ns;
wait;
end process;
END;
| mit | d7fd564c8c2a12fb0c9944bfb6ee9b6e | 0.434132 | 3.645293 | false | false | false | false |
nsauzede/cpu86 | papilio1_0_rom/coregen/blk_mem_40K.vhd | 4 | 5,211 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_40K.vhd when simulating
-- the core, blk_mem_40K. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_40K IS
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(15 downto 0);
dina: IN std_logic_VECTOR(7 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
END blk_mem_40K;
ARCHITECTURE blk_mem_40K_a OF blk_mem_40K IS
-- synthesis translate_off
component wrapped_blk_mem_40K
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(15 downto 0);
dina: IN std_logic_VECTOR(7 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
end component;
-- Configuration specification
for all : wrapped_blk_mem_40K use entity XilinxCoreLib.blk_mem_gen_v3_2(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 8,
c_initb_val => "0",
c_family => "spartan3",
c_read_width_a => 8,
c_disable_warn_bhv_coll => 1,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "blk_mem_40K.mif",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 1,
c_xdevicefamily => "spartan3e",
c_write_depth_b => 40960,
c_write_depth_a => 40960,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 16,
c_addrb_width => 16,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 1,
c_write_width_b => 8,
c_write_width_a => 8,
c_read_depth_b => 40960,
c_read_depth_a => 40960,
c_byte_size => 9,
c_sim_collision_check => "NONE",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_40K
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
-- synthesis translate_on
END blk_mem_40K_a;
| gpl-2.0 | 9b7db064425e80243c21e270219f9da6 | 0.542314 | 3.611227 | false | false | false | false |
CamelClarkson/MIPS | ALU/ALU_testbench.vhd | 1 | 5,413 | ----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- Email : [email protected]
-- Instructor Name: Dr. Chen Liu
-- Date : 09-25-2016
--
-- Create Date: 09/25/2016 03:14:09 PM
-- Design Name:
-- Module Name: ALU_testbench - ALU_TB_FUNC
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU_testbench is
end ALU_testbench;
architecture ALU_TB_FUNC of ALU_testbench is
component ALU is
Port ( A : in STD_LOGIC_VECTOR (31 downto 0); -- operands 1
B : in STD_LOGIC_VECTOR (31 downto 0); -- operands 2
P3 : in STD_LOGIC; -- Control signal 3
P2 : in STD_LOGIC; -- Conrtol signal 2
P1 : in STD_LOGIC; -- Conrtol signal 1
P0 : in STD_LOGIC; -- Conrtol signal 0
F : out STD_LOGIC_VECTOR (31 downto 0); -- ALU result
COUT : out STD_LOGIC; -- carry out
Overflow : out STD_LOGIC; -- overflow flag
ZERO : out STD_LOGIC); -- zero flag
end component ALU;
signal A : STD_LOGIC_VECTOR (31 downto 0);
signal B : STD_LOGIC_VECTOR (31 downto 0);
signal P3 : STD_LOGIC;
signal P2 : STD_LOGIC;
signal P1 : STD_LOGIC;
signal P0 : STD_LOGIC;
signal F : STD_LOGIC_VECTOR (31 downto 0);
signal COUT : STD_LOGIC;
signal Overflow : STD_LOGIC; --local signal declaration
signal ZERO : STD_LOGIC;
begin
DUT : ALU port map(--Design under test
A => A ,
B => B ,
P3 => P3 ,
P2 => P2,
P1 => P1,
P0 => P0,
F => F ,
COUT => COUT,
Overflow => Overflow,
ZERO => ZERO);
process
begin
--cycle 1: AND
A <= "11010000000000000000000000001011"; --
B <= "11110000000000000000000000000010"; --
P3 <= '0';
P2 <= '0';
P1 <= '0';
P0 <= '0';
wait for 10ns;
--cycle 2: OR
A <= "00000000000000001111000000001011"; --
B <= "00000111110000000000000000000010"; --
P3 <= '0';
P2 <= '0';
P1 <= '0';
P0 <= '1';
wait for 10ns;
--cycle 3: Add
A <= "00000000000000000000000000001011"; --
B <= "00000000000000000001111100000010"; --
P3 <= '0';
P2 <= '0';
P1 <= '1';
P0 <= '0';
wait for 10ns;
--cycle 4: Substract
A <= "01110000000000000000000000001011"; --
B <= "01110000000000000000000000000010"; --
P3 <= '0';
P2 <= '1';
P1 <= '1';
P0 <= '0';
wait for 10ns;
--cycle 5: set on less than A < B
A <= "11110000000000000000000000001011"; --
B <= "01110000000000000000000000001110"; --
P3 <= '0';
P2 <= '1';
P1 <= '1';
P0 <= '1';
wait for 10ns;
--cycle 6: NOR
A <= "11110000000000011100000000001011"; --
B <= "11110000000000000000000000011010"; --
P3 <= '1';
P2 <= '1';
P1 <= '0';
P0 <= '0';
wait for 10ns;
--cycle 7: Substract ,which ZERO is 1
A <= "01110000000000000000000000001011"; --
B <= "01110000000000000000000000001011"; --
P3 <= '0';
P2 <= '1';
P1 <= '1';
P0 <= '0';
wait for 10ns;
--cycle 8: Set on less than ,A > B
A <= "01110000000000000000001110001011"; --
B <= "01110000000000000000000000000011"; --
P3 <= '0';
P2 <= '1';
P1 <= '1';
P0 <= '1';
wait for 10ns;
--cycle 9: Set on less than ,A = B
A <= "00000000000000000000001110000011"; --
B <= "00000000000000000000001110000011"; --
P3 <= '0';
P2 <= '1';
P1 <= '1';
P0 <= '1';
wait for 10ns;
--cycle 10: Add to overflow
A <= "01100000000000000000000000001011"; --
B <= "01111111111111111101111100000010"; --
P3 <= '0';
P2 <= '0';
P1 <= '1';
P0 <= '0';
wait for 10ns;
-- end
A <= "00000000000000000000000000000000"; --
B <= "11111111111111111111111111111111"; --
P3 <= '0';
P2 <= '0';
P1 <= '0';
P0 <= '0';
wait for 10ns;
wait;
end process;
end ALU_TB_FUNC;
| mit | a586235f725fad7d29263087707b06cc | 0.47349 | 3.839007 | false | false | false | false |
VenturaSolutionsInc/VHDL | igmp/checksum_tb.vhd | 1 | 3,648 | -------------------------------------------------------------------------------
-- Title : Testbench for design "checksum"
-- Project :
-------------------------------------------------------------------------------
-- File : checksum_tb.vhd
-- Author : <sheac@DRESDEN>
-- Company :
-- Created : 2010-03-16
-- Last update: 2010-03-16
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-03-16 1.0 sheac Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity checksum_tb is
end checksum_tb;
-------------------------------------------------------------------------------
architecture testbench of checksum_tb is
component checksum
port (
dataClk : in std_logic;
reset : in std_logic;
start_checksum : in std_logic;
multicast_ip : in std_logic_vector(31 downto 0);
source_ip : in std_logic_vector(31 downto 0);
checksum_done : out std_logic;
ipv4_layer_checksum_j : out std_logic_vector(15 downto 0);
ipv4_layer_checksum_l : out std_logic_vector(15 downto 0);
igmp_layer_checksum_j : out std_logic_vector(15 downto 0);
igmp_layer_checksum_l : out std_logic_vector(15 downto 0));
end component;
-- component ports
signal dataClk : std_logic;
signal reset : std_logic;
signal start_checksum : std_logic;
signal multicast_ip : std_logic_vector(31 downto 0);
signal source_ip : std_logic_vector(31 downto 0);
signal checksum_done : std_logic;
signal ipv4_layer_checksum_j : std_logic_vector(15 downto 0);
signal ipv4_layer_checksum_l : std_logic_vector(15 downto 0);
signal igmp_layer_checksum_j : std_logic_vector(15 downto 0);
signal igmp_layer_checksum_l : std_logic_vector(15 downto 0);
-- clock
signal Clk : std_logic := '1';
begin -- testbench
-- component instantiation
DUT: checksum
port map (
dataClk => dataClk,
reset => reset,
start_checksum => start_checksum,
multicast_ip => multicast_ip,
source_ip => source_ip,
checksum_done => checksum_done,
ipv4_layer_checksum_j => ipv4_layer_checksum_j,
ipv4_layer_checksum_l => ipv4_layer_checksum_l,
igmp_layer_checksum_j => igmp_layer_checksum_j,
igmp_layer_checksum_l => igmp_layer_checksum_l);
gen_data_clk : process
begin
dataClk <= '1';
wait for 4 ns;
dataClk <= '0';
wait for 4 ns;
end process;
-- set the multicast address we are joining
multicast_ip <= X"EF9C1901";
-- provide the devices address
source_ip <= X"C0A80164";
control : process
begin
reset <= '1';
start_checksum <= '0';
wait for 16 ns;
reset <= '0';
start_checksum <= '1';
wait for 8 ns;
start_checksum <= '0';
wait;
end process;
end testbench;
-------------------------------------------------------------------------------
| gpl-2.0 | 4a9db3ab65c7262fccf99296ee30db60 | 0.455592 | 4.374101 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Encryption_Decryption/bak/rc5_enc.vhd | 1 | 8,572 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
USE WORK.RC5_PKG.ALL;
ENTITY rc5_enc IS
PORT (
clr,clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit input
di_vld : IN STD_LOGIC; -- Valid Input
key_rdy : IN STD_LOGIC;
skey : IN rc5_rom_26;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit output
do_rdy : OUT STD_LOGIC --Output is Ready
);
END rc5_enc;
ARCHITECTURE rtl OF rc5_enc IS
SIGNAL i_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); -- round counter
SIGNAL ab_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_pre : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register A
SIGNAL ba_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_pre : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register B
---- define a type for round keys
--TYPE rom IS ARRAY (0 TO 25) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
--CONSTANT skey : rom:=rom'( X"9BBBD8C8", X"1A37F7FB", X"46F8E8C5", X"460C6085",
-- X"70F83B8A", X"284B8303", X"513E1454", X"F621ED22",
-- X"3125065D", X"11A83A5D", X"D427686B", X"713AD82D",
-- X"4B792F99", X"2799A4DD", X"A7901C49", X"DEDE871A",
-- X"36C03196", X"A7EFC249", X"61A78BB8", X"3B0A1D2B",
-- X"4DBFCA76", X"AE162167", X"30D76B0A", X"43192304",
-- X"F6CC1431",X"65046380");
--
----RC5 state machine has five states
--TYPE StateType IS(ST_IDLE, -- In this state RC5 is ready for input
-- ST_PRE_ROUND, -- In this state RC5 pre-round op is performed
-- ST_ROUND_OP, -- In this state RC5 round op is performed.
-- -- The state machine remains in this state
-- -- for twelve clock cycles.
-- ST_READY -- In this state RC5 has completed encryption
-- );
-- RC5 state machine has five states: idle, pre_round, round and ready
SIGNAL state : enc_StateType;
BEGIN
-- A=((A XOR B)<<<B) + S[2*i];
ab_xor <= a_reg XOR b_reg;
WITH b_reg(4 DOWNTO 0) SELECT
a_rot<= ab_xor(30 DOWNTO 0) & ab_xor(31) WHEN "00001", --01
ab_xor(29 DOWNTO 0) & ab_xor(31 DOWNTO 30) WHEN "00010", --02
ab_xor(28 DOWNTO 0) & ab_xor(31 DOWNTO 29) WHEN "00011", --03
ab_xor(27 DOWNTO 0) & ab_xor(31 DOWNTO 28) WHEN "00100", --04
ab_xor(26 DOWNTO 0) & ab_xor(31 DOWNTO 27) WHEN "00101", --05
ab_xor(25 DOWNTO 0) & ab_xor(31 DOWNTO 26) WHEN "00110", --06
ab_xor(24 DOWNTO 0) & ab_xor(31 DOWNTO 25) WHEN "00111", --07
ab_xor(23 DOWNTO 0) & ab_xor(31 DOWNTO 24) WHEN "01000", --08
ab_xor(22 DOWNTO 0) & ab_xor(31 DOWNTO 23) WHEN "01001", --09
ab_xor(21 DOWNTO 0) & ab_xor(31 DOWNTO 22) WHEN "01010", --10
ab_xor(20 DOWNTO 0) & ab_xor(31 DOWNTO 21) WHEN "01011", --11
ab_xor(19 DOWNTO 0) & ab_xor(31 DOWNTO 20) WHEN "01100", --12
ab_xor(18 DOWNTO 0) & ab_xor(31 DOWNTO 19) WHEN "01101", --13
ab_xor(17 DOWNTO 0) & ab_xor(31 DOWNTO 18) WHEN "01110", --14
ab_xor(16 DOWNTO 0) & ab_xor(31 DOWNTO 17) WHEN "01111", --15
ab_xor(15 DOWNTO 0) & ab_xor(31 DOWNTO 16) WHEN "10000", --16
ab_xor(14 DOWNTO 0) & ab_xor(31 DOWNTO 15) WHEN "10001", --17
ab_xor(13 DOWNTO 0) & ab_xor(31 DOWNTO 14) WHEN "10010", --18
ab_xor(12 DOWNTO 0) & ab_xor(31 DOWNTO 13) WHEN "10011", --19
ab_xor(11 DOWNTO 0) & ab_xor(31 DOWNTO 12) WHEN "10100", --20
ab_xor(10 DOWNTO 0) & ab_xor(31 DOWNTO 11) WHEN "10101", --21
ab_xor(09 DOWNTO 0) & ab_xor(31 DOWNTO 10) WHEN "10110", --22
ab_xor(08 DOWNTO 0) & ab_xor(31 DOWNTO 09) WHEN "10111", --23
ab_xor(07 DOWNTO 0) & ab_xor(31 DOWNTO 08) WHEN "11000", --24
ab_xor(06 DOWNTO 0) & ab_xor(31 DOWNTO 07) WHEN "11001", --25
ab_xor(05 DOWNTO 0) & ab_xor(31 DOWNTO 06) WHEN "11010", --26
ab_xor(04 DOWNTO 0) & ab_xor(31 DOWNTO 05) WHEN "11011", --27
ab_xor(03 DOWNTO 0) & ab_xor(31 DOWNTO 04) WHEN "11100", --28
ab_xor(02 DOWNTO 0) & ab_xor(31 DOWNTO 03) WHEN "11101", --29
ab_xor(01 DOWNTO 0) & ab_xor(31 DOWNTO 02) WHEN "11110", --30
ab_xor(0) & ab_xor(31 DOWNTO 01) WHEN "11111", --31
ab_xor WHEN OTHERS;
a_pre<=din(63 DOWNTO 32) + skey(0); --A = A + S[0]
a<=a_rot + skey(CONV_INTEGER(i_cnt & '0')); -- S[2*i]
-- B=((B XOR A) <<<A) + S[2*i+1]
ba_xor <= b_reg XOR a;
WITH a(4 DOWNTO 0) SELECT
b_rot<= ba_xor(30 DOWNTO 0) & ba_xor(31) WHEN "00001", --01
ba_xor(29 DOWNTO 0) & ba_xor(31 DOWNTO 30) WHEN "00010", --02
ba_xor(28 DOWNTO 0) & ba_xor(31 DOWNTO 29) WHEN "00011", --03
ba_xor(27 DOWNTO 0) & ba_xor(31 DOWNTO 28) WHEN "00100", --04
ba_xor(26 DOWNTO 0) & ba_xor(31 DOWNTO 27) WHEN "00101", --05
ba_xor(25 DOWNTO 0) & ba_xor(31 DOWNTO 26) WHEN "00110", --06
ba_xor(24 DOWNTO 0) & ba_xor(31 DOWNTO 25) WHEN "00111", --07
ba_xor(23 DOWNTO 0) & ba_xor(31 DOWNTO 24) WHEN "01000", --08
ba_xor(22 DOWNTO 0) & ba_xor(31 DOWNTO 23) WHEN "01001", --09
ba_xor(21 DOWNTO 0) & ba_xor(31 DOWNTO 22) WHEN "01010", --10
ba_xor(20 DOWNTO 0) & ba_xor(31 DOWNTO 21) WHEN "01011", --11
ba_xor(19 DOWNTO 0) & ba_xor(31 DOWNTO 20) WHEN "01100", --12
ba_xor(18 DOWNTO 0) & ba_xor(31 DOWNTO 19) WHEN "01101", --13
ba_xor(17 DOWNTO 0) & ba_xor(31 DOWNTO 18) WHEN "01110", --14
ba_xor(16 DOWNTO 0) & ba_xor(31 DOWNTO 17) WHEN "01111", --15
ba_xor(15 DOWNTO 0) & ba_xor(31 DOWNTO 16) WHEN "10000", --16
ba_xor(14 DOWNTO 0) & ba_xor(31 DOWNTO 15) WHEN "10001", --17
ba_xor(13 DOWNTO 0) & ba_xor(31 DOWNTO 14) WHEN "10010", --18
ba_xor(12 DOWNTO 0) & ba_xor(31 DOWNTO 13) WHEN "10011", --19
ba_xor(11 DOWNTO 0) & ba_xor(31 DOWNTO 12) WHEN "10100", --20
ba_xor(10 DOWNTO 0) & ba_xor(31 DOWNTO 11) WHEN "10101", --21
ba_xor(09 DOWNTO 0) & ba_xor(31 DOWNTO 10) WHEN "10110", --22
ba_xor(08 DOWNTO 0) & ba_xor(31 DOWNTO 09) WHEN "10111", --23
ba_xor(07 DOWNTO 0) & ba_xor(31 DOWNTO 08) WHEN "11000", --24
ba_xor(06 DOWNTO 0) & ba_xor(31 DOWNTO 07) WHEN "11001", --25
ba_xor(05 DOWNTO 0) & ba_xor(31 DOWNTO 06) WHEN "11010", --26
ba_xor(04 DOWNTO 0) & ba_xor(31 DOWNTO 05) WHEN "11011", --27
ba_xor(03 DOWNTO 0) & ba_xor(31 DOWNTO 04) WHEN "11100", --28
ba_xor(02 DOWNTO 0) & ba_xor(31 DOWNTO 03) WHEN "11101", --29
ba_xor(01 DOWNTO 0) & ba_xor(31 DOWNTO 02) WHEN "11110", --30
ba_xor(0) & ba_xor(31 DOWNTO 01) WHEN "11111", --31
ba_xor WHEN OTHERS;
b_pre<=din(31 DOWNTO 0) + skey(1); --B = B + S[1]
b<=b_rot + skey(CONV_INTEGER(i_cnt & '1')); -- S[2*i+1]
A_register:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
a_reg<=din(63 DOWNTO 32);
ELSIF(rising_edge(clk)) THEN --clk'EVENT AND clk='1' can introduce error
IF(state=ST_PRE_ROUND) THEN
a_reg<=a_pre;
ELSIF(state=ST_ROUND_OP) THEN
a_reg<=a;
END IF;
END IF;
END PROCESS;
B_register:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
b_reg<=din(31 DOWNTO 0);
ELSIF(rising_edge(clk)) THEN
IF(state=ST_PRE_ROUND) THEN
b_reg<=b_pre;
ELSIF(state=ST_ROUND_OP) THEN
b_reg<=b;
END IF;
END IF;
END PROCESS;
State_Control:
PROCESS(clr, clk)
BEGIN
IF(clr='0') THEN
state<=ST_IDLE;
ELSIF(clk'EVENT AND clk='1') THEN
CASE state IS
WHEN ST_IDLE=> IF(di_vld='1' and key_rdy='1') THEN
state<=ST_PRE_ROUND;
END IF;
WHEN ST_PRE_ROUND=> state<=ST_ROUND_OP;
WHEN ST_ROUND_OP=> IF(i_cnt="1100") THEN
state<=ST_READY;
END IF;
WHEN ST_READY=> IF(di_vld='1' and key_rdy='1') THEN
state<=ST_PRE_ROUND;--can assume new keys and skip idle state
--state<=ST_IDLE;--If Input Changes then restart
END IF;
END CASE;
END IF;
END PROCESS;
round_counter:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
i_cnt<="0001";
ELSIF(rising_edge(clk) AND state=ST_ROUND_OP) THEN
IF(i_cnt="1100") THEN
i_cnt<="0001";
ELSE
i_cnt<=i_cnt+'1';
END IF;
END IF;
END PROCESS;
dout<=a_reg & b_reg;
WITH state SELECT
do_rdy<='1' WHEN ST_READY,
'0' WHEN OTHERS;
END rtl; | lgpl-2.1 | 08670abb00723e7655ee9c2a35ea5f80 | 0.581311 | 2.731676 | false | false | false | false |
nsauzede/cpu86 | papilio1_0_rom/testbench/papilio1_tb.vhd | 2 | 12,834 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- TestBench --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.STD_LOGIC_UNSIGNED.all;
LIBRARY std;
USE std.TEXTIO.all;
USE work.utils.all;
entity papilio1_tb is
end papilio1_tb ;
ARCHITECTURE struct OF papilio1_tb IS
-- Architecture declarations
signal dind1_s : std_logic;
signal dind2_s : std_logic;
-- Internal signal declarations
SIGNAL CLOCK_40MHZ : std_logic := '0';
SIGNAL CLOCK_32MHZ : std_logic := '0';
SIGNAL CTS : std_logic;
SIGNAL resetn : std_logic;
SIGNAL TXD : std_logic;
SIGNAL cpuerror : std_logic;
SIGNAL rdn_s : std_logic; -- Active Low Read Pulse (CLK)
SIGNAL rdrf : std_logic;
SIGNAL rxenable : std_logic;
SIGNAL txcmd : std_logic;
SIGNAL txenable : std_logic;
SIGNAL udbus : Std_Logic_Vector(7 DOWNTO 0);
CONSTANT DIVIDER_c : std_logic_vector(7 downto 0):="01000001"; -- 65, baudrate divider 40MHz
SIGNAL divtx_s : std_logic_vector(3 downto 0);
SIGNAL divcnt_s : std_logic_vector(7 downto 0);
SIGNAL rxclk16_s : std_logic;
SIGNAL tdre_s : std_logic;
SIGNAL wrn_s : std_logic;
SIGNAL char_s : std_logic_vector(7 downto 0);
signal rx : STD_LOGIC;
signal tx : STD_LOGIC;
signal W1A : STD_LOGIC_VECTOR (15 downto 0);
signal W1B : STD_LOGIC_VECTOR (15 downto 0);
signal W2C : STD_LOGIC_VECTOR (15 downto 0);
signal clk : STD_LOGIC;
-- Component Declarations
COMPONENT papilio1_top
Port ( rx : in STD_LOGIC;
tx : out STD_LOGIC;
W1A : inout STD_LOGIC_VECTOR (15 downto 0);
W1B : inout STD_LOGIC_VECTOR (15 downto 0);
W2C : inout STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC);
-- PORT(
-- CLOCK_40MHZ : IN std_logic;
-- CTS : IN std_logic := '1';
-- PIN3 : IN std_logic;
-- RXD : IN std_logic;
-- LED1 : OUT std_logic;
-- LED2N : OUT std_logic;
-- LED3N : OUT std_logic;
-- PIN4 : OUT std_logic;
-- RTS : OUT std_logic;
-- TXD : OUT std_logic
-- );
END COMPONENT;
COMPONENT uartrx
PORT (
clk : IN std_logic;
enable : IN std_logic;
rdn : IN std_logic;
resetn : IN std_logic;
rx : IN std_logic;
dbus : OUT std_logic_vector (7 DOWNTO 0);
ferror : OUT std_logic;
rdrf : OUT std_logic
);
END COMPONENT;
COMPONENT uarttx
PORT (
clk : in std_logic ;
enable : in std_logic ; -- 1 x bit_rate transmit clock enable
resetn : in std_logic ;
dbus : in std_logic_vector (7 downto 0); -- input to txshift register
tdre : out std_logic ;
wrn : in std_logic ;
tx : out std_logic);
END COMPONENT;
BEGIN
CLOCK_40MHZ <= not CLOCK_40MHZ after 12.5 ns; -- 40MHz
-- CLOCK_40MHZ <= not CLOCK_40MHZ after 25 ns; -- 20MHz
CLOCK_32MHZ <= not CLOCK_32MHZ after 15.625 ns; -- 32MHz
process
variable L : line;
procedure write_to_uart (char_in : IN character) is
begin
char_s <=to_std_logic_vector(char_in);
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '0';
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '1';
wait until rising_edge(CLOCK_40MHZ);
wait until rising_edge(tdre_s);
end;
begin
CTS <= '1';
resetn <= '0'; -- PIN3 on Drigmorn1 connected to PIN2
wait for 100 ns;
resetn <= '1';
wrn_s <= '1'; -- Active low write strobe to TX UART
char_s <= (others => '1');
wait for 25.1 ms; -- wait for > prompt before issuing commands
-- write_to_uart('R');
write_to_uart('H');
wait for 47 ms; -- wait for > prompt before issuing commands
write_to_uart('D'); -- Issue Fill Memory command
write_to_uart('M');
write_to_uart('0');
write_to_uart('1');
write_to_uart('0');
write_to_uart('0');
wait for 1 ms;
write_to_uart('0');
write_to_uart('1');
write_to_uart('2');
write_to_uart('4');
wait for 50 ms; -- wait for > prompt before issuing commands
wait;
end process;
------------------------------------------------------------------------------
-- 8 bits divider
-- Generate rxenable clock (16 x baudrate)
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resetn) -- First divider
begin
if (resetn='0') then
divcnt_s <= (others => '0');
rxclk16_s <= '0'; -- Receive clock (x16, pulse)
elsif (rising_edge(CLOCK_40MHZ)) then
if divcnt_s=DIVIDER_c then
divcnt_s <= (others => '0');
rxclk16_s <= '1';
else
rxclk16_s <= '0';
divcnt_s <= divcnt_s + '1';
end if;
end if;
end process;
rxenable <= rxclk16_s;
------------------------------------------------------------------------------
-- divider by 16
-- rxclk16/16=txclk
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resetn)
begin
if (resetn='0') then
divtx_s <= (others => '0');
elsif (rising_edge(CLOCK_40MHZ)) then
if rxclk16_s='1' then
divtx_s <= divtx_s + '1';
if divtx_s="0000" then
txenable <= '1';
end if;
else
txenable <= '0';
end if;
end if;
end process;
assert not ((NOW > 0 ns) and cpuerror='1') report "**** CPU Error flag asserted ****" severity error;
------------------------------------------------------------------------------
-- UART Monitor
-- Display string on console after 80 characters or when CR character is received
------------------------------------------------------------------------------
process (rdrf,resetn)
variable L : line;
variable i_v : integer;
begin
if resetn='0' then
i_v := 0; -- clear character counter
elsif (rising_edge(rdrf)) then -- possible, pulse is wide!
if i_v=0 then
write(L,string'("RD UART : "));
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
elsif (i_v=80 or udbus=X"0D") then
writeline(output,L);
i_v:=0;
else
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
end if;
end if;
end process;
process (CLOCK_40MHZ,resetn) -- First/Second delay
begin
if (resetn='0') then
dind1_s <= '0';
dind2_s <= '0';
elsif (rising_edge(CLOCK_40MHZ)) then
dind1_s <= rdrf;
dind2_s <= dind1_s;
end if;
end process;
rdn_s <= '0' when (dind1_s='1' and dind2_s='0') else '1';
------------------------------------------------------------------------------
-- Top Level CPU+RAM+UART
------------------------------------------------------------------------------
U_0 : papilio1_top
PORT MAP (
rx => rx,
tx => tx,
W1A => w1a,
W1B => w1b,
W2C => w2c,
clk => clk
);
clk <= CLOCK_32MHZ;
TXD <= tx;
rx <= txcmd;
w1b(1) <= resetn;
-- CTS => CTS,
-- PIN3 => resetn,
-- RXD => txcmd,
--TXD => TXD,
-- LED1 => cpuerror,
------------------------------------------------------------------------------
-- TX Uart
------------------------------------------------------------------------------
U_1 : uarttx
port map (
clk => CLOCK_40MHZ,
enable => txenable,
resetn => resetn,
dbus => char_s,
tdre => tdre_s,
wrn => wrn_s,
tx => txcmd
);
------------------------------------------------------------------------------
-- RX Uart
------------------------------------------------------------------------------
U_2 : uartrx
PORT MAP (
clk => CLOCK_40MHZ,
enable => rxenable,
resetn => resetn,
dbus => udbus,
rdn => rdn_s,
rdrf => rdrf,
ferror => OPEN,
rx => TXD
);
END struct;
| gpl-2.0 | 5516a62b53b5665a442311a135ea92bc | 0.372214 | 4.737542 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/biufsm_fsm.vhd | 3 | 17,357 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.cpu86pack.ALL;
USE work.cpu86instr.ALL;
ENTITY biufsm IS
PORT(
clk : IN std_logic;
flush_coming : IN std_logic;
flush_req : IN std_logic;
irq_req : IN std_logic;
irq_type : IN std_logic_vector (1 DOWNTO 0);
opc_req : IN std_logic;
read_req : IN std_logic;
reg1freed : IN std_logic; -- Delayed version (1 clk) of reg1free
reg4free : IN std_logic;
regnbok : IN std_logic;
reset : IN std_logic;
w_biufsm_s : IN std_logic;
write_req : IN std_logic;
addrplus4 : OUT std_logic;
biu_error : OUT std_logic;
biu_status : OUT std_logic_vector (2 DOWNTO 0);
irq_ack : OUT std_logic;
irq_clr : OUT std_logic;
latchabus : OUT std_logic;
latchclr : OUT std_logic;
latchm : OUT std_logic;
latcho : OUT std_logic;
latchrw : OUT std_logic;
ldposplus1 : OUT std_logic;
muxabus : OUT std_logic_vector (1 DOWNTO 0);
rdcode_s : OUT std_logic;
rddata_s : OUT std_logic;
regplus1 : OUT std_logic;
rw_ack : OUT std_logic;
wr_s : OUT std_logic;
flush_ack : BUFFER std_logic;
inta1 : BUFFER std_logic
);
END biufsm ;
ARCHITECTURE fsm OF biufsm IS
signal ws_s : std_logic_vector(WS_WIDTH-1 downto 0);
signal oddflag_s : std_logic;
signal rwmem3_s : std_logic; -- Misaligned Read/Write cycle
TYPE STATE_TYPE IS (
Sreset,
Sws,
Smaxws,
Sack,
Srdopc,
Serror,
Swrite,
Swsw,
Smaxwsw,
Sackw,
Swrodd,
Sread,
Srdodd,
Swsr,
Smaxwsr,
Sackr,
Sflush1,
Sfull,
Sint,
Sintws2,
Sflush2,
Sintws1
);
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
SIGNAL biu_error_int : std_logic ;
SIGNAL biu_status_cld : std_logic_vector (2 DOWNTO 0);
BEGIN
clocked_proc : PROCESS (clk,reset)
BEGIN
IF (reset = '1') THEN
current_state <= Sreset;
biu_error <= '0';
biu_status_cld <= "011";
oddflag_s <= '0';
ws_s <= (others=>'0');
ELSIF (clk'EVENT AND clk = '1') THEN
current_state <= next_state;
biu_error <= biu_error_int;
ws_s <= (others=>'0');
CASE current_state IS
WHEN Sreset =>
biu_status_cld<="000";
WHEN Sws =>
ws_s <= ws_s + '1';
IF (flush_req = '1') THEN
biu_status_cld<="011";
END IF;
WHEN Smaxws =>
IF (flush_req = '1') THEN
biu_status_cld<="011";
END IF;
WHEN Sack =>
oddflag_s<='0';
IF (write_req = '1') THEN
biu_status_cld<="010";
ELSIF (read_req = '1') THEN
biu_status_cld<="001";
ELSIF (flush_req = '1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
biu_status_cld<="000";
ELSIF (regnbok = '0' and
reg4free = '0') THEN
ELSE
biu_status_cld<="011";
END IF;
WHEN Srdopc =>
ws_s <= (others=>'0');
IF (flush_req = '1') THEN
biu_status_cld<="011";
END IF;
WHEN Swrite =>
ws_s <= (others=>'0');
oddflag_s<='0';
WHEN Swsw =>
ws_s <= ws_s + '1';
WHEN Sackw =>
IF (rwmem3_s = '1') THEN
ELSIF (flush_req = '1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' ) THEN
biu_status_cld<="000";
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
biu_status_cld<="011";
END IF;
WHEN Swrodd =>
ws_s <= (others=>'0');
oddflag_s<='1';
WHEN Sread =>
ws_s <= (others=>'0');
oddflag_s<='0';
WHEN Srdodd =>
ws_s <= (others=>'0');
oddflag_s<='1';
WHEN Swsr =>
ws_s <= ws_s + '1';
WHEN Sackr =>
IF (rwmem3_s = '1') THEN
ELSIF (flush_req='1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' ) THEN
biu_status_cld<="000";
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
biu_status_cld<="011";
END IF;
WHEN Sfull =>
IF (write_req='1') THEN
biu_status_cld<="010";
ELSIF (read_req='1') THEN
biu_status_cld<="001";
ELSIF (flush_req = '1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
biu_status_cld<="000";
END IF;
WHEN Sintws2 =>
biu_status_cld<="011";
WHEN Sflush2 =>
biu_status_cld<="000";
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
current_state,
flush_coming,
flush_req,
irq_req,
irq_type,
opc_req,
read_req,
reg1freed,
reg4free,
regnbok,
rwmem3_s,
write_req,
ws_s
)
-----------------------------------------------------------------
BEGIN
-- Default Assignment
addrplus4 <= '0';
biu_error_int <= '0';
irq_ack <= '0';
irq_clr <= '0';
latchabus <= '0';
latchclr <= '0';
latchm <= '0';
latcho <= '0';
latchrw <= '0';
ldposplus1 <= '0';
muxabus <= "00";
rdcode_s <= '0';
rddata_s <= '0';
regplus1 <= '0';
rw_ack <= '0';
wr_s <= '0';
flush_ack <= '0';
inta1 <= '0';
-- Combined Actions
CASE current_state IS
WHEN Sreset =>
latchrw <= '1' ;
next_state <= Srdopc;
WHEN Sws =>
IF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (ws_s=MAX_WS-1) THEN
next_state <= Smaxws;
ELSE
next_state <= Sws;
END IF;
WHEN Smaxws =>
latchabus<='1';
addrplus4<='1';
latchclr <= '1' ;
ldposplus1<='1';
IF (flush_req = '1') THEN
next_state <= Sflush1;
ELSE
next_state <= Sack;
END IF;
WHEN Sack =>
latchm<=reg1freed;
regplus1<='1';
IF (write_req = '1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Swrite;
ELSIF (read_req = '1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Sread;
ELSIF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
latchrw <= '1' ;
next_state <= Srdopc;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
next_state <= Sfull;
END IF;
WHEN Srdopc =>
rdcode_s <= '1';
latcho <= regnbok and opc_req;
IF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (ws_s/=MAX_WS) THEN
next_state <= Sws;
ELSE
next_state <= Smaxws;
END IF;
WHEN Serror =>
biu_error_int <= '1';
next_state <= Serror;
WHEN Swrite =>
wr_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsw;
ELSE
next_state <= Smaxwsw;
END IF;
WHEN Swsw =>
latcho <= regnbok and opc_req;
IF (ws_s=MAX_WS-1) THEN
next_state <= Smaxwsw;
ELSE
next_state <= Swsw;
END IF;
WHEN Smaxwsw =>
latcho <= regnbok and opc_req;
latchclr <= '1' ;
rw_ack<= not rwmem3_s;
next_state <= Sackw;
WHEN Sackw =>
latcho <= regnbok and opc_req;
IF (rwmem3_s = '1') THEN
muxabus <="10";
latchrw<='1';
next_state <= Swrodd;
ELSIF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' ) THEN
muxabus <="00";
latchrw<='1';
next_state <= Srdopc;
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
next_state <= Sfull;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
muxabus <="00";
next_state <= Sack;
END IF;
WHEN Swrodd =>
latcho <= regnbok and opc_req;
wr_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsw;
ELSE
next_state <= Smaxwsw;
END IF;
WHEN Sread =>
rddata_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsr;
ELSE
next_state <= Smaxwsr;
END IF;
WHEN Srdodd =>
rddata_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsr;
ELSE
next_state <= Smaxwsr;
END IF;
WHEN Swsr =>
IF (ws_s=MAX_WS-1) THEN
next_state <= Smaxwsr;
ELSE
next_state <= Swsr;
END IF;
WHEN Smaxwsr =>
latchclr <= '1' ;
rw_ack<= not rwmem3_s;
next_state <= Sackr;
WHEN Sackr =>
IF (rwmem3_s = '1') THEN
muxabus <="10";
latchrw <= '1';
next_state <= Srdodd;
ELSIF (flush_req='1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' ) THEN
muxabus <="00";
latchrw<='1';
next_state <= Srdopc;
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
next_state <= Sfull;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
muxabus <="00";
next_state <= Sack;
END IF;
WHEN Sflush1 =>
flush_ack<='1';
IF (flush_req='0') THEN
muxabus<="01";
next_state <= Sflush2;
ELSE
next_state <= Sflush1;
END IF;
WHEN Sfull =>
latcho <= regnbok and opc_req;
IF (write_req='1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Swrite;
ELSIF (read_req='1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Sread;
ELSIF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
latchrw <= '1' ;
next_state <= Srdopc;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
next_state <= Sfull;
END IF;
WHEN Sint =>
latcho <= opc_req;
if irq_type="00" then inta1<='1';
end if;
irq_ack<='1';
next_state <= Sintws1;
WHEN Sintws2 =>
if irq_type="00" then
inta1<='1';
end if;
irq_clr <= '1';
next_state <= Sfull;
WHEN Sflush2 =>
latchabus<='1';
addrplus4<='0';
latchrw <= '1' ;
muxabus <="01";
next_state <= Srdopc;
WHEN Sintws1 =>
if irq_type="00" then
inta1<='1';
end if;
next_state <= Sintws2;
WHEN OTHERS =>
next_state <= Sreset;
END CASE;
END PROCESS nextstate_proc;
biu_status <= biu_status_cld;
rwmem3_s <= '1' when (w_biufsm_s='1' and oddflag_s='0') else '0';
END fsm;
| gpl-2.0 | b26e4fd0e4ee59d8871a2c30df670747 | 0.379674 | 4.398632 | false | false | false | false |
nsauzede/cpu86 | papilio1_0/coregen/blk_mem_40Kx.vhd | 2 | 5,211 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_40K.vhd when simulating
-- the core, blk_mem_40K. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_40K IS
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(15 downto 0);
dina: IN std_logic_VECTOR(7 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
END blk_mem_40K;
ARCHITECTURE blk_mem_40K_a OF blk_mem_40K IS
-- synthesis translate_off
component wrapped_blk_mem_40K
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(15 downto 0);
dina: IN std_logic_VECTOR(7 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
end component;
-- Configuration specification
for all : wrapped_blk_mem_40K use entity XilinxCoreLib.blk_mem_gen_v3_1(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 8,
c_initb_val => "0",
c_family => "spartan3",
c_read_width_a => 8,
c_disable_warn_bhv_coll => 1,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "blk_mem_40K.mif",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 1,
c_xdevicefamily => "spartan3e",
c_write_depth_b => 40960,
c_write_depth_a => 40960,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 16,
c_addrb_width => 16,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 1,
c_write_width_b => 8,
c_write_width_a => 8,
c_read_depth_b => 40960,
c_read_depth_a => 40960,
c_byte_size => 9,
c_sim_collision_check => "NONE",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_40K
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
-- synthesis translate_on
END blk_mem_40K_a;
| gpl-2.0 | ff1e1767bbb424746cd6bdf26f481352 | 0.542314 | 3.611227 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Encryption_Decryption/bak/rc5_enc_2.bak.vhd | 1 | 3,731 | --RC5 Encryption
--A = A + S[0];
--B = B + S[1];
--for i=1 to 12 do
----A = ((A XOR B) <<< B) + S[2*i];
----B = ((B XOR A) <<< A) + S[2*1+1];
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
USE WORK.RC5_PKG.ALL;
ENTITY rc5_enc IS
PORT (
clr,clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit input
di_vld : IN STD_LOGIC; -- Valid Input
key_rdy : IN STD_LOGIC;
skey : IN rc5_rom_26;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit output
do_rdy : OUT STD_LOGIC --Output is Ready
);
END rc5_enc;
ARCHITECTURE rtl OF rc5_enc IS
SIGNAL i_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); -- round counter
SIGNAL ab_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_pre : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register A
SIGNAL ba_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_pre : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register B
-- RC5 state machine has five states: idle, pre_round, round and ready
SIGNAL state : enc_StateType;
BEGIN
a_pre<=din(63 DOWNTO 32) + skey(0);--A = A + S[0]
b_pre<=din(31 DOWNTO 0) + skey(1); --B = B + S[1]
-- A=((A XOR B)<<<B) + S[2*i];
ab_xor <= a_reg XOR b_reg;--A XOR B
ROT_A_LEFT: rotLeft
PORT MAP(din=>ab_xor,amnt=>b_reg(4 DOWNTO 0),dout=>a_rot);--A <<< B
a<=a_rot + skey(CONV_INTEGER(i_cnt & '0')); --A + S[2*i]
-- B=((B XOR A) <<<A) + S[2*i+1]
ba_xor <= b_reg XOR a; -- B XOR A
ROT_B_LEFT: rotLeft
PORT MAP(din=>ba_xor,amnt=>a(4 DOWNTO 0),dout=>b_rot);--B <<< A
b<=b_rot + skey(CONV_INTEGER(i_cnt & '1')); --B + S[2*i+1]
A_register:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
a_reg<=din(63 DOWNTO 32);
ELSIF(rising_edge(clk)) THEN --clk'EVENT AND clk='1' can introduce error
IF(state=ST_PRE_ROUND) THEN
a_reg<=a_pre;
ELSIF(state=ST_ROUND_OP) THEN
a_reg<=a;
END IF;
END IF;
END PROCESS;
B_register:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
b_reg<=din(31 DOWNTO 0);
ELSIF(rising_edge(clk)) THEN
IF(state=ST_PRE_ROUND) THEN
b_reg<=b_pre;
ELSIF(state=ST_ROUND_OP) THEN
b_reg<=b;
END IF;
END IF;
END PROCESS;
State_Control:
PROCESS(clr, clk)
BEGIN
IF(clr='0') THEN
state<=ST_IDLE;
ELSIF(clk'EVENT AND clk='1') THEN
CASE state IS
WHEN ST_IDLE=> IF(di_vld='1' and key_rdy='1') THEN
state<=ST_PRE_ROUND;
END IF;
WHEN ST_PRE_ROUND=> state<=ST_ROUND_OP;
WHEN ST_ROUND_OP=> IF(i_cnt="1100") THEN
state<=ST_READY;
END IF;
WHEN ST_READY=> IF(di_vld='1' and key_rdy='1') THEN
state<=ST_PRE_ROUND;--can assume new keys and skip idle state
--state<=ST_IDLE;--If Input Changes then restart
END IF;
END CASE;
END IF;
END PROCESS;
round_counter:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
i_cnt<="0001";
ELSIF(rising_edge(clk) AND state=ST_ROUND_OP) THEN
IF(i_cnt="1100") THEN
i_cnt<="0001";
ELSE
i_cnt<=i_cnt+'1';
END IF;
END IF;
END PROCESS;
dout<=a_reg & b_reg;
WITH state SELECT
do_rdy<='1' WHEN ST_READY,
'0' WHEN OTHERS;
END rtl; | lgpl-2.1 | 18362225cc2aefa87cd1a833812ae7e7 | 0.549719 | 2.809488 | false | false | false | false |
nsauzede/cpu86 | papilio2_vga/ipcore_dir/blk_mem_40K.vhd | 3 | 6,130 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2017 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_40K.vhd when simulating
-- the core, blk_mem_40K. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_40K IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END blk_mem_40K;
ARCHITECTURE blk_mem_40K_a OF blk_mem_40K IS
-- synthesis translate_off
COMPONENT wrapped_blk_mem_40K
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_blk_mem_40K USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 16,
c_addrb_width => 16,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 1,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "blk_mem_40K.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 65536,
c_read_depth_b => 65536,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 65536,
c_write_depth_b => 65536,
c_write_mode_a => "READ_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_40K
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END blk_mem_40K_a;
| gpl-2.0 | 5122db1cb8d868258d28d9a84a1471a4 | 0.537357 | 3.816936 | false | false | false | false |
nsauzede/cpu86 | p2_lcd_spi/drigmorn1_top.vhd | 1 | 11,654 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Toplevel : CPU86, 256Byte ROM, 16550 UART, 40K8 SRAM (all blockrams used)--
-------------------------------------------------------------------------------
-- Revision History: --
-- --
-- Date: Revision Author --
-- --
-- 30 Dec 2007 0.1 H. Tiggeler First version --
-- 17 May 2008 0.75 H. Tiggeler Updated for CPU86 ver0.75 --
-- 27 Jun 2008 0.79 H. Tiggeler Changed UART to Opencores 16750 --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY drigmorn1_top IS
PORT(
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
vramaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
spi_cs : out std_logic;
spi_clk : out std_logic;
spi_mosi : out std_logic;
spi_miso : in std_logic;
buttons : in STD_LOGIC_VECTOR (3 downto 0);
leds : out STD_LOGIC_VECTOR (3 downto 0);
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END drigmorn1_top ;
ARCHITECTURE struct OF drigmorn1_top IS
-- Architecture declarations
signal csromn : std_logic;
signal csesramn : std_logic;
signal csisramn : std_logic;
signal csspin : std_logic;
signal csspi : std_logic;
signal csbutled : std_logic := '1';
-- Internal signal declarations
signal leds_b : STD_LOGIC_VECTOR (3 downto 0);
signal vramaddr2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
-- signal vrambase : STD_LOGIC_VECTOR(15 DOWNTO 0):=x"4000";
signal vrambase : STD_LOGIC_VECTOR(15 DOWNTO 0):=x"0000";
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL abus : std_logic_vector(19 DOWNTO 0);
SIGNAL clk : std_logic;
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_esram : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_spi : std_logic_vector(7 DOWNTO 0);
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL rdn : std_logic;
SIGNAL resoutn : std_logic;
SIGNAL sel_s : std_logic_vector(5 DOWNTO 0);
-- SIGNAL sel_s : std_logic_vector(4 DOWNTO 0);
SIGNAL wea : std_logic_VECTOR(0 DOWNTO 0);
SIGNAL wran : std_logic;
SIGNAL wrcom : std_logic;
SIGNAL wspi : std_logic;
SIGNAL wrn : std_logic;
signal rxclk_s : std_logic;
BEGIN
sram_addr <= '0' & abus;
---- sram_data <= dbus_.
-- dbus_esram <= sram_data;
-- sram_data <= (others => 'Z') when rdn='0' else sram_data;
-- sram_ce <= csesramn;
-- sram_we <= wrn;
-- sram_oe <= rdn;
process(csesramn,wrn,rdn,dbus_out,sram_data)
begin
sram_ce <= '1';
sram_we <= '1';
sram_oe <= '1';
sram_data <= (others => 'Z');
if csesramn='0' then
sram_ce <= '0';
if wrn='0' then
sram_data <= dbus_out;
sram_we <= '0';
else
if rdn='0' then
dbus_esram <= sram_data;
sram_oe <= '0';
end if;
end if;
end if;
end process;
leds <= leds_b;
leds_b <= dbus_out(3 downto 0) when (csbutled='0') and (wrn='0') else leds_b;
-- Architecture concurrent statements
-- HDL Embedded Text Block 4 mux
-- dmux 1
process(sel_s,dbus_com1,dbus_in,dbus_rom,dbus_esram,dbus_spi,buttons)
-- process(sel_s,dbus_com1,dbus_in,dbus_rom,dbus_esram,dbus_spi)
begin
case sel_s is
when "011111" => dbus_in_cpu <= dbus_com1; -- UART
when "101111" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when "110111" => dbus_in_cpu <= dbus_in; -- Embedded SRAM
when "111011" => dbus_in_cpu <= dbus_spi; -- SPI
-- when "111101" => dbus_in_cpu <= dbus_esram; -- External SRAM
when "111101" => dbus_in_cpu <= sram_data; -- External SRAM
when "111110" => dbus_in_cpu <= x"0" & buttons; -- butled
when others => dbus_in_cpu <= dbus_in_cpu; -- Embedded SRAM
end case;
end process;
-- HDL Embedded Text Block 7 clogic
clk <= CLOCK_40MHZ;
wrcom <= not wrn;
wea(0)<= not wrn and not csisramn;
wspi<= not wrn;
PIN4 <= resoutn; -- For debug only
-- dbus_in_cpu multiplexer
sel_s <= cscom1 & csromn & csisramn & csspin & csesramn & csbutled;
-- sel_s <= cscom1 & csromn & csisramn & csspin & csesramn;
-- chip_select
-- Comport, uart_16550
-- COM1, 0x3F8-0x3FF
-- cscom1 <= '0' when (abus(15 downto 3)="0000001111111" AND iom='1') else '1';
cscom1 <= '0' when ((abus(15 downto 4)=X"03F") AND iom='1') else '1';
-- SPI, 0x400-0x407
-- csspin <= '0' when (abus(15 downto 3)="0000010000000" AND iom='1') else '1';
csspin <= '0' when ((abus(15 downto 4)=X"040") AND iom='1') else '1';
csspi <= not csspin;
-- BUTLED, 0x500-0x507
csbutled <= '0' when ((abus(15 downto 4)=X"050") AND iom='1') else '1';
-- Bootstrap ROM 256 bytes
-- FFFFF-FF=FFF00
csromn <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
-- external SRAM
-- 0xE0000
-- csesramn <= '0' when ((abus(19 downto 16)=X"1") AND iom='0') else '1'; -- 0x10000
csesramn <= '0' when ((abus(19 downto 16)=X"E") AND iom='0') else '1'; -- 0xE0000
-- csesramn <= '0' when (csromn='1' and csisramn='1' AND iom='0') else '1';
-- csesramn <= not (cscom1 and csromnn and csiramn);
-- internal SRAM
-- below 0x10000
csisramn <= '0' when ((abus(19 downto 16)=X"0") AND iom='0') else '1';
spim0: entity work.spi_master
port map ( clk => clk,
reset => por,
cpu_address => abus(2 downto 0),
cpu_wait => open,
data_in => dbus_out,
data_out => dbus_spi,
enable => csspi,
req_read => '0',
req_write => wspi,
slave_cs => spi_cs,
slave_clk => spi_clk,
slave_mosi => spi_mosi,
slave_miso => spi_miso
);
nmi <= '0';
intr <= '0';
dout <= '0';
dout1 <= '0';
DCDn <= '0';
DSRn <= '0';
RIn <= '0';
por <= NOT(PIN3);
-- Instance port mappings.
U_1 : entity work.cpu86
PORT MAP (
clk => clk,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus,
cpuerror => LED1,
dbus_out => dbus_out,
inta => OPEN,
iom => iom,
rdn => rdn,
resoutn => resoutn,
wran => wran,
wrn => wrn
);
-- U_3 : blk_mem_40K
-- PORT MAP (
-- clka => clk,
-- dina => dbus_out,
-- addra => abus(15 DOWNTO 0),
-- wea => wea,
-- douta => dbus_in
-- );
vramaddr2 <= vramaddr + vrambase;
U_3 : entity work.blk_mem_40K
PORT MAP (
clka => clk,
dina => dbus_out,
addra => abus(15 DOWNTO 0),
wea => wea,
douta => dbus_in,
clkb => clk,
dinb => (others => '0'),
addrb => vramaddr2,
web => (others => '0'),
doutb => vramdata
);
U_2 : entity work.bootstrap
PORT MAP (
abus => abus(7 DOWNTO 0),
dbus => dbus_rom
);
U_0 : entity work.uart_top
PORT MAP (
BR_clk => rxclk_s,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
abus => abus(2 DOWNTO 0),
clk => clk,
csn => cscom1,
dbus_in => dbus_out,
rdn => rdn,
resetn => resoutn,
sRX => RXD,
wrn => wrn,
B_CLK => rxclk_s,
DTRn => OPEN,
IRQ => OPEN,
OUT1n => led2n,
OUT2n => led3n,
RTSn => RTS,
dbus_out => dbus_com1,
stx => TXD
);
END struct;
| gpl-2.0 | 236c4e6f899ac16a93d05d5ee05447f0 | 0.465763 | 3.778859 | false | false | false | false |
nsauzede/cpu86 | p2_lcd_spi/wingbutled.vhd | 1 | 1,013 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:23:33 02/02/2011
-- Design Name:
-- Module Name: wingbutled - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
entity wingbutled is
Port (
io : inout STD_LOGIC_VECTOR (7 downto 0);
buttons : out STD_LOGIC_VECTOR (3 downto 0);
leds : in STD_LOGIC_VECTOR (3 downto 0)
);
end wingbutled;
architecture Behavioral of wingbutled is
begin
io(0) <= leds(3);
io(2) <= leds(2);
io(4) <= leds(1);
io(6) <= leds(0);
io(1) <= 'Z';
io(3) <= 'Z';
io(5) <= 'Z';
io(7) <= 'Z';
buttons(3) <= io(1);
buttons(2) <= io(3);
buttons(1) <= io(5);
buttons(0) <= io(7);
end Behavioral;
| gpl-2.0 | f1706368169a6976b6273f9d2b0a0842 | 0.502468 | 2.961988 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/aaatop.vhd | 1 | 5,481 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:25 02/11/2015
-- Design Name:
-- Module Name: aaatop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
----------------------------------------------------------------------------------
-- LED example, by Jerome Cornet
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity Aaatop is
Port (
CLK,reset : in STD_LOGIC;
txd : inout std_logic;
rxd : in std_logic;
ARD_RESET : out STD_LOGIC;
DUO_SW1 : in STD_LOGIC;
-- DUO_LED : out std_logic;
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
W1A : inout STD_LOGIC_VECTOR (7 downto 0);
W2C : inout STD_LOGIC_VECTOR (15 downto 0);
W2D : inout STD_LOGIC_VECTOR (15 downto 0);
Arduino : inout STD_LOGIC_VECTOR (21 downto 0)
-- Arduino : inout STD_LOGIC_VECTOR (53 downto 0)
);
end Aaatop;
architecture Behavioral of Aaatop is
signal CLOCK_40MHZ : std_logic;
signal CTS : std_logic := '1';
signal PIN3 : std_logic;
signal LED1 : std_logic;
signal LED2N : std_logic;
signal LED3N : std_logic;
signal PIN4 : std_logic;
signal RTS : std_logic;
signal buttons : std_logic_vector(5 downto 0);
signal audio_left : STD_LOGIC;
signal audio_right : STD_LOGIC;
signal ud : STD_LOGIC;
signal rl : STD_LOGIC;
signal enab : STD_LOGIC;
signal vsync : STD_LOGIC;
signal hsync : STD_LOGIC;
signal ck : STD_LOGIC;
signal r : std_logic_vector(5 downto 0);
signal g : std_logic_vector(5 downto 0);
signal b : std_logic_vector(5 downto 0);
signal vramaddr : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal vramdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
COMPONENT drigmorn1_top
PORT(
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
vramaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END component ;
component clk32to40
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end component;
begin
ARD_RESET <= not(DUO_SW1);
CTS <= '1';
-- PIN3 <= not Arduino(40); -- por
-- PIN3 <= reset; -- por
PIN3 <= '1'; -- por
-- Arduino(38) <= Arduino(40);
-- Arduino(42) <= Arduino(44);
-- Arduino(46) <= Arduino(48);
-- Arduino(50) <= Arduino(52);
-- Arduino(38) <= LED1;
-- Arduino(42) <= LED2N;
-- Arduino(46) <= LED3N;
-- Arduino(50) <= '0';
-- sram_addr <= (others => '0');
-- sram_ce <= '0';
-- sram_we <= '0';
-- sram_oe <= '0';
drigmorn1_top0 : drigmorn1_top
PORT map(
sram_addr => sram_addr,
sram_data => sram_data,
sram_ce => sram_ce,
sram_we => sram_we,
sram_oe => sram_oe,
vramaddr => vramaddr,
vramdata => vramdata,
CLOCK_40MHZ => CLOCK_40MHZ,
CTS => CTS,
PIN3 => PIN3,
RXD => RXD,
LED1 => LED1,
LED2N => LED2N,
LED3N => LED3N,
PIN4 => PIN4,
RTS => RTS,
TXD => TXD
);
dcm0: clk32to40
port map
(-- Clock in ports
CLK_IN1 => clk,
-- Clock out ports
CLK_OUT1 => CLOCK_40MHZ);
winglcd0 : entity work.winglcdsndbut Port map(
W1A => w2c,
W1B => w2d,
buttons => buttons,
audio_left => audio_left,
audio_right => audio_right,
ud => ud,
rl => rl,
enab => enab,
vsync => vsync,
hsync => hsync,
ck => ck,
r => r,
g => g,
b => b
);
w1a(0) <= vsync;
w1a(5) <= hsync;
w1a(7) <= r(0);
lcdctl0 : entity work.lcdctl Port map(
clk => CLOCK_40MHZ,
-- clk => clk,
reset=>reset,
vramaddr => vramaddr,
vramdata => vramdata,
ud => ud,
rl => rl,
enab => enab,
vsync => vsync,
hsync => hsync,
ck => ck,
r => r,
g => g,
b => b
);
end Behavioral;
| gpl-2.0 | 591fc139f1ca4490e2b669ee4669d02e | 0.515417 | 3.321818 | false | false | false | false |
freecores/t48 | bench/vhdl/t49_rom-lpm-a.vhd | 1 | 3,689 | -------------------------------------------------------------------------------
--
-- T8x49 ROM
-- Wrapper for ROM model from the LPM library.
--
-- $Id: t49_rom-lpm-a.vhd,v 1.1 2006-06-21 00:58:27 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
architecture lpm of t49_rom is
component lpm_rom
generic (
LPM_WIDTH : positive;
LPM_TYPE : string := "LPM_ROM";
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_FILE : string;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_HINT : string := "UNUSED"
);
port (
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
inclock : in std_logic;
outclock : in std_logic;
memenab : in std_logic;
q : out std_logic_vector(LPM_WIDTH-1 downto 0)
);
end component;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
rom_b : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_TYPE => "LPM_ROM",
LPM_WIDTHAD => 11,
LPM_NUMWORDS => 2 ** 11,
LPM_FILE => "rom_t49.hex",
LPM_ADDRESS_CONTROL => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_HINT => "UNUSED"
)
port map (
address => rom_addr_i,
inclock => clk_i,
outclock => clk_i,
memenab => vdd_s,
q => rom_data_o
);
end lpm;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | de61491264b842ad0cd59cbc28de2119 | 0.578748 | 4.412679 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GN33BXJAZX.vhd | 4 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN33BXJAZX is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN33BXJAZX is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 + 1 ,
width_inr=> 0,
width_outl=> 2,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture; | mit | de6b325f22eab69b546bac75399978fc | 0.648803 | 3.066434 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_SInitDelay.vhd | 20 | 3,601 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 7.2)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2007 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SInitDelay is
generic (
lpm_width : positive :=8;
lpm_delay : positive :=2;
SequenceLength : positive :=1;
SequenceValue : std_logic_vector :="1";
ResetValue : std_logic_vector :="00000001"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic ;
ena : in std_logic :='1';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
sclr : in std_logic :='0';
result : out std_logic_vector(lpm_width-1 downto 0) :=(others=>'0')
);
end alt_dspbuilder_SInitDelay;
architecture SInitDelay_SYNTH of alt_dspbuilder_SInitDelay is
type StdUArray is array (lpm_delay-1 downto 0) of std_logic_vector (lpm_width-1 downto 0);
signal DelayLine : StdUArray;
signal dataa_int : std_logic_vector(lpm_width-1 downto 0);
signal seqenable : std_logic ;
signal enadff : std_logic ;
signal aclr_i : std_logic ;
begin
aclr_i <= aclr or user_aclr;
u0: alt_dspbuilder_sAltrPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion , width=> lpm_width)
port map (d => dataa, r => dataa_int);
gnoseq: if ((SequenceLength=1) and (SequenceValue="1")) generate
enadff <= ena;
end generate gnoseq;
gseq: if not ((SequenceLength=1) and (SequenceValue="1")) generate
u:alt_dspbuilder_vecseq generic map (SequenceLength=>SequenceLength,SequenceValue=>SequenceValue)
port map (clock=>clock, ena=>ena, aclr=>aclr_i, sclr=>sclr, yout=> seqenable);
enadff <= seqenable and ena;
end generate gseq;
gen1:if lpm_delay=1 generate
process(clock, aclr_i)
begin
if aclr_i='1' then
result <= ResetValue;
elsif clock'event and clock='1' then
if (sclr ='1') then
result <= ResetValue;
elsif enadff ='1' then
result <= dataa_int;
end if;
end if;
end process;
end generate;
gen2:if lpm_delay>1 generate
process(clock, aclr_i)
begin
if aclr_i='1' then
DelayLine <= (others => ResetValue);
elsif clock'event and clock='1' then
if (sclr='1') then
DelayLine <= (others => ResetValue);
elsif (enadff='1') then
DelayLine(0) <= dataa_int;
for i in 1 to lpm_delay-1 loop
DelayLine(i) <= DelayLine(i-1);
end loop;
end if;
end if;
end process;
result <= DelayLine(lpm_delay-1);
end generate;
end SInitDelay_SYNTH;
| mit | b547aa6c83b5778ff30a60b6dc7255e7 | 0.654263 | 3.565347 | false | false | false | false |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_v_tc_0_0/sim/tutorial_v_tc_0_0.vhd | 1 | 15,469 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:v_tc:6.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY v_tc_v6_1;
USE v_tc_v6_1.v_tc;
ENTITY tutorial_v_tc_0_0 IS
PORT (
clk : IN STD_LOGIC;
clken : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
gen_clken : IN STD_LOGIC;
hsync_out : OUT STD_LOGIC;
hblank_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
vblank_out : OUT STD_LOGIC;
active_video_out : OUT STD_LOGIC;
resetn : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
irq : OUT STD_LOGIC;
fsync_in : IN STD_LOGIC;
fsync_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END tutorial_v_tc_0_0;
ARCHITECTURE tutorial_v_tc_0_0_arch OF tutorial_v_tc_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_v_tc_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT v_tc IS
GENERIC (
C_HAS_AXI4_LITE : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_GEN_INTERLACED : INTEGER;
C_GEN_HACTIVE_SIZE : INTEGER;
C_GEN_VACTIVE_SIZE : INTEGER;
C_GEN_CPARITY : INTEGER;
C_GEN_FIELDID_POLARITY : INTEGER;
C_GEN_VBLANK_POLARITY : INTEGER;
C_GEN_HBLANK_POLARITY : INTEGER;
C_GEN_VSYNC_POLARITY : INTEGER;
C_GEN_HSYNC_POLARITY : INTEGER;
C_GEN_AVIDEO_POLARITY : INTEGER;
C_GEN_ACHROMA_POLARITY : INTEGER;
C_GEN_VIDEO_FORMAT : INTEGER;
C_GEN_HFRAME_SIZE : INTEGER;
C_GEN_F0_VFRAME_SIZE : INTEGER;
C_GEN_F1_VFRAME_SIZE : INTEGER;
C_GEN_HSYNC_START : INTEGER;
C_GEN_HSYNC_END : INTEGER;
C_GEN_F0_VBLANK_HSTART : INTEGER;
C_GEN_F0_VBLANK_HEND : INTEGER;
C_GEN_F0_VSYNC_VSTART : INTEGER;
C_GEN_F0_VSYNC_VEND : INTEGER;
C_GEN_F0_VSYNC_HSTART : INTEGER;
C_GEN_F0_VSYNC_HEND : INTEGER;
C_GEN_F1_VBLANK_HSTART : INTEGER;
C_GEN_F1_VBLANK_HEND : INTEGER;
C_GEN_F1_VSYNC_VSTART : INTEGER;
C_GEN_F1_VSYNC_VEND : INTEGER;
C_GEN_F1_VSYNC_HSTART : INTEGER;
C_GEN_F1_VSYNC_HEND : INTEGER;
C_FSYNC_HSTART0 : INTEGER;
C_FSYNC_VSTART0 : INTEGER;
C_FSYNC_HSTART1 : INTEGER;
C_FSYNC_VSTART1 : INTEGER;
C_FSYNC_HSTART2 : INTEGER;
C_FSYNC_VSTART2 : INTEGER;
C_FSYNC_HSTART3 : INTEGER;
C_FSYNC_VSTART3 : INTEGER;
C_FSYNC_HSTART4 : INTEGER;
C_FSYNC_VSTART4 : INTEGER;
C_FSYNC_HSTART5 : INTEGER;
C_FSYNC_VSTART5 : INTEGER;
C_FSYNC_HSTART6 : INTEGER;
C_FSYNC_VSTART6 : INTEGER;
C_FSYNC_HSTART7 : INTEGER;
C_FSYNC_VSTART7 : INTEGER;
C_FSYNC_HSTART8 : INTEGER;
C_FSYNC_VSTART8 : INTEGER;
C_FSYNC_HSTART9 : INTEGER;
C_FSYNC_VSTART9 : INTEGER;
C_FSYNC_HSTART10 : INTEGER;
C_FSYNC_VSTART10 : INTEGER;
C_FSYNC_HSTART11 : INTEGER;
C_FSYNC_VSTART11 : INTEGER;
C_FSYNC_HSTART12 : INTEGER;
C_FSYNC_VSTART12 : INTEGER;
C_FSYNC_HSTART13 : INTEGER;
C_FSYNC_VSTART13 : INTEGER;
C_FSYNC_HSTART14 : INTEGER;
C_FSYNC_VSTART14 : INTEGER;
C_FSYNC_HSTART15 : INTEGER;
C_FSYNC_VSTART15 : INTEGER;
C_MAX_PIXELS : INTEGER;
C_MAX_LINES : INTEGER;
C_NUM_FSYNCS : INTEGER;
C_INTERLACE_EN : INTEGER;
C_GEN_AUTO_SWITCH : INTEGER;
C_DETECT_EN : INTEGER;
C_SYNC_EN : INTEGER;
C_GENERATE_EN : INTEGER;
C_DET_HSYNC_EN : INTEGER;
C_DET_VSYNC_EN : INTEGER;
C_DET_HBLANK_EN : INTEGER;
C_DET_VBLANK_EN : INTEGER;
C_DET_AVIDEO_EN : INTEGER;
C_DET_ACHROMA_EN : INTEGER;
C_GEN_HSYNC_EN : INTEGER;
C_GEN_VSYNC_EN : INTEGER;
C_GEN_HBLANK_EN : INTEGER;
C_GEN_VBLANK_EN : INTEGER;
C_GEN_AVIDEO_EN : INTEGER;
C_GEN_ACHROMA_EN : INTEGER;
C_GEN_FIELDID_EN : INTEGER;
C_DET_FIELDID_EN : INTEGER
);
PORT (
clk : IN STD_LOGIC;
clken : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
det_clken : IN STD_LOGIC;
gen_clken : IN STD_LOGIC;
intc_if : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
field_id_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
hblank_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
vblank_in : IN STD_LOGIC;
active_video_in : IN STD_LOGIC;
active_chroma_in : IN STD_LOGIC;
field_id_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
hblank_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
vblank_out : OUT STD_LOGIC;
active_video_out : OUT STD_LOGIC;
active_chroma_out : OUT STD_LOGIC;
resetn : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
irq : OUT STD_LOGIC;
fsync_in : IN STD_LOGIC;
fsync_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT v_tc;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF clken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 clken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 s_axi_aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF hsync_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF hblank_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out HBLANK";
ATTRIBUTE X_INTERFACE_INFO OF vsync_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF vblank_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out VBLANK";
ATTRIBUTE X_INTERFACE_INFO OF active_video_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 resetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RREADY";
ATTRIBUTE X_INTERFACE_INFO OF irq: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IRQ INTERRUPT";
BEGIN
U0 : v_tc
GENERIC MAP (
C_HAS_AXI4_LITE => 1,
C_HAS_INTC_IF => 0,
C_GEN_INTERLACED => 0,
C_GEN_HACTIVE_SIZE => 1920,
C_GEN_VACTIVE_SIZE => 1080,
C_GEN_CPARITY => 0,
C_GEN_FIELDID_POLARITY => 1,
C_GEN_VBLANK_POLARITY => 1,
C_GEN_HBLANK_POLARITY => 1,
C_GEN_VSYNC_POLARITY => 1,
C_GEN_HSYNC_POLARITY => 1,
C_GEN_AVIDEO_POLARITY => 1,
C_GEN_ACHROMA_POLARITY => 1,
C_GEN_VIDEO_FORMAT => 2,
C_GEN_HFRAME_SIZE => 2200,
C_GEN_F0_VFRAME_SIZE => 1125,
C_GEN_F1_VFRAME_SIZE => 1125,
C_GEN_HSYNC_START => 2008,
C_GEN_HSYNC_END => 2052,
C_GEN_F0_VBLANK_HSTART => 1920,
C_GEN_F0_VBLANK_HEND => 1920,
C_GEN_F0_VSYNC_VSTART => 1083,
C_GEN_F0_VSYNC_VEND => 1088,
C_GEN_F0_VSYNC_HSTART => 1920,
C_GEN_F0_VSYNC_HEND => 1920,
C_GEN_F1_VBLANK_HSTART => 1920,
C_GEN_F1_VBLANK_HEND => 1920,
C_GEN_F1_VSYNC_VSTART => 1083,
C_GEN_F1_VSYNC_VEND => 1088,
C_GEN_F1_VSYNC_HSTART => 1920,
C_GEN_F1_VSYNC_HEND => 1920,
C_FSYNC_HSTART0 => 0,
C_FSYNC_VSTART0 => 0,
C_FSYNC_HSTART1 => 0,
C_FSYNC_VSTART1 => 0,
C_FSYNC_HSTART2 => 0,
C_FSYNC_VSTART2 => 0,
C_FSYNC_HSTART3 => 0,
C_FSYNC_VSTART3 => 0,
C_FSYNC_HSTART4 => 0,
C_FSYNC_VSTART4 => 0,
C_FSYNC_HSTART5 => 0,
C_FSYNC_VSTART5 => 0,
C_FSYNC_HSTART6 => 0,
C_FSYNC_VSTART6 => 0,
C_FSYNC_HSTART7 => 0,
C_FSYNC_VSTART7 => 0,
C_FSYNC_HSTART8 => 0,
C_FSYNC_VSTART8 => 0,
C_FSYNC_HSTART9 => 0,
C_FSYNC_VSTART9 => 0,
C_FSYNC_HSTART10 => 0,
C_FSYNC_VSTART10 => 0,
C_FSYNC_HSTART11 => 0,
C_FSYNC_VSTART11 => 0,
C_FSYNC_HSTART12 => 0,
C_FSYNC_VSTART12 => 0,
C_FSYNC_HSTART13 => 0,
C_FSYNC_VSTART13 => 0,
C_FSYNC_HSTART14 => 0,
C_FSYNC_VSTART14 => 0,
C_FSYNC_HSTART15 => 0,
C_FSYNC_VSTART15 => 0,
C_MAX_PIXELS => 4096,
C_MAX_LINES => 4096,
C_NUM_FSYNCS => 1,
C_INTERLACE_EN => 0,
C_GEN_AUTO_SWITCH => 0,
C_DETECT_EN => 0,
C_SYNC_EN => 0,
C_GENERATE_EN => 1,
C_DET_HSYNC_EN => 1,
C_DET_VSYNC_EN => 1,
C_DET_HBLANK_EN => 1,
C_DET_VBLANK_EN => 1,
C_DET_AVIDEO_EN => 1,
C_DET_ACHROMA_EN => 0,
C_GEN_HSYNC_EN => 1,
C_GEN_VSYNC_EN => 1,
C_GEN_HBLANK_EN => 1,
C_GEN_VBLANK_EN => 1,
C_GEN_AVIDEO_EN => 1,
C_GEN_ACHROMA_EN => 0,
C_GEN_FIELDID_EN => 0,
C_DET_FIELDID_EN => 0
)
PORT MAP (
clk => clk,
clken => clken,
s_axi_aclk => s_axi_aclk,
s_axi_aclken => s_axi_aclken,
det_clken => '1',
gen_clken => gen_clken,
field_id_in => '0',
hsync_in => '0',
hblank_in => '0',
vsync_in => '0',
vblank_in => '0',
active_video_in => '0',
active_chroma_in => '0',
hsync_out => hsync_out,
hblank_out => hblank_out,
vsync_out => vsync_out,
vblank_out => vblank_out,
active_video_out => active_video_out,
resetn => resetn,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
irq => irq,
fsync_in => fsync_in,
fsync_out => fsync_out
);
END tutorial_v_tc_0_0_arch;
| gpl-2.0 | 1071441fb32e276c720420e1e9d31395 | 0.639214 | 3.185544 | false | false | false | false |
Bourgeoisie/ECE368-RISC16 | 368RISC/ipcore_dir/instruct_blk_mem_gen_v7_3/example_design/instruct_blk_mem_gen_v7_3_prod.vhd | 1 | 10,371 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: instruct_blk_mem_gen_v7_3_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : instruct_blk_mem_gen_v7_3.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 20
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 16
-- C_READ_DEPTH_A : 16
-- C_ADDRA_WIDTH : 4
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 16
-- C_READ_DEPTH_B : 16
-- C_ADDRB_WIDTH : 4
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY instruct_blk_mem_gen_v7_3_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END instruct_blk_mem_gen_v7_3_prod;
ARCHITECTURE xilinx OF instruct_blk_mem_gen_v7_3_prod IS
COMPONENT instruct_blk_mem_gen_v7_3_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : instruct_blk_mem_gen_v7_3_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| mit | d591018971eba62cacc1a5f06fde5805 | 0.494359 | 3.782276 | false | false | false | false |
freecores/t48 | bench/vhdl/tb_t8048_t8243.vhd | 1 | 10,222 | -------------------------------------------------------------------------------
--
-- The testbench for t8048 driving a t8243.
--
-- $Id: tb_t8048_t8243.vhd,v 1.1 2006-07-13 22:55:10 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb_t8048_t8243 is
end tb_t8048_t8243;
use work.t48_core_comp_pack.generic_ram_ena;
use work.t48_system_comp_pack.t8048;
use work.t8243_comp_pack.t8243;
use work.t48_tb_pack.all;
architecture behav of tb_t8048_t8243 is
-- clock period, 11 MHz
constant period_c : time := 90 ns;
component lpm_rom
generic (
LPM_WIDTH : positive;
LPM_TYPE : string := "LPM_ROM";
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_FILE : string;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_HINT : string := "UNUSED"
);
port (
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
inclock : in std_logic;
outclock : in std_logic;
memenab : in std_logic;
q : out std_logic_vector(LPM_WIDTH-1 downto 0)
);
end component;
signal xtal_s : std_logic;
signal res_n_s : std_logic;
signal int_n_s : std_logic;
signal ale_s : std_logic;
signal psen_n_s : std_logic;
signal prog_n_s : std_logic;
signal p1_b : std_logic_vector( 7 downto 0);
signal p2_b : std_logic_vector( 7 downto 0);
signal p4_b : std_logic_vector( 3 downto 0);
signal p5_b : std_logic_vector( 3 downto 0);
signal db_b : std_logic_vector( 7 downto 0);
signal ext_mem_addr_s : std_logic_vector(11 downto 0);
signal ext_ram_data_from_s : std_logic_vector( 7 downto 0);
signal ext_ram_we_s : std_logic;
signal ext_rom_data_s : std_logic_vector( 7 downto 0);
signal rd_n_s : std_logic;
signal wr_n_s : std_logic;
signal zero_s : std_logic;
signal one_s : std_logic;
begin
zero_s <= '0';
one_s <= '1';
p2_b <= (others => 'H');
p1_b <= (others => 'H');
-----------------------------------------------------------------------------
-- External ROM, 3k bytes
-- Initialized by file t48_ext_rom.hex.
-----------------------------------------------------------------------------
ext_rom_b : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_TYPE => "LPM_ROM",
LPM_WIDTHAD => 12,
LPM_NUMWORDS => 3 * (2 ** 10),
LPM_FILE => "rom_t48_ext.hex",
LPM_ADDRESS_CONTROL => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_HINT => "UNUSED"
)
port map (
address => ext_mem_addr_s,
inclock => xtal_s,
outclock => zero_s, -- unused
memenab => one_s,
q => ext_rom_data_s
);
ext_ram_b : generic_ram_ena
generic map (
addr_width_g => 8,
data_width_g => 8
)
port map (
clk_i => xtal_s,
a_i => ext_mem_addr_s(7 downto 0),
we_i => ext_ram_we_s,
ena_i => one_s,
d_i => db_b,
d_o => ext_ram_data_from_s
);
t8048_b : t8048
port map (
xtal_i => xtal_s,
reset_n_i => res_n_s,
t0_b => p1_b(0),
int_n_i => int_n_s,
ea_i => zero_s,
rd_n_o => rd_n_s,
psen_n_o => psen_n_s,
wr_n_o => wr_n_s,
ale_o => ale_s,
db_b => db_b,
t1_i => p1_b(1),
p2_b => p2_b,
p1_b => p1_b,
prog_n_o => prog_n_s
);
t8243_b : t8243
port map (
cs_n_i => zero_s,
prog_n_i => prog_n_s,
p2_b => p2_b(3 downto 0),
p4_b => p4_b,
p5_b => p5_b,
p6_b => p4_b,
p7_b => p5_b
);
p4_b <= (others => 'H');
p5_b <= (others => 'H');
-----------------------------------------------------------------------------
-- Read from external memory
--
db_b <= ext_rom_data_s
when psen_n_s = '0' else
(others => 'Z');
db_b <= ext_ram_data_from_s
when rd_n_s = '0' else
(others => 'Z');
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- External RAM access signals
--
ext_ram: process (wr_n_s,
ale_s,
p2_b,
db_b)
begin
-- lowest 1k of external ROM is not used
ext_mem_addr_s(11 downto 8) <= To_X01Z(p2_b(3 downto 0));
if ale_s'event and ale_s = '0' then
if not is_X(db_b) then
ext_mem_addr_s(7 downto 0) <= db_b;
else
ext_mem_addr_s(7 downto 0) <= (others => '0');
end if;
end if;
if wr_n_s'event and wr_n_s = '1' then
ext_ram_we_s <= '0';
end if;
if wr_n_s'event and wr_n_s = '0' then
ext_ram_we_s <= '1';
end if;
end process ext_ram;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The clock generator
--
clk_gen: process
begin
xtal_s <= '0';
wait for period_c/2;
xtal_s <= '1';
wait for period_c/2;
end process clk_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The reset generator
--
res_gen: process
begin
res_n_s <= '0';
wait for 5 * period_c;
res_n_s <= '1';
wait;
end process res_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The interrupt generator
--
int_gen: process
begin
int_n_s <= '1';
wait for 750 * period_c;
int_n_s <= '0';
wait for 45 * period_c;
end process int_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- End of simulation detection
--
eos: process
begin
outer: loop
wait on tb_accu_s;
if tb_accu_s = "10101010" then
wait on tb_accu_s;
if tb_accu_s = "01010101" then
wait on tb_accu_s;
if tb_accu_s = "00000001" then
-- wait for instruction strobe of this move
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
-- wait for next strobe
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
assert false
report "Simulation Result: PASS."
severity note;
else
assert false
report "Simulation Result: FAIL."
severity note;
end if;
assert false
report "End of simulation reached."
severity failure;
end if;
end if;
end loop;
end process eos;
--
-----------------------------------------------------------------------------
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.7 2006/06/24 00:51:50 arniml
-- comment added about lower 1k of external ROM
--
-- Revision 1.6 2006/06/22 00:21:28 arniml
-- added external ROM
--
-- Revision 1.5 2006/06/21 01:04:05 arniml
-- replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom/t3x_rom
--
-- Revision 1.4 2004/04/18 19:00:58 arniml
-- connect T0 and T1 to P1
--
-- Revision 1.3 2004/04/14 20:57:44 arniml
-- wait for instruction strobe after final end-of-simulation detection
-- this ensures that the last mov instruction is part of the dump and
-- enables 100% matching with i8039 simulator
--
-- Revision 1.2 2004/03/26 22:39:28 arniml
-- enhance simulation result string
--
-- Revision 1.1 2004/03/24 21:42:10 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 02986f1cbe5ae9c38f1649628d4cfa78 | 0.486108 | 3.771956 | false | false | false | false |
lelongdunet/dspunit | rtl/regBtoW.vhd | 2 | 4,459 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity regBtoW is
generic (
addr_width : integer
);
port (
--@inputs
reset : in std_logic;
clk : in std_logic;
data_in : in std_logic_vector(7 downto 0);
addr_in : in std_logic_vector(addr_width downto 0);
wr_in : in std_logic;
regbank_sel : in std_logic;
--@outputs;
data_out : out std_logic_vector(15 downto 0);
addr_out : out std_logic_vector((addr_width - 1) downto 0);
wr_out : out std_logic
);
end regBtoW;
--=----------------------------------------------------------------------------
architecture archi_BtoWreg of regBtoW is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_firstbyte_ok : std_logic;
signal s_addr_out : std_logic_vector((addr_width - 1) downto 0);
signal s_data_low_out : std_logic_vector(7 downto 0);
signal s_data_high_out : std_logic_vector(7 downto 0);
begin -- archs_BtoWreg
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_conv : process (clk, reset)
begin -- process p_conv
if reset = '0' then -- asynchronous reset
s_addr_out <= (others => '1');
addr_out <= (others => '1');
s_data_low_out <= (others => '0');
s_data_high_out <= (others => '0');
wr_out <= '0';
elsif rising_edge(clk) then -- rising clock edge
if (wr_in = '1' and regbank_sel = '1') then
if s_firstbyte_ok = '1' then
s_addr_out <= addr_in(addr_width downto 1);
addr_out <= addr_in(addr_width downto 1);
s_data_high_out <= data_in;
wr_out <= '0';
elsif(s_addr_out = addr_in(addr_width downto 1)) then
s_data_low_out <= data_in;
addr_out <= s_addr_out;
s_addr_out <= (others => '1');
wr_out <= '1';
else
wr_out <= '0';
s_addr_out <= (others => '1');
addr_out <= addr_in(addr_width downto 1);
end if;
else
addr_out <= addr_in(addr_width downto 1);
wr_out <= '0';
end if;
end if;
end process p_conv;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_firstbyte_ok <= addr_in(0);
data_out <= s_data_high_out & s_data_low_out;
end archi_BtoWreg;
-------------------------------------------------------------------------------
| gpl-3.0 | 76fb8fa0faf7ca9a244e200b7cca4aeb | 0.414891 | 4.540733 | false | false | false | false |
freecores/t48 | rtl/vhdl/alu.vhd | 1 | 13,640 | -------------------------------------------------------------------------------
--
-- The Arithmetic Logic Unit (ALU).
-- It contains the ALU core plus the Accumulator and the Temp Reg.
--
-- $Id: alu.vhd,v 1.9 2005-06-11 10:08:43 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
use work.t48_alu_pack.alu_op_t;
entity t48_alu is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
write_accu_i : in boolean;
write_shadow_i : in boolean;
write_temp_reg_i : in boolean;
read_alu_i : in boolean;
-- Decoder Interface ------------------------------------------------------
carry_i : in std_logic;
carry_o : out std_logic;
aux_carry_o : out std_logic;
alu_op_i : in alu_op_t;
use_carry_i : in boolean;
da_high_i : in boolean;
da_overflow_o : out boolean;
accu_low_i : in boolean;
p06_temp_reg_i : in boolean;
p60_temp_reg_i : in boolean
);
end t48_alu;
library ieee;
use ieee.numeric_std.all;
use work.t48_pack.clk_active_c;
use work.t48_pack.res_active_c;
use work.t48_pack.bus_idle_level_c;
use work.t48_pack.nibble_t;
use work.t48_alu_pack.all;
-- pragma translate_off
use work.t48_tb_pack.tb_accu_s;
-- pragma translate_on
architecture rtl of t48_alu is
-- the Accumulator and Temp Reg
signal accumulator_q,
accu_shadow_q,
temp_req_q : word_t;
-- inputs to the ALU core
signal in_a_s,
in_b_s : word_t;
-- output of the ALU core
signal data_s : word_t;
signal add_result_s : alu_operand_t;
begin
-----------------------------------------------------------------------------
-- Process working_regs
--
-- Purpose:
-- Implements the working registers:
-- + Accumulator
-- + Temp Reg
--
working_regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
accumulator_q <= (others => '0');
accu_shadow_q <= (others => '0');
temp_req_q <= (others => '0');
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
if write_accu_i then
if accu_low_i then
accumulator_q(nibble_t'range) <= data_i(nibble_t'range);
else
accumulator_q <= data_i;
end if;
end if;
if write_shadow_i then
-- write shadow directly from t48 data bus
accu_shadow_q <= data_i;
else
-- default: update shadow Accumulator from real Accumulator
accu_shadow_q <= accumulator_q;
end if;
if p06_temp_reg_i then
-- low nibble of DA sequence
temp_req_q <= "00000110";
elsif p60_temp_reg_i then
-- high nibble of DA sequence
temp_req_q <= "01100000";
elsif write_temp_reg_i then
-- normal load from T48 bus
temp_req_q <= data_i;
end if;
end if;
end if;
end process working_regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Build the inputs to the ALU core.
-- Input A:
-- Unary operators use only Input A.
-- Is always fed from the shadow Accumulator.
-- Assumption: It never happens that the Accumulator is written and then
-- read for an ALU operation in the next cycle.
-- Its contents can thus be staged through the shadow Accu.
-- Input B:
-- Is always fed from the Temp Reg.
-----------------------------------------------------------------------------
in_a_s <= accu_shadow_q;
in_b_s <= temp_req_q;
-----------------------------------------------------------------------------
-- Process alu_core
--
-- Purpose:
-- Implements the ALU core.
-- All operations defined in alu_op_t are handled here.
--
alu_core: process (in_a_s,
in_b_s,
alu_op_i,
carry_i,
use_carry_i,
add_result_s)
begin
-- default assigments
data_s <= (others => '0');
carry_o <= '0';
case alu_op_i is
-- Operation: AND -------------------------------------------------------
when ALU_AND =>
data_s <= in_a_s and in_b_s;
-- Operation: OR --------------------------------------------------------
when ALU_OR =>
data_s <= in_a_s or in_b_s;
-- Operation: XOR -------------------------------------------------------
when ALU_XOR =>
data_s <= in_a_s xor in_b_s;
-- Operation: Add -------------------------------------------------------
when ALU_ADD =>
data_s <= add_result_s(data_s'range);
carry_o <= add_result_s(add_result_s'high);
-- Operation: CPL -------------------------------------------------------
when ALU_CPL =>
data_s <= not in_a_s;
-- Operation: CLR -------------------------------------------------------
when ALU_CLR =>
data_s <= (others => '0');
-- Operation: RL --------------------------------------------------------
when ALU_RL =>
data_s(7 downto 1) <= in_a_s(6 downto 0);
carry_o <= in_a_s(7);
if use_carry_i then
data_s(0) <= carry_i;
else
data_s(0) <= in_a_s(7);
end if;
-- Operation: RR --------------------------------------------------------
when ALU_RR =>
data_s(6 downto 0) <= in_a_s(7 downto 1);
carry_o <= in_a_s(0);
if use_carry_i then
data_s(7) <= carry_i;
else
data_s(7) <= in_a_s(0);
end if;
-- Operation: Swap ------------------------------------------------------
when ALU_SWAP =>
data_s(3 downto 0) <= in_a_s(7 downto 4);
data_s(7 downto 4) <= in_a_s(3 downto 0);
-- Operation: DEC -------------------------------------------------------
when ALU_DEC =>
data_s <= add_result_s(data_s'range);
-- Operation: INC -------------------------------------------------------
when ALU_INC =>
data_s <= add_result_s(data_s'range);
-- Operation CONCAT -----------------------------------------------------
when ALU_CONCAT =>
data_s <= in_b_s(7 downto 4) & in_a_s(3 downto 0);
-- Operation: NOP -------------------------------------------------------
when ALU_NOP =>
data_s <= in_a_s;
when others =>
-- pragma translate_off
assert false
report "Unknown ALU operation selected!"
severity error;
-- pragma translate_on
end case;
end process alu_core;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process adder
--
-- Purpose:
-- Implements the adder used by several instructions.
-- This way of modelling the adder forces resource sharing of:
-- * ADD
-- * INC
-- * DEC
--
adder: process (in_a_s,
in_b_s,
alu_op_i,
carry_i,
use_carry_i)
variable add_a_v, add_b_v : alu_operand_t;
variable c_v : alu_operand_t;
variable result_v : UNSIGNED(alu_operand_t'range);
variable aux_c_v : std_logic_vector(1 downto 0);
begin
-- Carry Selection --------------------------------------------------------
c_v := (others => '0');
if use_carry_i and carry_i = '1' then
c_v(0) := '1';
end if;
-- Operand Selection ------------------------------------------------------
-- defaults for ADD
add_a_v := '0' & in_a_s;
add_b_v := '0' & in_b_s;
case alu_op_i is
when ALU_INC =>
add_b_v := (others => '0');
add_b_v(0) := '1';
when ALU_DEC =>
add_b_v := (others => '1');
when others =>
null;
end case;
-- The Adder --------------------------------------------------------------
result_v := UNSIGNED(add_a_v) +
UNSIGNED(add_b_v) +
UNSIGNED(c_v);
add_result_s <= std_logic_vector(result_v);
-- Auxiliary Carry --------------------------------------------------------
aux_c_v := in_a_s(4) & in_b_s(4);
aux_carry_o <= '0';
case aux_c_v is
when "00" | "11" =>
if result_v(4) = '1' then
aux_carry_o <= '1';
end if;
when "01" | "10" =>
if result_v(4) = '0' then
aux_carry_o <= '1';
end if;
when others =>
null;
end case;
end process adder;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process da_overflow
--
-- Purpose:
-- Detect overflow situation during DA sequence.
--
da_overflow: process (accu_shadow_q,
da_high_i)
variable da_nibble_v : nibble_t;
function da_overflow_f(data : in nibble_t) return boolean is
variable overflow_v : boolean;
begin
case data is
when "1010" |
"1011" |
"1100" |
"1101" |
"1110" |
"1111" =>
overflow_v := true;
when others =>
overflow_v := false;
end case;
return(overflow_v);
end;
begin
if da_high_i then
da_nibble_v := accu_shadow_q(7 downto 4);
else
da_nibble_v := accu_shadow_q(3 downto 0);
end if;
da_overflow_o <= da_overflow_f(da_nibble_v);
end process da_overflow;
--
-----------------------------------------------------------------------------
-- pragma translate_off
-----------------------------------------------------------------------------
-- Testbench support.
-----------------------------------------------------------------------------
tb_accu_s <= accumulator_q;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Output Multiplexer.
-----------------------------------------------------------------------------
data_o <= data_s
when read_alu_i else
(others => bus_idle_level_c);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.8 2004/04/24 23:43:56 arniml
-- move from std_logic_arith to numeric_std
--
-- Revision 1.7 2004/04/07 22:09:03 arniml
-- remove unused signals
--
-- Revision 1.6 2004/04/07 20:56:23 arniml
-- default assignment for aux_carry_o
--
-- Revision 1.5 2004/04/06 20:21:53 arniml
-- fix sensitivity list
--
-- Revision 1.4 2004/04/06 18:10:41 arniml
-- rework adder and force resource sharing between ADD, INC and DEC
--
-- Revision 1.3 2004/04/04 14:18:52 arniml
-- add measures to implement XCHD
--
-- Revision 1.2 2004/03/28 21:08:51 arniml
-- support for DA instruction
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 51d586c6ee9280d2597cb597d69df12d | 0.453446 | 4.161074 | false | false | false | false |
Bourgeoisie/ECE368-RISC16 | 368RISC/ipcore_dir/instruct_blk_mem_gen_v7_3/simulation/instruct_blk_mem_gen_v7_3_synth.vhd | 1 | 8,987 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: instruct_blk_mem_gen_v7_3_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY instruct_blk_mem_gen_v7_3_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE instruct_blk_mem_gen_v7_3_synth_ARCH OF instruct_blk_mem_gen_v7_3_synth IS
COMPONENT instruct_blk_mem_gen_v7_3_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: instruct_blk_mem_gen_v7_3_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
| mit | 1cbe15296bc18da8875eda293e138772 | 0.570491 | 3.552174 | false | false | false | false |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_ftch_mngr.vhd | 1 | 26,963 | -------------------------------------------------------------------------------
-- axi_sg_ftch_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_mngr.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/20/10 v1_00_a
-- ^^^^^^
-- CR568950
-- Qualified reseting of sg_idle from axi_sg_ftch_pntr with associated channel's
-- flush control.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_nxtdesc_wren : in std_logic ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_nxtdesc_wren : in std_logic ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
--
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_ftch_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_cmnd_wr_i : std_logic := '0';
signal ftch_cmnd_data_i : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0)
:= (others => '0');
signal ch1_sg_idle : std_logic := '0';
signal ch1_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_sg_idle : std_logic := '0';
signal ch2_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ftch_done : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal ftch_interr : std_logic := '0';
signal ftch_slverr : std_logic := '0';
signal ftch_decerr : std_logic := '0';
signal ftch_error_early : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_cmnd_wr <= ftch_cmnd_wr_i;
ftch_cmnd_data <= ftch_cmnd_data_i;
ftch_error <= ftch_error_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
I_FTCH_SG : entity axi_vdma_v6_2.axi_sg_ftch_sm
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
updt_error => updt_error ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_updt_done => ch1_updt_done ,
ch1_desc_flush => ch1_desc_flush ,
ch1_sg_idle => ch1_sg_idle ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_fetch_address => ch1_fetch_address ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_interr_set => ch1_ftch_interr_set ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_updt_done => ch2_updt_done ,
ch2_desc_flush => ch2_desc_flush ,
ch2_sg_idle => ch2_sg_idle ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_fetch_address => ch2_fetch_address ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_interr_set => ch2_ftch_interr_set ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_ftch_pause => ch2_ftch_pause ,
-- Transfer Request
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Transfer Status
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_stale_desc => ftch_stale_desc ,
ftch_error_addr => ftch_error_addr ,
ftch_error_early => ftch_error_early
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Pointer Manager
-------------------------------------------------------------------------------
I_FTCH_PNTR_MNGR : entity axi_vdma_v6_2.axi_sg_ftch_pntr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
nxtdesc => nxtdesc ,
-------------------------------
-- CHANNEL 1
-------------------------------
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,--CR568950
-- CURDESC update on run/stop assertion (from ftch_sm)
ch1_curdesc => ch1_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch1_fetch_address => ch1_fetch_address ,
ch1_sg_idle => ch1_sg_idle ,
-------------------------------
-- CHANNEL 2
-------------------------------
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,--CR568950
-- CURDESC update on run/stop assertion (from ftch_sm)
ch2_curdesc => ch2_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren ,
ch2_taildesc => ch2_taildesc ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch2_fetch_address => ch2_fetch_address ,
ch2_sg_idle => ch2_sg_idle
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Command / Status Interface
-------------------------------------------------------------------------------
I_FTCH_CMDSTS_IF : entity axi_vdma_v6_2.axi_sg_ftch_cmdsts_if
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from fetch sm
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- Scatter Gather Fetch Status
mm2s_err => mm2s_err ,
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_error_early => ftch_error_early
);
end implementation;
| gpl-2.0 | c5379816febe3a2bc8072c02ee5135e0 | 0.359493 | 5.006127 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_single_pulse.vhd | 4 | 1,594 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_single_pulse is
generic (
DELAY : positive := 1;
SIGNAL_TYPE : string := "Impulse";
IMPULSE_WIDTH : positive := 1
);
port (
result : out std_logic;
clock : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_single_pulse;
architecture rtl of alt_dspbuilder_single_pulse is
component alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic (
DELAY : positive := 1;
SIGNAL_TYPE : string := "Step Down";
IMPULSE_WIDTH : positive := 1
);
port (
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
result : out std_logic;
sclr : in std_logic
);
end component alt_dspbuilder_single_pulse_GN2XGKTRR3;
begin
alt_dspbuilder_single_pulse_GN2XGKTRR3_0: if ((DELAY = 1) and (SIGNAL_TYPE = "Step Down") and (IMPULSE_WIDTH = 1)) generate
inst_alt_dspbuilder_single_pulse_GN2XGKTRR3_0: alt_dspbuilder_single_pulse_GN2XGKTRR3
generic map(DELAY => 1, SIGNAL_TYPE => "Step Down", IMPULSE_WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, result => result, sclr => sclr);
end generate;
assert not (((DELAY = 1) and (SIGNAL_TYPE = "Step Down") and (IMPULSE_WIDTH = 1)))
report "Please run generate again" severity error;
end architecture rtl;
| mit | 5b029c7d7de5b10d7a6dfe28e569ac81 | 0.702008 | 3.21371 | false | false | false | false |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_ftch_noqueue.vhd | 1 | 14,890 | -------------------------------------------------------------------------------
-- axi_sg_ftch_noqueue
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_noqueue.vhd
-- Description: This entity is the no queue version
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 6/16/10 v4_03
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
library lib_pkg_v1_0;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32
-- Master AXI Stream Data Width
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel Control --
desc_flush : in std_logic ; --
ftch_active : in std_logic ; --
ftch_queue_empty : out std_logic ; --
ftch_queue_full : out std_logic ; --
--
writing_nxtdesc_in : in std_logic ; --
writing_curdesc_out : out std_logic ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ftch_tvalid : out std_logic ; --
m_axis_ftch_tready : in std_logic ; --
m_axis_ftch_tlast : out std_logic --
);
end axi_sg_ftch_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel 1 internal signals
signal curdesc_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_tvalid : std_logic := '0';
signal ftch_tvalid : std_logic := '0';
signal ftch_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast : std_logic := '0';
signal ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal writing_nxtdesc : std_logic := '0';
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal writing_lsb : std_logic := '0';
signal writing_msb : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Write current descriptor to FIFO or out channel port
---------------------------------------------------------------------------
WRITE_CURDESC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
curdesc_tdata <= (others => '0');
curdesc_tvalid <= '0';
writing_lsb <= '0';
writing_msb <= '0';
-- Write LSB Address on command write
elsif(ftch_cmnd_wr = '1' and ftch_active = '1')then
curdesc_tdata <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
curdesc_tvalid <= '1';
writing_lsb <= '1';
writing_msb <= '0';
-- On ready write MSB address
elsif(writing_lsb = '1' and ftch_tready = '1')then
curdesc_tdata <= msb_curdesc;
curdesc_tvalid <= '1';
writing_lsb <= '0';
writing_msb <= '1';
-- On MSB write and ready then clear all
elsif(writing_msb = '1' and ftch_tready = '1')then
curdesc_tdata <= (others => '0');
curdesc_tvalid <= '0';
writing_lsb <= '0';
writing_msb <= '0';
end if;
end if;
end process WRITE_CURDESC_PROCESS;
---------------------------------------------------------------------------
-- TVALID MUX
-- MUX tvalid out channel port
---------------------------------------------------------------------------
TVALID_TDATA_MUX : process(writing_curdesc,
writing_nxtdesc,
ftch_active,
curdesc_tvalid,
curdesc_tdata,
m_axis_mm2s_tvalid,
m_axis_mm2s_tdata,
m_axis_mm2s_tlast)
begin
-- Select current descriptor to drive out (Queue or Channel Port)
if(writing_curdesc = '1')then
ftch_tvalid <= curdesc_tvalid;
ftch_tdata <= curdesc_tdata;
ftch_tlast <= '0';
-- Deassert tvalid when capturing next descriptor pointer
elsif(writing_nxtdesc = '1')then
ftch_tvalid <= '0';
ftch_tdata <= (others => '0');
ftch_tlast <= '0';
-- Otherwise drive data from Datamover out (Queue or Channel Port)
elsif(ftch_active = '1')then
ftch_tvalid <= m_axis_mm2s_tvalid;
ftch_tdata <= m_axis_mm2s_tdata;
ftch_tlast <= m_axis_mm2s_tlast;
else
ftch_tvalid <= '0';
ftch_tdata <= (others => '0');
ftch_tlast <= '0';
end if;
end process TVALID_TDATA_MUX;
---------------------------------------------------------------------------
-- Map internal stream to external
---------------------------------------------------------------------------
m_axis_ftch_tdata <= ftch_tdata;
m_axis_ftch_tlast <= ftch_tlast;
m_axis_ftch_tvalid <= ftch_tvalid;
ftch_tready <= m_axis_ftch_tready;
m_axis_mm2s_tready <= ftch_tready;
---------------------------------------------------------------------------
-- generate psuedo empty flag for Idle generation
---------------------------------------------------------------------------
Q_EMPTY_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then
if(m_axi_sg_aresetn = '0' or desc_flush = '1')then
ftch_queue_empty <= '1';
-- Else on valid and ready modify empty flag
elsif(ftch_tvalid = '1' and m_axis_ftch_tready = '1')then
-- On last mark as empty
if(ftch_tlast = '1' )then
ftch_queue_empty <= '1';
-- Otherwise mark as not empty
else
ftch_queue_empty <= '0';
end if;
end if;
end if;
end process Q_EMPTY_PROCESS;
-- do not need to indicate full to axi_sg_ftch_sm. Only
-- needed for queue case to allow other channel to be serviced
-- if it had queue room
ftch_queue_full <= '0';
-- If writing curdesc out then flag for proper mux selection
writing_curdesc <= curdesc_tvalid;
-- Map intnal signal to port
writing_curdesc_out <= writing_curdesc;
-- Map port to internal signal
writing_nxtdesc <= writing_nxtdesc_in;
end implementation;
| gpl-2.0 | 519d5833350681d5ba5cbc159f60cb26 | 0.407589 | 5.030405 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_multiplexer_GNLGLCKYZ5.vhd | 4 | 1,351 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiplexer_GNLGLCKYZ5 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 24;
pipeline : natural := 0;
number_inputs : natural := 4);
port(
clock : in std_logic;
aclr : in std_logic;
sel : in std_logic_vector(1 downto 0);
result : out std_logic_vector(23 downto 0);
ena : in std_logic;
user_aclr : in std_logic;
in0 : in std_logic_vector(23 downto 0);
in1 : in std_logic_vector(23 downto 0);
in2 : in std_logic_vector(23 downto 0);
in3 : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_multiplexer_GNLGLCKYZ5 is
signal data_muxin : std_logic_vector(95 downto 0);
Begin
data_muxin <= in3 & in2 & in1 & in0 ;
nto1Multiplexeri : alt_dspbuilder_sMuxAltr generic map (
lpm_pipeline =>0,
lpm_size => 4,
lpm_widths => 2 ,
lpm_width => 24 ,
SelOneHot => 0 )
port map (
clock => clock,
ena => ena,
user_aclr => user_aclr,
aclr => aclr,
data => data_muxin,
sel => sel,
result => result);
end architecture;
| mit | b1949083a30741a66470d6b8f50a9167 | 0.638786 | 2.808732 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_if_statement_GNJ7D74ANQ.vhd | 4 | 1,401 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a>b";
number_inputs : integer := 2;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNJ7D74ANQ is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(a>b) ;
true <= result;
end architecture;
| mit | fc525ed246199dd0d2dc26b39dbda053 | 0.622413 | 3.25814 | false | false | false | false |
freecores/t48 | rtl/vhdl/system/lpm_ram_dq.vhd | 2 | 14,256 | --------------------------------------------------------------------------
-- This VHDL file was developed by Altera Corporation. It may be
-- freely copied and/or distributed at no cost. Any persons using this
-- file for any purpose do so at their own risk, and are responsible for
-- the results of such use. Altera Corporation does not guarantee that
-- this file is complete, correct, or fit for any particular purpose.
-- NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must
-- accompany any copy of this file.
--
--------------------------------------------------------------------------
-- LPM Synthesizable Models (Support string type generic)
--------------------------------------------------------------------------
-- Version 2.0 (lpm 220) Date 01/04/00
--
-- 1. Fixed LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO and LPM_ROM to correctly
-- read in values from LPM_FILE (*.hex) when the DATA width is greater
-- than 16 bits.
-- 2. Explicit sign conversions are added to standard logic vector
-- comparisons in LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO, LPM_ROM, and
-- LPM_COMPARE.
-- 3. LPM_FIFO_DC is rewritten to have correct outputs.
-- 4. LPM_FIFO outputs zeros when nothing has been read from it, and
-- outputs LPM_NUMWORDS mod exp(2, LPM_WIDTHU) when it is full.
-- 5. Fixed LPM_DIVIDE to divide correctly.
--------------------------------------------------------------------------
-- Version 1.9 (lpm 220) Date 11/30/99
--
-- 1. Fixed UNUSED file not found problem and initialization problem
-- with LPM_RAM_DP, LPM_RAM_DQ, and LPM_RAM_IO.
-- 2. Fixed LPM_MULT when SUM port is not used.
-- 3. Fixed LPM_FIFO_DC to enable read when rdclock and wrclock rise
-- at the same time.
-- 4. Fixed LPM_COUNTER comparison problem when signed library is loaded
-- and counter is incrementing.
-- 5. Got rid of "Illegal Character" error message at time = 0 ns when
-- simulating LPM_COUNTER.
--------------------------------------------------------------------------
-- Version 1.8 (lpm 220) Date 10/25/99
--
-- 1. Some LPM_PVALUE implementations were missing, and now implemented.
-- 2. Fixed LPM_COUNTER to count correctly without conversion overflow,
-- that is, when LPM_MODULUS = 2 ** LPM_WIDTH.
-- 3. Fixed LPM_RAM_DP sync process sensitivity list to detect wraddress
-- changes.
--------------------------------------------------------------------------
-- Version 1.7 (lpm 220) Date 07/13/99
--
-- Changed LPM_RAM_IO so that it can be used to simulate both MP2 and
-- Quartus behaviour and LPM220-compliant behaviour.
--------------------------------------------------------------------------
-- Version 1.6 (lpm 220) Date 06/15/99
--
-- 1. Fixed LPM_ADD_SUB sign extension problem and subtraction bug.
-- 2. Fixed LPM_COUNTER to use LPM_MODULUS value.
-- 3. Added CIN and COUT port, and discarded EQ port in LPM_COUNTER to
-- comply with the specfication.
-- 4. Included LPM_RAM_DP, LPM_RAM_DQ, LPM_RAM_IO, LPM_ROM, LPM_FIFO, and
-- LPM_FIFO_DC; they are all initialized to 0's.
--------------------------------------------------------------------------
-- Version 1.5 (lpm 220) Date 05/10/99
--
-- Changed LPM_MODULUS from string type to integer.
--------------------------------------------------------------------------
-- Version 1.4 (lpm 220) Date 02/05/99
--
-- 1. Added LPM_DIVIDE module.
-- 2. Added CLKEN port to LPM_MUX, LPM_DECODE, LPM_ADD_SUB, LPM_MULT
-- and LPM_COMPARE
-- 3. Replaced the constants holding string with the actual string.
--------------------------------------------------------------------------
-- Version 1.3 Date 07/30/96
--
-- Modification History
--
-- 1. Changed the DEFAULT value to "UNUSED" for LPM_SVALUE, LPM_AVALUE,
-- LPM_MODULUS, and LPM_NUMWORDS, LPM_HINT,LPM_STRENGTH, LPM_DIRECTION,
-- and LPM_PVALUE
--
-- 2. Added the two dimentional port components (AND, OR, XOR, and MUX).
--------------------------------------------------------------------------
-- Excluded Functions:
--
-- LPM_FSM and LPM_TTABLE
--
--------------------------------------------------------------------------
-- Assumptions:
--
-- 1. All ports and signal types are std_logic or std_logic_vector
-- from IEEE 1164 package.
-- 2. Synopsys std_logic_arith, std_logic_unsigned, and std_logic_signed
-- package are assumed to be accessible from IEEE library.
-- 3. lpm_component_package must be accessible from library work.
-- 4. The default value of LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, LPM_HINT,
-- LPM_NUMWORDS, LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE is
-- string "UNUSED".
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--use IEEE.std_logic_unsigned.all;
use std.textio.all;
entity LPM_RAM_DQ is
generic (LPM_WIDTH : positive;
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
function int_to_str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function hex_str_to_int( str : string ) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer;
begin
for i in len downto 1 loop
case str(i) is
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when 'A' =>
digit := 10;
when 'a' =>
digit := 10;
when 'B' =>
digit := 11;
when 'b' =>
digit := 11;
when 'C' =>
digit := 12;
when 'c' =>
digit := 12;
when 'D' =>
digit := 13;
when 'd' =>
digit := 13;
when 'E' =>
digit := 14;
when 'e' =>
digit := 14;
when 'F' =>
digit := 15;
when 'f' =>
digit := 15;
when others =>
ASSERT FALSE
REPORT "Illegal character "& str(i) & "in Intel Hex File! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 16 + digit;
end loop;
return ivalue;
end;
procedure Shrink_line(L : inout LINE; pos : in integer) is
subtype nstring is string(1 to pos);
variable stmp : nstring;
begin
if pos >= 1 then
read(l, stmp);
end if;
end;
end LPM_RAM_DQ;
architecture LPM_SYN of lpm_ram_dq is
--type lpm_memory is array(lpm_numwords-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
type lpm_memory is array(integer range (2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
signal data_tmp, data_reg : std_logic_vector(lpm_width-1 downto 0);
signal q_tmp, q_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal address_tmp, address_reg : std_logic_vector(lpm_widthad-1 downto 0);
signal we_tmp, we_reg : std_logic;
begin
sync: process(data, data_reg, address, address_reg,
we, we_reg, q_tmp, q_reg)
begin
if (lpm_address_control = "REGISTERED") then
address_tmp <= address_reg;
we_tmp <= we_reg;
else
address_tmp <= address;
we_tmp <= we;
end if;
if (lpm_indata = "REGISTERED") then
data_tmp <= data_reg;
else
data_tmp <= data;
end if;
if (lpm_outdata = "REGISTERED") then
q <= q_reg;
else
q <= q_tmp;
end if;
end process;
input_reg: process (inclock)
begin
if inclock'event and inclock = '1' then
data_reg <= data;
address_reg <= address;
we_reg <= we;
end if;
end process;
output_reg: process (outclock)
begin
if outclock'event and outclock = '1' then
q_reg <= q_tmp;
end if;
end process;
memory: process(data_tmp, we_tmp, address_tmp)
variable mem_data : lpm_memory;
variable mem_data_tmp : integer := 0;
variable mem_init: boolean := false;
variable i,j,k,lineno: integer := 0;
variable buf: line ;
variable booval: boolean ;
FILE unused_file: TEXT IS OUT "UNUSED";
FILE mem_data_file: TEXT IS IN LPM_FILE;
variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1);
variable startadd: string(4 downto 1);
variable ibase: integer := 0;
variable ibyte: integer := 0;
variable istartadd: integer := 0;
variable check_sum_vec, check_sum_vec_tmp: unsigned(7 downto 0);
begin
-- INITIALIZE --
if NOT(mem_init) then
-- INITIALIZE TO 0 --
for i in mem_data'LOW to mem_data'HIGH loop
mem_data(i) := (OTHERS => '0');
end loop;
if (LPM_FILE = "UNUSED") then
ASSERT FALSE
REPORT "Initialization file not found!"
SEVERITY WARNING;
else
WHILE NOT ENDFILE(mem_data_file) loop
booval := true;
READLINE(mem_data_file, buf);
lineno := lineno + 1;
check_sum_vec := (OTHERS => '0');
if (buf(buf'LOW) = ':') then
i := 1;
shrink_line(buf, i);
READ(L=>buf, VALUE=>byte, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format!"
SEVERITY ERROR;
end if;
ibyte := hex_str_to_int(byte);
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(ibyte, check_sum_vec'length);
READ(L=>buf, VALUE=>startadd, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
istartadd := hex_str_to_int(startadd);
addr(2) := startadd(4);
addr(1) := startadd(3);
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length);
addr(2) := startadd(2);
addr(1) := startadd(1);
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length);
READ(L=>buf, VALUE=>rec_type, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(rec_type), check_sum_vec'length);
else
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
case rec_type is
when "00"=> -- Data record
i := 0;
k := lpm_width / 8;
if ((lpm_width MOD 8) /= 0) then
k := k + 1;
end if;
-- k = no. of bytes per CAM entry.
while (i < ibyte) loop
mem_data_tmp := 0;
for j in 1 to k loop
READ(L=>buf, VALUE=>datain,good=>booval); -- read in data a byte (2 hex chars) at a time.
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(datain), check_sum_vec'length);
mem_data_tmp := mem_data_tmp * 256 + hex_str_to_int(datain);
end loop;
i := i + k;
mem_data(ibase + istartadd) := STD_LOGIC_VECTOR(to_unsigned(mem_data_tmp, lpm_width));
istartadd := istartadd + 1;
end loop;
when "01"=>
exit;
when "02"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format for record type 02! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := ibase * 256 + hex_str_to_int(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(base), check_sum_vec'length);
end loop;
ibase := ibase * 16;
when OTHERS =>
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal record type in Intel Hex File! "
SEVERITY ERROR;
end case;
READ(L=>buf, VALUE=>checksum,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Checksum is missing! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
check_sum_vec_tmp := to_unsigned(hex_str_to_int(checksum), check_sum_vec_tmp'length);
if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Incorrect checksum!"
SEVERITY ERROR;
end if;
end loop;
end if;
mem_init := TRUE;
end if;
-- MEMORY FUNCTION --
if we_tmp = '1' then
mem_data (to_integer(unsigned(address_tmp))) := data_tmp;
end if;
q_tmp <= mem_data(to_integer(unsigned(address_tmp)));
end process;
end LPM_SYN;
-- pragma translate_off
configuration lpm_ram_dq_c0 of lpm_ram_dq is
for lpm_syn
end for;
end lpm_ram_dq_c0;
-- pragma translate_on
| gpl-2.0 | 9ba1018644b3e37b550a6a1ce5575286 | 0.570426 | 3.303824 | false | false | false | false |
lelongdunet/dspunit | rtl/dspunit_pac.vhd | 2 | 13,906 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.dspalu_pac.all;
use work.bit_manipulation.all;
-------------------------------------------------------------------------------
package dspunit_pac is
constant sig_width : positive := 16;
constant cmdreg_addr_width : natural := 4;
constant cmdreg_data_width : positive := 16;
constant cmdreg_width : positive := 16;
constant cmdregs_length : positive := 16;
constant acc_width : positive := 40;
constant acc_reduce_width : positive := 30;
constant lut_in_width : positive := 13;
constant lut_sel_width : positive := 4;
constant lut_out_width : positive := sig_width;
constant angle_width : positive := 13;
constant c_dsp_pipe_length : positive := 4;
constant div_pipe_length : positive := sig_width + 1;
function sig_cst_init(realval : real) return std_logic_vector;
function module(a : signed; b : signed) return integer;
procedure dispsig(name : string; ind : integer; val : integer);
--type t_dsp_cmdregs is array (0 to ((2**cmdreg_addr_width) - 1)) of std_logic_vector((cmdreg_width - 1) downto 0);
type t_dsp_cmdregs is array (0 to cmdregs_length - 1) of std_logic_vector((cmdreg_width - 1) downto 0);
type t_dsp_bus is
record
op_done : std_logic;
-- memory 0
data_out_m0 : std_logic_vector((sig_width - 1) downto 0);
addr_r_m0 : unsigned((cmdreg_width - 1) downto 0);
addr_w_m0 : unsigned((cmdreg_width - 1) downto 0);
wr_en_m0 : std_logic;
c_en_m0 : std_logic;
-- memory 1
data_out_m1 : std_logic_vector((sig_width - 1) downto 0);
addr_m1 : unsigned((cmdreg_width - 1) downto 0);
wr_en_m1 : std_logic;
c_en_m1 : std_logic;
-- memory 2
data_out_m2 : std_logic_vector((sig_width - 1) downto 0);
addr_m2 : unsigned((cmdreg_width - 1) downto 0);
wr_en_m2 : std_logic;
c_en_m2 : std_logic;
-- alu
mul_in_a1 : std_logic_vector((sig_width - 1) downto 0);
mul_in_b1 : std_logic_vector((sig_width - 1) downto 0);
mul_in_a2 : std_logic_vector((sig_width - 1) downto 0);
mul_in_b2 : std_logic_vector((sig_width - 1) downto 0);
acc_mode1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
acc_mode2 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
alu_select : std_logic_vector((alu_select_width - 1) downto 0); -- t_alu_select;
cmp_mode : std_logic_vector((cmp_mode_width - 1) downto 0); -- t_cmp_mode;
cmp_pol : std_logic;
cmp_store : std_logic;
-- divider
div_num : std_logic_vector((2*sig_width - 1) downto 0);
div_den : std_logic_vector((sig_width - 1) downto 0);
-- global counter
gcounter_reset : std_logic;
-- shared lut
lut_in : std_logic_vector((lut_in_width - 1) downto 0);
lut_select : std_logic_vector((lut_sel_width - 1) downto 0);
end record;
constant c_dsp_bus_init : t_dsp_bus := (
op_done => '0',
-- memory 0
data_out_m0 => (others => '0'),
addr_r_m0 => (others => '0'),
addr_w_m0 => (others => '0'),
wr_en_m0 => '0',
c_en_m0 => '0',
-- memory 1
data_out_m1 => (others => '0'),
addr_m1 => (others => '0'),
wr_en_m1 => '0',
c_en_m1 => '0',
-- memory 2
data_out_m2 => (others => '0'),
addr_m2 => (others => '0'),
wr_en_m2 => '0',
c_en_m2 => '0',
-- alu
mul_in_a1 => (others => '0'),
mul_in_b1 => (others => '0'),
mul_in_a2 => (others => '0'),
mul_in_b2 => (others => '0'),
acc_mode1 => acc_none,
acc_mode2 => acc_none,
alu_select => alu_none,
cmp_mode => cmp_none,
cmp_pol => '0',
cmp_store => '0',
-- divider
div_num => (others => '0'),
div_den => (others => '0'),
-- global counter
gcounter_reset => '0',
-- shared lut
lut_in => (others => '0'),
lut_select => (others => '0')
);
function "or" (a, b : t_dsp_bus) return t_dsp_bus;
function "and" (a : std_logic_vector; b : std_logic) return std_logic_vector;
function dsp_cmdregs_init return t_dsp_cmdregs;
-------------------------------------------------------------------------------
-- General params
-------------------------------------------------------------------------------
constant c_dspmem_pipe_depth : integer := 2;
-------------------------------------------------------------------------------
-- Register address
-------------------------------------------------------------------------------
-- registers offsets of dspunit
constant DSPADDR_STARTADDR0 : positive := 1;
constant DSPADDR_LENGTH0 : positive := 2;
constant DSPADDR_STARTADDR1 : positive := 3;
constant DSPADDR_LENGTH1 : positive := 4;
constant DSPADDR_STARTADDR2 : positive := 5;
constant DSPADDR_LENGTH2 : positive := 6;
constant DSPADDR_OPCODE : positive := 7;
constant DSPADDR_SR : positive := 8;
-- Bits of status register
constant DSP_SRBIT_DONE : natural := 0;
constant DSP_SRBIT_RUN : natural := 1;
constant DSP_SRBIT_LOADED : natural := 2;
constant DSP_SRBIT_DONE_IE : natural := 3;
constant DSP_SRBIT_EMPTY_IE : natural := 4;
constant DSP_SRBIT_DONE_IF : natural := 5;
constant DSP_SRBIT_EMPTY_IF : natural := 6;
constant DSP_SRBIT_UNUSED : natural := 7;
-- opcodes of availables processings
constant opcode_width : positive := 4;
constant opcode_cpflip : std_logic_vector((opcode_width - 1) downto 0) := "0010";
constant opcode_cpmem : std_logic_vector((opcode_width - 1) downto 0) := "0100";
constant opcode_setmem : std_logic_vector((opcode_width - 1) downto 0) := "0101";
constant opcode_dotopnorm : std_logic_vector((opcode_width - 1) downto 0) := "0111";
constant opcode_dotdiv : std_logic_vector((opcode_width - 1) downto 0) := "1000";
constant opcode_fft : std_logic_vector((opcode_width - 1) downto 0) := "1100";
constant opcode_dotcmul : std_logic_vector((opcode_width - 1) downto 0) := "1101";
-- opflags (options related to each operation)
constant opflag_width : positive := 8;
constant opflag_ifft : std_logic_vector((opflag_width - 1) downto 0) := "00000001";
constant opflagbit_ifft : natural := 0;
constant opflag_bitrev : std_logic_vector((opflag_width - 1) downto 0) := "00000010";
constant opflagbit_bitrev : natural := 1;
constant opflag_mainmem : std_logic_vector((opflag_width - 1) downto 0) := "00000010";
constant opflagbit_mainmem : natural := 1;
constant opflag_savestep : std_logic_vector((opflag_width - 1) downto 0) := "00001000";
constant opflagbit_savestep : natural := 3;
constant opflag_muladd : std_logic_vector((opflag_width - 1) downto 0) := "00000001";
constant opflagbit_muladd : natural := 0;
constant opflag_l1norm : std_logic_vector((opflag_width - 1) downto 0) := "00000010";
constant opflagbit_l1norm : natural := 1;
constant opflag_tocomplex : std_logic_vector((opflag_width - 1) downto 0) := "00000001";
constant opflagbit_tocomplex : natural := 0;
constant opflag_fromcomplex : std_logic_vector((opflag_width - 1) downto 0) := "00000010";
constant opflagbit_fromcomplex : natural := 1;
constant opflag_m0 : std_logic_vector((opflag_width - 1) downto 0) := "00100000";
constant opflagbit_m0 : natural := 5;
constant opflag_m1 : std_logic_vector((opflag_width - 1) downto 0) := "01000000";
constant opflagbit_m1 : natural := 6;
constant opflag_m2 : std_logic_vector((opflag_width - 1) downto 0) := "10000000";
constant opflagbit_m2 : natural := 7;
constant opflag_srcm0 : std_logic_vector((opflag_width - 1) downto 0) := "00000100";
constant opflagbit_srcm0 : natural := 2;
constant opflag_srcm1 : std_logic_vector((opflag_width - 1) downto 0) := "00001000";
constant opflagbit_srcm1 : natural := 3;
constant opflag_srcm2 : std_logic_vector((opflag_width - 1) downto 0) := "00010000";
constant opflagbit_srcm2 : natural := 4;
constant opflag_srcswap : std_logic_vector((opflag_width - 1) downto 0) := "00000010";
constant opflagbit_srcswap : natural := 1;
-- selection of math lut
constant lutsel_none : std_logic_vector((lut_sel_width - 1) downto 0) := "0000";
constant lutsel_cos : std_logic_vector((lut_sel_width - 1) downto 0) := "0001";
constant lutsel_sin : std_logic_vector((lut_sel_width - 1) downto 0) := "0010";
end dspunit_pac;
package body dspunit_pac is
function sig_cst_init(realval : real) return std_logic_vector
is
variable fracval : real;
variable fracint : integer;
begin
fracval := realval * real(2 ** (sig_width - 1));
fracint := integer(floor(fracval));
return std_logic_vector(to_signed(fracint, sig_width));
end sig_cst_init;
function module(a : signed; b : signed) return integer
is
variable res : real;
begin
res := sqrt(real(to_integer(a))**2 + real(to_integer(b))**2);
return integer(res);
end module;
procedure dispsig(name : string; ind : integer; val : integer)
is
variable msg : line;
begin
write(msg, string'("dispsig : "));
write(msg, name);
write(msg, string'("("));
write(msg, ind);
write(msg, string'(") = "));
write(msg, val);
report msg.all;
end dispsig;
function "or" (a, b : t_dsp_bus) return t_dsp_bus is
variable y : t_dsp_bus;
begin
-- y <= a or b;
y.op_done := a.op_done or b.op_done ;
y.data_out_m0 := a.data_out_m0 or b.data_out_m0 ;
y.addr_r_m0 := a.addr_r_m0 or b.addr_r_m0 ;
y.addr_w_m0 := a.addr_w_m0 or b.addr_w_m0 ;
y.wr_en_m0 := a.wr_en_m0 or b.wr_en_m0 ;
y.c_en_m0 := a.c_en_m0 or b.c_en_m0 ;
y.data_out_m1 := a.data_out_m1 or b.data_out_m1 ;
y.addr_m1 := a.addr_m1 or b.addr_m1 ;
y.wr_en_m1 := a.wr_en_m1 or b.wr_en_m1 ;
y.c_en_m1 := a.c_en_m1 or b.c_en_m1 ;
y.data_out_m2 := a.data_out_m2 or b.data_out_m2 ;
y.addr_m2 := a.addr_m2 or b.addr_m2 ;
y.wr_en_m2 := a.wr_en_m2 or b.wr_en_m2 ;
y.c_en_m2 := a.c_en_m2 or b.c_en_m2 ;
y.mul_in_a1 := a.mul_in_a1 or b.mul_in_a1 ;
y.mul_in_b1 := a.mul_in_b1 or b.mul_in_b1 ;
y.mul_in_a2 := a.mul_in_a2 or b.mul_in_a2 ;
y.mul_in_b2 := a.mul_in_b2 or b.mul_in_b2 ;
y.acc_mode1 := a.acc_mode1 or b.acc_mode1 ;
y.acc_mode2 := a.acc_mode2 or b.acc_mode2 ;
y.alu_select := a.alu_select or b.alu_select ;
y.cmp_mode := a.cmp_mode or b.cmp_mode ;
y.cmp_pol := a.cmp_pol or b.cmp_pol ;
y.cmp_store := a.cmp_store or b.cmp_store ;
y.div_num := a.div_num or b.div_num ;
y.div_den := a.div_den or b.div_den ;
y.gcounter_reset := a.gcounter_reset or b.gcounter_reset;
y.lut_in := a.lut_in or b.lut_in ;
y.lut_select := a.lut_select or b.lut_select ;
return y;
end "or";
function "and" (a : std_logic_vector; b : std_logic) return std_logic_vector is
constant L : natural := a'length;
alias aa : std_logic_vector((L - 1) downto 0) is A;
variable yy : std_logic_vector((L - 1) downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa(i) and b;
end loop;
return yy;
end "and";
function dsp_cmdregs_init return t_dsp_cmdregs is
variable regs : t_dsp_cmdregs;
begin
for i in 0 to cmdregs_length - 1 loop
regs(i) := (others => '0');
end loop;
return regs;
end dsp_cmdregs_init;
end dspunit_pac;
| gpl-3.0 | 4495fd8033d0af8e9a8b186c1b47b153 | 0.533223 | 3.347617 | false | false | false | false |
michaelmiehling/A25_VME_TB | Testbench/z126_01_pasmi_m25p32_sim.vhd | 1 | 131,650 | -- megafunction wizard: %ALTASMI_PARALLEL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTASMI_PARALLEL
-- ============================================================
-- File Name: z126_01_pasmi_sim_m25p32_2.vhd
-- Megafunction Name(s):
-- ALTASMI_PARALLEL
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altasmi_parallel CBX_AUTO_BLACKBOX="ALL" DATA_WIDTH="STANDARD" DEVICE_FAMILY="Cyclone III" EPCS_TYPE="EPCS16" PAGE_SIZE=256 PORT_BULK_ERASE="PORT_USED" PORT_EN4B_ADDR="PORT_UNUSED" PORT_FAST_READ="PORT_USED" PORT_ILLEGAL_ERASE="PORT_USED" PORT_ILLEGAL_WRITE="PORT_USED" PORT_RDID_OUT="PORT_USED" PORT_READ_ADDRESS="PORT_UNUSED" PORT_READ_RDID="PORT_USED" PORT_READ_SID="PORT_UNUSED" PORT_READ_STATUS="PORT_USED" PORT_SECTOR_ERASE="PORT_USED" PORT_SECTOR_PROTECT="PORT_USED" PORT_SHIFT_BYTES="PORT_USED" PORT_WREN="PORT_USED" PORT_WRITE="PORT_USED" USE_EAB="ON" addr bulk_erase busy clkin data_valid datain dataout fast_read illegal_erase illegal_write rden rdid_out read_rdid read_status sector_erase sector_protect shift_bytes status_out wren write INTENDED_DEVICE_FAMILY="Cyclone III" ALTERA_INTERNAL_OPTIONS=SUPPRESS_DA_RULE_INTERNAL=C106
--VERSION_BEGIN 11.1SP2 cbx_a_gray2bin 2012:01:25:21:14:55:SJ cbx_a_graycounter 2012:01:25:21:14:55:SJ cbx_altasmi_parallel 2012:01:25:21:14:55:SJ cbx_altdpram 2012:01:25:21:14:55:SJ cbx_altsyncram 2012:01:25:21:14:56:SJ cbx_cyclone 2012:01:25:21:14:56:SJ cbx_cycloneii 2012:01:25:21:14:56:SJ cbx_fifo_common 2012:01:25:21:14:55:SJ cbx_lpm_add_sub 2012:01:25:21:14:56:SJ cbx_lpm_compare 2012:01:25:21:14:56:SJ cbx_lpm_counter 2012:01:25:21:14:56:SJ cbx_lpm_decode 2012:01:25:21:14:56:SJ cbx_lpm_mux 2012:01:25:21:14:56:SJ cbx_mgl 2012:01:25:21:17:49:SJ cbx_scfifo 2012:01:25:21:14:56:SJ cbx_stratix 2012:01:25:21:14:56:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_stratixiii 2012:01:25:21:14:56:SJ cbx_stratixv 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ VERSION_END
LIBRARY altera_mf;
USE altera_mf.all;
LIBRARY cycloneii;
USE cycloneii.all;
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = a_graycounter 5 cycloneii_asmiblock 1 lpm_compare 2 lpm_counter 2 lut 70 mux21 2 reg 147
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY z126_01_pasmi_sim_m25p32_altasmi_parallel_l2q2 IS
PORT
(
addr : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
bulk_erase : IN STD_LOGIC := '0';
busy : OUT STD_LOGIC;
clkin : IN STD_LOGIC;
data_valid : OUT STD_LOGIC;
datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
fast_read : IN STD_LOGIC := '0';
illegal_erase : OUT STD_LOGIC;
illegal_write : OUT STD_LOGIC;
rden : IN STD_LOGIC;
rdid_out : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
read_rdid : IN STD_LOGIC := '0';
read_status : IN STD_LOGIC := '0';
sector_erase : IN STD_LOGIC := '0';
sector_protect : IN STD_LOGIC := '0';
shift_bytes : IN STD_LOGIC := '0';
status_out : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC := '1';
write : IN STD_LOGIC := '0'
);
END z126_01_pasmi_sim_m25p32_altasmi_parallel_l2q2;
ARCHITECTURE RTL OF z126_01_pasmi_sim_m25p32_altasmi_parallel_l2q2 IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "SUPPRESS_DA_RULE_INTERNAL=C106";
SIGNAL wire_addbyte_cntr_w_lg_w_q_range137w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addbyte_cntr_w_lg_w_q_range140w141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addbyte_cntr_clk_en : STD_LOGIC;
SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w92w135w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addbyte_cntr_clock : STD_LOGIC;
SIGNAL wire_addbyte_cntr_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_addbyte_cntr_w_q_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addbyte_cntr_w_q_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_gen_cntr_w_lg_w_q_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_gen_cntr_w_lg_w_q_range97w98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_gen_cntr_clk_en : STD_LOGIC;
SIGNAL wire_w_lg_in_operation44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_gen_cntr_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_gen_cntr_w_q_range97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_gen_cntr_w_q_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_spstage_cntr_w_lg_w_q_range598w599w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_spstage_cntr_clk_en : STD_LOGIC;
SIGNAL wire_w_lg_do_sec_prot595w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_spstage_cntr_clock : STD_LOGIC;
SIGNAL wire_spstage_cntr_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_spstage_cntr_w_q_range596w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_spstage_cntr_w_q_range598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w247w248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range89w92w244w245w246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range89w92w249w250w251w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range89w90w91w257w258w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w94w322w323w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w92w269w270w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w92w244w245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w92w249w250w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w90w91w257w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_lg_w_q_range89w94w322w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_lg_w_q_range89w92w269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_lg_w_q_range89w92w244w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_lg_w_q_range89w92w249w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_lg_w_q_range89w92w135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range88w93w107w108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_lg_w_q_range88w93w107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_lg_w_q_range89w90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_q_range89w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_q_range89w92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range88w93w107w108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_q_range88w93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_lg_w_q_range89w90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_clk_en : STD_LOGIC;
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_w82w83w84w85w86w87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_stage_cntr_w_q_range88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_stage_cntr_w_q_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_wrstage_cntr_w_lg_w_q_range494w495w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_wrstage_cntr_w_lg_w_q_range492w493w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_wrstage_cntr_clk_en : STD_LOGIC;
SIGNAL wire_w_lg_w490w491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_wrstage_cntr_clock : STD_LOGIC;
SIGNAL wire_wrstage_cntr_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_wrstage_cntr_w_q_range492w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_wrstage_cntr_w_q_range494w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_cycloneii_asmiblock3_data0out : STD_LOGIC;
SIGNAL add_msb_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_add_msb_reg_ena : STD_LOGIC;
SIGNAL wire_addr_reg_d : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL addr_reg : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_addr_reg_ena : STD_LOGIC_VECTOR(23 DOWNTO 0);
SIGNAL wire_addr_reg_w_lg_w_lg_w535w536w537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_lg_w535w536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w531w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w535w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range512w518w524w525w526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range512w518w524w529w530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range512w518w524w529w534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_lg_w_lg_w_lg_w_q_range512w513w514w515w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_lg_w_lg_w_lg_w_q_range512w518w524w525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_lg_w_lg_w_lg_w_q_range512w518w524w529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_lg_w_lg_w_q_range512w513w514w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_lg_w_lg_w_q_range512w518w519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_lg_w_lg_w_q_range512w518w524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_lg_w_q_range512w513w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_lg_w_q_range512w518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_q_range533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_q_range528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_q_range523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_q_range517w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_q_range512w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_reg_w_q_range301w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_asmi_opcode_reg_d : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL asmi_opcode_reg : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_asmi_opcode_reg_ena : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_asmi_opcode_reg_w_q_range147w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL buf_empty_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL bulk_erase_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_bulk_erase_reg_ena : STD_LOGIC;
SIGNAL busy_delay_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL busy_det_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL clr_addmsb_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL clr_endrbyte_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_clr_endrbyte_reg_w_lg_q388w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL clr_rdid_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL clr_rdid_reg2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL clr_read_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL clr_read_reg2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL clr_rstat_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL clr_rstat_reg2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL clr_secprot_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL clr_secprot_reg2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL clr_write_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL clr_write_reg2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL cnt_bfend_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL do_wrmemadd_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dvalid_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_dvalid_reg_ena : STD_LOGIC;
SIGNAL dvalid_reg2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL end1_cyc_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL end1_cyc_reg2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL end_op_hdlyreg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL end_op_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL end_opfdly_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL end_pgwrop_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_end_pgwrop_reg_ena : STD_LOGIC;
SIGNAL end_rbyte_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_end_rbyte_reg_ena : STD_LOGIC;
SIGNAL end_read_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL fast_read_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_fast_read_reg_ena : STD_LOGIC;
SIGNAL ill_erase_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL ill_write_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL illegal_erase_dly_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL illegal_write_dly_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL max_cnt_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL maxcnt_shift_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL maxcnt_shift_reg2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL ncs_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_ncs_reg_ena : STD_LOGIC;
SIGNAL wire_ncs_reg_w_lg_q291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pgwrbuf_dataout_d : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL pgwrbuf_dataout : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_pgwrbuf_dataout_ena : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_pgwrbuf_dataout_w_q_range438w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL power_up_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rdid_out_reg : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL read_bufdly_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_read_data_reg_d : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL read_data_reg : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_read_data_reg_ena : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_read_dout_reg_d : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL read_dout_reg : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_read_dout_reg_ena : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL read_rdid_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL read_status_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sec_erase_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_sec_erase_reg_ena : STD_LOGIC;
SIGNAL sec_prot_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_sec_prot_reg_ena : STD_LOGIC;
SIGNAL shftpgwr_data_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL shift_op_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sprot_rstat_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL stage2_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL stage3_dly_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL stage3_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL stage4_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL start_sppoll_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_start_sppoll_reg_ena : STD_LOGIC;
SIGNAL start_sppoll_reg2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL start_wrpoll_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_start_wrpoll_reg_ena : STD_LOGIC;
SIGNAL start_wrpoll_reg2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_statreg_int_d : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL statreg_int : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_statreg_int_ena : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_statreg_out_d : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL statreg_out : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_statreg_out_ena : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL streg_datain_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_streg_datain_reg_ena : STD_LOGIC;
SIGNAL write_prot_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_write_prot_reg_ena : STD_LOGIC;
SIGNAL write_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_write_reg_ena : STD_LOGIC;
SIGNAL write_rstat_reg : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_wrstat_dreg_d : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wrstat_dreg : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_wrstat_dreg_ena : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_wrstat_dreg_w_q_range602w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_cmpr5_aeb : STD_LOGIC;
SIGNAL wire_cmpr5_dataa : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_cmpr5_datab : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_cmpr6_aeb : STD_LOGIC;
SIGNAL wire_cmpr6_dataa : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_cmpr6_datab : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_pgwr_data_cntr_clk_en : STD_LOGIC;
SIGNAL wire_w_lg_w_lg_w_lg_shift_bytes_wire434w450w451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pgwr_data_cntr_q : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_pgwr_data_cntr_w_q_range455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pgwr_data_cntr_w_q_range458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pgwr_data_cntr_w_q_range461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pgwr_data_cntr_w_q_range464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pgwr_data_cntr_w_q_range467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pgwr_data_cntr_w_q_range470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pgwr_data_cntr_w_q_range473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pgwr_data_cntr_w_q_range476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pgwr_read_cntr_q : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_mux211_dataout : STD_LOGIC;
SIGNAL wire_mux212_dataout : STD_LOGIC;
SIGNAL wire_scfifo4_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_scfifo4_q : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_scfifo4_rdreq : STD_LOGIC;
SIGNAL wire_w_lg_read_buf436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_scfifo4_wrreq : STD_LOGIC;
SIGNAL wire_w_lg_w_lg_shift_bytes_wire434w435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_scfifo4_w_q_range441w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_scfifo4_w_q_range446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w413w414w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w413w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w584w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w377w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_end_operation409w410w411w412w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_load_opcode158w159w160w210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_load_opcode158w159w160w161w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_load_opcode163w164w165w212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_load_opcode163w164w165w166w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_load_opcode182w183w184w222w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_load_opcode182w183w184w185w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_do_read274w275w276w277w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_do_write408w581w582w583w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w586w587w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_do_read330w374w375w376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_do_sec_erase318w319w320w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_do_sec_prot612w613w614w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_end_operation409w410w411w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_load_opcode158w159w160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_load_opcode163w164w165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_load_opcode182w183w184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_do_read274w275w276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_do_read274w275w321w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_do_write408w581w582w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_do_read330w374w375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_do_4baddr150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_do_polling420w421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_do_sec_erase318w319w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_do_sec_prot612w613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_do_write171w172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_do_write56w253w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_end_operation409w410w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode152w206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode152w153w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode173w216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode173w174w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode158w159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode176w218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode176w177w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode179w220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode179w180w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode187w224w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode187w188w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode190w226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode190w191w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode168w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode168w169w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode163w164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode182w183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode155w208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_load_opcode155w156w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_reach_max_cnt484w485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_start_poll259w260w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_do_read274w275w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_do_write408w581w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_bufdly439w440w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w490w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_do_write65w66w499w585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_do_write65w66w488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_do_write65w66w67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_do_read330w374w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_do_write65w311w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_end_operation422w423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_rden_wire315w316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_4baddr150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_bulk_erase254w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_polling420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_sec_erase318w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_sec_prot600w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_sec_prot612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_sec_prot621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_write171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_write63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_write56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_end_operation409w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_load_opcode152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_load_opcode173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_load_opcode158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_load_opcode176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_load_opcode179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_load_opcode187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_load_opcode190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_load_opcode168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_load_opcode163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_load_opcode182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_load_opcode155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_not_busy309w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_not_busy304w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_not_busy610w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_not_busy605w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_reach_max_cnt484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_bufdly447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_bufdly442w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_shift_opcode148w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_stage3_wire314w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_stage3_wire341w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_stage3_wire302w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_stage3_wire603w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_stage4_wire343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_start_poll259w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_wren_wire615w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_do_write56w272w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_bp0_wire516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_bp1_wire511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_bp2_wire522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_buf_empty553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_busy_wire2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_clkin_wire42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_4baddr404w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_bulk_erase406w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_fast_read273w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_memadd327w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_polling268w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_read274w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_read_rdid45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_read_stat46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_sec_erase407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_sec_prot405w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_wren47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_write408w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_end_add_cycle75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_end_fast_read69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_end_ophdly43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_end_pgwr_data55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_end_read72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rden_wire389w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_reach_max_cnt449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_bufdly439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_rdid_wire11w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_sid_wire10w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_status_wire26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sec_erase_wire29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sec_protect_wire14w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_st_busy_wire102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_prot_true487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_wire21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range61w62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w586w587w588w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_load_opcode190w226w227w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_load_opcode190w191w192w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_do_write65w66w488w489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_do_write65w311w312w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_rden_wire315w316w317w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_not_busy304w305w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_not_busy605w606w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_bufdly442w443w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_stage4_wire343w344w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_wren_wire615w616w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_load_opcode190w226w227w228w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_load_opcode190w191w192w193w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_do_write65w311w312w313w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w229w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w194w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w229w230w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w194w195w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w229w230w231w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w194w195w196w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w229w230w231w232w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w194w195w196w197w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w229w230w231w232w233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w194w195w196w197w198w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_w229w230w231w232w233w234w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_w194w195w196w197w198w199w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w235w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w200w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w235w236w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w200w201w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w200w201w202w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_do_read_sid130w131w132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_do_read330w331w332w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_do_read_sid130w131w132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_do_write65w66w499w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_do_read330w342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_do_read330w331w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_do_read_sid130w131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_do_sec_erase501w502w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_do_write65w66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_data0out_wire346w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_4baddr255w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_read330w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_read_sid130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_read_stat340w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_sec_erase501w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_wren256w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_do_write65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_end_operation422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_load_opcode238w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rden_wire315w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_bufdly437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range453w456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range457w459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range460w462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range463w465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range466w468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range469w471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range472w474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range475w477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL b4addr_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL be_write_prot : STD_LOGIC;
SIGNAL berase_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL bp0_wire : STD_LOGIC;
SIGNAL bp1_wire : STD_LOGIC;
SIGNAL bp2_wire : STD_LOGIC;
SIGNAL bp3_wire : STD_LOGIC;
SIGNAL buf_empty : STD_LOGIC;
SIGNAL bulk_erase_wire : STD_LOGIC;
SIGNAL busy_wire : STD_LOGIC;
SIGNAL clkin_wire : STD_LOGIC;
SIGNAL clr_rdid_wire : STD_LOGIC;
SIGNAL clr_read_wire : STD_LOGIC;
SIGNAL clr_rstat_wire : STD_LOGIC;
SIGNAL clr_secprot_wire : STD_LOGIC;
SIGNAL clr_write_wire : STD_LOGIC;
SIGNAL cnt_bfend_wire_in : STD_LOGIC;
SIGNAL data0out_wire : STD_LOGIC;
SIGNAL data_valid_wire : STD_LOGIC;
SIGNAL dataout_wire : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL do_4baddr : STD_LOGIC;
SIGNAL do_bulk_erase : STD_LOGIC;
SIGNAL do_fast_read : STD_LOGIC;
SIGNAL do_memadd : STD_LOGIC;
SIGNAL do_polling : STD_LOGIC;
SIGNAL do_read : STD_LOGIC;
SIGNAL do_read_rdid : STD_LOGIC;
SIGNAL do_read_sid : STD_LOGIC;
SIGNAL do_read_stat : STD_LOGIC;
SIGNAL do_sec_erase : STD_LOGIC;
SIGNAL do_sec_prot : STD_LOGIC;
SIGNAL do_secprot_wren : STD_LOGIC;
SIGNAL do_sprot_polling : STD_LOGIC;
SIGNAL do_sprot_rstat : STD_LOGIC;
SIGNAL do_wren : STD_LOGIC;
SIGNAL do_write : STD_LOGIC;
SIGNAL do_write_polling : STD_LOGIC;
SIGNAL do_write_rstat : STD_LOGIC;
SIGNAL do_write_wren : STD_LOGIC;
SIGNAL dummy_read_buf : STD_LOGIC;
SIGNAL end1_cyc_dlyncs_in_wire : STD_LOGIC;
SIGNAL end1_cyc_gen_cntr_wire : STD_LOGIC;
SIGNAL end1_cyc_normal_in_wire : STD_LOGIC;
SIGNAL end1_cyc_reg_in_wire : STD_LOGIC;
SIGNAL end_add_cycle : STD_LOGIC;
SIGNAL end_add_cycle_mux_datab_wire : STD_LOGIC;
SIGNAL end_fast_read : STD_LOGIC;
SIGNAL end_one_cyc_pos : STD_LOGIC;
SIGNAL end_one_cycle : STD_LOGIC;
SIGNAL end_operation : STD_LOGIC;
SIGNAL end_opfdly : STD_LOGIC;
SIGNAL end_ophdly : STD_LOGIC;
SIGNAL end_pgwr_data : STD_LOGIC;
SIGNAL end_read : STD_LOGIC;
SIGNAL end_read_byte : STD_LOGIC;
SIGNAL end_wrstage : STD_LOGIC;
SIGNAL fast_read_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL fast_read_wire : STD_LOGIC;
SIGNAL ill_erase_wire : STD_LOGIC;
SIGNAL ill_write_wire : STD_LOGIC;
SIGNAL illegal_erase_b4out_wire : STD_LOGIC;
SIGNAL illegal_write_b4out_wire : STD_LOGIC;
SIGNAL in_operation : STD_LOGIC;
SIGNAL load_opcode : STD_LOGIC;
SIGNAL memadd_sdoin : STD_LOGIC;
SIGNAL not_busy : STD_LOGIC;
SIGNAL oe_wire : STD_LOGIC;
SIGNAL page_size_wire : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL pagewr_buf_not_empty : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL rden_wire : STD_LOGIC;
SIGNAL rdid_load : STD_LOGIC;
SIGNAL rdid_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL reach_max_cnt : STD_LOGIC;
SIGNAL read_buf : STD_LOGIC;
SIGNAL read_bufdly : STD_LOGIC;
SIGNAL read_data_reg_in_wire : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL read_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL read_rdid_wire : STD_LOGIC;
SIGNAL read_sid_wire : STD_LOGIC;
SIGNAL read_status_wire : STD_LOGIC;
SIGNAL read_wire : STD_LOGIC;
SIGNAL rsid_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL rsid_sdoin : STD_LOGIC;
SIGNAL rstat_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL scein_wire : STD_LOGIC;
SIGNAL sdoin_wire : STD_LOGIC;
SIGNAL sec_erase_wire : STD_LOGIC;
SIGNAL sec_protect_wire : STD_LOGIC;
SIGNAL secprot_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL secprot_sdoin : STD_LOGIC;
SIGNAL serase_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL shift_bytes_wire : STD_LOGIC;
SIGNAL shift_opcode : STD_LOGIC;
SIGNAL shift_opdata : STD_LOGIC;
SIGNAL shift_pgwr_data : STD_LOGIC;
SIGNAL st_busy_wire : STD_LOGIC;
SIGNAL stage2_wire : STD_LOGIC;
SIGNAL stage3_wire : STD_LOGIC;
SIGNAL stage4_wire : STD_LOGIC;
SIGNAL start_poll : STD_LOGIC;
SIGNAL start_sppoll : STD_LOGIC;
SIGNAL start_wrpoll : STD_LOGIC;
SIGNAL to_sdoin_wire : STD_LOGIC;
SIGNAL wren_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wren_wire : STD_LOGIC;
SIGNAL write_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL write_prot_true : STD_LOGIC;
SIGNAL write_sdoin : STD_LOGIC;
SIGNAL write_wire : STD_LOGIC;
SIGNAL wire_w_addr_range308w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_addr_range303w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_b4addr_opcode_range205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_b4addr_opcode_range149w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_berase_opcode_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_berase_opcode_range157w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_datain_range609w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datain_range604w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_dataout_wire_range345w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_fast_read_opcode_range217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_fast_read_opcode_range175w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_pagewr_buf_not_empty_range453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_pagewr_buf_not_empty_range457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_pagewr_buf_not_empty_range460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_pagewr_buf_not_empty_range463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_pagewr_buf_not_empty_range466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_pagewr_buf_not_empty_range469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_pagewr_buf_not_empty_range472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_pagewr_buf_not_empty_range475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_pagewr_buf_not_empty_range61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rdid_opcode_range223w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rdid_opcode_range186w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_read_opcode_range219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_read_opcode_range178w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_rsid_opcode_range225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rsid_opcode_range189w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_rstat_opcode_range213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rstat_opcode_range167w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_secprot_opcode_range221w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_secprot_opcode_range181w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_serase_opcode_range211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_serase_opcode_range162w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_wren_opcode_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_wren_opcode_range154w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_w_write_opcode_range215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_write_opcode_range170w : STD_LOGIC_VECTOR (6 DOWNTO 0);
COMPONENT a_graycounter
GENERIC
(
PVALUE : NATURAL := 0;
WIDTH : NATURAL := 8;
lpm_type : STRING := "a_graycounter"
);
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
cnt_en : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0);
qbin : OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0);
sclr : IN STD_LOGIC := '0';
updown : IN STD_LOGIC := '1'
);
END COMPONENT;
COMPONENT cycloneii_asmiblock
PORT
(
data0out : OUT STD_LOGIC;
dclkin : IN STD_LOGIC;
oe : IN STD_LOGIC := '1';
scein : IN STD_LOGIC;
sdoin : IN STD_LOGIC
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT lpm_counter
GENERIC
(
lpm_avalue : STRING := "0";
lpm_direction : STRING := "DEFAULT";
lpm_modulus : NATURAL := 0;
lpm_port_updown : STRING := "PORT_CONNECTIVITY";
lpm_pvalue : STRING := "0";
lpm_svalue : STRING := "0";
lpm_width : NATURAL;
lpm_type : STRING := "lpm_counter"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aload : IN STD_LOGIC := '0';
aset : IN STD_LOGIC := '0';
cin : IN STD_LOGIC := '1';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
cnt_en : IN STD_LOGIC := '1';
cout : OUT STD_LOGIC;
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
eq : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
sclr : IN STD_LOGIC := '0';
sload : IN STD_LOGIC := '0';
sset : IN STD_LOGIC := '0';
updown : IN STD_LOGIC := '1'
);
END COMPONENT;
COMPONENT scfifo
GENERIC
(
ADD_RAM_OUTPUT_REGISTER : STRING := "OFF";
ALLOW_RWCYCLE_WHEN_FULL : STRING := "OFF";
ALMOST_EMPTY_VALUE : NATURAL := 0;
ALMOST_FULL_VALUE : NATURAL := 0;
LPM_NUMWORDS : NATURAL;
LPM_SHOWAHEAD : STRING := "OFF";
LPM_WIDTH : NATURAL;
LPM_WIDTHU : NATURAL := 1;
OVERFLOW_CHECKING : STRING := "ON";
UNDERFLOW_CHECKING : STRING := "ON";
USE_EAB : STRING := "ON";
lpm_type : STRING := "scfifo"
);
PORT
(
aclr : IN STD_LOGIC := '0';
almost_empty : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
clock : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
empty : OUT STD_LOGIC;
full : OUT STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
rdreq : IN STD_LOGIC;
sclr : IN STD_LOGIC := '0';
usedw : OUT STD_LOGIC_VECTOR(LPM_WIDTHU-1 DOWNTO 0);
wrreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
wire_w_lg_w413w414w(0) <= wire_w413w(0) AND wire_w_lg_do_4baddr404w(0);
wire_w413w(0) <= wire_w_lg_w_lg_w_lg_w_lg_end_operation409w410w411w412w(0) AND wire_w_lg_do_sec_prot405w(0);
wire_w584w(0) <= wire_w_lg_w_lg_w_lg_w_lg_do_write408w581w582w583w(0) AND end_operation;
wire_w377w(0) <= wire_w_lg_w_lg_w_lg_w_lg_do_read330w374w375w376w(0) AND end_read_byte;
wire_w_lg_w_lg_w_lg_w_lg_end_operation409w410w411w412w(0) <= wire_w_lg_w_lg_w_lg_end_operation409w410w411w(0) AND wire_w_lg_do_bulk_erase406w(0);
wire_w_lg_w_lg_w_lg_w_lg_load_opcode158w159w160w210w(0) <= wire_w_lg_w_lg_w_lg_load_opcode158w159w160w(0) AND wire_w_berase_opcode_range209w(0);
loop0 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_w_lg_w_lg_load_opcode158w159w160w161w(i) <= wire_w_lg_w_lg_w_lg_load_opcode158w159w160w(0) AND wire_w_berase_opcode_range157w(i);
END GENERATE loop0;
wire_w_lg_w_lg_w_lg_w_lg_load_opcode163w164w165w212w(0) <= wire_w_lg_w_lg_w_lg_load_opcode163w164w165w(0) AND wire_w_serase_opcode_range211w(0);
loop1 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_w_lg_w_lg_load_opcode163w164w165w166w(i) <= wire_w_lg_w_lg_w_lg_load_opcode163w164w165w(0) AND wire_w_serase_opcode_range162w(i);
END GENERATE loop1;
wire_w_lg_w_lg_w_lg_w_lg_load_opcode182w183w184w222w(0) <= wire_w_lg_w_lg_w_lg_load_opcode182w183w184w(0) AND wire_w_secprot_opcode_range221w(0);
loop2 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_w_lg_w_lg_load_opcode182w183w184w185w(i) <= wire_w_lg_w_lg_w_lg_load_opcode182w183w184w(0) AND wire_w_secprot_opcode_range181w(i);
END GENERATE loop2;
wire_w_lg_w_lg_w_lg_w_lg_do_read274w275w276w277w(0) <= wire_w_lg_w_lg_w_lg_do_read274w275w276w(0) AND end_one_cycle;
wire_w_lg_w_lg_w_lg_w_lg_do_write408w581w582w583w(0) <= wire_w_lg_w_lg_w_lg_do_write408w581w582w(0) AND wire_w_lg_do_4baddr404w(0);
wire_w_lg_w586w587w(0) <= wire_w586w(0) AND end_operation;
wire_w_lg_w_lg_w_lg_w_lg_do_read330w374w375w376w(0) <= wire_w_lg_w_lg_w_lg_do_read330w374w375w(0) AND end_one_cyc_pos;
wire_w_lg_w_lg_w_lg_do_sec_erase318w319w320w(0) <= wire_w_lg_w_lg_do_sec_erase318w319w(0) AND end_operation;
wire_w_lg_w_lg_w_lg_do_sec_prot612w613w614w(0) <= wire_w_lg_w_lg_do_sec_prot612w613w(0) AND wire_spstage_cntr_w_q_range596w(0);
wire_w_lg_w_lg_w_lg_end_operation409w410w411w(0) <= wire_w_lg_w_lg_end_operation409w410w(0) AND wire_w_lg_do_sec_erase407w(0);
wire_w_lg_w_lg_w_lg_load_opcode158w159w160w(0) <= wire_w_lg_w_lg_load_opcode158w159w(0) AND wire_w_lg_do_read_stat46w(0);
wire_w_lg_w_lg_w_lg_load_opcode163w164w165w(0) <= wire_w_lg_w_lg_load_opcode163w164w(0) AND wire_w_lg_do_read_stat46w(0);
wire_w_lg_w_lg_w_lg_load_opcode182w183w184w(0) <= wire_w_lg_w_lg_load_opcode182w183w(0) AND wire_w_lg_do_read_stat46w(0);
wire_w_lg_w_lg_w_lg_do_read274w275w276w(0) <= wire_w_lg_w_lg_do_read274w275w(0) AND wire_w_lg_w_lg_do_write56w272w(0);
wire_w_lg_w_lg_w_lg_do_read274w275w321w(0) <= wire_w_lg_w_lg_do_read274w275w(0) AND clr_write_wire;
wire_w_lg_w_lg_w_lg_do_write408w581w582w(0) <= wire_w_lg_w_lg_do_write408w581w(0) AND wire_w_lg_do_bulk_erase406w(0);
wire_w586w(0) <= wire_w_lg_w_lg_w_lg_w_lg_do_write65w66w499w585w(0) AND wire_wrstage_cntr_w_lg_w_q_range492w493w(0);
wire_w_lg_w_lg_w_lg_do_read330w374w375w(0) <= wire_w_lg_w_lg_do_read330w374w(0) AND wire_stage_cntr_w_lg_w_q_range88w93w(0);
wire_w_lg_w_lg_do_4baddr150w151w(0) <= wire_w_lg_do_4baddr150w(0) AND wire_w_lg_do_wren47w(0);
wire_w_lg_w_lg_do_polling420w421w(0) <= wire_w_lg_do_polling420w(0) AND stage3_dly_reg;
wire_w_lg_w_lg_do_sec_erase318w319w(0) <= wire_w_lg_do_sec_erase318w(0) AND wire_w_lg_do_read_stat46w(0);
wire_w_lg_w_lg_do_sec_prot612w613w(0) <= wire_w_lg_do_sec_prot612w(0) AND wire_spstage_cntr_w_lg_w_q_range598w599w(0);
wire_w_lg_w_lg_do_write171w172w(0) <= wire_w_lg_do_write171w(0) AND wire_w_lg_do_wren47w(0);
wire_w_lg_w_lg_do_write56w253w(0) <= wire_w_lg_do_write56w(0) AND end_pgwr_data;
wire_w_lg_w_lg_end_operation409w410w(0) <= wire_w_lg_end_operation409w(0) AND wire_w_lg_do_write408w(0);
wire_w_lg_w_lg_load_opcode152w206w(0) <= wire_w_lg_load_opcode152w(0) AND wire_w_b4addr_opcode_range205w(0);
loop3 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_load_opcode152w153w(i) <= wire_w_lg_load_opcode152w(0) AND wire_w_b4addr_opcode_range149w(i);
END GENERATE loop3;
wire_w_lg_w_lg_load_opcode173w216w(0) <= wire_w_lg_load_opcode173w(0) AND wire_w_write_opcode_range215w(0);
loop4 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_load_opcode173w174w(i) <= wire_w_lg_load_opcode173w(0) AND wire_w_write_opcode_range170w(i);
END GENERATE loop4;
wire_w_lg_w_lg_load_opcode158w159w(0) <= wire_w_lg_load_opcode158w(0) AND wire_w_lg_do_wren47w(0);
wire_w_lg_w_lg_load_opcode176w218w(0) <= wire_w_lg_load_opcode176w(0) AND wire_w_fast_read_opcode_range217w(0);
loop5 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_load_opcode176w177w(i) <= wire_w_lg_load_opcode176w(0) AND wire_w_fast_read_opcode_range175w(i);
END GENERATE loop5;
wire_w_lg_w_lg_load_opcode179w220w(0) <= wire_w_lg_load_opcode179w(0) AND wire_w_read_opcode_range219w(0);
loop6 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_load_opcode179w180w(i) <= wire_w_lg_load_opcode179w(0) AND wire_w_read_opcode_range178w(i);
END GENERATE loop6;
wire_w_lg_w_lg_load_opcode187w224w(0) <= wire_w_lg_load_opcode187w(0) AND wire_w_rdid_opcode_range223w(0);
loop7 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_load_opcode187w188w(i) <= wire_w_lg_load_opcode187w(0) AND wire_w_rdid_opcode_range186w(i);
END GENERATE loop7;
wire_w_lg_w_lg_load_opcode190w226w(0) <= wire_w_lg_load_opcode190w(0) AND wire_w_rsid_opcode_range225w(0);
loop8 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_load_opcode190w191w(i) <= wire_w_lg_load_opcode190w(0) AND wire_w_rsid_opcode_range189w(i);
END GENERATE loop8;
wire_w_lg_w_lg_load_opcode168w214w(0) <= wire_w_lg_load_opcode168w(0) AND wire_w_rstat_opcode_range213w(0);
loop9 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_load_opcode168w169w(i) <= wire_w_lg_load_opcode168w(0) AND wire_w_rstat_opcode_range167w(i);
END GENERATE loop9;
wire_w_lg_w_lg_load_opcode163w164w(0) <= wire_w_lg_load_opcode163w(0) AND wire_w_lg_do_wren47w(0);
wire_w_lg_w_lg_load_opcode182w183w(0) <= wire_w_lg_load_opcode182w(0) AND wire_w_lg_do_wren47w(0);
wire_w_lg_w_lg_load_opcode155w208w(0) <= wire_w_lg_load_opcode155w(0) AND wire_w_wren_opcode_range207w(0);
loop10 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_load_opcode155w156w(i) <= wire_w_lg_load_opcode155w(0) AND wire_w_wren_opcode_range154w(i);
END GENERATE loop10;
wire_w_lg_w_lg_reach_max_cnt484w485w(0) <= wire_w_lg_reach_max_cnt484w(0) AND wren_wire;
wire_w_lg_w_lg_start_poll259w260w(0) <= wire_w_lg_start_poll259w(0) AND do_polling;
wire_w_lg_w_lg_do_read274w275w(0) <= wire_w_lg_do_read274w(0) AND wire_w_lg_do_fast_read273w(0);
wire_w_lg_w_lg_do_write408w581w(0) <= wire_w_lg_do_write408w(0) AND wire_w_lg_do_sec_erase407w(0);
loop11 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_read_bufdly439w440w(i) <= wire_w_lg_read_bufdly439w(0) AND wire_pgwrbuf_dataout_w_q_range438w(i);
END GENERATE loop11;
wire_w490w(0) <= wire_w_lg_w_lg_w_lg_w_lg_do_write65w66w488w489w(0) AND end_wrstage;
wire_w_lg_w_lg_w_lg_w_lg_do_write65w66w499w585w(0) <= wire_w_lg_w_lg_w_lg_do_write65w66w499w(0) AND wire_wrstage_cntr_w_q_range494w(0);
wire_w_lg_w_lg_w_lg_do_write65w66w488w(0) <= wire_w_lg_w_lg_do_write65w66w(0) AND wire_w_lg_write_prot_true487w(0);
wire_w_lg_w_lg_w_lg_do_write65w66w67w(0) <= wire_w_lg_w_lg_do_write65w66w(0) AND write_prot_true;
wire_w_lg_w_lg_do_read330w374w(0) <= wire_w_lg_do_read330w(0) AND wire_stage_cntr_w_q_range89w(0);
wire_w_lg_w_lg_do_write65w311w(0) <= wire_w_lg_do_write65w(0) AND do_memadd;
wire_w_lg_w_lg_end_operation422w423w(0) <= wire_w_lg_end_operation422w(0) AND do_read_stat;
wire_w_lg_w_lg_rden_wire315w316w(0) <= wire_w_lg_rden_wire315w(0) AND not_busy;
wire_w_lg_do_4baddr150w(0) <= do_4baddr AND wire_w_lg_do_read_stat46w(0);
wire_w_lg_do_bulk_erase254w(0) <= do_bulk_erase AND wire_w_lg_do_read_stat46w(0);
wire_w_lg_do_polling420w(0) <= do_polling AND end_one_cyc_pos;
wire_w_lg_do_sec_erase318w(0) <= do_sec_erase AND wire_w_lg_do_wren47w(0);
wire_w_lg_do_sec_prot600w(0) <= do_sec_prot AND wire_spstage_cntr_w_lg_w_q_range598w599w(0);
wire_w_lg_do_sec_prot612w(0) <= do_sec_prot AND stage3_wire;
wire_w_lg_do_sec_prot621w(0) <= do_sec_prot AND wire_spstage_cntr_w_q_range598w(0);
wire_w_lg_do_write171w(0) <= do_write AND wire_w_lg_do_read_stat46w(0);
wire_w_lg_do_write63w(0) <= do_write AND wire_w_lg_w_pagewr_buf_not_empty_range61w62w(0);
wire_w_lg_do_write56w(0) <= do_write AND shift_pgwr_data;
wire_w_lg_end_operation409w(0) <= end_operation AND do_read_stat;
wire_w_lg_load_opcode152w(0) <= load_opcode AND wire_w_lg_w_lg_do_4baddr150w151w(0);
wire_w_lg_load_opcode173w(0) <= load_opcode AND wire_w_lg_w_lg_do_write171w172w(0);
wire_w_lg_load_opcode158w(0) <= load_opcode AND do_bulk_erase;
wire_w_lg_load_opcode176w(0) <= load_opcode AND do_fast_read;
wire_w_lg_load_opcode179w(0) <= load_opcode AND do_read;
wire_w_lg_load_opcode187w(0) <= load_opcode AND do_read_rdid;
wire_w_lg_load_opcode190w(0) <= load_opcode AND do_read_sid;
wire_w_lg_load_opcode168w(0) <= load_opcode AND do_read_stat;
wire_w_lg_load_opcode163w(0) <= load_opcode AND do_sec_erase;
wire_w_lg_load_opcode182w(0) <= load_opcode AND do_sec_prot;
wire_w_lg_load_opcode155w(0) <= load_opcode AND do_wren;
wire_w_lg_not_busy309w(0) <= not_busy AND wire_w_addr_range308w(0);
loop12 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_not_busy304w(i) <= not_busy AND wire_w_addr_range303w(i);
END GENERATE loop12;
wire_w_lg_not_busy610w(0) <= not_busy AND wire_w_datain_range609w(0);
loop13 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_not_busy605w(i) <= not_busy AND wire_w_datain_range604w(i);
END GENERATE loop13;
wire_w_lg_reach_max_cnt484w(0) <= reach_max_cnt AND shift_bytes_wire;
wire_w_lg_read_bufdly447w(0) <= read_bufdly AND wire_scfifo4_w_q_range446w(0);
loop14 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_read_bufdly442w(i) <= read_bufdly AND wire_scfifo4_w_q_range441w(i);
END GENERATE loop14;
loop15 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_shift_opcode148w(i) <= shift_opcode AND wire_asmi_opcode_reg_w_q_range147w(i);
END GENERATE loop15;
wire_w_lg_stage3_wire314w(0) <= stage3_wire AND wire_w_lg_w_lg_w_lg_w_lg_do_write65w311w312w313w(0);
wire_w_lg_stage3_wire341w(0) <= stage3_wire AND wire_w_lg_do_read_stat340w(0);
loop16 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_stage3_wire302w(i) <= stage3_wire AND wire_addr_reg_w_q_range301w(i);
END GENERATE loop16;
loop17 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_stage3_wire603w(i) <= stage3_wire AND wire_wrstat_dreg_w_q_range602w(i);
END GENERATE loop17;
wire_w_lg_stage4_wire343w(0) <= stage4_wire AND wire_w_lg_w_lg_do_read330w342w(0);
wire_w_lg_start_poll259w(0) <= start_poll AND do_read_stat;
wire_w_lg_wren_wire615w(0) <= wren_wire AND not_busy;
wire_w_lg_w_lg_do_write56w272w(0) <= NOT wire_w_lg_do_write56w(0);
wire_w_lg_bp0_wire516w(0) <= NOT bp0_wire;
wire_w_lg_bp1_wire511w(0) <= NOT bp1_wire;
wire_w_lg_bp2_wire522w(0) <= NOT bp2_wire;
wire_w_lg_buf_empty553w(0) <= NOT buf_empty;
wire_w_lg_busy_wire2w(0) <= NOT busy_wire;
wire_w_lg_clkin_wire42w(0) <= NOT clkin_wire;
wire_w_lg_do_4baddr404w(0) <= NOT do_4baddr;
wire_w_lg_do_bulk_erase406w(0) <= NOT do_bulk_erase;
wire_w_lg_do_fast_read273w(0) <= NOT do_fast_read;
wire_w_lg_do_memadd327w(0) <= NOT do_memadd;
wire_w_lg_do_polling268w(0) <= NOT do_polling;
wire_w_lg_do_read274w(0) <= NOT do_read;
wire_w_lg_do_read_rdid45w(0) <= NOT do_read_rdid;
wire_w_lg_do_read_stat46w(0) <= NOT do_read_stat;
wire_w_lg_do_sec_erase407w(0) <= NOT do_sec_erase;
wire_w_lg_do_sec_prot405w(0) <= NOT do_sec_prot;
wire_w_lg_do_wren47w(0) <= NOT do_wren;
wire_w_lg_do_write408w(0) <= NOT do_write;
wire_w_lg_end_add_cycle75w(0) <= NOT end_add_cycle;
wire_w_lg_end_fast_read69w(0) <= NOT end_fast_read;
wire_w_lg_end_ophdly43w(0) <= NOT end_ophdly;
wire_w_lg_end_pgwr_data55w(0) <= NOT end_pgwr_data;
wire_w_lg_end_read72w(0) <= NOT end_read;
wire_w_lg_rden_wire389w(0) <= NOT rden_wire;
wire_w_lg_reach_max_cnt449w(0) <= NOT reach_max_cnt;
wire_w_lg_read_bufdly439w(0) <= NOT read_bufdly;
wire_w_lg_read_rdid_wire11w(0) <= NOT read_rdid_wire;
wire_w_lg_read_sid_wire10w(0) <= NOT read_sid_wire;
wire_w_lg_read_status_wire26w(0) <= NOT read_status_wire;
wire_w_lg_sec_erase_wire29w(0) <= NOT sec_erase_wire;
wire_w_lg_sec_protect_wire14w(0) <= NOT sec_protect_wire;
wire_w_lg_st_busy_wire102w(0) <= NOT st_busy_wire;
wire_w_lg_write_prot_true487w(0) <= NOT write_prot_true;
wire_w_lg_write_wire21w(0) <= NOT write_wire;
wire_w_lg_w_pagewr_buf_not_empty_range61w62w(0) <= NOT wire_w_pagewr_buf_not_empty_range61w(0);
wire_w_lg_w_lg_w586w587w588w(0) <= wire_w_lg_w586w587w(0) OR write_prot_true;
wire_w_lg_w_lg_w_lg_load_opcode190w226w227w(0) <= wire_w_lg_w_lg_load_opcode190w226w(0) OR wire_w_lg_w_lg_load_opcode187w224w(0);
loop18 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_w_lg_load_opcode190w191w192w(i) <= wire_w_lg_w_lg_load_opcode190w191w(i) OR wire_w_lg_w_lg_load_opcode187w188w(i);
END GENERATE loop18;
wire_w_lg_w_lg_w_lg_w_lg_do_write65w66w488w489w(0) <= wire_w_lg_w_lg_w_lg_do_write65w66w488w(0) OR do_4baddr;
wire_w_lg_w_lg_w_lg_do_write65w311w312w(0) <= wire_w_lg_w_lg_do_write65w311w(0) OR do_read;
wire_w_lg_w_lg_w_lg_rden_wire315w316w317w(0) <= wire_w_lg_w_lg_rden_wire315w316w(0) OR wire_w_lg_stage3_wire314w(0);
loop19 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_not_busy304w305w(i) <= wire_w_lg_not_busy304w(i) OR wire_w_lg_stage3_wire302w(i);
END GENERATE loop19;
loop20 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_not_busy605w606w(i) <= wire_w_lg_not_busy605w(i) OR wire_w_lg_stage3_wire603w(i);
END GENERATE loop20;
loop21 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_read_bufdly442w443w(i) <= wire_w_lg_read_bufdly442w(i) OR wire_w_lg_w_lg_read_bufdly439w440w(i);
END GENERATE loop21;
wire_w_lg_w_lg_stage4_wire343w344w(0) <= wire_w_lg_stage4_wire343w(0) OR wire_w_lg_stage3_wire341w(0);
wire_w_lg_w_lg_wren_wire615w616w(0) <= wire_w_lg_wren_wire615w(0) OR wire_w_lg_w_lg_w_lg_do_sec_prot612w613w614w(0);
wire_w_lg_w_lg_w_lg_w_lg_load_opcode190w226w227w228w(0) <= wire_w_lg_w_lg_w_lg_load_opcode190w226w227w(0) OR wire_w_lg_w_lg_w_lg_w_lg_load_opcode182w183w184w222w(0);
loop22 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_w_lg_w_lg_load_opcode190w191w192w193w(i) <= wire_w_lg_w_lg_w_lg_load_opcode190w191w192w(i) OR wire_w_lg_w_lg_w_lg_w_lg_load_opcode182w183w184w185w(i);
END GENERATE loop22;
wire_w_lg_w_lg_w_lg_w_lg_do_write65w311w312w313w(0) <= wire_w_lg_w_lg_w_lg_do_write65w311w312w(0) OR do_fast_read;
wire_w229w(0) <= wire_w_lg_w_lg_w_lg_w_lg_load_opcode190w226w227w228w(0) OR wire_w_lg_w_lg_load_opcode179w220w(0);
loop23 : FOR i IN 0 TO 6 GENERATE
wire_w194w(i) <= wire_w_lg_w_lg_w_lg_w_lg_load_opcode190w191w192w193w(i) OR wire_w_lg_w_lg_load_opcode179w180w(i);
END GENERATE loop23;
wire_w_lg_w229w230w(0) <= wire_w229w(0) OR wire_w_lg_w_lg_load_opcode176w218w(0);
loop24 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w194w195w(i) <= wire_w194w(i) OR wire_w_lg_w_lg_load_opcode176w177w(i);
END GENERATE loop24;
wire_w_lg_w_lg_w229w230w231w(0) <= wire_w_lg_w229w230w(0) OR wire_w_lg_w_lg_load_opcode173w216w(0);
loop25 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_w194w195w196w(i) <= wire_w_lg_w194w195w(i) OR wire_w_lg_w_lg_load_opcode173w174w(i);
END GENERATE loop25;
wire_w_lg_w_lg_w_lg_w229w230w231w232w(0) <= wire_w_lg_w_lg_w229w230w231w(0) OR wire_w_lg_w_lg_load_opcode168w214w(0);
loop26 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_w_lg_w194w195w196w197w(i) <= wire_w_lg_w_lg_w194w195w196w(i) OR wire_w_lg_w_lg_load_opcode168w169w(i);
END GENERATE loop26;
wire_w_lg_w_lg_w_lg_w_lg_w229w230w231w232w233w(0) <= wire_w_lg_w_lg_w_lg_w229w230w231w232w(0) OR wire_w_lg_w_lg_w_lg_w_lg_load_opcode163w164w165w212w(0);
loop27 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_w_lg_w_lg_w194w195w196w197w198w(i) <= wire_w_lg_w_lg_w_lg_w194w195w196w197w(i) OR wire_w_lg_w_lg_w_lg_w_lg_load_opcode163w164w165w166w(i);
END GENERATE loop27;
wire_w_lg_w_lg_w_lg_w_lg_w_lg_w229w230w231w232w233w234w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w229w230w231w232w233w(0) OR wire_w_lg_w_lg_w_lg_w_lg_load_opcode158w159w160w210w(0);
loop28 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_w_lg_w_lg_w_lg_w194w195w196w197w198w199w(i) <= wire_w_lg_w_lg_w_lg_w_lg_w194w195w196w197w198w(i) OR wire_w_lg_w_lg_w_lg_w_lg_load_opcode158w159w160w161w(i);
END GENERATE loop28;
wire_w235w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w_lg_w229w230w231w232w233w234w(0) OR wire_w_lg_w_lg_load_opcode155w208w(0);
loop29 : FOR i IN 0 TO 6 GENERATE
wire_w200w(i) <= wire_w_lg_w_lg_w_lg_w_lg_w_lg_w194w195w196w197w198w199w(i) OR wire_w_lg_w_lg_load_opcode155w156w(i);
END GENERATE loop29;
wire_w_lg_w235w236w(0) <= wire_w235w(0) OR wire_w_lg_w_lg_load_opcode152w206w(0);
loop30 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w200w201w(i) <= wire_w200w(i) OR wire_w_lg_w_lg_load_opcode152w153w(i);
END GENERATE loop30;
loop31 : FOR i IN 0 TO 6 GENERATE
wire_w_lg_w_lg_w200w201w202w(i) <= wire_w_lg_w200w201w(i) OR wire_w_lg_shift_opcode148w(i);
END GENERATE loop31;
wire_w134w(0) <= wire_w_lg_w_lg_w_lg_w_lg_do_read_sid130w131w132w133w(0) OR do_read_rdid;
wire_w_lg_w_lg_w_lg_w_lg_do_read_sid130w131w132w133w(0) <= wire_w_lg_w_lg_w_lg_do_read_sid130w131w132w(0) OR do_sec_erase;
wire_w_lg_w_lg_w_lg_do_read330w331w332w(0) <= wire_w_lg_w_lg_do_read330w331w(0) OR do_sec_erase;
wire_w_lg_w_lg_w_lg_do_read_sid130w131w132w(0) <= wire_w_lg_w_lg_do_read_sid130w131w(0) OR do_write;
wire_w_lg_w_lg_w_lg_do_write65w66w499w(0) <= wire_w_lg_w_lg_do_write65w66w(0) OR do_4baddr;
wire_w_lg_w_lg_do_read330w342w(0) <= wire_w_lg_do_read330w(0) OR do_read_sid;
wire_w_lg_w_lg_do_read330w331w(0) <= wire_w_lg_do_read330w(0) OR do_write;
wire_w_lg_w_lg_do_read_sid130w131w(0) <= wire_w_lg_do_read_sid130w(0) OR do_fast_read;
wire_w_lg_w_lg_do_sec_erase501w502w(0) <= wire_w_lg_do_sec_erase501w(0) OR do_bulk_erase;
wire_w_lg_w_lg_do_write65w66w(0) <= wire_w_lg_do_write65w(0) OR do_bulk_erase;
wire_w_lg_data0out_wire346w(0) <= data0out_wire OR wire_w_dataout_wire_range345w(0);
wire_w_lg_do_4baddr255w(0) <= do_4baddr OR wire_w_lg_do_bulk_erase254w(0);
wire_w_lg_do_read330w(0) <= do_read OR do_fast_read;
wire_w_lg_do_read_sid130w(0) <= do_read_sid OR do_read;
wire_w_lg_do_read_stat340w(0) <= do_read_stat OR do_read_rdid;
wire_w_lg_do_sec_erase501w(0) <= do_sec_erase OR do_write;
wire_w_lg_do_wren256w(0) <= do_wren OR wire_w_lg_do_4baddr255w(0);
wire_w_lg_do_write65w(0) <= do_write OR do_sec_erase;
wire_w_lg_end_operation422w(0) <= end_operation OR wire_w_lg_w_lg_do_polling420w421w(0);
wire_w_lg_load_opcode238w(0) <= load_opcode OR shift_opcode;
wire_w_lg_rden_wire315w(0) <= rden_wire OR wren_wire;
wire_w_lg_read_bufdly437w(0) <= read_bufdly OR shift_pgwr_data;
wire_w_lg_w_pagewr_buf_not_empty_range453w456w(0) <= wire_w_pagewr_buf_not_empty_range453w(0) OR wire_pgwr_data_cntr_w_q_range455w(0);
wire_w_lg_w_pagewr_buf_not_empty_range457w459w(0) <= wire_w_pagewr_buf_not_empty_range457w(0) OR wire_pgwr_data_cntr_w_q_range458w(0);
wire_w_lg_w_pagewr_buf_not_empty_range460w462w(0) <= wire_w_pagewr_buf_not_empty_range460w(0) OR wire_pgwr_data_cntr_w_q_range461w(0);
wire_w_lg_w_pagewr_buf_not_empty_range463w465w(0) <= wire_w_pagewr_buf_not_empty_range463w(0) OR wire_pgwr_data_cntr_w_q_range464w(0);
wire_w_lg_w_pagewr_buf_not_empty_range466w468w(0) <= wire_w_pagewr_buf_not_empty_range466w(0) OR wire_pgwr_data_cntr_w_q_range467w(0);
wire_w_lg_w_pagewr_buf_not_empty_range469w471w(0) <= wire_w_pagewr_buf_not_empty_range469w(0) OR wire_pgwr_data_cntr_w_q_range470w(0);
wire_w_lg_w_pagewr_buf_not_empty_range472w474w(0) <= wire_w_pagewr_buf_not_empty_range472w(0) OR wire_pgwr_data_cntr_w_q_range473w(0);
wire_w_lg_w_pagewr_buf_not_empty_range475w477w(0) <= wire_w_pagewr_buf_not_empty_range475w(0) OR wire_pgwr_data_cntr_w_q_range476w(0);
b4addr_opcode <= (OTHERS => '0');
be_write_prot <= (do_bulk_erase AND (((bp3_wire OR bp2_wire) OR bp1_wire) OR bp0_wire));
berase_opcode <= "11000111";
bp0_wire <= statreg_int(2);
bp1_wire <= statreg_int(3);
bp2_wire <= statreg_int(4);
bp3_wire <= statreg_int(6);
buf_empty <= buf_empty_reg;
bulk_erase_wire <= bulk_erase_reg;
busy <= (busy_wire OR busy_delay_reg);
busy_wire <= (((((((((do_read_rdid OR do_read_sid) OR do_read) OR do_fast_read) OR do_write) OR do_sec_prot) OR do_read_stat) OR do_sec_erase) OR do_bulk_erase) OR do_4baddr);
clkin_wire <= clkin;
clr_rdid_wire <= clr_rdid_reg2;
clr_read_wire <= clr_read_reg2;
clr_rstat_wire <= clr_rstat_reg2;
clr_secprot_wire <= clr_secprot_reg2;
clr_write_wire <= clr_write_reg2;
cnt_bfend_wire_in <= (wire_gen_cntr_w_lg_w_q_range99w100w(0) AND wire_gen_cntr_q(0));
data0out_wire <= wire_cycloneii_asmiblock3_data0out;
data_valid <= data_valid_wire;
data_valid_wire <= dvalid_reg2;
dataout <= ( read_data_reg(7 DOWNTO 0));
dataout_wire <= ( "0000");
do_4baddr <= '0';
do_bulk_erase <= (((((((wire_w_lg_read_rdid_wire11w(0) AND wire_w_lg_read_sid_wire10w(0)) AND wire_w_lg_sec_protect_wire14w(0)) AND (NOT (read_wire OR fast_read_wire))) AND wire_w_lg_write_wire21w(0)) AND wire_w_lg_read_status_wire26w(0)) AND wire_w_lg_sec_erase_wire29w(0)) AND bulk_erase_wire);
do_fast_read <= (((wire_w_lg_read_rdid_wire11w(0) AND wire_w_lg_read_sid_wire10w(0)) AND wire_w_lg_sec_protect_wire14w(0)) AND fast_read_wire);
do_memadd <= do_wrmemadd_reg;
do_polling <= (do_write_polling OR do_sprot_polling);
do_read <= '0';
do_read_rdid <= read_rdid_wire;
do_read_sid <= '0';
do_read_stat <= (((((((wire_w_lg_read_rdid_wire11w(0) AND wire_w_lg_read_sid_wire10w(0)) AND wire_w_lg_sec_protect_wire14w(0)) AND (NOT (read_wire OR fast_read_wire))) AND wire_w_lg_write_wire21w(0)) AND read_status_wire) OR do_write_rstat) OR do_sprot_rstat);
do_sec_erase <= ((((((wire_w_lg_read_rdid_wire11w(0) AND wire_w_lg_read_sid_wire10w(0)) AND wire_w_lg_sec_protect_wire14w(0)) AND (NOT (read_wire OR fast_read_wire))) AND wire_w_lg_write_wire21w(0)) AND wire_w_lg_read_status_wire26w(0)) AND sec_erase_wire);
do_sec_prot <= ((wire_w_lg_read_rdid_wire11w(0) AND wire_w_lg_read_sid_wire10w(0)) AND sec_protect_wire);
do_secprot_wren <= (wire_w_lg_do_sec_prot600w(0) AND (NOT wire_spstage_cntr_q(0)));
do_sprot_polling <= (wire_w_lg_do_sec_prot621w(0) AND wire_spstage_cntr_q(0));
do_sprot_rstat <= sprot_rstat_reg;
do_wren <= (do_write_wren OR do_secprot_wren);
do_write <= ((((wire_w_lg_read_rdid_wire11w(0) AND wire_w_lg_read_sid_wire10w(0)) AND wire_w_lg_sec_protect_wire14w(0)) AND (NOT (read_wire OR fast_read_wire))) AND write_wire);
do_write_polling <= ((wire_w_lg_w_lg_do_write65w66w(0) AND wire_wrstage_cntr_q(1)) AND wire_wrstage_cntr_w_lg_w_q_range492w493w(0));
do_write_rstat <= write_rstat_reg;
do_write_wren <= ((NOT wire_wrstage_cntr_q(1)) AND wire_wrstage_cntr_q(0));
dummy_read_buf <= maxcnt_shift_reg2;
end1_cyc_dlyncs_in_wire <= (((((((((wire_stage_cntr_w_lg_w_lg_w_q_range88w93w107w(0) AND (NOT wire_gen_cntr_q(2))) AND wire_gen_cntr_q(1)) AND (NOT wire_gen_cntr_q(0))) OR wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range88w93w107w108w109w(0)) OR (do_read AND end_read)) OR (do_fast_read AND end_fast_read)) OR wire_w_lg_w_lg_w_lg_do_write65w66w67w(0)) OR wire_w_lg_do_write63w(0)) OR ((do_read_stat AND start_poll) AND wire_w_lg_st_busy_wire102w(0)));
end1_cyc_gen_cntr_wire <= (wire_gen_cntr_w_lg_w_q_range99w100w(0) AND (NOT wire_gen_cntr_q(0)));
end1_cyc_normal_in_wire <= (((((((((wire_stage_cntr_w_lg_w_lg_w_q_range88w93w107w(0) AND (NOT wire_gen_cntr_q(2))) AND wire_gen_cntr_q(1)) AND wire_gen_cntr_q(0)) OR wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range88w93w107w108w109w(0)) OR (do_read AND end_read)) OR (do_fast_read AND end_fast_read)) OR wire_w_lg_w_lg_w_lg_do_write65w66w67w(0)) OR wire_w_lg_do_write63w(0)) OR ((do_read_stat AND start_poll) AND wire_w_lg_st_busy_wire102w(0)));
end1_cyc_reg_in_wire <= wire_mux211_dataout;
end_add_cycle <= wire_mux212_dataout;
end_add_cycle_mux_datab_wire <= (wire_addbyte_cntr_q(2) AND wire_addbyte_cntr_q(1));
end_fast_read <= end_read_reg;
end_one_cyc_pos <= end1_cyc_reg2;
end_one_cycle <= end1_cyc_reg;
end_operation <= end_op_reg;
end_opfdly <= end_opfdly_reg;
end_ophdly <= end_op_hdlyreg;
end_pgwr_data <= end_pgwrop_reg;
end_read <= end_read_reg;
end_read_byte <= end_rbyte_reg;
end_wrstage <= end_operation;
fast_read_opcode <= "00001011";
fast_read_wire <= fast_read_reg;
ill_erase_wire <= ill_erase_reg;
ill_write_wire <= ill_write_reg;
illegal_erase <= ill_erase_wire;
illegal_erase_b4out_wire <= ((do_sec_erase OR do_bulk_erase) AND write_prot_true);
illegal_write <= ill_write_wire;
illegal_write_b4out_wire <= ((do_write AND write_prot_true) OR wire_w_lg_do_write63w(0));
in_operation <= busy_wire;
load_opcode <= ((((wire_stage_cntr_w_lg_w_q_range89w90w(0) AND wire_stage_cntr_w_lg_w_q_range88w93w(0)) AND (NOT wire_gen_cntr_q(2))) AND wire_gen_cntr_w_lg_w_q_range97w98w(0)) AND wire_gen_cntr_q(0));
memadd_sdoin <= add_msb_reg;
not_busy <= busy_det_reg;
oe_wire <= '0';
page_size_wire <= "100000000";
pagewr_buf_not_empty <= ( wire_w_lg_w_pagewr_buf_not_empty_range475w477w & wire_w_lg_w_pagewr_buf_not_empty_range472w474w & wire_w_lg_w_pagewr_buf_not_empty_range469w471w & wire_w_lg_w_pagewr_buf_not_empty_range466w468w & wire_w_lg_w_pagewr_buf_not_empty_range463w465w & wire_w_lg_w_pagewr_buf_not_empty_range460w462w & wire_w_lg_w_pagewr_buf_not_empty_range457w459w & wire_w_lg_w_pagewr_buf_not_empty_range453w456w & wire_pgwr_data_cntr_q(0));
rden_wire <= rden;
rdid_load <= (end_operation AND do_read_rdid);
rdid_opcode <= "10011111";
rdid_out <= ( rdid_out_reg(7 DOWNTO 0));
reach_max_cnt <= max_cnt_reg;
read_buf <= (((((end_one_cycle AND do_write) AND wire_w_lg_do_read_stat46w(0)) AND wire_w_lg_do_wren47w(0)) AND (wire_stage_cntr_w_lg_w_q_range89w94w(0) OR wire_addbyte_cntr_w_lg_w_q_range137w142w(0))) AND wire_w_lg_buf_empty553w(0));
read_bufdly <= read_bufdly_reg;
read_data_reg_in_wire <= ( read_dout_reg(7 DOWNTO 0));
read_opcode <= (OTHERS => '0');
read_rdid_wire <= read_rdid_reg;
read_sid_wire <= '0';
read_status_wire <= read_status_reg;
read_wire <= '0';
rsid_opcode <= (OTHERS => '0');
rsid_sdoin <= '0';
rstat_opcode <= "00000101";
scein_wire <= wire_ncs_reg_w_lg_q291w(0);
sdoin_wire <= to_sdoin_wire;
sec_erase_wire <= sec_erase_reg;
sec_protect_wire <= sec_prot_reg;
secprot_opcode <= "00000001";
secprot_sdoin <= (stage3_wire AND streg_datain_reg);
serase_opcode <= "11011000";
shift_bytes_wire <= shift_bytes;
shift_opcode <= shift_op_reg;
shift_opdata <= stage2_wire;
shift_pgwr_data <= shftpgwr_data_reg;
st_busy_wire <= statreg_int(0);
stage2_wire <= stage2_reg;
stage3_wire <= stage3_reg;
stage4_wire <= stage4_reg;
start_poll <= (start_wrpoll OR start_sppoll);
start_sppoll <= start_sppoll_reg2;
start_wrpoll <= start_wrpoll_reg2;
status_out <= ( statreg_out(7 DOWNTO 0));
to_sdoin_wire <= (((((shift_opdata AND asmi_opcode_reg(7)) OR rsid_sdoin) OR memadd_sdoin) OR write_sdoin) OR secprot_sdoin);
wren_opcode <= "00000110";
wren_wire <= wren;
write_opcode <= "00000010";
write_prot_true <= write_prot_reg;
write_sdoin <= ((((do_write AND stage4_wire) AND wire_wrstage_cntr_q(1)) AND wire_wrstage_cntr_q(0)) AND pgwrbuf_dataout(7));
write_wire <= write_reg;
wire_w_addr_range308w(0) <= addr(0);
wire_w_addr_range303w <= addr(23 DOWNTO 1);
wire_w_b4addr_opcode_range205w(0) <= b4addr_opcode(0);
wire_w_b4addr_opcode_range149w <= b4addr_opcode(7 DOWNTO 1);
wire_w_berase_opcode_range209w(0) <= berase_opcode(0);
wire_w_berase_opcode_range157w <= berase_opcode(7 DOWNTO 1);
wire_w_datain_range609w(0) <= datain(0);
wire_w_datain_range604w <= datain(7 DOWNTO 1);
wire_w_dataout_wire_range345w(0) <= dataout_wire(1);
wire_w_fast_read_opcode_range217w(0) <= fast_read_opcode(0);
wire_w_fast_read_opcode_range175w <= fast_read_opcode(7 DOWNTO 1);
wire_w_pagewr_buf_not_empty_range453w(0) <= pagewr_buf_not_empty(0);
wire_w_pagewr_buf_not_empty_range457w(0) <= pagewr_buf_not_empty(1);
wire_w_pagewr_buf_not_empty_range460w(0) <= pagewr_buf_not_empty(2);
wire_w_pagewr_buf_not_empty_range463w(0) <= pagewr_buf_not_empty(3);
wire_w_pagewr_buf_not_empty_range466w(0) <= pagewr_buf_not_empty(4);
wire_w_pagewr_buf_not_empty_range469w(0) <= pagewr_buf_not_empty(5);
wire_w_pagewr_buf_not_empty_range472w(0) <= pagewr_buf_not_empty(6);
wire_w_pagewr_buf_not_empty_range475w(0) <= pagewr_buf_not_empty(7);
wire_w_pagewr_buf_not_empty_range61w(0) <= pagewr_buf_not_empty(8);
wire_w_rdid_opcode_range223w(0) <= rdid_opcode(0);
wire_w_rdid_opcode_range186w <= rdid_opcode(7 DOWNTO 1);
wire_w_read_opcode_range219w(0) <= read_opcode(0);
wire_w_read_opcode_range178w <= read_opcode(7 DOWNTO 1);
wire_w_rsid_opcode_range225w(0) <= rsid_opcode(0);
wire_w_rsid_opcode_range189w <= rsid_opcode(7 DOWNTO 1);
wire_w_rstat_opcode_range213w(0) <= rstat_opcode(0);
wire_w_rstat_opcode_range167w <= rstat_opcode(7 DOWNTO 1);
wire_w_secprot_opcode_range221w(0) <= secprot_opcode(0);
wire_w_secprot_opcode_range181w <= secprot_opcode(7 DOWNTO 1);
wire_w_serase_opcode_range211w(0) <= serase_opcode(0);
wire_w_serase_opcode_range162w <= serase_opcode(7 DOWNTO 1);
wire_w_wren_opcode_range207w(0) <= wren_opcode(0);
wire_w_wren_opcode_range154w <= wren_opcode(7 DOWNTO 1);
wire_w_write_opcode_range215w(0) <= write_opcode(0);
wire_w_write_opcode_range170w <= write_opcode(7 DOWNTO 1);
wire_addbyte_cntr_w_lg_w_q_range137w142w(0) <= wire_addbyte_cntr_w_q_range137w(0) AND wire_addbyte_cntr_w_lg_w_q_range140w141w(0);
wire_addbyte_cntr_w_lg_w_q_range140w141w(0) <= NOT wire_addbyte_cntr_w_q_range140w(0);
wire_addbyte_cntr_clk_en <= wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w92w135w136w(0);
wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w92w135w136w(0) <= wire_stage_cntr_w_lg_w_lg_w_q_range89w92w135w(0) AND wire_w134w(0);
wire_addbyte_cntr_clock <= wire_w_lg_clkin_wire42w(0);
wire_addbyte_cntr_w_q_range140w(0) <= wire_addbyte_cntr_q(0);
wire_addbyte_cntr_w_q_range137w(0) <= wire_addbyte_cntr_q(1);
addbyte_cntr : a_graycounter
GENERIC MAP (
WIDTH => 3
)
PORT MAP (
aclr => end_operation,
clk_en => wire_addbyte_cntr_clk_en,
clock => wire_addbyte_cntr_clock,
q => wire_addbyte_cntr_q
);
wire_gen_cntr_w_lg_w_q_range99w100w(0) <= wire_gen_cntr_w_q_range99w(0) AND wire_gen_cntr_w_lg_w_q_range97w98w(0);
wire_gen_cntr_w_lg_w_q_range97w98w(0) <= NOT wire_gen_cntr_w_q_range97w(0);
wire_gen_cntr_clk_en <= wire_w_lg_in_operation44w(0);
wire_w_lg_in_operation44w(0) <= in_operation AND wire_w_lg_end_ophdly43w(0);
wire_gen_cntr_w_q_range97w(0) <= wire_gen_cntr_q(1);
wire_gen_cntr_w_q_range99w(0) <= wire_gen_cntr_q(2);
gen_cntr : a_graycounter
GENERIC MAP (
WIDTH => 3
)
PORT MAP (
aclr => end_one_cycle,
clk_en => wire_gen_cntr_clk_en,
clock => clkin_wire,
q => wire_gen_cntr_q
);
wire_spstage_cntr_w_lg_w_q_range598w599w(0) <= NOT wire_spstage_cntr_w_q_range598w(0);
wire_spstage_cntr_clk_en <= wire_w_lg_do_sec_prot595w(0);
wire_w_lg_do_sec_prot595w(0) <= do_sec_prot AND end_operation;
wire_spstage_cntr_clock <= wire_w_lg_clkin_wire42w(0);
wire_spstage_cntr_w_q_range596w(0) <= wire_spstage_cntr_q(0);
wire_spstage_cntr_w_q_range598w(0) <= wire_spstage_cntr_q(1);
spstage_cntr : a_graycounter
GENERIC MAP (
WIDTH => 2
)
PORT MAP (
aclr => clr_secprot_wire,
clk_en => wire_spstage_cntr_clk_en,
clock => wire_spstage_cntr_clock,
q => wire_spstage_cntr_q
);
wire_stage_cntr_w_lg_w247w248w(0) <= wire_stage_cntr_w247w(0) AND end_one_cycle;
wire_stage_cntr_w247w(0) <= wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range89w92w244w245w246w(0) AND end_add_cycle;
wire_stage_cntr_w252w(0) <= wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range89w92w249w250w251w(0) AND end_one_cycle;
wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range89w92w244w245w246w(0) <= wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w92w244w245w(0) AND wire_w_lg_do_read_stat46w(0);
wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range89w92w249w250w251w(0) <= wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w92w249w250w(0) AND wire_w_lg_do_read_stat46w(0);
wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range89w90w91w257w258w(0) <= wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w90w91w257w(0) AND end_one_cycle;
wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w94w322w323w(0) <= wire_stage_cntr_w_lg_w_lg_w_q_range89w94w322w(0) AND end_one_cyc_pos;
wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w92w269w270w(0) <= wire_stage_cntr_w_lg_w_lg_w_q_range89w92w269w(0) AND end_one_cycle;
wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w92w244w245w(0) <= wire_stage_cntr_w_lg_w_lg_w_q_range89w92w244w(0) AND wire_w_lg_do_wren47w(0);
wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w92w249w250w(0) <= wire_stage_cntr_w_lg_w_lg_w_q_range89w92w249w(0) AND wire_w_lg_do_wren47w(0);
wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w90w91w257w(0) <= wire_stage_cntr_w_lg_w_lg_w_q_range89w90w91w(0) AND wire_w_lg_do_wren256w(0);
wire_stage_cntr_w_lg_w_lg_w_q_range89w94w322w(0) <= wire_stage_cntr_w_lg_w_q_range89w94w(0) AND end_add_cycle;
wire_stage_cntr_w_lg_w_lg_w_q_range89w92w269w(0) <= wire_stage_cntr_w_lg_w_q_range89w92w(0) AND do_read_stat;
wire_stage_cntr_w_lg_w_lg_w_q_range89w92w244w(0) <= wire_stage_cntr_w_lg_w_q_range89w92w(0) AND do_sec_erase;
wire_stage_cntr_w_lg_w_lg_w_q_range89w92w249w(0) <= wire_stage_cntr_w_lg_w_q_range89w92w(0) AND do_sec_prot;
wire_stage_cntr_w_lg_w_lg_w_q_range89w92w135w(0) <= wire_stage_cntr_w_lg_w_q_range89w92w(0) AND end_one_cyc_pos;
wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range88w93w107w108w109w(0) <= wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range88w93w107w108w(0) AND end1_cyc_gen_cntr_wire;
wire_stage_cntr_w_lg_w_lg_w_q_range88w93w107w(0) <= wire_stage_cntr_w_lg_w_q_range88w93w(0) AND wire_stage_cntr_w_lg_w_q_range89w90w(0);
wire_stage_cntr_w_lg_w_lg_w_q_range89w90w91w(0) <= wire_stage_cntr_w_lg_w_q_range89w90w(0) AND wire_stage_cntr_w_q_range88w(0);
wire_stage_cntr_w_lg_w_q_range89w94w(0) <= wire_stage_cntr_w_q_range89w(0) AND wire_stage_cntr_w_lg_w_q_range88w93w(0);
wire_stage_cntr_w_lg_w_q_range89w92w(0) <= wire_stage_cntr_w_q_range89w(0) AND wire_stage_cntr_w_q_range88w(0);
wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range88w93w107w108w(0) <= NOT wire_stage_cntr_w_lg_w_lg_w_q_range88w93w107w(0);
wire_stage_cntr_w_lg_w_q_range88w93w(0) <= NOT wire_stage_cntr_w_q_range88w(0);
wire_stage_cntr_w_lg_w_q_range89w90w(0) <= NOT wire_stage_cntr_w_q_range89w(0);
wire_stage_cntr_clk_en <= wire_w_lg_w_lg_w_lg_w_lg_w_lg_w82w83w84w85w86w87w(0);
wire_w_lg_w_lg_w_lg_w_lg_w_lg_w82w83w84w85w86w87w(0) <= (((((((((in_operation AND end_one_cycle) AND (NOT (stage3_wire AND wire_w_lg_end_add_cycle75w(0)))) AND (NOT (stage4_wire AND wire_w_lg_end_read72w(0)))) AND (NOT (stage4_wire AND wire_w_lg_end_fast_read69w(0)))) AND (NOT wire_w_lg_w_lg_w_lg_do_write65w66w67w(0))) AND (NOT wire_w_lg_do_write63w(0))) AND (NOT (stage3_wire AND st_busy_wire))) AND (NOT (wire_w_lg_do_write56w(0) AND wire_w_lg_end_pgwr_data55w(0)))) AND (NOT (stage2_wire AND do_wren))) AND (NOT ((((stage3_wire AND do_sec_erase) AND wire_w_lg_do_wren47w(0)) AND wire_w_lg_do_read_stat46w(0)) AND wire_w_lg_do_read_rdid45w(0)));
wire_stage_cntr_w_q_range88w(0) <= wire_stage_cntr_q(0);
wire_stage_cntr_w_q_range89w(0) <= wire_stage_cntr_q(1);
stage_cntr : a_graycounter
GENERIC MAP (
WIDTH => 2
)
PORT MAP (
aclr => end_ophdly,
clk_en => wire_stage_cntr_clk_en,
clock => clkin_wire,
q => wire_stage_cntr_q
);
wire_wrstage_cntr_w_lg_w_q_range494w495w(0) <= wire_wrstage_cntr_w_q_range494w(0) AND wire_wrstage_cntr_w_lg_w_q_range492w493w(0);
wire_wrstage_cntr_w_lg_w_q_range492w493w(0) <= NOT wire_wrstage_cntr_w_q_range492w(0);
wire_wrstage_cntr_clk_en <= wire_w_lg_w490w491w(0);
wire_w_lg_w490w491w(0) <= wire_w490w(0) AND wire_w_lg_st_busy_wire102w(0);
wire_wrstage_cntr_clock <= wire_w_lg_clkin_wire42w(0);
wire_wrstage_cntr_w_q_range492w(0) <= wire_wrstage_cntr_q(0);
wire_wrstage_cntr_w_q_range494w(0) <= wire_wrstage_cntr_q(1);
wrstage_cntr : a_graycounter
GENERIC MAP (
WIDTH => 2
)
PORT MAP (
aclr => clr_write_wire,
clk_en => wire_wrstage_cntr_clk_en,
clock => wire_wrstage_cntr_clock,
q => wire_wrstage_cntr_q
);
cycloneii_asmiblock3 : cycloneii_asmiblock
PORT MAP (
data0out => wire_cycloneii_asmiblock3_data0out,
dclkin => clkin_wire,
oe => oe_wire,
scein => scein_wire,
sdoin => sdoin_wire
);
PROCESS (clkin_wire, clr_addmsb_reg)
BEGIN
IF (clr_addmsb_reg = '1') THEN add_msb_reg <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_add_msb_reg_ena = '1') THEN add_msb_reg <= addr_reg(23);
END IF;
END IF;
END PROCESS;
wire_add_msb_reg_ena <= (((wire_w_lg_w_lg_w_lg_do_read330w331w332w(0) AND (NOT (wire_w_lg_do_write65w(0) AND wire_w_lg_do_memadd327w(0)))) AND wire_stage_cntr_q(1)) AND wire_stage_cntr_q(0));
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(0) = '1') THEN addr_reg(0) <= wire_addr_reg_d(0);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(1) = '1') THEN addr_reg(1) <= wire_addr_reg_d(1);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(2) = '1') THEN addr_reg(2) <= wire_addr_reg_d(2);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(3) = '1') THEN addr_reg(3) <= wire_addr_reg_d(3);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(4) = '1') THEN addr_reg(4) <= wire_addr_reg_d(4);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(5) = '1') THEN addr_reg(5) <= wire_addr_reg_d(5);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(6) = '1') THEN addr_reg(6) <= wire_addr_reg_d(6);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(7) = '1') THEN addr_reg(7) <= wire_addr_reg_d(7);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(8) = '1') THEN addr_reg(8) <= wire_addr_reg_d(8);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(9) = '1') THEN addr_reg(9) <= wire_addr_reg_d(9);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(10) = '1') THEN addr_reg(10) <= wire_addr_reg_d(10);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(11) = '1') THEN addr_reg(11) <= wire_addr_reg_d(11);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(12) = '1') THEN addr_reg(12) <= wire_addr_reg_d(12);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(13) = '1') THEN addr_reg(13) <= wire_addr_reg_d(13);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(14) = '1') THEN addr_reg(14) <= wire_addr_reg_d(14);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(15) = '1') THEN addr_reg(15) <= wire_addr_reg_d(15);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(16) = '1') THEN addr_reg(16) <= wire_addr_reg_d(16);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(17) = '1') THEN addr_reg(17) <= wire_addr_reg_d(17);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(18) = '1') THEN addr_reg(18) <= wire_addr_reg_d(18);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(19) = '1') THEN addr_reg(19) <= wire_addr_reg_d(19);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(20) = '1') THEN addr_reg(20) <= wire_addr_reg_d(20);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(21) = '1') THEN addr_reg(21) <= wire_addr_reg_d(21);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(22) = '1') THEN addr_reg(22) <= wire_addr_reg_d(22);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_addr_reg_ena(23) = '1') THEN addr_reg(23) <= wire_addr_reg_d(23);
END IF;
END IF;
END PROCESS;
wire_addr_reg_d <= ( wire_w_lg_w_lg_not_busy304w305w & wire_w_lg_not_busy309w);
loop32 : FOR i IN 0 TO 23 GENERATE
wire_addr_reg_ena(i) <= wire_w_lg_w_lg_w_lg_rden_wire315w316w317w(0);
END GENERATE loop32;
wire_addr_reg_w_lg_w_lg_w535w536w537w(0) <= wire_addr_reg_w_lg_w535w536w(0) AND bp0_wire;
wire_addr_reg_w_lg_w535w536w(0) <= wire_addr_reg_w535w(0) AND wire_w_lg_bp1_wire511w(0);
wire_addr_reg_w527w(0) <= wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range512w518w524w525w526w(0) AND bp0_wire;
wire_addr_reg_w531w(0) <= wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range512w518w524w529w530w(0) AND bp1_wire;
wire_addr_reg_w535w(0) <= wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range512w518w524w529w534w(0) AND wire_w_lg_bp2_wire522w(0);
wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range512w518w524w525w526w(0) <= wire_addr_reg_w_lg_w_lg_w_lg_w_q_range512w518w524w525w(0) AND bp1_wire;
wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range512w518w524w529w530w(0) <= wire_addr_reg_w_lg_w_lg_w_lg_w_q_range512w518w524w529w(0) AND wire_w_lg_bp2_wire522w(0);
wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range512w518w524w529w534w(0) <= wire_addr_reg_w_lg_w_lg_w_lg_w_q_range512w518w524w529w(0) AND wire_addr_reg_w_q_range533w(0);
wire_addr_reg_w_lg_w_lg_w_lg_w_q_range512w513w514w515w(0) <= wire_addr_reg_w_lg_w_lg_w_q_range512w513w514w(0) AND bp0_wire;
wire_addr_reg_w_lg_w_lg_w_lg_w_q_range512w518w524w525w(0) <= wire_addr_reg_w_lg_w_lg_w_q_range512w518w524w(0) AND wire_w_lg_bp2_wire522w(0);
wire_addr_reg_w_lg_w_lg_w_lg_w_q_range512w518w524w529w(0) <= wire_addr_reg_w_lg_w_lg_w_q_range512w518w524w(0) AND wire_addr_reg_w_q_range528w(0);
wire_addr_reg_w_lg_w_lg_w_q_range512w513w514w(0) <= wire_addr_reg_w_lg_w_q_range512w513w(0) AND wire_w_lg_bp1_wire511w(0);
wire_addr_reg_w_lg_w_lg_w_q_range512w518w519w(0) <= wire_addr_reg_w_lg_w_q_range512w518w(0) AND bp2_wire;
wire_addr_reg_w_lg_w_lg_w_q_range512w518w524w(0) <= wire_addr_reg_w_lg_w_q_range512w518w(0) AND wire_addr_reg_w_q_range523w(0);
wire_addr_reg_w_lg_w_q_range512w513w(0) <= wire_addr_reg_w_q_range512w(0) AND bp2_wire;
wire_addr_reg_w_lg_w_q_range512w518w(0) <= wire_addr_reg_w_q_range512w(0) AND wire_addr_reg_w_q_range517w(0);
wire_addr_reg_w_q_range533w(0) <= addr_reg(16);
wire_addr_reg_w_q_range528w(0) <= addr_reg(17);
wire_addr_reg_w_q_range523w(0) <= addr_reg(18);
wire_addr_reg_w_q_range517w(0) <= addr_reg(19);
wire_addr_reg_w_q_range512w(0) <= addr_reg(20);
wire_addr_reg_w_q_range301w <= addr_reg(22 DOWNTO 0);
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_asmi_opcode_reg_ena(0) = '1') THEN asmi_opcode_reg(0) <= wire_asmi_opcode_reg_d(0);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_asmi_opcode_reg_ena(1) = '1') THEN asmi_opcode_reg(1) <= wire_asmi_opcode_reg_d(1);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_asmi_opcode_reg_ena(2) = '1') THEN asmi_opcode_reg(2) <= wire_asmi_opcode_reg_d(2);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_asmi_opcode_reg_ena(3) = '1') THEN asmi_opcode_reg(3) <= wire_asmi_opcode_reg_d(3);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_asmi_opcode_reg_ena(4) = '1') THEN asmi_opcode_reg(4) <= wire_asmi_opcode_reg_d(4);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_asmi_opcode_reg_ena(5) = '1') THEN asmi_opcode_reg(5) <= wire_asmi_opcode_reg_d(5);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_asmi_opcode_reg_ena(6) = '1') THEN asmi_opcode_reg(6) <= wire_asmi_opcode_reg_d(6);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_asmi_opcode_reg_ena(7) = '1') THEN asmi_opcode_reg(7) <= wire_asmi_opcode_reg_d(7);
END IF;
END IF;
END PROCESS;
wire_asmi_opcode_reg_d <= ( wire_w_lg_w_lg_w200w201w202w & wire_w_lg_w235w236w);
loop33 : FOR i IN 0 TO 7 GENERATE
wire_asmi_opcode_reg_ena(i) <= wire_w_lg_load_opcode238w(0);
END GENERATE loop33;
wire_asmi_opcode_reg_w_q_range147w <= asmi_opcode_reg(6 DOWNTO 0);
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN buf_empty_reg <= wire_cmpr6_aeb;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_write_wire)
BEGIN
IF (clr_write_wire = '1') THEN bulk_erase_reg <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_bulk_erase_reg_ena = '1') THEN bulk_erase_reg <= bulk_erase;
END IF;
END IF;
END PROCESS;
wire_bulk_erase_reg_ena <= (wire_w_lg_busy_wire2w(0) AND wren_wire);
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (power_up_reg = '1') THEN busy_delay_reg <= busy_wire;
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN busy_det_reg <= wire_w_lg_busy_wire2w(0);
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_addmsb_reg <= ((wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w94w322w323w(0) OR wire_w_lg_w_lg_w_lg_do_read274w275w321w(0)) OR wire_w_lg_w_lg_w_lg_do_sec_erase318w319w320w(0));
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN clr_endrbyte_reg <= ((((wire_w_lg_do_read330w(0) AND (NOT wire_gen_cntr_q(2))) AND wire_gen_cntr_q(1)) AND wire_gen_cntr_q(0)) OR clr_read_wire);
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_rdid_reg <= end_operation;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_rdid_reg2 <= clr_rdid_reg;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_read_reg <= ((end_operation OR do_read_sid) OR do_sec_prot);
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_read_reg2 <= clr_read_reg;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_rstat_reg <= ((end_operation OR do_read_sid) OR do_read);
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_rstat_reg2 <= clr_rstat_reg;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_secprot_reg <= (((wire_spstage_cntr_q(1) AND wire_spstage_cntr_q(0)) AND end_operation) OR do_read_sid);
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_secprot_reg2 <= clr_secprot_reg;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_write_reg <= ((((((wire_w_lg_w_lg_w586w587w588w(0) OR wire_w_lg_do_write63w(0)) OR wire_w584w(0)) OR do_read_sid) OR do_sec_prot) OR do_read) OR do_fast_read);
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_write_reg2 <= clr_write_reg;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN cnt_bfend_reg <= cnt_bfend_wire_in;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN do_wrmemadd_reg <= (wire_wrstage_cntr_q(1) AND wire_wrstage_cntr_q(0));
END IF;
END PROCESS;
PROCESS (clkin_wire, end_operation)
BEGIN
IF (end_operation = '1') THEN dvalid_reg <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_dvalid_reg_ena = '1') THEN dvalid_reg <= (end_read_byte AND end_one_cyc_pos);
END IF;
END IF;
END PROCESS;
wire_dvalid_reg_ena <= wire_w_lg_do_read330w(0);
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN dvalid_reg2 <= dvalid_reg;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN end1_cyc_reg <= end1_cyc_reg_in_wire;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN end1_cyc_reg2 <= end_one_cycle;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN end_op_hdlyreg <= end_operation;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN end_op_reg <= ((((((((((wire_stage_cntr_w_lg_w_q_range89w94w(0) AND ((wire_w_lg_w_lg_w_lg_w_lg_do_read274w275w276w277w(0) OR (do_read AND end_read)) OR (do_fast_read AND end_fast_read))) OR (wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range89w92w269w270w(0) AND wire_w_lg_do_polling268w(0))) OR ((((((do_read_rdid AND end_one_cycle) AND wire_stage_cntr_q(1)) AND wire_stage_cntr_q(0)) AND wire_addbyte_cntr_q(2)) AND wire_addbyte_cntr_q(1)) AND wire_addbyte_cntr_q(0))) OR (wire_w_lg_w_lg_start_poll259w260w(0) AND wire_w_lg_st_busy_wire102w(0))) OR wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range89w90w91w257w258w(0)) OR wire_w_lg_w_lg_w_lg_do_write65w66w67w(0)) OR wire_w_lg_w_lg_do_write56w253w(0)) OR wire_w_lg_do_write63w(0)) OR wire_stage_cntr_w252w(0)) OR wire_stage_cntr_w_lg_w247w248w(0));
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN end_opfdly_reg <= end_operation;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_write_wire)
BEGIN
IF (clr_write_wire = '1') THEN end_pgwrop_reg <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_end_pgwrop_reg_ena = '1') THEN end_pgwrop_reg <= buf_empty;
END IF;
END IF;
END PROCESS;
wire_end_pgwrop_reg_ena <= ((cnt_bfend_reg AND do_write) AND shift_pgwr_data);
PROCESS (clkin_wire, clr_endrbyte_reg)
BEGIN
IF (clr_endrbyte_reg = '1') THEN end_rbyte_reg <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_end_rbyte_reg_ena = '1') THEN end_rbyte_reg <= wire_w_lg_w_lg_w_lg_do_read330w374w375w(0);
END IF;
END IF;
END PROCESS;
wire_end_rbyte_reg_ena <= (wire_gen_cntr_w_lg_w_q_range99w100w(0) AND wire_gen_cntr_q(0));
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN end_read_reg <= (((wire_w_lg_rden_wire389w(0) AND wire_w_lg_do_read330w(0)) AND data_valid_wire) AND end_read_byte);
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_read_wire)
BEGIN
IF (clr_read_wire = '1') THEN fast_read_reg <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_fast_read_reg_ena = '1') THEN fast_read_reg <= fast_read;
END IF;
END IF;
END PROCESS;
wire_fast_read_reg_ena <= (wire_w_lg_busy_wire2w(0) AND rden_wire);
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN ill_erase_reg <= (illegal_erase_dly_reg OR illegal_erase_b4out_wire);
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN ill_write_reg <= (illegal_write_dly_reg OR illegal_write_b4out_wire);
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (power_up_reg = '1') THEN illegal_erase_dly_reg <= illegal_erase_b4out_wire;
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (power_up_reg = '1') THEN illegal_write_dly_reg <= illegal_write_b4out_wire;
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN max_cnt_reg <= wire_cmpr5_aeb;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN maxcnt_shift_reg <= (wire_w_lg_w_lg_reach_max_cnt484w485w(0) AND wire_w_lg_do_write408w(0));
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN maxcnt_shift_reg2 <= maxcnt_shift_reg;
END IF;
END PROCESS;
PROCESS (clkin_wire, end_ophdly)
BEGIN
IF (end_ophdly = '1') THEN ncs_reg <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_ncs_reg_ena = '1') THEN ncs_reg <= '1';
END IF;
END IF;
END PROCESS;
wire_ncs_reg_ena <= (wire_stage_cntr_w_lg_w_lg_w_q_range89w90w91w(0) AND end_one_cyc_pos);
wire_ncs_reg_w_lg_q291w(0) <= NOT ncs_reg;
PROCESS (clkin_wire, clr_write_wire)
BEGIN
IF (clr_write_wire = '1') THEN pgwrbuf_dataout(0) <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_pgwrbuf_dataout_ena(0) = '1') THEN pgwrbuf_dataout(0) <= wire_pgwrbuf_dataout_d(0);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_write_wire)
BEGIN
IF (clr_write_wire = '1') THEN pgwrbuf_dataout(1) <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_pgwrbuf_dataout_ena(1) = '1') THEN pgwrbuf_dataout(1) <= wire_pgwrbuf_dataout_d(1);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_write_wire)
BEGIN
IF (clr_write_wire = '1') THEN pgwrbuf_dataout(2) <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_pgwrbuf_dataout_ena(2) = '1') THEN pgwrbuf_dataout(2) <= wire_pgwrbuf_dataout_d(2);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_write_wire)
BEGIN
IF (clr_write_wire = '1') THEN pgwrbuf_dataout(3) <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_pgwrbuf_dataout_ena(3) = '1') THEN pgwrbuf_dataout(3) <= wire_pgwrbuf_dataout_d(3);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_write_wire)
BEGIN
IF (clr_write_wire = '1') THEN pgwrbuf_dataout(4) <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_pgwrbuf_dataout_ena(4) = '1') THEN pgwrbuf_dataout(4) <= wire_pgwrbuf_dataout_d(4);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_write_wire)
BEGIN
IF (clr_write_wire = '1') THEN pgwrbuf_dataout(5) <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_pgwrbuf_dataout_ena(5) = '1') THEN pgwrbuf_dataout(5) <= wire_pgwrbuf_dataout_d(5);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_write_wire)
BEGIN
IF (clr_write_wire = '1') THEN pgwrbuf_dataout(6) <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_pgwrbuf_dataout_ena(6) = '1') THEN pgwrbuf_dataout(6) <= wire_pgwrbuf_dataout_d(6);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_write_wire)
BEGIN
IF (clr_write_wire = '1') THEN pgwrbuf_dataout(7) <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_pgwrbuf_dataout_ena(7) = '1') THEN pgwrbuf_dataout(7) <= wire_pgwrbuf_dataout_d(7);
END IF;
END IF;
END PROCESS;
wire_pgwrbuf_dataout_d <= ( wire_w_lg_w_lg_read_bufdly442w443w & wire_w_lg_read_bufdly447w);
loop34 : FOR i IN 0 TO 7 GENERATE
wire_pgwrbuf_dataout_ena(i) <= wire_w_lg_read_bufdly437w(0);
END GENERATE loop34;
wire_pgwrbuf_dataout_w_q_range438w <= pgwrbuf_dataout(6 DOWNTO 0);
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN power_up_reg <= (busy_wire OR busy_delay_reg);
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (rdid_load = '1') THEN rdid_out_reg <= ( read_dout_reg(7 DOWNTO 0));
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN read_bufdly_reg <= read_buf;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_read_data_reg_ena(0) = '1') THEN read_data_reg(0) <= wire_read_data_reg_d(0);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_read_data_reg_ena(1) = '1') THEN read_data_reg(1) <= wire_read_data_reg_d(1);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_read_data_reg_ena(2) = '1') THEN read_data_reg(2) <= wire_read_data_reg_d(2);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_read_data_reg_ena(3) = '1') THEN read_data_reg(3) <= wire_read_data_reg_d(3);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_read_data_reg_ena(4) = '1') THEN read_data_reg(4) <= wire_read_data_reg_d(4);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_read_data_reg_ena(5) = '1') THEN read_data_reg(5) <= wire_read_data_reg_d(5);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_read_data_reg_ena(6) = '1') THEN read_data_reg(6) <= wire_read_data_reg_d(6);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_read_data_reg_ena(7) = '1') THEN read_data_reg(7) <= wire_read_data_reg_d(7);
END IF;
END IF;
END PROCESS;
wire_read_data_reg_d <= ( read_data_reg_in_wire(7 DOWNTO 0));
loop35 : FOR i IN 0 TO 7 GENERATE
wire_read_data_reg_ena(i) <= wire_w377w(0);
END GENERATE loop35;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_read_dout_reg_ena(0) = '1') THEN read_dout_reg(0) <= wire_read_dout_reg_d(0);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_read_dout_reg_ena(1) = '1') THEN read_dout_reg(1) <= wire_read_dout_reg_d(1);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_read_dout_reg_ena(2) = '1') THEN read_dout_reg(2) <= wire_read_dout_reg_d(2);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_read_dout_reg_ena(3) = '1') THEN read_dout_reg(3) <= wire_read_dout_reg_d(3);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_read_dout_reg_ena(4) = '1') THEN read_dout_reg(4) <= wire_read_dout_reg_d(4);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_read_dout_reg_ena(5) = '1') THEN read_dout_reg(5) <= wire_read_dout_reg_d(5);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_read_dout_reg_ena(6) = '1') THEN read_dout_reg(6) <= wire_read_dout_reg_d(6);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_read_dout_reg_ena(7) = '1') THEN read_dout_reg(7) <= wire_read_dout_reg_d(7);
END IF;
END IF;
END PROCESS;
wire_read_dout_reg_d <= ( read_dout_reg(6 DOWNTO 0) & wire_w_lg_data0out_wire346w);
loop36 : FOR i IN 0 TO 7 GENERATE
wire_read_dout_reg_ena(i) <= wire_w_lg_w_lg_stage4_wire343w344w(0);
END GENERATE loop36;
PROCESS (clkin_wire, clr_rdid_wire)
BEGIN
IF (clr_rdid_wire = '1') THEN read_rdid_reg <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (busy_wire = '0') THEN read_rdid_reg <= read_rdid;
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_rstat_wire)
BEGIN
IF (clr_rstat_wire = '1') THEN read_status_reg <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (busy_wire = '0') THEN read_status_reg <= read_status;
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_write_wire)
BEGIN
IF (clr_write_wire = '1') THEN sec_erase_reg <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_sec_erase_reg_ena = '1') THEN sec_erase_reg <= sector_erase;
END IF;
END IF;
END PROCESS;
wire_sec_erase_reg_ena <= (wire_w_lg_busy_wire2w(0) AND wren_wire);
PROCESS (clkin_wire, clr_secprot_wire)
BEGIN
IF (clr_secprot_wire = '1') THEN sec_prot_reg <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_sec_prot_reg_ena = '1') THEN sec_prot_reg <= sector_protect;
END IF;
END IF;
END PROCESS;
wire_sec_prot_reg_ena <= (wire_w_lg_busy_wire2w(0) AND wren_wire);
PROCESS (clkin_wire, end_ophdly)
BEGIN
IF (end_ophdly = '1') THEN shftpgwr_data_reg <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN shftpgwr_data_reg <= ((wire_stage_cntr_w_lg_w_q_range89w94w(0) AND wire_wrstage_cntr_q(1)) AND wire_wrstage_cntr_q(0));
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN shift_op_reg <= wire_stage_cntr_w_lg_w_lg_w_q_range89w90w91w(0);
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_secprot_wire)
BEGIN
IF (clr_secprot_wire = '1') THEN sprot_rstat_reg <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN sprot_rstat_reg <= (wire_w_lg_do_sec_prot621w(0) AND wire_spstage_cntr_q(0));
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN stage2_reg <= wire_stage_cntr_w_lg_w_lg_w_q_range89w90w91w(0);
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '1' AND clkin_wire'event) THEN stage3_dly_reg <= wire_stage_cntr_w_lg_w_q_range89w92w(0);
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN stage3_reg <= wire_stage_cntr_w_lg_w_q_range89w92w(0);
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN stage4_reg <= wire_stage_cntr_w_lg_w_q_range89w94w(0);
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_secprot_wire)
BEGIN
IF (clr_secprot_wire = '1') THEN start_sppoll_reg <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_start_sppoll_reg_ena = '1') THEN start_sppoll_reg <= wire_stage_cntr_w_lg_w_q_range89w92w(0);
END IF;
END IF;
END PROCESS;
wire_start_sppoll_reg_ena <= ((do_sprot_rstat AND do_polling) AND end_one_cycle);
PROCESS (clkin_wire, clr_secprot_wire)
BEGIN
IF (clr_secprot_wire = '1') THEN start_sppoll_reg2 <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN start_sppoll_reg2 <= start_sppoll_reg;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_write_wire)
BEGIN
IF (clr_write_wire = '1') THEN start_wrpoll_reg <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_start_wrpoll_reg_ena = '1') THEN start_wrpoll_reg <= wire_stage_cntr_w_lg_w_q_range89w92w(0);
END IF;
END IF;
END PROCESS;
wire_start_wrpoll_reg_ena <= ((do_write_rstat AND do_polling) AND end_one_cycle);
PROCESS (clkin_wire, clr_write_wire)
BEGIN
IF (clr_write_wire = '1') THEN start_wrpoll_reg2 <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN start_wrpoll_reg2 <= start_wrpoll_reg;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_rstat_wire)
BEGIN
IF (clr_rstat_wire = '1') THEN statreg_int(0) <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_statreg_int_ena(0) = '1') THEN statreg_int(0) <= wire_statreg_int_d(0);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_rstat_wire)
BEGIN
IF (clr_rstat_wire = '1') THEN statreg_int(1) <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_statreg_int_ena(1) = '1') THEN statreg_int(1) <= wire_statreg_int_d(1);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_rstat_wire)
BEGIN
IF (clr_rstat_wire = '1') THEN statreg_int(2) <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_statreg_int_ena(2) = '1') THEN statreg_int(2) <= wire_statreg_int_d(2);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_rstat_wire)
BEGIN
IF (clr_rstat_wire = '1') THEN statreg_int(3) <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_statreg_int_ena(3) = '1') THEN statreg_int(3) <= wire_statreg_int_d(3);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_rstat_wire)
BEGIN
IF (clr_rstat_wire = '1') THEN statreg_int(4) <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_statreg_int_ena(4) = '1') THEN statreg_int(4) <= wire_statreg_int_d(4);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_rstat_wire)
BEGIN
IF (clr_rstat_wire = '1') THEN statreg_int(5) <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_statreg_int_ena(5) = '1') THEN statreg_int(5) <= wire_statreg_int_d(5);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_rstat_wire)
BEGIN
IF (clr_rstat_wire = '1') THEN statreg_int(6) <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_statreg_int_ena(6) = '1') THEN statreg_int(6) <= wire_statreg_int_d(6);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_rstat_wire)
BEGIN
IF (clr_rstat_wire = '1') THEN statreg_int(7) <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_statreg_int_ena(7) = '1') THEN statreg_int(7) <= wire_statreg_int_d(7);
END IF;
END IF;
END PROCESS;
wire_statreg_int_d <= ( read_dout_reg(7 DOWNTO 0));
loop37 : FOR i IN 0 TO 7 GENERATE
wire_statreg_int_ena(i) <= wire_w_lg_w_lg_end_operation422w423w(0);
END GENERATE loop37;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_statreg_out_ena(0) = '1') THEN statreg_out(0) <= wire_statreg_out_d(0);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_statreg_out_ena(1) = '1') THEN statreg_out(1) <= wire_statreg_out_d(1);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_statreg_out_ena(2) = '1') THEN statreg_out(2) <= wire_statreg_out_d(2);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_statreg_out_ena(3) = '1') THEN statreg_out(3) <= wire_statreg_out_d(3);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_statreg_out_ena(4) = '1') THEN statreg_out(4) <= wire_statreg_out_d(4);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_statreg_out_ena(5) = '1') THEN statreg_out(5) <= wire_statreg_out_d(5);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_statreg_out_ena(6) = '1') THEN statreg_out(6) <= wire_statreg_out_d(6);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire)
BEGIN
IF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_statreg_out_ena(7) = '1') THEN statreg_out(7) <= wire_statreg_out_d(7);
END IF;
END IF;
END PROCESS;
wire_statreg_out_d <= ( read_dout_reg(7 DOWNTO 0));
loop38 : FOR i IN 0 TO 7 GENERATE
wire_statreg_out_ena(i) <= wire_w_lg_w413w414w(0);
END GENERATE loop38;
PROCESS (clkin_wire, end_opfdly)
BEGIN
IF (end_opfdly = '1') THEN streg_datain_reg <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_streg_datain_reg_ena = '1') THEN streg_datain_reg <= wrstat_dreg(7);
END IF;
END IF;
END PROCESS;
wire_streg_datain_reg_ena <= (wire_w_lg_do_sec_prot600w(0) AND wire_spstage_cntr_q(0));
PROCESS (clkin_wire, clr_write_wire)
BEGIN
IF (clr_write_wire = '1') THEN write_prot_reg <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_write_prot_reg_ena = '1') THEN write_prot_reg <= ((wire_w_lg_do_write65w(0) AND (((((wire_addr_reg_w_lg_w_lg_w535w536w537w(0) OR (wire_addr_reg_w531w(0) AND wire_w_lg_bp0_wire516w(0))) OR wire_addr_reg_w527w(0)) OR ((wire_addr_reg_w_lg_w_lg_w_q_range512w518w519w(0) AND wire_w_lg_bp1_wire511w(0)) AND wire_w_lg_bp0_wire516w(0))) OR wire_addr_reg_w_lg_w_lg_w_lg_w_q_range512w513w514w515w(0)) OR (bp2_wire AND bp1_wire))) OR be_write_prot);
END IF;
END IF;
END PROCESS;
wire_write_prot_reg_ena <= (((wire_w_lg_w_lg_do_sec_erase501w502w(0) AND (NOT wire_wrstage_cntr_q(1))) AND wire_wrstage_cntr_q(0)) AND end_ophdly);
PROCESS (clkin_wire, clr_write_wire)
BEGIN
IF (clr_write_wire = '1') THEN write_reg <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_write_reg_ena = '1') THEN write_reg <= write;
END IF;
END IF;
END PROCESS;
wire_write_reg_ena <= (wire_w_lg_busy_wire2w(0) AND wren_wire);
PROCESS (clkin_wire, clr_write_wire)
BEGIN
IF (clr_write_wire = '1') THEN write_rstat_reg <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN write_rstat_reg <= (wire_w_lg_w_lg_w_lg_do_write65w66w499w(0) AND (((NOT wire_wrstage_cntr_q(1)) AND wire_wrstage_cntr_w_lg_w_q_range492w493w(0)) OR wire_wrstage_cntr_w_lg_w_q_range494w495w(0)));
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_secprot_wire)
BEGIN
IF (clr_secprot_wire = '1') THEN wrstat_dreg(0) <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_wrstat_dreg_ena(0) = '1') THEN wrstat_dreg(0) <= wire_wrstat_dreg_d(0);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_secprot_wire)
BEGIN
IF (clr_secprot_wire = '1') THEN wrstat_dreg(1) <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_wrstat_dreg_ena(1) = '1') THEN wrstat_dreg(1) <= wire_wrstat_dreg_d(1);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_secprot_wire)
BEGIN
IF (clr_secprot_wire = '1') THEN wrstat_dreg(2) <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_wrstat_dreg_ena(2) = '1') THEN wrstat_dreg(2) <= wire_wrstat_dreg_d(2);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_secprot_wire)
BEGIN
IF (clr_secprot_wire = '1') THEN wrstat_dreg(3) <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_wrstat_dreg_ena(3) = '1') THEN wrstat_dreg(3) <= wire_wrstat_dreg_d(3);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_secprot_wire)
BEGIN
IF (clr_secprot_wire = '1') THEN wrstat_dreg(4) <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_wrstat_dreg_ena(4) = '1') THEN wrstat_dreg(4) <= wire_wrstat_dreg_d(4);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_secprot_wire)
BEGIN
IF (clr_secprot_wire = '1') THEN wrstat_dreg(5) <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_wrstat_dreg_ena(5) = '1') THEN wrstat_dreg(5) <= wire_wrstat_dreg_d(5);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_secprot_wire)
BEGIN
IF (clr_secprot_wire = '1') THEN wrstat_dreg(6) <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_wrstat_dreg_ena(6) = '1') THEN wrstat_dreg(6) <= wire_wrstat_dreg_d(6);
END IF;
END IF;
END PROCESS;
PROCESS (clkin_wire, clr_secprot_wire)
BEGIN
IF (clr_secprot_wire = '1') THEN wrstat_dreg(7) <= '0';
ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN
IF (wire_wrstat_dreg_ena(7) = '1') THEN wrstat_dreg(7) <= wire_wrstat_dreg_d(7);
END IF;
END IF;
END PROCESS;
wire_wrstat_dreg_d <= ( wire_w_lg_w_lg_not_busy605w606w & wire_w_lg_not_busy610w);
loop39 : FOR i IN 0 TO 7 GENERATE
wire_wrstat_dreg_ena(i) <= wire_w_lg_w_lg_wren_wire615w616w(0);
END GENERATE loop39;
wire_wrstat_dreg_w_q_range602w <= wrstat_dreg(6 DOWNTO 0);
wire_cmpr5_dataa <= ( page_size_wire(8 DOWNTO 0));
wire_cmpr5_datab <= ( wire_pgwr_data_cntr_q(8 DOWNTO 0));
cmpr5 : lpm_compare
GENERIC MAP (
LPM_WIDTH => 9
)
PORT MAP (
aeb => wire_cmpr5_aeb,
dataa => wire_cmpr5_dataa,
datab => wire_cmpr5_datab
);
wire_cmpr6_dataa <= ( wire_pgwr_data_cntr_q(8 DOWNTO 0));
wire_cmpr6_datab <= ( wire_pgwr_read_cntr_q(8 DOWNTO 0));
cmpr6 : lpm_compare
GENERIC MAP (
LPM_WIDTH => 9
)
PORT MAP (
aeb => wire_cmpr6_aeb,
dataa => wire_cmpr6_dataa,
datab => wire_cmpr6_datab
);
wire_pgwr_data_cntr_clk_en <= wire_w_lg_w_lg_w_lg_shift_bytes_wire434w450w451w(0);
wire_w_lg_w_lg_w_lg_shift_bytes_wire434w450w451w(0) <= ((shift_bytes_wire AND wren_wire) AND wire_w_lg_reach_max_cnt449w(0)) AND wire_w_lg_do_write408w(0);
wire_pgwr_data_cntr_w_q_range455w(0) <= wire_pgwr_data_cntr_q(1);
wire_pgwr_data_cntr_w_q_range458w(0) <= wire_pgwr_data_cntr_q(2);
wire_pgwr_data_cntr_w_q_range461w(0) <= wire_pgwr_data_cntr_q(3);
wire_pgwr_data_cntr_w_q_range464w(0) <= wire_pgwr_data_cntr_q(4);
wire_pgwr_data_cntr_w_q_range467w(0) <= wire_pgwr_data_cntr_q(5);
wire_pgwr_data_cntr_w_q_range470w(0) <= wire_pgwr_data_cntr_q(6);
wire_pgwr_data_cntr_w_q_range473w(0) <= wire_pgwr_data_cntr_q(7);
wire_pgwr_data_cntr_w_q_range476w(0) <= wire_pgwr_data_cntr_q(8);
pgwr_data_cntr : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_width => 9
)
PORT MAP (
aclr => clr_write_wire,
clk_en => wire_pgwr_data_cntr_clk_en,
clock => clkin_wire,
q => wire_pgwr_data_cntr_q
);
pgwr_read_cntr : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_width => 9
)
PORT MAP (
aclr => clr_write_wire,
clk_en => read_buf,
clock => clkin_wire,
q => wire_pgwr_read_cntr_q
);
wire_mux211_dataout <= end1_cyc_dlyncs_in_wire WHEN (((do_write OR do_sec_prot) OR do_sec_erase) OR do_bulk_erase) = '1' ELSE end1_cyc_normal_in_wire;
wire_mux212_dataout <= end_add_cycle_mux_datab_wire WHEN do_fast_read = '1' ELSE wire_addbyte_cntr_w_lg_w_q_range137w142w(0);
wire_scfifo4_data <= ( datain(7 DOWNTO 0));
wire_scfifo4_rdreq <= wire_w_lg_read_buf436w(0);
wire_w_lg_read_buf436w(0) <= read_buf OR dummy_read_buf;
wire_scfifo4_wrreq <= wire_w_lg_w_lg_shift_bytes_wire434w435w(0);
wire_w_lg_w_lg_shift_bytes_wire434w435w(0) <= (shift_bytes_wire AND wren_wire) AND wire_w_lg_do_write408w(0);
wire_scfifo4_w_q_range441w <= wire_scfifo4_q(7 DOWNTO 1);
wire_scfifo4_w_q_range446w(0) <= wire_scfifo4_q(0);
scfifo4 : scfifo
GENERIC MAP (
LPM_NUMWORDS => 258,
LPM_WIDTH => 8,
LPM_WIDTHU => 9,
USE_EAB => "ON"
)
PORT MAP (
aclr => clr_write_wire,
clock => clkin_wire,
data => wire_scfifo4_data,
q => wire_scfifo4_q,
rdreq => wire_scfifo4_rdreq,
wrreq => wire_scfifo4_wrreq
);
END RTL; --z126_01_pasmi_sim_m25p32_altasmi_parallel_l2q2
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY z126_01_pasmi_sim_m25p32 IS
PORT
(
addr : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
bulk_erase : IN STD_LOGIC ;
clkin : IN STD_LOGIC ;
datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
fast_read : IN STD_LOGIC ;
rden : IN STD_LOGIC ;
read_rdid : IN STD_LOGIC ;
read_status : IN STD_LOGIC ;
sector_erase : IN STD_LOGIC ;
sector_protect : IN STD_LOGIC ;
shift_bytes : IN STD_LOGIC ;
wren : IN STD_LOGIC ;
write : IN STD_LOGIC ;
busy : OUT STD_LOGIC ;
data_valid : OUT STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
illegal_erase : OUT STD_LOGIC ;
illegal_write : OUT STD_LOGIC ;
rdid_out : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
status_out : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END z126_01_pasmi_sim_m25p32;
ARCHITECTURE RTL OF z126_01_pasmi_sim_m25p32 IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
ATTRIBUTE clearbox_macroname: string;
ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "ALTASMI_PARALLEL";
ATTRIBUTE clearbox_defparam: string;
ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "data_width=STANDARD;epcs_type=EPCS16;intended_device_family=Cyclone III;lpm_hint=UNUSED;lpm_type=altasmi_parallel;page_size=256;port_bulk_erase=PORT_USED;port_en4b_addr=PORT_UNUSED;port_fast_read=PORT_USED;port_illegal_erase=PORT_USED;port_illegal_write=PORT_USED;port_rdid_out=PORT_USED;port_read_address=PORT_UNUSED;port_read_rdid=PORT_USED;port_read_sid=PORT_UNUSED;port_read_status=PORT_USED;port_sector_erase=PORT_USED;port_sector_protect=PORT_USED;port_shift_bytes=PORT_USED;port_wren=PORT_USED;port_write=PORT_USED;use_eab=ON;";
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC ;
COMPONENT z126_01_pasmi_sim_m25p32_altasmi_parallel_l2q2
PORT (
sector_protect : IN STD_LOGIC ;
bulk_erase : IN STD_LOGIC ;
clkin : IN STD_LOGIC ;
data_valid : OUT STD_LOGIC ;
datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
fast_read : IN STD_LOGIC ;
illegal_erase : OUT STD_LOGIC ;
rden : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdid_out : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
read_rdid : IN STD_LOGIC ;
addr : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
busy : OUT STD_LOGIC ;
read_status : IN STD_LOGIC ;
sector_erase : IN STD_LOGIC ;
status_out : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
write : IN STD_LOGIC ;
illegal_write : OUT STD_LOGIC ;
shift_bytes : IN STD_LOGIC ;
wren : IN STD_LOGIC
);
END COMPONENT;
BEGIN
data_valid <= sub_wire0;
illegal_erase <= sub_wire1;
dataout <= sub_wire2(7 DOWNTO 0);
rdid_out <= sub_wire3(7 DOWNTO 0);
busy <= sub_wire4;
status_out <= sub_wire5(7 DOWNTO 0);
illegal_write <= sub_wire6;
z126_01_pasmi_sim_m25p32_altasmi_parallel_l2q2_component : z126_01_pasmi_sim_m25p32_altasmi_parallel_l2q2
PORT MAP (
sector_protect => sector_protect,
bulk_erase => bulk_erase,
clkin => clkin,
datain => datain,
fast_read => fast_read,
rden => rden,
read_rdid => read_rdid,
addr => addr,
read_status => read_status,
sector_erase => sector_erase,
write => write,
shift_bytes => shift_bytes,
wren => wren,
data_valid => sub_wire0,
illegal_erase => sub_wire1,
dataout => sub_wire2,
rdid_out => sub_wire3,
busy => sub_wire4,
status_out => sub_wire5,
illegal_write => sub_wire6
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: DATA_WIDTH STRING "STANDARD"
-- Retrieval info: CONSTANT: EPCS_TYPE STRING "EPCS16"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altasmi_parallel"
-- Retrieval info: CONSTANT: PAGE_SIZE NUMERIC "256"
-- Retrieval info: CONSTANT: PORT_BULK_ERASE STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_EN4B_ADDR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FAST_READ STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_ILLEGAL_ERASE STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_ILLEGAL_WRITE STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_RDID_OUT STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_READ_ADDRESS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_READ_RDID STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_READ_SID STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_READ_STATUS STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_SECTOR_ERASE STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_SECTOR_PROTECT STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_SHIFT_BYTES STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_WREN STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_WRITE STRING "PORT_USED"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: addr 0 0 24 0 INPUT NODEFVAL "addr[23..0]"
-- Retrieval info: CONNECT: @addr 0 0 24 0 addr 0 0 24 0
-- Retrieval info: USED_PORT: bulk_erase 0 0 0 0 INPUT NODEFVAL "bulk_erase"
-- Retrieval info: CONNECT: @bulk_erase 0 0 0 0 bulk_erase 0 0 0 0
-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: USED_PORT: clkin 0 0 0 0 INPUT NODEFVAL "clkin"
-- Retrieval info: CONNECT: @clkin 0 0 0 0 clkin 0 0 0 0
-- Retrieval info: USED_PORT: data_valid 0 0 0 0 OUTPUT NODEFVAL "data_valid"
-- Retrieval info: CONNECT: data_valid 0 0 0 0 @data_valid 0 0 0 0
-- Retrieval info: USED_PORT: datain 0 0 8 0 INPUT NODEFVAL "datain[7..0]"
-- Retrieval info: CONNECT: @datain 0 0 8 0 datain 0 0 8 0
-- Retrieval info: USED_PORT: dataout 0 0 8 0 OUTPUT NODEFVAL "dataout[7..0]"
-- Retrieval info: CONNECT: dataout 0 0 8 0 @dataout 0 0 8 0
-- Retrieval info: USED_PORT: fast_read 0 0 0 0 INPUT NODEFVAL "fast_read"
-- Retrieval info: CONNECT: @fast_read 0 0 0 0 fast_read 0 0 0 0
-- Retrieval info: USED_PORT: illegal_erase 0 0 0 0 OUTPUT NODEFVAL "illegal_erase"
-- Retrieval info: CONNECT: illegal_erase 0 0 0 0 @illegal_erase 0 0 0 0
-- Retrieval info: USED_PORT: illegal_write 0 0 0 0 OUTPUT NODEFVAL "illegal_write"
-- Retrieval info: CONNECT: illegal_write 0 0 0 0 @illegal_write 0 0 0 0
-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT NODEFVAL "rden"
-- Retrieval info: CONNECT: @rden 0 0 0 0 rden 0 0 0 0
-- Retrieval info: USED_PORT: rdid_out 0 0 8 0 OUTPUT NODEFVAL "rdid_out[7..0]"
-- Retrieval info: CONNECT: rdid_out 0 0 8 0 @rdid_out 0 0 8 0
-- Retrieval info: USED_PORT: read_rdid 0 0 0 0 INPUT NODEFVAL "read_rdid"
-- Retrieval info: CONNECT: @read_rdid 0 0 0 0 read_rdid 0 0 0 0
-- Retrieval info: USED_PORT: read_status 0 0 0 0 INPUT NODEFVAL "read_status"
-- Retrieval info: CONNECT: @read_status 0 0 0 0 read_status 0 0 0 0
-- Retrieval info: USED_PORT: sector_erase 0 0 0 0 INPUT NODEFVAL "sector_erase"
-- Retrieval info: CONNECT: @sector_erase 0 0 0 0 sector_erase 0 0 0 0
-- Retrieval info: USED_PORT: sector_protect 0 0 0 0 INPUT NODEFVAL "sector_protect"
-- Retrieval info: CONNECT: @sector_protect 0 0 0 0 sector_protect 0 0 0 0
-- Retrieval info: USED_PORT: shift_bytes 0 0 0 0 INPUT NODEFVAL "shift_bytes"
-- Retrieval info: CONNECT: @shift_bytes 0 0 0 0 shift_bytes 0 0 0 0
-- Retrieval info: USED_PORT: status_out 0 0 8 0 OUTPUT NODEFVAL "status_out[7..0]"
-- Retrieval info: CONNECT: status_out 0 0 8 0 @status_out 0 0 8 0
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @wren 0 0 0 0 wren 0 0 0 0
-- Retrieval info: USED_PORT: write 0 0 0 0 INPUT NODEFVAL "write"
-- Retrieval info: CONNECT: @write 0 0 0 0 write 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL z126_01_pasmi_sim_m25p32_2.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL z126_01_pasmi_sim_m25p32_2.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL z126_01_pasmi_sim_m25p32_2.bsf FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL z126_01_pasmi_sim_m25p32_2_inst.vhd FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL z126_01_pasmi_sim_m25p32_2.inc FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL z126_01_pasmi_sim_m25p32_2.cmp FALSE TRUE
| gpl-3.0 | 38dfaa8c9d4b41d3cc2304abbe776343 | 0.681732 | 2.383107 | false | false | false | false |
cathalmccabe/PYNQ | boards/ip/dvi2rgb_v1_7/src/dvi2rgb.vhd | 4 | 11,324 | -------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 24 July 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 sink interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure, deserialization, phase alignment, channel deskew and
-- decode logic. It outputs 24-bit RGB video data along with pixel clock and
-- synchronization signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dvi2rgb is
Generic (
kEmulateDDC : boolean := true; --will emulate a DDC EEPROM with basic EDID, if set to yes
kRstActiveHigh : boolean := true; --true, if active-high; false, if active-low
kAddBUFG : boolean := true; --true, if PixelClk should be re-buffered with BUFG
kClkRange : natural := 2; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
kEdidFileName : string := "900p_edid.data"; -- Select EDID file to use
-- 7-series specific
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
TMDS_Data_p : in std_logic_vector(2 downto 0);
TMDS_Data_n : in std_logic_vector(2 downto 0);
-- Auxiliary signals
RefClk : in std_logic; --200 MHz reference clock for IDELAYCTRL, reset, lock monitoring etc.
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video out
vid_pData : out std_logic_vector(23 downto 0);
vid_pVDE : out std_logic;
vid_pHSync : out std_logic;
vid_pVSync : out std_logic;
PixelClk : out std_logic; --pixel-clock recovered from the DVI interface
SerialClk : out std_logic; -- advanced use only; 5x PixelClk
aPixelClkLckd : out std_logic; -- advanced use only; PixelClk and SerialClk stable
-- Optional DDC port
DDC_SDA_I : in std_logic;
DDC_SDA_O : out std_logic;
DDC_SDA_T : out std_logic;
DDC_SCL_I : in std_logic;
DDC_SCL_O : out std_logic;
DDC_SCL_T : out std_logic;
pRst : in std_logic; -- synchronous reset; will restart locking procedure
pRst_n : in std_logic -- synchronous reset; will restart locking procedure
);
end dvi2rgb;
architecture Behavioral of dvi2rgb is
type dataIn_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type eyeSize_t is array (2 downto 0) of std_logic_vector(kIDLY_TapWidth-1 downto 0);
signal aLocked, SerialClk_int, PixelClk_int, pLockLostRst: std_logic;
signal pRdy, pVld, pDE, pAlignErr, pC0, pC1 : std_logic_vector(2 downto 0);
signal pDataIn : dataIn_t;
signal pEyeSize : eyeSize_t;
signal aRst_int, pRst_int : std_logic;
signal pData : std_logic_vector(23 downto 0);
signal pVDE, pHSync, pVSync : std_logic;
-- set KEEP attribute so that synthesis does not optimize this register
-- in case we want to connect it to an inserted ILA debug core
attribute KEEP : string;
attribute KEEP of pEyeSize: signal is "TRUE";
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
pRst_int <= not pRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
pRst_int <= pRst;
end generate ResetActiveHigh;
-- Clocking infrastructure to obtain a usable fast serial clock and a slow parallel clock
TMDS_ClockingX: entity work.TMDS_Clocking
generic map (
kClkRange => kClkRange)
port map (
aRst => aRst_int,
RefClk => RefClk,
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
aLocked => aLocked,
PixelClk => PixelClk_int, -- slow parallel clock
SerialClk => SerialClk_int -- fast serial clock
);
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aLocked,
OutClk => PixelClk_int,
oRst => pLockLostRst);
-- Three data channel decoders
DataDecoders: for iCh in 2 downto 0 generate
DecoderX: entity work.TMDS_Decoder
generic map (
kCtlTknCount => kMinTknCntForBlank, --how many subsequent control tokens make a valid blank detection (DVI spec)
kTimeoutMs => kBlankTimeoutMs, --what is the maximum time interval for a blank to be detected (DVI spec)
kRefClkFrqMHz => 200, --what is the RefClk frequency
kIDLY_TapValuePs => kIDLY_TapValuePs, --delay in ps per tap
kIDLY_TapWidth => kIDLY_TapWidth) --number of bits for IDELAYE2 tap counter
port map (
aRst => pLockLostRst,
PixelClk => PixelClk_int,
SerialClk => SerialClk_int,
RefClk => RefClk,
pRst => pRst_int,
sDataIn_p => TMDS_Data_p(iCh),
sDataIn_n => TMDS_Data_n(iCh),
pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew
pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew
pAlignErr => pAlignErr(iCh),
pC0 => pC0(iCh),
pC1 => pC1(iCh),
pMeRdy => pRdy(iCh),
pMeVld => pVld(iCh),
pVde => pDE(iCh),
pDataIn(7 downto 0) => pDataIn(iCh),
pEyeSize => pEyeSize(iCh)
);
end generate DataDecoders;
-- RGB Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason video_data uses RBG packing
pData(23 downto 16) <= pDataIn(2); -- red is channel 2
pData(7 downto 0) <= pDataIn(1); -- green is channel 1
pData(15 downto 8) <= pDataIn(0); -- blue is channel 0
pHSync <= pC0(0); -- channel 0 carries control signals too
pVSync <= pC1(0); -- channel 0 carries control signals too
pVDE <= pDE(0); -- since channels are aligned, all of them are either active or blanking at once
-- Clock outputs
SerialClk <= SerialClk_int; -- fast 5x pixel clock for advanced use only
aPixelClkLckd <= aLocked;
----------------------------------------------------------------------------------
-- Re-buffer PixelClk with a BUFG so that it can reach the whole device, unlike
-- through a BUFR. Since BUFG introduces a delay on the clock path, pixel data is
-- re-registered here.
----------------------------------------------------------------------------------
GenerateBUFG: if kAddBUFG generate
ResyncToBUFG_X: entity work.ResyncToBUFG
port map (
-- Video in
piData => pData,
piVDE => pVDE,
piHSync => pHSync,
piVSync => pVSync,
PixelClkIn => PixelClk_int,
-- Video out
poData => vid_pData,
poVDE => vid_pVDE,
poHSync => vid_pHSync,
poVSync => vid_pVSync,
PixelClkOut => PixelClk
);
end generate GenerateBUFG;
DontGenerateBUFG: if not kAddBUFG generate
vid_pData <= pData;
vid_pVDE <= pVDE;
vid_pHSync <= pHSync;
vid_pVSync <= pVSync;
PixelClk <= PixelClk_int;
end generate DontGenerateBUFG;
----------------------------------------------------------------------------------
-- Optional DDC EEPROM Display Data Channel - Bi-directional (DDC2B)
-- The EDID will be loaded from the file specified below in kInitFileName.
----------------------------------------------------------------------------------
GenerateDDC: if kEmulateDDC generate
DDC_EEPROM: entity work.EEPROM_8b
generic map (
kSampleClkFreqInMHz => 200,
kSlaveAddress => "1010000",
kAddrBits => 7, -- 128 byte EDID 1.x data
kWritable => false,
kInitFileName => kEdidFileName) -- name of file containing init values
port map(
SampleClk => RefClk,
sRst => '0',
aSDA_I => DDC_SDA_I,
aSDA_O => DDC_SDA_O,
aSDA_T => DDC_SDA_T,
aSCL_I => DDC_SCL_I,
aSCL_O => DDC_SCL_O,
aSCL_T => DDC_SCL_T);
end generate GenerateDDC;
end Behavioral;
| bsd-3-clause | ff9d0175bffd6d36015f495fb2981f06 | 0.609679 | 4.555109 | false | false | false | false |
nulldozer/purisc | Compute_Group/MAGIC_clocked/RAM_7.vhd | 1 | 10,399 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM_7.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY RAM_7 IS
PORT
(
aclr : IN STD_LOGIC := '0';
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END RAM_7;
ARCHITECTURE SYN OF ram_7 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
init_file => "RAM_7.mif",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "CLEAR0",
outdata_aclr_b => "CLEAR0",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "OLD_DATA",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 10,
widthad_b => 10,
width_a => 32,
width_b => 32,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
aclr0 => aclr,
address_a => address_a,
address_b => address_b,
clock0 => clock,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "1"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "RAM_7.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INIT_FILE STRING "RAM_7.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
-- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
-- Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
-- Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
-- Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
-- Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_7.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_7.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_7.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_7.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_7_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | 145c322d52517c2a822e1fe6a060aaaf | 0.666314 | 3.290823 | false | false | false | false |
michaelmiehling/A25_VME_TB | Testbench/M25P32/internal_logic.vhd | 1 | 34,773 | -------------------------------------------------------
-- Author: Hugues CREUSY
--February 2004
-- VHDL model
-- project: M25P32 50 MHz,
-- release: 1.0
-----------------------------------------------------
-- Unit : Internal logic
-----------------------------------------------------
-------------------------------------------------------------
-- These VHDL models are provided "as is" without warranty
-- of any kind, included but not limited to, implied warranty
-- of merchantability and fitness for a particular purpose.
-------------------------------------------------------------
------------------------------------------------------------------
--
-- INTERNAL LOGIC
--
------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library STD;
use STD.textio.ALL;
library WORK;
use WORK.MEM_UTIL_PKG.ALL;
-----------------------------------------------------------------------
-- Entity
-----------------------------------------------------------------------
-- This entity modelizes data reception and treatment by the SPI bus --
-----------------------------------------------------------------------
ENTITY Internal_Logic IS
GENERIC ( SIZE : positive;
Plength : positive;
SSIZE : positive;
Nb_BPi: positive;
signature : STD_LOGIC_VECTOR (7 downto 0);
manufacturerID : STD_LOGIC_VECTOR (7 downto 0);
memtype : STD_LOGIC_VECTOR (7 downto 0);
density : STD_LOGIC_VECTOR (7 downto 0);
NB_BIT_DATA: positive;
NB_BIT_ADD: positive;
NB_BIT_ADD_MEM: positive;
Tc: TIME;
tSLCH: TIME;
tCHSL: TIME;
tCH: TIME;
tCL: TIME;
tDVCH: TIME;
tCHDX: TIME;
tCHSH: TIME;
tSHCH: TIME;
tSHSL: TIME;
tSHQZ: TIME;
tCLQV: TIME;
tHLCH: TIME;
tCHHH: TIME;
tHHCH: TIME;
tCHHL: TIME;
tHHQX: TIME;
tHLQZ: TIME;
tWHSL: TIME;
tSHWL: TIME;
tDP:TIME;
tRES1:TIME;
tRES2:TIME;
tW: TIME;
tPP:TIME;
tSE:TIME;
tBE:TIME
);
PORT ( C, D,W,S,hold: IN std_logic;
data_to_read: IN std_logic_vector (NB_BIT_DATA-1 downto 0);
Power_up: IN boolean;
Q: OUT std_logic;
p_prog: OUT page(0 TO (Plength-1));
add_mem: OUT std_logic_vector(NB_BIT_ADD_MEM-1 downto 0);
write_op,read_op,BE_enable,SE_enable,add_pp_enable,PP_enable,READ_enable,data_request: OUT boolean;
wrsr: INOUT boolean;
srwd_wrsr: INOUT boolean;
write_protect: INOUT boolean
);
END Internal_Logic;
-----------------------------------------------------------------------------
-- Architecture
-----------------------------------------------------------------------------
-- The architecture contains a process count_bit which counts the bits and --
-- bytes received, a process data_in which latches the data on data_latch. --
-- After that an asynchronous decode process makes data, operation codes --
-- and adresses treatment, and give instructions to a synchronous process --
-- (on clock c) which contains further instructions, warnings and failures --
-- concerning each one of the functions. --
-----------------------------------------------------------------------------
ARCHITECTURE behavioral OF Internal_Logic IS
SIGNAL only_rdsr, only_res,select_ok,raz, byte_ok,add_overflow,add_overflow_1,add_overflow_2: boolean:= false;
SIGNAL write_protect_toggle: boolean:= false;
SIGNAL cpt: integer:=0;
SIGNAL byte_cpt: integer:=0;
SIGNAL data_latch: std_logic_vector(NB_BIT_DATA-1 downto 0):="00000000";
SIGNAL wren, wrdi, rdsr, read_data,fast_read, pp, se, be, dp, res, rdid: boolean:=false; --HC 24/09/03
SIGNAL Q_bis:std_logic:='Z';
SIGNAL register_bis, status_register,wr_latch: std_logic_vector(7 downto 0):="00000000";
SIGNAL protect,wr_cycle,hold_cond: boolean:=false;
SIGNAL inhib_wren,inhib_wrdi,inhib_rdsr,inhib_WRSR,inhib_READ,inhib_PP,
inhib_SE,inhib_BE,inhib_DP,inhib_RES, inhib_RDID :boolean:=false; --HC 24/09/03
SIGNAL reset_WEL,WEL,WIP:std_logic:='0';
SIGNAL c_int : std_logic;
CONSTANT LSB_TO_CODE_PAGE:natural:=to_bit_code(Plength);
CONSTANT top_mem:positive:=size/NB_BIT_DATA-1;
SIGNAL t_write_protect_toggle: TIME:=0 ns;
BEGIN
Status_register<=register_bis;
-------------------------------------------------------------
-- This process generates the Hold condition when it is valid
hold_com: PROCESS
-------------------------------------------------------------
BEGIN
WAIT ON HOLD;
IF (HOLD = '0' AND S='0') THEN
IF (C='0') THEN
hold_cond <= true;
REPORT " HOLD: COMMUNICATION PAUSED "
SEVERITY NOTE;
ELSE WAIT ON C,hold;
IF (C='0') THEN
hold_cond <= true;
REPORT " HOLD: COMMUNICATION PAUSED "
SEVERITY NOTE;
END IF;
END IF;
ELSIF (HOLD = '1') THEN
IF (C='0') THEN
hold_cond <= false;
REPORT " HOLD: COMMUNICATION STARTS "
SEVERITY NOTE;
ELSE WAIT ON C,hold;
IF (C='0') THEN
hold_cond <= false;
REPORT " HOLD: COMMUNICATION STARTS "
SEVERITY NOTE;
END IF;
END IF;
END IF;
END PROCESS hold_com ;
------------------------------------------------------------------------
-- This process inhibits the internal clock when hold condition is valid
horloge: PROCESS
------------------------------------------------------------------------
BEGIN
WAIT ON C;
IF (NOT hold_cond) THEN
C_int<=C;
ELSIF (hold_cond) THEN
C_int<='0';
END IF;
END PROCESS horloge;
-----------------------------------------------------------------
-- This process inhibits data output when hold condition is valid
data_output: PROCESS
-----------------------------------------------------------------
BEGIN
WAIT ON hold_cond,Q_bis,S;
IF (hold_cond'event) THEN
IF (hold_cond) THEN
Q<='Z' after tHLQZ;
ELSIF (NOT hold_cond) THEN
Q<=Q_bis after tHHQX;
END IF;
ELSIF (NOT hold_cond) THEN
Q<=Q_bis;
END IF;
END PROCESS data_output;
------------------------------------------------------------
-- This process increments 2 counters: one bit counter (cpt)
-- one byte counter (byte_cpt)
count_bit: PROCESS
------------------------------------------------------------
VARIABLE count_enable: boolean := false;
BEGIN
WAIT ON C_int,raz;
IF (raz or NOT select_ok) THEN
cpt <= 0;
byte_cpt <= 0;
count_enable := false;
ELSE
IF (C_int = '1') THEN
-- count enable is an intermediate variable which allows cpt to be
-- constant during a whole period
count_enable := true;
END IF;
IF(count_enable AND C_int'event AND C_int = '0')THEN
cpt <= (cpt +1) MOD 8;
END IF;
IF(C_int = '0' AND byte_ok)THEN
byte_cpt <= (byte_cpt+1);
END IF;
END IF;
END PROCESS count_bit;
-----------------------------------------------------------------------
-- This process latches every byte of data received and returns byte_ok
data_in: PROCESS
-----------------------------------------------------------------------
VARIABLE data: std_logic_vector (7 downto 0):="00000000";
BEGIN
WAIT ON C_int,Select_ok;
IF (NOT select_ok) then
raz<=true;
byte_ok<=false;
data_latch<="00000000";
data:="00000000";
ELSIF (C_int'event and C_int='1') THEN
raz<=false;
IF (cpt=0) THEN
data_latch<="00000000";
byte_ok<=false;
END IF;
data(7-cpt):=D;
IF (cpt=7) THEN
byte_ok<=true;
data_latch<=data;
END IF;
END IF;
END PROCESS data_in;
---------------------------------------------------------------
----------------- ASYNCHRONOUS DECODE PROCESS -----------------
---------------------------------------------------------------
decode : PROCESS
VARIABLE LSB_adress:std_logic_vector(LSB_to_code_page-1 downto 0);
VARIABLE j:natural:=0;
VARIABLE adress:std_logic_vector (nb_bit_add_mem-1 downto 0);
VARIABLE adress_1, adress_2, adress_3: std_logic_vector(7 downto 0);
VARIABLE bit_to_code_mem:natural:=TO_bit_code(size/NB_BIT_DATA);
VARIABLE cut_add:std_logic_vector(bit_to_code_mem-1 downto 0);
VARIABLE register_temp:std_logic_vector ((NB_BIT_DATA-1) downto 0);
VARIABLE int_add:natural:=0;
VARIABLE first_run: boolean:=true;
VARIABLE message: LINE;
VARIABLE BP:std_logic_vector(NB_BPi-1 downto 0);
VARIABLE SR_MASK:std_logic_vector(7 downto 0):="10000000";
CONSTANT page_ini:std_logic_vector ((NB_BIT_DATA-1) downto 0):="11111111";
----------------------------------------------------------------------
-- Read and write status register procedures
-- PROCEDURE read_status (file_name:STRING; status: OUT std_logic_vector(7 downto 0)) IS
-- file data_file : text open read_mode is file_name;
-- VARIABLE L:LINE;
-- VARIABLE bit_status:bit_vector(7 downto 0);
-- BEGIN
-- readline (data_file,L);
-- READ(L,bit_status);
-- status:=to_StdLogicVector(bit_status) AND SR_Mask;
-- END read_status;
-- PROCEDURE write_status (file_name:STRING; status: IN std_logic_vector(7 downto 0)) IS
-- file data_file : text open write_mode is file_name;
-- VARIABLE L:LINE;
-- VARIABLE bit_status: bit_vector(7 downto 0);
-- BEGIN
-- bit_status:=to_BitVector(status);
-- WRITE(L,bit_status);
-- writeline (data_file,L);
-- END write_status;
---------------------------------------------------------------------
BEGIN
----------------------------------------------------------
-- Status Register initialization
----------------------------------------------------------
-- IF first_run THEN
-- WRITE (message,string'("Trying to load status_register.txt"));
-- writeline (output,message);
-- read_status("status_register.txt",register_temp);
-- register_bis<=register_temp;
-- first_run:=false;
-- END IF;
-------------------------------------------
-- wait statements
-------------------------------------------
WAIT ON Power_up,byte_ok,wr_cycle,WEL,reset_WEL,WIP,
inhib_WRSR,inhib_READ,inhib_PP,inhib_SE,
inhib_BE,inhib_rdsr,inhib_DP,inhib_RES, inhib_RDID;
---------------------------
-- status register mask ini
---------------------------
FOR i IN 0 TO NB_BPi-1 LOOP
SR_Mask(i+2):='1';
END LOOP;
-------------------------------------------
-- adresses initialization and reset
-------------------------------------------
IF (byte_cpt=0) THEN
FOR i IN 0 TO NB_BIT_ADD-1 LOOP
adress_1(i):='0';
adress_2(i):='0';
adress_3(i):='0';
END LOOP;
FOR i IN 0 TO NB_BIT_ADD_MEM-1 LOOP
adress(i):='0';
END LOOP;
add_mem<=adress;
END IF;
----------------------------------
-- page to program reset (FFh)
----------------------------------
IF (NOT PP) THEN
FOR i IN 0 TO (Plength-1) LOOP
P_prog(i)<=page_ini;
END LOOP;
END IF;
-----------------------------------------------------------
-- op_code decode
-----------------------------------------------------------
IF ((byte_ok'event AND byte_ok) AND (byte_cpt=0)) THEN
IF (data_latch="00000110") THEN
IF(only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE wren<=true;
write_op<=true;
END IF;
ELSIF (data_latch="00000100") THEN
IF(only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE wrdi<=true;
write_op<=true;
END IF;
ELSIF (data_latch="00000101") THEN
IF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE rdsr<=true;
END IF;
ELSIF (data_latch="00000001") THEN
IF(only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE wrsr<=true;
write_op<=true;
END IF;
ELSIF (data_latch="00000011") THEN
IF (only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE read_data<=true;
read_op<=true;
END IF;
ELSIF (data_latch="00001011") THEN
IF (only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE fast_read<=true;
END IF;
ELSIF (data_latch="00000010") THEN
IF (only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE pp<=true;
write_op<=true;
END IF;
ELSIF (data_latch="11011000") THEN
IF (only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE se<=true;
write_op<=true;
END IF;
ELSIF (data_latch="11000111") THEN
IF (only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE be<=true;
write_op<=true;
FOR i IN 0 TO NB_BPi-1 LOOP
BP(i):=status_register(i+2);
END LOOP;
IF (BP/="000") THEN
protect<=true;
write_op <= false;
END IF;
END IF;
ELSIF (data_latch="10111001") THEN
IF (only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE dp<=true;
END IF;
ELSIF (data_latch="10101011") THEN
IF (only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSE res<=true;
END IF;
ELSIF (data_latch="10011111") THEN -- HC 24/09/03
IF (only_rdsr) THEN
REPORT "This Opcode is not decoded during a Prog. Cycle"
SEVERITY ERROR;
ELSIF (only_res) THEN
REPORT "This Opcode is not decoded during a DEEP POWER DOWN"
SEVERITY ERROR;
ELSE rdid<=true;
END IF;
ELSE report " False instruction, please retry "
severity ERROR;
END IF;
END IF;
-----------------------------------------------------------------------
-- addresses and data reception and treatment
-----------------------------------------------------------------------
IF ((byte_ok'event AND byte_ok)AND(byte_cpt=1)AND(NOT only_rdsr)AND(NOT (only_res))) THEN
IF (((read_data) or (fast_read) or (se) or (pp)) AND (NOT rdsr)) THEN adress_1:=data_latch;
ELSIF (wrsr AND (NOT rdsr)) THEN
wr_latch<=data_latch;
END IF;
END IF;
IF ((byte_ok'event AND byte_ok)AND(byte_cpt=2)AND(NOT only_rdsr)AND(NOT (only_res))) THEN
IF (((read_data) or (fast_read) or (se) or (pp)) AND (NOT rdsr)) THEN
adress_2:=data_latch;
END IF;
END IF;
IF ((byte_ok'event AND byte_ok)AND(byte_cpt=3)AND(NOT only_rdsr)AND(NOT (only_res))) THEN
IF (((read_data) or (fast_read) or (se) or (pp)) AND (NOT rdsr)) THEN adress_3:=data_latch;
FOR i IN 0 TO (NB_BIT_ADD-1) LOOP
adress(i):=adress_3(i);
adress(i+NB_BIT_ADD):=adress_2(i);
adress(i+2*NB_BIT_ADD):=adress_1(i);
add_mem<=adress;
END LOOP;
FOR i in (LSB_TO_CODE_PAGE-1) downto 0 LOOP
LSB_adress(i):=adress(i);
END LOOP;
END IF;
IF ((se or pp) AND (NOT rdsr)) THEN
-------------------------------------------
-- To ignore "don't care MSB" of the adress
-------------------------------------------
FOR i IN 0 TO bit_to_code_mem-1 LOOP
cut_add(i):=adress(i);
END LOOP;
int_add:=to_natural(cut_add);
--------------------------------------------------
-- Sector protection detection
--------------------------------------------------
FOR i IN 0 TO NB_BPi-1 LOOP
BP(i):=status_register(i+2);
END LOOP;
IF (BP="111" or BP="110") THEN
protect<=true;
write_op <= false;
ELSIF BP="101" THEN
IF int_add>=((TOP_MEM+1)/2) THEN
protect<=true;
write_op <= false;
END IF;
ELSIF BP="100" THEN
IF int_add>=((TOP_MEM+1)*3/4) THEN
protect<=true;
write_op <= false;
END IF;
ELSIF BP="011" THEN
IF int_add>=((TOP_MEM+1)*7/8) THEN
protect<=true;
write_op <= false;
END IF;
ELSIF BP="010" THEN
IF int_add>=((TOP_MEM+1)*15/16) THEN
protect<=true;
write_op <= false;
END IF;
ELSIF BP="001" THEN
IF int_add>=((TOP_MEM+1)*31/32) THEN
protect<=true;
write_op <= false;
END IF;
ELSE protect<=false;
END IF;
END IF;
END IF;
-----------------------------------------------------------------------------
-- PAGE PROGRAM
-- The adress's LSBs necessary to code a whole page are converted to a natural
-- and used to fullfill the page buffer p_prog the same way as the memory page
-- will be fullfilled.
----------------------------------------------------------------------------
IF (byte_ok'event and byte_ok and (byte_cpt>=4)AND(PP)AND(NOT only_rdsr)AND(NOT rdsr)) THEN
j:=(byte_cpt - 1 - NB_BIT_ADD_MEM/NB_BIT_ADD + to_natural(LSB_adress)) MOD(Plength);
p_prog(j)<=data_latch;
END IF;
----------------------------------------------
--- READ INSTRUCTIONS
----------------------------------------------
-- to inhib READ instruction
IF (inhib_read) THEN
read_op <= false;
READ_data<=false;
fast_READ<=false;
READ_enable<=false;
data_request<=false;
END IF;
-- to launch adress treatment in memory access
IF ( ((byte_ok'event AND byte_ok) AND READ_data AND (byte_cpt=3))
OR ((byte_ok'event AND byte_ok) AND fast_READ AND (byte_cpt=4)) ) THEN
READ_enable<=true;
END IF;
-- to send a request for the data pointed by the adress
IF ( ((byte_ok'event AND byte_ok) AND READ_data AND (byte_cpt>=3) )
OR ((byte_ok'event AND byte_ok) AND fast_READ AND (byte_cpt>=4)) ) THEN
data_request<=true;
END IF;
IF ( (READ_data AND (byte_cpt>3) AND (NOT byte_ok)) OR
(fast_READ AND (byte_cpt>4) AND (NOT byte_ok)) ) THEN
data_request<=false;
END IF;
--------------------------------------------------------
-- STATUS REGISTER INSTRUCTIONS
--------------------------------------------------------
-- WREN/WRDI instructions
-------------------------
IF (WEL'event AND WEL='1') THEN
register_bis(1)<='1';
END IF;
IF (inhib_wren'event and inhib_wren) THEN
WREN<=false;
write_op<=false;
END IF;
IF (inhib_wrdi'event and inhib_wrdi) THEN
WRDI<=false;
write_op<=false;
END IF;
------------------------
-- RESET WEL instruction
------------------------
IF (reset_WEL'event AND reset_WEL='1') THEN
register_bis(1)<='0';
END IF;
IF (Power_up'event AND Power_up) THEN
register_bis(1)<='0';
END IF;
---------------------
-- WRSR instructions
---------------------
IF (wr_cycle'event AND (wr_cycle))THEN
REPORT "Write status register cycle has begun"
severity NOTE;
register_bis<=((register_bis) or ("00000011"));
END IF;
IF (wr_cycle'event AND (NOT wr_cycle)) THEN
REPORT "Write status register cycle is finished"
severity NOTE;
register_bis<=((wr_latch) and SR_Mask);
-- register_temp:=wr_latch and SR_Mask;
-- write_status("status_register.txt",register_temp);
wrsr<=false;
END IF;
IF (inhib_WRSR'event and inhib_WRSR) THEN
wrsr<=false;
END IF;
IF (NOT wrsr) THEN
wr_latch<="00000000";
END IF;
--------
-- PROG
--------
IF (WIP'event AND WIP='1') THEN
register_bis(0)<='1';
END IF;
IF (WIP'event AND WIP='0') THEN
register_bis(0)<='0';
write_op<=false;
END IF;
--------------------
-- rdsr instruction
--------------------
IF (inhib_rdsr'event AND inhib_rdsr) THEN
rdsr<=false;
END IF;
------------------------------------------------------------
-- BULK/SECTOR ERASE INSTRUCTIONS
------------------------------------------------------------
IF (inhib_BE) THEN
protect<=false;
BE<=false;
END IF;
IF (inhib_SE) THEN
protect<=false;
SE<=false;
END IF;
------------------------------------------------------------
-- PAGE PROGRAM INSTRUCTIONS
------------------------------------------------------------
IF (inhib_PP) THEN
protect<=false;
PP<=false;
END IF;
------------------------------------------------------------
-- DEEP POWER DOWN
-- RELEASE FROM DEEP POWER DOWN AND READ ELECTRONIC SIGNATURE
-------------------------------------------------------------
IF (inhib_DP) THEN DP <=false; END IF;
IF (inhib_RES) THEN RES<=false; END IF;
-----------------------------
-- Read Jedec ID --HC 24/03/09
-----------------------------
IF (inhib_RDID) THEN RDID <= FALSE; END IF;
END PROCESS decode;
----------------------------------------------------------
----------------- SYNCHRONOUS PROCESS ----------------
----------------------------------------------------------
sync_instructions: PROCESS
VARIABLE i,j,k:natural:=0;
BEGIN
WAIT ON C_int, select_ok;
WEL<='0';
reset_WEL<='0';
---------------------------------------------
-- READ_data
---------------------------------------------
IF ((NOT READ_data) AND (NOT fast_read)) THEN
inhib_READ<=false;
END IF;
IF (((byte_cpt=0)
or (byte_cpt=1)
or (byte_cpt=2)
or (byte_cpt=3 AND cpt/=7))
AND READ_data AND (NOT select_ok)) THEN
REPORT "Instruction canceled because the chip is deselected"
SEVERITY WARNING;
inhib_READ<=true;
END IF;
IF (READ_data AND ((byte_cpt=3 AND cpt=7) OR (byte_cpt>=4))) THEN
IF (NOT select_ok) THEN
inhib_READ<=true;
i:=0;
Q_bis<='Z' after tSHQZ;
ELSIF (C_int'event AND C_int='0')THEN
Q_bis<=data_to_read(7-i) after tCLQV;
i:=(i+1) mod 8;
END IF;
END IF;
--------------------------------------------------------------------
-- Fast_Read
--------------------------------------------------------------------
IF (((byte_cpt=0)
or (byte_cpt=1)
or (byte_cpt=2)
or (byte_cpt=3)
or (byte_cpt=4 AND cpt/=7))
AND fast_READ AND (NOT select_ok)) THEN
REPORT "Instruction canceled because the chip is deselected"
SEVERITY WARNING;
inhib_READ<=true;
END IF;
IF (fast_READ AND ((byte_cpt=4 AND cpt=7) OR (byte_cpt>=5))) THEN
IF (NOT select_ok) THEN
inhib_READ<=true;
i:=0;
Q_bis<='Z' after tSHQZ;
ELSIF (C_int'event AND C_int='0')THEN
Q_bis<=data_to_read(7-i) after tCLQV;
i:=(i+1) mod 8;
END IF;
END IF;
-------------------------------------------
-- Write_enable
-------------------------------------------
IF (NOT WREN) THEN
inhib_WREN<=false;
END IF;
IF (WREN AND (NOT only_rdsr) AND (NOT only_res)) THEN
IF (C_int'event AND C_int='1') THEN
inhib_wren<=true;
report "Instruction canceled because the chip is still selected."
severity WARNING;
ELSIF (NOT select_ok) THEN
WEL<=('1');
inhib_wren<=true;
END IF;
END IF;
---------------------------------------------
-- Write_disable
---------------------------------------------
IF (NOT WRDI) THEN
inhib_WRDI<=false;
END IF;
IF (WRDI AND (NOT only_rdsr) AND (NOT only_res)) THEN
IF (C_int'event AND C_int='1') THEN
inhib_wrdi<=true;
report "Instruction canceled because the chip is still selected."
severity WARNING;
ELSIF (NOT select_ok) THEN
reset_WEL<=('1');
inhib_wrdi<=true;
END IF;
END IF;
-------------------------------------------
-- Write_status_register
-------------------------------------------
IF (NOT WRSR) THEN
inhib_WRSR<=false;
END IF;
IF (WRSR AND (NOT only_rdsr) AND (NOT only_res)) THEN
IF (byte_cpt=1 AND (cpt /=7 OR not byte_ok) AND (NOT wr_cycle)) THEN
IF (NOT select_ok) THEN
REPORT "Instruction canceled because the chip is deselected"
SEVERITY WARNING;
inhib_WRSR<=true;
END IF;
ELSIF (byte_cpt=1 AND cpt=7 AND byte_ok) THEN
IF (write_protect) THEN
REPORT "Instruction canceled because status register is hardware protected"
SEVERITY warning;
inhib_WRSR<=true;
ELSIF (select_ok'event AND (NOT select_ok)) THEN
IF (status_register(1)='0') THEN
REPORT "Instruction canceled because WEL is reset"
SEVERITY WARNING;
inhib_WRSR<=true;
ELSE wr_cycle<=true;
WIP <= '1';
WAIT FOR tW;
WIP <= '0';
wr_cycle<=false;
END IF;
END IF;
ELSIF (byte_cpt=2)THEN
IF ((C_int'event AND C_int='1') AND (NOT rdsr)) THEN
REPORT "Instruction canceled because the chip is still selected"
SEVERITY WARNING;
inhib_WRSR<=true;
ELSIF (select_ok'event AND (NOT select_ok)) THEN
IF (status_register(1)='0') THEN
REPORT "Instruction canceled because WEL is reset"
SEVERITY WARNING;
inhib_WRSR<=true;
ELSE wr_cycle<=true;
WIP <= '1';
WAIT FOR tW;
WIP <= '0';
wr_cycle<=false;
END IF;
END IF;
END IF;
END IF;
---------------------------------------------
-- Bulk_erase
---------------------------------------------
IF (NOT BE) THEN
inhib_BE<=false;
END IF;
IF (BE AND (NOT only_rdsr) AND (NOT only_res)) THEN
IF (C_int'event AND C_int='1') THEN
REPORT "Instruction canceled because the chip is still selected"
SEVERITY WARNING;
inhib_BE<=true;
ELSIF (NOT select_ok) THEN
IF (status_register(1)='0') THEN
REPORT "Instruction canceled because WEL is reset"
SEVERITY WARNING;
BE_enable<=false;
inhib_BE<=true;
ELSIF (protect AND BE) THEN
REPORT "Instruction canceled because at least one sector is protected"
SEVERITY WARNING;
BE_enable<=false;
inhib_BE<=true;
ELSE REPORT "Bulk erase cycle has begun"
severity NOTE;
BE_enable<=true;
WIP<='1';
WAIT for tBE;
REPORT "Bulk erase cycle is finished"
severity NOTE;
BE_enable<=false;
inhib_BE<=true;
WIP<='0';
reset_WEL<='1';
END IF;
END IF;
END IF;
---------------------------------------------
-- Sector_erase
---------------------------------------------
IF (NOT SE) THEN
inhib_SE<=false;
END IF;
IF ((byte_cpt=0 or byte_cpt=1 or byte_cpt=2 or (byte_cpt=3 AND (cpt/=7 OR not byte_ok)))
AND SE AND (NOT only_rdsr) AND (NOT only_res)) THEN
IF (NOT select_ok) THEN
REPORT "Instruction canceled because the chip is deselected"
SEVERITY WARNING;
inhib_SE<=true;
END IF;
END IF;
IF ((byte_cpt=4 OR (byte_cpt=3 AND cpt=7 AND byte_ok)) AND SE AND (NOT only_RDSR) AND (NOT only_res)) THEN
IF (byte_cpt=4 AND (C_int'event AND C_int='1')) THEN
REPORT "Instruction canceled because the chip is still selected"
SEVERITY WARNING;
inhib_SE<=true;
ELSIF (NOT select_ok) THEN
IF (status_register(1)='0') THEN
REPORT "Instruction canceled because WEL is reset"
SEVERITY warning;
SE_enable<=false;
inhib_SE<=true;
ELSIF (protect AND SE) THEN
REPORT "Instruction canceled because the SE sector is protected"
SEVERITY WARNING;
SE_enable<=false;
inhib_SE<=true;
ELSE REPORT "Sector erase cycle has begun"
severity NOTE;
SE_enable<=true;
WIP<='1';
WAIT for tSE;
REPORT "Sector erase cycle is finished"
severity NOTE;
SE_enable<=false;
inhib_SE<=true;
WIP<='0';
reset_WEL<='1';
END IF;
END IF;
END IF;
---------------------------------------------
-- Page_Program
---------------------------------------------
IF (NOT PP) THEN
inhib_PP<=false;
add_pp_enable<=false;
pp_enable<=false;
END IF;
IF ((byte_cpt=0 or byte_cpt=1 or byte_cpt=2 or byte_cpt=3 or (byte_cpt=4 AND (cpt/=7 OR NOT byte_ok)))
AND PP AND (NOT only_rdsr) AND (NOT only_res) AND (NOT select_ok)) THEN
REPORT "Instruction canceled because the chip is deselected"
SEVERITY WARNING;
inhib_PP<=true;
END IF;
IF ((byte_cpt=5 OR (byte_cpt=4 AND cpt=7)) AND PP AND (NOT only_rdsr) AND (NOT only_res)) THEN
add_pp_enable<=true;
IF (status_register(1)='0') THEN
REPORT "Instruction canceled because WEL is reset"
SEVERITY warning;
PP_enable<=false;
inhib_PP<=true;
ELSIF (protect AND PP) THEN
REPORT "Instruction canceled because the PP sector is protected"
SEVERITY WARNING;
PP_enable<=false;
inhib_PP<=true;
END IF;
IF (select_ok'event AND (NOT select_ok) AND PP) THEN
REPORT "Page program cycle has begun"
severity NOTE;
WIP<='1';
WAIT for tPP;
REPORT "Page program cycle is finished"
SEVERITY NOTE;
PP_enable<=true;
WIP<='0';
inhib_PP<=true;
reset_WEL<='1';
END IF;
END IF;
IF (byte_cpt>5 AND PP AND (NOT only_rdsr) AND (NOT only_res) AND byte_ok) THEN
IF (select_ok'event AND (NOT select_ok)) THEN
REPORT "Page program cycle has begun"
severity NOTE;
WIP<='1';
WAIT for tPP;
REPORT "Page program cycle is finished"
SEVERITY NOTE;
PP_enable<=true;
WIP<='0';
inhib_PP<=true;
reset_WEL<='1';
END IF;
END IF;
IF (byte_cpt>5 AND PP AND (NOT only_rdsr) AND (NOT only_res) AND (NOT byte_ok)) THEN
IF (select_ok'event AND (NOT select_ok)) THEN
REPORT "Instruction canceled because the chip is deselected"
SEVERITY WARNING;
inhib_PP<=true;
PP_enable<=false;
END IF;
END IF;
-------------------------------------------
-- Deep Power Down
-------------------------------------------
IF (NOT DP) THEN
inhib_DP<=false;
only_res<=false;
END IF;
IF (DP AND (NOT only_rdsr) AND (NOT only_res) AND (NOT RES)) THEN
IF (C_int'event AND C_int='1') THEN
report "Instruction canceled because the chip is still selected."
severity WARNING;
inhib_DP<=true;
only_res<=false;
ELSIF (select_ok'event AND (NOT select_ok)) THEN
REPORT "Chip is entering deep power down mode"
SEVERITY NOTE;
-- useful when chip is selected again to inhib every op_code except RES
-- and to check tDP
only_res<=true;
END IF;
END IF;
-----------------------------------------------------------------------
-- Release from Deep Power Down Mode and Read Electronic Signature
-----------------------------------------------------------------------
IF (NOT RES) THEN
inhib_RES<=false;
j:=0;
END IF;
IF (RES AND (byte_cpt=1 and cpt=0) AND (NOT only_rdsr) AND (NOT select_ok) ) THEN
IF (only_res) THEN -- HC 22/09/03
REPORT "The chip is releasing from DEEP POWER DOWN"
SEVERITY NOTE;
inhib_RES<=false, true after tRES1;
inhib_DP<=false, true after tRES1;
ELSE
inhib_RES<=true; --HC 22/09/03
inhib_DP<=true; --HC 22/09/03
END IF;
ELSIF (((byte_cpt=1 AND cpt>0) OR (byte_cpt=2) OR (byte_cpt=3) OR (byte_cpt=4 AND (cpt<7 OR NOT byte_ok)))
AND RES AND (NOT only_rdsr) AND (NOT select_ok)) THEN
REPORT "Electronic Signature must be read at least once. Instruction not valid"
severity ERROR;
ELSIF (((byte_cpt=4 AND cpt=7 AND byte_ok) OR (byte_cpt>4)) AND RES AND (NOT only_rdsr)AND (NOT select_ok)) THEN
IF ( only_res) THEN -- HC 22/09/03
inhib_RES<=true after tRES2;
inhib_DP<=true after tRES2;
REPORT "The Chip is releasing from DEEP POWER DOWN" SEVERITY NOTE;
ELSE
inhib_RES<=true after tRES2; -- HC 22/09/03
inhib_DP<=true after tRES2; -- HC 22/09/03
END IF;
Q_bis<='Z';
ELSIF (((byte_cpt=3 AND cpt=7) OR byte_cpt>=4)
AND RES AND (NOT only_rdsr) AND (C_int'event AND C_int='0')) THEN
Q_bis<=signature(7-j) after tCLQV;
j:=(j+1) mod 8;
END IF;
-----------------------------------------------------------------------
-- Read Jedec Signature -- HC 24/09/03
-----------------------------------------------------------------------
IF (NOT RDID) THEN
inhib_RDID<=false;
END IF;
IF ((byte_cpt=0) AND RDID AND (NOT select_ok))
THEN REPORT "Instuction canceled because the chip is deselected" SEVERITY WARNING;
inhib_RDID <= true;
END IF;
IF (RDID AND ((byte_cpt=0 AND cpt=7) OR (byte_cpt>=1))) THEN
IF (NOT select_ok) THEN
inhib_RDID <= true;
k:=0;
Q_bis <='Z' after tSHQZ;
ELSIF (C_int'event AND C_int='0' AND byte_cpt<=1) THEN
Q_bis <= manufacturerID(7-k) after tCLQV;
k:=(k+1) MOD 8;
ELSIF (C_int'event AND C_int='0' AND byte_cpt=2) THEN
Q_bis <= memtype(7-k) after tCLQV;
k:=(k+1) MOD 8;
ELSIF (C_int'event AND C_int='0' AND byte_cpt=3) THEN
Q_bis <= density(7-k) after tCLQV;
k:=(k+1) MOD 8;
ELSIF (C_int'event AND C_int='0' AND byte_cpt>3) THEN
Q_bis <= '0' after tCLQV;
END IF;
END IF;
END PROCESS sync_instructions;
---------------------------------------------------------
-- This process shifts out status register on data output
Read_status_register: PROCESS
---------------------------------------------------------
VARIABLE j:integer:=0;
BEGIN
WAIT ON C_int,select_ok, rdsr;
IF (NOT rdsr) THEN
inhib_rdsr<=false;
END IF;
IF (RDSR AND (NOT select_ok)) THEN
j:=0;
Q_bis<= 'Z' after tSHQZ;
inhib_rdsr<=true;
ELSIF (RDSR AND (C_int'event AND C_int='0')) THEN
Q_bis<=status_register(7-j) after tCLQV;
j:=(j+1) mod 8;
END IF;
END PROCESS read_status_register;
----------------------------------------------------------------------------------------
-- This process checks select and deselect conditions. Some other conditions are tested:
-- prog cycle, deep power down mode and read electronic signature.
pin_S: PROCESS
----------------------------------------------------------------------------------------
BEGIN
WAIT ON S;
IF (S='0') THEN
IF (RES AND only_res) THEN -- HC 22/09/03
REPORT "The chip must be deselected during tRES"
severity ERROR;
ELSIF (DP) THEN
IF (NOT only_res'stable(tDP)) THEN
REPORT "The chip must be deselected during tDP"
severity ERROR;
ELSE
REPORT "Only a read electronic signature instruction will be valid !"
SEVERITY NOTE;
END IF;
END IF;
IF Power_up THEN select_ok<=true;
END IF;
IF(pp or wrsr or be or se) THEN
REPORT "Only a read status register instruction will be valid !"
SEVERITY NOTE;
only_rdsr<=true;
END IF;
END IF;
IF (S='1') THEN
select_ok<=false;
only_rdsr<=false;
END IF;
END PROCESS pin_S;
----------------------------------------------------------------
-- This Process detects the hardware protection mode
HPM_detect: PROCESS
----------------------------------------------------------------
BEGIN
WAIT ON W,C_int;
IF (W = '0'AND status_REGISTER(7) ='1') THEN
write_protect <= true;
END IF;
IF (W = '1') THEN
write_protect <= false;
END IF;
END PROCESS HPM_detect ;
----------------------------------------------------------------------
-- This process detects if Write_protect toggles during an instruction
write_protect_toggle_detect: PROCESS
----------------------------------------------------------------------
BEGIN
WAIT ON select_ok,write_protect;
IF (write_protect AND select_ok) THEN
write_protect_toggle <= true;
IF (now /= 0 ns) THEN t_write_protect_toggle <= now; END IF;
END IF;
IF (NOT select_ok) THEN write_protect_toggle <= false; END IF;
END PROCESS write_protect_toggle_detect;
---------------------------------------------------------------------
-- This process returns an error if SRWD=1 and Wc is swithed during a
-- WRSR instruction
---------------------------------------------------------------------
wc_error_detect: PROCESS
BEGIN
WAIT ON wrsr, write_protect_toggle;
IF (wrsr AND write_protect_toggle) THEN
IF (NOW /= 0 ns) THEN
REPORT "It is not allowed to switch the Wc pin during a WRSR instruction"
severity FAILURE;
END IF;
END IF;
IF (wrsr AND (status_REGISTER(7) ='1')) THEN
srwd_wrsr <= TRUE; -- becomes one when WRSR is decoded and WIP=1
END IF;
IF (NOT wrsr) THEN srwd_wrsr <= FALSE; END IF;
END PROCESS wc_error_detect;
END behavioral;
| gpl-3.0 | 2b0576c92c1fcbf0e9dd382b96c63bca | 0.56009 | 3.396132 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator | tb_Test_Pattern_Generator/hdl/alt_dspbuilder_case_statement_GNFTM45DFU.vhd | 4 | 904 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_case_statement_GNFTM45DFU is
generic ( number_outputs : integer := 2;
hasDefault : natural := 0;
pipeline : natural := 0;
width : integer := 16);
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(15 downto 0);
r0 : out std_logic;
r1 : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_case_statement_GNFTM45DFU is
begin
caseproc:process( input )
begin
case input is
when "0000000000000000" =>
r0 <= '1';
r1 <= '0';
when "0000000000000100" =>
r0 <= '0';
r1 <= '1';
when others =>
r0 <= '0';
r1 <= '0';
end case;
end process;
end architecture;
| mit | 7074050e082c4b3f5609e11e1b785758 | 0.63385 | 2.935065 | false | false | false | false |
freecores/t48 | rtl/vhdl/t48_pack-p.vhd | 1 | 2,475 | -------------------------------------------------------------------------------
--
-- $Id: t48_pack-p.vhd,v 1.1 2004-03-23 21:31:53 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package t48_pack is
-----------------------------------------------------------------------------
-- Global constants
-----------------------------------------------------------------------------
-- clock active level
constant clk_active_c : std_logic := '1';
-- reset active level
constant res_active_c : std_logic := '0';
-- idle level on internal data bus
constant bus_idle_level_c : std_logic := '1';
-- global data word width
constant word_width_c : natural := 8;
-- data memory address width
constant dmem_addr_width_c : natural := 8;
-- program memory address width
constant pmem_addr_width_c : natural := 12;
-----------------------------------------------------------------------------
-- Global data types
-----------------------------------------------------------------------------
-- the global data word width type
subtype word_t is std_logic_vector(word_width_c-1 downto 0);
subtype nibble_t is std_logic_vector(word_width_c/2-1 downto 0);
-- the global data memory address type
subtype dmem_addr_t is std_logic_vector(dmem_addr_width_c-1 downto 0);
-- the global program memory address type
subtype pmem_addr_t is std_logic_vector(pmem_addr_width_c-1 downto 0);
subtype page_t is std_logic_vector(pmem_addr_width_c-1 downto word_width_c);
-- the machine states
type mstate_t is (MSTATE1, MSTATE2, MSTATE3, MSTATE4, MSTATE5);
-----------------------------------------------------------------------------
-- Global functions
-----------------------------------------------------------------------------
function to_stdLogic(input: boolean) return std_logic;
function to_boolean(input: std_logic) return boolean;
end t48_pack;
package body t48_pack is
function to_stdLogic(input: boolean) return std_logic is
begin
if input then
return '1';
else
return '0';
end if;
end to_stdLogic;
function to_boolean(input: std_logic) return boolean is
begin
if input = '1' then
return true;
else
return false;
end if;
end to_boolean;
end t48_pack;
| gpl-2.0 | 7d68c796bb6268aef85b9899670d4ee8 | 0.498182 | 4.380531 | false | false | false | false |
Bourgeoisie/ECE368-RISC16 | 368RISC/ipcore_dir/tmp/_cg/Instruct_Memory/example_design/Instruct_Memory_prod.vhd | 2 | 10,300 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: Instruct_Memory_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : Instruct_Memory.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 32
-- C_READ_DEPTH_A : 32
-- C_ADDRA_WIDTH : 5
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 32
-- C_READ_DEPTH_B : 32
-- C_ADDRB_WIDTH : 5
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Instruct_Memory_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END Instruct_Memory_prod;
ARCHITECTURE xilinx OF Instruct_Memory_prod IS
COMPONENT Instruct_Memory_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : Instruct_Memory_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| mit | b0adac69fef0b659f6839f86979d85aa | 0.493592 | 3.844718 | false | false | false | false |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_rst_processing_system7_0_100M_0/sim/tutorial_rst_processing_system7_0_100M_0.vhd | 1 | 5,935 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY tutorial_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END tutorial_rst_processing_system7_0_100M_0;
ARCHITECTURE tutorial_rst_processing_system7_0_100M_0_arch OF tutorial_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END tutorial_rst_processing_system7_0_100M_0_arch;
| gpl-2.0 | 21024d6583c29e32420ea1acf9a160b2 | 0.710025 | 3.601335 | false | false | false | false |
michaelmiehling/A25_VME_TB | 16x010-00_src/Source/terminal_pkg.vhd | 1 | 22,063 | ---------------------------------------------------------------
-- Title : Package for simulation terminal
-- Project : -
---------------------------------------------------------------
-- File : terminal_pkg.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 22/09/03
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.9 $
--
-- $Log: terminal_pkg.vhd,v $
-- Revision 1.9 2010/08/16 12:57:16 FLenhardt
-- Added an overloaded MTEST which accepts a seed number as an input
--
-- Revision 1.8 2009/01/13 10:57:52 FLenhardt
-- Defined that TGA=2 means configuration access
--
-- Revision 1.7 2008/09/10 17:26:45 MSchindler
-- added flash_mtest_indirect procedure
--
-- Revision 1.6 2007/07/26 07:48:15 FLenhardt
-- Defined usage of TGA
--
-- Revision 1.5 2007/07/18 10:53:34 FLenhardt
-- Fixed bug regarding MTEST printout
--
-- Revision 1.4 2007/07/18 10:28:35 mernst
-- - Changed err to sum up errors instead of setting a specific value
-- - Added dat vector to terminal_in record
--
-- Revision 1.3 2006/08/24 08:52:02 mmiehling
-- changed txt_out to integer
--
-- Revision 1.1 2006/06/23 16:33:04 MMiehling
-- Initial Revision
--
-- Revision 1.2 2006/05/12 10:49:17 MMiehling
-- initialization of iram now with mem_init (back)
-- added testcase 14
--
-- Revision 1.1 2006/05/09 16:51:16 MMiehling
-- Initial Revision
--
-- Revision 1.2 2005/10/27 08:35:35 flenhardt
-- Added IRQ to TERMINAL_IN_TYPE record
--
-- Revision 1.1 2005/08/23 15:21:07 MMiehling
-- Initial Revision
--
-- Revision 1.1 2005/07/01 15:47:38 MMiehling
-- Initial Revision
--
-- Revision 1.2 2005/01/31 16:28:59 mmiehling
-- updated
--
-- Revision 1.1 2004/11/16 12:09:07 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.print_pkg.all;
USE ieee.std_logic_arith.ALL;
PACKAGE terminal_pkg IS
TYPE terminal_in_type IS record
done : boolean; -- edge indicates end of transfer
busy : std_logic; -- indicates status of master
err : natural; -- number of errors occured
irq : std_logic; -- interrupt request
dat : std_logic_vector(31 DOWNTO 0); -- Input data
END record;
TYPE terminal_out_type IS record
adr : std_logic_vector(31 DOWNTO 0); -- address
tga : std_logic_vector(5 DOWNTO 0); -- 0=mem, 1=io, 2=conf
dat : std_logic_vector(31 DOWNTO 0); -- write data
wr : natural; -- 0=read, 1=write, 2=wait for numb cycles
typ : natural; -- 0=b, w=1, l=2
numb : natural; -- number of transactions (1=single, >1=burst)
start : boolean; -- edge starts transfer
txt : integer; -- enables info messages -- 0=quiet, 1=only errors, 2=all
END record;
-- Bus Accesses
PROCEDURE init( SIGNAL terminal_out : OUT terminal_out_type);
PROCEDURE wait_for( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
numb : natural;
woe : boolean
);
PROCEDURE rd32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE rd16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE rd8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE wr32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
);
PROCEDURE wr16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
);
PROCEDURE wr8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
);
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
err : INOUT natural
) ;
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
seed : natural;
err : INOUT natural
) ;
PROCEDURE flash_mtest_indirect( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
adr_if : std_logic_vector; -- = address of indirect interface
txt_out : integer;
tga : std_logic_vector;
err : OUT natural
) ;
END terminal_pkg;
PACKAGE BODY terminal_pkg IS
----------------------------------------------------------------------------------------------------------
PROCEDURE init( SIGNAL terminal_out : OUT terminal_out_type) IS
BEGIN
terminal_out.adr <= (OTHERS => '0');
terminal_out.tga <= (OTHERS => '0');
terminal_out.dat <= (OTHERS => '0');
terminal_out.wr <= 0;
terminal_out.typ <= 0;
terminal_out.numb <= 0;
terminal_out.txt <= 0;
terminal_out.start <= TRUE;
END PROCEDURE init;
PROCEDURE wait_for( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
numb : natural;
woe : boolean
) IS
BEGIN
terminal_out.wr <= 2;
terminal_out.numb <= numb;
terminal_out.txt <= 0;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
PROCEDURE rd32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 2;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE rd16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 1;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE rd8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 0;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE wr32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 1;
terminal_out.typ <= 2;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
PROCEDURE wr8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 1;
terminal_out.typ <= 0;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
PROCEDURE wr16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 1;
terminal_out.typ <= 1;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
-- This is the legacy MTEST (without seed)
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
mtest(terminal_in, terminal_out, adr, adr_end, typ, numb, txt_out, tga, 0, err);
END PROCEDURE;
-- This is an overloaded MTEST which accepts a seed number as an input,
-- which can be used to generate the pseudo-random data in different ways
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
seed : natural;
err : INOUT natural
) IS
VARIABLE loc_err : natural;
VARIABLE loc_adr : std_logic_vector(31 DOWNTO 0);
VARIABLE loc_dat : std_logic_vector(31 DOWNTO 0);
VARIABLE numb_cnt : natural;
BEGIN
loc_adr := adr;
numb_cnt := 0;
loc_err := 0;
loc_dat := adr;
while NOT(numb_cnt = numb) LOOP
CASE typ IS
WHEN 0 => -- long
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896 + seed;
wr32(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga, loc_err);
loc_adr := loc_adr + x"4";
END LOOP;
WHEN 1 => -- word
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896 + seed;
wr16(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga);
rd16(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga, loc_err);
loc_adr := loc_adr + x"2";
END LOOP;
WHEN 2 => -- byte
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896 + seed;
wr8(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga);
rd8(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga, loc_err);
loc_adr := loc_adr + x"1";
END LOOP;
WHEN OTHERS =>
print("ERROR terminal_pkg: typ IS NOT defined!");
END CASE;
numb_cnt := numb_cnt + 1;
END LOOP;
IF loc_err > 0 THEN
print_s_i(" mtest FAIL errors: ", loc_err);
ELSE
print(" mtest PASS");
END IF;
err := err + loc_err;
END PROCEDURE;
PROCEDURE flash_mtest_indirect( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
adr_if : std_logic_vector; -- = address of indirect interface
txt_out : integer;
tga : std_logic_vector;
err : OUT natural
) IS
VARIABLE loc_err : natural;
VARIABLE loc_err2 : natural;
VARIABLE loc_adr : std_logic_vector(31 DOWNTO 0);
VARIABLE loc_dat : std_logic_vector(31 DOWNTO 0);
VARIABLE numb_cnt : natural;
BEGIN
--loc_adr := adr;
numb_cnt := 0;
loc_err := 0;
loc_dat := adr;
while NOT(numb_cnt = numb) LOOP
CASE typ IS
WHEN 0 => -- long
loc_adr := conv_std_logic_vector((conv_integer(adr)/4),32);
print("Flash Address OF the address register will be autoincremented");
print("Writing 32-bit data into Data Register => 32-bit Flash Memory access with indirect addressing");
print("Reading 32-bit-Address Register IN order TO control exact address register content");
while NOT (loc_adr = conv_std_logic_vector((conv_integer(adr_end)/4),32)) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
wr32(terminal_in, terminal_out, adr_if + x"0000_0004", loc_dat(31 DOWNTO 0), 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0000", "001" & loc_adr(28 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading address register: other value expected");
END IF;
loc_adr := loc_adr + x"1";
loc_err := loc_err + loc_err2;
END LOOP;
print("Reading Data Register from Memory using indirect addressing");
loc_adr := conv_std_logic_vector((conv_integer(adr)/4),32);
loc_dat := adr;
while NOT (loc_adr = conv_std_logic_vector((conv_integer(adr_end)/4),32)) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0004", loc_dat(31 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading data register: value READ from memory isn´t expected value");
END IF;
loc_err := loc_err + loc_err2;
loc_adr := loc_adr + x"1";
END LOOP;
WHEN 1 => -- word
loc_adr := conv_std_logic_vector((conv_integer(adr)/2),32);
print("Flash Address OF the address register will be autoincremented");
print("Writing 16-bit data into Data Register => 16-bit Flash Memory access with indirect addressing");
print("Reading 32-bit-Address Register IN order TO control exact address register content");
while NOT (loc_adr = conv_std_logic_vector((conv_integer(adr_end)/2),32)) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
wr32(terminal_in, terminal_out, adr_if + x"0000_0004", x"0000" & loc_dat(15 DOWNTO 0), 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0000", "010" & loc_adr(28 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading address register: other value expected");
END IF;
loc_adr := loc_adr + x"1";
loc_err := loc_err + loc_err2;
END LOOP;
print("READ AND Check 16-bit-Data from Memory using indirect addressing");
loc_adr := conv_std_logic_vector((conv_integer(adr)/2),32);
loc_dat := adr;
while NOT (loc_adr = conv_std_logic_vector((conv_integer(adr_end)/2),32)) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0004", x"0000" & loc_dat(15 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading data register: value READ from memory isn´t expected value");
END IF;
loc_err := loc_err + loc_err2;
loc_adr := loc_adr + x"1";
END LOOP;
WHEN 2 => -- byte
loc_adr := adr;
print("Flash Address OF the address register will be autoincremented");
print("Writing 8-bit data into Data Register => 8-bit Flash Memory access with indirect addressing");
print("Reading 32-bit-Address Register IN order TO control exact address register content");
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
wr32(terminal_in, terminal_out, adr_if + x"0000_0004", x"000000" & loc_dat(7 DOWNTO 0), 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0000", "000" & loc_adr(28 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading address register: other value expected");
END IF;
loc_adr := loc_adr + x"1";
loc_err := loc_err + loc_err2;
END LOOP;
print("READ AND Check 8-bit-Data from Memory using indirect addressing");
loc_adr := adr;
loc_dat := adr;
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0004", x"000000" & loc_dat(7 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading data register: value READ from memory isn´t expected value");
END IF;
loc_err := loc_err + loc_err2;
loc_adr := loc_adr + x"1";
END LOOP;
WHEN OTHERS =>
print("ERROR terminal_pkg: typ IS NOT defined!");
END CASE;
numb_cnt := numb_cnt + 1;
END LOOP;
IF loc_err > 0 THEN
print_s_i(" mtest_indirect FAIL errors: ", loc_err);
ELSE
print(" mtest_indirect PASS");
END IF;
err := loc_err;
END PROCEDURE;
--------------------------------------------------------------------------------------------
END; | gpl-3.0 | 4eedf6585ecda81851eeb4a710e2baaa | 0.558628 | 3.15727 | false | false | false | false |
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