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siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/RTL/New_SHMU_on_Node/ram.vhd
6
3,172
--------------------------------------------------------------------- -- TITLE: Random Access Memory -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 4/21/01 -- FILENAME: ram.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements the RAM, reads the executable from either "code.txt", -- or for Altera "code[0-3].hex". -- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_textio.all; use std.textio.all; use work.mlite_pack.all; entity ram is generic(memory_type : string := "DEFAULT"; stim_file: string :="code.txt"); port(clk : in std_logic; reset : in std_logic; enable : in std_logic; write_byte_enable : in std_logic_vector(3 downto 0); address : in std_logic_vector(31 downto 2); data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0)); end; --entity ram architecture logic of ram is constant ADDRESS_WIDTH : natural := 13; subtype word is std_logic_vector(data_write'length-1 downto 0); type storage_array is array(natural range 0 to (2 ** ADDRESS_WIDTH)/4 - 1) of word; signal storage : storage_array; begin ram_proc: process(clk, enable, write_byte_enable, address, data_write) --mem_write, mem_sel variable data : std_logic_vector(31 downto 0); variable index : natural := 0; file load_file : text open read_mode is stim_file; variable hex_file_line : line; begin --Load in the ram executable image if index = 0 then while not endfile(load_file) loop --The following two lines had to be commented out for synthesis readline(load_file, hex_file_line); hread(hex_file_line, data); storage(index) <= data; index := index + 1; end loop; end if; if rising_edge(clk) then index := conv_integer(address(ADDRESS_WIDTH-1 downto 2)); data := storage(index); if enable = '1' then if write_byte_enable(0) = '1' then data(7 downto 0) := data_write(7 downto 0); end if; if write_byte_enable(1) = '1' then data(15 downto 8) := data_write(15 downto 8); end if; if write_byte_enable(2) = '1' then data(23 downto 16) := data_write(23 downto 16); end if; if write_byte_enable(3) = '1' then data(31 downto 24) := data_write(31 downto 24); end if; end if; if write_byte_enable /= "0000" then storage(index) <= data; end if; end if; data_read <= data; end process; end; --architecture logic
gpl-3.0
445093ec4e21ad0c6d6de4a1f09a229c
0.559584
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simoesusp/Processador-ICMC
Processor_FPGA/Processor_Template_VHDL_DE70/cpu.vhd
1
28,019
-- Processador Versao 3: 23/05/2013 -- Jeg e Ceg concertado!! -- Video com 16 cores e tela de 40 colunas por 30 linhas libraRY ieee; use ieee.std_LOGIC_1164.all; use ieee.std_LOGIC_ARITH.all; use ieee.std_LOGIC_unsigned.all; entity cpu is port( clk : in std_LOGIC; reset : in std_LOGIC; Mem : in STD_LOGIC_VECTOR(15 downto 0); M5 : out STD_LOGIC_VECTOR(15 downto 0); M1 : out STD_LOGIC_VECTOR(15 downto 0); RW : out std_LOGIC; key : in STD_LOGIC_VECTOR(7 downto 0); videoflag : out std_LOGIC; vga_pos : out STD_LOGIC_VECTOR(15 downto 0); vga_char : out STD_LOGIC_VECTOR(15 downto 0); Ponto : out STD_LOGIC_VECTOR(2 downto 0); halt_ack : out std_LOGIC; halt_req : in std_LOGIC; PC_data : out STD_LOGIC_VECTOR(15 downto 0); break : out STD_LOGIC ); end cpu; ARCHITECTURE main of cpu is TYPE STATES is (fetch, decode, exec, halted); -- Estados da Maquina de Controle do Processador TYPE Registers is array(0 to 7) of STD_LOGIC_VECTOR(15 downto 0); -- Banco de Registradores TYPE LoadRegisters is array(0 to 7) of std_LOGIC; -- Sinais de LOAD dos Registradores do Banco -- INSTRUCTION SET: 29 INSTRUCTIONS -- Data Manipulation Instructions: -- Usage -- Action -- Format CONSTANT LOAD : STD_LOGIC_VECTOR(5 downto 0) := "110000"; -- LOAD RX END -- RX <- M[END] Format: < inst(6) | RX(3) | xxxxxxx > + 16bit END CONSTANT STORE : STD_LOGIC_VECTOR(5 downto 0) := "110001"; -- STORE END RX -- M[END] <- RX Format: < inst(6) | RX(3) | xxxxxxx > + 16bit END CONSTANT LOADIMED : STD_LOGIC_VECTOR(5 downto 0) := "111000"; -- LOADN RX Nr -- RX <- Nr Format: < inst(6) | RX(3) | xxxxxxb0 > + 16bit Numero CONSTANT LOADINDEX : STD_LOGIC_VECTOR(5 downto 0) := "111100"; -- LOADI RX RY -- RX <- M[RY] Format: < inst(6) | RX(3) | RY(3) | xxxx > CONSTANT STOREINDEX : STD_LOGIC_VECTOR(5 downto 0) := "111101"; -- STOREI RX RY -- M[RX] <- RY Format: < inst(6) | RX(3) | RY(3) | xxxx > CONSTANT MOV : STD_LOGIC_VECTOR(5 downto 0) := "110011"; -- MOV RX RY -- RX <- RY Format: < inst(6) | RX(3) | RY(3) | xx | x0 > -- MOV RX SP RX <- SP Format: < inst(6) | RX(3) | xxx | xx | 01 > -- MOV SP RX SP <- RX Format: < inst(6) | RX(3) | xxx | xx | 11 > -- I/O Instructions: CONSTANT OUTCHAR : STD_LOGIC_VECTOR(5 downto 0) := "110010"; -- OUTCHAR RX RY -- Video[RY] <- Char(RX) Format: < inst(6) | RX(3) | RY(3) | xxxx > -- RX contem o codigo do caracter de 0 a 127, sendo que 96 iniciais estao prontos com a tabela ASCII -- RX(6 downto 0) + 32 = Caractere da tabela ASCII - Ver Manual PDF -- RX(10 downto 7) = Cor : 0-branco, 1-marrom, 2-verde, 3-oliva, 4-azul marinho, 5-roxo, 6-teal, 7-prata, 8-cinza, 9-vermelho, 10-lima, 11-amarelo, 12-azul, 13-rosa, 14-aqua, 15-preto -- RY(10 downto 0) = tamanho da tela = 30 linhas x 40 colunas: posicao continua de 0 a 1199 no RY CONSTANT INCHAR : STD_LOGIC_VECTOR(5 downto 0) := "110101"; -- INCHAR RX -- RX[5..0] <- KeyPressed RX[15..6] <- 0's Format: < inst(6) | RX(3) | xxxxxxx > -- Se nao pressionar nenhuma tecla, RX recebe 00FF CONSTANT ARITH : STD_LOGIC_VECTOR(1 downto 0) := "10"; -- Aritmethic Instructions(All should begin wiht "10"): CONSTANT ADD : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- ADD RX RY RZ / ADDC RX RY RZ -- RX <- RY + RZ / RX <- RY + RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C > CONSTANT SUB : STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- SUB RX RY RZ / SUBC RX RY RZ -- RX <- RY - RZ / RX <- RY - RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C > CONSTANT MULT : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- MUL RX RY RZ / MUL RX RY RZ -- RX <- RY * RZ / RX <- RY * RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C > CONSTANT DIV : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- DIV RX RY RZ -- RX <- RY / RZ / RX <- RY / RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C > CONSTANT INC : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- INC RX / DEC RX -- RX <- RX + 1 / RX <- RX - 1 -- b6= INC/DEC : 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx > CONSTANT LMOD : STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- MOD RX RY RZ -- RX <- RY MOD RZ Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x > CONSTANT LOGIC : STD_LOGIC_VECTOR(1 downto 0) := "01"; -- LOGIC Instructions (All should begin wiht "01"): CONSTANT LAND : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- AND RX RY RZ -- RZ <- RX AND RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x > CONSTANT LOR : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- OR RX RY RZ -- RZ <- RX OR RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x > CONSTANT LXOR : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- XOR RX RY RZ -- RZ <- RX XOR RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x > CONSTANT LNOT : STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- NOT RX RY -- RX <- NOT(RY) Format: < inst(6) | RX(3) | RY(3) | xxxx > CONSTANT SHIFT : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- SHIFTL0 RX,n / SHIFTL1 RX,n / SHIFTR0 RX,n / SHIFTR1 RX,n / ROTL RX,n / ROTR RX,n -- SHIFT/Rotate RX -- b6=shif/rotate: 0/1 b5=left/right: 0/1; b4=fill; -- Format: < inst(6) | RX(3) | b6 b5 b4 | nnnn > CONSTANT CMP : STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- CMP RX RY -- Compare RX and RY and set FR : Format: < inst(6) | RX(3) | RY(3) | xxxx > Flag Register: <...DIVbyZero|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater> -- JMP Condition: (UNconditional, EQual, Not Equal, Zero, Not Zero, CarRY, Not CarRY, GReater, LEsser, Equal or Greater, Equal or Lesser, OVerflow, Not OVerflow, Negative, DIVbyZero, NOT USED) -- FLOW CONTROL Instructions: CONSTANT JMP : STD_LOGIC_VECTOR(5 downto 0) := "000010"; -- JMP END -- PC <- 16bit END : b9-b6 = COND Format: < inst(6) | COND(4) | xxxxxx > + 16bit END CONSTANT CALL : STD_LOGIC_VECTOR(5 downto 0) := "000011"; -- CALL END -- M[SP] <- PC | SP-- | PC <- 16bit END : b9-b6 = COND Format: < inst(6) | COND(4) | xxxxxx > + 16bit END CONSTANT RTS : STD_LOGIC_VECTOR(5 downto 0) := "000100"; -- RTS -- SP++ | PC <- M[SP] | b6=RX/FR: 1/0 Format: < inst(6) | xxxxxxxxxx > CONSTANT PUSH : STD_LOGIC_VECTOR(5 downto 0) := "000101"; -- PUSH RX / PUSH FR -- M[SP] <- RX / M[SP] <- FR | SP-- : b6=RX/FR: 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx > CONSTANT POP : STD_LOGIC_VECTOR(5 downto 0) := "000110"; -- POP RX / POP FR -- SP++ | RX <- M[SP] / FR <- M[SP] : b6=RX/FR: 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx > -- Control Instructions: CONSTANT NOP : STD_LOGIC_VECTOR(5 downto 0) := "000000"; -- NOP -- Do Nothing Format: < inst(6) | xxxxxxxxxx > CONSTANT HALT : STD_LOGIC_VECTOR(5 downto 0) := "001111"; -- HALT -- StOP Here Format: < inst(6) | xxxxxxxxxx > CONSTANT SETC : STD_LOGIC_VECTOR(5 downto 0) := "001000"; -- CLEARC / SETC -- Set/Clear CarRY: b9 = 1-set; 0-clear Format: < inst(6) | b9 | xxxxxxxxx > CONSTANT BREAKP : STD_LOGIC_VECTOR(5 downto 0) := "001110"; -- BREAK POINT -- Switch to manual clock Format: < inst(6) | xxxxxxxxxx > -- CONSTANTes para controle do Mux2: Estes sinais selecionam as respectivas entradas para o Mux2 CONSTANT sULA : STD_LOGIC_VECTOR (2 downto 0) := "000"; CONSTANT sMem : STD_LOGIC_VECTOR (2 downto 0) := "001"; CONSTANT sM4 : STD_LOGIC_VECTOR (2 downto 0) := "010"; CONSTANT sTECLADO : STD_LOGIC_VECTOR (2 downto 0) := "011"; -- nao tinha CONSTANT sSP : STD_LOGIC_VECTOR (2 downto 0) := "100"; -- Sinais para o Processo da ULA signal OP : STD_LOGIC_VECTOR(6 downto 0); -- OP(6) deve ser setado para OPeracoes com carRY signal x, y, result : STD_LOGIC_VECTOR(15 downto 0); signal FR : STD_LOGIC_VECTOR(15 downto 0); -- Flag Register: <...DIVbyZero|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater> signal auxFR : STD_LOGIC_VECTOR(15 downto 0); -- Representa um barramento conectando a ULA ao Mux6 para escrever no FR begin -- Maquina de Controle process(clk, reset) --Register Declaration: variable PC : STD_LOGIC_VECTOR(15 downto 0); -- Program Counter variable IR : STD_LOGIC_VECTOR(15 downto 0); -- Instruction Register variable SP : STD_LOGIC_VECTOR(15 downto 0); -- Stack Pointer variable MAR : STD_LOGIC_VECTOR(15 downto 0); -- Memory address Register VARIABLE TECLADO :STD_LOGIC_VECTOR(15 downto 0); -- Registrador para receber dados do teclado -- nao tinha variable reg : Registers; -- Mux dos barramentos de dados internos VARIABLE M2 :STD_LOGIC_VECTOR(15 downto 0); -- Mux dos barramentos de dados internos para os Registradores VARIABLE M3, M4 :STD_LOGIC_VECTOR(15 downto 0); -- Mux dos Registradores para as entradas da ULA -- Novos Sinais da Versao 2: Controle dos registradores internos (Load-Inc-Dec) variable LoadReg : LoadRegisters; variable LoadIR : std_LOGIC; variable LoadMAR : std_LOGIC; variable LoadPC : std_LOGIC; variable IncPC : std_LOGIC; VARIABLE LoadSP : STD_LOGIC; variable IncSP : std_LOGIC; variable DecSP : std_LOGIC; -- Selecao dos Mux 2 e 6 variable selM2 : STD_LOGIC_VECTOR(2 downto 0); variable selM6 : STD_LOGIC_VECTOR(2 downto 0); VARIABLE BreakFlag : STD_LOGIC; -- Para sinalizar a mudanca para Clock manual/Clock Automatico para a nova instrucao Break variable state : STATES; -- Estados do processador: fetch, decode, exec, halted -- Seletores dos registradores para execussao das instrucoes variable RX : integer; variable RY : integer; variable RZ : integer; begin if(reset = '1') then state := fetch; -- inicializa o estado na busca! M1(15 downto 0) <= x"0000"; -- inicializa na linha Zero da memoria -> Programa tem que comecar na linha Zero !! videoflag <= '0'; RX := 0; RY := 0; RZ := 0; RW <= '0'; LoadIR := '0'; LoadMAR := '0'; LoadPC := '0'; IncPC := '0'; IncSP := '0'; DecSP := '0'; selM2 := sMem; selM6 := sULA; LoadReg(0) := '0'; LoadReg(1) := '0'; LoadReg(2) := '0'; LoadReg(3) := '0'; LoadReg(4) := '0'; LoadReg(5) := '0'; LoadReg(6) := '0'; LoadReg(7) := '0'; REG(0) := x"0000"; REG(1) := x"0000"; REG(2) := x"0000"; REG(3) := x"0000"; REG(4) := x"0000"; REG(5) := x"0000"; REG(6) := x"0000"; REG(7) := x"0000"; PC := x"0000"; -- inicializa na linha Zero da memoria -> Programa tem que comecar na linha Zero !! SP := x"7f00"; -- Inicializa a Pilha no final da mem�ria: 7ffc IR := x"0000"; MAR := x"0000"; BreakFlag:= '0'; -- Break Point Flag BREAK <= '0'; -- Break Point output to switch to manual clock -- Novo na Versao 3 HALT_ack <= '0'; elsif(clk'event and clk = '1') then if(LoadIR = '1') then IR := Mem; end if; if(LoadPC = '1') then PC := Mem; end if; if(IncPC = '1') then PC := PC + x"0001"; end if; if(LoadMAR = '1') then MAR := Mem; end if; if(LoadSP = '1') then SP := M3; end if; if(IncSP = '1') then SP := SP + x"0001"; end if; if(DecSP = '1') then SP := SP - x"0001"; end if; -- Selecao do Mux6 if (selM6 = sULA) THEN FR <= auxFR; -- Sempre recebe flags da ULA ELSIF (selM6 = sMem) THEN FR <= Mem; END IF; -- A menos que seja POP FR, quando recebe da Memoria -- Atualiza o nome dos registradores!!! RX := conv_integer(IR(9 downto 7)); RY := conv_integer(IR(6 downto 4)); RZ := conv_integer(IR(3 downto 1)); -- Selecao do Mux2 if (selM2 = sULA) THEN M2 := RESULT; ELSIF (selM2 = sMem) THEN M2 := Mem; ELSIF (selM2 = sM4) THEN M2 := M4; ELSIF (selM2 = sTECLADO)THEN M2 := TECLADO; ELSIF (selM2 = sSP) THEN M2 := SP; END IF; -- Carrega dados do Mux 2 para os registradores if(LoadReg(RX) = '1') then reg(RX) := M2; end if; -- Reseta os sinais de controle APOS usa-los acima -- Zera todos os sinais de controle, para depois ligar um por um nas instrucoes a medida que for necessario: a ultima atribuicao e' a que vale no processo!!! LoadIR := '0'; LoadMAR := '0'; LoadPC := '0'; IncPC := '0'; IncSP := '0'; DecSP := '0'; LoadSP := '0'; selM6 := sULA; -- Sempre atualiza o FR da ULA, a nao ser que a instrucao seja POP FR LoadReg(0) := '0'; LoadReg(1) := '0'; LoadReg(2) := '0'; LoadReg(3) := '0'; LoadReg(4) := '0'; LoadReg(5) := '0'; LoadReg(6) := '0'; LoadReg(7) := '0'; videoflag <= '0'; -- Abaixa o sinal para a "Placa de Video" : sobe a cada OUTCHAR RW <= '0'; -- Sinal de Letura/Ecrita da mem�ria em Leitura -- Novo na Versao 3 if(halt_req = '1') then state := halted; end if; -- Novo na Versao 3: para escrever PC no LCD da placa PC_data <= PC; case state is --************************************************************************ -- FETCH STATE --************************************************************************ when fetch => PONTO <= "001"; -- Inicio das acoes do ciclo de Busca !! M1 <= PC; RW <= '0'; LoadIR := '1'; IncPC := '1'; STATE := decode; -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX --************************************************************************ -- DECODE STATE --************************************************************************ when decode => PONTO <= "010"; --======================================================================== -- INCHAR RX[7..0] <- KeyPressed RX[15..8] <- 0 --======================================================================== IF(IR(15 DOWNTO 10) = INCHAR) THEN -- Se nenhuma tecla for pressionada no momento da leitura, Rx <- x"00FF" TECLADO(7 downto 0) := key(7 downto 0); TECLADO(15 downto 8) := X"00"; selM2 := sTECLADO; LoadReg(RX) := '1'; state := fetch; END IF; --======================================================================== -- OUTCHAR Video[RY] <- Char(RX) --======================================================================== IF(IR(15 DOWNTO 10) = OUTCHAR) THEN M3 := Reg(Rx); -- M3 <- Rx M4 := Reg(Ry); -- M4 <- Ry -- Este bloco troca a cor do preto pelo branco: agora a cor "0000" = Branco ! if( M3(11 downto 8) = "0000" ) then M3(11 downto 8) := "1111"; elsif( M3(11 downto 8) = "1111" ) then M3(11 downto 8) := "0000"; end if; vga_char <= M3; --vga_char <= M3 : C�digo do Character vem do Rx via M3 vga_pos <= M4; -- Posicao na tela do Character vem do Ry via M4 videoflag <= '1'; -- Sobe o videoflag para gravar o charactere na mem�ria de video state := fetch; END IF; --======================================================================== -- MOV RX/SP <- RY/SP -- MOV RX RY RX <- RY Format: < inst(6) | RX(3) | RY(3) | xx | x0 > -- MOV RX SP RX <- SP Format: < inst(6) | RX(3) | xxx | xx | 01 > -- MOV SP RX SP <- RX Format: < inst(6) | RX(3) | xxx | xx | 11 > --======================================================================== IF(IR(15 DOWNTO 10) = MOV) THEN state := fetch; END IF; --======================================================================== -- STORE DIReto M[END] <- RX --======================================================================== IF(IR(15 DOWNTO 10) = STORE) THEN -- Busca o endereco state := exec; -- Vai para o estado de Executa para gravar Registrador no endereco END IF; --======================================================================== -- STORE indexado por registrador M[RX] <- RY --======================================================================== IF(IR(15 DOWNTO 10) = STOREINDEX) THEN state := fetch; END IF; --======================================================================== -- LOAD Direto RX <- M[End] --======================================================================== IF(IR(15 DOWNTO 10) = LOAD) THEN -- Busca o endereco state := exec; -- Vai para o estado de Executa para buscar o dado do endereco END IF; --======================================================================== -- LOAD Imediato RX <- Nr --======================================================================== IF(IR(15 DOWNTO 10) = LOADIMED) THEN M1 <= PC; -- M1 <- PC Rw <= '0'; -- Rw <= '0' selM2 := sMeM; -- M2 <- MEM LoadReg(RX) := '1'; -- LRx <- 1 IncPC := '1'; -- IncPC <- 1 state := fetch; END IF; --======================================================================== -- LOAD Indexado por registrador RX <- M(RY) --======================================================================== IF(IR(15 DOWNTO 10) = LOADINDEX) THEN state := fetch; END IF; --======================================================================== -- LOGIC OPERATION ('SHIFT', and 'CMP' NOT INCLUDED) RX <- RY (?) RZ --======================================================================== IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) /= SHIFT AND IR(13 DOWNTO 10) /= CMP) THEN state := fetch; END IF; --======================================================================== -- CMP RX, RY --======================================================================== IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) = CMP) THEN state := fetch; END IF; --======================================================================== -- SHIFT RX, RY RX <- SHIFT[ RY] ROTATE INCluded ! --======================================================================== IF(IR(15 DOWNTO 14) = LOGIC and (IR(13 DOWNTO 10) = SHIFT)) THEN if(IR(6 DOWNTO 4) = "000") then -- SHIFT LEFT 0 Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))sll conv_integer(IR(3 DOWNTO 0))); elsif(IR(6 DOWNTO 4) = "001") then -- SHIFT LEFT 1 Reg(RX) := not (To_StdLOGICVector(to_bitvector(not Reg(RY))sll conv_integer(IR(3 DOWNTO 0)))); elsif(IR(6 DOWNTO 4) = "010") then -- SHIFT RIGHT 0 Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))srl conv_integer(IR(3 DOWNTO 0))); elsif(IR(6 DOWNTO 4) = "011") then -- SHIFT RIGHT 0 Reg(RX) := not (To_StdLOGICVector(to_bitvector(not Reg(RY))srl conv_integer(IR(3 DOWNTO 0)))); elsif(IR(6 DOWNTO 5) = "11") then -- ROTATE RIGHT Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))ror conv_integer(IR(3 DOWNTO 0))); elsif(IR(6 DOWNTO 5) = "10") then -- ROTATE LEFT Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))rol conv_integer(IR(3 DOWNTO 0))); end if; state := fetch; end if; --======================================================================== -- JMP END PC <- 16bit END : b9-b6 = COND -- Flag Register: <...Negative|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater> -- JMP Condition: (UNconditional, EQual, Not Equal, Zero, Not Zero, CarRY, Not CarRY, GReater, LEsser, Equal or Greater, Equal or Lesser, OVerflow, Not OVerflow, Negative, DIVbyZero, NOT USED) --======================================================================== IF(IR(15 DOWNTO 10) = JMP) THEN state := fetch; END IF; --======================================================================== -- PUSH RX --======================================================================== IF(IR(15 DOWNTO 10) = PUSH) THEN state := fetch; END IF; --======================================================================== -- POP RX --======================================================================== IF(IR(15 DOWNTO 10) = POP) THEN state := exec; END IF; --======================================================================== -- CALL END PC <- 16bit END : b9-b6 = COND PUSH(PC) -- Flag Register: <...Negative|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater> -- JMP Condition: (UNconditional, EQual, Not Equal, Zero, Not Zero, CarRY, Not CarRY, GReater, LEsser, Equal or Greater, Equal or Lesser, OVerflow, Not OVerflow, Negative, DIVbyZero, NOT USED) --======================================================================== IF(IR(15 DOWNTO 10) = CALL) THEN END IF; --======================================================================== -- RTS PC <- Mem[SP] --======================================================================== IF(IR(15 DOWNTO 10) = RTS) THEN state := exec; END IF; --======================================================================== -- ARITH OPERATION ('INC' NOT INCLUDED) RX <- RY (?) RZ --======================================================================== IF(IR(15 DOWNTO 14) = ARITH AND IR(13 DOWNTO 10) /= INC) THEN state := fetch; END IF; --======================================================================== -- INC/DEC RX <- RX (+ or -) 1 --======================================================================== IF(IR(15 DOWNTO 14) = ARITH AND IR(13 DOWNTO 10) = INC) THEN state := fetch; END IF; --======================================================================== -- NOP --======================================================================== IF( IR(15 DOWNTO 10) = NOP) THEN state := fetch; end if; --======================================================================== -- HALT --======================================================================== IF( IR(15 DOWNTO 10) = HALT) THEN state := halted; END IF; --======================================================================== -- SETC/CLEARC --======================================================================== IF( IR(15 DOWNTO 10) = SETC) THEN FR(4) <= IR(9); -- Bit 9 define se vai ser SET ou CLEAR state := fetch; end if; --======================================================================== -- BREAKP --======================================================================== IF( IR(15 DOWNTO 10) = BREAKP) THEN BreakFlag := not(BreakFlag); -- Troca entre clock manual e clock autom�tico BREAK <= BreakFlag; state := fetch; PONTO <= "101"; END IF; -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX --************************************************************************ -- EXECUTE STATE --************************************************************************ when exec => PONTO <= "100"; --======================================================================== -- EXEC STORE DIReto M[END] <- RX --======================================================================== IF(IR(15 DOWNTO 10) = STORE) THEN state := fetch; END IF; --======================================================================== -- EXEC LOAD DIReto RX <- M[END] --======================================================================== IF(IR(15 DOWNTO 10) = LOAD) THEN state := fetch; END IF; --======================================================================== -- EXEC POP RX/FR --======================================================================== IF(IR(15 DOWNTO 10) = POP) THEN state := fetch; END IF; --======================================================================== -- EXEC CALL Pilha <- PC e PC <- 16bit END : --======================================================================== IF(IR(15 DOWNTO 10) = CALL) THEN state := fetch; END IF; --======================================================================== -- EXEC RTS PC <- Mem[SP] --======================================================================== IF(IR(15 DOWNTO 10) = RTS) THEN state := fetch; END IF; -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX --************************************************************************ -- HALT STATE --************************************************************************ WHEN halted => PONTO <= "111"; state := halted; halt_ack <= '1'; WHEN OTHERS => state := fetch; videoflag <= '0'; PONTO <= "000"; END CASE; end if; end process; --************************************************************************ -- ULA ---> 3456 (3042) --************************************************************************ PROCESS (OP, X, Y, reset) VARIABLE AUX : STD_LOGIC_VECTOR(15 downto 0); VARIABLE RESULT32 : STD_LOGIC_VECTOR(31 downto 0); BEGIN IF (reset = '1') THEN auxFR <= x"0000"; RESULT <= x"0000"; else auxFR <= FR; --======================================================================== -- ARITH --======================================================================== IF (OP (5 downto 4) = ARITH) THEN CASE OP (3 downto 0) IS WHEN ADD => IF (OP(6) = '1') THEN --Soma com carRY AUX := X + Y + FR(4); RESULT32 := (x"00000000" + X + Y + FR(4)); ELSE --Soma sem carRY AUX := X + Y; RESULT32 := (x"00000000" + X + Y); end if; if(RESULT32 > "01111111111111111") THEN -- CarRY auxFR(4) <= '1'; ELSE auxFR(4) <= '0'; end if; WHEN SUB => AUX := X - Y; WHEN MULT => RESULT32 := X * Y; AUX := RESULT32(15 downto 0); if(RESULT32 > x"0000FFFF") THEN -- ARITHmetic Overflow auxFR(5) <= '1'; ELSE auxFR(5) <= '0'; end if; WHEN DIV => IF(Y = x"0000") THEN AUX := x"0000"; auxFR(6) <= '1'; -- DIV by Zero ELSE AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X)/CONV_INTEGER(Y), 16); auxFR(6) <= '0'; END IF; WHEN LMOD => IF(Y = x"0000") THEN AUX := x"0000"; auxFR(6) <= '1'; -- DIV by Zero ELSE AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X) mod CONV_INTEGER(Y), 16); auxFR(6) <= '0'; END IF; WHEN others => -- invalid operation, defaults to nothing AUX := X; END CASE; if(AUX = x"0000") THEN auxFR(3) <= '1'; -- FR = <...|zero|equal|lesser|greater> ELSE auxFR(3) <= '0'; -- FR = <...|zero|equal|lesser|greater> end if; if(AUX < x"0000") THEN -- NEGATIVO auxFR(9) <= '1'; ELSE auxFR(9) <= '0'; end if; RESULT <= AUX; ELSIF (OP (5 downto 4) = LOGIC) THEN IF (OP (3 downto 0) = CMP) THEN result <= x; IF (x > y) THEN auxFR(2 downto 0) <= "001"; -- FR = <...|zero|equal|lesser|greater> ELSIF (x < y) THEN auxFR(2 downto 0) <= "010"; -- FR = <...|zero|equal|lesser|greater> ELSIF (x = y) THEN auxFR(2 downto 0) <= "100"; -- FR = <...|zero|equal|lesser|greater> END IF; ELSE CASE OP (3 downto 0) IS WHEN LAND => result <= x and y; WHEN LXOR => result <= x xor y; WHEN LOR => result <= x or y; WHEN LNOT => result <= not x; WHEN others => -- invalid operation, defaults to nothing RESULT <= X; END CASE; if(result = x"0000") THEN auxFR(3) <= '1'; -- FR = <...|zero|equal|lesser|greater> ELSE auxFR(3) <= '0'; -- FR = <...|zero|equal|lesser|greater> end if; END IF; END IF; END IF; -- Reset END PROCESS; end main;
gpl-3.0
b4c6004ad215186cf6c96a3dd65d9890
0.46685
3.507263
false
false
false
false
simoesusp/Processador-ICMC
Processor_FPGA/Processor_Template_VHDL_DE70/debounce.vhd
3
697
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; ENTITY debounce IS PORT(pb, clock_100Hz : IN STD_LOGIC; pb_debounced : OUT STD_LOGIC); END debounce; ARCHITECTURE a OF debounce IS SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN -- Debounce Button: Filters out mechanical switch bounce for around 40Ms. -- Debounce clock should be approximately 10ms process begin wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1'); SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); SHIFT_PB(3) <= PB; If SHIFT_PB(3 Downto 0)="0000" THEN PB_DEBOUNCED <= '0'; ELSE PB_DEBOUNCED <= '1'; End if; end process; end a;
gpl-3.0
2c4b4d0e6bf30b502360764994655df6
0.6901
2.95339
false
false
false
false
simoesusp/Processador-ICMC
Processor_FPGA/Processor_Template_VHDL_DE70/REG2.vhd
3
726
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; ENTITY REG2 IS PORT( CLK : IN STD_LOGIC; CLR : IN STD_LOGIC; LID : IN STD_LOGIC_VECTOR(2 DOWNTO 0); I : IN STD_LOGIC_VECTOR(15 DOWNTO 0); O : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END REG2; ARCHITECTURE main OF REG2 IS BEGIN PROCESS(CLK, CLR) VARIABLE DATA : STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN IF(CLR = '1') THEN DATA := x"0000"; O <= x"0000"; ELSIF(CLK'EVENT AND CLK = '1') THEN IF(LID(0) = '1') THEN DATA := I; ELSIF(LID(1) = '1') THEN DATA := DATA + x"1"; ELSIF(LID(2) = '1') THEN DATA := DATA - x"1"; END IF; END IF; O <= DATA; END PROCESS; END main;
gpl-3.0
8129fb1fadcb1f8753300588996fcdb5
0.603306
2.512111
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/RTL/NI_Test/Router_32_bit_credit_based_packet_drop_classifier_SHMU.vhd
3
21,940
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; --use IEEE.STD_LOGIC_ARITH.ALL; --use IEEE.STD_LOGIC_UNSIGNED.ALL; entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping generic ( DATA_WIDTH: integer := 32; current_address : integer := 0; Rxy_rst : integer := 10; Cx_rst : integer := 10; healthy_counter_threshold : integer := 8; faulty_counter_threshold: integer := 2; counter_depth: integer := 4; NoC_size: integer := 4 ); port ( reset, clk: in std_logic; RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0); credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic; valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic; valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic; credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic; TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0); Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic; Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic; -- should be connected to NI link_faults: out std_logic_vector(4 downto 0); turn_faults: out std_logic_vector(19 downto 0); Rxy_reconf_PE: in std_logic_vector(7 downto 0); Cx_reconf_PE: in std_logic_vector(3 downto 0); Reconfig_command : in std_logic ); end router_credit_based_PD_C_SHMU; architecture behavior of router_credit_based_PD_C_SHMU is COMPONENT FIFO_credit_based is generic ( DATA_WIDTH: integer := 32 ); port ( reset: in std_logic; clk: in std_logic; RX: in std_logic_vector(DATA_WIDTH-1 downto 0); valid_in: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; credit_out: out std_logic; empty_out: out std_logic; Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0); fault_info, health_info: out std_logic ); end COMPONENT; COMPONENT counter_threshold_classifier is generic ( counter_depth: integer := 8; healthy_counter_threshold: integer := 4; faulty_counter_threshold: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; faulty_packet, Healthy_packet: in std_logic; Healthy, intermittent, Faulty: out std_logic ); end COMPONENT; COMPONENT allocator is port ( reset: in std_logic; clk: in std_logic; -- flow control credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic; req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic; req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic; req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic; req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic; req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic; empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic; -- grant_X_Y means the grant for X output port towards Y input port -- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot! valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic; grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic; grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic; grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic; grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic; grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic ); end COMPONENT; COMPONENT parity_checker_for_LBDR is generic(DATA_WIDTH : integer := 32); port( RX: in std_logic_vector(DATA_WIDTH-1 downto 0); empty: in std_logic; faulty: out std_logic ); end COMPONENT; COMPONENT LBDR_packet_drop is generic ( cur_addr_rst: integer := 8; Rxy_rst: integer := 8; Cx_rst: integer := 8; NoC_size: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic; empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); dst_addr: in std_logic_vector(NoC_size-1 downto 0); faulty: in std_logic; packet_drop_order: out std_logic; grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic; Rxy_reconf_PE: in std_logic_vector(7 downto 0); Cx_reconf_PE: in std_logic_vector(3 downto 0); Reconfig_command : in std_logic ); end COMPONENT; COMPONENT XBAR is generic ( DATA_WIDTH: integer := 32 ); port ( North_in: in std_logic_vector(DATA_WIDTH-1 downto 0); East_in: in std_logic_vector(DATA_WIDTH-1 downto 0); West_in: in std_logic_vector(DATA_WIDTH-1 downto 0); South_in: in std_logic_vector(DATA_WIDTH-1 downto 0); Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0); sel: in std_logic_vector (4 downto 0); Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0) ); end COMPONENT; signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0); -- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic; signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic; signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic; signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic; signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic; signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic; signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic; signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic; signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic; signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic; signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic; signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0); signal LBDR_Fault_N, LBDR_Fault_E, LBDR_Fault_W, LBDR_Fault_S, LBDR_Fault_L: std_logic; signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic; signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic; signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic; signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic; signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic; signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic; begin turn_faults <= "00000000000000000000"; link_faults <= sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L; --link_faults <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L; Faulty_N_out <= sig_Faulty_N_out; Faulty_E_out <= sig_Faulty_E_out; Faulty_W_out <= sig_Faulty_W_out; Faulty_S_out <= sig_Faulty_S_out; -- all the counter_threshold modules CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N, Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out); CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E, Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out); CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W, Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out); CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S, Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out); CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L, Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L); -- all the FIFOs FIFO_N: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N, read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN, credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N); FIFO_E: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E, read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE, credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E); FIFO_W: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W, read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW, credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W); FIFO_S: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S, read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS, credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S); FIFO_L: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L, read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L, credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ parity_LBDR_N: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_N, empty_N, LBDR_Fault_N); parity_LBDR_E: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_E, empty_E, LBDR_Fault_E); parity_LBDR_W: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_W, empty_W, LBDR_Fault_W); parity_LBDR_S: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_S, empty_S, LBDR_Fault_S); parity_LBDR_L: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_L, empty_L, LBDR_Fault_L); --- all the LBDRs LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_N, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(NoC_size downto 1) , faulty => LBDR_Fault_N, packet_drop_order => packet_drop_order_N, grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN, Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command); LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_E, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(NoC_size downto 1) , faulty => LBDR_Fault_E, packet_drop_order => packet_drop_order_E, grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE, Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command); LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_W, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(NoC_size downto 1) , faulty => LBDR_Fault_W, packet_drop_order => packet_drop_order_W, grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW, Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command); LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_S, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(NoC_size downto 1) , faulty => LBDR_Fault_S, packet_drop_order => packet_drop_order_S, grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS, Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command); LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_L, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(NoC_size downto 1) , faulty => LBDR_Fault_L, packet_drop_order => packet_drop_order_L, grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0', Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- switch allocator allocator_unit: allocator port map ( reset => reset, clk => clk, -- flow control credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L, -- requests from the LBDRS req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL, req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL, req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL, req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL, req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0', empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L, valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L, -- grant_X_Y means the grant for X output port towards Y input port -- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot! grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL, grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL, grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL, grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL, grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Xbar select_signals Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL; Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL; Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL; Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL; Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0'; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Xbars XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_N, Data_out=> TX_N); XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_E, Data_out=> TX_E); XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_W, Data_out=> TX_W); XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_S, Data_out=> TX_S); XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_L, Data_out=> TX_L); end;
gpl-3.0
6f6847f4224704d723ad4b720d58501d
0.569553
3.04934
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/ScanMux.vhd
3
994
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ScanMux is Generic (ControlSize : positive := 3); Port ( ScanMux_in : in STD_LOGIC_VECTOR((2**ControlSize)-1 downto 0); SelectedBy : in STD_LOGIC_VECTOR(ControlSize-1 downto 0); ScanMux_out : out STD_LOGIC); end ScanMux; architecture ScanMux_arch of ScanMux is signal internal_connections: std_logic_vector((2**(ControlSize+1))-2 downto 0); begin internal_connections((2**ControlSize)-1 downto 0) <= ScanMux_in; mux_network: for i in 0 to ControlSize-1 generate mux_layer: for j in 0 to 2**(ControlSize-1-i)-1 generate internal_connections((2**(ControlSize+1))-(2**(ControlSize-i))+j) <= internal_connections((2**(ControlSize+1))-(2**(ControlSize+1-i))+2*j+1) when SelectedBy(i) = '1' else internal_connections((2**(ControlSize+1))-(2**(ControlSize+1-i))+2*j+0); end generate; end generate; ScanMux_out <= internal_connections((2**(ControlSize+1))-2); end ScanMux_arch;
gpl-3.0
2f5e622ac2d43c5fdb66181a59e46eff
0.673038
3.451389
false
false
false
false
domagalski/pocketcorr
fpga/snap/fft_2048ch_6a_core.vhd
1
4,837
-- Generated from Simulink block library IEEE; use IEEE.std_logic_1164.all; library xil_defaultlib; use xil_defaultlib.conv_pkg.all; entity fft_2048ch_6a_core_ip is port ( pol0_in0 : in std_logic_vector( 18-1 downto 0 ); pol0_in1 : in std_logic_vector( 18-1 downto 0 ); pol1_in0 : in std_logic_vector( 18-1 downto 0 ); pol1_in1 : in std_logic_vector( 18-1 downto 0 ); pol2_in0 : in std_logic_vector( 18-1 downto 0 ); pol2_in1 : in std_logic_vector( 18-1 downto 0 ); pol3_in0 : in std_logic_vector( 18-1 downto 0 ); pol3_in1 : in std_logic_vector( 18-1 downto 0 ); pol4_in0 : in std_logic_vector( 18-1 downto 0 ); pol4_in1 : in std_logic_vector( 18-1 downto 0 ); pol5_in0 : in std_logic_vector( 18-1 downto 0 ); pol5_in1 : in std_logic_vector( 18-1 downto 0 ); shift : in std_logic_vector( 16-1 downto 0 ); sync : in std_logic_vector( 32-1 downto 0 ); clk : in std_logic; out0 : out std_logic_vector( 36-1 downto 0 ); out1 : out std_logic_vector( 36-1 downto 0 ); out2 : out std_logic_vector( 36-1 downto 0 ); out3 : out std_logic_vector( 36-1 downto 0 ); out4 : out std_logic_vector( 36-1 downto 0 ); out5 : out std_logic_vector( 36-1 downto 0 ); overflow : out std_logic_vector( 6-1 downto 0 ); sync_out : out std_logic_vector( 1-1 downto 0 ) ); end fft_2048ch_6a_core_ip; -- Generated from Simulink block library IEEE; use IEEE.std_logic_1164.all; library xil_defaultlib; use xil_defaultlib.conv_pkg.all; entity fft_2048ch_6a_core_ip_struct is port ( pol0_in0 : in std_logic_vector( 18-1 downto 0 ); pol0_in1 : in std_logic_vector( 18-1 downto 0 ); pol1_in0 : in std_logic_vector( 18-1 downto 0 ); pol1_in1 : in std_logic_vector( 18-1 downto 0 ); pol2_in0 : in std_logic_vector( 18-1 downto 0 ); pol2_in1 : in std_logic_vector( 18-1 downto 0 ); pol3_in0 : in std_logic_vector( 18-1 downto 0 ); pol3_in1 : in std_logic_vector( 18-1 downto 0 ); pol4_in0 : in std_logic_vector( 18-1 downto 0 ); pol4_in1 : in std_logic_vector( 18-1 downto 0 ); pol5_in0 : in std_logic_vector( 18-1 downto 0 ); pol5_in1 : in std_logic_vector( 18-1 downto 0 ); shift : in std_logic_vector( 16-1 downto 0 ); sync : in std_logic_vector( 32-1 downto 0 ); clk_1 : in std_logic; ce_1 : in std_logic; out0 : out std_logic_vector( 36-1 downto 0 ); out1 : out std_logic_vector( 36-1 downto 0 ); out2 : out std_logic_vector( 36-1 downto 0 ); out3 : out std_logic_vector( 36-1 downto 0 ); out4 : out std_logic_vector( 36-1 downto 0 ); out5 : out std_logic_vector( 36-1 downto 0 ); overflow : out std_logic_vector( 6-1 downto 0 ); sync_out : out std_logic_vector( 1-1 downto 0 ) ); end fft_2048ch_6a_core_ip_struct; architecture structural of fft_2048ch_6a_core_ip_struct is component fft_2048ch_6a_core_ip port ( pol0_in0 : in std_logic_vector( 18-1 downto 0 ); pol0_in1 : in std_logic_vector( 18-1 downto 0 ); pol1_in0 : in std_logic_vector( 18-1 downto 0 ); pol1_in1 : in std_logic_vector( 18-1 downto 0 ); pol2_in0 : in std_logic_vector( 18-1 downto 0 ); pol2_in1 : in std_logic_vector( 18-1 downto 0 ); pol3_in0 : in std_logic_vector( 18-1 downto 0 ); pol3_in1 : in std_logic_vector( 18-1 downto 0 ); pol4_in0 : in std_logic_vector( 18-1 downto 0 ); pol4_in1 : in std_logic_vector( 18-1 downto 0 ); pol5_in0 : in std_logic_vector( 18-1 downto 0 ); pol5_in1 : in std_logic_vector( 18-1 downto 0 ); shift : in std_logic_vector( 16-1 downto 0 ); sync : in std_logic_vector( 32-1 downto 0 ); clk : in std_logic; out0 : out std_logic_vector( 36-1 downto 0 ); out1 : out std_logic_vector( 36-1 downto 0 ); out2 : out std_logic_vector( 36-1 downto 0 ); out3 : out std_logic_vector( 36-1 downto 0 ); out4 : out std_logic_vector( 36-1 downto 0 ); out5 : out std_logic_vector( 36-1 downto 0 ); overflow : out std_logic_vector( 6-1 downto 0 ); sync_out : out std_logic_vector( 1-1 downto 0 ) ); end component; begin fft_2048ch_6a_core_ip_inst : fft_2048ch_6a_core_ip port map ( pol0_in0 => pol0_in0, pol0_in1 => pol0_in1, pol1_in0 => pol1_in0, pol1_in1 => pol1_in1, pol2_in0 => pol2_in0, pol2_in1 => pol2_in1, pol3_in0 => pol3_in0, pol3_in1 => pol3_in1, pol4_in0 => pol4_in0, pol4_in1 => pol4_in1, pol5_in0 => pol5_in0, pol5_in1 => pol5_in1, shift => shift , sync => sync , clk => clk_1 , out0 => out0 , out1 => out1 , out2 => out2 , out3 => out3 , out4 => out4 , out5 => out5 , overflow => overflow, sync_out => sync_out ); end structural;
gpl-3.0
6f336f567fd0c8e4b5805990d6944d57
0.605334
2.783084
false
false
false
false
ashtonchase/logic_analyzer
src/la_top.vhd
1
8,359
---------------------------------------------------------------------------- -- Title : Logic Analyzer Top Module -- Project : fpga_logic_analyzer ------------------------------------------------------------------------------- -- File : la_top.vhd -- Created : 2016-02-22 -- Last update: 2016-04-09 -- Standard : VHDL'08 ------------------------------------------------------------------------------- -- Description: This is the top instatiting modue of the logic analyzer. This -- will define the generic I/O interfaces to the system. Ideally, all modules -- below this will be portable to whatever your target hardware will be. -- -- Stucture: (incomplete) -- ----------- -- RX | UART | -- -----| | -- | | -- TX | | -- -----| | -- | | -- | | -- ----------- ------------------------------------------------------------------------------- -- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt ------------------------------------------------------------------------------- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-02-22 1.0 ashton Created -- 2016-03-09 1.1 ashton Added sample_storage_block and -- DATA_WIDTH and SAMPLE_DEPTH generics. -- 2016-04-?? 1.2 paul made integration updates. -- 2016-04-09 1.3 ashton updated sample rate block instantiation ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity la_top is generic ( BAUD_RATE : positive := 115_200; INPUT_CLK_RATE_HZ : positive range 10_000_000 to 200_000_000 := 100_000_000; DATA_WIDTH : positive range 1 to 32 := 8; SAMPLE_DEPTH : positive range 1 to 2**18 := 2**8); port ( --COMMON INTERFACES clk : in std_logic; --clock rst : in std_logic := '0'; --reset, (async high/ sync low) --data input. defaulte to zeroes so you don't have to hook all 32 lines up. din : in std_logic_vector(31 downto 0) := (others => '0'); --UART INTERFACES uart_rx : in std_logic; -- UART Receive Data uart_tx : out std_logic; -- UART Transmit Data armed : out std_logic; triggered : out std_logic; capture_rdy : out std_logic; --data_sent : out std_logic; command_ready : out std_logic; debug : out std_logic_vector(7 downto 0)); begin --entity-wide checks assert IS_X(clk) = false report "clk is undefined" severity error; assert IS_X(din) = false report "din is undefined" severity error; assert IS_X(uart_rx) = false report "uart_rx is undefined" severity error; end entity la_top; architecture structural of la_top is -- LA Control Signals signal rst_cmd : std_logic := '0'; signal arm_cmd : std_logic; signal id_cmd : std_logic; signal debug_cmd : std_logic; signal sample_enable : std_logic := '1'; signal sample_cnt_rst : std_logic; signal delay_cnt_4x : std_logic_vector(16-1 downto 0) := (others => '0'); signal read_cnt_4x : std_logic_vector(16-1 downto 0) := (others => '1'); signal par_trig_msk : std_logic_vector(32-1 downto 0) := (others => '0'); signal par_trig_val : std_logic_vector(32-1 downto 0) := (others => '1'); -- Input to Storage Signals signal in_fifo_tdata : std_logic_vector(31 downto 0); signal in_fifo_tvalid : std_logic; signal in_fifo_tlast : std_logic; signal in_fifo_tready : std_logic; signal in_fifo_tfull : std_logic; signal in_fifo_tempty : std_logic; signal in_fifo_tflush : std_logic; -- Output from Storage Signals signal out_fifo_tdata : std_logic_vector(7 downto 0); signal out_fifo_tvalid : std_logic; signal out_fifo_tlast : std_logic; signal out_fifo_tready : std_logic; -- Sump Comms Signals signal sump_byte : std_logic_vector(7 downto 0); signal command_ready_int : std_logic; signal data_sent : std_logic; -- Message Processing Signals signal sample_f : std_logic_vector(23 downto 0); signal armed_int : std_logic; begin -- ARCHITECTURE structural command_ready <= command_ready_int; debug <= sump_byte; capture_control_block : entity work.capture_ctrl generic map ( DATA_WIDTH => DATA_WIDTH) port map ( clk => clk, rst => rst, -- din => din(7 downto 0), armed => armed_int, triggered => triggered, id_cmd => id_cmd, rst_cmd => rst_cmd, arm_cmd => arm_cmd, debug_cmd => debug_cmd, sample_enable => sample_enable, sample_cnt_rst => sample_cnt_rst, delay_cnt_4x => delay_cnt_4x, read_cnt_4x => read_cnt_4x, par_trig_msk => par_trig_msk, par_trig_val => par_trig_val, capture_rdy => capture_rdy, -- FIX: NOT USED, don't need. message_processing will try. you determine if it will work -- fifo_tdata => in_fifo_tdata, fifo_tvalid => in_fifo_tvalid, fifo_tlast => in_fifo_tlast, fifo_tready => in_fifo_tready, fifo_tfull => in_fifo_tfull, fifo_tempty => in_fifo_tempty, fifo_aresetn => in_fifo_tflush); sample_storage_block : entity work.storage generic map ( FIFO_SIZE => SAMPLE_DEPTH) port map ( clk => clk, reset => rst, -- in_fifo_tdata => in_fifo_tdata, in_fifo_tvalid => in_fifo_tvalid, in_fifo_tlast => in_fifo_tlast, in_fifo_tready => in_fifo_tready, in_fifo_tfull => in_fifo_tfull, in_fifo_tempty => in_fifo_tempty, in_fifo_tflush => in_fifo_tflush, -- out_fifo_tdata => out_fifo_tdata, out_fifo_tvalid => out_fifo_tvalid, out_fifo_tlast => out_fifo_tlast, out_fifo_tready => data_sent); -- data_sent is named poorly, using it for ready signal SUMP_UART_block : entity work.SUMPComms generic map (clock_freq => INPUT_CLK_RATE_HZ, baud_rate => baud_rate) port map ( clk => clk, rst => rst, rx => uart_rx, tx => uart_tx, tx_command => out_fifo_tdata, command_ready => command_ready_int, data_ready => out_fifo_tvalid, data_sent => data_sent, command => sump_byte); Message_processing_block : entity work.msg_processor port map ( clk => clk, rst => rst, -- byte_in => sump_byte, byte_new => command_ready_int, -- sample_f => sample_f, --outputs reset => rst_cmd, armed => arm_cmd, send_ID => id_cmd, send_debug=> debug_cmd, read_cnt => read_cnt_4x, delay_cnt => delay_cnt_4x, trig_msk => par_trig_msk, trig_vals => par_trig_val); sample_rate_block : entity work.sample_rate_ctrl -- not implemented yet port map( clk => clk, rst => rst, divider_rate => sample_f, reset => sample_cnt_rst, armed => armed_int, sample_en => sample_enable); armed <= armed_int; end architecture structural;
gpl-2.0
739a14b068682923c9005f3f53cee97d
0.532001
3.79093
false
false
false
false
AndyMcC0/UVVM_All
uvvm_vvc_framework/src/ti_uvvm_engine.vhd
1
2,231
--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <[email protected]>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library uvvm_util; context uvvm_util.uvvm_util_context; library uvvm_vvc_framework; use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all; entity ti_uvvm_engine is end entity; architecture func of ti_uvvm_engine is begin -------------------------------------------------------- -- Initializes the UVVM VVC Framework -------------------------------------------------------- p_initialize_uvvm : process begin -- shared_uvvm_state is initialized to IDLE. Hence it will stay in IDLE if this procedure is not included in the TB shared_uvvm_state := PHASE_A; wait for 0 ns; -- A single delta cycle if (shared_uvvm_state = PHASE_B) then tb_failure("ti_uvvm_engine seems to have been instantiated more than once in this testbench system", C_SCOPE); end if; shared_uvvm_state := PHASE_B; wait for 0 ns; -- A single delta cycle shared_uvvm_state := INIT_COMPLETED; wait; end process p_initialize_uvvm; end func;
mit
8bbc505ee793478531d7ddc832f6935f
0.555356
4.946785
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/LBDR_packet_drop_with_checkers/LBDR_packet_drop_with_checkers.vhd
3
23,415
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity LBDR_packet_drop is generic ( cur_addr_rst: integer := 8; Cx_rst: integer := 8; NoC_size: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; Rxy_reconf: in std_logic_vector(7 downto 0); Reconfig : in std_logic; Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic; empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); dst_addr: in std_logic_vector(NoC_size-1 downto 0); packet_drop_order: out std_logic; grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic; -- Checker outputs -- Routing part checkers err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in, err_header_not_empty_packet_drop_in, err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal, err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order, -- Cx_Reconf checkers err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal, -- Rxy_Reconf checkers err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal : out std_logic ); end LBDR_packet_drop; architecture behavior of LBDR_packet_drop is signal Cx, Cx_in: std_logic_vector(3 downto 0); signal Temp_Cx, Temp_Cx_in: std_logic_vector(3 downto 0); signal reconfig_cx, reconfig_cx_in: std_logic; signal Rxy, Rxy_in: std_logic_vector(7 downto 0); signal cur_addr: std_logic_vector(NoC_size-1 downto 0); signal N1, E1, W1, S1 :std_logic :='0'; signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic; signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic; signal grants: std_logic; signal packet_drop, packet_drop_in: std_logic; signal ReConf_FF_in, ReConf_FF_out: std_logic; -- Signal(s) required for checker(s) signal packet_drop_order_sig: std_logic; component LBDR_packet_drop_routing_part_pseudo_checkers is generic ( cur_addr_rst: integer := 5; NoC_size: integer := 4 ); port ( empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic; grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; dst_addr: in std_logic_vector(NoC_size-1 downto 0); Cx: in std_logic_vector(3 downto 0); Rxy: in std_logic_vector(7 downto 0); packet_drop: in std_logic; N1_out, E1_out, W1_out, S1_out: in std_logic; Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic; grants: in std_logic; packet_drop_order: in std_logic; packet_drop_in: in std_logic; -- Checker outputs err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in, err_header_not_empty_packet_drop_in, err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal, err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order : out std_logic ); end component; component Cx_Reconf_pseudo_checkers is port ( reconfig_cx: in std_logic; flit_type: in std_logic_vector(2 downto 0); empty: in std_logic; grants: in std_logic; Cx_in: in std_logic_vector(3 downto 0); Temp_Cx: in std_logic_vector(3 downto 0); reconfig_cx_in: in std_logic; Cx: in std_logic_vector(3 downto 0); Faulty_C_N: in std_logic; Faulty_C_E: in std_logic; Faulty_C_W: in std_logic; Faulty_C_S: in std_logic; Temp_Cx_in: in std_logic_vector(3 downto 0); -- Checker Outputs err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal : out std_logic ); end component; component Rxy_Reconf_pseudo_checkers is port ( ReConf_FF_out: in std_logic; flit_type: in std_logic_vector(2 downto 0); empty: in std_logic; grants: in std_logic; Rxy_in: in std_logic_vector(7 downto 0); Rxy_reconf: in std_logic_vector(7 downto 0); ReConf_FF_in: in std_logic; Rxy: in std_logic_vector(7 downto 0); Reconfig : in std_logic; err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal : out std_logic ); end component; begin packet_drop_order <= packet_drop_order_sig; -- LBDR packet drop routing part checkers instantiation LBDR_packet_drop_routing_part_checkers: LBDR_packet_drop_routing_part_pseudo_checkers generic map (cur_addr_rst => cur_addr_rst, NoC_size => NoC_size) port map ( empty => empty, flit_type => flit_type, Req_N_FF => Req_N_FF, Req_E_FF => Req_E_FF, Req_W_FF => Req_W_FF, Req_S_FF => Req_S_FF, Req_L_FF => Req_L_FF, grant_N => grant_N, grant_E => grant_E, grant_W => grant_W, grant_S => grant_S, grant_L => grant_L, dst_addr => dst_addr, Cx => Cx, Rxy => Rxy, packet_drop => packet_drop, N1_out => N1, E1_out => E1, W1_out => W1, S1_out => S1, Req_N_in => Req_N_in, Req_E_in => Req_E_in, Req_W_in => Req_W_in, Req_S_in => Req_S_in, Req_L_in => Req_L_in, grants => grants, packet_drop_order => packet_drop_order_sig, packet_drop_in => packet_drop_in, -- Checker outputs err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => err_grants_onehot, err_grants_mismatch => err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in, err_header_not_empty_packet_drop_in => err_header_not_empty_packet_drop_in, err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal => err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal, err_header_empty_packet_drop_in_packet_drop_equal => err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => err_packet_drop_order ); -- LBDR packet drop Cx Reconfiguration module checkers instantiation Cx_Reconf_checkers: Cx_Reconf_pseudo_checkers port map ( reconfig_cx => reconfig_cx, flit_type => flit_type, empty => empty, grants => grants, Cx_in => Cx_in, Temp_Cx => Temp_Cx, reconfig_cx_in => reconfig_cx_in, Cx => Cx, Faulty_C_N => Faulty_C_N, Faulty_C_E => Faulty_C_E, Faulty_C_W => Faulty_C_W, Faulty_C_S => Faulty_C_S, Temp_Cx_in => Temp_Cx_in, -- Checker Outputs err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal ); -- LBDR packet drop Rxy Reconfiguration checkers instantiation Rxy_Reconf_checkers : Rxy_Reconf_pseudo_checkers port map ( ReConf_FF_out => ReConf_FF_out, flit_type => flit_type, empty => empty, grants => grants, Rxy_in => Rxy_in, Rxy_reconf => Rxy_reconf, ReConf_FF_in => ReConf_FF_in, Rxy => Rxy, Reconfig => Reconfig, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal ); grants <= grant_N or grant_E or grant_W or grant_S or grant_L; cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length)); N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0'; E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0'; W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0'; S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0'; process(clk, reset) begin if reset = '0' then Rxy <= Rxy_reconf; Req_N_FF <= '0'; Req_E_FF <= '0'; Req_W_FF <= '0'; Req_S_FF <= '0'; Req_L_FF <= '0'; Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length)); Temp_Cx <= (others => '0'); ReConf_FF_out <= '0'; reconfig_cx <= '0'; packet_drop <= '0'; elsif clk'event and clk = '1' then Rxy <= Rxy_in; Req_N_FF <= Req_N_in; Req_E_FF <= Req_E_in; Req_W_FF <= Req_W_in; Req_S_FF <= Req_S_in; Req_L_FF <= Req_L_in; ReConf_FF_out <= ReConf_FF_in; Cx <= Cx_in; reconfig_cx <= reconfig_cx_in; Temp_Cx <= Temp_Cx_in; packet_drop <= packet_drop_in; end if; end process; -- The combionational part process(Rxy_reconf, ReConf_FF_out, Rxy, Reconfig, flit_type, grants, empty)begin if ReConf_FF_out= '1' and flit_type = "100" and empty = '0' and grants = '1' then Rxy_in <= Rxy_reconf; ReConf_FF_in <= '0'; else Rxy_in <= Rxy; if Reconfig = '1' then ReConf_FF_in <= '1'; else ReConf_FF_in <= ReConf_FF_out; end if; end if; end process; process(Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Cx, Temp_Cx, flit_type, reconfig_cx, empty, grants) begin Temp_Cx_in <= Temp_Cx; if reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' then Cx_in <= Temp_Cx; reconfig_cx_in <= '0'; else Cx_in <= Cx; if (Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1' then reconfig_cx_in <= '1'; Temp_Cx_in <= not(Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N) and Cx; else reconfig_cx_in <= reconfig_cx; end if; end if; end process; Req_N <= Req_N_FF; Req_E <= Req_E_FF; Req_W <= Req_W_FF; Req_S <= Req_S_FF; Req_L <= Req_L_FF; process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants, packet_drop) begin packet_drop_in <= packet_drop; if flit_type = "001" and empty = '0' then Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0); Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1); Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2); Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3); if dst_addr = cur_addr then Req_L_in <= '1'; else Req_L_in <= Req_L_FF; -- Added to remove latch possibility. Correct ?? end if; if ((((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0)) or (((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1)) or (((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2)) or (((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3))) ='0' and dst_addr /= cur_addr then packet_drop_in <= '1'; end if; elsif flit_type = "100" and empty = '0' and grants = '1' then Req_N_in <= '0'; Req_E_in <= '0'; Req_W_in <= '0'; Req_S_in <= '0'; Req_L_in <= '0'; else Req_N_in <= Req_N_FF; Req_E_in <= Req_E_FF; Req_W_in <= Req_W_FF; Req_S_in <= Req_S_FF; Req_L_in <= Req_L_FF; end if; if flit_type = "100" and empty = '0' then if packet_drop = '1' then packet_drop_in <= '0'; end if; end if; end process; packet_drop_order_sig <= packet_drop; END;
gpl-3.0
91de9e05d457d77b75a1c851cba22806
0.519368
3.307671
false
true
false
false
simoesusp/Processador-ICMC
Processor_FPGA/Processor_Template_VHDL_DE70/MUX1.vhd
4
6,693
-- megafunction wizard: %LPM_MUX% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: LPM_MUX -- ============================================================ -- File Name: MUX1.vhd -- Megafunction Name(s): -- LPM_MUX -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 10.1 Build 153 11/29/2010 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.all; ENTITY MUX1 IS PORT ( data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END MUX1; ARCHITECTURE SYN OF mux1 IS -- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL sub_wire2 : STD_LOGIC_2D (3 DOWNTO 0, 15 DOWNTO 0); SIGNAL sub_wire3 : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL sub_wire4 : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL sub_wire5 : STD_LOGIC_VECTOR (15 DOWNTO 0); BEGIN sub_wire5 <= data0x(15 DOWNTO 0); sub_wire4 <= data1x(15 DOWNTO 0); sub_wire3 <= data2x(15 DOWNTO 0); result <= sub_wire0(15 DOWNTO 0); sub_wire1 <= data3x(15 DOWNTO 0); sub_wire2(3, 0) <= sub_wire1(0); sub_wire2(3, 1) <= sub_wire1(1); sub_wire2(3, 2) <= sub_wire1(2); sub_wire2(3, 3) <= sub_wire1(3); sub_wire2(3, 4) <= sub_wire1(4); sub_wire2(3, 5) <= sub_wire1(5); sub_wire2(3, 6) <= sub_wire1(6); sub_wire2(3, 7) <= sub_wire1(7); sub_wire2(3, 8) <= sub_wire1(8); sub_wire2(3, 9) <= sub_wire1(9); sub_wire2(3, 10) <= sub_wire1(10); sub_wire2(3, 11) <= sub_wire1(11); sub_wire2(3, 12) <= sub_wire1(12); sub_wire2(3, 13) <= sub_wire1(13); sub_wire2(3, 14) <= sub_wire1(14); sub_wire2(3, 15) <= sub_wire1(15); sub_wire2(2, 0) <= sub_wire3(0); sub_wire2(2, 1) <= sub_wire3(1); sub_wire2(2, 2) <= sub_wire3(2); sub_wire2(2, 3) <= sub_wire3(3); sub_wire2(2, 4) <= sub_wire3(4); sub_wire2(2, 5) <= sub_wire3(5); sub_wire2(2, 6) <= sub_wire3(6); sub_wire2(2, 7) <= sub_wire3(7); sub_wire2(2, 8) <= sub_wire3(8); sub_wire2(2, 9) <= sub_wire3(9); sub_wire2(2, 10) <= sub_wire3(10); sub_wire2(2, 11) <= sub_wire3(11); sub_wire2(2, 12) <= sub_wire3(12); sub_wire2(2, 13) <= sub_wire3(13); sub_wire2(2, 14) <= sub_wire3(14); sub_wire2(2, 15) <= sub_wire3(15); sub_wire2(1, 0) <= sub_wire4(0); sub_wire2(1, 1) <= sub_wire4(1); sub_wire2(1, 2) <= sub_wire4(2); sub_wire2(1, 3) <= sub_wire4(3); sub_wire2(1, 4) <= sub_wire4(4); sub_wire2(1, 5) <= sub_wire4(5); sub_wire2(1, 6) <= sub_wire4(6); sub_wire2(1, 7) <= sub_wire4(7); sub_wire2(1, 8) <= sub_wire4(8); sub_wire2(1, 9) <= sub_wire4(9); sub_wire2(1, 10) <= sub_wire4(10); sub_wire2(1, 11) <= sub_wire4(11); sub_wire2(1, 12) <= sub_wire4(12); sub_wire2(1, 13) <= sub_wire4(13); sub_wire2(1, 14) <= sub_wire4(14); sub_wire2(1, 15) <= sub_wire4(15); sub_wire2(0, 0) <= sub_wire5(0); sub_wire2(0, 1) <= sub_wire5(1); sub_wire2(0, 2) <= sub_wire5(2); sub_wire2(0, 3) <= sub_wire5(3); sub_wire2(0, 4) <= sub_wire5(4); sub_wire2(0, 5) <= sub_wire5(5); sub_wire2(0, 6) <= sub_wire5(6); sub_wire2(0, 7) <= sub_wire5(7); sub_wire2(0, 8) <= sub_wire5(8); sub_wire2(0, 9) <= sub_wire5(9); sub_wire2(0, 10) <= sub_wire5(10); sub_wire2(0, 11) <= sub_wire5(11); sub_wire2(0, 12) <= sub_wire5(12); sub_wire2(0, 13) <= sub_wire5(13); sub_wire2(0, 14) <= sub_wire5(14); sub_wire2(0, 15) <= sub_wire5(15); LPM_MUX_component : LPM_MUX GENERIC MAP ( lpm_size => 4, lpm_type => "LPM_MUX", lpm_width => 16, lpm_widths => 2 ) PORT MAP ( data => sub_wire2, sel => sel, result => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2" -- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL "data0x[15..0]" -- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL "data1x[15..0]" -- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL "data2x[15..0]" -- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL "data3x[15..0]" -- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]" -- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]" -- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0 -- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0 -- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0 -- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0 -- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0 -- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm
gpl-3.0
ec27f4f77ea2bea61ba8bf3227ce6232
0.598984
2.647547
false
false
false
false
elainemielas/CVUT_BI-PNO
project2/automat.vhd
1
5,538
library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity AUTOMAT is port ( KEY_F : in std_logic; -- high for one clock when key 'f' pressed KEY_U : in std_logic; -- high for one clock when key 'u' pressed KEY_L : in std_logic; -- high for one clock when key 'l' pressed KEY_PRESS : in std_logic; -- high for one clock when any key pressed CLK : in std_logic; -- standard 50MHz clock RESET : in std_logic; JCHYBA : out std_logic; -- detekovano s 1 chybou SHODA : out std_logic -- detekovana uplna shoda ); end AUTOMAT; architecture AUTOMAT_BODY of AUTOMAT is signal STAV, DALSI_STAV : std_logic_vector(0 to 8); -- bit 0 = stav 1 a tak dale begin PRECHODY : process (KEY_F, KEY_U, KEY_L, KEY_PRESS, STAV) begin DALSI_STAV <= STAV; case STAV is -- 1 when "100000000" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 else DALSI_STAV <= "100001000"; -- 1,6 end if; -- 1,2 when "110000000" => if KEY_F = '1' then DALSI_STAV <= "110000100"; -- 1,2,7 elsif KEY_U = '1' then DALSI_STAV <= "101001000"; -- 1,3,6 else DALSI_STAV <= "100001100"; -- 1,6,7 end if; -- 1,6 when "100001000" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 elsif KEY_U = '1' then DALSI_STAV <= "100001100"; -- 1,6,7 else DALSI_STAV <= "100001000"; -- 1,6 end if; -- 1,2,7 when "110000100" => if KEY_F = '1' then DALSI_STAV <= "110000100"; -- 1,2,7 elsif KEY_U = '1' then DALSI_STAV <= "101001000"; -- 1,3,6 elsif KEY_L = '1' then DALSI_STAV <= "100001110"; -- 1,6,7,8 else DALSI_STAV <= "100001100"; -- 1,6,7 end if; -- 1,6,7 when "100001100" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 elsif KEY_U = '1' then DALSI_STAV <= "100001100"; -- 1,6,7 elsif KEY_L = '1' then DALSI_STAV <= "100001010"; -- 1,6,8 else DALSI_STAV <= "100001000"; -- 1,6 end if; -- 1,3,6 when "101001000" => if KEY_F = '1' then DALSI_STAV <= "110000010"; -- 1,2,8 elsif KEY_U = '1' then DALSI_STAV <= "100001110"; -- 1,6,7,8 elsif KEY_L = '1' then DALSI_STAV <= "100101000"; -- 1,4,6 else DALSI_STAV <= "100001010"; -- 1,6,8 end if; -- 1,6,7,8 when "100001110" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 elsif KEY_U = '1' then DALSI_STAV <= "100001100"; -- 1,6,7 elsif KEY_L = '1' then DALSI_STAV <= "100001011"; -- 1,6,8,9 else DALSI_STAV <= "100001000"; -- 1,6 end if; -- 1,6,8 when "100001010" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 elsif KEY_U = '1' then DALSI_STAV <= "100001100"; -- 1,6,7 elsif KEY_L = '1' then DALSI_STAV <= "100001001"; -- 1,6,9 else DALSI_STAV <= "100001000"; -- 1,6 end if; -- 1,4,6 when "100101000" => if KEY_F = '1' then DALSI_STAV <= "110000001"; -- 1,2,9 elsif KEY_U = '1' then DALSI_STAV <= "100001101"; -- 1,6,7,9 elsif KEY_L = '1' then DALSI_STAV <= "100011000"; -- 1,5,6 else DALSI_STAV <= "100001001"; -- 1,6,9 end if; -- 1,2,8 when "110000010" => if KEY_F = '1' then DALSI_STAV <= "110000100"; -- 1,2,7 elsif KEY_U = '1' then DALSI_STAV <= "101001000"; -- 1,3,6 elsif KEY_L = '1' then DALSI_STAV <= "100001101"; -- 1,6,7,9 else DALSI_STAV <= "100001100"; -- 1,6,7 end if; -- 1,6,8,9 when "100001011" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 elsif KEY_U = '1' then DALSI_STAV <= "100001100"; -- 1,6,7 elsif KEY_L = '1' then DALSI_STAV <= "100001001"; -- 1,6,9 else DALSI_STAV <= "100001000"; -- 1,6 end if; -- 1,6,9 when "100001001" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 elsif KEY_U = '1' then DALSI_STAV <= "100001100"; -- 1,6,7 else DALSI_STAV <= "100001000"; -- 1,6 end if; -- 1,2,9 when "110000001" => if KEY_F = '1' then DALSI_STAV <= "110000100"; -- 1,2,7 elsif KEY_U = '1' then DALSI_STAV <= "101001000"; -- 1,3,6 else DALSI_STAV <= "100001100"; -- 1,6,7 end if; -- 1,6,7,9 when "100001101" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 elsif KEY_U = '1' then DALSI_STAV <= "100001100"; -- 1,6,7 elsif KEY_L = '1' then DALSI_STAV <= "100001010"; -- 1,6,8 else DALSI_STAV <= "100001000"; -- 1,6 end if; -- 1,5,6 when "100011000" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 elsif KEY_U = '1' then DALSI_STAV <= "100001100"; -- 1,6,7 else DALSI_STAV <= "100001000"; -- 1,6 end if; when others => NULL; end case; end process; VYSTUPY : process (STAV) begin JCHYBA <= '0'; SHODA <= '0'; if STAV(8) = '1' then JCHYBA <= '1'; elsif STAV(4) = '1' then SHODA <= '1'; end if; end process; REG : process (CLK) begin if CLK'event and CLK = '1' then if RESET = '1' then STAV <= "100000000"; -- reset elsif KEY_PRESS = '1' then STAV <= DALSI_STAV; else STAV <= STAV; end if; end if; end process; end architecture;
mit
8b88ac3a8eefdaa3687ca83f98db19fe
0.538281
2.995133
false
false
false
false
camacazio/de0_nano_DAC
DE0_12bitDAC_controller/FT245_communication.vhd
1
9,042
---------------------------------------------------------------------------------- -- Communication with FT245 for USB to 8-bit parrallel interface -- Handles communication with computer and sends data to rest of system ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity FT245Comm is Port ( -- Clocks clk_comm : in std_logic; -- USB to FIFO communication: FT245RL comm_data : in std_logic_vector(7 downto 0); -- Unidirectional data bus comm_rxfl : in std_logic; -- FIFO has data for read, default '1' comm_rdl : out std_logic := '1'; -- Fetch from FIFO, default '1' -- Data output word data_q : out std_logic_vector(15 downto 0); -- Word for the rest of the system -- Address for memory location for data addr_comm_q : out std_logic_vector(13 downto 0); -- address for writing to the M9K RAM -- Enable for different DAC memory blocks chan0_wren : out std_logic; chan1_wren : out std_logic; logic_wren : out std_logic; -- USB command to run operations in rest of system run_wave0 : out std_logic; run_wave1 : out std_logic; run_logic : out std_logic ); end entity; architecture Behavioral of FT245Comm is ---------------------------------------------------------------------------------- -- SIGNALS ---------------------------------------------------------------------------------- -- Internal copy of word of data signal data_out : std_logic_vector(15 downto 0) := (others => '0'); -- Steps through the write port of the M9K RAM signal addr_comm : std_logic_vector((addr_comm_q'length - 1) downto 0) := (others => '0'); -- Sets the channel for data communication (whether TTL sequence or DAC memory) signal channel : std_logic_vector(7 downto 0) := (others => '0'); -- Enables writing to the chosen channel's M9K signal chanx_wren : std_logic := '0'; -- Enables running sequences to the chosen channel signal run_wavex : std_logic := '0'; ---------------------------------------------------------------------------------- -- BEGIN ---------------------------------------------------------------------------------- begin -- Latch data data_q <= data_out; -- Latch memory address addr_comm_q <= addr_comm; -- Latch the 'write enable' for memory depending on channel chan0_wren <= chanx_wren when channel = x"00" else '0'; chan1_wren <= chanx_wren when channel = x"01" else '0'; -- For the case that data is being transmitted for pulse sequencing logic_wren <= chanx_wren when channel = x"02" else '0'; -- Running the next waveform via communication channel run_wave0 <= run_wavex when channel = x"00" else '0'; run_wave1 <= run_wavex when channel = x"01" else '0'; -- run logic sequencing run_logic <= run_wavex when channel = x"02" else '0'; process (clk_comm, comm_rxfl) -- Define FSM type COMM_STATES is (RESET, IDLE, RECEIVE); -- Command states have multiple copies of commands for grabbing 1 byte at a time type COMMANDS is (NONE, BURST1, BURST2, WRITE1, WRITE2, SETADDR1, SETADDR2, CHANNEL1); variable comm_state : COMM_STATES := RESET; variable command : COMMANDS := NONE; -- data byte on each transmit variable data_in : std_logic_vector(7 downto 0); -- For counting number of words to take in on a burst write command variable count : std_logic_vector(15 downto 0); -- Used to siginify a need to walk through address locations variable inc_addr : std_logic; -- Counter for the run_wave trigger for slower processes variable run_count : std_logic_vector(1 downto 0); -- Command states list -- Commands for writing data to memory -- Sets burst length constant CMD_BURST : std_logic_vector(7 downto 0) := x"00"; -- Write waveform data constant CMD_WRITESINGLE : std_logic_vector(7 downto 0) := x"01"; constant CMD_WRITEBURST : std_logic_vector(7 downto 0) := x"02"; -- Input the address to begin writing in memory constant CMD_SETADDR : std_logic_vector(7 downto 0) := x"03"; -- Select system channel to receive data constant CMD_CHANNEL : std_logic_vector(7 downto 0) := x"04"; -- Run the wave via USB connection constant CMD_RUNWAVE : std_logic_vector(7 downto 0) := x"05"; begin if rising_edge(clk_comm) then case comm_state is when RESET => -- Clear values to default comm_rdl <= '1'; addr_comm <= (others => '0'); chanx_wren <= '0'; run_wavex <= '0'; count := (others => '0'); run_count := (others => '0'); inc_addr := '0'; command := NONE; -- Return to IDLE comm_state := IDLE; when IDLE => -- IDLE until data transfer with FIFO or other processes is ready/complete -- Are we ready/writing or just staying in idle if comm_rxfl = '0' then comm_rdl <= '0'; -- Take the read line low to take data. Data available on the next clock cycle. comm_state := RECEIVE; else -- Stay in IDLE comm_rdl <= '1'; -- default comm_state := IDLE; end if; -- At end of WRITE2, wren line should have been raised, now clear here chanx_wren <= '0'; -- Running waveforms, reset the trigger after a wait period if run_wavex = '1' then run_count := run_count + 1; if run_count = 0 then run_wavex <= '0'; end if; end if; -- If flagged, increment address for writing location addr_comm <= addr_comm + inc_addr; inc_addr := '0'; -- RECEIVE cycle. RECEIVE->IDLE->RECEIVE->...->IDLE when RECEIVE => -- Data is available data_in := comm_data; -- Latch data -- Raise the Rd line and proceed to command "RECEIVE1". -- "RECEIVE1" will trigger the "RECEIVE2" state if more data is available. comm_rdl <= '1'; comm_state := IDLE; -- Interpret or route incoming data. case command is when NONE => -- Incoming is a command case data_in is when CMD_BURST => -- Following two bytes is the burst count for writing a burst of data command := BURST1; when CMD_WRITESINGLE => -- Following two bytes are data to be written into the memory count := CONV_STD_LOGIC_VECTOR(1,count'length); -- Burst count is 1; command := WRITE1; when CMD_WRITEBURST => -- Interpret each pair of subsequent bytes as a write and decrement burst count until 0 if count > 0 then command := WRITE1; else command := NONE; end if; when CMD_SETADDR => -- Following two bytes is the address for the start of memory storage command := SETADDR1; when CMD_CHANNEL => -- Following byte sets the communication channel for a device command := CHANNEL1; when CMD_RUNWAVE => -- Flag to run waveforms or other operations run_wavex <= '1'; command := NONE; -- unkown command; ignore when others => command := NONE; end case; --Begin handling of the COMMAND_STATES cases -- CMD_BURST sequence when BURST1 => -- First of two bytes. Little Endian count := x"00" & data_in; command := BURST2; when BURST2 => -- Second of two bytes. Little Endian count := data_in & count(7 downto 0); command := NONE; -- Done with this command -- CMD_WRITESINGLE and CMD_WRITEBURST. when WRITE1 => -- Place data on register data_out <= x"00" & data_in; -- We need a second byte to finish the data command := WRITE2; when WRITE2 => -- Place data on register data_out <= data_in & data_out(7 downto 0); -- Prepare stepping to the next memory location chanx_wren <= '1'; inc_addr := '1'; -- Decrement count, none command when done, else repeat. count := count - 1; if count < 1 then -- Done with writing to memory so allow rest of process to function command := NONE; -- Done with write command else command := WRITE1; -- Read more data from FIFO as it becomes available. end if; -- CMD_SETLEN sequence when SETADDR1 => -- First of two bytes. Little Endian addr_comm(7 downto 0) <= data_in; command := SETADDR2; when SETADDR2 => -- Second of two bytes. Little Endian addr_comm <= data_in(addr_comm'LENGTH-9 downto 0) & addr_comm(7 downto 0); command := NONE; -- Done with this command -- CMD_CHANNEL sequence when CHANNEL1 => -- set the communication channel channel <= data_in; command := NONE; when others => command := NONE; end case; end case; end if; end process; end Behavioral;
gpl-3.0
c25962de7b897c0a263e29d76c51d90c
0.579739
3.49112
false
false
false
false
kiwih/subleq-vhdl
dual_port_memfile.vhd
1
1,335
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --comment to go here entity dual_port_memfile is generic( ADDR_WIDTH : integer := 4; DATA_WIDTH : integer := 16; MEM_LENGTH : integer := 128 ); port( CLK: in std_logic; WRITE_EN_A: in std_logic; ADDR_A: in std_logic_vector(ADDR_WIDTH - 1 downto 0); DATA_IN_A: in std_logic_vector(DATA_WIDTH - 1 downto 0); DATA_OUT_A: out std_logic_vector(DATA_WIDTH - 1 downto 0); WRITE_EN_B: in std_logic; ADDR_B: in std_logic_vector(ADDR_WIDTH - 1 downto 0); DATA_IN_B: in std_logic_vector(DATA_WIDTH - 1 downto 0); DATA_OUT_B: out std_logic_vector(DATA_WIDTH - 1 downto 0) ); end entity; architecture beh of dual_port_memfile is type memory_type is array(0 to MEM_LENGTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0); signal memory : memory_type := ( 0 => x"0000", 1 => x"FFF1", --negative F 2 => x"0001", others => (others => '0') ); begin process(CLK) begin if rising_edge(CLK) then if WRITE_EN_A = '1' then memory(to_integer(unsigned(ADDR_A))) <= DATA_IN_A; end if; if WRITE_EN_B = '1' then memory(to_integer(unsigned(ADDR_B))) <= DATA_IN_B; end if; end if; DATA_OUT_A <= memory(to_integer(unsigned(ADDR_A))); DATA_OUT_B <= memory(to_integer(unsigned(ADDR_B))); end process; end architecture beh;
mit
66cd135e99dd98a879bc61fbf9d56cce
0.652434
2.617647
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/Arbiter_out_one_hot_with_checkers/arbiter_out_one_hot_with_checkers.vhd
3
16,049
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; entity arbiter_out is port ( reset: in std_logic; clk: in std_logic; X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules credit: in std_logic_vector(1 downto 0); grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot) -- Checker outputs err_Requests_state_in_state_not_equal, err_IDLE_req_X_N, err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N, err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E, err_West_req_X_W, err_West_credit_not_zero_req_X_E_grant_E, err_West_credit_zero_or_not_req_X_W_not_grant_W, err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S, err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L, err_IDLE_req_X_E, err_North_req_X_E, err_East_req_X_W, err_West_req_X_S, err_South_req_X_L, err_Local_req_X_N, err_IDLE_req_X_W, err_North_req_X_W, err_East_req_X_S, err_West_req_X_L, err_South_req_X_N, err_Local_req_X_E, err_IDLE_req_X_S, err_North_req_X_S, err_East_req_X_L, err_West_req_X_N, err_South_req_X_E, err_Local_req_X_W, err_IDLE_req_X_L, err_North_req_X_L, err_East_req_X_N, err_West_req_X_E, err_South_req_X_W, err_Local_req_X_S, err_state_in_onehot, err_no_request_grants, err_request_IDLE_state, err_request_IDLE_not_Grants, err_state_North_Invalid_Grant, err_state_East_Invalid_Grant, err_state_West_Invalid_Grant, err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant, err_Grants_onehot_or_all_zero : out std_logic ); end; architecture behavior of arbiter_out is component Arbiter_out_one_hot_pseudo_checkers is port ( credit: in std_logic_vector(1 downto 0); req_X_E, req_X_N, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : in std_logic; -- Grants given to LBDR requests (encoded as one-hot) state_in: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM -- Checker outputs err_Requests_state_in_state_not_equal, err_IDLE_req_X_N, err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N, err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E, err_West_req_X_W, err_West_credit_not_zero_req_X_E_grant_E, err_West_credit_zero_or_not_req_X_W_not_grant_W, err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S, err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L, err_IDLE_req_X_E, err_North_req_X_E, err_East_req_X_W, err_West_req_X_S, err_South_req_X_L, err_Local_req_X_N, err_IDLE_req_X_W, err_North_req_X_W, err_East_req_X_S, err_West_req_X_L, err_South_req_X_N, err_Local_req_X_E, err_IDLE_req_X_S, err_North_req_X_S, err_East_req_X_L, err_West_req_X_N, err_South_req_X_E, err_Local_req_X_W, err_IDLE_req_X_L, err_North_req_X_L, err_East_req_X_N, err_West_req_X_E, err_South_req_X_W, err_Local_req_X_S, err_state_in_onehot, err_no_request_grants, err_request_IDLE_state, err_request_IDLE_not_Grants, err_state_North_Invalid_Grant, err_state_East_Invalid_Grant, err_state_West_Invalid_Grant, err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant, err_Grants_onehot_or_all_zero : out std_logic ); end component; --TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local); CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001"; CONSTANT Local: std_logic_vector (5 downto 0) := "000010"; CONSTANT North: std_logic_vector (5 downto 0) := "000100"; CONSTANT East: std_logic_vector (5 downto 0) := "001000"; CONSTANT West: std_logic_vector (5 downto 0) := "010000"; CONSTANT South: std_logic_vector (5 downto 0) := "100000"; SIGNAL state, state_in : std_logic_vector (5 downto 0) := IDLE; -- : STATE_TYPE := IDLE; SIGNAL grant_Y_N_sig, grant_Y_E_sig, grant_Y_W_sig, grant_Y_S_sig, grant_Y_L_sig : std_logic; begin -- We did this because of the checker outputs! grant_Y_N <= grant_Y_N_sig; grant_Y_E <= grant_Y_E_sig; grant_Y_W <= grant_Y_W_sig; grant_Y_S <= grant_Y_S_sig; grant_Y_L <= grant_Y_L_sig; -- Sequential part process (clk, reset)begin if reset = '0' then state <= IDLE; elsif clk'event and clk ='1' then state <= state_in; end if; end process; -- Arbiter_out checkers module instantiation CHECKERS: Arbiter_out_one_hot_pseudo_checkers port map ( credit => credit, req_X_E => X_N_Y, req_X_N => X_E_Y, req_X_W => X_W_Y, req_X_S => X_S_Y, req_X_L => X_L_Y, state => state, grant_Y_N => grant_Y_N_sig, grant_Y_E => grant_Y_E_sig, grant_Y_W => grant_Y_W_sig, grant_Y_S => grant_Y_S_sig, grant_Y_L => grant_Y_L_sig, state_in => state_in, -- Checker outputs err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal, err_IDLE_req_X_N => err_IDLE_req_X_N, err_North_req_X_N => err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N => err_North_credit_not_zero_req_X_N_grant_N, err_North_credit_zero_or_not_req_X_N_not_grant_N => err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E => err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E => err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E => err_East_credit_zero_or_not_req_X_E_not_grant_E, err_West_req_X_W => err_West_req_X_W, err_West_credit_not_zero_req_X_E_grant_E => err_West_credit_not_zero_req_X_E_grant_E, err_West_credit_zero_or_not_req_X_W_not_grant_W => err_West_credit_zero_or_not_req_X_W_not_grant_W, err_South_req_X_S => err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S => err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S => err_South_credit_zero_or_not_req_X_S_not_grant_S, err_Local_req_X_L => err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L => err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L => err_Local_credit_zero_or_not_req_X_L_not_grant_L, err_IDLE_req_X_E => err_IDLE_req_X_E, err_North_req_X_E => err_North_req_X_E, err_East_req_X_W => err_East_req_X_W, err_West_req_X_S => err_West_req_X_S, err_South_req_X_L => err_South_req_X_L, err_Local_req_X_N => err_Local_req_X_N, err_IDLE_req_X_W => err_IDLE_req_X_W, err_North_req_X_W => err_North_req_X_W, err_East_req_X_S => err_East_req_X_S, err_West_req_X_L => err_West_req_X_L, err_South_req_X_N => err_South_req_X_N, err_Local_req_X_E => err_Local_req_X_E, err_IDLE_req_X_S => err_IDLE_req_X_S, err_North_req_X_S => err_North_req_X_S, err_East_req_X_L => err_East_req_X_L, err_West_req_X_N => err_West_req_X_N, err_South_req_X_E => err_South_req_X_E, err_Local_req_X_W => err_Local_req_X_W, err_IDLE_req_X_L => err_IDLE_req_X_L, err_North_req_X_L => err_North_req_X_L, err_East_req_X_N => err_East_req_X_N, err_West_req_X_E => err_West_req_X_E, err_South_req_X_W => err_South_req_X_W, err_Local_req_X_S => err_Local_req_X_S, err_state_in_onehot => err_state_in_onehot, err_no_request_grants => err_no_request_grants, err_request_IDLE_state => err_request_IDLE_state, err_request_IDLE_not_Grants => err_request_IDLE_not_Grants, err_state_North_Invalid_Grant => err_state_North_Invalid_Grant, err_state_East_Invalid_Grant => err_state_East_Invalid_Grant, err_state_West_Invalid_Grant => err_state_West_Invalid_Grant, err_state_South_Invalid_Grant => err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant => err_state_Local_Invalid_Grant, err_Grants_onehot_or_all_zero => err_Grants_onehot_or_all_zero ); -- anything below here is pure combinational process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin grant_Y_N_sig <= '0'; grant_Y_E_sig <= '0'; grant_Y_W_sig <= '0'; grant_Y_S_sig <= '0'; grant_Y_L_sig <= '0'; case state is when IDLE => if X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; else state_in <= IDLE; end if; when North => if credit /= "00" and X_N_Y = '1' then grant_Y_N_sig <= '1'; end if; if X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; else state_in <= IDLE; end if; when East => if credit /= "00" and X_E_Y = '1' then grant_Y_E_sig <= '1'; end if; if X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; elsif X_N_Y ='1' then state_in <= North; else state_in <= IDLE; end if; when West => if credit /= "00" and X_W_Y = '1' then grant_Y_W_sig <= '1'; end if; if X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; elsif X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; else state_in <= IDLE; end if; when South => if credit /= "00" and X_S_Y = '1' then grant_Y_S_sig <= '1'; end if; if X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; elsif X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; else state_in <= IDLE; end if; when others => if credit /= "00" and X_L_Y = '1' then grant_Y_L_sig <= '1'; end if; if X_L_Y = '1' then state_in <= Local; elsif X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; else state_in <= IDLE; end if; end case; end process; end;
gpl-3.0
eef315a4711fcb964ab548be90d0eab9
0.417347
3.522608
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/Checkers/Control_Part_Checkers/LBDR_packet_drop_checkers/LBDR_routing_part/RTL/LBDR_packet_drop_routing_part_pseudo_with_checkers_top.vhd
3
13,908
library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity LBDR_packet_drop_routing_part_pseudo_with_checkers_top is generic ( cur_addr_rst: integer := 5; NoC_size: integer := 4 ); port ( empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); dst_addr: in std_logic_vector(NoC_size-1 downto 0); grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic; Cx: in std_logic_vector(3 downto 0); Rxy: in std_logic_vector(7 downto 0); packet_drop: in std_logic; packet_drop_order_out: out std_logic; packet_drop_in_out: out std_logic; Req_N_in_out, Req_E_in_out, Req_W_in_out, Req_S_in_out, Req_L_in_out: out std_logic; N1_out, E1_out, W1_out, S1_out: out std_logic; grants_out: out std_logic; -- Checker outputs --err_header_not_empty_Requests_in_onehot, err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in, err_header_not_empty_packet_drop_in, err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal, err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order : out std_logic ); end LBDR_packet_drop_routing_part_pseudo_with_checkers_top; architecture behavior of LBDR_packet_drop_routing_part_pseudo_with_checkers_top is component LBDR_packet_drop_routing_part_pseudo is generic ( cur_addr_rst: integer := 5; NoC_size: integer := 4 ); port ( empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); dst_addr: in std_logic_vector(NoC_size-1 downto 0); grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic; Cx: in std_logic_vector(3 downto 0); Rxy: in std_logic_vector(7 downto 0); packet_drop: in std_logic; packet_drop_order: out std_logic; packet_drop_in: out std_logic; Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: out std_logic; N1_out, E1_out, W1_out, S1_out: out std_logic; grants_out: out std_logic ); end component; component LBDR_packet_drop_routing_part_pseudo_checkers is generic ( cur_addr_rst: integer := 5; NoC_size: integer := 4 ); port ( empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic; grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; dst_addr: in std_logic_vector(NoC_size-1 downto 0); Cx: in std_logic_vector(3 downto 0); Rxy: in std_logic_vector(7 downto 0); packet_drop: in std_logic; N1_out, E1_out, W1_out, S1_out: in std_logic; Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic; grants: in std_logic; packet_drop_order: in std_logic; packet_drop_in: in std_logic; -- Checker outputs --err_header_not_empty_Requests_in_onehot, err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in, err_header_not_empty_packet_drop_in, err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal, err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order : out std_logic ); end component; signal Req_N_in_sig, Req_E_in_sig, Req_W_in_sig, Req_S_in_sig, Req_L_in_sig: std_logic; signal N1_out_sig, E1_out_sig, W1_out_sig, S1_out_sig: std_logic; signal grants_out_sig, packet_drop_order_sig, packet_drop_in_sig: std_logic; begin packet_drop_in_out <= packet_drop_in_sig; packet_drop_order_out <= packet_drop_order_sig; Req_N_in_out <= Req_N_in_sig; Req_E_in_out <= Req_E_in_sig; Req_W_in_out <= Req_W_in_sig; Req_S_in_out <= Req_S_in_sig; Req_L_in_out <= Req_L_in_sig; N1_out <= N1_out_sig; E1_out <= E1_out_sig; W1_out <= W1_out_sig; S1_out <= S1_out_sig; grants_out <= grants_out_sig; -- LBDR packet drop routing part (pseudo-combinational) module instantiation LBDR_routing_part_pseudo: LBDR_packet_drop_routing_part_pseudo generic map (cur_addr_rst => 5, NoC_size => 4) port map ( empty => empty, flit_type => flit_type, dst_addr => dst_addr, grant_N => grant_N, grant_E => grant_E, grant_W => grant_W, grant_S => grant_S, grant_L => grant_L, Req_N_FF => Req_N_FF, Req_E_FF => Req_E_FF, Req_W_FF => Req_W_FF, Req_S_FF => Req_S_FF, Req_L_FF => Req_L_FF, Cx => Cx, Rxy => Rxy, packet_drop => packet_drop, packet_drop_order => packet_drop_order_sig, packet_drop_in => packet_drop_in_sig, Req_N_in => Req_N_in_sig, Req_E_in => Req_E_in_sig, Req_W_in => Req_W_in_sig, Req_S_in => Req_S_in_sig, Req_L_in => Req_L_in_sig, N1_out => N1_out_sig, E1_out => E1_out_sig, W1_out => W1_out_sig, S1_out => S1_out_sig, grants_out => grants_out_sig ); -- LBDR packet drop routing part checkers instantiation CHECKERS: LBDR_packet_drop_routing_part_pseudo_checkers generic map (cur_addr_rst => 5, NoC_size => 4) port map ( empty => empty, flit_type => flit_type, Req_N_FF => Req_N_FF, Req_E_FF => Req_E_FF, Req_W_FF => Req_W_FF, Req_S_FF => Req_S_FF, Req_L_FF => Req_L_FF, grant_N => grant_N, grant_E => grant_E, grant_W => grant_W, grant_S => grant_S, grant_L => grant_L, dst_addr => dst_addr, Cx => Cx, Rxy => Rxy, packet_drop => packet_drop, N1_out => N1_out_sig, E1_out => E1_out_sig, W1_out => W1_out_sig, S1_out => S1_out_sig, Req_N_in => Req_N_in_sig, Req_E_in => Req_E_in_sig, Req_W_in => Req_W_in_sig, Req_S_in => Req_S_in_sig, Req_L_in => Req_L_in_sig, grants => grants_out_sig, packet_drop_order => packet_drop_order_sig, packet_drop_in => packet_drop_in_sig, -- Checker outputs --err_header_not_empty_Requests_in_onehot => err_header_not_empty_Requests_in_onehot, err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => err_grants_onehot, err_grants_mismatch => err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in, err_header_not_empty_packet_drop_in => err_header_not_empty_packet_drop_in, err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal => err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal, err_header_empty_packet_drop_in_packet_drop_equal => err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => err_packet_drop_order ); end behavior;
gpl-3.0
f88366e3c12d882ad3937512fe70d626
0.471455
3.557033
false
false
false
false
ashtonchase/logic_analyzer
target_hardware/Zybo/zybo_top.vhd
1
4,355
------------------------------------------------------------------------------- -- Title : Zybo Board Top Level -- Project : fpga_logic_analyzer ------------------------------------------------------------------------------- -- File : zybo_top.vhd -- Created : 2016-02-22 -- Last update: 2016-02-22 -- Standard : VHDL'08 ------------------------------------------------------------------------------- -- Description: Xilinx Zynq 7000 on a Digilent Zybo Board Top Level Module, ------------------------------------------------------------------------------- -- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt ------------------------------------------------------------------------------- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-02-22 1.0 ashton Created ------------------------------------------------------------------------------- ENTITY zybo_top IS PORT ( clk : IN STD_LOGIC; -- 125 MHz clock je : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- PMOD JE inputs led : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --LED outputs sw : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Switches btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0) --Buttons ); END ENTITY zybo_top; ARCHITECTURE top OF zybo_top IS ----------------------------------------------------------------------------- -- Components ----------------------------------------------------------------------------- COMPONENT clock_gen PORT ( -- Clock in ports clk_in1 : IN STD_LOGIC; -- Clock out ports clk_25mhz : OUT STD_LOGIC; -- Status and control signals reset : IN STD_LOGIC; locked : OUT STD_LOGIC ); END COMPONENT; ----------------------------------------------------------------------------- -- Signals ----------------------------------------------------------------------------- SIGNAL reset : STD_LOGIC := '1'; -- reset (async high, sync low) SIGNAL run_clk : STD_LOGIC := '0'; -- clock output of the clocking wizard SIGNAL clk_locked : STD_LOGIC := '0'; -- indicator if the clocking wizard has locked ----------------------------------------------------------------------------- -- Aliases ----------------------------------------------------------------------------- ALIAS reset_btn : STD_LOGIC IS btn(0); BEGIN -- ARCHITECTURE top ----------------------------------------------------------------------------- -- Component Instatiations ----------------------------------------------------------------------------- -- purpose: this component will generate the desired system clock based on -- the 125 MHz input clock. Not the output is already downstream of a global -- clock buffer -- inputs : clk, reset -- outputs: clk_locked run_clk_component : clock_gen PORT MAP ( -- Clock in ports clk_in1 => clk, -- Clock out ports clk_out1 => run_clk, -- Status and control signals reset => reset_btn, locked => clk_locked ); -- purpose: this process will reset the system when btn0 is pressed -- type : combinational -- inputs : reset_btn, clk, clk_locked -- outputs: reset reset_proc : PROCESS (reset_btn, clk) IS BEGIN -- PROCESS reset_proc IF reset_btn = '1' THEN reset <= '1'; ELSIF rising_edge(clk) THEN reset <= '0'; END IF; END PROCESS reset_proc; END ARCHITECTURE top;
gpl-2.0
301d9c2ba1d628128b4e3865dbe2e8eb
0.455798
5.228091
false
false
false
false
elainemielas/CVUT_BI-PNO
cvika/had/tb_decoder.vhd
1
872
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity TB_DECODER is end entity TB_DECODER; architecture TB_DECODER_BODY of TB_DECODER is component DECODER port ( BIN_VALUE : in std_logic_vector (2 downto 0); ONE_HOT : out std_logic_vector (7 downto 0) ); end component; signal T_BIN_VALUE : std_logic_vector (2 downto 0); signal T_ONE_HOT : std_logic_vector (7 downto 0); begin UUT : DECODER port map (BIN_VALUE => T_BIN_VALUE, ONE_HOT => T_ONE_HOT); TEST : process begin for I in 0 to 7 loop T_BIN_VALUE <= conv_std_logic_vector (I, 3); wait for 30 ns; for J in 0 to 7 loop if (I = J) then assert T_ONE_HOT(J) = '1' report "ERROR!" severity ERROR; else assert T_ONE_HOT(J) = '0' report "ERROR!" severity ERROR; end if; end loop; end loop; end process; end architecture;
mit
b9cc7958ee110cce072a461380c97e85
0.649083
2.812903
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Processor_NI/mlite_pack.vhd
3
26,214
--------------------------------------------------------------------- -- TITLE: Plasma Misc. Package -- Main AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 2/15/01 -- FILENAME: mlite_pack.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Data types, constants, and add functions needed for the Plasma CPU. -- modified by: Siavoosh Payandeh Azad -- Change logs: -- * An NI has been added to the file as a new module -- * some changes has been applied to the ports of the older modules -- to facilitate the new module! --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package mlite_pack is constant ZERO : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; constant ONES : std_logic_vector(31 downto 0) := "11111111111111111111111111111111"; --make HIGH_Z equal to ZERO if compiler complains constant HIGH_Z : std_logic_vector(31 downto 0) := "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; subtype alu_function_type is std_logic_vector(3 downto 0); constant ALU_NOTHING : alu_function_type := "0000"; constant ALU_ADD : alu_function_type := "0001"; constant ALU_SUBTRACT : alu_function_type := "0010"; constant ALU_LESS_THAN : alu_function_type := "0011"; constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100"; constant ALU_OR : alu_function_type := "0101"; constant ALU_AND : alu_function_type := "0110"; constant ALU_XOR : alu_function_type := "0111"; constant ALU_NOR : alu_function_type := "1000"; subtype shift_function_type is std_logic_vector(1 downto 0); constant SHIFT_NOTHING : shift_function_type := "00"; constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01"; constant SHIFT_RIGHT_SIGNED : shift_function_type := "11"; constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10"; subtype mult_function_type is std_logic_vector(3 downto 0); constant MULT_NOTHING : mult_function_type := "0000"; constant MULT_READ_LO : mult_function_type := "0001"; constant MULT_READ_HI : mult_function_type := "0010"; constant MULT_WRITE_LO : mult_function_type := "0011"; constant MULT_WRITE_HI : mult_function_type := "0100"; constant MULT_MULT : mult_function_type := "0101"; constant MULT_SIGNED_MULT : mult_function_type := "0110"; constant MULT_DIVIDE : mult_function_type := "0111"; constant MULT_SIGNED_DIVIDE : mult_function_type := "1000"; subtype a_source_type is std_logic_vector(1 downto 0); constant A_FROM_REG_SOURCE : a_source_type := "00"; constant A_FROM_IMM10_6 : a_source_type := "01"; constant A_FROM_PC : a_source_type := "10"; subtype b_source_type is std_logic_vector(1 downto 0); constant B_FROM_REG_TARGET : b_source_type := "00"; constant B_FROM_IMM : b_source_type := "01"; constant B_FROM_SIGNED_IMM : b_source_type := "10"; constant B_FROM_IMMX4 : b_source_type := "11"; subtype c_source_type is std_logic_vector(2 downto 0); constant C_FROM_NULL : c_source_type := "000"; constant C_FROM_ALU : c_source_type := "001"; constant C_FROM_SHIFT : c_source_type := "001"; --same as alu constant C_FROM_MULT : c_source_type := "001"; --same as alu constant C_FROM_MEMORY : c_source_type := "010"; constant C_FROM_PC : c_source_type := "011"; constant C_FROM_PC_PLUS4 : c_source_type := "100"; constant C_FROM_IMM_SHIFT16: c_source_type := "101"; constant C_FROM_REG_SOURCEN: c_source_type := "110"; subtype pc_source_type is std_logic_vector(1 downto 0); constant FROM_INC4 : pc_source_type := "00"; constant FROM_OPCODE25_0 : pc_source_type := "01"; constant FROM_BRANCH : pc_source_type := "10"; constant FROM_LBRANCH : pc_source_type := "11"; subtype branch_function_type is std_logic_vector(2 downto 0); constant BRANCH_LTZ : branch_function_type := "000"; constant BRANCH_LEZ : branch_function_type := "001"; constant BRANCH_EQ : branch_function_type := "010"; constant BRANCH_NE : branch_function_type := "011"; constant BRANCH_GEZ : branch_function_type := "100"; constant BRANCH_GTZ : branch_function_type := "101"; constant BRANCH_YES : branch_function_type := "110"; constant BRANCH_NO : branch_function_type := "111"; -- mode(32=1,16=2,8=3), signed, write subtype mem_source_type is std_logic_vector(3 downto 0); constant MEM_FETCH : mem_source_type := "0000"; constant MEM_READ32 : mem_source_type := "0100"; constant MEM_WRITE32 : mem_source_type := "0101"; constant MEM_READ16 : mem_source_type := "1000"; constant MEM_READ16S : mem_source_type := "1010"; constant MEM_WRITE16 : mem_source_type := "1001"; constant MEM_READ8 : mem_source_type := "1100"; constant MEM_READ8S : mem_source_type := "1110"; constant MEM_WRITE8 : mem_source_type := "1101"; constant NI_reserved_data_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111"; constant NI_flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; constant NI_counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001"; constant uart_count_value_address : std_logic_vector(29 downto 0) := "000000000000000010000000000100"; function bv_adder(a : in std_logic_vector; b : in std_logic_vector; do_add: in std_logic) return std_logic_vector; function bv_negate(a : in std_logic_vector) return std_logic_vector; function bv_increment(a : in std_logic_vector(31 downto 2) ) return std_logic_vector; function bv_inc(a : in std_logic_vector ) return std_logic_vector; -- For Altera COMPONENT lpm_ram_dp generic ( LPM_WIDTH : natural; -- MUST be greater than 0 LPM_WIDTHAD : natural; -- MUST be greater than 0 LPM_NUMWORDS : natural := 0; LPM_INDATA : string := "REGISTERED"; LPM_OUTDATA : string := "REGISTERED"; LPM_RDADDRESS_CONTROL : string := "REGISTERED"; LPM_WRADDRESS_CONTROL : string := "REGISTERED"; LPM_FILE : string := "UNUSED"; LPM_TYPE : string := "LPM_RAM_DP"; USE_EAB : string := "OFF"; INTENDED_DEVICE_FAMILY : string := "UNUSED"; RDEN_USED : string := "TRUE"; LPM_HINT : string := "UNUSED"); port ( RDCLOCK : in std_logic := '0'; RDCLKEN : in std_logic := '1'; RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0); RDEN : in std_logic := '1'; DATA : in std_logic_vector(LPM_WIDTH-1 downto 0); WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0); WREN : in std_logic; WRCLOCK : in std_logic := '0'; WRCLKEN : in std_logic := '1'; Q : out std_logic_vector(LPM_WIDTH-1 downto 0)); END COMPONENT; -- For Altera component LPM_RAM_DQ generic ( LPM_WIDTH : natural; -- MUST be greater than 0 LPM_WIDTHAD : natural; -- MUST be greater than 0 LPM_NUMWORDS : natural := 0; LPM_INDATA : string := "REGISTERED"; LPM_ADDRESS_CONTROL: string := "REGISTERED"; LPM_OUTDATA : string := "REGISTERED"; LPM_FILE : string := "UNUSED"; LPM_TYPE : string := "LPM_RAM_DQ"; USE_EAB : string := "OFF"; INTENDED_DEVICE_FAMILY : string := "UNUSED"; LPM_HINT : string := "UNUSED"); port ( DATA : in std_logic_vector(LPM_WIDTH-1 downto 0); ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0); INCLOCK : in std_logic := '0'; OUTCLOCK : in std_logic := '0'; WE : in std_logic; Q : out std_logic_vector(LPM_WIDTH-1 downto 0)); end component; -- For Xilinx component RAM16X1D -- synthesis translate_off generic (INIT : bit_vector := X"0000"); -- synthesis translate_on port (DPO : out STD_ULOGIC; SPO : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; D : in STD_ULOGIC; DPRA0 : in STD_ULOGIC; DPRA1 : in STD_ULOGIC; DPRA2 : in STD_ULOGIC; DPRA3 : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; -- For Xilinx Virtex-5 component RAM32X1D -- synthesis translate_off generic (INIT : bit_vector := X"00000000"); -- synthesis translate_on port (DPO : out STD_ULOGIC; SPO : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; A4 : in STD_ULOGIC; D : in STD_ULOGIC; DPRA0 : in STD_ULOGIC; DPRA1 : in STD_ULOGIC; DPRA2 : in STD_ULOGIC; DPRA3 : in STD_ULOGIC; DPRA4 : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; component pc_next port(clk : in std_logic; reset_in : in std_logic; pc_new : in std_logic_vector(31 downto 2); take_branch : in std_logic; pause_in : in std_logic; opcode25_0 : in std_logic_vector(25 downto 0); pc_source : in pc_source_type; pc_future : out std_logic_vector(31 downto 2); pc_current : out std_logic_vector(31 downto 2); pc_plus4 : out std_logic_vector(31 downto 2)); end component; component mem_ctrl port(clk : in std_logic; reset_in : in std_logic; pause_in : in std_logic; nullify_op : in std_logic; address_pc : in std_logic_vector(31 downto 2); opcode_out : out std_logic_vector(31 downto 0); address_in : in std_logic_vector(31 downto 0); mem_source : in mem_source_type; data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); pause_out : out std_logic; address_next : out std_logic_vector(31 downto 2); byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0)); end component; component control port(opcode : in std_logic_vector(31 downto 0); intr_signal : in std_logic; --NI_read_flag : in std_logic; --NI_write_flag : in std_logic; rs_index : out std_logic_vector(5 downto 0); rt_index : out std_logic_vector(5 downto 0); rd_index : out std_logic_vector(5 downto 0); imm_out : out std_logic_vector(15 downto 0); alu_func : out alu_function_type; shift_func : out shift_function_type; mult_func : out mult_function_type; branch_func : out branch_function_type; a_source_out : out a_source_type; b_source_out : out b_source_type; c_source_out : out c_source_type; pc_source_out: out pc_source_type; mem_source_out:out mem_source_type; exception_out: out std_logic); end component; component reg_bank generic(memory_type : string := "XILINX_16X"); port(clk : in std_logic; reset_in : in std_logic; pause : in std_logic; interrupt_in : in std_logic; -- modified rs_index : in std_logic_vector(5 downto 0); rt_index : in std_logic_vector(5 downto 0); rd_index : in std_logic_vector(5 downto 0); reg_source_out : out std_logic_vector(31 downto 0); reg_target_out : out std_logic_vector(31 downto 0); reg_dest_new : in std_logic_vector(31 downto 0); intr_enable : out std_logic); end component; component bus_mux port(imm_in : in std_logic_vector(15 downto 0); reg_source : in std_logic_vector(31 downto 0); a_mux : in a_source_type; a_out : out std_logic_vector(31 downto 0); reg_target : in std_logic_vector(31 downto 0); b_mux : in b_source_type; b_out : out std_logic_vector(31 downto 0); c_bus : in std_logic_vector(31 downto 0); c_memory : in std_logic_vector(31 downto 0); c_pc : in std_logic_vector(31 downto 2); c_pc_plus4 : in std_logic_vector(31 downto 2); c_mux : in c_source_type; reg_dest_out : out std_logic_vector(31 downto 0); branch_func : in branch_function_type; take_branch : out std_logic); end component; component alu generic(alu_type : string := "DEFAULT"); port(a_in : in std_logic_vector(31 downto 0); b_in : in std_logic_vector(31 downto 0); alu_function : in alu_function_type; c_alu : out std_logic_vector(31 downto 0)); end component; component shifter generic(shifter_type : string := "DEFAULT" ); port(value : in std_logic_vector(31 downto 0); shift_amount : in std_logic_vector(4 downto 0); shift_func : in shift_function_type; c_shift : out std_logic_vector(31 downto 0)); end component; component mult generic(mult_type : string := "DEFAULT"); port(clk : in std_logic; reset_in : in std_logic; a, b : in std_logic_vector(31 downto 0); mult_func : in mult_function_type; c_mult : out std_logic_vector(31 downto 0); pause_out : out std_logic); end component; component pipeline port(clk : in std_logic; reset : in std_logic; a_bus : in std_logic_vector(31 downto 0); a_busD : out std_logic_vector(31 downto 0); b_bus : in std_logic_vector(31 downto 0); b_busD : out std_logic_vector(31 downto 0); alu_func : in alu_function_type; alu_funcD : out alu_function_type; shift_func : in shift_function_type; shift_funcD : out shift_function_type; mult_func : in mult_function_type; mult_funcD : out mult_function_type; reg_dest : in std_logic_vector(31 downto 0); reg_destD : out std_logic_vector(31 downto 0); rd_index : in std_logic_vector(5 downto 0); rd_indexD : out std_logic_vector(5 downto 0); rs_index : in std_logic_vector(5 downto 0); rt_index : in std_logic_vector(5 downto 0); pc_source : in pc_source_type; mem_source : in mem_source_type; a_source : in a_source_type; b_source : in b_source_type; c_source : in c_source_type; c_bus : in std_logic_vector(31 downto 0); pause_any : in std_logic; pause_pipeline : out std_logic); end component; component mlite_cpu generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_ mult_type : string := "DEFAULT"; shifter_type : string := "DEFAULT"; alu_type : string := "DEFAULT"; pipeline_stages : natural := 2); --2 or 3 port(clk : in std_logic; reset_in : in std_logic; intr_in : in std_logic; --NI_read_flag : in std_logic; --NI_write_flag : in std_logic; address_next : out std_logic_vector(31 downto 2); --for synch ram byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0); mem_pause : in std_logic); end component; component cache generic(memory_type : string := "DEFAULT"); port(clk : in std_logic; reset : in std_logic; address_next : in std_logic_vector(31 downto 2); byte_we_next : in std_logic_vector(3 downto 0); cpu_address : in std_logic_vector(31 downto 2); mem_busy : in std_logic; cache_access : out std_logic; --access 4KB cache cache_checking : out std_logic; --checking if cache hit cache_miss : out std_logic); --cache miss end component; --cache component ram generic(memory_type : string := "DEFAULT"; stim_file: string :="code.txt"); port(clk : in std_logic; enable : in std_logic; reset : in std_logic; write_byte_enable : in std_logic_vector(3 downto 0); address : in std_logic_vector(31 downto 2); data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0)); end component; --ram component NI generic(current_address : integer := 10 -- the current node's address ); -- reserved address for the counter port(clk : in std_logic; reset : in std_logic; enable : in std_logic; write_byte_enable : in std_logic_vector(3 downto 0); address : in std_logic_vector(31 downto 2); data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); --NI_read_flag : out std_logic; --NI_write_flag : out std_logic; irq_out : out std_logic; credit_in : in std_logic; valid_out: out std_logic; TX: out std_logic_vector(31 downto 0); credit_out : out std_logic; valid_in: in std_logic; RX: in std_logic_vector(31 downto 0) ); end component; --network interface component uart generic(log_file : string := "UNUSED"); port(clk : in std_logic; reset : in std_logic; enable_read : in std_logic; enable_write : in std_logic; data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); uart_read : in std_logic; uart_write : out std_logic; busy_write : out std_logic; data_avail : out std_logic; reg_enable : in std_logic; reg_write_byte_enable : in std_logic_vector(3 downto 0); reg_address : in std_logic_vector(31 downto 2); reg_data_write : in std_logic_vector(31 downto 0); reg_data_read : out std_logic_vector(31 downto 0) ); end component; --uart component eth_dma port(clk : in std_logic; --25 MHz reset : in std_logic; enable_eth : in std_logic; select_eth : in std_logic; rec_isr : out std_logic; send_isr : out std_logic; address : out std_logic_vector(31 downto 2); --to DDR byte_we : out std_logic_vector(3 downto 0); data_write : out std_logic_vector(31 downto 0); data_read : in std_logic_vector(31 downto 0); pause_in : in std_logic; mem_address : in std_logic_vector(31 downto 2); --from CPU mem_byte_we : in std_logic_vector(3 downto 0); data_w : in std_logic_vector(31 downto 0); pause_out : out std_logic; E_RX_CLK : in std_logic; --2.5 MHz receive E_RX_DV : in std_logic; --data valid E_RXD : in std_logic_vector(3 downto 0); --receive nibble E_TX_CLK : in std_logic; --2.5 MHz transmit E_TX_EN : out std_logic; --transmit enable E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble end component; --eth_dma component plasma generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM"; log_file : string := "UNUSED"; ethernet : std_logic := '0'; use_cache : std_logic := '0'; current_address : integer := 10; stim_file: string :="code.txt"); port(clk : in std_logic; reset : in std_logic; uart_write : out std_logic; uart_read : in std_logic; address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_write : out std_logic_vector(31 downto 0); data_read : in std_logic_vector(31 downto 0); mem_pause_in : in std_logic; no_ddr_start : out std_logic; no_ddr_stop : out std_logic; gpio0_out : out std_logic_vector(31 downto 0); gpioA_in : in std_logic_vector(31 downto 0); credit_in : in std_logic; valid_out: out std_logic; TX: out std_logic_vector(31 downto 0); credit_out : out std_logic; valid_in: in std_logic; RX: in std_logic_vector(31 downto 0) ); end component; --plasma component ddr_ctrl port(clk : in std_logic; clk_2x : in std_logic; reset_in : in std_logic; address : in std_logic_vector(25 downto 2); byte_we : in std_logic_vector(3 downto 0); data_w : in std_logic_vector(31 downto 0); data_r : out std_logic_vector(31 downto 0); active : in std_logic; no_start : in std_logic; no_stop : in std_logic; pause : out std_logic; SD_CK_P : out std_logic; --clock_positive SD_CK_N : out std_logic; --clock_negative SD_CKE : out std_logic; --clock_enable SD_BA : out std_logic_vector(1 downto 0); --bank_address SD_A : out std_logic_vector(12 downto 0); --address(row or col) SD_CS : out std_logic; --chip_select SD_RAS : out std_logic; --row_address_strobe SD_CAS : out std_logic; --column_address_strobe SD_WE : out std_logic; --write_enable SD_DQ : inout std_logic_vector(15 downto 0); --data SD_UDM : out std_logic; --upper_byte_enable SD_UDQS : inout std_logic; --upper_data_strobe SD_LDM : out std_logic; --low_byte_enable SD_LDQS : inout std_logic); --low_data_strobe end component; --ddr component memory generic(address_width : natural := 16); port(clk : in std_logic; address : in std_logic_vector(31 downto 2); data_write : in std_logic_vector(31 downto 0); pause : in std_logic; byte_we : in std_logic_vector(3 downto 0); data_read : out std_logic_vector(31 downto 0) ); end component; --entity memory end; --package mlite_pack package body mlite_pack is function bv_adder(a : in std_logic_vector; b : in std_logic_vector; do_add: in std_logic) return std_logic_vector is variable A1, B1, S : UNSIGNED(a'length downto 0); begin A1 := resize(unsigned(a), A1'length); B1 := resize(unsigned(b), B1'length); if do_add = '1' then S := A1 + B1; else S := A1 - B1; end if; return std_logic_vector(S); end; --function function bv_negate(a : in std_logic_vector) return std_logic_vector is variable carry_in : std_logic; variable not_a : std_logic_vector(a'length-1 downto 0); variable result : std_logic_vector(a'length-1 downto 0); begin not_a := not a; carry_in := '1'; for index in a'reverse_range loop result(index) := not_a(index) xor carry_in; carry_in := carry_in and not_a(index); end loop; return result; end; --function function bv_increment(a : in std_logic_vector(31 downto 2) ) return std_logic_vector is variable carry_in : std_logic; variable result : std_logic_vector(31 downto 2); begin carry_in := '1'; for index in 2 to 31 loop result(index) := a(index) xor carry_in; carry_in := a(index) and carry_in; end loop; return result; end; --function function bv_inc(a : in std_logic_vector ) return std_logic_vector is variable carry_in : std_logic; variable result : std_logic_vector(a'length-1 downto 0); begin carry_in := '1'; for index in 0 to a'length-1 loop result(index) := a(index) xor carry_in; carry_in := a(index) and carry_in; end loop; return result; end; --function end; --package body
gpl-3.0
7a35dcf024d9f0080b1bc48a525a2374
0.54406
3.668346
false
false
false
false
SKravitsky/ECEC412
DataMemory.vhd
1
933
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity DataMemory is port( WriteData: in std_logic_vector(31 downto 0); Address: in std_logic_vector(31 downto 0); Clk, MemRead, MemWrite: in std_logic; ReadData: out std_logic_vector(31 downto 0) ); end DataMemory; architecture Structural of DataMemory is type mem_array is array(0 to 32) of std_logic_vector(31 downto 0); signal data_mem: mem_array := ( 1 => X"00000004", 2 => X"00000005", others => X"00000000" ); signal tempData: std_logic_vector(31 downto 0) := X"00000000"; begin ReadData <= tempData; process(Clk) begin if falling_edge(Clk) then if MemWrite = '1' then data_mem(to_integer(unsigned(Address)) / 4) <= WriteData; end if; if MemRead = '1' then tempData <= data_mem(to_integer(unsigned(Address)) / 4); end if; end if; end process; end Structural;
apache-2.0
57a5a9a8ea97ee0c7ac1f9821eae2658
0.650589
3.380435
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/immortal_temp_iddt_monitor_instrument.vhd
3
6,590
--Copyright (C) 2017 Konstantin Shibin ------------------------------------------------------------ -- File name: immortal_temp_iddt_monitor_instrument.vhd ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; USE ieee.numeric_std.ALL; entity immortal_temp_iddt_monitor_instrument is port ( -- IJTAG connection TCK : in std_logic; RST : in std_logic; SEL : in std_logic; SI : in std_logic; SE : in std_logic; UE : in std_logic; CE : in std_logic; SO : out std_logic; toF : out std_logic; toC : out std_logic; -- Monitor connections control : out std_logic_vector(2 downto 0); adc_data : in std_logic_vector(11 downto 0); adc_drdy : in std_logic ); end immortal_temp_iddt_monitor_instrument; architecture rtl of immortal_temp_iddt_monitor_instrument is component SReg is Generic ( Size : positive := 32); Port ( -- Scan Interface scan_client ---------- SI : in STD_LOGIC; -- ScanInPort SO : out STD_LOGIC; -- ScanOutPort SEL : in STD_LOGIC; -- SelectPort ---------------------------------------- SE : in STD_LOGIC; -- ShiftEnPort CE : in STD_LOGIC; -- CaptureEnPort UE : in STD_LOGIC; -- UpdateEnPort RST : in STD_LOGIC; -- ResetPort TCK : in STD_LOGIC; -- TCKPort DI : in STD_LOGIC_VECTOR (Size-1 downto 0); --DataInPort DO : out STD_LOGIC_VECTOR (Size-1 downto 0)); --DataOutPort end component; signal shiftreg_update : std_logic_vector (31 downto 0); signal threshold_H : std_logic_vector (11 downto 0); signal threshold_L : std_logic_vector (11 downto 0); signal monitor_controls : std_logic_vector (2 downto 0); signal threshold_compare_dir : std_logic; signal f_output_enable : std_logic; signal threshold_H_active : std_logic; signal threshold_L_active : std_logic; signal threshold_H_GT : std_logic; signal threshold_H_LE : std_logic; signal threshold_L_GT : std_logic; signal threshold_L_LE : std_logic; signal adc_data_sync, adc_data_sync_first : std_logic_vector (11 downto 0); signal adc_data_local_copy : std_logic_vector (11 downto 0); signal adc_data_local_copy_32b : std_logic_vector (31 downto 0); signal adc_drdy_sync, adc_drdy_sync_first : std_logic; signal adc_drdy_prev, adc_drdy_strobe : std_logic; signal UE_prev, update_strobe : std_logic; begin -- Shift register for capturing data from monitor and updating control and compare threshold shiftreg : SReg Generic map ( Size => 32) Port map ( -- Scan Interface scan_client ---------- SI => SI, -- Input Port SI = SI SO => SO, SEL => SEL, SE => SE, CE => CE, UE => UE, RST => RST, TCK => TCK, DI => adc_data_local_copy_32b, DO => shiftreg_update); -- shiftreg_update description: -- [11:0] threshold A -- [23:12] threshold B -- [24] threshold comparison direction: 0: adc data >= threshold; 1: adc data < threshold -- [25] F flag output enabled -- [26] update enable for threshold values, comp direction, f enable -- [30:28] control signals -- [31] control signals update enable synchronizer_adc : process(TCK,RST) begin if RST = '1' then adc_data_sync_first <= (others => '0'); adc_data_sync <= (others => '0'); elsif TCK'event and TCK = '1' then adc_data_sync_first <= adc_data; adc_data_sync <= adc_data_sync_first; end if; end process; -- synchronizer adc_data_copy: process(TCK, RST) begin if RST = '1' then adc_data_local_copy <= (others => '0'); adc_drdy_sync_first <= '0'; adc_drdy_sync <= '0'; adc_drdy_prev <= '0'; adc_drdy_strobe <= '0'; elsif TCK'event and TCK = '1' then adc_drdy_sync_first <= adc_drdy; adc_drdy_sync <= adc_drdy_sync_first; adc_drdy_prev <= adc_drdy_sync; adc_drdy_strobe <= not adc_drdy_prev and adc_drdy_sync; if adc_drdy_strobe = '1' then adc_data_local_copy <= adc_data_sync; end if; end if; end process; adc_data_local_copy_32b <= "00000000000000000000" & adc_data_local_copy; update_strobes: process(TCK) begin if TCK'event and TCK = '0' then UE_prev <= UE; update_strobe <= not UE_prev and UE and SEL; end if; end process; threshold_controls_set: process(TCK, RST) begin if RST = '1' then threshold_H <= (others => '0'); threshold_L <= (others => '0'); threshold_compare_dir <= '0'; f_output_enable <= '0'; monitor_controls <= (others => '0'); elsif TCK'event and TCK = '0' then if update_strobe = '1' then if shiftreg_update(26) = '1' then -- update thresholds only when bit 26 allows it threshold_H <= shiftreg_update(11 downto 0); threshold_L <= shiftreg_update(23 downto 12); threshold_compare_dir <= shiftreg_update(24); f_output_enable <= shiftreg_update(25); end if; if shiftreg_update(31) = '1' then -- update controls only when bit 31 allows it monitor_controls <= shiftreg_update(30 downto 28); end if; end if; end if; end process; control <= monitor_controls; threshold_H_GT <= '1' when (to_integer(unsigned(threshold_H)) > to_integer(unsigned(adc_data_local_copy))) else '0'; threshold_H_LE <= '1' when (to_integer(unsigned(threshold_H)) <= to_integer(unsigned(adc_data_local_copy))) else '0'; threshold_L_GT <= '1' when (to_integer(unsigned(threshold_L)) > to_integer(unsigned(adc_data_local_copy))) else '0'; threshold_L_LE <= '1' when (to_integer(unsigned(threshold_L)) <= to_integer(unsigned(adc_data_local_copy))) else '0'; threshold_H_active <= (threshold_H_GT and threshold_compare_dir) or (threshold_H_LE and not threshold_compare_dir); threshold_L_active <= (threshold_L_GT and threshold_compare_dir) or (threshold_L_LE and not threshold_compare_dir); toF <= (threshold_H_active or threshold_L_active) and f_output_enable; toC <= not (threshold_H_active and f_output_enable); end;
gpl-3.0
6d8eb40db87fdaaf6307480e7fabc6b2
0.567223
3.560238
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/Allocator_with_checkers/allocator_credit_counter_logic_pseudo_checkers.vhd
3
15,296
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity allocator_credit_counter_logic_pseudo_checkers is port ( -- flow control credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic; credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0); valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid ! credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0); -- Checker outputs err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_N_credit_counter_N_out_increment, err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change, err_grant_N_credit_counter_N_out_decrement, err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change, err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_E_credit_counter_E_out_increment, err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change, err_grant_E_credit_counter_E_out_decrement, err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change, err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_W_credit_counter_W_out_increment, err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change, err_grant_W_credit_counter_W_out_decrement, err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change, err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_S_credit_counter_S_out_increment, err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change, err_grant_S_credit_counter_S_out_decrement, err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change, err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal, err_credit_in_L_credit_counter_L_out_increment, err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change, err_grant_L_credit_counter_L_out_decrement, err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change, err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic ); end allocator_credit_counter_logic_pseudo_checkers; architecture behavior of allocator_credit_counter_logic_pseudo_checkers is begin -- The combionational part ---------------------------------------------------------------- -- Checkers for the process handling the credit counters -- North credit counter process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out) begin if (credit_in_N = '1' and valid_N = '1' and credit_counter_N_in /= credit_counter_N_out) then err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1'; else err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0'; end if; end process; process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out) begin if (credit_in_N = '1' and valid_N = '0' and credit_counter_N_out < 3 and credit_counter_N_in /= credit_counter_N_out + 1) then err_credit_in_N_credit_counter_N_out_increment <= '1'; else err_credit_in_N_credit_counter_N_out_increment <= '0'; end if; end process; process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out) begin if (credit_in_N = '1' and valid_N = '0' and credit_counter_N_out = 3 and credit_counter_N_in /= credit_counter_N_out) then err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '1'; else err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '0'; end if; end process; process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out) begin if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out > 0 and credit_counter_N_in /= credit_counter_N_out - 1) then err_grant_N_credit_counter_N_out_decrement <= '1'; else err_grant_N_credit_counter_N_out_decrement <= '0'; end if; end process; process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out) begin if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out = 0 and credit_counter_N_in /= credit_counter_N_out) then err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '1'; else err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '0'; end if; end process; process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out) begin if (credit_in_N = '0' and valid_N = '0' and credit_counter_N_in /= credit_counter_N_out) then err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1'; else err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0'; end if; end process; -- East credit counter process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out) begin if (credit_in_E = '1' and valid_E = '1' and credit_counter_E_in /= credit_counter_E_out) then err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1'; else err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0'; end if; end process; process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out) begin if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out < 3 and credit_counter_E_in /= credit_counter_E_out + 1) then err_credit_in_E_credit_counter_E_out_increment <= '1'; else err_credit_in_E_credit_counter_E_out_increment <= '0'; end if; end process; process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out) begin if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out = 3 and credit_counter_E_in /= credit_counter_E_out) then err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '1'; else err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '0'; end if; end process; process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out) begin if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out > 0 and credit_counter_E_in /= credit_counter_E_out - 1) then err_grant_E_credit_counter_E_out_decrement <= '1'; else err_grant_E_credit_counter_E_out_decrement <= '0'; end if; end process; process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out) begin if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out = 0 and credit_counter_E_in /= credit_counter_E_out) then err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '1'; else err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '0'; end if; end process; process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out) begin if (credit_in_E = '0' and valid_E = '0' and credit_counter_E_in /= credit_counter_E_out) then err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1'; else err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0'; end if; end process; -- West credit counter process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out) begin if (credit_in_W = '1' and valid_W = '1' and credit_counter_W_in /= credit_counter_W_out) then err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1'; else err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0'; end if; end process; process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out) begin if (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out < 3 and credit_counter_W_in /= credit_counter_W_out + 1) then err_credit_in_W_credit_counter_W_out_increment <= '1'; else err_credit_in_W_credit_counter_W_out_increment <= '0'; end if; end process; process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out) begin if ( (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out = 3) and credit_counter_W_in /= credit_counter_W_out) then err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '1'; else err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '0'; end if; end process; process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out) begin if (valid_W = '1' and credit_in_W = '0' and credit_counter_W_out > 0 and credit_counter_W_in /= credit_counter_W_out - 1) then err_grant_W_credit_counter_W_out_decrement <= '1'; else err_grant_W_credit_counter_W_out_decrement <= '0'; end if; end process; process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out) begin if ( valid_W = '1' and credit_in_W = '0' and credit_counter_W_out = 0 and credit_counter_W_in /= credit_counter_W_out) then err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '1'; else err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '0'; end if; end process; process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out) begin if (credit_in_W = '0' and valid_W = '0' and credit_counter_W_in /= credit_counter_W_out) then err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1'; else err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0'; end if; end process; -- South credit counter process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out) begin if (credit_in_S = '1' and valid_S = '1' and credit_counter_S_in /= credit_counter_S_out) then err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1'; else err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0'; end if; end process; process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out) begin if (credit_in_S = '1' and valid_S = '0' and credit_counter_S_out < 3 and credit_counter_S_in /= credit_counter_S_out + 1) then err_credit_in_S_credit_counter_S_out_increment <= '1'; else err_credit_in_S_credit_counter_S_out_increment <= '0'; end if; end process; process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out) begin if ( credit_in_S = '1' and valid_S = '0' and credit_counter_S_out = 3 and credit_counter_S_in /= credit_counter_S_out) then err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '1'; else err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '0'; end if; end process; process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out) begin if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out > 0 and credit_counter_S_in /= credit_counter_S_out - 1) then err_grant_S_credit_counter_S_out_decrement <= '1'; else err_grant_S_credit_counter_S_out_decrement <= '0'; end if; end process; process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out) begin if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out = 0 and credit_counter_S_in /= credit_counter_S_out) then err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '1'; else err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '0'; end if; end process; process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out) begin if (credit_in_S = '0' and valid_S = '0' and credit_counter_S_in /= credit_counter_S_out) then err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1'; else err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0'; end if; end process; -- Local credit counter process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out) begin if (credit_in_L = '1' and valid_L = '1' and credit_counter_L_in /= credit_counter_L_out) then err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1'; else err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0'; end if; end process; process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out) begin if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out < 3 and credit_counter_L_in /= credit_counter_L_out + 1) then err_credit_in_L_credit_counter_L_out_increment <= '1'; else err_credit_in_L_credit_counter_L_out_increment <= '0'; end if; end process; process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out) begin if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out = 3 and credit_counter_L_in /= credit_counter_L_out) then err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '1'; else err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '0'; end if; end process; process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out) begin if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out > 0 and credit_counter_L_in /= credit_counter_L_out - 1) then err_grant_L_credit_counter_L_out_decrement <= '1'; else err_grant_L_credit_counter_L_out_decrement <= '0'; end if; end process; process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out) begin if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out = 0 and credit_counter_L_in /= credit_counter_L_out) then err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '1'; else err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '0'; end if; end process; process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out) begin if (credit_in_L = '0' and valid_L = '0' and credit_counter_L_in /= credit_counter_L_out) then err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1'; else err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0'; end if; end process; END;
gpl-3.0
09e9d7730a9ace70912a59aba759be18
0.667233
2.697232
false
false
false
false
simoesusp/Processador-ICMC
Processor_FPGA/Processor_Template_VHDL_DE70/REG.vhd
3
597
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; ENTITY REG IS PORT( CLK : IN STD_LOGIC; CLR : IN STD_LOGIC; LOAD : IN STD_LOGIC; I : IN STD_LOGIC_VECTOR(15 DOWNTO 0); O : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END REG; ARCHITECTURE main OF REG IS BEGIN PROCESS(CLK, CLR) VARIABLE DATA : STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN IF(CLR = '1') THEN DATA := x"0000"; O <= x"0000"; ELSIF(CLK'EVENT AND CLK = '1') THEN IF(LOAD = '1') THEN DATA := I; END IF; END IF; O <= DATA; END PROCESS; END main;
gpl-3.0
afee691d9e841157aa591783b2fc800e
0.626466
2.584416
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/ram_xilinx_0.vhd
3
181,455
--------------------------------------------------------------------- -- TITLE: Random Access Memory for Xilinx -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 11/06/05 -- FILENAME: ram_xilinx.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements Plasma internal RAM as RAMB for Spartan 3x -- -- Compile the MIPS C and assembly code into "test.axf". -- Run convert.exe to change "test.axf" to "code.txt" which -- will contain the hex values of the opcodes. -- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd", -- to create the "ram_image.vhd" file that will have the opcodes -- correctly placed inside the INIT_00 => strings. -- Then include ram_image.vhd in the simulation/synthesis. -- -- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache -- if the DDR cache is enabled. --------------------------------------------------------------------- -- UPDATED: 09/07/10 Olivier Rinaudo ([email protected]) -- new behaviour: 8KB expandable to 64KB of internal RAM -- -- MEMORY MAP -- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache) -- 2000..3FFF : 8KB 16KB block1 -- 4000..5FFF : 8KB 24KB block2 -- 6000..7FFF : 8KB 32KB block3 -- 8000..9FFF : 8KB 40KB block4 -- A000..BFFF : 8KB 48KB block5 -- C000..DFFF : 8KB 56KB block6 -- E000..FFFF : 8KB 64KB block7 --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use work.mlite_pack.all; library UNISIM; use UNISIM.vcomponents.all; entity ram_0 is generic(memory_type : string := "DEFAULT"; --Number of 8KB blocks of internal RAM, up to 64KB (1 to 8) block_count : integer := 8); port(clk : in std_logic; enable : in std_logic; reset : in std_logic; write_byte_enable : in std_logic_vector(3 downto 0); address : in std_logic_vector(31 downto 2); data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0)); end; --entity ram architecture logic of ram_0 is --type type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0); --Which 8KB block alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13); --Address within a 8KB block (without lower two bits) alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2); --Block enable with 1 bit per memory block signal block_enable: std_logic_vector(7 downto 0); --Block Data Out signal block_do: mem32_vector(7 downto 0); --Remember which block was selected signal block_sel_buf: std_logic_vector(2 downto 0); begin block_enable<= "00000001" when (enable='1') and (block_sel="000") else "00000010" when (enable='1') and (block_sel="001") else "00000100" when (enable='1') and (block_sel="010") else "00001000" when (enable='1') and (block_sel="011") else "00010000" when (enable='1') and (block_sel="100") else "00100000" when (enable='1') and (block_sel="101") else "01000000" when (enable='1') and (block_sel="110") else "10000000" when (enable='1') and (block_sel="111") else "00000000"; proc_blocksel: process (clk, block_sel) is begin if rising_edge(clk) then block_sel_buf <= block_sel; end if; end process; proc_do: process (block_do, block_sel_buf) is begin data_read <= block_do(conv_integer(block_sel_buf)); end process; -- BLOCKS generation block0: if (block_count > 0) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"afafafafafafafafafafafafafafafaf2308000c241400ac273c243c243c273c", INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f230c008c8c3caf00af00af2340afaf", INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f", INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac", INIT_04 => X"8c343c00af03af270003278f0300ac008f34af0000000014008f8fafaf03af27", INIT_05 => X"008f000c2400142480008f0010af03afaf270003278f0300ac008f3c00103000", INIT_06 => X"008f8f0010af24af03afaf270003278f8f030000140080008f000c000080af24", INIT_07 => X"03000004008faf24008f000c0024008f0010000c0024008f00102c008faf3000", INIT_08 => X"0c000080af24008f0010af27000c8f008f002727afafaf03afaf270003278f8f", INIT_09 => X"3c03af270003278f8f030000140080008fa0248faf24008f0014248024008f00", INIT_0A => X"0000000003278f8f030000008c3c0010000c0003afaf270003278f0330008c34", INIT_0B => X"243c000c343c243c24000c343c243c24000c243c000c243c000c243c03afaf27", INIT_0C => X"24243c243c243caf243caf24000c24243c243c243caf243caf24000c243c000c", INIT_0D => X"000c343c243c243c243caf243caf24000c343c243c243c243caf243caf24000c", INIT_0E => X"243c000c000c243c000c243c000c000c243c000c243c000c000c243c000c243c", INIT_0F => X"3c000c243c0010000c243c0014008c3c000c243c000c243c000c000c243c000c", INIT_10 => X"af240010af24afaf03afaf270003278f8f0300000c24000c0024008c3c000c24", INIT_11 => X"0c8f24000010008f001400008f8faf24008f0010af001400000014008f8f0010", INIT_12 => X"24008faf240010008f8c002400008f3c000c0024008c002400008f3c000c2400", INIT_13 => X"0c243c0010ac3c24008c3c000c243c0014248f001428008faf24008f000c24af", INIT_14 => X"0087000c24000c8faf00008f870010a7afafafaf03afaf270003278f8f030000", INIT_15 => X"0087a730240097af240010008f8c00008f000087000c24000c00008c00008f00", INIT_16 => X"000c243c0010ac3c24008c3c000c243c0014248f000c8f2400000c243c001428", INIT_17 => X"87000c24000c8faf0000008f870010a7afafafafaf03afaf270003278f8f0300", INIT_18 => X"87a730240097af240010008f8c00008f000087000c24000c00008c00008f0000", INIT_19 => X"008c00008f000087000c24000c8faf0000008f2400870010a7000c2400142800", INIT_1A => X"000c240014280087a730240097af240010008f8c00008f000087000c24000c00", INIT_1B => X"000c00008c00008f0000343c87000c24000c8faf0000000014008f870010a724", INIT_1C => X"24000c240014280087a730240097af240010008f8c00008f0000343c87000c24", INIT_1D => X"0c24000c00008c00008f0000343c87000c24000c8faf00000014008f870010a7", INIT_1E => X"2400000c243c0014280087a730240097af240010008f8c00008f0000343c8700", INIT_1F => X"af270003278f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c8f", INIT_20 => X"0c24000c00008c002400008f3c000c24000c8faf00008f8f0010afafaf2403af", INIT_21 => X"008f8f0010af000c24001428008faf24008faf240010008f8c002400008f3c00", INIT_22 => X"10008f8c002400008f3c000c24000c00008c002400008f3c000c24000c8faf00", INIT_23 => X"0010ac3c24008c3c000c243c0014248f000c243c001428008faf24008faf2400", INIT_24 => X"8f0000008fa000278f0000008f0010afaf03afaf270003278f8f0300000c243c", INIT_25 => X"00af008000278f0010af001428008faf24008fac008f002700008fa400270000", INIT_26 => X"10008f8c002400008f3c000c24000c0024008c002400008f3c000c24000c8f24", INIT_27 => X"24000c0024008c002400008f3c000c24000c8f2400af0084002700008faf2400", INIT_28 => X"3c000c24000c8f2400af008c002700008faf240010008f8c002400008f3c000c", INIT_29 => X"8faf24008faf240010008f8c002400008f3c000c24000c0024008c002400008f", INIT_2A => X"8f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c243c00142800", INIT_2B => X"000c24000c00008c3c000c24000c8faf00008f8fafaf24af2403afaf27000327", INIT_2C => X"8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f8c3c", INIT_2D => X"008f8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f", INIT_2E => X"240010008f8c243c000c24000c00008c243c000c24000c8faf00008faf240010", INIT_2F => X"008faf240010008f8c243c000c24000c00008c243c000c24000c8faf24008faf", INIT_30 => X"0014248f000c243caf240010008f8c243c000c00008c243c000c24000c8faf24", INIT_31 => X"28008c3caf03af27000003278f8f0300000c243c0010ac3c24008c3c000c243c", INIT_32 => X"a324af03af270003278f0324001000ac3c24008c3cac008f0024003c8c3c0010", INIT_33 => X"14003c8c340010240010248c3c00100083a4248fa3001000102400100094008f", INIT_34 => X"af270003278f0324a4008fa30010ac3cac243cac3cac008c3c240018008c3c00", INIT_35 => X"0010240010248c3c00100083a4248fa3001000102400100094008fa324afaf03", INIT_36 => X"3cac0024003c8c248c3c001028008c3c0004008f0010008faf008c34af008c34", INIT_37 => X"af008fafaf03af270003278f0324a4008fa30010ac243cac3cac3cac3c24008c", INIT_38 => X"10afafafafaf03afaf270003278f038f00140080a00080af24008faf24008f00", INIT_39 => X"8f8faf240010af240010248f0004008fa3001428008faf24008fa02400278f00", INIT_3A => X"008f001028008faf0000000014008f8faf00000014008f8f0010af24af000000", INIT_3B => X"1000008c008f00008f240014008fa000278f0000302430008f00100000302430", INIT_3C => X"8f0010008c008fa02400278faf24008f0014248f0000100004008faf24008f00", INIT_3D => X"2700248c008f0010ac008f00008f24000c8f0000008f2700100000008f248c00", INIT_3E => X"af03af270003278f0300ac343c343cafaf03af270003278f8f0300000c8f0000", INIT_3F => X"008fafaf03af270003278f038f0014008faf00008f24008faf302c008f0010af" ) port map ( DO => block_do(0)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(0), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"b8afaeadacabaaa9a8a7a6a5a4a3a2a1bd000000a560a4a0bd1d8404a5059c1c", INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9", INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf", INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594", INIT_04 => X"42420200c4a0bebd00e0bdbec0004300c302c2000007624000c2c3c5c4a0bebd", INIT_05 => X"00c20000040062024300c20000c4a0bebfbd00e0bdbec0004300c30200404200", INIT_06 => X"00c2c30000c202c4a0bebfbd00e0bdbebfc0000040004200c20000400042c343", INIT_07 => X"c000004100c2c24200c20000404200c200000000404200c200404200c2c24243", INIT_08 => X"00400042c34300c20000c2c20000c440c660c2c3c6c5c4a0bebfbd00e0bdbebf", INIT_09 => X"02a0bebd00e0bdbebfc0000040004200c24303c2c24200c2006202434200c200", INIT_0A => X"00000000e0bdbebfc002020042020040000000a0bebfbd00e0bdbec042004242", INIT_0B => X"44020000440245020600004402450206000044020000440200004402a0bebfbd", INIT_0C => X"04450246024702a24202a202000004450246024702a24202a202000044020000", INIT_0D => X"00004402450246024702a24202a20200004402450246024702a24202a2020000", INIT_0E => X"4402000000004402000044020000000044020000440200000000440200004402", INIT_0F => X"0200004402000000004402004000420200004402000044020000000044020000", INIT_10 => X"c2020000c202c0c0a0bebfbd00e0bdbebfc00000000400004005004202000044", INIT_11 => X"00c40500004000c200406200c2c3c24200c20000c000400007624000c2c30000", INIT_12 => X"4200c2c202006200c24362420300c30200004005004262420300c30200000400", INIT_13 => X"004402000043024300420200004402006202c300404200c2c24200c2000004c2", INIT_14 => X"00c20000040000c4c24300c3c20000c0c0c6c5c4a0bebfbd00e0bdbebfc00000", INIT_15 => X"00c2c2424200c2c202006200c2436200c30200c200000400004000426200c302", INIT_16 => X"00004402000043024300420200004402006202c30000c4050000004402004042", INIT_17 => X"c20000040000c4c2006200c2c30000c0c0c7c6c5c4a0bebfbd00e0bdbebfc000", INIT_18 => X"c2c2424200c2c202006200c2436200c30200c200000400004000426200c30200", INIT_19 => X"00426200c30200c20000040000c4c2006200c24300c20000c000000400404200", INIT_1A => X"00000400404200c2c2424200c2c202006200c2436200c30200c2000004000040", INIT_1B => X"00004000426200c302624202c30000040000c4c2000007624000c3c20000c202", INIT_1C => X"0200000400404200c2c2424200c2c202006200c2436200c302624202c3000004", INIT_1D => X"000400004000426200c302624202c30000040000c4c20007624000c3c20000c2", INIT_1E => X"05000000440200404200c2c2424200c2c202006200c2436200c302624202c300", INIT_1F => X"bfbd00e0bdbebfc00000004402000043024300420200004402006202c30000c4", INIT_20 => X"0004000040004262420300c3020000040000c4c26200c2c30000c0c0c202a0be", INIT_21 => X"00c2c30000c000000400404200c2c24200c2c202006200c24362420300c30200", INIT_22 => X"6200c24362420300c302000004000040004262420300c3020000040000c4c262", INIT_23 => X"000043024300420200004402006202c30000440200404200c2c24200c2c20200", INIT_24 => X"c2030200c24382c4c2030200c20000c0c0a0bebfbd00e0bdbebfc00000004402", INIT_25 => X"00c2004262c3c20000c000404200c2c24200c24300c362c30200c24382c40200", INIT_26 => X"6200c24362420300c30200000400004005004262420300c3020000040000c405", INIT_27 => X"0400004005004262420300c3020000040000c40500c2004262c30200c2c20200", INIT_28 => X"020000040000c40500c2004262c30200c2c202006200c24362420300c3020000", INIT_29 => X"c2c24200c2c202006200c24362420300c30200000400004005004262420300c3", INIT_2A => X"bebfc00000004402000043024300420200004402006202c30000440200404200", INIT_2B => X"0000040000400042020000040000c4c26200c2c3c0c202c202a0bebfbd00e0bd", INIT_2C => X"434202000004000040004242020000040000c4c26200c2c3c202006200c24302", INIT_2D => X"00c2434202000004000040004242020000040000c4c26200c2c3c202006200c2", INIT_2E => X"02006200c2434202000004000040004242020000040000c4c20200c2c2020062", INIT_2F => X"00c2c202006200c2434202000004000040004242020000040000c4c24200c2c2", INIT_30 => X"006202c300004402c202006200c2434202000040004242020000040000c4c242", INIT_31 => X"42004202c4a0bebd0000e0bdbebfc00000004402000043024300420200004402", INIT_32 => X"c202c4a0bebd00e0bdbec0020000004302430042024300c36242030243020040", INIT_33 => X"40620243020000020062024302004000c24303c2c000000043030040004200c2", INIT_34 => X"bebd00e0bdbec0024000c2c00000400243030240024300630302004000420200", INIT_35 => X"0000020062024302004000c24303c2c000000043030040004200c2c202c0c4a0", INIT_36 => X"02438242040243024402004042004202004000c2004000c2c2004202c2004202", INIT_37 => X"c200c2c5c4a0bebd00e0bdbec0024000c2c00000430302400240024302430042", INIT_38 => X"00c0c7c6c5c4a0bebfbd00e0bdbec0c200400042430063c46400c3c34300c200", INIT_39 => X"c2c3c2020000c202006202c3004100c2c000404200c2c24200c2430362c3c200", INIT_3A => X"00c200404200c2c2000007624000c3c2c20007624000c3c20000c202c2006200", INIT_3B => X"4062004200c26200c203004000c26283c4c3020242424200c200000202424242", INIT_3C => X"c20040004200c2430362c3c2c24200c2006202c3000000004100c2c24200c200", INIT_3D => X"c362034200c200004300c26200c2030000c4406200c2c30040628200c2044300", INIT_3E => X"c4a0bebd00e0bdbec0004363034202c5c4a0bebd00e0bdbebfc0000000c44062", INIT_3F => X"00c2c5c4a0bebd00e0bdbec0c2004000c2c26200c34200c2c2424200c20000c0" ) port map ( DO => block_do(0)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(0), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"00000000000000000000000000000000ff00000800ff1800350035003300b200", INIT_01 => X"000000000000000000000000000000000000072000002000d800d800ff700000", INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000", INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000", INIT_04 => X"0000200000f000ff00000000e800000000800010100000000000000000f000ff", INIT_05 => X"0000000000000000000000000000f00000ff00000000e8000000002000ff0000", INIT_06 => X"0000000000000000f00000ff0000000000e80000ff0000000000002000000000", INIT_07 => X"e80000ff000000ff000000002000000000000000200000000000000000000010", INIT_08 => X"0020000000000000000000000007002800380000000000f00000ff0000000000", INIT_09 => X"20f000ff0000000000e80000ff0000000000000000ff000000000000ff000000", INIT_0A => X"0000000000000000e8161600002000ff000100f00000ff00000000e800000000", INIT_0B => X"2a00000256922700000002561227000000002a0000002a0000002a00f00000ff", INIT_0C => X"032800280028000028000000000200280028002800002800000000002a000000", INIT_0D => X"0002230029002900290000290000000002430028002900290000290000000002", INIT_0E => X"2a00000400002a0000002a00000500002a0000002a00000300002a0000002a00", INIT_0F => X"0000002b00000000002b00000000330000002b0000002b00000200002a000000", INIT_10 => X"0000000000000000f00000ff0000000000e8000000000001200030330000002b", INIT_11 => X"010000300000000000ff10000000000000000000000000100000000000000000", INIT_12 => X"0000000000000000000010241800000000012000300010241800000000000000", INIT_13 => X"002b00000033000000330000002b000000000000ff0300000000000000000000", INIT_14 => X"0000000000000000001000000000000000000000f00000ff0000000000e80000", INIT_15 => X"000000ff00000000000000000000100000100000000000000020000010000010", INIT_16 => X"00002b00000033000000330000002b0000000000000100003000002b0000ff00", INIT_17 => X"000000000000000010000000000000000000000000f00000ff0000000000e800", INIT_18 => X"0000ff0000000000000000000010000010000000000000002000001000001000", INIT_19 => X"0000100000100000000000000000001000000001000000000000000000ff0000", INIT_1A => X"00000000ff00000000ff00000000000000000000100000100000000000000020", INIT_1B => X"00002000001000001010ff3f0000000000000000101000000000000000000000", INIT_1C => X"0000000000ff00000000ff000000000000000000001000001010ff3f00000000", INIT_1D => X"000000002000001000001010ff3f000000000000000010000000000000000000", INIT_1E => X"003000002b0000ff00000000ff000000000000000000001000001010ff3f0000", INIT_1F => X"00ff0000000000e80000002b00000033000000330000002b0000000000000100", INIT_20 => X"000000002000001029180000000000000000000010000000000000000012f000", INIT_21 => X"00000000000000000000ff000000000000000000000000000010291800000000", INIT_22 => X"00000000102a180000000000000000200000102a180000000000000000000010", INIT_23 => X"000033000000330000002b000000000000002c0000ff00000000000000000000", INIT_24 => X"001c1c0000001000001e1e000000000000f00000ff0000000000e80000002b00", INIT_25 => X"3000000010000000000000ff0000000000000000000010001000000010001000", INIT_26 => X"00000000102c18000000000000000120003000102c1800000000000000010000", INIT_27 => X"00000120003000102c1800000000000000010000300000001000100000000000", INIT_28 => X"000000000001000030000000100010000000000000000000102c180000000000", INIT_29 => X"000000000000000000000000102c18000000000000000120003000102c180000", INIT_2A => X"0000e80000002b00000033000000330000002b000000000000002c0000ff0000", INIT_2B => X"000000000020002c0000000000000000100000000000430012f00000ff000000", INIT_2C => X"002c0000000000002000002c0000000000000000100000000000000000002c00", INIT_2D => X"0000002c0000000000002000002c000000000000000010000000000000000000", INIT_2E => X"0000000000002c0000000000002000002c000000000000000010000000000000", INIT_2F => X"0000000000000000002c0000000000002000002c000000000000000000000000", INIT_30 => X"0000000000002c00000000000000002c0000002000002c0000000000000000ff", INIT_31 => X"0000330000f000ff000000000000e80000002b00000033000000330000002b00", INIT_32 => X"000000f000ff00000000e8ff0000103300000033000000001035180033000000", INIT_33 => X"0010400080000000000000320000000000000000000000000000000000000000", INIT_34 => X"00ff00000000e8000000000000ff33003300003200000035007f000000330000", INIT_35 => X"00000000000033000000000000000000000000000000000000000000000000f0", INIT_36 => X"000010352000007f330000000000330000000000000000000000008000000080", INIT_37 => X"0000000000f000ff00000000e8000000000000ff330000330032003300000033", INIT_38 => X"000000000000f00000ff00000000e80000ff0000000000000000000000000000", INIT_39 => X"000000ff0000000000000000000000000000ff00000000000000000010000000", INIT_3A => X"0000000000000000101000000000000000100000000000000000000000100000", INIT_3B => X"0010000000001800000000000000001800001616000000000000001616000000", INIT_3C => X"00000000000000000010000000ff00000000ff0000000000ff000000ff000000", INIT_3D => X"0010000000000000000000180000000006002810000000000010100000000000", INIT_3E => X"00f000ff00000000e80000fc0000200000f000ff0000000000e8000006002810", INIT_3F => X"00000000f000ff00000000e80000ff000000100000ff00000000000000000000" ) port map ( DO => block_do(0)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(0), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"4c4844403c3834302c2824201c181410980e00ac04fd2a001800b0000000f001", INIT_01 => X"504c4844403c3834302c2824201c18141000cc2410200060125c1058fc005450", INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854", INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410", INIT_04 => X"00200000082504f80008100c2500000000100012100d1b020014101410250cf0", INIT_05 => X"001800980d00040a000018001318251014e80008080425000000080000fa0200", INIT_06 => X"001020001e101c2025181ce00008181014250000e90000001800982500001801", INIT_07 => X"250000e0001010fc0010009825570014000700982530001400090a0014140f06", INIT_08 => X"9825000010010010001810140016a025a42514a8a8a4a025989c60000820181c", INIT_09 => X"002504f80008a0989c250000e400000010000d1010ff001000080a00ff001000", INIT_0A => X"000000000818101425030000000000fd003c00251014e8000808042501000020", INIT_0B => X"8000008878348c0002008878340c000100ae680000ae540000ae3c0025181ce0", INIT_0C => X"2184009c00b40010d800140200e7070c0024003c00106000140100ae680000ae", INIT_0D => X"00e7450174008c00a40010c800140400e72105fc0014002c00105000140300e7", INIT_0E => X"f800008b00ae680000aee000006300ae680000aec80000fe00ae680000aea800", INIT_0F => X"0000ae5000001300ae4800000700100000ae380000ae2800001400ae680000ae", INIT_10 => X"1403004b10031c18252024d8000820181c250000980a0005250a25100000ae5c", INIT_11 => X"05100a250026001400eb2a00101414020014000b140004100d1a020014100011", INIT_12 => X"0100181c0100030010002170800018000005250a250021708000180000983a00", INIT_13 => X"ae9c00000510000100100000ae7400000d011c00b2e800101002001000982018", INIT_14 => X"001000983a00d4181807002810002c1014302c28252024d80008282024250000", INIT_15 => X"001010ff0100101401000300180021002c80001000982000d425000021002c80", INIT_16 => X"00aee400000510000100100000aed800000d01140005300a2500aec40000d120", INIT_17 => X"1000983a00d418181218002810002d101434302c28252024d800082820242500", INIT_18 => X"1010ff0100101401000300180021002c80001000982000d425000021002c8000", INIT_19 => X"000021003080001000983a00d4181812180028230010002f1000980a00d00600", INIT_1A => X"00980a00ce06001010ff0100101401000300180021003080001000982000d425", INIT_1B => X"00d42500002100348021ffff1000983a00d4181812100d1a0200281000341001", INIT_1C => X"0100980a00c90a001010ff010010140100030018002100348021ffff10009820", INIT_1D => X"982000d42500002100388021ffff1000983a00d41818100d1a02002810003310", INIT_1E => X"0a2500aef00000ca0a001010ff010010140100030018002100388021ffff1000", INIT_1F => X"24d80008282024250000aee400000510000100100000aed800000d011400053c", INIT_20 => X"982000d425000021ec8000100000983a00d41c1c21001018002b101418342520", INIT_21 => X"001018002b1000980a00d20a00101001001014010003001c0021ec8000100000", INIT_22 => X"03001c0021148000100000982000d425000021148000100000983a00d41c1c23", INIT_23 => X"000510000100100000aed800000d011400ae140000d20a001010010010140100", INIT_24 => X"10030000100c21101003000010001f1014259094680008282024250000aee400", INIT_25 => X"2518000c21101000871000de0a0010100100103c001021108000101c21104000", INIT_26 => X"030018002158800010000098200005250a250021588000100000983a0005180a", INIT_27 => X"200005250a250021588000100000983a0005180a2518001c2110400010140100", INIT_28 => X"0000983a0005180a2518003c2110800010140100030018002158800010000098", INIT_29 => X"10100100101401000300180021588000100000980a0005250a25002158800010", INIT_2A => X"9094250000aee400000510000100100000aed800000d011400ae300000760a00", INIT_2B => X"00982000d42500800000983a00d41c1c240018141018211434252024d8000898", INIT_2C => X"04800000982000d4250004800000983a00d41c1c2500181410010003001c8000", INIT_2D => X"001c08800000982000d4250008800000983a00d41c1c2600181410010003001c", INIT_2E => X"010003001c0c800000982000d425000c800000983a00d41c1c27001410010003", INIT_2F => X"001410010003001c10800000982000d4250010800000983a00d41c1c12001410", INIT_30 => X"000d011000ae400010010003001c14800000d4250014800000983a00d41c1cee", INIT_31 => X"0f002400082504f8000008282024250000aee400000510000100100000aed800", INIT_32 => X"000110250cf00008080425ff0002252400010024000000082130800024000013", INIT_33 => X"0b24000000001f01000401f0000006000000321000002a000732000600000010", INIT_34 => X"14e80008100c25030000100000d82c00280100f00000003000fc000600240000", INIT_35 => X"003401000401280000060000005d1800003f00075d0006000000180001041825", INIT_36 => X"00002170800000fc200000100f00200000160008001a00040800000004000004", INIT_37 => X"0000101410250cf00008181425030000180000c32c01002800f0002000010020", INIT_38 => X"0a104c48444025383cc00008100c250000f20000000000140100141001001000", INIT_39 => X"184018ff0003180100050a48000500402f00f30f001010010010102021101000", INIT_3A => X"0010000a0a00101c12100d1b02001c4810100d1b02001c48003e140e1c121800", INIT_3B => X"0b2a0000004c2300140f000c001c102110140300ff57ff001000080300ff30ff", INIT_3C => X"4c000b0000004c102d21101414ff0014000aff1800000200c0001414ff001400", INIT_3D => X"20230f00004c000c00004c2300140f00f844252100142000122a2300140f0000", INIT_3E => X"10250cf000080804250000180360000c082504f8000840383c250000f8442521", INIT_3F => X"00080c082504f80008100c250000f1001010240010ff001000ff010000000d00" ) port map ( DO => block_do(0)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(0), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block0 block1: if (block_count > 1) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"00008f8faf000c8faf0000008f00008fafaf03afaf270003278f030000008f00", INIT_01 => X"8f0000003c8fac008fac008fac008f30008fafafafafaf03af270003278f8f03", INIT_02 => X"0010248f001428008faf24008faf00008f0030003000008f8c008f0010afac00", INIT_03 => X"10240014008f8f001024001000008f8c008f001024001000008f8c008f001024", INIT_04 => X"03af270003278f0300008faf03af270003278f0300001024001028008c008f00", INIT_05 => X"343c000c243c000c343c34af24afaf03afafaf27000003278f030000343c8faf", INIT_06 => X"240004008c340010ac24ac343c24ae000c242424000c243cac008f343caf008c", INIT_07 => X"008fae000c242424000c24000c0024008f000c243c0014248faf000c8faf008c", INIT_08 => X"00000000000003278f8f8f0300000c00142c008fac008f24af000c8f0010af24", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000102040912000000", INIT_0F => X"fffffffffffffffffffffffffffffffffffffffffffffefcf9f2e4c992000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000606060606050000000000", INIT_13 => X"0000000000000000000000000000000000000000000000010101010101000000", INIT_14 => X"3d3d3d3d3d3d676620740a0a747320650a000000000000000000000000000000", INIT_15 => X"694c7363726d69546e616f6269546f6175206467730a00696920746c6c67730a", INIT_16 => X"4e490a007420696c54004546455000454d500a6469540030617261736d657061", INIT_17 => X"544c4c0a0a53200a4c2000454e490a0044414f4c41454e490a0044414f4c4145", INIT_18 => X"0000000000000000000054204945540a54204d0a542043422f440a2054494920", INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000102040912000000000000000000000000000000", INIT_1F => X"fffffffffffffffffffffefcf9f2e4c992000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000606060606050000000000000000000000000000000000", INIT_23 => X"0000000000000000000000010101010101000000000000000000000000000000", INIT_24 => X"7566542055000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000072756570695300736e61756369670a0a727475526e2068616e", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(1)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(1), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"6200c2c3c20000c4c2430300c30200c2c5c4a0bebfbd00e0bdbec0620200c202", INIT_01 => X"c240026202c34000c24000c24300c24300c2c0c7c6c5c4a0bebd00e0bdbebfc0", INIT_02 => X"006202c300404200c2c24200c2c24300c2404202424300c24300c20000c04300", INIT_03 => X"0002006200c2c300000200404300c24300c200000200404300c24300c2000002", INIT_04 => X"a0bebd00e0bdbec00200c2c4a0bebd00e0bdbec000000002004042004200c200", INIT_05 => X"4202000044020000440205c202c5c4a0b0bebfbd0000e0bdbec002624202c3c4", INIT_06 => X"0200400042020000400243630302020000040510000044024300c34202c20042", INIT_07 => X"00c20200000405100000040000400500c200004402006202c3c20000c4c20042", INIT_08 => X"000000000000e0bdb0bebfc000000000404200c24300c302c20000c40000c242", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"00000000000000000000000000000000010204091224489123468d1a34000000", INIT_0F => X"fffffffffffffffffffffffffffffefcf9f2e4c99224489123468d1a34000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff", INIT_11 => X"0000000000000000000000000000000000000003030303030300000000000000", INIT_12 => X"02010000000000000000000000000000010101020515100b0500fb1a150f0a05", INIT_13 => X"0000000000000000000000000000000000000000000001504f4e4d4c4b050403", INIT_14 => X"0a3d3d3d3d3d0a747369540a656d707247000000000000000000000000000000", INIT_15 => X"6e69736379656e65737470696e656e63622f6920740a006f762f69697420740a", INIT_16 => X"554d0a0073746c206f00444144410053414c0a6f6e6500306e206c206220726c", INIT_17 => X"4949540a0a45500a4546005347460a0021534e414c52554d0a0021494e414c52", INIT_18 => X"0000000000000000000020544f52200a20544f0a2054545420450a00454f562f", INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"00000000010204091224489123468d1a34000000000000000000000000000000", INIT_1F => X"fffffefcf9f2e4c99224489123468d1a34000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff", INIT_21 => X"0000000000000003030303030300000000000000000000000000000000000000", INIT_22 => X"00000000010101020515100b0500fb1a150f0a05000000000000000000000000", INIT_23 => X"0000000000000000000001504f4e4d4c4b050403020100000000000000000000", INIT_24 => X"20203a5441000000000000000000000000000000000000000000000000000000", INIT_25 => X"00000000000000206d74616e65007420746e6f6e690a006b2074542074696420", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(1)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(1), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"100000000000070000101f00001000000000f00000ff00000000e8101400001f", INIT_01 => X"001814100f000000000000000000000000000000000000f000ff0000000000e8", INIT_02 => X"0000000000ff0000000000000000100000180010001000000000000000000000", INIT_03 => X"0000000000000000000000001000000000000000000000100000000000000000", INIT_04 => X"f000ff00000000e817000000f000ff00000000e8100000000000000000000000", INIT_05 => X"00200000320000007801e100000000f0000000ff0000000000e81010ff1f0000", INIT_06 => X"7f00000000800000007f00ff0f7f00000700007f000032000000000020000000", INIT_07 => X"000000000700007f000000000120003000000032000000000000000800000000", INIT_08 => X"0000000000000000000000e810000100ff0000000000007f0000080000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0101010101010101010101010101010000000000000000000000000000000000", INIT_0B => X"0202020201010101010101010101010101010101010101010101010101010101", INIT_0C => X"0202020202020202020202020202020202020202020202020202020202020202", INIT_0D => X"0303030303030303030303030303030303030303030303030303030303030202", INIT_0E => X"0000000000000000010204091224489123468d1a3468d1a2458a152b56030303", INIT_0F => X"fffffffffffffefcf9f2e4c99224489123468d1a3468d1a2458a152b56000000", INIT_10 => X"0000000000000000000000000000000000080808080707000000000000ffffff", INIT_11 => X"000000000000000000000000000000000101039e9b9794918e0f0c0906030000", INIT_12 => X"46230000000000000000000095a8c0e00d50c1a1439e5b17d4914e4f0cc98643", INIT_13 => X"1212121212000000000000000000202429303a48619123c7a4815d3a17b08d69", INIT_14 => X"003d3d3d3d3d0069686e650073616c6165121212121212121212121212121212", INIT_15 => X"67730a65206d67730a69657467730a7474206e616954006e69206f63696d6954", INIT_16 => X"4d4550003a65656674002149215300542041006e6773003020746c73656e696c", INIT_17 => X"4f43494d0044410044410054205453000a53205443204d4550000a4c20544320", INIT_18 => X"0000000000000000000000454e414f420045524d00454f5253524100534e4920", INIT_19 => X"00000000000000000000000000000000000000000000000000001212ed515302", INIT_1A => X"0101010000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0101010101010101010101010101010101010101010101010101010101010101", INIT_1C => X"0202020202020202020202020202020202020202020202020101010101010101", INIT_1D => X"0303030303030303030303030303030303030202020202020202020202020202", INIT_1E => X"1224489123468d1a3468d1a2458a152b56030303030303030303030303030303", INIT_1F => X"9224489123468d1a3468d1a2458a152b56000000000000000000000001020409", INIT_20 => X"0000000000080808080707000000000000fffffffffffffffffffefcf9f2e4c9", INIT_21 => X"000000000101039e9b9794918e0f0c0906030000000000000000000000000000", INIT_22 => X"95a8c0e00d50c1a1439e5b17d4914e4f0cc98643000000000000000000000000", INIT_23 => X"0000202429303a48619123c7a4815d3a17b08d69462300000000000000000000", INIT_24 => X"6379204552121212121212121212121212121212121212121200000000000000", INIT_25 => X"0000000000000000622063676e000a7469696d676e4200737770205568732072", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(1)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(1), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"250014101400dc101025400020400024242025181ce000080804252500000c00", INIT_01 => X"20250224ff1000001c000018000014ff0010041c181410250cf0000820181c25", INIT_02 => X"0004010400ea080000000100000421000425ff2b010700000000140013000000", INIT_03 => X"0c04000400181c00140300042a002400001c001f0200042a0024000018002a01", INIT_04 => X"2504f80008080425420008082504f80008100c25250002050004020000002000", INIT_05 => X"500000ae6c000080407d0010013c38252c3034c80000080804254224feff0808", INIT_06 => X"fc002e000000003300fc00fffffc0000f90103fc00aea8000000143000140000", INIT_07 => X"00100000f90103fc00980a0005250a251000aecc00001a011c1c009118180000", INIT_08 => X"0b070503000008382c30342525006000ca650010000020fc20009d1800091001", INIT_09 => X"9d97958b89837f716d6b67656159534f4947433d3b352f2b29251f1d1713110d", INIT_0A => X"5b514b3d393733251b19150f0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a3", INIT_0B => X"231d0b09fdf7f3ebe7dfd3cfcdc9c1bbb7b1afa5a399918d857f7b756f67615d", INIT_0C => X"efe7e3ddd7cfc5bdb3aba5a195938d878381776b69655f5957514b413b39332d", INIT_0D => X"d1cbc7b9b3ada9a1978f8b7773716d5f5b5955473d3b37352b291d130501f9f5", INIT_0E => X"010204091224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78e5dfd7", INIT_0F => X"f9f2e4c99224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78000000", INIT_10 => X"070001020301010000000101010102030718110a03fcf5231c150e0700fffefc", INIT_11 => X"0000010303010100010059647285a0c80b90212807e6c5a483a5846342210007", INIT_12 => X"8a4500030103030001000100ae6472856dc80b90212807e6c5a483a584634221", INIT_13 => X"38373635340005010300010001005d689c8b41d117a245c8833ef9b46f5914cf", INIT_14 => X"003d3d3d3d3d006e696773007420616c6e2b2c2d2e2f30313233343d3c3b3a39", INIT_15 => X"20740073616f2074006f722020740069727367646e65000a73646e6170756e65", INIT_16 => X"422052002073646161000a4c00530020545300652074000a3168656d72756d20", INIT_17 => X"4e4150550021530021490020544948000a4550495543422052000a4546495543", INIT_18 => X"0908070605040302010000535354504900535945005352415520440054205344", INIT_19 => X"6159534f4947433d3b352f2b29251f1d1713110d0b07050300002246cb153520", INIT_1A => X"0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a39d97958b89837f716d6b6765", INIT_1B => X"cdc9c1bbb7b1afa5a399918d857f7b756f67615d5b514b3d393733251b19150f", INIT_1C => X"95938d878381776b69655f5957514b413b39332d231d0b09fdf7f3ebe7dfd3cf", INIT_1D => X"73716d5f5b5955473d3b37352b291d130501f9f5efe7e3ddd7cfc5bdb3aba5a1", INIT_1E => X"3468d1a2458a152b56ac59b367cf9e3c78e5dfd7d1cbc7b9b3ada9a1978f8b77", INIT_1F => X"3468d1a2458a152b56ac59b367cf9e3c78000000010204091224489123468d1a", INIT_20 => X"010102030718110a03fcf5231c150e0700fffefcf9f2e4c99224489123468d1a", INIT_21 => X"7285a0c80b90212807e6c5a483a5846342210007070001020301010000000101", INIT_22 => X"ae6472856dc80b90212807e6c5a483a584634221000001030301010001005964", INIT_23 => X"01005d689c8b41d117a245c8833ef9b46f5914cf8a4500030103030001000100", INIT_24 => X"616f4953542b2c2d2e2f30313233343d3c3b3a39383736353400050103000100", INIT_25 => X"0000000100000000656e6b2064000a656f636d206e6500216f756f41652c7465", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(1)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(1), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block1 block2: if (block_count > 2) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(2)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(2), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(2)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(2), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(2)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(2), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(2)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(2), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block2 block3: if (block_count > 3) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(3)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(3), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(3)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(3), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(3)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(3), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(3)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(3), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block3 block4: if (block_count > 4) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(4)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(4), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(4)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(4), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(4)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(4), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(4)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(4), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block4 block5: if (block_count > 5) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(5)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(5), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(5)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(5), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(5)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(5), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(5)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(5), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block5 block6: if (block_count > 6) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(6)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(6), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(6)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(6), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(6)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(6), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(6)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(6), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block6 block7: if (block_count > 7) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(7)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(7), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(7)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(7), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(7)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(7), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(7)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(7), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block7 end; --architecture logic
gpl-3.0
261943f14169a2fc72c4a7a7340758c5
0.843311
5.637524
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/RTL/ParityChecker_packet_detector.vhd
4
2,664
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; entity parity_checker_packet_detector is generic(DATA_WIDTH : integer := 32); port( reset: in std_logic; clk: in std_logic; RX: in std_logic_vector(DATA_WIDTH-1 downto 0); valid_in: in std_logic; faulty_packet, healthy_packet: out std_logic ); end parity_checker_packet_detector; architecture behavior of parity_checker_packet_detector is signal xor_all: std_logic; signal fault_out, fault_out_in: std_logic; alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3); type state_type IS (Idle, Header_flit, Body_flit, Tail_flit); SIGNAL state_out, state_in : state_type; begin -- sequential process process(reset, clk)begin if reset = '0' then state_out <= Idle; fault_out <= '0'; elsif clk'event and clk = '1' then state_out <= state_in; fault_out <= fault_out_in; end if; end process; --anything bellow this is combinatorial -- this part is the typical parity process(valid_in, RX) begin if valid_in = '1' then xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1)); else xor_all <= '0'; end if; end process; process(valid_in, RX, xor_all)begin fault_out_in <= '0'; if valid_in = '1' and xor_all /= RX(0) then fault_out_in <= '1'; end if; end process; -- FSM for packet health detection process(flit_type, fault_out, state_out, valid_in) begin faulty_packet <= '0'; healthy_packet <= '0'; --if valid_in = '1' then case(state_out) is when Idle => if flit_type = "001" then state_in <= Header_flit; else state_in <= state_out; end if; when Header_flit => if fault_out = '0' then if flit_type = "010" then state_in <= Body_flit; else state_in <= state_out; end if; else state_in <= Idle; faulty_packet <= '1'; end if; when Body_flit => if fault_out = '0' then if flit_type = "100" then state_in <= Tail_flit; else state_in <= state_out; end if; else state_in <= Idle; faulty_packet <= '1'; end if; when Tail_flit => state_in <= Idle; if fault_out = '0' then healthy_packet <= '1'; else faulty_packet <= '1'; end if; when others => state_in <= state_out; end case; --else -- state_in <= state_out; --end if; end process; end;
gpl-3.0
974a797ff9a2910d9773e8fac9c2430c
0.563438
3.108518
false
false
false
false
AndyMcC0/UVVM_All
uvvm_util/src/protected_types_pkg.vhd
3
4,716
--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <[email protected]>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library ieee; use ieee.std_logic_1164.all; use std.textio.all; use work.types_pkg.all; use work.adaptations_pkg.all; use work.string_methods_pkg.all; package protected_types_pkg is type t_protected_alert_attention_counters is protected procedure increment( alert_level : t_alert_level; attention : t_attention := REGARD; -- count, expect, ignore number : natural := 1 ); impure function get( alert_level: t_alert_level; attention : t_attention := REGARD ) return natural; procedure to_string( order : t_order ); end protected t_protected_alert_attention_counters; type t_protected_semaphore is protected impure function get_semaphore return boolean; procedure release_semaphore; end protected t_protected_semaphore; type t_protected_acknowledge_cmd_idx is protected impure function set_index(index : integer) return boolean; impure function get_index return integer; procedure release_index; end protected t_protected_acknowledge_cmd_idx; end package protected_types_pkg; --============================================================================= --============================================================================= package body protected_types_pkg is -------------------------------------------------------------------------------- type t_protected_alert_attention_counters is protected body variable priv_alert_attention_counters : t_alert_attention_counters; procedure increment( alert_level: t_alert_level; attention : t_attention := REGARD; number : natural := 1 ) is begin priv_alert_attention_counters(alert_level)(attention) := priv_alert_attention_counters(alert_level)(attention) + number; end; impure function get( alert_level: t_alert_level; attention : t_attention := REGARD ) return natural is begin return priv_alert_attention_counters(alert_level)(attention); end; procedure to_string( order : t_order ) is begin to_string(priv_alert_attention_counters, order); end; end protected body t_protected_alert_attention_counters; type t_protected_semaphore is protected body variable v_priv_semaphore_taken : boolean := false; impure function get_semaphore return boolean is begin if v_priv_semaphore_taken = false then -- semaphore was free v_priv_semaphore_taken := true; return true; else -- semaphore was not free return false; end if; end; procedure release_semaphore is begin v_priv_semaphore_taken := false; end procedure; end protected body t_protected_semaphore; type t_protected_acknowledge_cmd_idx is protected body variable v_priv_idx : integer := -1; impure function set_index(index : integer) return boolean is begin -- for broadcast if v_priv_idx = -1 or v_priv_idx = index then -- index was now set v_priv_idx := index; return true; else -- index was set by another vvc return false; end if; end; impure function get_index return integer is begin return v_priv_idx; end; procedure release_index is begin v_priv_idx := -1; end procedure; end protected body t_protected_acknowledge_cmd_idx; end package body protected_types_pkg;
mit
3ab95f0f68afe8f2045f2038b033dc39
0.586726
4.687873
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/RTL/NI_Test/NI.vhd
3
27,338
--------------------------------------------------------------------- -- Copyright (C) 2016 Siavoosh Payandeh Azad -- -- Network interface: Its an interrupt based memory mapped I/O for sending and recieving packets. -- the data that is sent to NI should be of the following form: -- FIRST write: 4bit source(31-28), 4 bit destination(27-14), 8bit packet length(23-16) -- Body write: 28 bit data(27-0) -- Last write: 28 bit data(27-0) --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use IEEE.NUMERIC_STD.all; use ieee.std_logic_textio.all; use std.textio.all; use work.mlite_pack.all; use ieee.std_logic_misc.all; entity NI is generic(current_address : integer := 10; -- the current node's address SHMU_address : integer := 0; reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111"; -- Behrad: NI's reserved address ? flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the memory mapped I/O counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001"; reconfiguration_address : std_logic_vector(29 downto 0) := "000000000000000010000000000010"; -- reserved address for reconfiguration register self_diagnosis_address : std_logic_vector(29 downto 0) := "000000000000000010000000000011"); -- reserved address for self diagnosis register port(clk : in std_logic; reset : in std_logic; enable : in std_logic; write_byte_enable : in std_logic_vector(3 downto 0); address : in std_logic_vector(31 downto 2); data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); -- Flags used by JNIFR and JNIFW instructions --NI_read_flag : out std_logic; -- One if the N2P fifo is empty. No read should be performed if one. --NI_write_flag : out std_logic; -- One if P2N fifo is full. no write should be performed if one. -- interrupt signal: generated evertime a packet is recieved! irq_out : out std_logic; -- signals for sending packets to network credit_in : in std_logic; valid_out: out std_logic; TX: out std_logic_vector(31 downto 0); -- data sent to the NoC -- signals for reciving packets from the network credit_out : out std_logic; valid_in: in std_logic; RX: in std_logic_vector(31 downto 0); -- data recieved form the NoC -- fault information signals from the router link_faults: in std_logic_vector(4 downto 0); turn_faults: in std_logic_vector(19 downto 0); Rxy_reconf_PE: out std_logic_vector(7 downto 0); Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits) Reconfig_command : out std_logic ); end; --entity NI architecture logic of NI is -- packet format: -- the parity bit is calculated by the NI and the processor has no control over it -- flit type is generated by the NI and process has no control over it -- header flit -- 32 3bits 14 bits 14 bits 1bit 0 -- .----------------------------------------------------------------------. -- | flit type| SOURCE ADDRESS | DESTINATION ADDRESS |parity bit | -- '----------------------------------------------------------------------' -- SOURCE ADDRESS is added automatically by the NI (the processor has no control over it) -- DESTINATION ADDRESS is writen in the first write by the PE in FIFO_Data_out(13 downto 0) -- body flit 1 -- 32 3bits 14 bits 14 bits 1bit 0 -- .----------------------------------------------------------------------. -- | flit type| PACKET LENGTH | PACKET ID |parity bit | -- '----------------------------------------------------------------------' -- PACEKT ID is determined and added by the NI (the processor has no control over it) -- PACKET LENGTH is written in the 2nd write by PE in FIFO_Data_out(27 downto 14) -- other body flits -- 32 3bits 28 bits 1bit 0 -- .----------------------------------------------------------------------. -- | flit type| PAYLOAD DATA |parity bit | -- '----------------------------------------------------------------------' -- PAYLOAD DATA is written by the PE in FIFO_Data_out(27 downto 0) -- Tail flits -- 32 3bits 28 bits 1bit 0 -- .----------------------------------------------------------------------. -- | flit type| PAYLOAD DATA |parity bit | -- '----------------------------------------------------------------------' -- PAYLOAD DATA is written by the PE in FIFO_Data_out(27 downto 0) -- all the following signals are for sending data from processor to NoC signal storage, storage_in : std_logic_vector(31 downto 0); signal valid_data_in, valid_data: std_logic; signal old_address: std_logic_vector(31 downto 2); -- Behrad: What is old address ? signal P2N_FIFO_read_pointer, P2N_FIFO_read_pointer_in, P2N_FIFO_write_pointer, P2N_FIFO_write_pointer_in: std_logic_vector(3 downto 0); signal P2N_write_en: std_logic; signal P2N_FIFO_MEM_1, P2N_FIFO_MEM_1_in : std_logic_vector(31 downto 0); signal P2N_FIFO_MEM_2, P2N_FIFO_MEM_2_in : std_logic_vector(31 downto 0); signal P2N_FIFO_MEM_3, P2N_FIFO_MEM_3_in : std_logic_vector(31 downto 0); signal P2N_FIFO_MEM_4, P2N_FIFO_MEM_4_in : std_logic_vector(31 downto 0); signal P2N_full, P2N_empty: std_logic; signal credit_counter_in, credit_counter_out: std_logic_vector(1 downto 0); signal packet_counter_in, packet_counter_out: std_logic_vector(13 downto 0); signal packet_length_counter_in, packet_length_counter_out: std_logic_vector(13 downto 0); signal grant : std_logic; type STATE_TYPE IS (IDLE, HEADER_FLIT, BODY_FLIT_1, BODY_FLIT, TAIL_FLIT, DIAGNOSIS_HEADER, DIAGNOSIS_BODY, DIAGNOSIS_BODY_1, DIAGNOSIS_TAIL); signal state, state_in : STATE_TYPE := IDLE; signal FIFO_Data_out : std_logic_vector(31 downto 0); signal flag_register, flag_register_in : std_logic_vector(31 downto 0); -- all the following signals are for sending the packets from NoC to processor signal N2P_FIFO_MEM_1, N2P_FIFO_MEM_1_in : std_logic_vector(31 downto 0); signal N2P_FIFO_MEM_2, N2P_FIFO_MEM_2_in : std_logic_vector(31 downto 0); signal N2P_FIFO_MEM_3, N2P_FIFO_MEM_3_in : std_logic_vector(31 downto 0); signal N2P_FIFO_MEM_4, N2P_FIFO_MEM_4_in : std_logic_vector(31 downto 0); signal N2P_Data_out, data_read_in : std_logic_vector(31 downto 0); signal N2P_FIFO_read_pointer, N2P_FIFO_read_pointer_in: std_logic_vector(3 downto 0); signal N2P_FIFO_write_pointer, N2P_FIFO_write_pointer_in: std_logic_vector(3 downto 0); signal N2P_full, N2P_empty: std_logic; signal N2P_read_en, N2P_read_en_in, N2P_write_en: std_logic; signal counter_register_in, counter_register : std_logic_vector(1 downto 0); signal fault_info, fault_info_in: std_logic_vector(24 downto 0); signal sent_info, fault_info_ready, fault_info_ready_in: std_logic; signal self_diagnosis_reg_out, self_diagnosis_reg_in: std_logic_vector(31 downto 0); signal self_diagnosis_flag, self_diagnosis_flag_in: std_logic; begin process(clk, enable, write_byte_enable) begin if reset = '1' then storage <= (others => '0'); valid_data <= '0'; P2N_FIFO_read_pointer <= "0001"; P2N_FIFO_write_pointer <= "0001"; P2N_FIFO_MEM_1 <= (others=>'0'); P2N_FIFO_MEM_2 <= (others=>'0'); P2N_FIFO_MEM_3 <= (others=>'0'); P2N_FIFO_MEM_4 <= (others=>'0'); credit_counter_out <= "11"; packet_length_counter_out <= (others=>'0'); state <= IDLE; packet_counter_out <= (others=>'0'); ------------------------------------------------ N2P_FIFO_MEM_1 <= (others=>'0'); N2P_FIFO_MEM_2 <= (others=>'0'); N2P_FIFO_MEM_3 <= (others=>'0'); N2P_FIFO_MEM_4 <= (others=>'0'); N2P_FIFO_read_pointer <= "0001"; N2P_FIFO_write_pointer <= "0001"; credit_out <= '0'; counter_register <= (others => '0'); N2P_read_en <= '0'; flag_register <= (others =>'0'); old_address <= (others =>'0'); fault_info <= (others => '0'); fault_info_ready <= '0'; self_diagnosis_reg_out <= (others => '0'); self_diagnosis_flag <= '0'; elsif clk'event and clk = '1' then old_address <= address; P2N_FIFO_write_pointer <= P2N_FIFO_write_pointer_in; P2N_FIFO_read_pointer <= P2N_FIFO_read_pointer_in; credit_counter_out <= credit_counter_in; packet_length_counter_out <= packet_length_counter_in; valid_data <= valid_data_in; if P2N_write_en = '1' then --write into the memory P2N_FIFO_MEM_1 <= P2N_FIFO_MEM_1_in; P2N_FIFO_MEM_2 <= P2N_FIFO_MEM_2_in; P2N_FIFO_MEM_3 <= P2N_FIFO_MEM_3_in; P2N_FIFO_MEM_4 <= P2N_FIFO_MEM_4_in; end if; packet_counter_out <= packet_counter_in; if write_byte_enable /= "0000" then storage <= storage_in; end if; state <= state_in; ------------------------------------------------ if N2P_write_en = '1' then --write into the memory N2P_FIFO_MEM_1 <= N2P_FIFO_MEM_1_in; N2P_FIFO_MEM_2 <= N2P_FIFO_MEM_2_in; N2P_FIFO_MEM_3 <= N2P_FIFO_MEM_3_in; N2P_FIFO_MEM_4 <= N2P_FIFO_MEM_4_in; end if; counter_register <= counter_register_in; N2P_FIFO_write_pointer <= N2P_FIFO_write_pointer_in; N2P_FIFO_read_pointer <= N2P_FIFO_read_pointer_in; credit_out <= '0'; N2P_read_en <= N2P_read_en_in; if N2P_read_en = '1' then credit_out <= '1'; end if; flag_register <= flag_register_in; fault_info <= fault_info_in; fault_info_ready <= fault_info_ready_in; self_diagnosis_reg_out <= self_diagnosis_reg_in; self_diagnosis_flag <= self_diagnosis_flag_in; end if; end process; -- everything bellow this line is pure combinatorial! --------------------------------------------------------------------------------------- --below this is code for communication from PE 2 NoC -- Process used for sending reconfiguration command from PE to router (which is part of NoC) process(enable, address, write_byte_enable) begin -- Some initializations Reconfig_command <= '0'; Rxy_reconf_PE <= (others =>'0'); Cx_reconf_PE <= (others =>'0'); if address = reconfiguration_address and enable = '1' then if write_byte_enable /= "0000" then -- In this case, data_write definitely includes the connectivity bits and routing bits for -- reconfiguring LBDR logic. Rxy_reconf_PE <= data_write(7 downto 0); -- Rxy is 8 bits long Cx_reconf_PE <= data_write(11 downto 8); -- Cx is 4 bits long Reconfig_command <= '1'; end if; end if; end process; process(write_byte_enable, enable, address, storage, data_write, valid_data, P2N_write_en) begin storage_in <= storage ; valid_data_in <= valid_data; -- If PE wants to send data to NoC via NI (data is valid) if enable = '1' and address = reserved_address then if write_byte_enable /= "0000" then valid_data_in <= '1'; end if; -- Behrad: So according to Plasma, is write_byte_enable always one-hot ? -- (of course it can also be "0000") if write_byte_enable(0) = '1' then storage_in(7 downto 0) <= data_write(7 downto 0); end if; if write_byte_enable(1) = '1' then storage_in(15 downto 8) <= data_write(15 downto 8); end if; if write_byte_enable(2) = '1' then storage_in(23 downto 16) <= data_write(23 downto 16); end if; if write_byte_enable(3) = '1' then storage_in(31 downto 24) <= data_write(31 downto 24); end if; end if; if P2N_write_en = '1' then valid_data_in <= '0'; end if; end process; -- Process for storing in FIFO (based on the position write pointer is pointing to) -- Write pointer is encoded as one-hot! process(storage, P2N_FIFO_write_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin case(P2N_FIFO_write_pointer) is when "0001" => P2N_FIFO_MEM_1_in <= storage; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4; when "0010" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= storage; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4; when "0100" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= storage; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4; when "1000" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= storage; when others => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4; end case ; end process; -- Process for reading from FIFO (based on the position read pointer is pointing to) -- read pointer is encoded as one-hot! process(P2N_FIFO_read_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin case( P2N_FIFO_read_pointer ) is when "0001" => FIFO_Data_out <= P2N_FIFO_MEM_1; when "0010" => FIFO_Data_out <= P2N_FIFO_MEM_2; when "0100" => FIFO_Data_out <= P2N_FIFO_MEM_3; when "1000" => FIFO_Data_out <= P2N_FIFO_MEM_4; when others => FIFO_Data_out <= P2N_FIFO_MEM_1; end case ; end process; -- Write pointer update process (after each write operation, write pointer is rotated one bit to the left) process(P2N_write_en, P2N_FIFO_write_pointer)begin if P2N_write_en = '1' then P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer(2 downto 0) & P2N_FIFO_write_pointer(3); else P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer; end if; end process; -- Read pointer update process (after each read operation, read pointer is rotated one bit to the left) process(P2N_FIFO_read_pointer, grant, fault_info_ready)begin P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer; if grant = '1' and fault_info_ready = '0' then -- Behrad: so grant here works somehow like read_en signal for FIFO ? P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer(2 downto 0) & P2N_FIFO_read_pointer(3); end if; end process; process(P2N_full, valid_data) begin if valid_data = '1' and P2N_full ='0' then P2N_write_en <= '1'; else P2N_write_en <= '0'; end if; end process; -- Process for updating full and empty signals process(P2N_FIFO_write_pointer, P2N_FIFO_read_pointer) begin P2N_empty <= '0'; P2N_full <= '0'; if P2N_FIFO_read_pointer = P2N_FIFO_write_pointer then P2N_empty <= '1'; end if; if P2N_FIFO_write_pointer = P2N_FIFO_read_pointer(0) & P2N_FIFO_read_pointer(3 downto 1) then P2N_full <= '1'; end if; end process; process (credit_in, credit_counter_out, grant)begin credit_counter_in <= credit_counter_out; if credit_in = '1' and grant = '1' then credit_counter_in <= credit_counter_out; elsif credit_in = '1' and credit_counter_out < 3 then credit_counter_in <= credit_counter_out + 1; elsif grant = '1' and credit_counter_out > 0 then credit_counter_in <= credit_counter_out - 1; end if; end process; -- flag setting and clearing for self diagnosis process(link_faults, turn_faults, self_diagnosis_flag, old_address)begin if (link_faults /= "00000" or turn_faults /= "00000000000000000000") and SHMU_address = current_address then self_diagnosis_flag_in <= '1'; elsif old_address = self_diagnosis_address then self_diagnosis_flag_in <= '0'; else self_diagnosis_flag_in <= self_diagnosis_flag; end if; end process; -- handling fault information! process(link_faults, turn_faults, sent_info, fault_info_ready, fault_info)begin self_diagnosis_reg_in <= self_diagnosis_reg_out; -- If current node is not SHMU, we need to send fault information to SHMU if (link_faults /= "00000" or turn_faults /= "00000000") and SHMU_address /= current_address then fault_info_in <= turn_faults & link_faults; fault_info_ready_in <= '1'; -- If current node is SHMU, we handle it locally elsif (link_faults /= "00000" or turn_faults /= "00000000") and SHMU_address = current_address then self_diagnosis_reg_in <= "0000000" & turn_faults & link_faults; else fault_info_in <= fault_info; fault_info_ready_in <= fault_info_ready; end if; if sent_info = '1' then fault_info_ready_in <= '0'; end if; end process; process(P2N_empty, state, credit_counter_out, packet_length_counter_out, packet_counter_out, FIFO_Data_out, fault_info_ready) begin -- Some initializations sent_info <= '0'; TX <= (others => '0'); grant<= '0'; packet_length_counter_in <= packet_length_counter_out; packet_counter_in <= packet_counter_out; case(state) is when IDLE => if fault_info_ready = '1' then state_in <= DIAGNOSIS_HEADER; elsif P2N_empty = '0' then state_in <= HEADER_FLIT; else state_in <= IDLE; end if; when HEADER_FLIT => if credit_counter_out /= "00" and P2N_empty = '0' then grant <= '1'; --TX <= "001" & "0000" & FIFO_Data_out(23 downto 16) & FIFO_Data_out(31 downto 28) & -- std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out & XOR_REDUCE("001" & "0000" & -- FIFO_Data_out(23 downto 16) & FIFO_Data_out(31 downto 28) & -- std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out); TX <= "001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0) & XOR_REDUCE("001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0)); state_in <= BODY_FLIT_1; else state_in <= HEADER_FLIT; end if; when BODY_FLIT_1 => if credit_counter_out /= "00" and P2N_empty = '0'then packet_length_counter_in <= (FIFO_Data_out(27 downto 14))-2; grant <= '1'; TX <= "010" &FIFO_Data_out(27 downto 14) & packet_counter_out & XOR_REDUCE( "010" &FIFO_Data_out(27 downto 14) & packet_counter_out); state_in <= BODY_FLIT; else state_in <= BODY_FLIT_1; end if; when BODY_FLIT => if credit_counter_out /= "00" and P2N_empty = '0'then grant <= '1'; TX <= "010" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("010" & FIFO_Data_out(27 downto 0)); packet_length_counter_in <= packet_length_counter_out - 1; if packet_length_counter_out > 2 then state_in <= BODY_FLIT; else state_in <= TAIL_FLIT; end if; else state_in <= BODY_FLIT; end if; when TAIL_FLIT => if credit_counter_out /= "00" and P2N_empty = '0' then grant <= '1'; packet_length_counter_in <= packet_length_counter_out - 1; TX <= "100" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("100" & FIFO_Data_out(27 downto 0)); packet_counter_in <= packet_counter_out +1; state_in <= IDLE; else state_in <= TAIL_FLIT; end if; -- SHMU stuff ---------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ when DIAGNOSIS_HEADER => if credit_counter_out /= "00" then grant <= '1'; TX <= "001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0) & XOR_REDUCE("001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0)); --TX <= "001" & "000000000011" & "0000" & std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out & XOR_REDUCE("001" & "000000000011" & "0000" & std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out); state_in <= DIAGNOSIS_BODY_1; else state_in <= DIAGNOSIS_HEADER; end if; when DIAGNOSIS_BODY_1 => if credit_counter_out /= "00" then grant <= '1'; state_in <= DIAGNOSIS_BODY; TX <= "010" & std_logic_vector(to_unsigned(4, 14)) & packet_counter_out & XOR_REDUCE( "010" & std_logic_vector(to_unsigned(4, 14)) & packet_counter_out ); else state_in <= DIAGNOSIS_BODY_1; end if; when DIAGNOSIS_BODY => if credit_counter_out /= "00" then grant <= '1'; --FD (Fault Diagnosis) : 01000110 01000100 -- fault info is 13 bits TX <= "010" & "0100011001000100" & fault_info(11 downto 0) & XOR_REDUCE("010" & "0100011001000100" & fault_info(11 downto 0)); state_in <= DIAGNOSIS_TAIL; else state_in <= DIAGNOSIS_BODY; end if; when DIAGNOSIS_TAIL => if credit_counter_out /= "00" then grant <= '1'; TX <= "100" & fault_info(24 downto 12) & "000000000000000" & XOR_REDUCE("100" & fault_info(24 downto 12) & "000000000000000"); state_in <= IDLE; sent_info <= '1'; packet_counter_in <= packet_counter_out +1; else state_in <= DIAGNOSIS_TAIL; end if; when others => state_in <= IDLE; end case ; end procesS; valid_out <= grant; ---------------------------------------------------------------------------------------- --below this is code for communication from NoC 2 PE process(RX, N2P_FIFO_write_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin case( N2P_FIFO_write_pointer ) is when "0001" => N2P_FIFO_MEM_1_in <= RX; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4; when "0010" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= RX; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4; when "0100" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= RX; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4; when "1000" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= RX; when others => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4; end case ; end process; process(N2P_FIFO_read_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin case( N2P_FIFO_read_pointer ) is when "0001" => N2P_Data_out <= N2P_FIFO_MEM_1; when "0010" => N2P_Data_out <= N2P_FIFO_MEM_2; when "0100" => N2P_Data_out <= N2P_FIFO_MEM_3; when "1000" => N2P_Data_out <= N2P_FIFO_MEM_4; when others => N2P_Data_out <= N2P_FIFO_MEM_1; end case ; end process; process(address, write_byte_enable, N2P_empty)begin if address = reserved_address and write_byte_enable = "0000" and N2P_empty = '0' then N2P_read_en_in <= '1'; else N2P_read_en_in <= '0'; end if; end process; process(N2P_write_en, N2P_FIFO_write_pointer)begin if N2P_write_en = '1'then N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer(2 downto 0)&N2P_FIFO_write_pointer(3); else N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer; end if; end process; process(N2P_read_en, N2P_empty, N2P_FIFO_read_pointer)begin if (N2P_read_en = '1' and N2P_empty = '0') then N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer(2 downto 0)&N2P_FIFO_read_pointer(3); else N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer; end if; end process; process(N2P_full, valid_in) begin if (valid_in = '1' and N2P_full ='0') then N2P_write_en <= '1'; else N2P_write_en <= '0'; end if; end process; process(N2P_FIFO_write_pointer, N2P_FIFO_read_pointer) begin if N2P_FIFO_read_pointer = N2P_FIFO_write_pointer then N2P_empty <= '1'; else N2P_empty <= '0'; end if; if N2P_FIFO_write_pointer = N2P_FIFO_read_pointer(0)&N2P_FIFO_read_pointer(3 downto 1) then N2P_full <= '1'; else N2P_full <= '0'; end if; end process; process(N2P_read_en, N2P_Data_out, old_address, flag_register) begin if old_address = reserved_address and N2P_read_en = '1' then data_read <= N2P_Data_out; elsif old_address = flag_address then data_read <= flag_register; elsif old_address = counter_address then data_read <= "000000000000000000000000000000" & counter_register; elsif old_address = self_diagnosis_address then data_read <= self_diagnosis_reg_out; else data_read <= (others => 'U'); end if; end process; process(N2P_write_en, N2P_read_en, RX, N2P_Data_out)begin counter_register_in <= counter_register; if N2P_write_en = '1' and RX(31 downto 29) = "001" and N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then counter_register_in <= counter_register; elsif N2P_write_en = '1' and RX(31 downto 29) = "001" then counter_register_in <= counter_register +1; elsif N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then counter_register_in <= counter_register -1; end if; end process; flag_register_in <= N2P_empty & P2N_full & self_diagnosis_flag & "00000000000000000000000000000"; --NI_read_flag <= N2P_empty; --NI_write_flag <= P2N_full; irq_out <= '0'; end; --architecture logic
gpl-3.0
162d915395a299dd8a2313859609a21e
0.56972
3.261124
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/LBDR_packet_drop_with_checkers_with_FI/LBDR_packet_drop_with_checkers_with_FI.vhd
3
24,292
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; use work.component_pack.all; entity LBDR_packet_drop is generic ( cur_addr_rst: integer := 8; Rxy_rst: integer := 8; Cx_rst: integer := 8; NoC_size: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic; empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); dst_addr: in std_logic_vector(NoC_size-1 downto 0); faulty: in std_logic; packet_drop_order: out std_logic; grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic; Rxy_reconf_PE: in std_logic_vector(7 downto 0); Cx_reconf_PE: in std_logic_vector(3 downto 0); Reconfig_command : in std_logic; -- fault injector shift register with serial input signals TCK: in std_logic; SE: in std_logic; -- shift enable UE: in std_logic; -- update enable SI: in std_logic; -- serial Input SO: out std_logic; -- serial output -- Checker outputs -- Routing part checkers err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in,err_grants_onehot,err_grants_mismatch, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1,err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1,err_dst_addr_cur_addr_not_E1,err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1,err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order, -- Cx_Reconf checkers err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added -- Rxy_Reconf checkers err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic ); end LBDR_packet_drop; architecture behavior of LBDR_packet_drop is ---------------------------------------- -- Signals related to fault injection -- ---------------------------------------- -- Total: 9 bits signal FI_add_sta: std_logic_vector(8 downto 0); -- 7 bits for fault injection location address (ceil of log2(70) = 7) -- 2 bits for type of fault (SA0 or SA1) signal non_faulty_signals: std_logic_vector (69 downto 0); -- 70 bits for internal- and output-related signals (non-faulty) signal faulty_signals: std_logic_vector(69 downto 0); -- 70 bits for internal- and output-related signals (with single stuck-at fault injected in one of them) ---------------------------------------- ---------------------------------------- signal Cx, Cx_in: std_logic_vector(3 downto 0); signal Temp_Cx, Temp_Cx_in: std_logic_vector(3 downto 0); signal reconfig_cx, reconfig_cx_in: std_logic; signal ReConf_FF_in, ReConf_FF_out: std_logic; signal Rxy, Rxy_in: std_logic_vector(7 downto 0); signal Rxy_tmp, Rxy_tmp_in: std_logic_vector(7 downto 0); signal cur_addr: std_logic_vector(NoC_size-1 downto 0); signal N1, E1, W1, S1 :std_logic :='0'; signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic; signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic; signal grants: std_logic; signal packet_drop, packet_drop_in: std_logic; -- Signal(s) required for checker(s) signal packet_drop_order_sig: std_logic; -- Signal(s) used for creating the chain of injected fault locations -- Total: 70 bits ??!! -- LBDR internal-related signals signal Cx_faulty, Cx_in_faulty: std_logic_vector(3 downto 0); signal Temp_Cx_faulty, Temp_Cx_in_faulty: std_logic_vector(3 downto 0); signal reconfig_cx_faulty, reconfig_cx_in_faulty: std_logic; signal ReConf_FF_in_faulty, ReConf_FF_out_faulty: std_logic; signal Rxy_faulty, Rxy_in_faulty: std_logic_vector(7 downto 0); signal Rxy_tmp_faulty, Rxy_tmp_in_faulty: std_logic_vector(7 downto 0); --signal cur_addr_faulty: std_logic_vector(NoC_size-1 downto 0); -- current address not included yet, in this way ??!! signal N1_faulty, E1_faulty, W1_faulty, S1_faulty :std_logic; signal Req_N_in_faulty, Req_E_in_faulty, Req_W_in_faulty, Req_S_in_faulty, Req_L_in_faulty: std_logic; signal Req_N_FF_faulty, Req_E_FF_faulty, Req_W_FF_faulty, Req_S_FF_faulty, Req_L_FF_faulty: std_logic; signal grants_faulty: std_logic; signal packet_drop_faulty, packet_drop_in_faulty: std_logic; -- LBDR output-related signals signal packet_drop_order_sig_faulty: std_logic; begin ------------------------------------- ---- Related to fault injection ----- ------------------------------------- -- Total: 70 bits -- Still not sure whether to include cur_addr or not ??!! -- for packet_drop_order output, not sure whether to include that one or the signal with _sig suffix in its name ??!! non_faulty_signals <= Cx & Cx_in & Temp_Cx & Temp_Cx_in & reconfig_cx & reconfig_cx_in & ReConf_FF_in & ReConf_FF_out & Rxy & Rxy_in & Rxy_tmp & Rxy_tmp_in & N1 & E1 & W1 & S1 & Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in & Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF & grants & packet_drop & packet_drop_in & packet_drop_order_sig; -- Fault injector module instantiation FI: fault_injector generic map(DATA_WIDTH => 70, ADDRESS_WIDTH => 7) port map (data_in=> non_faulty_signals , address => FI_add_sta(8 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals ); -- Extracting faulty values for internal- and output-related signals -- Total: 70 bits Cx_faulty <= faulty_signals (69 downto 66); Cx_in_faulty <= faulty_signals (65 downto 62); Temp_Cx_faulty <= faulty_signals (61 downto 58); Temp_Cx_in_faulty <= faulty_signals (57 downto 54); reconfig_cx_faulty <= faulty_signals (53); reconfig_cx_in_faulty <= faulty_signals (52); ReConf_FF_in_faulty <= faulty_signals (51); ReConf_FF_out_faulty <= faulty_signals (50); Rxy_faulty <= faulty_signals (49 downto 42); Rxy_in_faulty <= faulty_signals (41 downto 34); Rxy_tmp_faulty <= faulty_signals (33 downto 26); Rxy_tmp_in_faulty <= faulty_signals (25 downto 18); N1_faulty <= faulty_signals (17); E1_faulty <= faulty_signals (16); W1_faulty <= faulty_signals (15); S1_faulty <= faulty_signals (14); Req_N_in_faulty <= faulty_signals (13); Req_E_in_faulty <= faulty_signals (12); Req_W_in_faulty <= faulty_signals (11); Req_S_in_faulty <= faulty_signals (10); Req_L_in_faulty <= faulty_signals (9); Req_N_FF_faulty <= faulty_signals (8); Req_E_FF_faulty <= faulty_signals (7); Req_W_FF_faulty <= faulty_signals (6); Req_S_FF_faulty <= faulty_signals (5); Req_L_FF_faulty <= faulty_signals (4); grants_faulty <= faulty_signals (3); packet_drop_faulty <= faulty_signals (2); packet_drop_in_faulty <= faulty_signals (1); packet_drop_order_sig_faulty <= faulty_signals (0); -- Total: 9 bits SR: shift_register_serial_in generic map(REG_WIDTH => 9) port map ( TCK=> TCK, reset=>reset, SE=> SE, UE=> UE, SI=> SI, SO=> SO, data_out_parallel=> FI_add_sta ); ------------------------------------- ------------------------------------- -- Becuase of checkers we did this packet_drop_order <= packet_drop_order_sig; -- LBDR packet drop routing part checkers instantiation LBDR_packet_drop_routing_part_checkers: LBDR_packet_drop_routing_part_pseudo_checkers generic map (cur_addr_rst => cur_addr_rst, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) port map ( empty => empty, flit_type => flit_type, Req_N_FF => Req_N_FF_faulty, Req_E_FF => Req_E_FF_faulty, Req_W_FF => Req_W_FF_faulty, Req_S_FF => Req_S_FF_faulty, Req_L_FF => Req_L_FF_faulty, grant_N => grant_N, grant_E => grant_E, grant_W => grant_W, grant_S => grant_S, grant_L => grant_L, dst_addr => dst_addr, faulty => faulty, Cx => Cx_faulty, Rxy => Rxy_faulty, packet_drop => packet_drop_faulty, N1_out => N1_faulty, E1_out => E1_faulty, W1_out => W1_faulty, S1_out => S1_faulty, Req_N_in => Req_N_in_faulty, Req_E_in => Req_E_in_faulty, Req_W_in => Req_W_in_faulty, Req_S_in => Req_S_in_faulty, Req_L_in => Req_L_in_faulty, grants => grants_faulty, packet_drop_order => packet_drop_order_sig_faulty, packet_drop_in => packet_drop_in_faulty, -- Checker outputs err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => err_grants_onehot, err_grants_mismatch => err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => err_packet_drop_order); -- LBDR packet drop Cx Reconfiguration module checkers instantiation Cx_Reconf_checkers: Cx_Reconf_pseudo_checkers port map ( reconfig_cx => reconfig_cx_faulty, flit_type => flit_type, empty => empty, grants => grants_faulty, Cx_in => Cx_in_faulty, Temp_Cx => Temp_Cx_faulty, reconfig_cx_in => reconfig_cx_in_faulty, Cx => Cx_faulty, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command => Reconfig_command, Faulty_C_N => Faulty_C_N, Faulty_C_E => Faulty_C_E, Faulty_C_W => Faulty_C_W, Faulty_C_S => Faulty_C_S, Temp_Cx_in => Temp_Cx_in_faulty, -- Checker Outputs err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal ); -- LBDR packet drop Rxy Reconfiguration checkers instantiation Rxy_Reconf_checkers : Rxy_Reconf_pseudo_checkers port map ( ReConf_FF_out => ReConf_FF_out_faulty, Rxy => Rxy_faulty, Rxy_tmp => Rxy_tmp_faulty,Reconfig_command => Reconfig_command, flit_type => flit_type, grants => grants_faulty, empty => empty, Rxy_reconf_PE => Rxy_reconf_PE, Rxy_in => Rxy_in_faulty, Rxy_tmp_in => Rxy_tmp_in_faulty, ReConf_FF_in => ReConf_FF_in_faulty, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); grants <= grant_N or grant_E or grant_W or grant_S or grant_L; cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length)); N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0'; E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0'; W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0'; S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0'; process(clk, reset) begin if reset = '0' then Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length)); Rxy_tmp <= (others => '0'); Req_N_FF <= '0'; Req_E_FF <= '0'; Req_W_FF <= '0'; Req_S_FF <= '0'; Req_L_FF <= '0'; Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length)); Temp_Cx <= (others => '0'); ReConf_FF_out <= '0'; reconfig_cx <= '0'; packet_drop <= '0'; elsif clk'event and clk = '1' then Rxy <= Rxy_in; Rxy_tmp <= Rxy_tmp_in; Req_N_FF <= Req_N_in; Req_E_FF <= Req_E_in; Req_W_FF <= Req_W_in; Req_S_FF <= Req_S_in; Req_L_FF <= Req_L_in; ReConf_FF_out <= ReConf_FF_in; Cx <= Cx_in; reconfig_cx <= reconfig_cx_in; Temp_Cx <= Temp_Cx_in; packet_drop <= packet_drop_in; end if; end process; -- The combionational part process(Reconfig_command, Rxy_reconf_PE, Rxy_tmp, ReConf_FF_out, Rxy, flit_type, grants, empty)begin if ReConf_FF_out= '1' and flit_type = "100" and empty = '0' and grants = '1' then Rxy_tmp_in <= Rxy_tmp; Rxy_in <= Rxy_tmp; ReConf_FF_in <= '0'; else Rxy_in <= Rxy; if Reconfig_command = '1'then Rxy_tmp_in <= Rxy_reconf_PE; ReConf_FF_in <= '1'; else Rxy_tmp_in <= Rxy_tmp; ReConf_FF_in <= ReConf_FF_out; end if; end if; end process; process(Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Cx, Temp_Cx, flit_type, reconfig_cx, empty, grants, Cx_reconf_PE, Reconfig_command) begin Temp_Cx_in <= Temp_Cx; if reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' then Cx_in <= Temp_Cx; reconfig_cx_in <= '0'; else Cx_in <= Cx; if (Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1' then reconfig_cx_in <= '1'; Temp_Cx_in <= not(Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N) and Cx; elsif Reconfig_command = '1' then reconfig_cx_in <= '1'; Temp_Cx_in <= Cx_reconf_PE; else reconfig_cx_in <= reconfig_cx; end if; end if; end process; Req_N <= Req_N_FF; Req_E <= Req_E_FF; Req_W <= Req_W_FF; Req_S <= Req_S_FF; Req_L <= Req_L_FF; process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants, packet_drop, faulty, dst_addr, cur_addr) begin packet_drop_in <= packet_drop; if flit_type = "001" and empty = '0' then Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0); Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1); Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2); Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3); if dst_addr = cur_addr then Req_L_in <= '1'; else Req_L_in <= '0'; end if; if faulty = '1' or (((((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0)) = '0') and ((((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1)) = '0') and ((((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2)) = '0') and ((((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3)) = '0') and (dst_addr /= cur_addr)) then packet_drop_in <= '1'; Req_N_in <= '0'; Req_E_in <= '0'; Req_W_in <= '0'; Req_S_in <= '0'; Req_L_in <= '0'; end if; elsif flit_type = "100" and empty = '0' and grants = '1' then Req_N_in <= '0'; Req_E_in <= '0'; Req_W_in <= '0'; Req_S_in <= '0'; Req_L_in <= '0'; else Req_N_in <= Req_N_FF; Req_E_in <= Req_E_FF; Req_W_in <= Req_W_FF; Req_S_in <= Req_S_FF; Req_L_in <= Req_L_FF; end if; if flit_type = "100" and empty = '0' then if packet_drop = '1' then packet_drop_in <= '0'; end if; end if; end process; packet_drop_order_sig <= packet_drop; END;
gpl-3.0
298d5c8b787d492803638454a29fe694
0.600033
3.010534
false
true
false
false
AndyMcC0/UVVM_All
bitvis_irqc/src/irqc_pif.vhd
3
4,203
--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <[email protected]>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- VHDL unit : Bitvis IRQC Library : irqc_pif -- -- Description : See dedicated powerpoint presentation and README-file(s) ------------------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.irqc_pif_pkg.all; entity irqc_pif is port( arst : in std_logic; clk : in std_logic; -- CPU interface cs : in std_logic; addr : in unsigned; wr : in std_logic; rd : in std_logic; din : in std_logic_vector(7 downto 0); dout : out std_logic_vector(7 downto 0) := (others => '0'); -- p2c : out t_p2c; c2p : in t_c2p ); end irqc_pif; architecture rtl of irqc_pif is signal p2c_i : t_p2c; -- internal version of output signal dout_i : std_logic_vector(7 downto 0) := (others => '0'); begin -- Assigning internally used signals to outputs p2c <= p2c_i; p_read_reg : process(cs, addr, rd, c2p, p2c_i) begin -- default values dout_i <= (others => '0'); if cs = '1' and rd = '1' then case to_integer(addr) is when C_ADDR_IRR => dout_i(C_NUM_SOURCES-1 downto 0) <= c2p.aro_irr; when C_ADDR_IER => dout_i(C_NUM_SOURCES-1 downto 0) <= p2c_i.rw_ier; when C_ADDR_IPR => dout_i(C_NUM_SOURCES-1 downto 0) <= c2p.aro_ipr; when C_ADDR_IRQ2CPU_ALLOWED => dout_i(0) <= c2p.aro_irq2cpu_allowed; when others => null; end case; end if; end process p_read_reg; dout <= dout_i; -- Writing to registers that are not functionally manipulated p_write_reg : process(clk, arst) begin if arst = '1' then p2c_i.rw_ier <= (others => '0'); elsif rising_edge(clk) then if cs = '1' and wr = '1' then case to_integer(addr) is when C_ADDR_IER => p2c_i.rw_ier <= din(C_NUM_SOURCES-1 downto 0); -- Auxiliary write (below) when others => null; end case; end if; end if; end process p_write_reg; -- Writing to registers that are functionally manipulated and/or located outside PIF (or dummy registers) p_aux : process(wr, addr, din) begin -- Note that arst is not considered here, but must be considered in any clocked process in the core -- Default - always to return to these values p2c_i.awt_icr(C_NUM_SOURCES-1 downto 0) <= (others => '0'); p2c_i.awt_itr(C_NUM_SOURCES-1 downto 0) <= (others => '0'); p2c_i.awt_irq2cpu_ena <= '0'; p2c_i.awt_irq2cpu_disable <= '0'; if (cs = '1' and wr = '1') then case to_integer(addr) is when C_ADDR_ITR => p2c_i.awt_itr <= din(C_NUM_SOURCES-1 downto 0); when C_ADDR_ICR => p2c_i.awt_icr <= din(C_NUM_SOURCES-1 downto 0); when C_ADDR_IRQ2CPU_ENA => p2c_i.awt_irq2cpu_ena <= din(0); when C_ADDR_IRQ2CPU_DISABLE => p2c_i.awt_irq2cpu_disable <= din(0); when others => null; end case; end if; end process p_aux; end rtl;
mit
b14cfcec7a3bf47ef7340e56fc08dc68
0.532239
3.598459
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/Allocator_with_checkers_with_FI/allocator_with_checkers_with_FI.vhd
3
95,634
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.component_pack.all; entity allocator is port ( reset: in std_logic; clk: in std_logic; -- flow control credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic; req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic; req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic; req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic; req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic; req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic; empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic; -- grant_X_Y means the grant for X output port towards Y input port -- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot! valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic; grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic; grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic; grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic; grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic; grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic; -- fault injector shift register with serial input signals TCK: in std_logic; SE: in std_logic; -- shift enable UE: in std_logic; -- update enable SI: in std_logic; -- serial Input SO: out std_logic; -- serial output -- Allocator logic checker outputs err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N, err_grant_N_E_sig_not_empty_E_grant_N_E, err_not_grant_N_E_sig_or_empty_E_not_grant_N_E, err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W, err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S, err_grant_N_L_sig_not_empty_L_grant_N_L, err_not_grant_N_L_sig_or_empty_L_not_grant_N_L, err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N, err_grant_E_E_sig_not_empty_E_grant_E_E, err_not_grant_E_E_sig_or_empty_E_not_grant_E_E, err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W, err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S, err_grant_E_L_sig_not_empty_L_grant_E_L, err_not_grant_E_L_sig_or_empty_L_not_grant_E_L, err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N, err_grant_W_E_sig_not_empty_E_grant_W_E, err_not_grant_W_E_sig_or_empty_E_not_grant_W_E, err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W, err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S, err_grant_W_L_sig_not_empty_L_grant_W_L, err_not_grant_W_L_sig_or_empty_L_not_grant_W_L, err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N, err_grant_S_E_sig_not_empty_E_grant_S_E, err_not_grant_S_E_sig_or_empty_E_not_grant_S_E, err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W, err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S, err_grant_S_L_sig_not_empty_L_grant_S_L, err_not_grant_S_L_sig_or_empty_L_not_grant_S_L, err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N, err_grant_L_E_sig_not_empty_E_grant_L_E, err_not_grant_L_E_sig_or_empty_E_not_grant_L_E, err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W, err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S, err_grant_L_L_sig_not_empty_L_grant_L_L, err_not_grant_L_L_sig_or_empty_L_not_grant_L_L, err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N, err_grant_signals_not_empty_grant_E, err_not_grant_signals_empty_not_grant_E, err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W, err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S, err_grant_signals_not_empty_grant_L, err_not_grant_signals_empty_not_grant_L, err_grants_valid_not_match, -- Allocator credit counter logic checker outputs err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_N_credit_counter_N_out_increment, err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change, err_grant_N_credit_counter_N_out_decrement, err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change, err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_E_credit_counter_E_out_increment, err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change, err_grant_E_credit_counter_E_out_decrement, err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change, err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_W_credit_counter_W_out_increment, err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change, err_grant_W_credit_counter_W_out_decrement, err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change, err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_S_credit_counter_S_out_increment, err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change, err_grant_S_credit_counter_S_out_decrement, err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change, err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal, err_credit_in_L_credit_counter_L_out_increment, err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change, err_grant_L_credit_counter_L_out_decrement, err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change, err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal, -- Arbiter_in checker outputs -- North Arbiter_in checker outputs N_err_Requests_state_in_state_not_equal, N_err_IDLE_Req_N, N_err_IDLE_grant_N, N_err_North_Req_N, N_err_North_grant_N, N_err_East_Req_E, N_err_East_grant_E, N_err_West_Req_W, N_err_West_grant_W, N_err_South_Req_S,N_err_South_grant_S,N_err_Local_Req_L, N_err_Local_grant_L, N_err_IDLE_Req_E, N_err_IDLE_grant_E, N_err_North_Req_E, N_err_North_grant_E, N_err_East_Req_W, N_err_East_grant_W, N_err_West_Req_S, N_err_West_grant_S, N_err_South_Req_L, N_err_South_grant_L, N_err_Local_Req_N, N_err_Local_grant_N, N_err_IDLE_Req_W, N_err_IDLE_grant_W, N_err_North_Req_W, N_err_North_grant_W, N_err_East_Req_S, N_err_East_grant_S, N_err_West_Req_L, N_err_West_grant_L, N_err_South_Req_N, N_err_South_grant_N, N_err_Local_Req_E, N_err_Local_grant_E, N_err_IDLE_Req_S, N_err_IDLE_grant_S, N_err_North_Req_S, N_err_North_grant_S, N_err_East_Req_L, N_err_East_grant_L, N_err_West_Req_N, N_err_West_grant_N, N_err_South_Req_E, N_err_South_grant_E, N_err_Local_Req_W, N_err_Local_grant_W, N_err_IDLE_Req_L, N_err_IDLE_grant_L, N_err_North_Req_L, N_err_North_grant_L, N_err_East_Req_N, N_err_East_grant_N, N_err_West_Req_E, N_err_West_grant_E, N_err_South_Req_W, N_err_South_grant_W, N_err_Local_Req_S, N_err_Local_grant_S, N_err_state_in_onehot, N_err_no_request_grants, N_err_request_no_grants, N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L, -- East Arbiter_in checker outputs E_err_Requests_state_in_state_not_equal, E_err_IDLE_Req_N, E_err_IDLE_grant_N, E_err_North_Req_N, E_err_North_grant_N, E_err_East_Req_E, E_err_East_grant_E, E_err_West_Req_W, E_err_West_grant_W, E_err_South_Req_S, E_err_South_grant_S, E_err_Local_Req_L, E_err_Local_grant_L, E_err_IDLE_Req_E, E_err_IDLE_grant_E, E_err_North_Req_E, E_err_North_grant_E, E_err_East_Req_W, E_err_East_grant_W, E_err_West_Req_S, E_err_West_grant_S, E_err_South_Req_L, E_err_South_grant_L, E_err_Local_Req_N, E_err_Local_grant_N, E_err_IDLE_Req_W, E_err_IDLE_grant_W, E_err_North_Req_W, E_err_North_grant_W, E_err_East_Req_S, E_err_East_grant_S, E_err_West_Req_L, E_err_West_grant_L, E_err_South_Req_N, E_err_South_grant_N, E_err_Local_Req_E, E_err_Local_grant_E, E_err_IDLE_Req_S, E_err_IDLE_grant_S, E_err_North_Req_S, E_err_North_grant_S, E_err_East_Req_L, E_err_East_grant_L, E_err_West_Req_N, E_err_West_grant_N, E_err_South_Req_E, E_err_South_grant_E, E_err_Local_Req_W, E_err_Local_grant_W, E_err_IDLE_Req_L, E_err_IDLE_grant_L, E_err_North_Req_L, E_err_North_grant_L, E_err_East_Req_N, E_err_East_grant_N, E_err_West_Req_E, E_err_West_grant_E, E_err_South_Req_W, E_err_South_grant_W, E_err_Local_Req_S, E_err_Local_grant_S, E_err_state_in_onehot, E_err_no_request_grants, E_err_request_no_grants, E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L, -- West Arbiter_in checker outputs W_err_Requests_state_in_state_not_equal, W_err_IDLE_Req_N, W_err_IDLE_grant_N, W_err_North_Req_N, W_err_North_grant_N, W_err_East_Req_E, W_err_East_grant_E, W_err_West_Req_W, W_err_West_grant_W, W_err_South_Req_S, W_err_South_grant_S, W_err_Local_Req_L, W_err_Local_grant_L, W_err_IDLE_Req_E, W_err_IDLE_grant_E, W_err_North_Req_E, W_err_North_grant_E, W_err_East_Req_W, W_err_East_grant_W, W_err_West_Req_S, W_err_West_grant_S, W_err_South_Req_L, W_err_South_grant_L, W_err_Local_Req_N, W_err_Local_grant_N, W_err_IDLE_Req_W, W_err_IDLE_grant_W, W_err_North_Req_W, W_err_North_grant_W, W_err_East_Req_S, W_err_East_grant_S, W_err_West_Req_L, W_err_West_grant_L, W_err_South_Req_N, W_err_South_grant_N, W_err_Local_Req_E, W_err_Local_grant_E, W_err_IDLE_Req_S, W_err_IDLE_grant_S, W_err_North_Req_S, W_err_North_grant_S, W_err_East_Req_L, W_err_East_grant_L, W_err_West_Req_N, W_err_West_grant_N, W_err_South_Req_E, W_err_South_grant_E, W_err_Local_Req_W, W_err_Local_grant_W, W_err_IDLE_Req_L, W_err_IDLE_grant_L, W_err_North_Req_L, W_err_North_grant_L, W_err_East_Req_N, W_err_East_grant_N, W_err_West_Req_E, W_err_West_grant_E, W_err_South_Req_W, W_err_South_grant_W, W_err_Local_Req_S, W_err_Local_grant_S, W_err_state_in_onehot, W_err_no_request_grants, W_err_request_no_grants, W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L, -- South Arbiter_in checker outputs S_err_Requests_state_in_state_not_equal, S_err_IDLE_Req_N, S_err_IDLE_grant_N, S_err_North_Req_N, S_err_North_grant_N, S_err_East_Req_E, S_err_East_grant_E, S_err_West_Req_W, S_err_West_grant_W, S_err_South_Req_S,S_err_South_grant_S,S_err_Local_Req_L, S_err_Local_grant_L, S_err_IDLE_Req_E, S_err_IDLE_grant_E, S_err_North_Req_E, S_err_North_grant_E, S_err_East_Req_W, S_err_East_grant_W, S_err_West_Req_S, S_err_West_grant_S, S_err_South_Req_L, S_err_South_grant_L, S_err_Local_Req_N, S_err_Local_grant_N, S_err_IDLE_Req_W, S_err_IDLE_grant_W, S_err_North_Req_W, S_err_North_grant_W, S_err_East_Req_S, S_err_East_grant_S, S_err_West_Req_L, S_err_West_grant_L, S_err_South_Req_N, S_err_South_grant_N, S_err_Local_Req_E, S_err_Local_grant_E, S_err_IDLE_Req_S, S_err_IDLE_grant_S, S_err_North_Req_S, S_err_North_grant_S, S_err_East_Req_L, S_err_East_grant_L, S_err_West_Req_N, S_err_West_grant_N, S_err_South_Req_E, S_err_South_grant_E, S_err_Local_Req_W, S_err_Local_grant_W, S_err_IDLE_Req_L, S_err_IDLE_grant_L, S_err_North_Req_L, S_err_North_grant_L, S_err_East_Req_N, S_err_East_grant_N, S_err_West_Req_E, S_err_West_grant_E, S_err_South_Req_W, S_err_South_grant_W, S_err_Local_Req_S, S_err_Local_grant_S, S_err_state_in_onehot, S_err_no_request_grants, S_err_request_no_grants, S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L, -- Local Arbiter_in checker outputs L_err_Requests_state_in_state_not_equal, L_err_IDLE_Req_N, L_err_IDLE_grant_N, L_err_North_Req_N, L_err_North_grant_N, L_err_East_Req_E, L_err_East_grant_E, L_err_West_Req_W, L_err_West_grant_W, L_err_South_Req_S, L_err_South_grant_S, L_err_Local_Req_L, L_err_Local_grant_L, L_err_IDLE_Req_E, L_err_IDLE_grant_E, L_err_North_Req_E, L_err_North_grant_E, L_err_East_Req_W, L_err_East_grant_W, L_err_West_Req_S, L_err_West_grant_S, L_err_South_Req_L, L_err_South_grant_L, L_err_Local_Req_N, L_err_Local_grant_N, L_err_IDLE_Req_W, L_err_IDLE_grant_W, L_err_North_Req_W, L_err_North_grant_W, L_err_East_Req_S, L_err_East_grant_S, L_err_West_Req_L, L_err_West_grant_L, L_err_South_Req_N, L_err_South_grant_N, L_err_Local_Req_E, L_err_Local_grant_E, L_err_IDLE_Req_S, L_err_IDLE_grant_S, L_err_North_Req_S, L_err_North_grant_S, L_err_East_Req_L, L_err_East_grant_L, L_err_West_Req_N, L_err_West_grant_N, L_err_South_Req_E, L_err_South_grant_E, L_err_Local_Req_W, L_err_Local_grant_W, L_err_IDLE_Req_L, L_err_IDLE_grant_L, L_err_North_Req_L, L_err_North_grant_L, L_err_East_Req_N, L_err_East_grant_N, L_err_West_Req_E, L_err_West_grant_E, L_err_South_Req_W, L_err_South_grant_W, L_err_Local_Req_S, L_err_Local_grant_S, L_err_state_in_onehot, L_err_no_request_grants, L_err_request_no_grants, L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S, L_err_no_Req_L_grant_L, -- Arbiter_out checker outputs -- North Arbiter_out checker outputs N_arbiter_out_err_Requests_state_in_state_not_equal, N_err_IDLE_req_X_N, N_err_North_req_X_N, N_err_North_credit_not_zero_req_X_N_grant_N, N_err_North_credit_zero_or_not_req_X_N_not_grant_N, N_err_East_req_X_E, N_err_East_credit_not_zero_req_X_E_grant_E, N_err_East_credit_zero_or_not_req_X_E_not_grant_E, N_err_West_req_X_W, N_err_West_credit_not_zero_req_X_W_grant_W, N_err_West_credit_zero_or_not_req_X_W_not_grant_W, N_err_South_req_X_S, N_err_South_credit_not_zero_req_X_S_grant_S, N_err_South_credit_zero_or_not_req_X_S_not_grant_S, N_err_Local_req_X_L, N_err_Local_credit_not_zero_req_X_L_grant_L, N_err_Local_credit_zero_or_not_req_X_L_not_grant_L, N_err_IDLE_req_X_E, N_err_North_req_X_E, N_err_East_req_X_W, N_err_West_req_X_S, N_err_South_req_X_L, N_err_Local_req_X_N, N_err_IDLE_req_X_W, N_err_North_req_X_W, N_err_East_req_X_S, N_err_West_req_X_L, N_err_South_req_X_N, N_err_Local_req_X_E, N_err_IDLE_req_X_S, N_err_North_req_X_S, N_err_East_req_X_L, N_err_West_req_X_N, N_err_South_req_X_E, N_err_Local_req_X_W, N_err_IDLE_req_X_L, N_err_North_req_X_L, N_err_East_req_X_N, N_err_West_req_X_E, N_err_South_req_X_W, N_err_Local_req_X_S, N_arbiter_out_err_state_in_onehot, N_arbiter_out_err_no_request_grants, N_err_request_IDLE_state, N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant, N_err_state_West_Invalid_Grant, N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant, N_err_Grants_onehot_or_all_zero, -- East Arbiter_out checker outputs E_arbiter_out_err_Requests_state_in_state_not_equal, E_err_IDLE_req_X_N, E_err_North_req_X_N, E_err_North_credit_not_zero_req_X_N_grant_N, E_err_North_credit_zero_or_not_req_X_N_not_grant_N, E_err_East_req_X_E, E_err_East_credit_not_zero_req_X_E_grant_E, E_err_East_credit_zero_or_not_req_X_E_not_grant_E, E_err_West_req_X_W, E_err_West_credit_not_zero_req_X_W_grant_W, E_err_West_credit_zero_or_not_req_X_W_not_grant_W, E_err_South_req_X_S, E_err_South_credit_not_zero_req_X_S_grant_S, E_err_South_credit_zero_or_not_req_X_S_not_grant_S, E_err_Local_req_X_L, E_err_Local_credit_not_zero_req_X_L_grant_L, E_err_Local_credit_zero_or_not_req_X_L_not_grant_L, E_err_IDLE_req_X_E, E_err_North_req_X_E, E_err_East_req_X_W, E_err_West_req_X_S, E_err_South_req_X_L, E_err_Local_req_X_N, E_err_IDLE_req_X_W, E_err_North_req_X_W, E_err_East_req_X_S, E_err_West_req_X_L, E_err_South_req_X_N, E_err_Local_req_X_E, E_err_IDLE_req_X_S, E_err_North_req_X_S, E_err_East_req_X_L, E_err_West_req_X_N, E_err_South_req_X_E, E_err_Local_req_X_W, E_err_IDLE_req_X_L, E_err_North_req_X_L, E_err_East_req_X_N, E_err_West_req_X_E, E_err_South_req_X_W, E_err_Local_req_X_S, E_arbiter_out_err_state_in_onehot, E_arbiter_out_err_no_request_grants, E_err_request_IDLE_state, E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant,E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant, E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero, -- West Arbiter_out checker outputs W_arbiter_out_err_Requests_state_in_state_not_equal, W_err_IDLE_req_X_N, W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N, W_err_North_credit_zero_or_not_req_X_N_not_grant_N, W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E, W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W, W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S, W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L, W_err_IDLE_req_X_E, W_err_North_req_X_E, W_err_East_req_X_W, W_err_West_req_X_S, W_err_South_req_X_L, W_err_Local_req_X_N, W_err_IDLE_req_X_W, W_err_North_req_X_W, W_err_East_req_X_S, W_err_West_req_X_L, W_err_South_req_X_N, W_err_Local_req_X_E, W_err_IDLE_req_X_S, W_err_North_req_X_S, W_err_East_req_X_L, W_err_West_req_X_N, W_err_South_req_X_E, W_err_Local_req_X_W, W_err_IDLE_req_X_L, W_err_North_req_X_L, W_err_East_req_X_N, W_err_West_req_X_E, W_err_South_req_X_W, W_err_Local_req_X_S, W_arbiter_out_err_state_in_onehot, W_arbiter_out_err_no_request_grants, W_err_request_IDLE_state, W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant, W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant, W_err_state_South_Invalid_Grant, W_err_state_Local_Invalid_Grant, W_err_Grants_onehot_or_all_zero, -- South Arbiter_out checker outputs S_arbiter_out_err_Requests_state_in_state_not_equal, S_err_IDLE_req_X_N, S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N, S_err_North_credit_zero_or_not_req_X_N_not_grant_N, S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E, S_err_East_credit_zero_or_not_req_X_E_not_grant_E, S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W, S_err_West_credit_zero_or_not_req_X_W_not_grant_W, S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S, S_err_South_credit_zero_or_not_req_X_S_not_grant_S, S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L, S_err_Local_credit_zero_or_not_req_X_L_not_grant_L, S_err_IDLE_req_X_E, S_err_North_req_X_E, S_err_East_req_X_W, S_err_West_req_X_S, S_err_South_req_X_L, S_err_Local_req_X_N, S_err_IDLE_req_X_W, S_err_North_req_X_W, S_err_East_req_X_S, S_err_West_req_X_L, S_err_South_req_X_N, S_err_Local_req_X_E, S_err_IDLE_req_X_S, S_err_North_req_X_S, S_err_East_req_X_L, S_err_West_req_X_N, S_err_South_req_X_E, S_err_Local_req_X_W, S_err_IDLE_req_X_L, S_err_North_req_X_L, S_err_East_req_X_N, S_err_West_req_X_E, S_err_South_req_X_W, S_err_Local_req_X_S, S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state, S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant, S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero, -- Local Arbiter_out checker outputs L_arbiter_out_err_Requests_state_in_state_not_equal, L_err_IDLE_req_X_N, L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N, L_err_North_credit_zero_or_not_req_X_N_not_grant_N, L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E, L_err_East_credit_zero_or_not_req_X_E_not_grant_E, L_err_West_req_X_W, L_err_West_credit_not_zero_req_X_W_grant_W, L_err_West_credit_zero_or_not_req_X_W_not_grant_W, L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S, L_err_South_credit_zero_or_not_req_X_S_not_grant_S, L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L, L_err_Local_credit_zero_or_not_req_X_L_not_grant_L, L_err_IDLE_req_X_E, L_err_North_req_X_E, L_err_East_req_X_W, L_err_West_req_X_S, L_err_South_req_X_L, L_err_Local_req_X_N, L_err_IDLE_req_X_W, L_err_North_req_X_W, L_err_East_req_X_S, L_err_West_req_X_L, L_err_South_req_X_N, L_err_Local_req_X_E, L_err_IDLE_req_X_S, L_err_North_req_X_S, L_err_East_req_X_L, L_err_West_req_X_N, L_err_South_req_X_E, L_err_Local_req_X_W, L_err_IDLE_req_X_L, L_err_North_req_X_L, L_err_East_req_X_N, L_err_West_req_X_E, L_err_South_req_X_W, L_err_Local_req_X_S, L_arbiter_out_err_state_in_onehot, L_arbiter_out_err_no_request_grants, L_err_request_IDLE_state, L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant, L_err_state_East_Invalid_Grant, L_err_state_West_Invalid_Grant, L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant, L_err_Grants_onehot_or_all_zero : out std_logic ); end allocator; architecture behavior of allocator is -- Allocator logic checker outputs and allocator credit counter logic checker outputs go directly to the output interface of Allocator ---------------------------------------- -- Signals related to fault injection -- ---------------------------------------- -- Total: 9 bits -- What about Arbiter_in and Arbiter_out ?! signal FI_add_sta: std_logic_vector (8 downto 0); -- 7 bits for fault injection location address (ceil of log2(80) = 7) -- 2 bits for type of fault (SA0 or SA1) signal non_faulty_signals: std_logic_vector (79 downto 0); -- 80 bits for internal- and output-related signals (non-faulty) signal faulty_signals: std_logic_vector(79 downto 0); -- 80 bits for internal- and output-related signals (with single stuck-at fault injected in one of them) -- For making the chain of faulty data from L, N, E, W and S Arbiter_in and then to L, N, E, W and S Arbiter_out and then to the output of Allocator signal fault_DO_serial_L_Arbiter_in_N_Arbiter_in, fault_DO_serial_N_Arbiter_in_E_Arbiter_in, fault_DO_serial_E_Arbiter_in_W_Arbiter_in: std_logic; signal fault_DO_serial_W_Arbiter_in_S_Arbiter_in, fault_DO_serial_S_Arbiter_in_L_Arbiter_out, fault_DO_serial_L_Arbiter_out_N_Arbiter_out: std_logic; signal fault_DO_serial_N_Arbiter_out_E_Arbiter_out, fault_DO_serial_E_Arbiter_out_W_Arbiter_out, fault_DO_serial_W_Arbiter_out_S_Arbiter_out: std_logic; signal fault_DO_serial_S_Arbiter_out_Allocator_logic: std_logic; ---------------------------------------- ---------------------------------------- -- So the idea is that we should have counters that keep track of credit! signal credit_counter_N_in, credit_counter_N_out: std_logic_vector(1 downto 0); signal credit_counter_E_in, credit_counter_E_out: std_logic_vector(1 downto 0); signal credit_counter_W_in, credit_counter_W_out: std_logic_vector(1 downto 0); signal credit_counter_S_in, credit_counter_S_out: std_logic_vector(1 downto 0); signal credit_counter_L_in, credit_counter_L_out: std_logic_vector(1 downto 0); signal grant_N, grant_E, grant_W, grant_S, grant_L: std_logic; signal X_N_N, X_N_E, X_N_W, X_N_S, X_N_L: std_logic; signal X_E_N, X_E_E, X_E_W, X_E_S, X_E_L: std_logic; signal X_W_N, X_W_E, X_W_W, X_W_S, X_W_L: std_logic; signal X_S_N, X_S_E, X_S_W, X_S_S, X_S_L: std_logic; signal X_L_N, X_L_E, X_L_W, X_L_S, X_L_L: std_logic; -- These signals belong to Allocator signal grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: std_logic; signal grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: std_logic; signal grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: std_logic; signal grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: std_logic; signal grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: std_logic; -- These signals are introduced when connecting output-related signals to the allocator checkers signal valid_N_sig, valid_E_sig, valid_W_sig, valid_S_sig, valid_L_sig : std_logic; signal grant_N_N_signal, grant_N_E_signal, grant_N_W_signal, grant_N_S_signal, grant_N_L_signal: std_logic; signal grant_E_N_signal, grant_E_E_signal, grant_E_W_signal, grant_E_S_signal, grant_E_L_signal: std_logic; signal grant_W_N_signal, grant_W_E_signal, grant_W_W_signal, grant_W_S_signal, grant_W_L_signal: std_logic; signal grant_S_N_signal, grant_S_E_signal, grant_S_W_signal, grant_S_S_signal, grant_S_L_signal: std_logic; signal grant_L_N_signal, grant_L_E_signal, grant_L_W_signal, grant_L_S_signal, grant_L_L_signal: std_logic; -- Signal(s) used for creating the chain of injected fault locations -- Total: ?? bits ??!! -- Allocator internal-related signals signal credit_counter_N_in_faulty, credit_counter_N_out_faulty: std_logic_vector(1 downto 0); signal credit_counter_E_in_faulty, credit_counter_E_out_faulty: std_logic_vector(1 downto 0); signal credit_counter_W_in_faulty, credit_counter_W_out_faulty: std_logic_vector(1 downto 0); signal credit_counter_S_in_faulty, credit_counter_S_out_faulty: std_logic_vector(1 downto 0); signal credit_counter_L_in_faulty, credit_counter_L_out_faulty: std_logic_vector(1 downto 0); signal grant_N_faulty, grant_E_faulty, grant_W_faulty, grant_S_faulty, grant_L_faulty: std_logic; signal grant_N_N_sig_faulty, grant_N_E_sig_faulty, grant_N_W_sig_faulty, grant_N_S_sig_faulty, grant_N_L_sig_faulty: std_logic; signal grant_E_N_sig_faulty, grant_E_E_sig_faulty, grant_E_W_sig_faulty, grant_E_S_sig_faulty, grant_E_L_sig_faulty: std_logic; signal grant_W_N_sig_faulty, grant_W_E_sig_faulty, grant_W_W_sig_faulty, grant_W_S_sig_faulty, grant_W_L_sig_faulty: std_logic; signal grant_S_N_sig_faulty, grant_S_E_sig_faulty, grant_S_W_sig_faulty, grant_S_S_sig_faulty, grant_S_L_sig_faulty: std_logic; signal grant_L_N_sig_faulty, grant_L_E_sig_faulty, grant_L_W_sig_faulty, grant_L_S_sig_faulty, grant_L_L_sig_faulty: std_logic; -- Allocator output-related signals signal valid_N_sig_faulty, valid_E_sig_faulty, valid_W_sig_faulty, valid_S_sig_faulty, valid_L_sig_faulty : std_logic; signal grant_N_N_signal_faulty, grant_N_E_signal_faulty, grant_N_W_signal_faulty, grant_N_S_signal_faulty, grant_N_L_signal_faulty: std_logic; signal grant_E_N_signal_faulty, grant_E_E_signal_faulty, grant_E_W_signal_faulty, grant_E_S_signal_faulty, grant_E_L_signal_faulty: std_logic; signal grant_W_N_signal_faulty, grant_W_E_signal_faulty, grant_W_W_signal_faulty, grant_W_S_signal_faulty, grant_W_L_signal_faulty: std_logic; signal grant_S_N_signal_faulty, grant_S_E_signal_faulty, grant_S_W_signal_faulty, grant_S_S_signal_faulty, grant_S_L_signal_faulty: std_logic; signal grant_L_N_signal_faulty, grant_L_E_signal_faulty, grant_L_W_signal_faulty, grant_L_S_signal_faulty, grant_L_L_signal_faulty: std_logic; begin ------------------------------------- ---- Related to fault injection ----- ------------------------------------- -- Total: 80 bits -- for valid and grant output signals, not sure whether to include them or the signals with _sig and _signal suffix in their name ??!! non_faulty_signals <= credit_counter_N_in & credit_counter_N_out & credit_counter_E_in & credit_counter_E_out & credit_counter_W_in & credit_counter_W_out & credit_counter_S_in & credit_counter_S_out & credit_counter_L_in & credit_counter_L_out & grant_N & grant_E & grant_W & grant_S & grant_L & grant_N_N_sig & grant_N_E_sig & grant_N_W_sig & grant_N_S_sig & grant_N_L_sig & grant_E_N_sig & grant_E_E_sig & grant_E_W_sig & grant_E_S_sig & grant_E_L_sig & grant_W_N_sig & grant_W_E_sig & grant_W_W_sig & grant_W_S_sig & grant_W_L_sig & grant_S_N_sig & grant_S_E_sig & grant_S_W_sig & grant_S_S_sig & grant_S_L_sig & grant_L_N_sig & grant_L_E_sig & grant_L_W_sig & grant_L_S_sig & grant_L_L_sig & valid_N_sig & valid_E_sig & valid_W_sig & valid_S_sig & valid_L_sig & grant_N_N_signal & grant_N_E_signal & grant_N_W_signal & grant_N_S_signal & grant_N_L_signal & grant_E_N_signal & grant_E_E_signal & grant_E_W_signal & grant_E_S_signal & grant_E_L_signal & grant_W_N_signal & grant_W_E_signal & grant_W_W_signal & grant_W_S_signal & grant_W_L_signal & grant_S_N_signal & grant_S_E_signal & grant_S_W_signal & grant_S_S_signal & grant_S_L_signal & grant_L_N_signal & grant_L_E_signal & grant_L_W_signal & grant_L_S_signal & grant_L_L_signal; -- Fault injector module instantiation FI: fault_injector generic map(DATA_WIDTH => 80, ADDRESS_WIDTH => 7) port map (data_in=> non_faulty_signals , address => FI_add_sta(8 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals ); -- Extracting faulty values for internal- and output-related signals -- Total: 17 bits credit_counter_N_in_faulty <= faulty_signals (79 downto 78); credit_counter_N_out_faulty <= faulty_signals (77 downto 76); credit_counter_E_in_faulty <= faulty_signals (75 downto 74); credit_counter_E_out_faulty <= faulty_signals (73 downto 72); credit_counter_W_in_faulty <= faulty_signals (71 downto 70); credit_counter_W_out_faulty <= faulty_signals (69 downto 68); credit_counter_S_in_faulty <= faulty_signals (67 downto 66); credit_counter_S_out_faulty <= faulty_signals (65 downto 64); credit_counter_L_in_faulty <= faulty_signals (63 downto 62); credit_counter_L_out_faulty <= faulty_signals (61 downto 60); grant_N_faulty <= faulty_signals (59); grant_E_faulty <= faulty_signals (58); grant_W_faulty <= faulty_signals (57); grant_S_faulty <= faulty_signals (56); grant_L_faulty <= faulty_signals (55); grant_N_N_sig_faulty <= faulty_signals (54); grant_N_E_sig_faulty <= faulty_signals (53); grant_N_W_sig_faulty <= faulty_signals (52); grant_N_S_sig_faulty <= faulty_signals (51); grant_N_L_sig_faulty <= faulty_signals (50); grant_E_N_sig_faulty <= faulty_signals (49); grant_E_E_sig_faulty <= faulty_signals (48); grant_E_W_sig_faulty <= faulty_signals (47); grant_E_S_sig_faulty <= faulty_signals (46); grant_E_L_sig_faulty <= faulty_signals (45); grant_W_N_sig_faulty <= faulty_signals (44); grant_W_E_sig_faulty <= faulty_signals (43); grant_W_W_sig_faulty <= faulty_signals (42); grant_W_S_sig_faulty <= faulty_signals (41); grant_W_L_sig_faulty <= faulty_signals (40); grant_S_N_sig_faulty <= faulty_signals (39); grant_S_E_sig_faulty <= faulty_signals (38); grant_S_W_sig_faulty <= faulty_signals (37); grant_S_S_sig_faulty <= faulty_signals (36); grant_S_L_sig_faulty <= faulty_signals (35); grant_L_N_sig_faulty <= faulty_signals (34); grant_L_E_sig_faulty <= faulty_signals (33); grant_L_W_sig_faulty <= faulty_signals (32); grant_L_S_sig_faulty <= faulty_signals (31); grant_L_L_sig_faulty <= faulty_signals (30); valid_N_sig_faulty <= faulty_signals (29); valid_E_sig_faulty <= faulty_signals (28); valid_W_sig_faulty <= faulty_signals (27); valid_S_sig_faulty <= faulty_signals (26); valid_L_sig_faulty <= faulty_signals (25); grant_N_N_signal_faulty <= faulty_signals (24); grant_N_E_signal_faulty <= faulty_signals (23); grant_N_W_signal_faulty <= faulty_signals (22); grant_N_S_signal_faulty <= faulty_signals (21); grant_N_L_signal_faulty <= faulty_signals (20); grant_E_N_signal_faulty <= faulty_signals (19); grant_E_E_signal_faulty <= faulty_signals (18); grant_E_W_signal_faulty <= faulty_signals (17); grant_E_S_signal_faulty <= faulty_signals (16); grant_E_L_signal_faulty <= faulty_signals (15); grant_W_N_signal_faulty <= faulty_signals (14); grant_W_E_signal_faulty <= faulty_signals (13); grant_W_W_signal_faulty <= faulty_signals (12); grant_W_S_signal_faulty <= faulty_signals (11); grant_W_L_signal_faulty <= faulty_signals (10); grant_S_N_signal_faulty <= faulty_signals (9); grant_S_E_signal_faulty <= faulty_signals (8); grant_S_W_signal_faulty <= faulty_signals (7); grant_S_S_signal_faulty <= faulty_signals (6); grant_S_L_signal_faulty <= faulty_signals (5); grant_L_N_signal_faulty <= faulty_signals (4); grant_L_E_signal_faulty <= faulty_signals (3); grant_L_W_signal_faulty <= faulty_signals (2); grant_L_S_signal_faulty <= faulty_signals (1); grant_L_L_signal_faulty <= faulty_signals (0); -- Total: 9 bits SR: shift_register_serial_in generic map(REG_WIDTH => 9) -- What about Arbiter_in and Arbiter_out ?! port map ( TCK=> TCK, reset=>reset, SE=> SE, UE => UE, SI=> fault_DO_serial_S_Arbiter_out_Allocator_logic, data_out_parallel=> FI_add_sta, SO=> SO ); ------------------------------------- ------------------------------------- -- We did this because of the checkers valid_N <= valid_N_sig; valid_E <= valid_E_sig; valid_W <= valid_W_sig; valid_S <= valid_S_sig; valid_L <= valid_L_sig; grant_N_N <= grant_N_N_signal; grant_E_N <= grant_E_N_signal; grant_W_N <= grant_W_N_signal; grant_S_N <= grant_S_N_signal; grant_L_N <= grant_L_N_signal; grant_N_E <= grant_N_E_signal; grant_E_E <= grant_E_E_signal; grant_W_E <= grant_W_E_signal; grant_S_E <= grant_S_E_signal; grant_L_E <= grant_L_E_signal; grant_N_W <= grant_N_W_signal; grant_E_W <= grant_E_W_signal; grant_W_W <= grant_W_W_signal; grant_S_W <= grant_S_W_signal; grant_L_W <= grant_L_W_signal; grant_N_S <= grant_N_S_signal; grant_E_S <= grant_E_S_signal; grant_W_S <= grant_W_S_signal; grant_S_S <= grant_S_S_signal; grant_L_S <= grant_L_S_signal; grant_N_L <= grant_N_L_signal; grant_E_L <= grant_E_L_signal; grant_W_L <= grant_W_L_signal; grant_S_L <= grant_S_L_signal; grant_L_L <= grant_L_L_signal; -- sequential part process(clk, reset) begin if reset = '0' then -- we start with all full cradit credit_counter_N_out <= (others=>'1'); credit_counter_E_out <= (others=>'1'); credit_counter_W_out <= (others=>'1'); credit_counter_S_out <= (others=>'1'); credit_counter_L_out <= (others=>'1'); elsif clk'event and clk = '1' then credit_counter_N_out <= credit_counter_N_in; credit_counter_E_out <= credit_counter_E_in; credit_counter_W_out <= credit_counter_W_in; credit_counter_S_out <= credit_counter_S_in; credit_counter_L_out <= credit_counter_L_in; end if; end process; -- The combionational part -- Taking Arbiter_in checker outputs to outputs of Allocator ??!! (Behrad has written this :( ) grant_N_N_signal <= grant_N_N_sig and not empty_N; grant_N_E_signal <= grant_N_E_sig and not empty_E; grant_N_W_signal <= grant_N_W_sig and not empty_W; grant_N_S_signal <= grant_N_S_sig and not empty_S; grant_N_L_signal <= grant_N_L_sig and not empty_L; grant_E_N_signal <= grant_E_N_sig and not empty_N; grant_E_E_signal <= grant_E_E_sig and not empty_E; grant_E_W_signal <= grant_E_W_sig and not empty_W; grant_E_S_signal <= grant_E_S_sig and not empty_S; grant_E_L_signal <= grant_E_L_sig and not empty_L; grant_W_N_signal <= grant_W_N_sig and not empty_N; grant_W_E_signal <= grant_W_E_sig and not empty_E; grant_W_W_signal <= grant_W_W_sig and not empty_W; grant_W_S_signal <= grant_W_S_sig and not empty_S; grant_W_L_signal <= grant_W_L_sig and not empty_L; grant_S_N_signal <= grant_S_N_sig and not empty_N; grant_S_E_signal <= grant_S_E_sig and not empty_E; grant_S_W_signal <= grant_S_W_sig and not empty_W; grant_S_S_signal <= grant_S_S_sig and not empty_S; grant_S_L_signal <= grant_S_L_sig and not empty_L; grant_L_N_signal <= grant_L_N_sig and not empty_N; grant_L_E_signal <= grant_L_E_sig and not empty_E; grant_L_W_signal <= grant_L_W_sig and not empty_W; grant_L_S_signal <= grant_L_S_sig and not empty_S; grant_L_L_signal <= grant_L_L_sig and not empty_L; grant_N <= (grant_N_N_sig and not empty_N )or (grant_N_E_sig and not empty_E) or (grant_N_W_sig and not empty_W) or (grant_N_S_sig and not empty_S) or (grant_N_L_sig and not empty_L); grant_E <= (grant_E_N_sig and not empty_N )or (grant_E_E_sig and not empty_E) or (grant_E_W_sig and not empty_W) or (grant_E_S_sig and not empty_S) or (grant_E_L_sig and not empty_L); grant_W <= (grant_W_N_sig and not empty_N )or (grant_W_E_sig and not empty_E) or (grant_W_W_sig and not empty_W) or (grant_W_S_sig and not empty_S) or (grant_W_L_sig and not empty_L); grant_S <= (grant_S_N_sig and not empty_N )or (grant_S_E_sig and not empty_E) or (grant_S_W_sig and not empty_W) or (grant_S_S_sig and not empty_S) or (grant_S_L_sig and not empty_L); grant_L <= (grant_L_N_sig and not empty_N )or (grant_L_E_sig and not empty_E) or (grant_L_W_sig and not empty_W) or (grant_L_S_sig and not empty_S) or (grant_L_L_sig and not empty_L); -- this process handles the credit counters! process(credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L, grant_N, grant_E, grant_W, grant_S, grant_L, credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out ) begin credit_counter_N_in <= credit_counter_N_out; credit_counter_E_in <= credit_counter_E_out; credit_counter_W_in <= credit_counter_W_out; credit_counter_S_in <= credit_counter_S_out; credit_counter_L_in <= credit_counter_L_out; if credit_in_N = '1' and grant_N = '1' then credit_counter_N_in <= credit_counter_N_out; elsif credit_in_N = '1' and credit_counter_N_out < 3 then credit_counter_N_in <= credit_counter_N_out + 1; elsif grant_N = '1' and credit_counter_N_out > 0 then credit_counter_N_in <= credit_counter_N_out - 1; end if; if credit_in_E = '1' and grant_E = '1' then credit_counter_E_in <= credit_counter_E_out; elsif credit_in_E = '1' and credit_counter_E_out < 3 then credit_counter_E_in <= credit_counter_E_out + 1; elsif grant_E = '1' and credit_counter_E_out > 0 then credit_counter_E_in <= credit_counter_E_out - 1; end if; if credit_in_W = '1' and grant_W = '1' then credit_counter_W_in <= credit_counter_W_out; elsif credit_in_W = '1' and credit_counter_W_out < 3 then credit_counter_W_in <= credit_counter_W_out + 1; elsif grant_W = '1' and credit_counter_W_out > 0 then credit_counter_W_in <= credit_counter_W_out - 1; end if; if credit_in_S = '1' and grant_S = '1' then credit_counter_S_in <= credit_counter_S_out; elsif credit_in_S = '1' and credit_counter_S_out < 3 then credit_counter_S_in <= credit_counter_S_out + 1; elsif grant_S = '1' and credit_counter_S_out > 0 then credit_counter_S_in <= credit_counter_S_out - 1; end if; if credit_in_L = '1' and grant_L = '1' then credit_counter_L_in <= credit_counter_L_out; elsif credit_in_L = '1' and credit_counter_L_out < 3 then credit_counter_L_in <= credit_counter_L_out + 1; elsif grant_L = '1' and credit_counter_L_out > 0 then credit_counter_L_in <= credit_counter_L_out - 1; end if; end process; --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Allocator logic checkers module instantiation ALLOCATOR_LOGIC_CHECKERS: allocator_logic_pseudo_checkers PORT MAP ( empty_N => empty_N, empty_E => empty_E, empty_W => empty_W, empty_S => empty_S, empty_L => empty_L, grant_N_N_sig => grant_N_N_sig_faulty, grant_N_E_sig => grant_N_E_sig_faulty, grant_N_W_sig => grant_N_W_sig_faulty, grant_N_S_sig => grant_N_S_sig_faulty, grant_N_L_sig => grant_N_L_sig_faulty, grant_E_N_sig => grant_E_N_sig_faulty, grant_E_E_sig => grant_E_E_sig_faulty, grant_E_W_sig => grant_E_W_sig_faulty, grant_E_S_sig => grant_E_S_sig_faulty, grant_E_L_sig => grant_E_L_sig_faulty, grant_W_N_sig => grant_W_N_sig_faulty, grant_W_E_sig => grant_W_E_sig_faulty, grant_W_W_sig => grant_W_W_sig_faulty, grant_W_S_sig => grant_W_S_sig_faulty, grant_W_L_sig => grant_W_L_sig_faulty, grant_S_N_sig => grant_S_N_sig_faulty, grant_S_E_sig => grant_S_E_sig_faulty, grant_S_W_sig => grant_S_W_sig_faulty, grant_S_S_sig => grant_S_S_sig_faulty, grant_S_L_sig => grant_S_L_sig_faulty, grant_L_N_sig => grant_L_N_sig_faulty, grant_L_E_sig => grant_L_E_sig_faulty, grant_L_W_sig => grant_L_W_sig_faulty, grant_L_S_sig => grant_L_S_sig_faulty, grant_L_L_sig => grant_L_L_sig_faulty, valid_N => valid_N_sig_faulty, valid_E => valid_E_sig_faulty, valid_W => valid_W_sig_faulty, valid_S => valid_S_sig_faulty, valid_L => valid_L_sig_faulty, grant_N_N => grant_N_N_signal_faulty, grant_N_E => grant_N_E_signal_faulty, grant_N_W => grant_N_W_signal_faulty, grant_N_S => grant_N_S_signal_faulty, grant_N_L => grant_N_L_signal_faulty, grant_E_N => grant_E_N_signal_faulty, grant_E_E => grant_E_E_signal_faulty, grant_E_W => grant_E_W_signal_faulty, grant_E_S => grant_E_S_signal_faulty, grant_E_L => grant_E_L_signal_faulty, grant_W_N => grant_W_N_signal_faulty, grant_W_E => grant_W_E_signal_faulty, grant_W_W => grant_W_W_signal_faulty, grant_W_S => grant_W_S_signal_faulty, grant_W_L => grant_W_L_signal_faulty, grant_S_N => grant_S_N_signal_faulty, grant_S_E => grant_S_E_signal_faulty, grant_S_W => grant_S_W_signal_faulty, grant_S_S => grant_S_S_signal_faulty, grant_S_L => grant_S_L_signal_faulty, grant_L_N => grant_L_N_signal_faulty, grant_L_E => grant_L_E_signal_faulty, grant_L_W => grant_L_W_signal_faulty, grant_L_S => grant_L_S_signal_faulty, grant_L_L => grant_L_L_signal_faulty, grant_N => grant_N_faulty, grant_E => grant_E_faulty, grant_W => grant_W_faulty, grant_S => grant_S_faulty, grant_L => grant_L_faulty, -- Checker Outputs err_grant_N_N_sig_not_empty_N_grant_N_N => err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N => err_not_grant_N_N_sig_or_empty_N_not_grant_N_N, err_grant_N_E_sig_not_empty_E_grant_N_E => err_grant_N_E_sig_not_empty_E_grant_N_E, err_not_grant_N_E_sig_or_empty_E_not_grant_N_E => err_not_grant_N_E_sig_or_empty_E_not_grant_N_E, err_grant_N_W_sig_not_empty_W_grant_N_W => err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W => err_not_grant_N_W_sig_or_empty_W_not_grant_N_W, err_grant_N_S_sig_not_empty_S_grant_N_S => err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S => err_not_grant_N_S_sig_or_empty_S_not_grant_N_S, err_grant_N_L_sig_not_empty_L_grant_N_L => err_grant_N_L_sig_not_empty_L_grant_N_L, err_not_grant_N_L_sig_or_empty_L_not_grant_N_L => err_not_grant_N_L_sig_or_empty_L_not_grant_N_L, err_grant_E_N_sig_not_empty_N_grant_E_N => err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N => err_not_grant_E_N_sig_or_empty_N_not_grant_E_N, err_grant_E_E_sig_not_empty_E_grant_E_E => err_grant_E_E_sig_not_empty_E_grant_E_E, err_not_grant_E_E_sig_or_empty_E_not_grant_E_E => err_not_grant_E_E_sig_or_empty_E_not_grant_E_E, err_grant_E_W_sig_not_empty_W_grant_E_W => err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W => err_not_grant_E_W_sig_or_empty_W_not_grant_E_W, err_grant_E_S_sig_not_empty_S_grant_E_S => err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S => err_not_grant_E_S_sig_or_empty_S_not_grant_E_S, err_grant_E_L_sig_not_empty_L_grant_E_L => err_grant_E_L_sig_not_empty_L_grant_E_L, err_not_grant_E_L_sig_or_empty_L_not_grant_E_L => err_not_grant_E_L_sig_or_empty_L_not_grant_E_L, err_grant_W_N_sig_not_empty_N_grant_W_N => err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N => err_not_grant_W_N_sig_or_empty_N_not_grant_W_N, err_grant_W_E_sig_not_empty_E_grant_W_E => err_grant_W_E_sig_not_empty_E_grant_W_E, err_not_grant_W_E_sig_or_empty_E_not_grant_W_E => err_not_grant_W_E_sig_or_empty_E_not_grant_W_E, err_grant_W_W_sig_not_empty_W_grant_W_W => err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W => err_not_grant_W_W_sig_or_empty_W_not_grant_W_W, err_grant_W_S_sig_not_empty_S_grant_W_S => err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S => err_not_grant_W_S_sig_or_empty_S_not_grant_W_S, err_grant_W_L_sig_not_empty_L_grant_W_L => err_grant_W_L_sig_not_empty_L_grant_W_L, err_not_grant_W_L_sig_or_empty_L_not_grant_W_L => err_not_grant_W_L_sig_or_empty_L_not_grant_W_L, err_grant_S_N_sig_not_empty_N_grant_S_N => err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N => err_not_grant_S_N_sig_or_empty_N_not_grant_S_N, err_grant_S_E_sig_not_empty_E_grant_S_E => err_grant_S_E_sig_not_empty_E_grant_S_E, err_not_grant_S_E_sig_or_empty_E_not_grant_S_E => err_not_grant_S_E_sig_or_empty_E_not_grant_S_E, err_grant_S_W_sig_not_empty_W_grant_S_W => err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W => err_not_grant_S_W_sig_or_empty_W_not_grant_S_W, err_grant_S_S_sig_not_empty_S_grant_S_S => err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S => err_not_grant_S_S_sig_or_empty_S_not_grant_S_S, err_grant_S_L_sig_not_empty_L_grant_S_L => err_grant_S_L_sig_not_empty_L_grant_S_L, err_not_grant_S_L_sig_or_empty_L_not_grant_S_L => err_not_grant_S_L_sig_or_empty_L_not_grant_S_L, err_grant_L_N_sig_not_empty_N_grant_L_N => err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N => err_not_grant_L_N_sig_or_empty_N_not_grant_L_N, err_grant_L_E_sig_not_empty_E_grant_L_E => err_grant_L_E_sig_not_empty_E_grant_L_E, err_not_grant_L_E_sig_or_empty_E_not_grant_L_E => err_not_grant_L_E_sig_or_empty_E_not_grant_L_E, err_grant_L_W_sig_not_empty_W_grant_L_W => err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W => err_not_grant_L_W_sig_or_empty_W_not_grant_L_W, err_grant_L_S_sig_not_empty_S_grant_L_S => err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S => err_not_grant_L_S_sig_or_empty_S_not_grant_L_S, err_grant_L_L_sig_not_empty_L_grant_L_L => err_grant_L_L_sig_not_empty_L_grant_L_L, err_not_grant_L_L_sig_or_empty_L_not_grant_L_L => err_not_grant_L_L_sig_or_empty_L_not_grant_L_L, err_grant_signals_not_empty_grant_N => err_grant_signals_not_empty_grant_N , err_not_grant_signals_empty_not_grant_N => err_not_grant_signals_empty_not_grant_N , err_grant_signals_not_empty_grant_E => err_grant_signals_not_empty_grant_E , err_not_grant_signals_empty_not_grant_E => err_not_grant_signals_empty_not_grant_E , err_grant_signals_not_empty_grant_W => err_grant_signals_not_empty_grant_W , err_not_grant_signals_empty_not_grant_W => err_not_grant_signals_empty_not_grant_W , err_grant_signals_not_empty_grant_S => err_grant_signals_not_empty_grant_S , err_not_grant_signals_empty_not_grant_S => err_not_grant_signals_empty_not_grant_S , err_grant_signals_not_empty_grant_L => err_grant_signals_not_empty_grant_L , err_not_grant_signals_empty_not_grant_L => err_not_grant_signals_empty_not_grant_L , err_grants_valid_not_match => err_grants_valid_not_match ); -- Allocator credit counter logic checkers module instantiation ALLOCATOR_CREDIT_COUNTER_LOGIC_CHECKERS: allocator_credit_counter_logic_pseudo_checkers PORT MAP ( credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L, credit_counter_N_out => credit_counter_N_out_faulty, credit_counter_E_out => credit_counter_E_out_faulty, credit_counter_W_out => credit_counter_W_out_faulty, credit_counter_S_out => credit_counter_S_out_faulty, credit_counter_L_out => credit_counter_L_out_faulty, valid_N => grant_N_faulty, -- Must be connected to grant signals! valid_E => grant_E_faulty, -- Must be connected to grant signals! valid_W => grant_W_faulty, -- Must be connected to grant signals! valid_S => grant_S_faulty, -- Must be connected to grant signals! valid_L => grant_L_faulty, -- Must be connected to grant signals! credit_counter_N_in => credit_counter_N_in_faulty, credit_counter_E_in => credit_counter_E_in_faulty, credit_counter_W_in => credit_counter_W_in_faulty, credit_counter_S_in => credit_counter_S_in_faulty, credit_counter_L_in => credit_counter_L_in_faulty, -- Checker Outputs err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_N_credit_counter_N_out_increment => err_credit_in_N_credit_counter_N_out_increment, err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change => err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change, err_grant_N_credit_counter_N_out_decrement => err_grant_N_credit_counter_N_out_decrement, err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change => err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change, err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_E_credit_counter_E_out_increment => err_credit_in_E_credit_counter_E_out_increment, err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change => err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change, err_grant_E_credit_counter_E_out_decrement => err_grant_E_credit_counter_E_out_decrement, err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change => err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change, err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_W_credit_counter_W_out_increment => err_credit_in_W_credit_counter_W_out_increment, err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change => err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change, err_grant_W_credit_counter_W_out_decrement => err_grant_W_credit_counter_W_out_decrement, err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change => err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change, err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_S_credit_counter_S_out_increment => err_credit_in_S_credit_counter_S_out_increment, err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change => err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change, err_grant_S_credit_counter_S_out_decrement => err_grant_S_credit_counter_S_out_decrement, err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change => err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change, err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal, err_credit_in_L_credit_counter_L_out_increment => err_credit_in_L_credit_counter_L_out_increment, err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change => err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change, err_grant_L_credit_counter_L_out_decrement => err_grant_L_credit_counter_L_out_decrement, err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change => err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change, err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal ); --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Arbiter In -- North Arbiter_in with checkers integrated (module instantiation) arb_N_X: Arbiter_in PORT MAP (reset => reset, clk => clk, Req_X_N=>req_N_N, Req_X_E=> req_N_E, Req_X_W=>req_N_W, Req_X_S=>req_N_S, Req_X_L=>req_N_L, X_N=>X_N_N, X_E=>X_N_E, X_W=>X_N_W, X_S=>X_N_S, X_L=>X_N_L, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_Arbiter_in_N_Arbiter_in, SO=> fault_DO_serial_N_Arbiter_in_E_Arbiter_in, -- North Arbiter_in Checker outputs err_Requests_state_in_state_not_equal => N_err_Requests_state_in_state_not_equal, err_IDLE_Req_N => N_err_IDLE_Req_N, err_IDLE_grant_N => N_err_IDLE_grant_N, err_North_Req_N => N_err_North_Req_N, err_North_grant_N => N_err_North_grant_N, err_East_Req_E => N_err_East_Req_E, err_East_grant_E => N_err_East_grant_E, err_West_Req_W => N_err_West_Req_W, err_West_grant_W => N_err_West_grant_W, err_South_Req_S => N_err_South_Req_S, err_South_grant_S => N_err_South_grant_S, err_Local_Req_L => N_err_Local_Req_L, err_Local_grant_L => N_err_Local_grant_L, err_IDLE_Req_E => N_err_IDLE_Req_E, err_IDLE_grant_E => N_err_IDLE_grant_E, err_North_Req_E => N_err_North_Req_E, err_North_grant_E => N_err_North_grant_E, err_East_Req_W => N_err_East_Req_W, err_East_grant_W => N_err_East_grant_W, err_West_Req_S => N_err_West_Req_S, err_West_grant_S => N_err_West_grant_S, err_South_Req_L => N_err_South_Req_L, err_South_grant_L => N_err_South_grant_L, err_Local_Req_N => N_err_Local_Req_N, err_Local_grant_N => N_err_Local_grant_N, err_IDLE_Req_W => N_err_IDLE_Req_W, err_IDLE_grant_W => N_err_IDLE_grant_W, err_North_Req_W => N_err_North_Req_W, err_North_grant_W => N_err_North_grant_W, err_East_Req_S => N_err_East_Req_S, err_East_grant_S => N_err_East_grant_S, err_West_Req_L => N_err_West_Req_L, err_West_grant_L => N_err_West_grant_L, err_South_Req_N => N_err_South_Req_N, err_South_grant_N => N_err_South_grant_N, err_Local_Req_E => N_err_Local_Req_E, err_Local_grant_E => N_err_Local_grant_E, err_IDLE_Req_S => N_err_IDLE_Req_S, err_IDLE_grant_S => N_err_IDLE_grant_S, err_North_Req_S => N_err_North_Req_S, err_North_grant_S => N_err_North_grant_S, err_East_Req_L => N_err_East_Req_L, err_East_grant_L => N_err_East_grant_L, err_West_Req_N => N_err_West_Req_N, err_West_grant_N => N_err_West_grant_N, err_South_Req_E => N_err_South_Req_E, err_South_grant_E => N_err_South_grant_E, err_Local_Req_W => N_err_Local_Req_W, err_Local_grant_W => N_err_Local_grant_W, err_IDLE_Req_L => N_err_IDLE_Req_L, err_IDLE_grant_L => N_err_IDLE_grant_L, err_North_Req_L => N_err_North_Req_L, err_North_grant_L => N_err_North_grant_L, err_East_Req_N => N_err_East_Req_N, err_East_grant_N => N_err_East_grant_N, err_West_Req_E => N_err_West_Req_E, err_West_grant_E => N_err_West_grant_E, err_South_Req_W => N_err_South_Req_W, err_South_grant_W => N_err_South_grant_W, err_Local_Req_S => N_err_Local_Req_S, err_Local_grant_S => N_err_Local_grant_S, err_state_in_onehot => N_err_state_in_onehot, err_no_request_grants => N_err_no_request_grants, err_request_no_grants => N_err_request_no_grants, err_no_Req_N_grant_N => N_err_no_Req_N_grant_N, err_no_Req_E_grant_E => N_err_no_Req_E_grant_E, err_no_Req_W_grant_W => N_err_no_Req_W_grant_W, err_no_Req_S_grant_S => N_err_no_Req_S_grant_S, err_no_Req_L_grant_L => N_err_no_Req_L_grant_L ); arb_E_X: Arbiter_in PORT MAP (reset => reset, clk => clk, Req_X_N=>req_E_N, Req_X_E=> req_E_E, Req_X_W=>req_E_W, Req_X_S=>req_E_S, Req_X_L=>req_E_L, X_N=>X_E_N, X_E=>X_E_E, X_W=>X_E_W, X_S=>X_E_S, X_L=>X_E_L, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_N_Arbiter_in_E_Arbiter_in, SO=> fault_DO_serial_E_Arbiter_in_W_Arbiter_in, -- East Arbiter_in Checker outputs err_Requests_state_in_state_not_equal => E_err_Requests_state_in_state_not_equal, err_IDLE_Req_N => E_err_IDLE_Req_N, err_IDLE_grant_N => E_err_IDLE_grant_N, err_North_Req_N => E_err_North_Req_N, err_North_grant_N => E_err_North_grant_N, err_East_Req_E => E_err_East_Req_E, err_East_grant_E => E_err_East_grant_E, err_West_Req_W => E_err_West_Req_W, err_West_grant_W => E_err_West_grant_W, err_South_Req_S => E_err_South_Req_S, err_South_grant_S => E_err_South_grant_S, err_Local_Req_L => E_err_Local_Req_L, err_Local_grant_L => E_err_Local_grant_L, err_IDLE_Req_E => E_err_IDLE_Req_E, err_IDLE_grant_E => E_err_IDLE_grant_E, err_North_Req_E => E_err_North_Req_E, err_North_grant_E => E_err_North_grant_E, err_East_Req_W => E_err_East_Req_W, err_East_grant_W => E_err_East_grant_W, err_West_Req_S => E_err_West_Req_S, err_West_grant_S => E_err_West_grant_S, err_South_Req_L => E_err_South_Req_L, err_South_grant_L => E_err_South_grant_L, err_Local_Req_N => E_err_Local_Req_N, err_Local_grant_N => E_err_Local_grant_N, err_IDLE_Req_W => E_err_IDLE_Req_W, err_IDLE_grant_W => E_err_IDLE_grant_W, err_North_Req_W => E_err_North_Req_W, err_North_grant_W => E_err_North_grant_W, err_East_Req_S => E_err_East_Req_S, err_East_grant_S => E_err_East_grant_S, err_West_Req_L => E_err_West_Req_L, err_West_grant_L => E_err_West_grant_L, err_South_Req_N => E_err_South_Req_N, err_South_grant_N => E_err_South_grant_N, err_Local_Req_E => E_err_Local_Req_E, err_Local_grant_E => E_err_Local_grant_E, err_IDLE_Req_S => E_err_IDLE_Req_S, err_IDLE_grant_S => E_err_IDLE_grant_S, err_North_Req_S => E_err_North_Req_S, err_North_grant_S => E_err_North_grant_S, err_East_Req_L => E_err_East_Req_L, err_East_grant_L => E_err_East_grant_L, err_West_Req_N => E_err_West_Req_N, err_West_grant_N => E_err_West_grant_N, err_South_Req_E => E_err_South_Req_E, err_South_grant_E => E_err_South_grant_E, err_Local_Req_W => E_err_Local_Req_W, err_Local_grant_W => E_err_Local_grant_W, err_IDLE_Req_L => E_err_IDLE_Req_L, err_IDLE_grant_L => E_err_IDLE_grant_L, err_North_Req_L => E_err_North_Req_L, err_North_grant_L => E_err_North_grant_L, err_East_Req_N => E_err_East_Req_N, err_East_grant_N => E_err_East_grant_N, err_West_Req_E => E_err_West_Req_E, err_West_grant_E => E_err_West_grant_E, err_South_Req_W => E_err_South_Req_W, err_South_grant_W => E_err_South_grant_W, err_Local_Req_S => E_err_Local_Req_S, err_Local_grant_S => E_err_Local_grant_S, err_state_in_onehot => E_err_state_in_onehot, err_no_request_grants => E_err_no_request_grants, err_request_no_grants => E_err_request_no_grants, err_no_Req_N_grant_N => E_err_no_Req_N_grant_N, err_no_Req_E_grant_E => E_err_no_Req_E_grant_E, err_no_Req_W_grant_W => E_err_no_Req_W_grant_W, err_no_Req_S_grant_S => E_err_no_Req_S_grant_S, err_no_Req_L_grant_L => E_err_no_Req_L_grant_L ); arb_W_X: Arbiter_in PORT MAP (reset => reset, clk => clk, Req_X_N=>req_W_N, Req_X_E=> req_W_E, Req_X_W=>req_W_W, Req_X_S=>req_W_S, Req_X_L=>req_W_L, X_N=>X_W_N, X_E=>X_W_E, X_W=>X_W_W, X_S=>X_W_S, X_L=>X_W_L, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_Arbiter_in_W_Arbiter_in, SO=> fault_DO_serial_W_Arbiter_in_S_Arbiter_in, -- West Arbiter_in Checker outputs err_Requests_state_in_state_not_equal => W_err_Requests_state_in_state_not_equal, err_IDLE_Req_N => W_err_IDLE_Req_N, err_IDLE_grant_N => W_err_IDLE_grant_N, err_North_Req_N => W_err_North_Req_N, err_North_grant_N => W_err_North_grant_N, err_East_Req_E => W_err_East_Req_E, err_East_grant_E => W_err_East_grant_E, err_West_Req_W => W_err_West_Req_W, err_West_grant_W => W_err_West_grant_W, err_South_Req_S => W_err_South_Req_S, err_South_grant_S => W_err_South_grant_S, err_Local_Req_L => W_err_Local_Req_L, err_Local_grant_L => W_err_Local_grant_L, err_IDLE_Req_E => W_err_IDLE_Req_E, err_IDLE_grant_E => W_err_IDLE_grant_E, err_North_Req_E => W_err_North_Req_E, err_North_grant_E => W_err_North_grant_E, err_East_Req_W => W_err_East_Req_W, err_East_grant_W => W_err_East_grant_W, err_West_Req_S => W_err_West_Req_S, err_West_grant_S => W_err_West_grant_S, err_South_Req_L => W_err_South_Req_L, err_South_grant_L => W_err_South_grant_L, err_Local_Req_N => W_err_Local_Req_N, err_Local_grant_N => W_err_Local_grant_N, err_IDLE_Req_W => W_err_IDLE_Req_W, err_IDLE_grant_W => W_err_IDLE_grant_W, err_North_Req_W => W_err_North_Req_W, err_North_grant_W => W_err_North_grant_W, err_East_Req_S => W_err_East_Req_S, err_East_grant_S => W_err_East_grant_S, err_West_Req_L => W_err_West_Req_L, err_West_grant_L => W_err_West_grant_L, err_South_Req_N => W_err_South_Req_N, err_South_grant_N => W_err_South_grant_N, err_Local_Req_E => W_err_Local_Req_E, err_Local_grant_E => W_err_Local_grant_E, err_IDLE_Req_S => W_err_IDLE_Req_S, err_IDLE_grant_S => W_err_IDLE_grant_S, err_North_Req_S => W_err_North_Req_S, err_North_grant_S => W_err_North_grant_S, err_East_Req_L => W_err_East_Req_L, err_East_grant_L => W_err_East_grant_L, err_West_Req_N => W_err_West_Req_N, err_West_grant_N => W_err_West_grant_N, err_South_Req_E => W_err_South_Req_E, err_South_grant_E => W_err_South_grant_E, err_Local_Req_W => W_err_Local_Req_W, err_Local_grant_W => W_err_Local_grant_W, err_IDLE_Req_L => W_err_IDLE_Req_L, err_IDLE_grant_L => W_err_IDLE_grant_L, err_North_Req_L => W_err_North_Req_L, err_North_grant_L => W_err_North_grant_L, err_East_Req_N => W_err_East_Req_N, err_East_grant_N => W_err_East_grant_N, err_West_Req_E => W_err_West_Req_E, err_West_grant_E => W_err_West_grant_E, err_South_Req_W => W_err_South_Req_W, err_South_grant_W => W_err_South_grant_W, err_Local_Req_S => W_err_Local_Req_S, err_Local_grant_S => W_err_Local_grant_S, err_state_in_onehot => W_err_state_in_onehot, err_no_request_grants => W_err_no_request_grants, err_request_no_grants => W_err_request_no_grants, err_no_Req_N_grant_N => W_err_no_Req_N_grant_N, err_no_Req_E_grant_E => W_err_no_Req_E_grant_E, err_no_Req_W_grant_W => W_err_no_Req_W_grant_W, err_no_Req_S_grant_S => W_err_no_Req_S_grant_S, err_no_Req_L_grant_L => W_err_no_Req_L_grant_L ); arb_S_X: Arbiter_in PORT MAP (reset => reset, clk => clk, Req_X_N=>req_S_N, Req_X_E=> req_S_E, Req_X_W=>req_S_W, Req_X_S=>req_S_S, Req_X_L=>req_S_L, X_N=>X_S_N, X_E=>X_S_E, X_W=>X_S_W, X_S=>X_S_S, X_L=>X_S_L, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_Arbiter_in_S_Arbiter_in, SO=> fault_DO_serial_S_Arbiter_in_L_Arbiter_out, -- South Arbiter_in Checker outputs err_Requests_state_in_state_not_equal => S_err_Requests_state_in_state_not_equal, err_IDLE_Req_N => S_err_IDLE_Req_N, err_IDLE_grant_N => S_err_IDLE_grant_N, err_North_Req_N => S_err_North_Req_N, err_North_grant_N => S_err_North_grant_N, err_East_Req_E => S_err_East_Req_E, err_East_grant_E => S_err_East_grant_E, err_West_Req_W => S_err_West_Req_W, err_West_grant_W => S_err_West_grant_W, err_South_Req_S => S_err_South_Req_S, err_South_grant_S => S_err_South_grant_S, err_Local_Req_L => S_err_Local_Req_L, err_Local_grant_L => S_err_Local_grant_L, err_IDLE_Req_E => S_err_IDLE_Req_E, err_IDLE_grant_E => S_err_IDLE_grant_E, err_North_Req_E => S_err_North_Req_E, err_North_grant_E => S_err_North_grant_E, err_East_Req_W => S_err_East_Req_W, err_East_grant_W => S_err_East_grant_W, err_West_Req_S => S_err_West_Req_S, err_West_grant_S => S_err_West_grant_S, err_South_Req_L => S_err_South_Req_L, err_South_grant_L => S_err_South_grant_L, err_Local_Req_N => S_err_Local_Req_N, err_Local_grant_N => S_err_Local_grant_N, err_IDLE_Req_W => S_err_IDLE_Req_W, err_IDLE_grant_W => S_err_IDLE_grant_W, err_North_Req_W => S_err_North_Req_W, err_North_grant_W => S_err_North_grant_W, err_East_Req_S => S_err_East_Req_S, err_East_grant_S => S_err_East_grant_S, err_West_Req_L => S_err_West_Req_L, err_West_grant_L => S_err_West_grant_L, err_South_Req_N => S_err_South_Req_N, err_South_grant_N => S_err_South_grant_N, err_Local_Req_E => S_err_Local_Req_E, err_Local_grant_E => S_err_Local_grant_E, err_IDLE_Req_S => S_err_IDLE_Req_S, err_IDLE_grant_S => S_err_IDLE_grant_S, err_North_Req_S => S_err_North_Req_S, err_North_grant_S => S_err_North_grant_S, err_East_Req_L => S_err_East_Req_L, err_East_grant_L => S_err_East_grant_L, err_West_Req_N => S_err_West_Req_N, err_West_grant_N => S_err_West_grant_N, err_South_Req_E => S_err_South_Req_E, err_South_grant_E => S_err_South_grant_E, err_Local_Req_W => S_err_Local_Req_W, err_Local_grant_W => S_err_Local_grant_W, err_IDLE_Req_L => S_err_IDLE_Req_L, err_IDLE_grant_L => S_err_IDLE_grant_L, err_North_Req_L => S_err_North_Req_L, err_North_grant_L => S_err_North_grant_L, err_East_Req_N => S_err_East_Req_N, err_East_grant_N => S_err_East_grant_N, err_West_Req_E => S_err_West_Req_E, err_West_grant_E => S_err_West_grant_E, err_South_Req_W => S_err_South_Req_W, err_South_grant_W => S_err_South_grant_W, err_Local_Req_S => S_err_Local_Req_S, err_Local_grant_S => S_err_Local_grant_S, err_state_in_onehot => S_err_state_in_onehot, err_no_request_grants => S_err_no_request_grants, err_request_no_grants => S_err_request_no_grants, err_no_Req_N_grant_N => S_err_no_Req_N_grant_N, err_no_Req_E_grant_E => S_err_no_Req_E_grant_E, err_no_Req_W_grant_W => S_err_no_Req_W_grant_W, err_no_Req_S_grant_S => S_err_no_Req_S_grant_S, err_no_Req_L_grant_L => S_err_no_Req_L_grant_L ); arb_L_X: Arbiter_in PORT MAP (reset => reset, clk => clk, Req_X_N=>req_L_N, Req_X_E=> req_L_E, Req_X_W=>req_L_W, Req_X_S=>req_L_S, Req_X_L=>req_L_L, X_N=>X_L_N, X_E=>X_L_E, X_W=>X_L_W, X_S=>X_L_S, X_L=>X_L_L, TCK=> TCK, SE=> SE, UE=> UE, SI=> SI, SO=> fault_DO_serial_L_Arbiter_in_N_Arbiter_in, -- Local Arbiter_in Checker outputs err_Requests_state_in_state_not_equal => L_err_Requests_state_in_state_not_equal, err_IDLE_Req_N => L_err_IDLE_Req_N, err_IDLE_grant_N => L_err_IDLE_grant_N, err_North_Req_N => L_err_North_Req_N, err_North_grant_N => L_err_North_grant_N, err_East_Req_E => L_err_East_Req_E, err_East_grant_E => L_err_East_grant_E, err_West_Req_W => L_err_West_Req_W, err_West_grant_W => L_err_West_grant_W, err_South_Req_S => L_err_South_Req_S, err_South_grant_S => L_err_South_grant_S, err_Local_Req_L => L_err_Local_Req_L, err_Local_grant_L => L_err_Local_grant_L, err_IDLE_Req_E => L_err_IDLE_Req_E, err_IDLE_grant_E => L_err_IDLE_grant_E, err_North_Req_E => L_err_North_Req_E, err_North_grant_E => L_err_North_grant_E, err_East_Req_W => L_err_East_Req_W, err_East_grant_W => L_err_East_grant_W, err_West_Req_S => L_err_West_Req_S, err_West_grant_S => L_err_West_grant_S, err_South_Req_L => L_err_South_Req_L, err_South_grant_L => L_err_South_grant_L, err_Local_Req_N => L_err_Local_Req_N, err_Local_grant_N => L_err_Local_grant_N, err_IDLE_Req_W => L_err_IDLE_Req_W, err_IDLE_grant_W => L_err_IDLE_grant_W, err_North_Req_W => L_err_North_Req_W, err_North_grant_W => L_err_North_grant_W, err_East_Req_S => L_err_East_Req_S, err_East_grant_S => L_err_East_grant_S, err_West_Req_L => L_err_West_Req_L, err_West_grant_L => L_err_West_grant_L, err_South_Req_N => L_err_South_Req_N, err_South_grant_N => L_err_South_grant_N, err_Local_Req_E => L_err_Local_Req_E, err_Local_grant_E => L_err_Local_grant_E, err_IDLE_Req_S => L_err_IDLE_Req_S, err_IDLE_grant_S => L_err_IDLE_grant_S, err_North_Req_S => L_err_North_Req_S, err_North_grant_S => L_err_North_grant_S, err_East_Req_L => L_err_East_Req_L, err_East_grant_L => L_err_East_grant_L, err_West_Req_N => L_err_West_Req_N, err_West_grant_N => L_err_West_grant_N, err_South_Req_E => L_err_South_Req_E, err_South_grant_E => L_err_South_grant_E, err_Local_Req_W => L_err_Local_Req_W, err_Local_grant_W => L_err_Local_grant_W, err_IDLE_Req_L => L_err_IDLE_Req_L, err_IDLE_grant_L => L_err_IDLE_grant_L, err_North_Req_L => L_err_North_Req_L, err_North_grant_L => L_err_North_grant_L, err_East_Req_N => L_err_East_Req_N, err_East_grant_N => L_err_East_grant_N, err_West_Req_E => L_err_West_Req_E, err_West_grant_E => L_err_West_grant_E, err_South_Req_W => L_err_South_Req_W, err_South_grant_W => L_err_South_grant_W, err_Local_Req_S => L_err_Local_Req_S, err_Local_grant_S => L_err_Local_grant_S, err_state_in_onehot => L_err_state_in_onehot, err_no_request_grants => L_err_no_request_grants, err_request_no_grants => L_err_request_no_grants, err_no_Req_N_grant_N => L_err_no_Req_N_grant_N, err_no_Req_E_grant_E => L_err_no_Req_E_grant_E, err_no_Req_W_grant_W => L_err_no_Req_W_grant_W, err_no_Req_S_grant_S => L_err_no_Req_S_grant_S, err_no_Req_L_grant_L => L_err_no_Req_L_grant_L ); --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Arbiter Out mobuldes instantiation(s) -- Y is N now -- North Arbiter_out with checkers integrated arb_X_N: arbiter_out port map (reset => reset, clk => clk, X_N_Y => X_N_N, X_E_Y => X_E_N, X_W_Y => X_W_N, X_S_Y => X_S_N, X_L_Y => X_L_N, credit => credit_counter_N_out, grant_Y_N => grant_N_N_sig, grant_Y_E => grant_N_E_sig, grant_Y_W => grant_N_W_sig, grant_Y_S => grant_N_S_sig, grant_Y_L => grant_N_L_sig, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_Arbiter_out_N_Arbiter_out, SO=> fault_DO_serial_N_Arbiter_out_E_Arbiter_out, -- Checker outputs err_Requests_state_in_state_not_equal => N_arbiter_out_err_Requests_state_in_state_not_equal, err_IDLE_req_X_N => N_err_IDLE_req_X_N, err_North_req_X_N => N_err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N => N_err_North_credit_not_zero_req_X_N_grant_N, err_North_credit_zero_or_not_req_X_N_not_grant_N => N_err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E => N_err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E => N_err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E => N_err_East_credit_zero_or_not_req_X_E_not_grant_E, err_West_req_X_W => N_err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W => N_err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W => N_err_West_credit_zero_or_not_req_X_W_not_grant_W, err_South_req_X_S => N_err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S => N_err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S => N_err_South_credit_zero_or_not_req_X_S_not_grant_S, err_Local_req_X_L => N_err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L => N_err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L => N_err_Local_credit_zero_or_not_req_X_L_not_grant_L, err_IDLE_req_X_E => N_err_IDLE_req_X_E, err_North_req_X_E => N_err_North_req_X_E, err_East_req_X_W => N_err_East_req_X_W, err_West_req_X_S => N_err_West_req_X_S, err_South_req_X_L => N_err_South_req_X_L, err_Local_req_X_N => N_err_Local_req_X_N, err_IDLE_req_X_W => N_err_IDLE_req_X_W, err_North_req_X_W => N_err_North_req_X_W, err_East_req_X_S => N_err_East_req_X_S, err_West_req_X_L => N_err_West_req_X_L, err_South_req_X_N => N_err_South_req_X_N, err_Local_req_X_E => N_err_Local_req_X_E, err_IDLE_req_X_S => N_err_IDLE_req_X_S, err_North_req_X_S => N_err_North_req_X_S, err_East_req_X_L => N_err_East_req_X_L, err_West_req_X_N => N_err_West_req_X_N, err_South_req_X_E => N_err_South_req_X_E, err_Local_req_X_W => N_err_Local_req_X_W, err_IDLE_req_X_L => N_err_IDLE_req_X_L, err_North_req_X_L => N_err_North_req_X_L, err_East_req_X_N => N_err_East_req_X_N, err_West_req_X_E => N_err_West_req_X_E, err_South_req_X_W => N_err_South_req_X_W, err_Local_req_X_S => N_err_Local_req_X_S, err_state_in_onehot => N_arbiter_out_err_state_in_onehot, err_no_request_grants => N_arbiter_out_err_no_request_grants, err_request_IDLE_state => N_err_request_IDLE_state, err_request_IDLE_not_Grants => N_err_request_IDLE_not_Grants, err_state_North_Invalid_Grant => N_err_state_North_Invalid_Grant, err_state_East_Invalid_Grant => N_err_state_East_Invalid_Grant, err_state_West_Invalid_Grant => N_err_state_West_Invalid_Grant, err_state_South_Invalid_Grant => N_err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant => N_err_state_Local_Invalid_Grant, err_Grants_onehot_or_all_zero => N_err_Grants_onehot_or_all_zero ); -- Y is E now -- East Arbiter_out with checkers integrated arb_X_E: arbiter_out port map (reset => reset, clk => clk, X_N_Y => X_N_E, X_E_Y => X_E_E, X_W_Y => X_W_E, X_S_Y => X_S_E, X_L_Y => X_L_E, credit => credit_counter_E_out, grant_Y_N => grant_E_N_sig, grant_Y_E => grant_E_E_sig, grant_Y_W => grant_E_W_sig, grant_Y_S => grant_E_S_sig, grant_Y_L => grant_E_L_sig, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_N_Arbiter_out_E_Arbiter_out, SO=> fault_DO_serial_E_Arbiter_out_W_Arbiter_out, -- Checker outputs err_Requests_state_in_state_not_equal => E_arbiter_out_err_Requests_state_in_state_not_equal, err_IDLE_req_X_N => E_err_IDLE_req_X_N, err_North_req_X_N => E_err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N => E_err_North_credit_not_zero_req_X_N_grant_N, err_North_credit_zero_or_not_req_X_N_not_grant_N => E_err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E => E_err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E => E_err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E => E_err_East_credit_zero_or_not_req_X_E_not_grant_E, err_West_req_X_W => E_err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W => E_err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W => E_err_West_credit_zero_or_not_req_X_W_not_grant_W, err_South_req_X_S => E_err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S => E_err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S => E_err_South_credit_zero_or_not_req_X_S_not_grant_S, err_Local_req_X_L => E_err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L => E_err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L => E_err_Local_credit_zero_or_not_req_X_L_not_grant_L, err_IDLE_req_X_E => E_err_IDLE_req_X_E, err_North_req_X_E => E_err_North_req_X_E, err_East_req_X_W => E_err_East_req_X_W, err_West_req_X_S => E_err_West_req_X_S, err_South_req_X_L => E_err_South_req_X_L, err_Local_req_X_N => E_err_Local_req_X_N, err_IDLE_req_X_W => E_err_IDLE_req_X_W, err_North_req_X_W => E_err_North_req_X_W, err_East_req_X_S => E_err_East_req_X_S, err_West_req_X_L => E_err_West_req_X_L, err_South_req_X_N => E_err_South_req_X_N, err_Local_req_X_E => E_err_Local_req_X_E, err_IDLE_req_X_S => E_err_IDLE_req_X_S, err_North_req_X_S => E_err_North_req_X_S, err_East_req_X_L => E_err_East_req_X_L, err_West_req_X_N => E_err_West_req_X_N, err_South_req_X_E => E_err_South_req_X_E, err_Local_req_X_W => E_err_Local_req_X_W, err_IDLE_req_X_L => E_err_IDLE_req_X_L, err_North_req_X_L => E_err_North_req_X_L, err_East_req_X_N => E_err_East_req_X_N, err_West_req_X_E => E_err_West_req_X_E, err_South_req_X_W => E_err_South_req_X_W, err_Local_req_X_S => E_err_Local_req_X_S, err_state_in_onehot => E_arbiter_out_err_state_in_onehot, err_no_request_grants => E_arbiter_out_err_no_request_grants, err_request_IDLE_state => E_err_request_IDLE_state, err_request_IDLE_not_Grants => E_err_request_IDLE_not_Grants, err_state_North_Invalid_Grant => E_err_state_North_Invalid_Grant, err_state_East_Invalid_Grant => E_err_state_East_Invalid_Grant, err_state_West_Invalid_Grant => E_err_state_West_Invalid_Grant, err_state_South_Invalid_Grant => E_err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant => E_err_state_Local_Invalid_Grant, err_Grants_onehot_or_all_zero => E_err_Grants_onehot_or_all_zero ); -- Y is W now -- West Arbiter_out with checkers integrated arb_X_W: arbiter_out port map (reset => reset, clk => clk, X_N_Y => X_N_W, X_E_Y => X_E_W, X_W_Y => X_W_W, X_S_Y => X_S_W, X_L_Y => X_L_W, credit => credit_counter_W_out, grant_Y_N => grant_W_N_sig, grant_Y_E => grant_W_E_sig, grant_Y_W => grant_W_W_sig, grant_Y_S => grant_W_S_sig, grant_Y_L => grant_W_L_sig, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_Arbiter_out_W_Arbiter_out, SO=> fault_DO_serial_W_Arbiter_out_S_Arbiter_out, -- Checker outputs err_Requests_state_in_state_not_equal => W_arbiter_out_err_Requests_state_in_state_not_equal, err_IDLE_req_X_N => W_err_IDLE_req_X_N, err_North_req_X_N => W_err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N => W_err_North_credit_not_zero_req_X_N_grant_N, err_North_credit_zero_or_not_req_X_N_not_grant_N => W_err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E => W_err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E => W_err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E => W_err_East_credit_zero_or_not_req_X_E_not_grant_E, err_West_req_X_W => W_err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W => W_err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W => W_err_West_credit_zero_or_not_req_X_W_not_grant_W, err_South_req_X_S => W_err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S => W_err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S => W_err_South_credit_zero_or_not_req_X_S_not_grant_S, err_Local_req_X_L => W_err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L => W_err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L => W_err_Local_credit_zero_or_not_req_X_L_not_grant_L, err_IDLE_req_X_E => W_err_IDLE_req_X_E, err_North_req_X_E => W_err_North_req_X_E, err_East_req_X_W => W_err_East_req_X_W, err_West_req_X_S => W_err_West_req_X_S, err_South_req_X_L => W_err_South_req_X_L, err_Local_req_X_N => W_err_Local_req_X_N, err_IDLE_req_X_W => W_err_IDLE_req_X_W, err_North_req_X_W => W_err_North_req_X_W, err_East_req_X_S => W_err_East_req_X_S, err_West_req_X_L => W_err_West_req_X_L, err_South_req_X_N => W_err_South_req_X_N, err_Local_req_X_E => W_err_Local_req_X_E, err_IDLE_req_X_S => W_err_IDLE_req_X_S, err_North_req_X_S => W_err_North_req_X_S, err_East_req_X_L => W_err_East_req_X_L, err_West_req_X_N => W_err_West_req_X_N, err_South_req_X_E => W_err_South_req_X_E, err_Local_req_X_W => W_err_Local_req_X_W, err_IDLE_req_X_L => W_err_IDLE_req_X_L, err_North_req_X_L => W_err_North_req_X_L, err_East_req_X_N => W_err_East_req_X_N, err_West_req_X_E => W_err_West_req_X_E, err_South_req_X_W => W_err_South_req_X_W, err_Local_req_X_S => W_err_Local_req_X_S, err_state_in_onehot => W_arbiter_out_err_state_in_onehot, err_no_request_grants => W_arbiter_out_err_no_request_grants, err_request_IDLE_state => W_err_request_IDLE_state, err_request_IDLE_not_Grants => W_err_request_IDLE_not_Grants, err_state_North_Invalid_Grant => W_err_state_North_Invalid_Grant, err_state_East_Invalid_Grant => W_err_state_East_Invalid_Grant, err_state_West_Invalid_Grant => W_err_state_West_Invalid_Grant, err_state_South_Invalid_Grant => W_err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant => W_err_state_Local_Invalid_Grant, err_Grants_onehot_or_all_zero => W_err_Grants_onehot_or_all_zero ); -- Y is S now -- South Arbiter_out with checkers integrated arb_X_S: arbiter_out port map (reset => reset, clk => clk, X_N_Y => X_N_S, X_E_Y => X_E_S, X_W_Y => X_W_S, X_S_Y => X_S_S, X_L_Y => X_L_S, credit => credit_counter_S_out, grant_Y_N => grant_S_N_sig, grant_Y_E => grant_S_E_sig, grant_Y_W => grant_S_W_sig, grant_Y_S => grant_S_S_sig, grant_Y_L => grant_S_L_sig, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_Arbiter_out_S_Arbiter_out, SO=> fault_DO_serial_S_Arbiter_out_Allocator_logic, -- Checker outputs err_Requests_state_in_state_not_equal => S_arbiter_out_err_Requests_state_in_state_not_equal, err_IDLE_req_X_N => S_err_IDLE_req_X_N, err_North_req_X_N => S_err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N => S_err_North_credit_not_zero_req_X_N_grant_N, err_North_credit_zero_or_not_req_X_N_not_grant_N => S_err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E => S_err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E => S_err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E => S_err_East_credit_zero_or_not_req_X_E_not_grant_E, err_West_req_X_W => S_err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W => S_err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W => S_err_West_credit_zero_or_not_req_X_W_not_grant_W, err_South_req_X_S => S_err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S => S_err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S => S_err_South_credit_zero_or_not_req_X_S_not_grant_S, err_Local_req_X_L => S_err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L => S_err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L => S_err_Local_credit_zero_or_not_req_X_L_not_grant_L, err_IDLE_req_X_E => S_err_IDLE_req_X_E, err_North_req_X_E => S_err_North_req_X_E, err_East_req_X_W => S_err_East_req_X_W, err_West_req_X_S => S_err_West_req_X_S, err_South_req_X_L => S_err_South_req_X_L, err_Local_req_X_N => S_err_Local_req_X_N, err_IDLE_req_X_W => S_err_IDLE_req_X_W, err_North_req_X_W => S_err_North_req_X_W, err_East_req_X_S => S_err_East_req_X_S, err_West_req_X_L => S_err_West_req_X_L, err_South_req_X_N => S_err_South_req_X_N, err_Local_req_X_E => S_err_Local_req_X_E, err_IDLE_req_X_S => S_err_IDLE_req_X_S, err_North_req_X_S => S_err_North_req_X_S, err_East_req_X_L => S_err_East_req_X_L, err_West_req_X_N => S_err_West_req_X_N, err_South_req_X_E => S_err_South_req_X_E, err_Local_req_X_W => S_err_Local_req_X_W, err_IDLE_req_X_L => S_err_IDLE_req_X_L, err_North_req_X_L => S_err_North_req_X_L, err_East_req_X_N => S_err_East_req_X_N, err_West_req_X_E => S_err_West_req_X_E, err_South_req_X_W => S_err_South_req_X_W, err_Local_req_X_S => S_err_Local_req_X_S, err_state_in_onehot => S_arbiter_out_err_state_in_onehot, err_no_request_grants => S_arbiter_out_err_no_request_grants, err_request_IDLE_state => S_err_request_IDLE_state, err_request_IDLE_not_Grants => S_err_request_IDLE_not_Grants, err_state_North_Invalid_Grant => S_err_state_North_Invalid_Grant, err_state_East_Invalid_Grant => S_err_state_East_Invalid_Grant, err_state_West_Invalid_Grant => S_err_state_West_Invalid_Grant, err_state_South_Invalid_Grant => S_err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant => S_err_state_Local_Invalid_Grant, err_Grants_onehot_or_all_zero => S_err_Grants_onehot_or_all_zero ); -- Y is L now -- Local Arbiter_out with checkers integrated arb_X_L: arbiter_out port map (reset => reset, clk => clk, X_N_Y => X_N_L, X_E_Y => X_E_L, X_W_Y => X_W_L, X_S_Y => X_S_L, X_L_Y => X_L_L, credit => credit_counter_L_out, grant_Y_N => grant_L_N_sig, grant_Y_E => grant_L_E_sig, grant_Y_W => grant_L_W_sig, grant_Y_S => grant_L_S_sig, grant_Y_L => grant_L_L_sig, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_Arbiter_in_L_Arbiter_out, SO=> fault_DO_serial_L_Arbiter_out_N_Arbiter_out, -- Checker outputs err_Requests_state_in_state_not_equal => L_arbiter_out_err_Requests_state_in_state_not_equal, err_IDLE_req_X_N => L_err_IDLE_req_X_N, err_North_req_X_N => L_err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N => L_err_North_credit_not_zero_req_X_N_grant_N, err_North_credit_zero_or_not_req_X_N_not_grant_N => L_err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E => L_err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E => L_err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E => L_err_East_credit_zero_or_not_req_X_E_not_grant_E, err_West_req_X_W => L_err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W => L_err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W => L_err_West_credit_zero_or_not_req_X_W_not_grant_W, err_South_req_X_S => L_err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S => L_err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S => L_err_South_credit_zero_or_not_req_X_S_not_grant_S, err_Local_req_X_L => L_err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L => L_err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L => L_err_Local_credit_zero_or_not_req_X_L_not_grant_L, err_IDLE_req_X_E => L_err_IDLE_req_X_E, err_North_req_X_E => L_err_North_req_X_E, err_East_req_X_W => L_err_East_req_X_W, err_West_req_X_S => L_err_West_req_X_S, err_South_req_X_L => L_err_South_req_X_L, err_Local_req_X_N => L_err_Local_req_X_N, err_IDLE_req_X_W => L_err_IDLE_req_X_W, err_North_req_X_W => L_err_North_req_X_W, err_East_req_X_S => L_err_East_req_X_S, err_West_req_X_L => L_err_West_req_X_L, err_South_req_X_N => L_err_South_req_X_N, err_Local_req_X_E => L_err_Local_req_X_E, err_IDLE_req_X_S => L_err_IDLE_req_X_S, err_North_req_X_S => L_err_North_req_X_S, err_East_req_X_L => L_err_East_req_X_L, err_West_req_X_N => L_err_West_req_X_N, err_South_req_X_E => L_err_South_req_X_E, err_Local_req_X_W => L_err_Local_req_X_W, err_IDLE_req_X_L => L_err_IDLE_req_X_L, err_North_req_X_L => L_err_North_req_X_L, err_East_req_X_N => L_err_East_req_X_N, err_West_req_X_E => L_err_West_req_X_E, err_South_req_X_W => L_err_South_req_X_W, err_Local_req_X_S => L_err_Local_req_X_S, err_state_in_onehot => L_arbiter_out_err_state_in_onehot, err_no_request_grants => L_arbiter_out_err_no_request_grants, err_request_IDLE_state => L_err_request_IDLE_state, err_request_IDLE_not_Grants => L_err_request_IDLE_not_Grants, err_state_North_Invalid_Grant => L_err_state_North_Invalid_Grant, err_state_East_Invalid_Grant => L_err_state_East_Invalid_Grant, err_state_West_Invalid_Grant => L_err_state_West_Invalid_Grant, err_state_South_Invalid_Grant => L_err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant => L_err_state_Local_Invalid_Grant, err_Grants_onehot_or_all_zero => L_err_Grants_onehot_or_all_zero ); --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- valid_N_sig <= grant_N; valid_E_sig <= grant_E; valid_W_sig <= grant_W; valid_S_sig <= grant_S; valid_L_sig <= grant_L; END;
gpl-3.0
39661258a98b2157e4a66448ca579495
0.614719
2.441636
false
false
false
false
Wynjones1/gbvhdl
synth/clock_gen.vhd
4
1,024
library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; entity clk_gen is generic( CLOCK_SPEED : integer := 50_000_000; REQUIRED_HZ : integer := 1); port( clk : in std_logic; reset : in std_logic; clk_out : out std_logic); end; architecture rtl of clk_gen is constant COUNT_MAX : integer := CLOCK_SPEED / (REQUIRED_HZ * 2); signal count : integer range 0 to COUNT_MAX - 1 := 0; signal clk_s : std_logic; begin process(clk, reset) begin if reset = '1' then count <= 0; clk_s <= '0'; elsif rising_edge(clk) then if count = COUNT_MAX - 1 then count <= 0; if clk_s = '1' then clk_s <= '0'; else clk_s <= '1'; end if; else count <= count + 1; end if; end if; end process; clk_out <= clk_s; end architecture;
mit
03d6be52b7806b138ff155b61971f416
0.466797
3.792593
false
false
false
false
AndyMcC0/UVVM_All
bitvis_uart/src/uart_pif.vhd
3
3,359
--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <[email protected]>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.uart_pif_pkg.all; entity uart_pif is port( arst : in std_logic; clk : in std_logic; -- CPU interface cs : in std_logic; addr : in unsigned; wr : in std_logic; rd : in std_logic; wdata : in std_logic_vector(7 downto 0); rdata : out std_logic_vector(7 downto 0) := (others => '0'); -- p2c : out t_p2c; c2p : in t_c2p ); end uart_pif; architecture rtl of uart_pif is signal p2c_i : t_p2c; -- internal version of output signal rdata_i : std_logic_vector(7 downto 0) := (others => '0'); begin -- Assigning internally used signals to outputs p2c <= p2c_i; -- -- Auxiliary Register Control. -- -- Provides read/write/trigger strobes and write data to auxiliary -- registers and fields, i.e., registers and fields implemented in core. -- p_aux : process (wdata, addr, cs, wr, rd) begin -- Defaults p2c_i.awo_tx_data <= (others => '0'); p2c_i.awo_tx_data_we <= '0'; p2c_i.aro_rx_data_re <= '0'; -- Write decoding if wr = '1' and cs = '1' then case to_integer(addr) is when C_ADDR_TX_DATA => p2c_i.awo_tx_data <= wdata; p2c_i.awo_tx_data_we <= '1'; when others => null; end case; end if; -- Read Enable Decoding if rd = '1' and cs = '1' then case to_integer(addr) is when C_ADDR_RX_DATA => p2c_i.aro_rx_data_re <= '1'; when others => null; end case; end if; end process p_aux; p_read_reg : process(cs, addr, rd, c2p, p2c_i) begin -- default values rdata_i <= (others => '0'); if cs = '1' and rd = '1' then case to_integer(addr) is when C_ADDR_RX_DATA => rdata_i(7 downto 0) <= c2p.aro_rx_data; when C_ADDR_RX_DATA_VALID => rdata_i(0) <= c2p.aro_rx_data_valid; when C_ADDR_TX_READY => rdata_i(0) <= c2p.aro_tx_ready; when others => null; end case; end if; end process p_read_reg; rdata <= rdata_i; end rtl;
mit
e49b81acda00edee4d3c5d0e9abda71b
0.523072
3.659041
false
false
false
false
SKravitsky/ECEC412
RegistersMulticycle.vhd
1
1,852
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity RegistersMulticycle is port( RR1, RR2, WR: in std_logic_vector(4 downto 0); WD: in std_logic_vector(31 downto 0); RegWrite: in std_logic; RD1, RD2: out std_logic_vector(31 downto 0) ); end RegistersMulticycle; Architecture Structural of RegistersMulticycle is type mem_array is array(0 to 31) of std_logic_vector(31 downto 0); signal reg_mem: mem_array := ( X"00000000", --0 $zero (constant value 0) X"00000000", -- $at (reserved for the assembler) X"00000000", -- $v0 (value for results and expression) X"00000000", -- $v1 X"00000000", -- $a0 (arguments) X"00000000", --5 $a1 X"00000000", -- $a2 X"00000000", -- $a3 X"00000000", -- $t0 (temporaries) X"00000000", -- $t1 X"00000000", --10 $t2 X"00000000", -- $t3 X"00000000", -- $t4 X"00000000", -- $t5 X"00000000", -- $t6 X"00000000", --15 $t7 X"00000000", -- $s0 (saved) X"00000000", -- $s1 X"00000000", -- $s2 X"00000000", -- $s3 X"0000000E", --20 $s4 X"00000005", -- $s5 X"00000000", -- $s6 X"00000000", -- $s7 X"00000000", -- $t8 (more temporaries) X"00000000", --25 $t9 X"00000000", -- $k0 (reserved for the operating system) X"00000000", -- $k1 X"00000000", -- $gp (global pointer) X"00000000", -- $sp (stack pointer) X"00000000", --30 $fp (frame pointer) X"00000000" -- $ra (return address) ); signal temp_data: std_logic_vector(31 downto 0) := X"00000000"; begin RD1 <= reg_mem(to_integer(unsigned(RR1))); RD2 <= reg_mem(to_integer(unsigned(RR2))); process(WD, WR, RegWrite) begin if RegWrite = '1' then reg_mem(to_integer(unsigned(WR))) <= WD; end if; end process; end Structural;
apache-2.0
b3607a8366f1841c7407ac04455398e2
0.584233
2.9632
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/NoC_Node.vhd
3
9,521
--------------------------------------------------------------------- -- TITLE: NoC_Node -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 4/21/01 -- ORIGNAL FILENAME: tbench.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- This entity provides a simple NoC node with plasma as its processor --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; use ieee.std_logic_unsigned.all; entity NoC_Node is generic(current_address : integer := 0; stim_file: string :="code.txt"; log_file : string := "output.txt"; mem_address_width : natural := 16; address_width : natural := 16; memory_type : string := "TRI_PORT_X" -- "DUAL_PORT_" -- "ALTERA_LPM" -- "XILINX_16X" ); port( reset : in std_logic; clk : in std_logic; uart_write : out std_logic; uart_read : in std_logic; credit_in : in std_logic; valid_out : out std_logic; TX : out std_logic_vector(31 downto 0); credit_out : out std_logic; valid_in : in std_logic; RX: in std_logic_vector(31 downto 0); link_faults : in std_logic_vector(4 downto 0); turn_faults : in std_logic_vector(19 downto 0); Rxy_reconf_PE : out std_logic_vector(7 downto 0); Cx_reconf_PE : out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits) Reconfig_command : out std_logic; -- IJTAG RAM instrument related signals --SI : in std_logic; --SO : out std_logic; --SEL : in std_logic; --SE : in std_logic; --CE : in std_logic; --UE : in std_logic; --RST : in std_logic; --TCK : in std_logic; GPIO_out: out std_logic_vector(15 downto 0); GPIO_in: in std_logic_vector(21 downto 0); IJTAG_select : in std_logic; IJTAG_clk : in std_logic; IJTAG_reset : in std_logic; IJTAG_enable : in std_logic; IJTAG_write_byte_enable : in std_logic_vector(3 downto 0); IJTAG_address : in std_logic_vector(31 downto 2); IJTAG_data_write : in std_logic_vector(31 downto 0); IJTAG_data_read : out std_logic_vector(31 downto 0) ); end; --entity NoC_Node architecture updated of NoC_Node is signal interrupt : std_logic := '0'; signal mem_write : std_logic; signal address : std_logic_vector(31 downto 2); signal data_write : std_logic_vector(31 downto 0); signal data_read : std_logic_vector(31 downto 0); signal pause1 : std_logic := '0'; signal pause2 : std_logic := '0'; signal pause : std_logic; signal no_ddr_start: std_logic; signal no_ddr_stop : std_logic; signal byte_we : std_logic_vector(3 downto 0); signal GPIO_out_tmp : std_logic_vector(31 downto 0); signal GPIO_in_tmp : std_logic_vector(31 downto 0); --signal credit_in, valid_in: std_logic := '0'; --signal credit_out, valid_out: std_logic := '0'; --signal RX: std_logic_vector(31 downto 0) := (others => '0'); --signal TX: std_logic_vector(31 downto 0) := (others => '0'); -- signal credit_counter_out_0: std_logic_vector (1 downto 0); -- IJTAG RAM instrument related stuff --signal RAM_instr_data_read : std_logic_vector(31 downto 0); --signal RAM_instr_data_write : std_logic_vector(31 downto 0); --signal RAM_instr_address_out : std_logic_vector(31 downto 2); --signal RAM_instr_write_enable : std_logic; --signal RAM_instrument_enabled : std_logic; --signal muxed_mem_clk : std_logic; --signal muxed_mem_address : std_logic_vector(31 downto 2); --signal muxed_mem_data_write : std_logic_vector(31 downto 0); --signal muxed_mem_data_read : std_logic_vector(31 downto 0); --signal muxed_mem_byte_we : std_logic_vector(3 downto 0); --signal muxed_mem_pause : std_logic; --component RAMAccessInstrument is -- Generic ( DataSize : positive := 8; -- AddressSize : positive := 8); -- Port ( -- Scan Interface scan_client ---------- -- SI : in STD_LOGIC; -- ScanInPort -- SO : out STD_LOGIC; -- ScanOutPort -- SEL : in STD_LOGIC; -- SelectPort -- ---------------------------------------- -- SE : in STD_LOGIC; -- ShiftEnPort -- CE : in STD_LOGIC; -- CaptureEnPort -- UE : in STD_LOGIC; -- UpdateEnPort -- RST : in STD_LOGIC; -- ResetPort -- TCK : in STD_LOGIC; -- TCKPort -- MEM_SIB_SEL : out STD_LOGIC; -- -- RAM interface -- RAM_data_read : in STD_LOGIC_VECTOR (DataSize-1 downto 0); -- RAM_data_write : out STD_LOGIC_VECTOR (DataSize-1 downto 0); -- RAM_address_out : out STD_LOGIC_VECTOR (AddressSize-1 downto 0); -- RAM_write_enable : out STD_LOGIC); --end component; begin --architecture --pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns; pause1 <= '0'; --pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns; pause2 <= '0'; pause <= pause1 or pause2; --gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK --gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV --gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD --gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK --GPIO connections GPIO_out <= GPIO_out_tmp(15 downto 0); GPIO_in_tmp <= (31 downto 22 => '0') & GPIO_in; u1_plasma: plasma generic map ( memory_type => memory_type, ethernet => '0', use_cache => '0', log_file => log_file, current_address => current_address, stim_file => stim_file ) PORT MAP ( clk => clk, reset => reset, uart_read => uart_read, uart_write => uart_write, address => address, byte_we => byte_we, data_write => data_write, data_read => data_read, mem_pause_in => pause, no_ddr_start => no_ddr_start, no_ddr_stop => no_ddr_stop, gpio0_out => GPIO_out_tmp, gpioA_in => GPIO_in_tmp, credit_in => credit_in, valid_out => valid_out, TX => TX, credit_out => credit_out, valid_in => valid_in, RX => RX, link_faults => link_faults, turn_faults => turn_faults, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE , Reconfig_command => Reconfig_command, IJTAG_select => IJTAG_select, IJTAG_clk => IJTAG_clk, IJTAG_reset => IJTAG_reset, IJTAG_enable => IJTAG_enable, IJTAG_write_byte_enable => IJTAG_write_byte_enable, IJTAG_address => IJTAG_address, IJTAG_data_write => IJTAG_data_write, IJTAG_data_read => IJTAG_data_read ); --memory_impl: memory -- generic map (address_width => mem_address_width) -- -- port map ( -- clk => muxed_mem_clk, -- address => muxed_mem_address, -- data_write => muxed_mem_data_write, -- pause => muxed_mem_pause, -- byte_we => muxed_mem_byte_we, -- data_read => muxed_mem_data_read -- ); --RAM_instr : RAMAccessInstrument -- generic map ( DataSize => 32, -- AddressSize => 30) -- port map ( SI => SI, -- SO => SO, -- SEL => SEL, -- SE => SE, -- CE => CE, -- UE => UE, -- RST => RST, -- TCK => TCK, -- MEM_SIB_SEL => RAM_instrument_enabled, -- RAM_data_read => RAM_instr_data_read, -- RAM_data_write => RAM_instr_data_write, -- RAM_address_out => RAM_instr_address_out, -- RAM_write_enable => RAM_instr_write_enable); --muxed_mem_clk <= clk when RAM_instrument_enabled = '0' else TCK; --muxed_mem_address <= address when RAM_instrument_enabled = '0' else RAM_instr_address_out; --muxed_mem_data_write <= data_write when RAM_instrument_enabled = '0' else RAM_instr_data_write; --muxed_mem_data_read <= data_read when RAM_instrument_enabled = '0' else RAM_instr_data_read; --muxed_mem_pause <= pause when RAM_instrument_enabled = '0' else '0'; --muxed_mem_byte_we <= byte_we when RAM_instrument_enabled = '0' else (others => RAM_instr_write_enable); end; --architecture logic
gpl-3.0
428a254773518af54d1bdce68f0bbd01
0.512026
3.698912
false
false
false
false
elainemielas/CVUT_BI-PNO
aut/automat.vhd
1
5,604
library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity AUTOMAT is port ( KEY_F : in std_logic; -- high for one clock when key 'f' pressed KEY_U : in std_logic; -- high for one clock when key 'u' pressed KEY_L : in std_logic; -- high for one clock when key 'l' pressed KEY_PRESS : in std_logic; -- high for one clock when any key pressed CLK : in std_logic; -- standard 50MHz clock RESET : in std_logic; JCHYBA : out std_logic; -- detekovano s 1 chybou SHODA : out std_logic; -- detekovana uplna shoda VYSTUP : out std_logic_vector ( 0 to 8 ) ); end AUTOMAT; architecture AUTOMAT_BODY of AUTOMAT is signal STAV, DALSI_STAV : std_logic_vector(0 to 8); -- bit 0 = stav 1 a tak dale begin PRECHODY : process (KEY_F, KEY_U, KEY_L, KEY_PRESS, STAV) begin DALSI_STAV <= STAV; case STAV is -- 1 when "100000000" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 else DALSI_STAV <= "100001000"; -- 1,6 end if; -- 1,2 when "110000000" => if KEY_F = '1' then DALSI_STAV <= "110000100"; -- 1,2,7 elsif KEY_U = '1' then DALSI_STAV <= "101001000"; -- 1,3,6 else DALSI_STAV <= "100001100"; -- 1,6,7 end if; -- 1,6 when "100001000" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 elsif KEY_U = '1' then DALSI_STAV <= "100001100"; -- 1,6,7 else DALSI_STAV <= "100001000"; -- 1,6 end if; -- 1,2,7 when "110000100" => if KEY_F = '1' then DALSI_STAV <= "110000100"; -- 1,2,7 elsif KEY_U = '1' then DALSI_STAV <= "101001000"; -- 1,3,6 elsif KEY_L = '1' then DALSI_STAV <= "100001110"; -- 1,6,7,8 else DALSI_STAV <= "100001100"; -- 1,6,7 end if; -- 1,6,7 when "100001100" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 elsif KEY_U = '1' then DALSI_STAV <= "100001100"; -- 1,6,7 elsif KEY_L = '1' then DALSI_STAV <= "100001010"; -- 1,6,8 else DALSI_STAV <= "100001000"; -- 1,6 end if; -- 1,3,6 when "101001000" => if KEY_F = '1' then DALSI_STAV <= "110000010"; -- 1,2,8 elsif KEY_U = '1' then DALSI_STAV <= "100001110"; -- 1,6,7,8 elsif KEY_L = '1' then DALSI_STAV <= "100101000"; -- 1,4,6 else DALSI_STAV <= "100001010"; -- 1,6,8 end if; -- 1,6,7,8 when "100001110" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 elsif KEY_U = '1' then DALSI_STAV <= "100001100"; -- 1,6,7 elsif KEY_L = '1' then DALSI_STAV <= "100001011"; -- 1,6,8,9 else DALSI_STAV <= "100001000"; -- 1,6 end if; -- 1,6,8 when "100001010" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 elsif KEY_U = '1' then DALSI_STAV <= "100001100"; -- 1,6,7 elsif KEY_L = '1' then DALSI_STAV <= "100001001"; -- 1,6,9 else DALSI_STAV <= "100001000"; -- 1,6 end if; -- 1,4,6 when "100101000" => if KEY_F = '1' then DALSI_STAV <= "110000001"; -- 1,2,9 elsif KEY_U = '1' then DALSI_STAV <= "100001101"; -- 1,6,7,9 elsif KEY_L = '1' then DALSI_STAV <= "100011000"; -- 1,5,6 else DALSI_STAV <= "100001001"; -- 1,6,9 end if; -- 1,2,8 when "110000010" => if KEY_F = '1' then DALSI_STAV <= "110000100"; -- 1,2,7 elsif KEY_U = '1' then DALSI_STAV <= "101001000"; -- 1,3,6 elsif KEY_L = '1' then DALSI_STAV <= "100001101"; -- 1,6,7,9 else DALSI_STAV <= "100001100"; -- 1,6,7 end if; -- 1,6,8,9 when "100001011" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 elsif KEY_U = '1' then DALSI_STAV <= "100001100"; -- 1,6,7 elsif KEY_L = '1' then DALSI_STAV <= "100001001"; -- 1,6,9 else DALSI_STAV <= "100001000"; -- 1,6 end if; -- 1,6,9 when "100001001" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 elsif KEY_U = '1' then DALSI_STAV <= "100001100"; -- 1,6,7 else DALSI_STAV <= "100001000"; -- 1,6 end if; -- 1,2,9 when "110000001" => if KEY_F = '1' then DALSI_STAV <= "110000100"; -- 1,2,7 elsif KEY_U = '1' then DALSI_STAV <= "101001000"; -- 1,3,6 else DALSI_STAV <= "100001100"; -- 1,6,7 end if; -- 1,6,7,9 when "100001101" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 elsif KEY_U = '1' then DALSI_STAV <= "100001100"; -- 1,6,7 elsif KEY_L = '1' then DALSI_STAV <= "100001010"; -- 1,6,8 else DALSI_STAV <= "100001000"; -- 1,6 end if; -- 1,5,6 when "100011000" => if KEY_F = '1' then DALSI_STAV <= "110000000"; -- 1,2 elsif KEY_U = '1' then DALSI_STAV <= "100001100"; -- 1,6,7 else DALSI_STAV <= "100001000"; -- 1,6 end if; when others => NULL; end case; end process; VYSTUPY : process (STAV) begin JCHYBA <= '0'; SHODA <= '0'; if STAV(8) = '1' then JCHYBA <= '1'; elsif STAV(4) = '1' then SHODA <= '1'; end if; VYSTUP <= STAV; end process; REG : process (CLK) begin if CLK'event and CLK = '1' then if RESET = '1' then STAV <= "100000000"; -- reset elsif KEY_PRESS = '1' then STAV <= DALSI_STAV; else STAV <= STAV; end if; end if; end process; end architecture;
mit
aad9c3ba4567df30bbf7f936fa0a1401
0.538544
2.99359
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Processor_NI/plasma.vhd
3
14,923
--------------------------------------------------------------------- -- TITLE: Plasma (CPU core with memory) -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 6/4/02 -- FILENAME: plasma.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- This entity combines the CPU core with memory and a UART. -- -- Memory Map: -- 0x00000000 - 0x0000ffff Internal RAM (8KB) -- 0x10000000 - 0x100fffff External RAM (1MB) -- Access all Misc registers with 32-bit accesses -- 0x20000000 Uart Write (will pause CPU if busy) -- 0x20000000 Uart Read -- 0x20000010 IRQ Mask -- 0x20000020 IRQ Status -- 0x20000030 GPIO0 Out Set bits -- 0x20000040 GPIO0 Out Clear bits -- 0x20000050 GPIOA In -- 0x20000060 Counter -- 0x20000070 Ethernet transmit count -- IRQ bits: -- 7 GPIO31 -- 6 ^GPIO31 -- 5 EthernetSendDone -- 4 EthernetReceive -- 3 Counter(18) -- 2 ^Counter(18) -- 1 ^UartWriteBusy -- 0 UartDataAvailable -- modified by: Siavoosh Payandeh Azad -- Change logs: -- * An NI has been instantiated! -- * some changes has been applied to the ports of the CPU to facilitate the new NI! --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity plasma is generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM"; log_file : string := "UNUSED"; ethernet : std_logic := '0'; use_cache : std_logic := '0'; current_address : integer := 0; stim_file: string :="code.txt"); port(clk : in std_logic; reset : in std_logic; uart_write : out std_logic; uart_read : in std_logic; address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_write : out std_logic_vector(31 downto 0); data_read : in std_logic_vector(31 downto 0); mem_pause_in : in std_logic; no_ddr_start : out std_logic; no_ddr_stop : out std_logic; gpio0_out : out std_logic_vector(31 downto 0); gpioA_in : in std_logic_vector(31 downto 0); credit_in : in std_logic; valid_out: out std_logic; TX: out std_logic_vector(31 downto 0); credit_out : out std_logic; valid_in: in std_logic; RX: in std_logic_vector(31 downto 0) ); end; --entity plasma architecture logic of plasma is signal address_next : std_logic_vector(31 downto 2); signal byte_we_next : std_logic_vector(3 downto 0); signal cpu_address : std_logic_vector(31 downto 0); signal cpu_byte_we : std_logic_vector(3 downto 0); signal cpu_data_w : std_logic_vector(31 downto 0); signal cpu_data_r : std_logic_vector(31 downto 0); signal cpu_pause : std_logic; signal data_read_uart : std_logic_vector(7 downto 0); signal write_enable : std_logic; signal eth_pause_in : std_logic; signal eth_pause : std_logic; signal mem_busy : std_logic; signal enable_misc : std_logic; signal enable_uart : std_logic; signal enable_uart_read : std_logic; signal enable_uart_write : std_logic; signal enable_eth : std_logic; signal gpio0_reg : std_logic_vector(31 downto 0); signal uart_write_busy : std_logic; signal uart_data_avail : std_logic; signal irq_mask_reg : std_logic_vector(7 downto 0); signal irq_status : std_logic_vector(7 downto 0); signal irq : std_logic; signal irq_eth_rec : std_logic; signal irq_eth_send : std_logic; signal counter_reg : std_logic_vector(31 downto 0); signal ram_enable : std_logic; signal ram_byte_we : std_logic_vector(3 downto 0); signal ram_address, ram_address_late : std_logic_vector(31 downto 2); signal ram_data_w : std_logic_vector(31 downto 0); signal ram_data_r, ram_data_r_ni, ram_data_r_uart : std_logic_vector(31 downto 0); signal NI_irq_out : std_logic; --signal NI_read_flag : std_logic; --signal NI_write_flag : std_logic; signal cache_access : std_logic; signal cache_checking : std_logic; signal cache_miss : std_logic; signal cache_hit : std_logic; begin --architecture write_enable <= '1' when cpu_byte_we /= "0000" else '0'; mem_busy <= eth_pause or mem_pause_in; cache_hit <= cache_checking and not cache_miss; cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy cache_miss or --Cache wait (cpu_address(28) and not cache_hit and mem_busy); --DDR or flash irq_status <= gpioA_in(31) & not gpioA_in(31) & irq_eth_send & irq_eth_rec & counter_reg(18) & not counter_reg(18) & not uart_write_busy & uart_data_avail; irq <= '1' when ((irq_status and irq_mask_reg) /= ZERO(7 downto 0) or (NI_irq_out = '1')) else '0'; -- modified by Behrad gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29); gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0); enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0'; enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0'; enable_uart_read <= enable_uart and not write_enable; enable_uart_write <= enable_uart and write_enable; enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0'; cpu_address(1 downto 0) <= "00"; u1_cpu: mlite_cpu generic map (memory_type => memory_type) PORT MAP ( clk => clk, reset_in => reset, intr_in => irq, --NI_read_flag => NI_read_flag, --NI_write_flag => NI_write_flag, address_next => address_next, --before rising_edge(clk) byte_we_next => byte_we_next, address => cpu_address(31 downto 2), --after rising_edge(clk) byte_we => cpu_byte_we, data_w => cpu_data_w, data_r => cpu_data_r, mem_pause => cpu_pause); opt_cache: if use_cache = '0' generate cache_access <= '0'; cache_checking <= '0'; cache_miss <= '0'; end generate; opt_cache2: if use_cache = '1' generate --Control 4KB unified cache that uses the upper 4KB of the 8KB --internal RAM. Only lowest 2MB of DDR is cached. u_cache: cache generic map (memory_type => memory_type) PORT MAP ( clk => clk, reset => reset, address_next => address_next, byte_we_next => byte_we_next, cpu_address => cpu_address(31 downto 2), mem_busy => mem_busy, cache_access => cache_access, --access 4KB cache cache_checking => cache_checking, --checking if cache hit cache_miss => cache_miss); --cache miss end generate; --opt_cache2 no_ddr_start <= not eth_pause and cache_checking; no_ddr_stop <= not eth_pause and cache_miss; eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking); misc_proc: process(clk, reset, cpu_address, enable_misc, ram_data_r, ram_address_late, ram_data_r_ni, data_read, data_read_uart, cpu_pause, irq_mask_reg, irq_status, gpio0_reg, write_enable, cache_checking, gpioA_in, counter_reg, cpu_data_w) begin case cpu_address(30 downto 28) is when "000" => --internal RAM if ((ram_address_late = NI_reserved_data_address) or (ram_address_late = NI_flag_address) or (ram_address_late = NI_counter_address)) then cpu_data_r <= ram_data_r_ni; elsif ram_address_late = uart_count_value_address then cpu_data_r <= ram_data_r_uart; else cpu_data_r <= ram_data_r; end if; when "001" => --external RAM if cache_checking = '1' then --cpu_data_r <= ram_data_r; --cache if ((ram_address_late = NI_reserved_data_address) or (ram_address_late = NI_flag_address) or (ram_address_late = NI_counter_address)) then cpu_data_r <= ram_data_r_ni; elsif ram_address_late = uart_count_value_address then cpu_data_r <= ram_data_r_uart; else cpu_data_r <= ram_data_r; --cache end if; else cpu_data_r <= data_read; --DDR end if; when "010" => --misc case cpu_address(6 downto 4) is when "000" => --uart cpu_data_r <= ZERO(31 downto 8) & data_read_uart; when "001" => --irq_mask cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg; when "010" => --irq_status cpu_data_r <= ZERO(31 downto 8) & irq_status; when "011" => --gpio0 cpu_data_r <= gpio0_reg; when "101" => --gpioA cpu_data_r <= gpioA_in; when "110" => --counter cpu_data_r <= counter_reg; when others => cpu_data_r <= gpioA_in; end case; when "011" => --flash cpu_data_r <= data_read; when others => cpu_data_r <= ZERO; end case; if reset = '1' then irq_mask_reg <= ZERO(7 downto 0); gpio0_reg <= ZERO; counter_reg <= ZERO; elsif rising_edge(clk) then counter_reg <= bv_inc(counter_reg); if cpu_pause = '0' then if enable_misc = '1' and write_enable = '1' then if cpu_address(6 downto 4) = "001" then irq_mask_reg <= cpu_data_w(7 downto 0); elsif cpu_address(6 downto 4) = "011" then gpio0_reg <= gpio0_reg or cpu_data_w; elsif cpu_address(6 downto 4) = "100" then gpio0_reg <= gpio0_reg and not cpu_data_w; elsif cpu_address(6 downto 4) = "110" then counter_reg <= cpu_data_w; end if; end if; end if; end if; end process; process(ram_address, reset, clk)begin if reset = '1' then ram_address_late <= (others => '0'); elsif clk'event and clk = '1' then ram_address_late <= ram_address; end if; end process; ram_proc: process(cache_access, cache_miss, address_next, cpu_address, byte_we_next, cpu_data_w, data_read) begin if cache_access = '1' then --Check if cache hit or write through ram_enable <= '1'; ram_byte_we <= byte_we_next; ram_address(31 downto 2) <= ZERO(31 downto 16) & "0001" & address_next(11 downto 2); ram_data_w <= cpu_data_w; elsif cache_miss = '1' then --Update cache after cache miss ram_enable <= '1'; ram_byte_we <= "1111"; ram_address(31 downto 2) <= ZERO(31 downto 16) & "0001" & cpu_address(11 downto 2); ram_data_w <= data_read; else --Normal non-cache access if address_next(30 downto 28) = "000" then ram_enable <= '1'; else ram_enable <= '0'; end if; ram_byte_we <= byte_we_next; ram_address(31 downto 2) <= address_next(31 downto 2); ram_data_w <= cpu_data_w; end if; end process; u2_ram: ram generic map (memory_type => memory_type, stim_file => stim_file) port map ( clk => clk, reset => reset, enable => ram_enable, write_byte_enable => ram_byte_we, address => ram_address, data_write => ram_data_w, data_read => ram_data_r); u3_uart: uart generic map (log_file => log_file) port map( clk => clk, reset => reset, enable_read => enable_uart_read, enable_write => enable_uart_write, data_in => cpu_data_w(7 downto 0), data_out => data_read_uart, uart_read => uart_read, uart_write => uart_write, busy_write => uart_write_busy, data_avail => uart_data_avail, reg_enable =>ram_enable, reg_write_byte_enable =>ram_byte_we, reg_address =>ram_address, reg_data_write =>ram_data_w, reg_data_read =>ram_data_r_uart); dma_gen: if ethernet = '0' generate address <= cpu_address(31 downto 2); byte_we <= cpu_byte_we; data_write <= cpu_data_w; eth_pause <= '0'; gpio0_out(28 downto 24) <= ZERO(28 downto 24); irq_eth_rec <= '0'; irq_eth_send <= '0'; end generate; dma_gen2: if ethernet = '1' generate u4_eth: eth_dma port map( clk => clk, reset => reset, enable_eth => gpio0_reg(24), select_eth => enable_eth, rec_isr => irq_eth_rec, send_isr => irq_eth_send, address => address, --to DDR byte_we => byte_we, data_write => data_write, data_read => data_read, pause_in => eth_pause_in, mem_address => cpu_address(31 downto 2), --from CPU mem_byte_we => cpu_byte_we, data_w => cpu_data_w, pause_out => eth_pause, E_RX_CLK => gpioA_in(20), E_RX_DV => gpioA_in(19), E_RXD => gpioA_in(18 downto 15), E_TX_CLK => gpioA_in(14), E_TX_EN => gpio0_out(28), E_TXD => gpio0_out(27 downto 24)); end generate; u4_ni: NI generic map(current_address => current_address) port map ( clk => clk, reset => reset, enable => ram_enable, write_byte_enable => ram_byte_we, address => ram_address, data_write => ram_data_w, data_read => ram_data_r_ni, --NI_read_flag => NI_read_flag, --NI_write_flag => NI_write_flag, irq_out => NI_irq_out, credit_in => credit_in, valid_out => valid_out, TX => TX, credit_out => credit_out, valid_in => valid_in, RX => RX ); end; --architecture logic
gpl-3.0
511f1bb5a1c10da4f637456a7c6d9975
0.525297
3.514602
false
false
false
false
elainemielas/CVUT_BI-PNO
cvika/had/KITT.vhd
1
1,246
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use WORK.CONSCTANS.ALL; entity KITT is port ( CLK : in std_logic; RESET : in std_logic; LEDS : out std_logic_vector (7 downto 0) ); end KITT; architecture KITT_BODY of KITT is signal CNT_OUT : std_logic_vector (OUTPUT_WIDTH - 1 downto 0); signal UP, TOP, BOTTOM : std_logic; component CONTROLLER is port( CLK : in std_logic; RESET : in std_logic; TOP : in std_logic; BOTTOM : in std_logic; UP : out std_logic ); end component; component COUNTER is port ( CLK : in std_logic; RESET : in std_logic; UP : in std_logic; CNT_OUT : out std_logic_vector (OUTPUT_WIDTH - 1 downto 0); TOP : out std_logic; BOTTOM : out std_logic ); end component; component DECODER is port ( BIN_VALUE : in std_logic_vector (2 downto 0); ONE_HOT : out std_logic_vector (7 downto 0) ); end component; begin RADIC : CONTROLLER port map ( CLK => CLK, RESET => RESET, UP => UP, TOP => TOP, BOTTOM => BOTTOM ); CITAC : COUNTER port map ( CLK => CLK, RESET => RESET, UP => UP, CNT_OUT => CNT_OUT, TOP => TOP, BOTTOM => BOTTOM ); DEKODER : DECODER port map ( BIN_VALUE => CNT_OUT, ONE_HOT => LEDS); end architecture;
mit
af818c68ac859ad78271c9d5d5128460
0.62199
2.945626
false
false
false
false
AndyMcC0/UVVM_All
uvvm_util/src/uvvm_util_context.vhd
1
1,596
--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <[email protected]>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ context uvvm_util_context is library uvvm_util; use uvvm_util.types_pkg.all; use uvvm_util.hierarchy_linked_list_pkg.all; use uvvm_util.string_methods_pkg.all; use uvvm_util.adaptations_pkg.all; use uvvm_util.methods_pkg.all; use uvvm_util.bfm_common_pkg.all; use uvvm_util.alert_hierarchy_pkg.all; use uvvm_util.license_pkg.all; use uvvm_util.protected_types_pkg.all; end context;
mit
6355b11b40708bab058f1249b0284bb7
0.552005
4.956522
false
false
false
false
SKravitsky/ECEC412
IDEXRegister.vhd
1
1,647
library ieee; use ieee.std_logic_1164.all; entity IDEXRegister is port( clk, ALUSrcIn, BranchIn, MemWriteIn, MemReadIn, MemtoRegIn, RegDstIn, RegWriteIn: in std_logic; ALUOpIn: std_logic_vector(1 downto 0); AddressIn, InstructionIn, ReadDataOneIn, ReadDataTwoIn: std_logic_vector(31 downto 0); ALUSrcOut, BranchOut, MemWriteOut, MemReadOut, MemtoRegOut, RegDstOut, RegWriteOut: out std_logic; ALUOpOut: out std_logic_vector(1 downto 0); AddressOut, InstructionOut, ReadDataOneOut, ReadDataTwoOut: out std_logic_vector(31 downto 0) ); end IDEXRegister; architecture Structural of IDEXRegister is signal ALUSrc, Branch, MemWrite, MemRead, MemtoReg, RegDst, RegWrite: std_logic := '0'; signal ALUOp: std_logic_vector(1 downto 0) := "00"; signal Address, Instruction, ReadDataOne, ReadDataTwo: std_logic_vector(31 downto 0) := X"00000000"; begin AddressOut <= Address; ALUOPOut <= ALUOp; ALUSrcOut <= ALUSrc; BranchOut <= Branch; InstructionOut <= Instruction; MemWriteOut <= MemWrite; MemReadOut <= MemRead; MemtoRegOut <= MemtoReg; ReadDataOneOut <= ReadDataOne; ReadDataTwoOut <= ReadDataTwo; RegDstOut <= RegDst; RegWriteOut <= RegWrite; process(clk) begin if rising_edge(clk) then Address <= AddressIn; ALUOp <= ALUOpIn; ALUSrc <= ALUSrcIn; Branch <= BranchIn; Instruction <= InstructionIn; MemWrite <= MemWriteIn; MemRead <= MemReadIn; MemtoReg <= MemtoRegIn; ReadDataOne <= ReadDataOneIn; ReadDataTwo <= ReadDataTwoIn; RegDst <= RegDstIn; RegWrite <= RegWriteIn; end if; end process; end Structural;
apache-2.0
ba36d7033dcdb90c290c26b288be2b78
0.703097
4.107232
false
false
false
false
camacazio/de0_nano_DAC
DE0_12bitDAC_controller/logic_processor.vhd
1
7,152
---------------------------------------------------------------------------------- -- Logic pulse sequencer -- Pulls data out from memory and assumes it comes in with the following flow: -- 1)Logic step values and little endian duration -- 2)Rest of duration -- If duration comes in as x"FFFF", read_addr is reset to 0 (it is up to the user to design software to insert this) -- If duration comes in as x"FFFE", the 'running' state is paused to await for a new trigger ( " ) ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity logic_processor is port ( -- Clock input clk_sys : in std_logic; -- reset trigger for logic process iRST : in std_logic; -- Memory data bus -- 16 bit data input for logic sequence data data_in : in std_logic_vector(15 downto 0); -- Memory address location for DAC data from memory read_addr_out : out std_logic_vector(9 downto 0); -- Input to begin running waveforms from computer trigger run_cmd : in std_logic; -- Pulse sequencing ports -- Input logic ports iLogic : in std_logic_vector(1 downto 0); -- Output logic ports oLogic : out std_logic_vector(3 downto 0); -- Logic for triggering the next waveform in memory oDAC0_trigger : out std_logic; oDAC1_trigger : out std_logic; -- Logic derived from ADC values, designed to go 'high' when voltage below some value iADC0_logic : in std_logic; iADC1_logic : in std_logic; -- Logic to enable the ADC interlock ADC_active : out std_logic; -- LEDs to display logic states oLED : out std_logic_vector(5 downto 0) ); end entity; architecture rtl of logic_processor is -- Internal copy of the address for reading from memory signal read_addr : std_logic_vector((read_addr_out'length - 1) downto 0) := (others => '0'); -- Internal version of output logic for singal processing signal Logic : std_logic_vector(3 downto 0) := (others => '0'); signal DAC_trigger : std_logic_vector(1 downto 0) := (others => '0'); -- Amount of clock cycles to read in new sequence constant READ_TIME : std_logic_vector(23 downto 0) := x"000002"; begin -- latch read address read_addr_out <= read_addr; -- push through input trigger to DAC oDAC0_trigger <= iLogic(0) when DAC_trigger(0) = '0' else '1'; oDAC1_trigger <= iLogic(0) when DAC_trigger(1) = '0' else '1'; -- ADC-measurement dependent logic oLogic(0) <= Logic(0) when iADC0_logic = '0' else '1'; oLogic(1) <= Logic(1) when iADC1_logic = '0' else '1'; oLogic(2) <= Logic(2); oLogic(3) <= Logic(3); -- Display logic states oLED(3 downto 0) <= Logic; oLED(5 downto 4) <= DAC_trigger; process (clk_sys, run_cmd, iLogic(1), iRST) -- States for the DAC type RUN_STATES is (RESET, IDLE, RUNNING); variable run_state : RUN_STATES := RESET; -- States when pulling data out of memory type READ_MODES is (READ_1, READ_2, DONE, NONE); variable read_mode : READ_MODES := READ_1; -- Data communication for the logic sequence variable data_comm : std_logic_vector(15 downto 0); -- The following are internal values for outputting to the DAC waveform -- Voltage values go 15 downto 4, we have 3 downto 0 to hold decimal points in lower bits variable logic_step : std_logic_vector(7 downto 0); variable duration : std_logic_vector(23 downto 0); -- "Reading" versions for reading memory while the DAC still runs the previous waveform cycle variable logic_step_read : std_logic_vector(7 downto 0); variable duration_read : std_logic_vector(23 downto 0); -- Whether or not we need to be counting variable timing : std_logic; begin -- check reset flag if iRST = '0' then run_state := RESET; else -- Logic sequence operations if rising_edge(clk_sys) then case run_state is when RESET => -- Return to boot conditions Logic <= (others => '0'); DAC_trigger <= (others => '0'); read_addr <= (others => '0'); run_state := IDLE; when IDLE => -- Awaiting a run command -- Prepare to begin reading data at start of 'running' read_mode := READ_1; -- No counting down when beginning to read a waveform timing := '0'; -- Check if the next value on the memory register signifies the end of memory, -- should be in the position to which READ_1 would point in memory if data_in = x"FFFF" then read_addr <= (others => '0'); end if; -- Check conditions to run the waveform if (run_cmd = '1' OR iLogic(1) = '1') then run_state := RUNNING; end if; when RUNNING => -- RUNNING is interpreting data at the current address -- Latch external waveform data data_comm := data_in; case read_mode is when READ_1 => -- Read in the time to run the waveform logic_step_read := data_comm(7 downto 0); duration_read(7 downto 0) := data_comm(15 downto 8); read_addr <= read_addr + '1'; -- Check if the time value flags the need to leave RUNNING if data_comm >= x"FFFE" then -- Await next run trigger run_state := IDLE; else -- Read in the starting voltage read_mode := READ_2; end if; when READ_2 => -- Read the voltage duration_read(23 downto 8) := data_comm; read_addr <= read_addr + '1'; -- Handling the case that duration - read_time < 0 to make sure we have time to load the next logic in each step if duration < READ_TIME then duration := READ_TIME; end if; -- Read in the slope read_mode := DONE; when DONE => -- Latch the read data into values used for writing to DACs logic_step := logic_step_read; -- If the next data requires waiting for a new trigger, need to allow the waveform to finish and then break to IDLE if data_comm >= x"FFFE" then duration := duration_read - 1 + READ_TIME; else duration := duration_read - 1; end if; -- We are going to be timing operation time timing := '1'; -- Prepared to run the waveform read_mode := NONE; when NONE => -- Case statement at NONE should end with the read address for the next waveform's time read_mode := NONE; end case; -- Output the logic vector Logic <= logic_step(3 downto 0); DAC_trigger <= logic_step(5 downto 4); ADC_active <= logic_step(6); if timing = '1' then if duration <= READ_TIME then --Start getting ready for the next round of data timing := '0'; -- Clear DAC triggers DAC_trigger <= (others => '0'); -- Read next pulse read_mode := READ_1; else -- Still waiting, so loop duration := duration - 1; read_mode := NONE; end if; end if; end case; end if; end if; end process; end rtl;
gpl-3.0
105999382726360ec1a0fd9ad582bf6f
0.60976
3.38156
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/allocator_credit_counter_logic_pseudo_checkers.vhd
9
15,296
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity allocator_credit_counter_logic_pseudo_checkers is port ( -- flow control credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic; credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0); valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid ! credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0); -- Checker outputs err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_N_credit_counter_N_out_increment, err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change, err_grant_N_credit_counter_N_out_decrement, err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change, err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_E_credit_counter_E_out_increment, err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change, err_grant_E_credit_counter_E_out_decrement, err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change, err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_W_credit_counter_W_out_increment, err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change, err_grant_W_credit_counter_W_out_decrement, err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change, err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_S_credit_counter_S_out_increment, err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change, err_grant_S_credit_counter_S_out_decrement, err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change, err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal, err_credit_in_L_credit_counter_L_out_increment, err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change, err_grant_L_credit_counter_L_out_decrement, err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change, err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic ); end allocator_credit_counter_logic_pseudo_checkers; architecture behavior of allocator_credit_counter_logic_pseudo_checkers is begin -- The combionational part ---------------------------------------------------------------- -- Checkers for the process handling the credit counters -- North credit counter process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out) begin if (credit_in_N = '1' and valid_N = '1' and credit_counter_N_in /= credit_counter_N_out) then err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1'; else err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0'; end if; end process; process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out) begin if (credit_in_N = '1' and valid_N = '1' and credit_counter_N_out < 3 and credit_counter_N_in /= credit_counter_N_out + 1) then err_credit_in_N_credit_counter_N_out_increment <= '1'; else err_credit_in_N_credit_counter_N_out_increment <= '0'; end if; end process; process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out) begin if (credit_in_N = '1' and valid_N = '0' and credit_counter_N_out = 3 and credit_counter_N_in /= credit_counter_N_out) then err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '1'; else err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '0'; end if; end process; process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out) begin if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out > 0 and credit_counter_N_in /= credit_counter_N_out - 1) then err_grant_N_credit_counter_N_out_decrement <= '1'; else err_grant_N_credit_counter_N_out_decrement <= '0'; end if; end process; process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out) begin if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out = 0 and credit_counter_N_in /= credit_counter_N_out) then err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '1'; else err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '0'; end if; end process; process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out) begin if (credit_in_N = '0' and valid_N = '0' and credit_counter_N_in /= credit_counter_N_out) then err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1'; else err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0'; end if; end process; -- East credit counter process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out) begin if (credit_in_E = '1' and valid_E = '1' and credit_counter_E_in /= credit_counter_E_out) then err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1'; else err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0'; end if; end process; process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out) begin if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out < 3 and credit_counter_E_in /= credit_counter_E_out + 1) then err_credit_in_E_credit_counter_E_out_increment <= '1'; else err_credit_in_E_credit_counter_E_out_increment <= '0'; end if; end process; process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out) begin if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out = 3 and credit_counter_E_in /= credit_counter_E_out) then err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '1'; else err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '0'; end if; end process; process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out) begin if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out > 0 and credit_counter_E_in /= credit_counter_E_out - 1) then err_grant_E_credit_counter_E_out_decrement <= '1'; else err_grant_E_credit_counter_E_out_decrement <= '0'; end if; end process; process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out) begin if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out = 0 and credit_counter_E_in /= credit_counter_E_out) then err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '1'; else err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '0'; end if; end process; process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out) begin if (credit_in_E = '0' and valid_E = '0' and credit_counter_E_in /= credit_counter_E_out) then err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1'; else err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0'; end if; end process; -- West credit counter process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out) begin if (credit_in_W = '1' and valid_W = '1' and credit_counter_W_in /= credit_counter_W_out) then err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1'; else err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0'; end if; end process; process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out) begin if (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out < 3 and credit_counter_W_in /= credit_counter_W_out + 1) then err_credit_in_W_credit_counter_W_out_increment <= '1'; else err_credit_in_W_credit_counter_W_out_increment <= '0'; end if; end process; process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out) begin if ( (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out = 3) and credit_counter_W_in /= credit_counter_W_out) then err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '1'; else err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '0'; end if; end process; process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out) begin if (valid_W = '1' and credit_in_W = '0' and credit_counter_W_out > 0 and credit_counter_W_in /= credit_counter_W_out - 1) then err_grant_W_credit_counter_W_out_decrement <= '1'; else err_grant_W_credit_counter_W_out_decrement <= '0'; end if; end process; process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out) begin if ( valid_W = '1' and credit_in_W = '0' and credit_counter_W_out = 0 and credit_counter_W_in /= credit_counter_W_out) then err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '1'; else err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '0'; end if; end process; process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out) begin if (credit_in_W = '0' and valid_W = '0' and credit_counter_W_in /= credit_counter_W_out) then err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1'; else err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0'; end if; end process; -- South credit counter process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out) begin if (credit_in_S = '1' and valid_S = '1' and credit_counter_S_in /= credit_counter_S_out) then err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1'; else err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0'; end if; end process; process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out) begin if (credit_in_S = '1' and valid_S = '0' and credit_counter_S_out < 3 and credit_counter_S_in /= credit_counter_S_out + 1) then err_credit_in_S_credit_counter_S_out_increment <= '1'; else err_credit_in_S_credit_counter_S_out_increment <= '0'; end if; end process; process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out) begin if ( credit_in_S = '1' and valid_S = '0' and credit_counter_S_out = 3 and credit_counter_S_in /= credit_counter_S_out) then err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '1'; else err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '0'; end if; end process; process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out) begin if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out > 0 and credit_counter_S_in /= credit_counter_S_out - 1) then err_grant_S_credit_counter_S_out_decrement <= '1'; else err_grant_S_credit_counter_S_out_decrement <= '0'; end if; end process; process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out) begin if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out = 0 and credit_counter_S_in /= credit_counter_S_out) then err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '1'; else err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '0'; end if; end process; process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out) begin if (credit_in_S = '0' and valid_S = '0' and credit_counter_S_in /= credit_counter_S_out) then err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1'; else err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0'; end if; end process; -- Local credit counter process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out) begin if (credit_in_L = '1' and valid_L = '1' and credit_counter_L_in /= credit_counter_L_out) then err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1'; else err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0'; end if; end process; process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out) begin if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out < 3 and credit_counter_L_in /= credit_counter_L_out + 1) then err_credit_in_L_credit_counter_L_out_increment <= '1'; else err_credit_in_L_credit_counter_L_out_increment <= '0'; end if; end process; process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out) begin if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out = 3 and credit_counter_L_in /= credit_counter_L_out) then err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '1'; else err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '0'; end if; end process; process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out) begin if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out > 0 and credit_counter_L_in /= credit_counter_L_out - 1) then err_grant_L_credit_counter_L_out_decrement <= '1'; else err_grant_L_credit_counter_L_out_decrement <= '0'; end if; end process; process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out) begin if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out = 0 and credit_counter_L_in /= credit_counter_L_out) then err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '1'; else err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '0'; end if; end process; process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out) begin if (credit_in_L = '0' and valid_L = '0' and credit_counter_L_in /= credit_counter_L_out) then err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1'; else err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0'; end if; end process; END;
gpl-3.0
25e823c11cd767d6cc6b8fa48539a05a
0.667233
2.697232
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Processor_NI/NI.vhd
3
19,778
--------------------------------------------------------------------- -- Copyright (C) 2016 Siavoosh Payandeh Azad -- -- Network interface: Its an interrupt based memory mapped I/O for sending and recieving packets. -- the data that is sent to NI should be of the following form: -- FIRST write: 4bit source(31-28), 4 bit destination(27-14), 8bit packet length(23-16) -- Body write: 28 bit data(27-0) -- Last write: 28 bit data(27-0) --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use IEEE.NUMERIC_STD.all; use ieee.std_logic_textio.all; use std.textio.all; use work.mlite_pack.all; use ieee.std_logic_misc.all; entity NI is generic(current_address : integer := 10 -- the current node's address ); -- reserved address for the counter port(clk : in std_logic; reset : in std_logic; enable : in std_logic; write_byte_enable : in std_logic_vector(3 downto 0); address : in std_logic_vector(31 downto 2); data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); -- Flags used by JNIFR and JNIFW instructions --NI_read_flag : out std_logic; -- One if the N2P fifo is empty. No read should be performed if one. --NI_write_flag : out std_logic; -- One if P2N fifo is full. no write should be performed if one. -- interrupt signal: generated evertime a packet is recieved! irq_out : out std_logic; -- signals for sending packets to network credit_in : in std_logic; valid_out: out std_logic; TX: out std_logic_vector(31 downto 0); -- data sent to the NoC -- signals for reciving packets from the network credit_out : out std_logic; valid_in: in std_logic; RX: in std_logic_vector(31 downto 0) -- data recieved form the NoC ); end; --entity NI architecture logic of NI is -- packet format: -- the parity bit is calculated by the NI and the processor has no control over it -- flit type is generated by the NI and process has no control over it -- header flit -- 32 3bits 14 bits 14 bits 1bit 0 -- .----------------------------------------------------------------------. -- | flit type| SOURCE ADDRESS | DESTINATION ADDRESS |parity bit | -- '----------------------------------------------------------------------' -- SOURCE ADDRESS is added automatically by the NI (the processor has no control over it) -- DESTINATION ADDRESS is writen in the first write by the PE in FIFO_Data_out(13 downto 0) -- body flit 1 -- 32 3bits 14 bits 14 bits 1bit 0 -- .----------------------------------------------------------------------. -- | flit type| PACKET LENGTH | PACKET ID |parity bit | -- '----------------------------------------------------------------------' -- PACEKT ID is determined and added by the NI (the processor has no control over it) -- PACKET LENGTH is written in the 2nd write by PE in FIFO_Data_out(27 downto 14) -- other body flits -- 32 3bits 28 bits 1bit 0 -- .----------------------------------------------------------------------. -- | flit type| PAYLOAD DATA |parity bit | -- '----------------------------------------------------------------------' -- PAYLOAD DATA is written by the PE in FIFO_Data_out(27 downto 0) -- Tail flits -- 32 3bits 28 bits 1bit 0 -- .----------------------------------------------------------------------. -- | flit type| PAYLOAD DATA |parity bit | -- '----------------------------------------------------------------------' -- PAYLOAD DATA is written by the PE in FIFO_Data_out(27 downto 0) -- all the following signals are for sending data from processor to NoC signal storage, storage_in : std_logic_vector(31 downto 0); signal valid_data_in, valid_data: std_logic; signal old_address: std_logic_vector(31 downto 2); signal P2N_FIFO_read_pointer, P2N_FIFO_read_pointer_in, P2N_FIFO_write_pointer, P2N_FIFO_write_pointer_in: std_logic_vector(3 downto 0); signal P2N_write_en: std_logic; signal P2N_FIFO_MEM_1, P2N_FIFO_MEM_1_in : std_logic_vector(31 downto 0); signal P2N_FIFO_MEM_2, P2N_FIFO_MEM_2_in : std_logic_vector(31 downto 0); signal P2N_FIFO_MEM_3, P2N_FIFO_MEM_3_in : std_logic_vector(31 downto 0); signal P2N_FIFO_MEM_4, P2N_FIFO_MEM_4_in : std_logic_vector(31 downto 0); signal P2N_full, P2N_empty: std_logic; signal credit_counter_in, credit_counter_out: std_logic_vector(1 downto 0); signal packet_counter_in, packet_counter_out: std_logic_vector(13 downto 0); signal packet_length_counter_in, packet_length_counter_out: std_logic_vector(13 downto 0); signal grant : std_logic; type STATE_TYPE IS (IDLE, HEADER_FLIT, BODY_FLIT_1, BODY_FLIT, TAIL_FLIT); signal state, state_in : STATE_TYPE := IDLE; signal FIFO_Data_out : std_logic_vector(31 downto 0); signal flag_register, flag_register_in : std_logic_vector(31 downto 0); -- all the following signals are for sending the packets from NoC to processor signal N2P_FIFO_MEM_1, N2P_FIFO_MEM_1_in : std_logic_vector(31 downto 0); signal N2P_FIFO_MEM_2, N2P_FIFO_MEM_2_in : std_logic_vector(31 downto 0); signal N2P_FIFO_MEM_3, N2P_FIFO_MEM_3_in : std_logic_vector(31 downto 0); signal N2P_FIFO_MEM_4, N2P_FIFO_MEM_4_in : std_logic_vector(31 downto 0); signal N2P_Data_out, data_read_in : std_logic_vector(31 downto 0); signal N2P_FIFO_read_pointer, N2P_FIFO_read_pointer_in: std_logic_vector(3 downto 0); signal N2P_FIFO_write_pointer, N2P_FIFO_write_pointer_in: std_logic_vector(3 downto 0); signal N2P_full, N2P_empty: std_logic; signal N2P_read_en, N2P_read_en_in, N2P_write_en: std_logic; signal counter_register_in, counter_register : std_logic_vector(1 downto 0); begin process(clk, enable, write_byte_enable) begin if reset = '1' then storage <= (others => '0'); valid_data <= '0'; P2N_FIFO_read_pointer <= "0001"; P2N_FIFO_write_pointer <= "0001"; P2N_FIFO_MEM_1 <= (others=>'0'); P2N_FIFO_MEM_2 <= (others=>'0'); P2N_FIFO_MEM_3 <= (others=>'0'); P2N_FIFO_MEM_4 <= (others=>'0'); credit_counter_out <= "11"; packet_length_counter_out <= (others=>'0'); state <= IDLE; packet_counter_out <= (others=>'0'); ------------------------------------------------ N2P_FIFO_MEM_1 <= (others=>'0'); N2P_FIFO_MEM_2 <= (others=>'0'); N2P_FIFO_MEM_3 <= (others=>'0'); N2P_FIFO_MEM_4 <= (others=>'0'); N2P_FIFO_read_pointer <= "0001"; N2P_FIFO_write_pointer <= "0001"; credit_out <= '0'; counter_register <= (others => '0'); N2P_read_en <= '0'; flag_register <= (others =>'0'); old_address <= (others =>'0'); elsif clk'event and clk = '1' then old_address <= address; P2N_FIFO_write_pointer <= P2N_FIFO_write_pointer_in; P2N_FIFO_read_pointer <= P2N_FIFO_read_pointer_in; credit_counter_out <= credit_counter_in; packet_length_counter_out <= packet_length_counter_in; valid_data <= valid_data_in; if P2N_write_en = '1' then --write into the memory P2N_FIFO_MEM_1 <= P2N_FIFO_MEM_1_in; P2N_FIFO_MEM_2 <= P2N_FIFO_MEM_2_in; P2N_FIFO_MEM_3 <= P2N_FIFO_MEM_3_in; P2N_FIFO_MEM_4 <= P2N_FIFO_MEM_4_in; end if; packet_counter_out <= packet_counter_in; if write_byte_enable /= "0000" then storage <= storage_in; end if; state <= state_in; ------------------------------------------------ if N2P_write_en = '1' then --write into the memory N2P_FIFO_MEM_1 <= N2P_FIFO_MEM_1_in; N2P_FIFO_MEM_2 <= N2P_FIFO_MEM_2_in; N2P_FIFO_MEM_3 <= N2P_FIFO_MEM_3_in; N2P_FIFO_MEM_4 <= N2P_FIFO_MEM_4_in; end if; counter_register <= counter_register_in; N2P_FIFO_write_pointer <= N2P_FIFO_write_pointer_in; N2P_FIFO_read_pointer <= N2P_FIFO_read_pointer_in; credit_out <= '0'; N2P_read_en <= N2P_read_en_in; if N2P_read_en = '1' then credit_out <= '1'; end if; flag_register <= flag_register_in; end if; end process; -- everything bellow this line is pure combinatorial! --------------------------------------------------------------------------------------- --below this is code for communication from PE 2 NoC process(write_byte_enable, enable, address, storage, data_write, valid_data, P2N_write_en) begin storage_in <= storage ; valid_data_in <= valid_data; if enable = '1' and address = NI_reserved_data_address then if write_byte_enable /= "0000" then valid_data_in <= '1'; end if; if write_byte_enable(0) = '1' then storage_in(7 downto 0) <= data_write(7 downto 0); end if; if write_byte_enable(1) = '1' then storage_in(15 downto 8) <= data_write(15 downto 8); end if; if write_byte_enable(2) = '1' then storage_in(23 downto 16) <= data_write(23 downto 16); end if; if write_byte_enable(3) = '1' then storage_in(31 downto 24) <= data_write(31 downto 24); end if; end if; if P2N_write_en = '1' then valid_data_in <= '0'; end if; end process; process(storage, P2N_FIFO_write_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin case(P2N_FIFO_write_pointer) is when "0001" => P2N_FIFO_MEM_1_in <= storage; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4; when "0010" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= storage; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4; when "0100" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= storage; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4; when "1000" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= storage; when others => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4; end case ; end process; process(P2N_FIFO_read_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin case( P2N_FIFO_read_pointer ) is when "0001" => FIFO_Data_out <= P2N_FIFO_MEM_1; when "0010" => FIFO_Data_out <= P2N_FIFO_MEM_2; when "0100" => FIFO_Data_out <= P2N_FIFO_MEM_3; when "1000" => FIFO_Data_out <= P2N_FIFO_MEM_4; when others => FIFO_Data_out <= P2N_FIFO_MEM_1; end case ; end process; process(P2N_write_en, P2N_FIFO_write_pointer)begin if P2N_write_en = '1'then P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer(2 downto 0) & P2N_FIFO_write_pointer(3); else P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer; end if; end process; process(P2N_FIFO_read_pointer, grant)begin P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer; if grant = '1' then P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer(2 downto 0) & P2N_FIFO_read_pointer(3); end if; end process; process(P2N_full, valid_data) begin if valid_data = '1' and P2N_full ='0' then P2N_write_en <= '1'; else P2N_write_en <= '0'; end if; end process; process(P2N_FIFO_write_pointer, P2N_FIFO_read_pointer) begin P2N_empty <= '0'; P2N_full <= '0'; if P2N_FIFO_read_pointer = P2N_FIFO_write_pointer then P2N_empty <= '1'; end if; if P2N_FIFO_write_pointer = P2N_FIFO_read_pointer(0) & P2N_FIFO_read_pointer(3 downto 1) then P2N_full <= '1'; end if; end process; process (credit_in, credit_counter_out, grant)begin credit_counter_in <= credit_counter_out; if credit_in = '1' and grant = '1' then credit_counter_in <= credit_counter_out; elsif credit_in = '1' and credit_counter_out < 3 then credit_counter_in <= credit_counter_out + 1; elsif grant = '1' and credit_counter_out > 0 then credit_counter_in <= credit_counter_out - 1; end if; end process; process(P2N_empty, state, credit_counter_out, packet_length_counter_out, packet_counter_out, FIFO_Data_out) variable LINEVARIABLE : line; file VEC_FILE : text is out "sent.txt"; begin TX <= (others => '0'); grant<= '0'; packet_length_counter_in <= packet_length_counter_out; packet_counter_in <= packet_counter_out; case(state) is when IDLE => if P2N_empty = '0' then state_in <= HEADER_FLIT; else state_in <= IDLE; end if; when HEADER_FLIT => if credit_counter_out /= "00" then grant <= '1'; TX <= "001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0) & XOR_REDUCE("001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0)); state_in <= BODY_FLIT; packet_length_counter_in <= ("0000" & FIFO_Data_out(23 downto 16))-1; else state_in <= HEADER_FLIT; end if; when BODY_FLIT_1 => if credit_counter_out /= "00" and P2N_empty = '0'then packet_length_counter_in <= (FIFO_Data_out(27 downto 14))-2; grant <= '1'; TX <= "010" &FIFO_Data_out(27 downto 14) & packet_counter_out & XOR_REDUCE( "010" &FIFO_Data_out(27 downto 14) & packet_counter_out); state_in <= BODY_FLIT; else state_in <= BODY_FLIT_1; end if; when BODY_FLIT => if credit_counter_out /= "00" and P2N_empty = '0'then grant <= '1'; TX <= "010" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("010" & FIFO_Data_out(27 downto 0)); packet_length_counter_in <= packet_length_counter_out - "000000000001"; if packet_length_counter_out = "000000000010" then state_in <= TAIL_FLIT; else state_in <= BODY_FLIT; end if; else state_in <= BODY_FLIT; end if; when TAIL_FLIT => if credit_counter_out /= "00" and P2N_empty = '0' then grant <= '1'; TX <= "100" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("100" & FIFO_Data_out(27 downto 0)); packet_counter_in <= packet_counter_out +1; state_in <= IDLE; else state_in <= TAIL_FLIT; end if; when others => state_in <= IDLE; end case ; end procesS; valid_out <= grant; ---------------------------------------------------------------------------------------- --below this is code for communication from NoC 2 PE process(RX, N2P_FIFO_write_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin case( N2P_FIFO_write_pointer ) is when "0001" => N2P_FIFO_MEM_1_in <= RX; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4; when "0010" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= RX; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4; when "0100" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= RX; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4; when "1000" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= RX; when others => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4; end case ; end process; process(N2P_FIFO_read_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin case( N2P_FIFO_read_pointer ) is when "0001" => N2P_Data_out <= N2P_FIFO_MEM_1; when "0010" => N2P_Data_out <= N2P_FIFO_MEM_2; when "0100" => N2P_Data_out <= N2P_FIFO_MEM_3; when "1000" => N2P_Data_out <= N2P_FIFO_MEM_4; when others => N2P_Data_out <= N2P_FIFO_MEM_1; end case ; end process; process(address, write_byte_enable, N2P_empty)begin if address = NI_reserved_data_address and write_byte_enable = "0000" and N2P_empty = '0' then N2P_read_en_in <= '1'; else N2P_read_en_in <= '0'; end if; end process; process(N2P_write_en, N2P_FIFO_write_pointer)begin if N2P_write_en = '1'then N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer(2 downto 0)&N2P_FIFO_write_pointer(3); else N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer; end if; end process; process(N2P_read_en, N2P_empty, N2P_FIFO_read_pointer)begin if (N2P_read_en = '1' and N2P_empty = '0') then N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer(2 downto 0)&N2P_FIFO_read_pointer(3); else N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer; end if; end process; process(N2P_full, valid_in) begin if (valid_in = '1' and N2P_full ='0') then N2P_write_en <= '1'; else N2P_write_en <= '0'; end if; end process; process(N2P_FIFO_write_pointer, N2P_FIFO_read_pointer) begin if N2P_FIFO_read_pointer = N2P_FIFO_write_pointer then N2P_empty <= '1'; else N2P_empty <= '0'; end if; if N2P_FIFO_write_pointer = N2P_FIFO_read_pointer(0)&N2P_FIFO_read_pointer(3 downto 1) then N2P_full <= '1'; else N2P_full <= '0'; end if; end process; process(N2P_read_en, N2P_Data_out, old_address, flag_register) begin if old_address = NI_reserved_data_address and N2P_read_en = '1' then data_read <= N2P_Data_out; elsif old_address = NI_flag_address then data_read <= flag_register; elsif old_address = NI_counter_address then data_read <= "000000000000000000000000000000" & counter_register; else data_read <= (others => 'U'); end if; end process; process(N2P_write_en, N2P_read_en, RX, N2P_Data_out)begin counter_register_in <= counter_register; if N2P_write_en = '1' and RX(31 downto 29) = "001" and N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then counter_register_in <= counter_register; elsif N2P_write_en = '1' and RX(31 downto 29) = "001" then counter_register_in <= counter_register +1; elsif N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then counter_register_in <= counter_register -1; end if; end process; flag_register_in <= N2P_empty & P2N_full & "000000000000000000000000000000"; --NI_read_flag <= N2P_empty; --NI_write_flag <= P2N_full; irq_out <= '0'; end; --architecture logic
gpl-3.0
642fb5e21da6ab8ca3b34c8028f98270
0.558499
3.054517
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/SReg.vhd
3
2,127
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity SReg is Generic ( Size : positive := 7); Port ( -- Scan Interface scan_client ---------- SI : in STD_LOGIC; -- ScanInPort SO : out STD_LOGIC; -- ScanOutPort SEL : in STD_LOGIC; -- SelectPort ---------------------------------------- SE : in STD_LOGIC; -- ShiftEnPort CE : in STD_LOGIC; -- CaptureEnPort UE : in STD_LOGIC; -- UpdateEnPort RST : in STD_LOGIC; -- ResetPort TCK : in STD_LOGIC; -- TCKPort DI : in STD_LOGIC_VECTOR (Size-1 downto 0); --DataInPort DO : out STD_LOGIC_VECTOR (Size-1 downto 0)); --DataOutPort end SReg; architecture SReg_arch of SReg is signal SR_so : STD_LOGIC; signal SR_do : STD_LOGIC_VECTOR (Size-1 downto 0); component ScanRegister is Generic (Size : positive; BitOrder : string; -- MSBLSB / LSBMSB SOSource : natural; ResetValue : STD_LOGIC_VECTOR); Port ( SI : in STD_LOGIC; CE : in STD_LOGIC; SE : in STD_LOGIC; UE : in STD_LOGIC; SEL : in STD_LOGIC; RST : in STD_LOGIC; TCK : in STD_LOGIC; SO : out STD_LOGIC; CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0); ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0)); end component; constant ResetValue : STD_LOGIC_VECTOR (Size-1 downto 0) := (others => '0'); -- ResetValue 1'b0 begin SO <= SR_so; -- Source SR DO <= SR_do; -- Source SR SR : ScanRegister Generic map (Size => Size, BitOrder => "MSBLSB", -- MSBLSB / LSBMSB SOSource => 0, -- Source SR[0] ResetValue => ResetValue) Port map ( SI => SI, -- ScanInSource SI CE => CE, SE => SE, UE => UE, SEL => SEL, RST => RST, TCK => TCK, SO => SR_so, CaptureSource => DI, -- CaptureSource DI ScanRegister_out => SR_do); end SReg_arch;
gpl-3.0
03c9d5d5a61c43a7290a5ed1efedf7a9
0.502116
4.154297
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/LBDR_packet_drop_with_checkers_with_FI/LBDR_packet_drop_routing_part_pseudo_checkers.vhd
3
14,131
--Copyright (C) 2016 Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity LBDR_packet_drop_routing_part_pseudo_checkers is generic ( cur_addr_rst: integer := 8; Rxy_rst: integer := 8; Cx_rst: integer := 8; NoC_size: integer := 4 ); port ( empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic; grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; dst_addr: in std_logic_vector(NoC_size-1 downto 0); faulty: in std_logic; Cx: in std_logic_vector(3 downto 0); Rxy: in std_logic_vector(7 downto 0); packet_drop: in std_logic; N1_out, E1_out, W1_out, S1_out: in std_logic; Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic; grants: in std_logic; packet_drop_order: in std_logic; packet_drop_in: in std_logic; -- Checker outputs err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order : out std_logic ); end LBDR_packet_drop_routing_part_pseudo_checkers; architecture behavior of LBDR_packet_drop_routing_part_pseudo_checkers is signal cur_addr: std_logic_vector(NoC_size-1 downto 0); signal Requests_FF: std_logic_vector(4 downto 0); signal Requests_in: std_logic_vector(4 downto 0); signal grant_signals: std_logic_vector(4 downto 0); begin cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length)); Requests_FF <= Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF; Requests_in <= Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in; grant_signals <= grant_N & grant_E & grant_W & grant_S & grant_L; -- Implementing checkers in form of concurrent assignments (combinational assertions) process (flit_type, empty, Requests_FF, Requests_in) begin if (flit_type = "001" and empty = '1' and Requests_FF /= Requests_in) then err_header_empty_Requests_FF_Requests_in <= '1'; else err_header_empty_Requests_FF_Requests_in <= '0'; end if; end process; process (flit_type, empty, grants, Requests_in) begin if (flit_type = "100" and empty = '0' and grants = '1' and Requests_in /= "00000") then err_tail_Requests_in_all_zero <= '1'; else err_tail_Requests_in_all_zero <= '0'; end if; end process; process (flit_type, empty, Requests_FF, Requests_in) begin if (flit_type = "100" and empty = '1' and Requests_FF /= Requests_in) then err_tail_empty_Requests_FF_Requests_in <= '1'; else err_tail_empty_Requests_FF_Requests_in <= '0'; end if; end process; process (flit_type, empty, grants, Requests_FF, Requests_in) begin err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '0'; if (flit_type = "100" and empty = '0' and grants = '0' and Requests_FF /= Requests_in) then err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '1'; end if; end process; process (grant_signals, grants) begin err_grants_onehot <= '0'; if ( (grant_signals = "00001" or grant_signals = "00010" or grant_signals = "00100" or grant_signals = "01000" or grant_signals = "10000") and grants = '0') then err_grants_onehot <= '1'; end if; end process; process (grant_signals, grants) begin err_grants_mismatch <= '0'; if ( grant_signals = "00000" and grants = '1') then err_grants_mismatch <= '1'; end if; end process; process (flit_type, Requests_FF, Requests_in) begin err_header_tail_Requests_FF_Requests_in <= '0'; if (flit_type /= "001" and flit_type /= "100" and Requests_FF /= Requests_in) then err_header_tail_Requests_FF_Requests_in <= '1'; end if; end process; process (cur_addr, dst_addr, N1_out) begin err_dst_addr_cur_addr_N1 <= '0'; if ( dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '0') then err_dst_addr_cur_addr_N1 <= '1'; end if; end process; process (cur_addr, dst_addr, N1_out) begin err_dst_addr_cur_addr_not_N1 <= '0'; if ( dst_addr(NoC_size-1 downto NoC_size/2) >= cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '1') then err_dst_addr_cur_addr_not_N1 <= '1'; end if; end process; process (cur_addr, dst_addr, E1_out) begin err_dst_addr_cur_addr_E1 <= '0'; if ( cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) and E1_out = '0') then err_dst_addr_cur_addr_E1 <= '1'; end if; end process; process (cur_addr, dst_addr, E1_out) begin err_dst_addr_cur_addr_not_E1 <= '0'; if ( cur_addr((NoC_size/2)-1 downto 0) >= dst_addr((NoC_size/2)-1 downto 0) and E1_out = '1') then err_dst_addr_cur_addr_not_E1 <= '1'; end if; end process; process (cur_addr, dst_addr, W1_out) begin err_dst_addr_cur_addr_W1 <= '0'; if ( dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) and W1_out = '0') then err_dst_addr_cur_addr_W1 <= '1'; end if; end process; process (cur_addr, dst_addr, W1_out) begin err_dst_addr_cur_addr_not_W1 <= '0'; if ( dst_addr((NoC_size/2)-1 downto 0) >= cur_addr((NoC_size/2)-1 downto 0) and W1_out = '1') then err_dst_addr_cur_addr_not_W1 <= '1'; end if; end process; process (cur_addr, dst_addr, S1_out) begin err_dst_addr_cur_addr_S1 <= '0'; if ( cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '0') then err_dst_addr_cur_addr_S1 <= '1'; end if; end process; process (cur_addr, dst_addr, S1_out) begin err_dst_addr_cur_addr_not_S1 <= '0'; if ( cur_addr(NoC_size-1 downto NoC_size/2) >= dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '1') then err_dst_addr_cur_addr_not_S1 <= '1'; end if; end process; process (flit_type, empty, dst_addr, cur_addr, Req_L_in) begin err_dst_addr_cur_addr_Req_L_in <= '0'; if ( flit_type = "001" and empty = '0' and dst_addr = cur_addr and Req_L_in = '0') then err_dst_addr_cur_addr_Req_L_in <= '1'; end if; end process; process (flit_type, empty, dst_addr, cur_addr, Req_L_in) begin err_dst_addr_cur_addr_not_Req_L_in <= '0'; if ( flit_type = "001" and empty = '0' and dst_addr /= cur_addr and Req_L_in = '1') then err_dst_addr_cur_addr_not_Req_L_in <= '1'; end if; end process; process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in) begin err_header_not_empty_faulty_drop_packet_in <= '0'; if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and ((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and ((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and ((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and (dst_addr /= cur_addr))) and packet_drop_in = '0') then err_header_not_empty_faulty_drop_packet_in <= '1'; end if; end process; process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in, packet_drop) begin err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '0'; if ( flit_type = "001" and empty = '0' and (faulty = '0' and not (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and ((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and ((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and ((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and (dst_addr /= cur_addr))) and packet_drop_in /= packet_drop) then err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '1'; end if; end process; process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, Requests_in) begin err_header_not_empty_faulty_Req_in_all_zero <= '0'; if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and ((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and ((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and ((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and (dst_addr /= cur_addr))) and Requests_in /= "00000") then err_header_not_empty_faulty_Req_in_all_zero <= '1'; end if; end process; process (flit_type, empty, Req_N_in, N1_out, E1_out, W1_out, Rxy, Cx) begin err_header_not_empty_Req_N_in <= '0'; if ( flit_type = "001" and empty = '0' and Req_N_in /= ( ((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0) ) ) then err_header_not_empty_Req_N_in <= '1'; end if; end process; process (flit_type, empty, Req_E_in, N1_out, E1_out, S1_out, Rxy, Cx) begin err_header_not_empty_Req_E_in <= '0'; if ( flit_type = "001" and empty = '0' and Req_E_in /= ( ((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1) ) ) then err_header_not_empty_Req_E_in <= '1'; end if; end process; process (flit_type, empty, Req_W_in, N1_out, W1_out, S1_out, Rxy, Cx) begin err_header_not_empty_Req_W_in <= '0'; if ( flit_type = "001" and empty = '0' and Req_W_in /= ( ((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2) ) ) then err_header_not_empty_Req_W_in <= '1'; end if; end process; process (flit_type, empty, Req_S_in, E1_out, W1_out, S1_out, Rxy, Cx) begin err_header_not_empty_Req_S_in <= '0'; if ( flit_type = "001" and empty = '0' and Req_S_in /= (((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) ) then err_header_not_empty_Req_S_in <= '1'; end if; end process; process (flit_type, empty, packet_drop_in, packet_drop) begin err_header_empty_packet_drop_in_packet_drop_equal <= '0'; if (flit_type = "001" and empty = '1' and packet_drop_in /= packet_drop ) then err_header_empty_packet_drop_in_packet_drop_equal <= '1'; end if; end process; process (flit_type, empty, packet_drop, packet_drop_in) begin err_tail_not_empty_packet_drop_not_packet_drop_in <= '0'; if (flit_type = "100" and empty = '0' and packet_drop = '1' and packet_drop_in /= '0' ) then err_tail_not_empty_packet_drop_not_packet_drop_in <= '1'; end if; end process; process (flit_type, empty, packet_drop, packet_drop_in) begin err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '0'; if (flit_type = "100" and empty = '0' and packet_drop = '0' and packet_drop_in /= packet_drop ) then err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '1'; end if; end process; process (flit_type, empty, packet_drop_in, packet_drop) begin err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '0'; if ( ((flit_type /= "001" and flit_type /= "100") or empty = '1') and packet_drop_in /= packet_drop ) then err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '1'; end if; end process; process (packet_drop_order, packet_drop) begin err_packet_drop_order <= '0'; if (packet_drop_order /= packet_drop) then err_packet_drop_order <= '1'; end if; end process; end behavior;
gpl-3.0
21a24e774376734f0691a1ebde9631c9
0.607671
2.718546
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Processor_NI/ram_xilinx.vhd
4
181,522
--------------------------------------------------------------------- -- TITLE: Random Access Memory for Xilinx -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 11/06/05 -- FILENAME: ram_xilinx.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements Plasma internal RAM as RAMB for Spartan 3x -- -- Compile the MIPS C and assembly code into "test.axf". -- Run convert.exe to change "test.axf" to "code.txt" which -- will contain the hex values of the opcodes. -- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd", -- to create the "ram_image.vhd" file that will have the opcodes -- correctly placed inside the INIT_00 => strings. -- Then include ram_image.vhd in the simulation/synthesis. -- -- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache -- if the DDR cache is enabled. --------------------------------------------------------------------- -- UPDATED: 09/07/10 Olivier Rinaudo ([email protected]) -- new behaviour: 8KB expandable to 64KB of internal RAM -- -- MEMORY MAP -- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache) -- 2000..3FFF : 8KB 16KB block1 -- 4000..5FFF : 8KB 24KB block2 -- 6000..7FFF : 8KB 32KB block3 -- 8000..9FFF : 8KB 40KB block4 -- A000..BFFF : 8KB 48KB block5 -- C000..DFFF : 8KB 56KB block6 -- E000..FFFF : 8KB 64KB block7 --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use work.mlite_pack.all; library UNISIM; use UNISIM.vcomponents.all; entity ram is generic(memory_type : string := "DEFAULT"; --Number of 8KB blocks of internal RAM, up to 64KB (1 to 8) block_count : integer := 1); port(clk : in std_logic; enable : in std_logic; write_byte_enable : in std_logic_vector(3 downto 0); address : in std_logic_vector(31 downto 2); data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0)); end; --entity ram architecture logic of ram is --type type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0); --Which 8KB block alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13); --Address within a 8KB block (without lower two bits) alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2); --Block enable with 1 bit per memory block signal block_enable: std_logic_vector(7 downto 0); --Block Data Out signal block_do: mem32_vector(7 downto 0); --Remember which block was selected signal block_sel_buf: std_logic_vector(2 downto 0); begin block_enable<= "00000001" when (enable='1') and (block_sel="000") else "00000010" when (enable='1') and (block_sel="001") else "00000100" when (enable='1') and (block_sel="010") else "00001000" when (enable='1') and (block_sel="011") else "00010000" when (enable='1') and (block_sel="100") else "00100000" when (enable='1') and (block_sel="101") else "01000000" when (enable='1') and (block_sel="110") else "10000000" when (enable='1') and (block_sel="111") else "00000000"; proc_blocksel: process (clk, block_sel) is begin if rising_edge(clk) then block_sel_buf <= block_sel; end if; end process; proc_do: process (block_do, block_sel_buf) is begin data_read <= block_do(conv_integer(block_sel_buf)); end process; -- BLOCKS generation block0: if (block_count > 0) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(0)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(0), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(0)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(0), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(0)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(0), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(0)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(0), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block0 block1: if (block_count > 1) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(1)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(1), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(1)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(1), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(1)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(1), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(1)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(1), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block1 block2: if (block_count > 2) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(2)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(2), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(2)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(2), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(2)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(2), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(2)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(2), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block2 block3: if (block_count > 3) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(3)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(3), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(3)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(3), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(3)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(3), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(3)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(3), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block3 block4: if (block_count > 4) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(4)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(4), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(4)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(4), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(4)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(4), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(4)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(4), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block4 block5: if (block_count > 5) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(5)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(5), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(5)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(5), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(5)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(5), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(5)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(5), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block5 block6: if (block_count > 6) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(6)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(6), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(6)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(6), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(6)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(6), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(6)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(6), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block6 block7: if (block_count > 7) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(7)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(7), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(7)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(7), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(7)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(7), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(7)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(7), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block7 end; --architecture logic
gpl-3.0
b234aae7c786144b473a7957ea522874
0.842906
6.992104
false
false
false
false
kiwih/subleq-vhdl
single_port_memfile.vhd
1
1,120
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --comment to go here entity single_port_memfile is generic( ADDR_WIDTH : integer := 4; DATA_WIDTH : integer := 16; MEM_LENGTH : integer := 128 ); port( CLK: in std_logic; WRITE_EN: in std_logic; ADDR: in std_logic_vector(ADDR_WIDTH - 1 downto 0); DATA_IN: in std_logic_vector(DATA_WIDTH - 1 downto 0); DATA_OUT: out std_logic_vector(DATA_WIDTH - 1 downto 0) ); end entity; architecture beh of single_port_memfile is type memory_type is array(0 to MEM_LENGTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0); signal memory : memory_type := ( 0 => x"01F001", 1 => x"000002", 2 => x"02F004", 3 => x"000002", 4 => x"000000", -- 0 => x"000001", -- 1 => x"000002", -- 2 => x"000003", -- 3 => x"000004", -- 4 => x"000005", -- 5 => x"000000", others => (others => '0') ); begin process(CLK) begin if rising_edge(CLK) then if WRITE_EN = '1' then memory(to_integer(unsigned(ADDR))) <= DATA_IN; end if; end if; end process; DATA_OUT <= memory(to_integer(unsigned(ADDR))); end architecture beh;
mit
56a68247d587ca38318a4a3af0e86593
0.623214
2.604651
false
false
false
false
FlatTargetInk/Spartan-HW
rotary_debounce.vhd
1
1,593
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12:52:06 04/28/2017 -- Design Name: -- Module Name: rotary_debounce - Structural -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity rotary_debounce is Port( CLK : in STD_LOGIC; EN : in STD_LOGIC; ROTIN : in STD_LOGIC_VECTOR(1 downto 0); ROUT : out STD_LOGIC_VECTOR(1 downto 0)); end rotary_debounce; architecture Structural of rotary_debounce is signal DEBOUNCED : STD_LOGIC_VECTOR(1 downto 0); begin ----> Debounce input <---- ROT_0: entity work.debounce generic map(wait_time => 15) port map(CLK => CLK, EN => EN, INPUT => ROTIN(0), OUTPUT => DEBOUNCED(0)); ROT_1: entity work.debounce generic map(wait_time => 15) port map(CLK => CLK, EN => EN, INPUT => ROTIN(1), OUTPUT => DEBOUNCED(1)); ----> Change state <---- the_wankel: entity work.rotary_machine port map(EN => EN, INS => DEBOUNCED, DIR => ROUT); end Structural;
mit
d5fddbf23475659a9e8c551353902859
0.58506
3.455531
false
false
false
false
ashtonchase/logic_analyzer
src/capture_ctrl_e.vhd
1
6,925
------------------------------------------------------------------------------- -- Title : Logic Analzyer Data Capture Controller Entity -- Project : fpga_logic_analyzer ------------------------------------------------------------------------------- -- File : la_ctrl_e.vhd -- Created : 2016-02-22 -- Last update: 2016-04-10 -- Standard : VHDL'08 ------------------------------------------------------------------------------- -- SUMMARY: This entity module is the primary capture controller of the -- Logic Analyzer. It responsible for matching the trigger mask to the sampled -- data bus, and the passing the requested amount of data out. -- -- FUNCTIONAL DESCRIPTION: -- Upon startup/reset, the controll will wait until the downstream fifo is -- ready by the asserted fifo_tready before proceeding. Once the fifo is ready, -- the capture_rdy flag will be asserted. In this state, the controller is -- continuously reading the parallel triggere mask, trigger value, number of -- read counts and number of delay counts on the inputs. When the arm command -- it asserted, these values will be locked in and the ARMED signal will be -- asserted for the remained of the capture cycle. Once ARMED, the data input -- (din) will be masked and compared against a the masked trigger values. If -- there is a match, the controller will either delay for the specified number -- of delay cycles (delay_cnt_4x) or start capturing data. Data will be captured -- for the specified depth (ready_cnt_4x). -- -- SAMPLE RATE CONTROL: -- During the delay and capture cycles, valid capture cycles will occur when -- sample_enable is asserted, otherwise the sampled data is not flaged as valid. -- This allowed for a divided sample rate. -- -- FIFO Interface: -- Capured data is deliverd via the output fifo inteface, based upon the -- AXI-Stream standard. Input sample data is continuously pulled from din -- and placed on fifo_tdata. Fifo_tvalid indicates is that data should be -- stored/transmitted as valid data. This allows for minimized logic around -- the datapath through this module. fifo_tlast will be assered on the last -- cycle of valid sampled data. -- NOTE: fifo_tready is only monitored at the start of the capture process. -- It is checked at the start to make sure that the fifo is ready before data -- is attempted to be sampled. Traditionally with an AXI-Stream interface a -- valid transaction occurs when tvalid and tready are both asserted for a -- give clock cycle; however, since the input data can't be paused, the -- capture controller must pass the data ever valid cycle of the triggered process. -------------------------------------------------------I------------------------ -- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt ------------------------------------------------------------------------------- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-02-22 1.0 ashton Created ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY capture_ctrl IS GENERIC ( DATA_WIDTH : POSITIVE RANGE 1 TO 32 := 8); PORT ( --top level interafaces clk : IN STD_LOGIC; -- Clock rst : IN STD_LOGIC := '0'; -- syncronous reset din : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); -- input channels --status indicators armed : OUT STD_LOGIC; --latched indicator when armed. triggered : OUT STD_LOGIC; --latched indicator when triggerd. ------message processing interfaces --serially received reset command. one clock cycle required rst_cmd : IN STD_LOGIC := '0'; --serially received arm command. one clock cycle required. arm_cmd : IN STD_LOGIC; --command to send out a predeterminged ID word id_cmd : in STD_LOGIC; --debug command debug_cmd : in STD_LOGIC; --sample enable trigger. for subsampling data. sample_enable : IN STD_LOGIC := '1'; --send a reset pulse to the sample rate clock sample_cnt_rst : OUT STD_LOGIC; --number of sample_rate cycles to delay captureing data after trigger has occured. delay_cnt_4x : IN STD_LOGIC_VECTOR(16-1 DOWNTO 0) := (OTHERS => '0'); --number of samples to read, times four. max==262,140 samples read_cnt_4x : IN STD_LOGIC_VECTOR(16-1 DOWNTO 0) := (OTHERS => '1'); --parallel trigger bit mask for par_trig_val. latched in on arm_cmd par_trig_msk : IN STD_LOGIC_VECTOR(32-1 DOWNTO 0) := (OTHERS => '0'); --parallel triger values, latched in on arm_cmd par_trig_val : IN STD_LOGIC_VECTOR(32-1 DOWNTO 0) := (OTHERS => '1'); --ready_to_arm indicator capture_rdy : OUT STD_LOGIC; --fifo interface fifo_tdata : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0); --captured --data output fifo_tvalid : OUT STD_LOGIC; -- indicating tdata has valid data fifo_tlast : OUT STD_LOGIC; -- no planned usage fifo_tready : IN STD_LOGIC := '1'; -- only used on initial setup fifo_tfull : IN STD_LOGIC := '0'; --no intended use fifo_tempty : IN STD_LOGIC := '1'; --needs to control capture_rdy fifo_aresetn : OUT STD_LOGIC; --used to flush fifo in reset cmd. --dummy placeholder placeholder : IN STD_LOGIC := '0' ); BEGIN ----------------------------------------------------------------------------- -- Architecture Independent Port Assertions ----------------------------------------------------------------------------- --confirm clk is connected ASSERT IS_X(clk) = FALSE REPORT "clock is undefined" SEVERITY ERROR; PROCESS (clk) IS BEGIN -- PROCESS IF rising_edge(clk) THEN -- rising clock edge --cofirm arm_cmd is connected ASSERT IS_X(arm_cmd) = FALSE REPORT "arm_cmd is undefined" SEVERITY ERROR; END IF; END PROCESS; END ENTITY capture_ctrl; --See capture_ctrl_a for architecture
gpl-2.0
35fe9221895179b6753065b52f3714d3
0.611986
4.402416
false
false
false
false
FlatTargetInk/Spartan-HW
rotary_machine.vhd
1
1,934
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:25:58 04/28/2017 -- Design Name: -- Module Name: rotary_machine - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity rotary_machine is Port( EN : in STD_LOGIC; INS : in STD_LOGIC_VECTOR(1 downto 0); -- 1->A, 0->B DIR : out STD_LOGIC_VECTOR(1 downto 0)); -- Event shown by transition end rotary_machine; architecture Behavioral of rotary_machine is type STATE_TYPE IS (IDLE, RISING_LEFT, RISING_RIGHT); signal cur_state : STATE_TYPE; --signal next_state : STATE_TYPE; signal OUTBUF : STD_LOGIC_VECTOR(1 downto 0) := (OTHERS => '0'); begin DIR <= OUTBUF; change_state: process(INS) begin -- if (INS'event) --and (EN = '1') -- then case cur_state is when RISING_LEFT => if (INS = "11") then OUTBUF(1) <= not OUTBUF(1); end if; cur_state <= IDLE; when RISING_RIGHT => if (INS = "11") then OUTBUF(0) <= not OUTBUF(0); end if; cur_state <= IDLE; when IDLE => case INS is when "10" => cur_state <= RISING_LEFT; when "01" => cur_state <= RISING_RIGHT; when others => cur_state <= IDLE; end case; end case; --cur_state <= next_state; -- end if; end process; end Behavioral; -- vim:set ts=3 sw=3 noexpandtab:
mit
514c53e01f651e752be2fa01024f32f8
0.577042
3.334483
false
false
false
false
AndyMcC0/UVVM_All
bitvis_vip_axistream/src/axistream_vvc.vhd
1
21,985
--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <[email protected]>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library uvvm_util; context uvvm_util.uvvm_util_context; library uvvm_vvc_framework; use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all; use work.axistream_bfm_pkg.all; use work.vvc_methods_pkg.all; -- shared_axistream_vvc_config use work.vvc_cmd_pkg.all; use work.td_target_support_pkg.all; use work.td_vvc_entity_support_pkg.all; use work.td_cmd_queue_pkg.all; use work.td_result_queue_pkg.all; --======================================================================================================================== entity axistream_vvc is generic ( -- When true: This VVC is an AXI4 Stream master. Data is output from BFM. -- When false: This VVC is an AXI4 Stream slave. Data is input to BFM. GC_VVC_IS_MASTER : boolean; GC_DATA_WIDTH : integer; GC_USER_WIDTH : integer := 1; -- (Note: STRB_WIDTH = DATA_WIDTH/8) GC_ID_WIDTH : integer := 1; GC_DEST_WIDTH : integer := 1; GC_INSTANCE_IDX : natural; GC_PACKETINFO_QUEUE_COUNT_MAX : natural := 1; -- Number of PacketInfo Queues, normally one per source VVC GC_AXISTREAM_BFM_CONFIG : t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT; GC_CMD_QUEUE_COUNT_MAX : natural := 1000; GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950; GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning; GC_RESULT_QUEUE_COUNT_MAX : natural := 1000; GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950; GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING ); port ( clk : in std_logic; axistream_vvc_if : inout t_axistream_if := init_axistream_if_signals(GC_VVC_IS_MASTER, GC_DATA_WIDTH, GC_USER_WIDTH, GC_ID_WIDTH, GC_DEST_WIDTH) ); begin -- Check the interface widths to assure that the interface was correctly set up assert (axistream_vvc_if.tdata'length = GC_DATA_WIDTH) report "axistream_vvc_if.data'length =/ GC_DATA_WIDTH" severity failure; end entity axistream_vvc; --======================================================================================================================== --======================================================================================================================== architecture behave of axistream_vvc is constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX); constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA); signal executor_is_busy : boolean := false; signal queue_is_increasing : boolean := false; signal last_cmd_idx_executed : natural := 0; signal terminate_current_cmd : t_flag_record; -- Instantiation of the element dedicated Queue shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue; shared variable result_queue : work.td_result_queue_pkg.t_generic_queue; alias vvc_config : t_vvc_config is shared_axistream_vvc_config(GC_INSTANCE_IDX); alias vvc_status : t_vvc_status is shared_axistream_vvc_status(GC_INSTANCE_IDX); alias transaction_info : t_transaction_info is shared_axistream_transaction_info(GC_INSTANCE_IDX); begin --======================================================================================================================== -- Constructor -- - Set up the defaults and show constructor if enabled --======================================================================================================================== work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_AXISTREAM_BFM_CONFIG, GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY, GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY); --======================================================================================================================== --======================================================================================================================== -- Command interpreter -- - Interpret, decode and acknowledge commands from the central sequencer --======================================================================================================================== cmd_interpreter : process variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT; begin -- 0. Initialize the process prior to first command work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion); -- initialise shared_vvc_last_received_cmd_idx for channel and instance shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0; -- Then for every single command from the sequencer loop -- basically as long as new commands are received -- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable) -- releases global semaphore ------------------------------------------------------------------------- work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, shared_vvc_cmd, v_local_vvc_cmd); v_cmd_has_been_acked := false; -- Clear flag -- update shared_vvc_last_received_cmd_idx with received command index shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx; -- 2a. Put command on the queue if intended for the executor ------------------------------------------------------------------------- if v_local_vvc_cmd.command_type = QUEUED then work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing); -- 2b. Otherwise command is intended for immediate response ------------------------------------------------------------------------- elsif v_local_vvc_cmd.command_type = IMMEDIATE then case v_local_vvc_cmd.operation is when AWAIT_COMPLETION => work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed); when AWAIT_ANY_COMPLETION => if not v_local_vvc_cmd.gen_boolean then -- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx); v_cmd_has_been_acked := true; end if; work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion); when DISABLE_LOG_MSG => uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE); when ENABLE_LOG_MSG => uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE); when FLUSH_COMMAND_QUEUE => work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS); when TERMINATE_CURRENT_COMMAND => work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd); when FETCH_RESULT => work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response); when others => tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE); end case; else tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE); end if; -- 3. Acknowledge command after running or queuing the command ------------------------------------------------------------------------- if not v_cmd_has_been_acked then work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx); end if; end loop; end process; --======================================================================================================================== --======================================================================================================================== -- Command executor -- - Fetch and execute the commands --======================================================================================================================== cmd_executor : process variable v_cmd : t_vvc_cmd_record; variable v_result : t_vvc_result; -- See vvc_cmd_pkg variable v_timestamp_start_of_current_bfm_access : time := 0 ns; variable v_timestamp_start_of_last_bfm_access : time := 0 ns; variable v_timestamp_end_of_last_bfm_access : time := 0 ns; variable v_command_is_bfm_access : boolean; begin -- 0. Initialize the process prior to first command ------------------------------------------------------------------------- work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd); loop -- 1. Set defaults, fetch command and log ------------------------------------------------------------------------- work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS); -- Reset the transaction info for waveview --transaction_info := C_TRANSACTION_INFO_DEFAULT; transaction_info.operation := v_cmd.operation; transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length); -- Check if command is a BFM access if v_cmd.operation = TRANSMIT or v_cmd.operation = RECEIVE or v_cmd.operation = EXPECT then v_command_is_bfm_access := true; else v_command_is_bfm_access := false; end if; -- Insert delay if needed work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config, command_is_bfm_access => v_command_is_bfm_access, timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access, timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access); if v_command_is_bfm_access then v_timestamp_start_of_current_bfm_access := now; end if; log(ID_BFM, "Running : " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd) & ".", C_SCOPE, vvc_config.msg_id_panel); -- 2. Execute the fetched command ------------------------------------------------------------------------- case v_cmd.operation is -- Only operations in the dedicated record are relevant -- VVC dedicated operations --=================================== when TRANSMIT => check_value(GC_VVC_IS_MASTER, true, TB_ERROR, "Sanity check: Method call only makes sense for master (source) VVC", C_SCOPE, ID_NEVER); -- Put in queue so that the monitor VVC knows what to expect -- Needed when the sink is in Monitor Mode, as an alternative to calling lbusExpect() for each packet transaction_info.numPacketsSent := transaction_info.numPacketsSent + 1; -- Call the corresponding procedure in the BFM package. axistream_transmit( data_array => v_cmd.data_array(0 to v_cmd.data_array_length-1), user_array => v_cmd.user_array(0 to v_cmd.user_array_length-1), strb_array => v_cmd.strb_array(0 to v_cmd.strb_array_length-1), id_array => v_cmd.id_array(0 to v_cmd.id_array_length-1), dest_array => v_cmd.dest_array(0 to v_cmd.dest_array_length-1), msg => format_msg(v_cmd), clk => clk, -- Using the non-record version to avoid fatal error in Modelsim: (SIGSEGV) Bad handle or reference axistream_if_tdata => axistream_vvc_if.tdata, axistream_if_tkeep => axistream_vvc_if.tkeep, axistream_if_tuser => axistream_vvc_if.tuser, axistream_if_tstrb => axistream_vvc_if.tstrb, axistream_if_tid => axistream_vvc_if.tid, axistream_if_tdest => axistream_vvc_if.tdest, axistream_if_tvalid => axistream_vvc_if.tvalid, axistream_if_tlast => axistream_vvc_if.tlast, axistream_if_tready => axistream_vvc_if.tready, scope => C_SCOPE, msg_id_panel => vvc_config.msg_id_panel, config => vvc_config.bfm_config); when RECEIVE => axistream_receive(data_array => v_result.data_array, data_length => v_result.data_length, user_array => v_result.user_array, strb_array => v_result.strb_array, id_array => v_result.id_array, dest_array => v_result.dest_array, msg => format_msg(v_cmd), clk => clk, -- Using the non-record version to avoid fatal error in Questa: (SIGSEGV) Bad handle or reference axistream_if_tdata => axistream_vvc_if.tdata, axistream_if_tkeep => axistream_vvc_if.tkeep, axistream_if_tuser => axistream_vvc_if.tuser, axistream_if_tstrb => axistream_vvc_if.tstrb, axistream_if_tid => axistream_vvc_if.tid, axistream_if_tdest => axistream_vvc_if.tdest, axistream_if_tvalid => axistream_vvc_if.tvalid, axistream_if_tlast => axistream_vvc_if.tlast, axistream_if_tready => axistream_vvc_if.tready, scope => C_SCOPE, msg_id_panel => vvc_config.msg_id_panel, config => vvc_config.bfm_config); -- Store the result work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue, cmd_idx => v_cmd.cmd_idx, result => v_result ); when EXPECT => -- Call the corresponding procedure in the BFM package. axistream_expect( exp_data_array => v_cmd.data_array(0 to v_cmd.data_array_length-1), exp_user_array => v_cmd.user_array(0 to v_cmd.user_array_length-1), exp_strb_array => v_cmd.strb_array(0 to v_cmd.strb_array_length-1), exp_id_array => v_cmd.id_array(0 to v_cmd.id_array_length-1), exp_dest_array => v_cmd.dest_array(0 to v_cmd.dest_array_length-1), msg => format_msg(v_cmd), clk => clk, -- Using the non-record version to avoid fatal error in Questa: (SIGSEGV) Bad handle or reference axistream_if_tdata => axistream_vvc_if.tdata, axistream_if_tkeep => axistream_vvc_if.tkeep, axistream_if_tuser => axistream_vvc_if.tuser, axistream_if_tstrb => axistream_vvc_if.tstrb, axistream_if_tid => axistream_vvc_if.tid, axistream_if_tdest => axistream_vvc_if.tdest, axistream_if_tvalid => axistream_vvc_if.tvalid, axistream_if_tlast => axistream_vvc_if.tlast, axistream_if_tready => axistream_vvc_if.tready, alert_level => v_cmd.alert_level, scope => C_SCOPE, msg_id_panel => vvc_config.msg_id_panel, config => vvc_config.bfm_config); -- UVVM common operations --=================================== when INSERT_DELAY => log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel); if v_cmd.gen_integer_array(0) = -1 then -- Delay specified using time wait until terminate_current_cmd.is_active = '1' for v_cmd.delay; else -- Delay specified using integer wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period; end if; when others => tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE); end case; if v_command_is_bfm_access then v_timestamp_end_of_last_bfm_access := now; v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access; if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and ((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " & to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE); end if; end if; -- Reset terminate flag if any occurred if (terminate_current_cmd.is_active = '1') then log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, vvc_config.msg_id_panel); uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd); end if; last_cmd_idx_executed <= v_cmd.cmd_idx; -- Reset the transaction info for waveview transaction_info := C_TRANSACTION_INFO_DEFAULT; end loop; end process; --======================================================================================================================== --======================================================================================================================== -- Command termination handler -- - Handles the termination request record (sets and resets terminate flag on request) --======================================================================================================================== cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset --======================================================================================================================== end behave;
mit
dbe24c9d6df10580fe4f0675467cc147
0.500932
4.538604
false
true
false
false
SKravitsky/ECEC412
EXMEMRegister.vhd
1
1,482
library ieee; use ieee.std_logic_1164.all; entity EXMEMRegister is port( clk, BranchIn, MemWriteIn, MemReadIn, MemtoRegIn, RegWriteIn, ZeroIn: in std_logic; WriteRegisterIn: in std_logic_vector(4 downto 0); AddressIn, ALUResultIn, WriteDataIn: in std_logic_vector(31 downto 0); BranchOut, MemWriteOut, MemReadOut, MemtoRegOut, RegWriteOut, ZeroOut: out std_logic; WriteRegisterOut: out std_logic_vector(4 downto 0); AddressOut, ALUResultOut, WriteDataOut: out std_logic_vector(31 downto 0) ); end EXMEMRegister; architecture Structural of EXMEMRegister is signal Branch, MemWrite, MemRead, MemtoReg, RegWrite, Zero: std_logic := '0'; signal WriteRegister: std_logic_vector(4 downto 0) := "00000"; signal Address, ALUResult, WriteData: std_logic_vector(31 downto 0) := X"00000000"; begin AddressOut <= Address; BranchOut <= Branch; MemWriteOut <= MemWrite; MemReadOut <= MemRead; MemtoRegOut <= MemtoReg; RegWriteOut <= RegWrite; ZeroOut <= Zero; WriteRegisterOut <= WriteRegister; WriteDataOut <= WriteData; ALUResultOut <= ALUResult; process(clk) begin if rising_edge(clk) then Address <= AddressIn; Branch <= BranchIn; MemWrite <= MemWriteIn; MemRead <= MemReadIn; MemtoReg <= MemtoRegIn; RegWrite <= RegWriteIn; Zero <= ZeroIn; WriteRegister <= WriteRegisterIn; WriteData <= WriteDataIn; ALUResult <= ALUResultIn; end if; end process; end Structural;
apache-2.0
6abf381e20d756633f71e705583594c3
0.703779
4.093923
false
false
false
false
simoesusp/Processador-ICMC
Software_Assembly/IR_Controller/Processor_IR_PWM_DE2_70/AP9_cpu.vhd
2
32,012
--------------------------------------------------- --apx-arch ap9 micro-processor--------------------- --16-bits width bus-------------------------------- --external clock----------------------------------- --builded by microenix, cOPyright (r) 2011--------- --for detailed description about this-------------- --architechture, please refer to the ap9 reference-- --manual.------------------------------------------ --------------------------------------------------- libraRY ieee; use ieee.std_LOGIC_1164.all; use ieee.std_LOGIC_ARITH.all; use ieee.std_LOGIC_unsigned.all; entity AP9_cpu is port( clk : in std_LOGIC; reset : in std_LOGIC; Mem : in STD_LOGIC_VECTOR(15 downto 0); M5 : out STD_LOGIC_VECTOR(15 downto 0); M1 : out STD_LOGIC_VECTOR(15 downto 0); RW : out std_LOGIC; key : in STD_LOGIC_VECTOR(7 downto 0); videoflag : out std_LOGIC; vga_pos : out STD_LOGIC_VECTOR(15 downto 0); vga_char : out STD_LOGIC_VECTOR(15 downto 0); Ponto : out STD_LOGIC_VECTOR(2 downto 0); halt_ack : out std_LOGIC; halt_req : in std_LOGIC; PC_data : out STD_LOGIC_VECTOR(15 downto 0) ); end AP9_cpu; ARCHITECTURE main of AP9_cpu is TYPE STATES is (fetch, decode, exec, halted); -- Estados da Maquina de Controle do Processador TYPE Registers is array(0 to 7) of STD_LOGIC_VECTOR(15 downto 0); -- Banco de Registradores TYPE LoadRegisters is array(0 to 7) of std_LOGIC; -- Sinais de LOAD dos Registradores do Banco -- INSTRUCTION SET: 29 INSTRUCTIONS -- Data Manipulation Instructions: -- Usage -- Action -- Format CONSTANT LOAD : STD_LOGIC_VECTOR(5 downto 0) := "110000"; -- LOAD RX END -- RX <- M[END] Format: < inst(6) | RX(3) | xxxxxxx > + 16bit END CONSTANT STORE : STD_LOGIC_VECTOR(5 downto 0) := "110001"; -- STORE END RX -- M[END] <- RX Format: < inst(6) | RX(3) | xxxxxxx > + 16bit END CONSTANT LOADIMED : STD_LOGIC_VECTOR(5 downto 0) := "111000"; -- LOADN RX Nr -- RX <- Nr Format: < inst(6) | RX(3) | xxxxxxb0 > + 16bit Numero CONSTANT LOADINDEX : STD_LOGIC_VECTOR(5 downto 0) := "111100"; -- LOADI RX RY -- RX <- M[RY] Format: < inst(6) | RX(3) | RY(3) | xxxx > CONSTANT STOREINDEX : STD_LOGIC_VECTOR(5 downto 0) := "111101"; -- STOREI RX RY -- M[RX] <- RY Format: < inst(6) | RX(3) | RY(3) | xxxx > CONSTANT MOV : STD_LOGIC_VECTOR(5 downto 0) := "110011"; -- MOV RX RY -- RX <- RY Format: < inst(6) | RX(3) | RY(3) | xx | x0 > -- MOV RX SP RX <- SP Format: < inst(6) | RX(3) | xxx | xx | 01 > -- MOV SP RX SP <- RX Format: < inst(6) | RX(3) | xxx | xx | 11 > -- I/O Instructions: CONSTANT OUTCHAR : STD_LOGIC_VECTOR(5 downto 0) := "110010"; -- OUTCHAR RX RY -- Video[RY] <- Char(RX) Format: < inst(6) | RX(3) | RY(3) | xxxx > CONSTANT INCHAR : STD_LOGIC_VECTOR(5 downto 0) := "110101"; -- INCHAR RX -- RX[5..0] <- KeyPressed RX[15..6] <- 0's Format: < inst(6) | RX(3) | xxxxxxx > -- Se nao pressionar nenhuma tecla, RX recebe 00FF CONSTANT ARITH : STD_LOGIC_VECTOR(1 downto 0) := "10"; -- Aritmethic Instructions(All should begin wiht "10"): CONSTANT ADD : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- ADD RX RY RZ / ADDC RX RY RZ -- RX <- RY + RZ / RX <- RY + RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C > CONSTANT SUB : STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- SUB RX RY RZ / SUBC RX RY RZ -- RX <- RY - RZ / RX <- RY - RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C > CONSTANT MULT : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- MUL RX RY RZ / MUL RX RY RZ -- RX <- RY * RZ / RX <- RY * RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C > CONSTANT DIV : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- DIV RX RY RZ -- RX <- RY / RZ / RX <- RY / RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C > CONSTANT INC : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- INC RX / DEC RX -- RX <- RX + 1 / RX <- RX - 1 -- b6= INC/DEC : 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx > CONSTANT LMOD : STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- MOD RX RY RZ -- RX <- RY MOD RZ Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x > CONSTANT LOGIC : STD_LOGIC_VECTOR(1 downto 0) := "01"; -- LOGIC Instructions (All should begin wiht "01"): CONSTANT LAND : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- AND RX RY RZ -- RZ <- RX AND RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x > CONSTANT LOR : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- OR RX RY RZ -- RZ <- RX OR RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x > CONSTANT LXOR : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- XOR RX RY RZ -- RZ <- RX XOR RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x > CONSTANT LNOT : STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- NOT RX RY -- RX <- NOT(RY) Format: < inst(6) | RX(3) | RY(3) | xxxx > CONSTANT SHIFT : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- SHIFTL0 RX,n / SHIFTL1 RX,n / SHIFTR0 RX,n / SHIFTR1 RX,n / ROTL RX,n / ROTR RX,n -- SHIFT/Rotate RX -- b6=shif/rotate: 0/1 b5=left/right: 0/1; b4=fill; -- Format: < inst(6) | RX(3) | b6 b5 b4 | nnnn > CONSTANT CMP : STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- CMP RX RY -- Compare RX and RY and set FR : Format: < inst(6) | RX(3) | RY(3) | xxxx > Flag Register: <...DIVbyZero|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater> -- JMP Condition: (UNconditional, EQual, Not Equal, Zero, Not Zero, CarRY, Not CarRY, GReater, LEsser, Equal or Greater, Equal or Lesser, OVerflow, Not OVerflow, Negative, DIVbyZero, NOT USED) -- FLOW CONTROL Instructions: CONSTANT JMP : STD_LOGIC_VECTOR(5 downto 0) := "000010"; -- JMP END -- PC <- 16bit END : b9-b6 = COND Format: < inst(6) | COND(4) | xxxxxx > + 16bit END CONSTANT CALL : STD_LOGIC_VECTOR(5 downto 0) := "000011"; -- CALL END -- M[SP] <- PC | SP-- | PC <- 16bit END : b9-b6 = COND Format: < inst(6) | COND(4) | xxxxxx > + 16bit END CONSTANT RTS : STD_LOGIC_VECTOR(5 downto 0) := "000100"; -- RTS -- SP++ | PC <- M[SP] | b6=RX/FR: 1/0 Format: < inst(6) | xxxxxxxxxx > CONSTANT PUSH : STD_LOGIC_VECTOR(5 downto 0) := "000101"; -- PUSH RX / PUSH FR -- M[SP] <- RX / M[SP] <- FR | SP-- : b6=RX/FR: 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx > CONSTANT POP : STD_LOGIC_VECTOR(5 downto 0) := "000110"; -- POP RX / POP FR -- SP++ | RX <- M[SP] / FR <- M[SP] : b6=RX/FR: 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx > -- Control Instructions: CONSTANT NOP : STD_LOGIC_VECTOR(5 downto 0) := "000000"; -- NOP -- Do Nothing Format: < inst(6) | xxxxxxxxxx > CONSTANT HALT : STD_LOGIC_VECTOR(5 downto 0) := "001111"; -- HALT -- StOP Here Format: < inst(6) | xxxxxxxxxx > CONSTANT SETC : STD_LOGIC_VECTOR(5 downto 0) := "001000"; -- CLEARC / SETC -- Set/Clear CarRY: b9 = 1-set; 0-clear Format: < inst(6) | b9 | xxxxxxxxx > CONSTANT BREAKP : STD_LOGIC_VECTOR(5 downto 0) := "001110"; -- BREAK POINT -- Switch to manual clock Format: < inst(6) | xxxxxxxxxx > -- CONSTANTes para controle do Mux2 CONSTANT sULA : STD_LOGIC_VECTOR (2 downto 0) := "000"; CONSTANT sMem : STD_LOGIC_VECTOR (2 downto 0) := "001"; CONSTANT sM4 : STD_LOGIC_VECTOR (2 downto 0) := "010"; CONSTANT skey : STD_LOGIC_VECTOR (2 downto 0) := "011"; --CONSTANT sTECLADO : STD_LOGIC_VECTOR (2 downto 0) := "011"; CONSTANT sSP : STD_LOGIC_VECTOR (2 downto 0) := "100"; -- CONSTANTes para controle do Mux2 -- CONSTANT sULA : STD_LOGIC_VECTOR(1 downto 0) := "00"; -- CONSTANT sMem : STD_LOGIC_VECTOR(1 downto 0) := "01"; -- CONSTANT sM4 : STD_LOGIC_VECTOR(1 downto 0) := "10"; -- CONSTANT skey : STD_LOGIC_VECTOR(1 downto 0) := "11"; -- Sinais para o Processo da ULA signal OP : STD_LOGIC_VECTOR(6 downto 0); -- OP(6) deve ser setado para OPeracoes com carRY signal x, y, result : STD_LOGIC_VECTOR(15 downto 0); signal FR : STD_LOGIC_VECTOR(15 downto 0); -- Flag Register: <...DIVbyZero|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater> signal auxFR : STD_LOGIC_VECTOR(15 downto 0); -- Representa um barramento conectando a ULA ao Mux6 para escrever no FR begin -- Maquina de Controle process(clk, reset) --Register Declaration: variable PC : STD_LOGIC_VECTOR(15 downto 0); -- Program Counter variable IR : STD_LOGIC_VECTOR(15 downto 0); -- Instruction Register variable SP : STD_LOGIC_VECTOR(15 downto 0); -- Stack Pointer variable MAR : STD_LOGIC_VECTOR(15 downto 0); -- Memory address Register --VARIABLE TECLADO :STD_LOGIC_VECTOR(15 downto 0); -- Registrador para receber dados do teclado variable reg : Registers; -- Mux dos barramentos de dados internos VARIABLE M2 :STD_LOGIC_VECTOR(15 downto 0); -- Mux dos barramentos de dados internos para os Registradores VARIABLE M3, M4 :STD_LOGIC_VECTOR(15 downto 0); -- Mux dos Registradores para as entradas da ULA -- Novos Sinais da V2 variable LoadReg : LoadRegisters; variable LoadIR : std_LOGIC; variable LoadMAR : std_LOGIC; variable LoadPC : std_LOGIC; variable IncPC : std_LOGIC; VARIABLE LoadSP : STD_LOGIC; variable IncSP : std_LOGIC; variable DecSP : std_LOGIC; variable selM2 : STD_LOGIC_VECTOR(2 downto 0); -- VARIABLE selM2 :STD_LOGIC_VECTOR (2 downto 0); variable selM6 : STD_LOGIC_VECTOR(2 downto 0); -- VARIABLE selM6 :STD_LOGIC_VECTOR (2 downto 0); VARIABLE BreakFlag : STD_LOGIC; variable state : STATES; variable RX : integer; variable RY : integer; variable RZ : integer; begin if(reset = '1') then state := fetch; M1(15 downto 0) <= x"0000"; videoflag <= '0'; RX := 0; RY := 0; RZ := 0; RW <= '0'; LoadIR := '0'; LoadMAR := '0'; LoadPC := '0'; IncPC := '0'; IncSP := '0'; DecSP := '0'; selM2 := sMem; selM6 := sULA; LoadReg(0) := '0'; LoadReg(1) := '0'; LoadReg(2) := '0'; LoadReg(3) := '0'; LoadReg(4) := '0'; LoadReg(5) := '0'; LoadReg(6) := '0'; LoadReg(7) := '0'; REG(0) := x"0000"; REG(1) := x"0000"; REG(2) := x"0000"; REG(3) := x"0000"; REG(4) := x"0000"; REG(5) := x"0000"; REG(6) := x"0000"; REG(7) := x"0000"; PC := x"0000"; SP := x"3ffc"; -- 7ffc IR := x"0000"; MAR := x"0000"; -- TECLADO := x"0000"; BreakFlag:= '0'; -- Break Point Flag --BREAK <= '0'; -- Break Point output to switch to manual clock -- nao tinha HALT_ack <= '0'; elsif(clk'event and clk = '1') then if(LoadIR = '1') then IR := Mem; end if; if(LoadPC = '1') then PC := Mem; end if; if(IncPC = '1') then PC := PC + x"0001"; end if; if(LoadMAR = '1') then MAR := Mem; end if; if(LoadSP = '1') then SP := M3; end if; if(IncSP = '1') then SP := SP + x"0001"; end if; if(DecSP = '1') then SP := SP - x"0001"; end if; -- Selecao do Mux6 if (selM6 = sULA) THEN FR <= auxFR; -- Sempre recebe flags da ULA ELSIF (selM6 = sMem) THEN FR <= Mem; END IF; -- A menos que seja POP FR, quando recebe da Memoria -- Atualiza o nome dos registradores!!! RX := conv_integer(IR(9 downto 7)); RY := conv_integer(IR(6 downto 4)); RZ := conv_integer(IR(3 downto 1)); -- Selecao do Mux2 if (selM2 = sULA) THEN M2 := RESULT; ELSIF (selM2 = sMem) THEN M2 := Mem; ELSIF (selM2 = sM4) THEN M2 := M4; ELSIF (selM2 = skey) THEN M2(15 downto 8) := x"00"; M2(7 downto 0) := key; ELSIF (selM2 = sSP) THEN M2 := SP; END IF; -- if (LoadReg(RX) = '1') then REG(RX) := M2; end if; if(LoadReg(RX) = '1') then reg(RX) := m2; end if; -- Reseta os sinais de controle APOS usa-los acima -- Zera todos os sinais de controle, para depois ligar um por um a medida que for necessario: a ultima atribuicao e' a que vale no processo!!! LoadIR := '0'; LoadMAR := '0'; LoadPC := '0'; IncPC := '0'; IncSP := '0'; DecSP := '0'; LoadSP := '0'; selM6 := sULA; -- Sempre atualiza o FR da ULA, a nao ser que a instrucao seja POP FR LoadReg(0) := '0'; LoadReg(1) := '0'; LoadReg(2) := '0'; LoadReg(3) := '0'; LoadReg(4) := '0'; LoadReg(5) := '0'; LoadReg(6) := '0'; LoadReg(7) := '0'; videoflag <= '0'; RW <= '0'; -- nao tinha if(halt_req = '1') then state := halted; end if; PC_data <= PC; case state is --************************************************************************ -- FETCH STATE --************************************************************************ when fetch => PONTO <= "001"; -- Inicio das acoes do ciclo de Busca !! M1 <= PC; RW <= '0'; LoadIR := '1'; IncPC := '1'; STATE := decode; -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX --************************************************************************ -- DECODE STATE --************************************************************************ when decode => PONTO <= "010"; --======================================================================== -- INCHAR RX[5..0] <- KeyPressed RX[15..6] <- 0 --======================================================================== IF(IR(15 DOWNTO 10) = INCHAR) THEN selM2 := skey; LoadReg(RX) := '1'; state := fetch; END IF; --======================================================================== -- OUTCHAR Video[RY] <- Char(RX) --======================================================================== IF(IR(15 DOWNTO 10) = OUTCHAR) THEN M3 := Reg(Rx); -- M3 <- Rx M4 := Reg(Ry); -- M4 <- Ry vga_char <= M3; vga_pos <= M4; videoflag <= '1'; state := fetch; END IF; --======================================================================== -- MOV RX/SP <- RY/SP -- MOV RX RY RX <- RY Format: < inst(6) | RX(3) | RY(3) | xx | x0 > -- MOV RX SP RX <- SP Format: < inst(6) | RX(3) | xxx | xx | 01 > -- MOV SP RX SP <- RX Format: < inst(6) | RX(3) | xxx | xx | 11 > --======================================================================== IF(IR(15 DOWNTO 10) = MOV) THEN IF(IR(0) = '0') THEN M4 := REG(RY); selM2 := sM4; LoadReg(RX) := '1'; ELSE IF(IR(1) = '0') THEN selM2 := sSP; LoadReg(RX) := '1'; ELSE M3 := REG(RX); LoadSP := '1'; END IF; END IF; state := fetch; END IF; --======================================================================== -- STORE DIReto M[END] <- RX --======================================================================== IF(IR(15 DOWNTO 10) = STORE) THEN -- Busca o endereco M1 <= PC; RW <= '0'; LoadMAR := '1'; IncPC := '1'; state := exec; END IF; --======================================================================== -- STORE indexado por registrador M[RX] <- RY --======================================================================== IF(IR(15 DOWNTO 10) = STOREINDEX) THEN M4 := Reg(Rx); -- M4 <- Rx M1 <= M4; -- M1 <- M4 M3 := Reg(Ry); -- M3 <- Ry M5 <= M3; Rw <= '1'; -- Rw <- 1 state := fetch; END IF; --======================================================================== -- LOAD Direto RX <- M[End] --======================================================================== IF(IR(15 DOWNTO 10) = LOAD) THEN -- Busca o endereco M1 <= PC; -- M1 <- PC Rw <= '0'; -- Rw <- 0 LoadMAR := '1';-- LMAR <- 1 IncPC := '1'; state := exec; END IF; --======================================================================== -- LOAD Imediato RX <- Nr --======================================================================== IF(IR(15 DOWNTO 10) = LOADIMED) THEN M1 <= PC; -- M1 <- PC Rw <= '0'; -- Rw <= '0' selM2 := sMeM; -- LRx <- 1 LoadReg(RX) := '1'; -- IncPC <- 1 IncPC := '1'; -- M2 <- MEM state := fetch; END IF; --======================================================================== -- LOAD Indexado por registrador RX <- M(RY) --======================================================================== IF(IR(15 DOWNTO 10) = LOADINDEX) THEN M4 := Reg(Ry); -- M4 <- Ry M1 <= M4; -- M1 <- M4 Rw <= '0'; -- Rw <- 0 selM2 := sMEM; -- M2 <- MEM LoadReg(Rx) := '1'; -- LRx <- 1 state := fetch; END IF; --======================================================================== -- LOGIC OPERATION ('SHIFT', 'CMP' AND 'NOT' NOT INCLUDED) RX <- RY (?) RZ --======================================================================== IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) /= SHIFT AND IR(13 DOWNTO 10) /= LNOT AND IR(13 DOWNTO 10) /= CMP) THEN M3 := Reg(Ry); M4 := Reg(Rz); X <= M3; Y <= M4; OP(5 downto 0 ) <= IR(15 downto 10); selM2 := sULA; LoadReg(Rx) := '1'; state := fetch; END IF; --======================================================================== -- NOT RX, RY RX <- NOT(RY) --======================================================================== IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) = LNOT) THEN M3 := REG(RX); M4 := REG(RY); X <= M3; Y <= M4; OP(5 downto 0) <= IR(15 downto 10); selM2 := sULA; LoadReg(Rx) := '1'; state := fetch; END IF; --======================================================================== -- CMP RX, RY --======================================================================== IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) = CMP) THEN M3 := Reg(Rx); M4 := Reg(Ry); X <= M3; Y <= M4; OP(5 downto 0 ) <= IR(15 downto 10); state := fetch; END IF; --======================================================================== -- SHIFT RX, RY RX <- SHIFT[ RY] ROTATE INCluded ! --======================================================================== IF(IR(15 DOWNTO 14) = LOGIC and (IR(13 DOWNTO 10) = SHIFT)) THEN if(IR(6 DOWNTO 4) = "000") then -- SHIFT LEFT 0 Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))sll conv_integer(IR(3 DOWNTO 0))); elsif(IR(6 DOWNTO 4) = "001") then -- SHIFT LEFT 1 Reg(RX) := not (To_StdLOGICVector(to_bitvector(not Reg(RY))sll conv_integer(IR(3 DOWNTO 0)))); elsif(IR(6 DOWNTO 4) = "010") then -- SHIFT RIGHT 0 Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))srl conv_integer(IR(3 DOWNTO 0))); elsif(IR(6 DOWNTO 4) = "011") then -- SHIFT RIGHT 0 Reg(RX) := not (To_StdLOGICVector(to_bitvector(not Reg(RY))srl conv_integer(IR(3 DOWNTO 0)))); elsif(IR(6 DOWNTO 5) = "11") then -- ROTATE RIGHT Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))ror conv_integer(IR(3 DOWNTO 0))); elsif(IR(6 DOWNTO 5) = "10") then -- ROTATE LEFT Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))rol conv_integer(IR(3 DOWNTO 0))); end if; state := fetch; end if; --======================================================================== -- JMP END PC <- 16bit END : b9-b6 = COND -- Flag Register: <...|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater> --======================================================================== IF(IR(15 DOWNTO 10) = JMP) THEN if((IR(9 downto 6) = "0000") or -- NO COND (IR(9 downto 6) = "0111" and FR(0) = '1') or -- GREATER (IR(9 downto 6) = "1001" and FR(2 downto 0) = "101") or -- greater equal (IR(9 downto 6) = "1000" and FR(1) = '1') or -- lesser (IR(9 downto 6) = "1010" and FR(2 downto 0) = "110") or -- lesser equal (IR(9 downto 6) = "0001" and FR(2) = '1') or -- equal (IR(9 downto 6) = "0010" and FR(2) = '0') or -- not equal (IR(9 downto 6) = "0011" and FR(3) = '1') or -- zero (IR(9 downto 6) = "0100" and FR(3) = '0') or -- not zero (IR(9 downto 6) = "0101" and FR(4) = '1') or -- carry (IR(9 downto 6) = "0110" and FR(4) = '0') or -- not carry (IR(9 downto 6) = "1011" and FR(5) = '1') or -- overflow (IR(9 downto 6) = "1100" and FR(5) = '0') or -- not overflow (IR(9 downto 6) = "1101" and FR(6) = '1') or -- DIV0 (IR(9 downto 6) = "1110" and FR(9) = '1')) then -- result negative M1 <= PC; RW <= '0'; LoadPC := '1'; else IncPC := '1'; end if; state := fetch; END IF; --======================================================================== -- PUSH RX --======================================================================== IF(IR(15 DOWNTO 10) = PUSH) THEN M1 <= SP; -- M1 <- SP Rw <= '1'; -- R/W <- 1 if(IR(6) = '0') then M3 := Reg(Rx); -- M3 <- Rx elsif(IR(6) = '1') then M3 := FR; end if; M5 <= M3; -- M5 <- M3 DecSP := '1'; -- DecSP <- 1 state := fetch; END IF; --======================================================================== -- POP RX --======================================================================== IF(IR(15 DOWNTO 10) = POP) THEN IncSP := '1'; state := exec; END IF; --======================================================================== -- CALL END PC <- 16bit END : b9-b6 = COND PUSH(PC) -- Flag Register: <...|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater> --======================================================================== IF(IR(15 DOWNTO 10) = CALL) THEN if((IR(9 downto 6) = "0000") or -- NO COND (IR(9 downto 6) = "0111" and FR(0) = '1') or -- GREATER (IR(9 downto 6) = "1001" and FR(2 downto 0) = "101") or -- greater equal (IR(9 downto 6) = "1000" and FR(1) = '1') or -- lesser (IR(9 downto 6) = "1010" and FR(2 downto 0) = "110") or -- lesser equal (IR(9 downto 6) = "0001" and FR(2) = '1') or -- equal (IR(9 downto 6) = "0010" and FR(2) = '0') or -- not equal (IR(9 downto 6) = "0011" and FR(3) = '1') or -- zero (IR(9 downto 6) = "0100" and FR(3) = '0') or -- not zero (IR(9 downto 6) = "0101" and FR(4) = '1') or -- carry (IR(9 downto 6) = "0110" and FR(4) = '0') or -- not carry (IR(9 downto 6) = "1011" and FR(5) = '1') or -- overflow (IR(9 downto 6) = "1100" and FR(5) = '0') or -- not overflow (IR(9 downto 6) = "1101" and FR(6) = '1') or -- DIV0 (IR(9 downto 6) = "1110" and FR(9) = '1')) then -- result negative RW <= '1'; -- Escreve PC na Pilha (M[SP] <- PC) M5 <= PC; M1 <= SP; DecSP := '1'; state := exec; ELSE IncPC := '1'; state := fetch; END IF; END IF; --======================================================================== -- RTS PC <- Mem[SP] --======================================================================== IF(IR(15 DOWNTO 10) = RTS) THEN IncSP := '1'; state := exec; END IF; --======================================================================== -- ARITH OPERATION ('INC' NOT INCLUDED) RX <- RY (?) RZ --======================================================================== IF(IR(15 DOWNTO 14) = ARITH AND IR(13 DOWNTO 10) /= INC) THEN M3 := Reg(Ry); M4 := Reg(RZ); X <= M3; Y <= M4; OP(5 downto 0 ) <= IR(15 downto 10); OP(6) <= IR(0); selM2 := sULA; LoadReg(Rx) := '1'; state := fetch; END IF; --======================================================================== -- INC RX <- RX (+ or -) 1 --======================================================================== IF(IR(15 DOWNTO 14) = ARITH AND IR(13 DOWNTO 10) = INC) THEN M3 := Reg(Rx); M4 := x"0001"; X <= M3; Y <= M4; OP(5 downto 4) <= ARITH; IF(IR(6) = '0') THEN OP(3 downto 0) <= ADD; ELSE OP(3 downto 0) <= SUB; END IF; selM2 := sULA; LoadReg(Rx) := '1'; state := fetch; END IF; --======================================================================== -- NOP --======================================================================== IF( IR(15 DOWNTO 10) = NOP) THEN state := fetch; end if; --======================================================================== -- HALT --======================================================================== IF( IR(15 DOWNTO 10) = HALT) THEN state := halted; END IF; --======================================================================== -- SETC/CLEARC --======================================================================== IF( IR(15 DOWNTO 10) = SETC) THEN FR(4) <= IR(9); state := fetch; end if; --======================================================================== -- BREAKP --======================================================================== IF( IR(15 DOWNTO 10) = BREAKP) THEN BreakFlag := not(BreakFlag); --BREAK <= BreakFlag; state := fetch; PONTO <= "101"; END IF; -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX --************************************************************************ -- EXECUTE STATE --************************************************************************ when exec => PONTO <= "100"; --======================================================================== -- EXEC STORE DIReto M[END] <- RX --======================================================================== IF(IR(15 DOWNTO 10) = STORE) THEN M1 <= MAR; Rw <= '1'; M3 := Reg(Rx); M5 <= M3; state := fetch; END IF; --======================================================================== -- EXEC LOAD DIReto RX <- M[END] --======================================================================== IF(IR(15 DOWNTO 10) = LOAD) THEN M1 <= Mar; Rw <= '0'; selM2 := sMem; LoadReg(Rx) := '1'; state := fetch; END IF; --======================================================================== -- EXEC POP RX --======================================================================== IF(IR(15 DOWNTO 10) = POP) THEN M1 <= SP; -- M1 <- SP Rw <= '0'; -- R/W <- 0 if(IR(6) = '0') then selM2 := sMem; -- M2 <- MEM LoadReg(Rx) := '1'; -- LRx <- 1 elsif(IR(6) = '1') then selM6 := sMem; end if; state := fetch; END IF; --======================================================================== -- EXEC CALL Pilha <- PC e PC <- 16bit END : --======================================================================== IF(IR(15 DOWNTO 10) = CALL) THEN M1 <= PC; -- M1 <- PC Rw <= '0'; -- R/W <- 0 LoadPC := '1'; -- LPC <- 1 state := fetch; END IF; --======================================================================== -- EXEC RTS PC <- Mem[SP] --======================================================================== IF(IR(15 DOWNTO 10) = RTS) THEN M1 <= SP; Rw <= '0'; LoadPC := '1'; IncPC := '1'; -- fazer em outro estado pq INCrementar e LOAD sao na SUBida de clock state := fetch; END IF; -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX --************************************************************************ -- HALT STATE --************************************************************************ WHEN halted => PONTO <= "111"; state := halted; halt_ack <= '1'; WHEN OTHERS => state := fetch; videoflag <= '0'; PONTO <= "000"; END CASE; end if; end process; --************************************************************************ -- ULA ---> 3456 (3042) --************************************************************************ PROCESS (OP, X, Y, reset) VARIABLE AUX : STD_LOGIC_VECTOR(15 downto 0); VARIABLE RESULT32 : STD_LOGIC_VECTOR(31 downto 0); BEGIN IF (reset = '1') THEN auxFR <= x"0000"; RESULT <= x"0000"; else auxFR <= FR; --======================================================================== -- ARITH --======================================================================== IF (OP (5 downto 4) = ARITH) THEN CASE OP (3 downto 0) IS WHEN ADD => IF (OP(6) = '1') THEN --Soma com carRY AUX := X + Y + FR(4); RESULT32 := (x"00000000" + X + Y + FR(4)); ELSE --Soma sem carRY AUX := X + Y; RESULT32 := (x"00000000" + X + Y); end if; if(RESULT32 > "01111111111111111") THEN -- CarRY auxFR(4) <= '1'; ELSE auxFR(4) <= '0'; end if; WHEN SUB => AUX := X - Y; WHEN MULT => RESULT32 := X * Y; AUX := RESULT32(15 downto 0); if(RESULT32 > x"0000FFFF") THEN -- ARITHmetic Overflow auxFR(5) <= '1'; ELSE auxFR(5) <= '0'; end if; WHEN DIV => IF(Y = x"0000") THEN AUX := x"0000"; auxFR(6) <= '1'; -- DIV by Zero ELSE AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X)/CONV_INTEGER(Y), 16); auxFR(6) <= '0'; END IF; WHEN LMOD => IF(Y = x"0000") THEN AUX := x"0000"; auxFR(6) <= '1'; -- DIV by Zero ELSE AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X) mod CONV_INTEGER(Y), 16); auxFR(6) <= '0'; END IF; WHEN others => -- invalid operation, defaults to nothing AUX := X; END CASE; if(AUX = x"0000") THEN auxFR(3) <= '1'; -- FR = <...|zero|equal|lesser|greater> ELSE auxFR(3) <= '0'; -- FR = <...|zero|equal|lesser|greater> end if; if(AUX < x"0000") THEN -- NEGATIVO auxFR(9) <= '1'; ELSE auxFR(9) <= '0'; end if; RESULT <= AUX; ELSIF (OP (5 downto 4) = LOGIC) THEN IF (OP (3 downto 0) = CMP) THEN result <= x; IF (x > y) THEN auxFR(2 downto 0) <= "001"; -- FR = <...|zero|equal|lesser|greater> ELSIF (x < y) THEN auxFR(2 downto 0) <= "010"; -- FR = <...|zero|equal|lesser|greater> ELSIF (x = y) THEN auxFR(2 downto 0) <= "100"; -- FR = <...|zero|equal|lesser|greater> END IF; ELSE CASE OP (3 downto 0) IS WHEN LAND => result <= x and y; WHEN LXOR => result <= x xor y; WHEN LOR => result <= x or y; WHEN LNOT => result <= not y; WHEN others => -- invalid operation, defaults to nothing RESULT <= X; END CASE; if(result = x"0000") THEN auxFR(3) <= '1'; -- FR = <...|zero|equal|lesser|greater> ELSE auxFR(3) <= '0'; -- FR = <...|zero|equal|lesser|greater> end if; END IF; END IF; END IF; -- Reset END PROCESS; end main;
gpl-3.0
a8decee1b6ca53a0bc6d0e39214ee146
0.428027
3.323505
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/RTL/New_SHMU_on_Node/NoC_Node.vhd
3
5,390
--------------------------------------------------------------------- -- TITLE: NoC_Node -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 4/21/01 -- ORIGNAL FILENAME: tbench.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- This entity provides a simple NoC node with plasma as its processor --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; use ieee.std_logic_unsigned.all; entity NoC_Node is generic( current_address : integer := 0; stim_file: string :="code.txt"; log_file : string := "output.txt"); port( reset : in std_logic; clk : in std_logic; credit_in : in std_logic; valid_out: out std_logic; TX: out std_logic_vector(31 downto 0); credit_out : out std_logic; valid_in: in std_logic; RX: in std_logic_vector(31 downto 0); link_faults: in std_logic_vector(4 downto 0); turn_faults: in std_logic_vector(7 downto 0); Rxy_reconf_PE: out std_logic_vector(7 downto 0); Cx_reconf_PE: out std_logic_vector(3 downto 0); Reconfig_command : out std_logic ); end; --entity NoC_Node architecture messed_up of NoC_Node is constant memory_type : string := "TRI_PORT_X"; -- "DUAL_PORT_"; -- "ALTERA_LPM"; -- "XILINX_16X"; signal interrupt : std_logic := '0'; signal mem_write : std_logic; signal address : std_logic_vector(31 downto 2); signal data_write : std_logic_vector(31 downto 0); signal data_read : std_logic_vector(31 downto 0); signal pause1 : std_logic := '0'; signal pause2 : std_logic := '0'; signal pause : std_logic; signal no_ddr_start: std_logic; signal no_ddr_stop : std_logic; signal byte_we : std_logic_vector(3 downto 0); signal uart_write : std_logic; signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0'); --signal credit_in, valid_in: std_logic := '0'; --signal credit_out, valid_out: std_logic := '0'; --signal RX: std_logic_vector(31 downto 0) := (others => '0'); --signal TX: std_logic_vector(31 downto 0) := (others => '0'); -- signal credit_counter_out_0: std_logic_vector (1 downto 0); begin --architecture --pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns; pause1 <= '0'; --pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns; pause2 <= '0'; pause <= pause1 or pause2; --gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK --gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV --gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD --gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK u1_plasma: plasma generic map (memory_type => memory_type, ethernet => '0', use_cache => '0', log_file => log_file, current_address => current_address, stim_file => stim_file) PORT MAP ( clk => clk, reset => reset, uart_read => uart_write, uart_write => uart_write, address => address, byte_we => byte_we, data_write => data_write, data_read => data_read, mem_pause_in => pause, no_ddr_start => no_ddr_start, no_ddr_stop => no_ddr_stop, gpio0_out => open, gpioA_in => gpioA_in, credit_in => credit_in, valid_out => valid_out, TX => TX, credit_out => credit_out, valid_in => valid_in, RX => RX, link_faults => link_faults, turn_faults => turn_faults, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command => Reconfig_command ); dram_proc: process(clk, address, byte_we, data_write, pause) constant ADDRESS_WIDTH : natural := 16; type storage_array is array(natural range 0 to (2 ** ADDRESS_WIDTH) / 4 - 1) of std_logic_vector(31 downto 0); variable storage : storage_array; variable data : std_logic_vector(31 downto 0); variable index : natural := 0; begin index := conv_integer(address(ADDRESS_WIDTH-1 downto 2)); data := storage(index); if byte_we(0) = '1' then data(7 downto 0) := data_write(7 downto 0); end if; if byte_we(1) = '1' then data(15 downto 8) := data_write(15 downto 8); end if; if byte_we(2) = '1' then data(23 downto 16) := data_write(23 downto 16); end if; if byte_we(3) = '1' then data(31 downto 24) := data_write(31 downto 24); end if; if rising_edge(clk) then if address(30 downto 28) = "001" and byte_we /= "0000" then storage(index) := data; end if; end if; if pause = '0' then data_read <= data; end if; end process; end; --architecture logic
gpl-3.0
72552ffd7e0ef51b238892ed14ad38a6
0.530241
3.534426
false
false
false
false
Wynjones1/gbvhdl
src/alu.vhd
1
8,357
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.std_logic_misc.all; use work.types.all; use work.interfaces.all; entity alu is port( input : in alu_in_if; output : out alu_out_if); end entity; architecture rtl of alu is signal flags : byte_t; signal q : byte_t; signal i0 : byte_t; signal i1 : byte_t; begin output.flags <= flags; output.q <= q; i0 <= input.i0; i1 <= input.i1; process(flags, q, i0, i1, input) constant RES_WIDTH : integer := input.i0'length + 1; variable res_slv : std_logic_vector(RES_WIDTH - 1 downto 0); variable res : unsigned(RES_WIDTH - 1 downto 0); variable i0_int : unsigned(input.i0'length - 1 downto 0); variable i1_int : unsigned(input.i1'length - 1 downto 0); variable carry : unsigned(0 downto 0); begin i0_int := unsigned(input.i0); i1_int := unsigned(input.i1); carry := unsigned(input.flags(CARRY_BIT downto CARRY_BIT)); flags <= input.flags; q <= (others => '0'); case input.op is when alu_op_add => res := ('0' & i0_int) + ('0' & i1_int); res_slv := std_logic_vector(res); q <= res_slv(7 downto 0); flags(CARRY_BIT) <= res(8); flags(ZERO_BIT) <= nor_reduce(res_slv(7 downto 0)); res(4 downto 0) := ('0' & i0_int(3 downto 0)) + i1_int(3 downto 0); flags(HALF_CARRY_BIT) <= res(4); flags(SUBTRACT_BIT) <= '0'; when alu_op_adc => res := (('0' & i0_int) + i1_int) + carry; res_slv := std_logic_vector(res); q <= res_slv(7 downto 0); flags(CARRY_BIT) <= res(8); flags(ZERO_BIT) <= nor_reduce(res_slv(7 downto 0)); res(4 downto 0) := ('0' & i0_int(3 downto 0)) + i1_int(3 downto 0) + carry; flags(HALF_CARRY_BIT) <= res(4); flags(SUBTRACT_BIT) <= '0'; when alu_op_and => q <= i0 and i1; flags(ZERO_BIT) <= nor_reduce(i0 and i1); flags(SUBTRACT_BIT) <= '0'; flags(CARRY_BIT) <= '0'; flags(HALF_CARRY_BIT) <= '1'; when alu_op_bit => q <= (others => '0'); flags(ZERO_BIT) <= not i0(to_integer(i1_int(2 downto 0))); flags(SUBTRACT_BIT) <= '0'; flags(HALF_CARRY_BIT) <= '1'; when alu_op_cp => -- compare op, no output at q q <= (others => '0'); if i0_int < i1_int then flags(CARRY_BIT) <= '1'; else flags(CARRY_BIT) <= '0'; end if; if i0_int(3 downto 0) < i1_int(3 downto 0) then flags(HALF_CARRY_BIT) <= '1'; else flags(HALF_CARRY_BIT) <= '0'; end if; flags(ZERO_BIT) <= nor_reduce(std_logic_vector(i0_int - i1_int)); flags(SUBTRACT_BIT) <= '1'; when alu_op_cpl => q <= not i0; flags(HALF_CARRY_BIT) <= '1'; flags(SUBTRACT_BIT) <= '1'; when alu_op_daa => res := (others => '0'); res_slv := std_logic_vector(res); q <= res_slv(7 downto 0); flags(ZERO_BIT) <= nor_reduce(res_slv); flags(HALF_CARRY_BIT) <= '0'; when alu_op_or => q <= i0 or i1; flags(CARRY_BIT) <= '0'; flags(HALF_CARRY_BIT) <= '0'; flags(SUBTRACT_BIT) <= '0'; flags(ZERO_BIT) <= nor_reduce(i0 or i1); when alu_op_rl => q <= i0(6 downto 0) & input.flags(CARRY_BIT); flags(CARRY_BIT) <= i0(7); flags(HALF_CARRY_BIT) <= '0'; flags(SUBTRACT_BIT) <= '0'; flags(ZERO_BIT) <= nor_reduce(i0(6 downto 0) & input.flags(CARRY_BIT)); when alu_op_rlc => q <= i0(6 downto 0) & i0(7); flags(CARRY_BIT) <= i0(7); flags(HALF_CARRY_BIT) <= '0'; flags(SUBTRACT_BIT) <= '0'; flags(ZERO_BIT) <= nor_reduce(i0); when alu_op_rr => q <= input.flags(CARRY_BIT) & i0(7 downto 1); flags(CARRY_BIT) <= i0(0); flags(HALF_CARRY_BIT) <= '0'; flags(SUBTRACT_BIT) <= '0'; flags(ZERO_BIT) <= nor_reduce(input.flags(CARRY_BIT) & i0(7 downto 1)); when alu_op_rrc => q <= i0(0) & i0(7 downto 1); flags(CARRY_BIT) <= i0(0); flags(HALF_CARRY_BIT) <= '0'; flags(SUBTRACT_BIT) <= '0'; flags(ZERO_BIT) <= nor_reduce(i0); when alu_op_sla => q <= i0(6 downto 0) & '0'; flags(CARRY_BIT) <= i0(7); flags(HALF_CARRY_BIT) <= '0'; flags(SUBTRACT_BIT) <= '0'; flags(ZERO_BIT) <= nor_reduce(i0(6 downto 0)); when alu_op_sra => q <= i0(7) & i0(7 downto 1); flags(CARRY_BIT) <= i0(0); flags(HALF_CARRY_BIT) <= '0'; flags(SUBTRACT_BIT) <= '0'; flags(ZERO_BIT) <= nor_reduce(i0(7 downto 1)); when alu_op_srl => q <= '0' & i0(7 downto 1); flags(CARRY_BIT) <= i0(0); flags(HALF_CARRY_BIT) <= '0'; flags(SUBTRACT_BIT) <= '0'; flags(ZERO_BIT) <= nor_reduce(i0(7 downto 1)); when alu_op_sub => res(7 downto 0) := i0_int - i1_int; res_slv := std_logic_vector(res); q <= res_slv(7 downto 0); if i0_int < i1_int then flags(CARRY_BIT) <= '1'; else flags(CARRY_BIT) <= '0'; end if; if i0_int(3 downto 0) < i1_int(3 downto 0) then flags(HALF_CARRY_BIT) <= '1'; else flags(HALF_CARRY_BIT) <= '0'; end if; flags(ZERO_BIT) <= nor_reduce(res_slv(7 downto 0)); flags(SUBTRACT_BIT) <= '1'; when alu_op_sbc => res(7 downto 0) := ((i0_int - i1_int) - carry); res_slv := std_logic_vector(res); q <= res_slv(7 downto 0); if i0_int < (i1_int + carry) then flags(CARRY_BIT) <= '1'; else flags(CARRY_BIT) <= '0'; end if; if i0_int(3 downto 0) < (('0' & i1_int(3 downto 0)) + carry) then flags(HALF_CARRY_BIT) <= '1'; else flags(HALF_CARRY_BIT) <= '0'; end if; flags(SUBTRACT_BIT) <= '1'; flags(ZERO_BIT) <= nor_reduce(res_slv(7 downto 0)); when alu_op_swap => q(3 downto 0) <= i0(7 downto 4); q(7 downto 4) <= i0(3 downto 0); flags(CARRY_BIT) <= '0'; flags(HALF_CARRY_BIT) <= '0'; flags(SUBTRACT_BIT) <= '0'; flags(ZERO_BIT) <= nor_reduce(i0); when alu_op_set => q <= i0; q(to_integer(i1_int(2 downto 0))) <= '1'; when alu_op_reset => q <= i0; q(to_integer(i1_int(2 downto 0))) <= '0'; when alu_op_xor => q <= i0 xor i1; flags(CARRY_BIT) <= '0'; flags(HALF_CARRY_BIT) <= '0'; flags(SUBTRACT_BIT) <= '0'; flags(ZERO_BIT) <= nor_reduce(i0 xor i1); when others => q <= (others => 'X'); end case; end process; end rtl;
mit
e0523c28957a4e97bc952b7da05feea8
0.406486
3.53511
false
false
false
false
ashtonchase/logic_analyzer
src/capture_ctrl_a.vhd
1
11,251
------------------------------------------------------------------------------- -- Title : Logic Analzyer Data Capture Controller Architecture -- Project : fpga_logic_analyzer ------------------------------------------------------------------------------- -- File : la_ctrl_ea.vhd -- Created : 2016-02-27 -- Last update: 2016-04-10 -- Standard : VHDL'08 ------------------------------------------------------------------------------- -- Description: This entity module is the primary capture controller of the -- Analyzer Module. ------------------------------------------------------------------------------- -- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt ------------------------------------------------------------------------------- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-02-27 1.0 ashton Created ------------------------------------------------------------------------------- -- LIBRARY ieee; -- USE ieee.std_logic_1164.ALL; -- USE ieee.numeric_std.ALL; LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; --see capture_ctrl_e for entity definition -- ENTITY capture_ctrl IS -- GENERIC ( -- DATA_WIDTH : POSITIVE RANGE 1 TO 32 := 8); -- PORT ( -- --top level interafaces -- clk : IN STD_LOGIC; -- Clock -- rst : IN STD_LOGIC := '0'; -- syncronous reset -- din : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); -- input channels -- --status indicators -- armed : OUT STD_LOGIC; --latched indicator when armed. -- triggered : OUT STD_LOGIC; --latched indicator when triggerd. -- ------message processing interfaces -- --serially received reset command. one clock cycle required -- rst_cmd : IN STD_LOGIC := '0'; -- --serially received arm command. one clock cycle required. -- arm_cmd : IN STD_LOGIC; -- --sample enable trigger. for subsampling data. -- sample_enable : IN STD_LOGIC := '1'; -- --send a reset pulse to the sample rate clock -- sample_cnt_rst : OUT STD_LOGIC; -- --number of samples to read, times four. max==262,140 samples -- read_cnt_4x : IN STD_LOGIC_VECTOR(16-1 DOWNTO 0) := (OTHERS => '1'); -- --parallel trigger bit mask for par_trig_val. latched in on arm_cmd -- par_trig_msk : IN STD_LOGIC_VECTOR(32-1 DOWNTO 0) := (OTHERS => '0'); -- --parallel triger values, latched in on arm_cmd -- par_trig_val : IN STD_LOGIC_VECTOR(32-1 DOWNTO 0) := (OTHERS => '1'); -- --ready_to_arm indicator -- capture_rdy : OUT STD_LOGIC; -- --fifo interface -- fifo_tdata : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0); --captured -- --data output -- fifo_tvalid : OUT STD_LOGIC; -- indicating tdata has valid data -- fifo_tlast : OUT STD_LOGIC; -- no planned usage -- fifo_tready : IN STD_LOGIC := '1'; -- only used on initial setup -- fifo_tfull : IN STD_LOGIG := '0'; -- --dummy placeholder -- placeholder : IN STD_LOGIC := '0' -- ); -- END ENTITY capture_ctrl; ARCHITECTURE behavioral OF capture_ctrl IS constant DEVICE_ID : std_logic_vector(31 downto 0) := X"53_4c_41_31"; -- --ASCII SLA1 --entity related signals SIGNAL din_ff : STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '1'); SIGNAL armed_o : STD_LOGIC := '0'; SIGNAL triggered_o : STD_LOGIC := '0'; SIGNAL sample_cnt_rst_o : STD_LOGIC := '1'; SIGNAL delay_cnt_4x_l : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL read_cnt_4x_l : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := (OTHERS => '1'); SIGNAL par_trig_msk_l : STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL par_trig_val_l : STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '1'); SIGNAL capture_rdy_o : STD_LOGIC := '0'; SIGNAL fifo_tdata_o : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := (OTHERS => '1'); SIGNAL fifo_tvalid_o : STD_LOGIC := '0'; SIGNAL fifo_tlast_o : STD_LOGIC := '0'; SIGNAL din_masked, par_val_masked : STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL trig : STD_LOGIC :='0'; --state machine signals TYPE state_t IS (INIT, WAIT_FOR_ARM_OR_ID_CMD, WAIT_FOR_TRIGGER, DELAY_HOLD, CAPTURE_DATA); SIGNAL state : state_t := INIT; --capture count SIGNAL capture_cnt,capture_cnt_plus, delay_cnt, delay_cnt_plus : NATURAL RANGE 0 TO 262_141+1 := 0; BEGIN -- ARCHITECTURE behavioral --fast trigger detect --fast adds capture_cnt_plus<=capture_cnt + 1; delay_cnt_plus<=delay_cnt+1; ----------------------------------------------------------------------------- -- Concurrent assigments ----------------------------------------------------------------------------- --fifo assignments fifo_tdata <= fifo_tdata_o; fifo_tvalid <= fifo_tvalid_o; fifo_tlast <= fifo_tlast_o; --mp_assignemets capture_rdy <= capture_rdy_o; --top lelel assigments armed <= armed_o; triggered <= trig; sample_cnt_rst <= sample_cnt_rst_o; din_masked <= din_ff AND par_trig_msk_l; par_val_masked <= par_trig_val_l AND par_trig_msk_l; ----------------------------------------------------------------------------- -- Processes ----------------------------------------------------------------------------- -- purpose: this is the main capture process encapsulating a state machine -- type : sequential -- inputs : clk, rst -- outputs: capture_process : PROCESS (clk) IS PROCEDURE inc ( SIGNAL val_to_inc : INOUT NATURAL) IS BEGIN val_to_inc <= val_to_inc+1; END PROCEDURE; BEGIN -- PROCESS capture_process is_clk : IF rising_edge(clk) THEN -- rising clock edge --default assigments if ((din_masked) = (par_val_masked)) then trig <='1' ; else trig <='0'; end if; din_ff <= din; fifo_tdata_o <= (OTHERS => '0'); fifo_tdata_o(DATA_WIDTH-1 DOWNTO 0) <= din_ff; fifo_tvalid_o <= '0'; fifo_tlast_o <= '0'; sample_cnt_rst_o <= '1'; capture_rdy_o <= '0'; fifo_aresetn <= '0'; is_rst : IF rst = '1' THEN -- synchronous reset (active high) state <= INIT; fifo_aresetn <= '1'; ELSE fsm : CASE state IS WHEN INIT => is_fifo_ready : IF fifo_tready = '1' THEN state <= WAIT_FOR_ARM_OR_ID_CMD; capture_cnt <= 0; delay_cnt <= 0; armed_o <= '0'; triggered_o <= '0'; END IF is_fifo_ready; ------------------------------------------------------------------- WHEN WAIT_FOR_ARM_OR_ID_CMD => par_trig_msk_l <= par_trig_msk(DATA_WIDTH-1 DOWNTO 0); par_trig_val_l <= par_trig_val(DATA_WIDTH-1 DOWNTO 0); delay_cnt_4x_l <= X"00_00"; read_cnt_4x_l <= delay_cnt_4x; capture_rdy_o <= '1'; is_arm : IF arm_cmd = '1' THEN state <= WAIT_FOR_TRIGGER; armed_o <= '1'; END IF is_arm; is_ID_requested: if id_cmd='1' then fifo_tdata_o <= DEVICE_ID; fifo_tvalid_o <='1'; end if is_ID_requested; is_debug_requested: if debug_cmd='1' then fifo_tdata_o <= par_trig_msk_l & par_trig_val_l & din_masked & par_val_masked; fifo_tvalid_o <='1'; end if is_debug_requested; ------------------------------------------------------------------- WHEN WAIT_FOR_TRIGGER => is_trigged : IF trig='1' THEN --go delay if requred should_delay : IF delay_cnt_4x_l = X"00_00" THEN state <= CAPTURE_DATA; sample_cnt_rst_o <= '0'; fifo_tvalid_o <= '1'; ELSE state <= DELAY_HOLD; END IF should_delay; triggered_o <= '1'; capture_cnt<=capture_cnt_plus; END IF is_trigged; ------------------------------------------------------------------- WHEN DELAY_HOLD => is_dly_done : IF (delay_cnt = to_integer(UNSIGNED(delay_cnt_4x_l))*4+4) THEN delay_cnt <= 0; state <= CAPTURE_DATA; ELSIF sample_enable = '1' THEN delay_cnt<=delay_cnt_plus; END IF is_dly_done; ------------------------------------------------------------------- WHEN CAPTURE_DATA => --keep sample rate clock from being reset sample_cnt_rst_o <= '0'; triggered_o <= '1'; --will the next sample be the last one, the go ahead an assert tlast. is_ready_for_tlast : IF (capture_cnt+1 = to_integer(UNSIGNED(read_cnt_4x_l))*4+4) THEN fifo_tlast_o <= '1'; END IF is_ready_for_tlast; is_done : IF (capture_cnt = to_integer(UNSIGNED(read_cnt_4x_l))*4+4) THEN state <= INIT; delay_cnt <= 0; --else more samples to collect -- ELSIF delay_cnt_4x_l = X"00_00" THEN -- capture_cnt<=capture_cnt_plus; -- fifo_tvalid_o <= '1'; ELSIF sample_enable = '1' THEN capture_cnt<=capture_cnt_plus; fifo_tvalid_o <= '1'; END IF is_done; ------------------------------------------------------------------- WHEN OTHERS => NULL; END CASE fsm; END IF is_rst; END IF is_clk; END PROCESS capture_process; ----------------------------------------------------------------------------- -- Component Instantiations ----------------------------------------------------------------------------- END ARCHITECTURE behavioral;
gpl-2.0
ff0338ddfa721abe8fd8abe6dea21ae6
0.469292
4.101713
false
false
false
false
AndyMcC0/UVVM_All
bitvis_vip_sbi/src/vvc_cmd_pkg.vhd
3
6,948
--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <[email protected]>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library uvvm_util; context uvvm_util.uvvm_util_context; library uvvm_vvc_framework; use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all; --================================================================================================= --================================================================================================= --================================================================================================= package vvc_cmd_pkg is --=============================================================================================== -- t_operation -- - Bitvis defined BFM operations --=============================================================================================== type t_operation is ( -- UVVM common NO_OPERATION, AWAIT_COMPLETION, AWAIT_ANY_COMPLETION, ENABLE_LOG_MSG, DISABLE_LOG_MSG, FLUSH_COMMAND_QUEUE, FETCH_RESULT, INSERT_DELAY, TERMINATE_CURRENT_COMMAND, -- VVC local WRITE, READ, CHECK, POLL_UNTIL); constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 32; constant C_VVC_CMD_ADDR_MAX_LENGTH : natural := 32; constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300; --=============================================================================================== -- t_vvc_cmd_record -- - Record type used for communication with the VVC --=============================================================================================== type t_vvc_cmd_record is record -- Common UVVM fields (Used by td_vvc_framework_common_methods_pkg procedures, and thus mandatory) operation : t_operation; proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH); msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH); cmd_idx : natural; command_type : t_immediate_or_queued; -- QUEUED/IMMEDIATE msg_id : t_msg_id; gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed gen_boolean : boolean; -- Generic boolean timeout : time; alert_level : t_alert_level; delay : time; quietness : t_quietness; -- VVC dedicated fields addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0); -- Max width may be increased if required data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0); max_polls : integer; end record; constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := ( operation => NO_OPERATION, -- Default unless overwritten by a common operation addr => (others => '0'), data => (others => '0'), max_polls => 1, alert_level => failure, proc_call => (others => NUL), msg => (others => NUL), cmd_idx => 0, command_type => NO_command_type, msg_id => NO_ID, gen_integer_array => (others => -1), gen_boolean => false, timeout => 0 ns, delay => 0 ns, quietness => NON_QUIET ); --=============================================================================================== -- shared_vvc_cmd -- - Shared variable used for transmitting VVC commands --=============================================================================================== shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT; --=============================================================================================== -- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response : -- -- - These are used for storing the result of the read/receive BFM commands issued by the VVC, -- - so that the result can be transported from the VVC to the sequencer via a -- a fetch_result() call as described in VVC_Framework_common_methods_QuickRef -- -- - t_vvc_result matches the return value of read/receive procedure in the BFM. --=============================================================================================== subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0); type t_vvc_result_queue_element is record cmd_idx : natural; -- from UVVM handshake mechanism result : t_vvc_result; end record; type t_vvc_response is record fetch_is_accepted : boolean; transaction_result : t_transaction_result; result : t_vvc_result; end record; shared variable shared_vvc_response : t_vvc_response; --=============================================================================================== -- t_last_received_cmd_idx : -- - Used to store the last queued cmd in vvc interpreter. --=============================================================================================== type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer; --=============================================================================================== -- shared_vvc_last_received_cmd_idx -- - Shared variable used to get last queued index from vvc to sequencer --=============================================================================================== shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1)); end package vvc_cmd_pkg; package body vvc_cmd_pkg is end package body vvc_cmd_pkg;
mit
993c13def1cfb1037465fa0d487e875a
0.452504
5.097579
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/ScanRegister_for_SIBFCX.vhd
3
2,121
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ScanRegister_for_SIBFCX is Generic (Size : positive; BitOrder : string; -- MSBLSB / LSBMSB SOSource : natural; ResetValue : STD_LOGIC_VECTOR); Port ( SI : in STD_LOGIC; CE : in STD_LOGIC; SE : in STD_LOGIC; UE : in STD_LOGIC; SEL : in STD_LOGIC; RST : in STD_LOGIC; TCK : in STD_LOGIC; SO : out STD_LOGIC; CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0); ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0); ue_mux_out : out STD_LOGIC_VECTOR (Size-1 downto 0)); end ScanRegister_for_SIBFCX; architecture ScanRegister_arch of ScanRegister_for_SIBFCX is signal and_ce, and_se, and_ue: std_logic; signal internal_si: std_logic_vector(Size downto 0); signal cs_reg: std_logic_vector(Size-1 downto 0); signal u_reg: std_logic_vector(Size-1 downto 0):=ResetValue; signal se_mux, ce_mux, ue_mux: std_logic_vector(Size-1 downto 0); begin -- Basic Combinational Logic and_ce <= CE and SEL; and_se <= SE and SEL; and_ue <= UE and SEL; internal_si(Size) <= SI; -- TDR Shift Register Core SCAN_REGISTER: for i in Size-1 downto 0 generate -- Multiplexers se_mux(i) <= internal_si(i+1) when and_se = '1' else cs_reg(i); ce_mux(i) <= CaptureSource(i) when and_ce = '1' else se_mux(i); ue_mux(i) <= cs_reg(i) when and_ue = '1' else u_reg(i); -- Flip-Flops cs_reg(i) <= ce_mux(i) when TCK'event and TCK = '1'; process(RST,TCK) begin if RST = '1' then u_reg(i) <= ResetValue(Size-1-i); elsif TCK'event and TCK = '0' then u_reg(i) <= ue_mux(i); end if; end process; -- Internal Connections internal_si(i) <= cs_reg(i); end generate; -- Outputs MSBLSB_SO : if BitOrder = "MSBLSB" generate SO <= internal_si(SOSource); end generate; LSBMSB_SO : if BitOrder = "LSBMSB" generate SO <= internal_si(Size-1-SOSource); end generate; ScanRegister_out <= u_reg; ue_mux_out <= ue_mux; end ScanRegister_arch;
gpl-3.0
48e27909017551839500c9798eb335b0
0.606318
3.060606
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/Fault_injector.vhd
13
1,277
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; USE ieee.numeric_std.ALL; use IEEE.math_real."ceil"; use IEEE.math_real."log2"; entity fault_injector is generic(DATA_WIDTH : integer := 32); port( data_in: in std_logic_vector (DATA_WIDTH-1 downto 0); address: in std_logic_vector(integer(ceil(log2(real(DATA_WIDTH))))-1 downto 0); sta_0: in std_logic; sta_1: in std_logic; data_out: out std_logic_vector (DATA_WIDTH-1 downto 0) ); end fault_injector; architecture behavior of fault_injector is signal mask: std_logic_vector (DATA_WIDTH-1 downto 0); begin -- data_in | sta_0 | sta_1 | data_out -- --------|--------|--------|---------- -- 0 | 0 | 0 | 0 -- 1 | 0 | 0 | 1 -- X | 0 | 1 | 1 -- X | 1 | 0 | 0 process (address) begin mask <= (others => '0'); mask(to_integer(unsigned(address))) <= '1'; end process; Gen_faulty: for i in 0 to DATA_WIDTH-1 generate data_out(i) <= (not mask(i) and data_in(i)) or (mask(i) and not sta_0 and not sta_1 and data_in(i)) or (mask(i) and sta_1 and not sta_0) ; --data_out(i) <= data_in(i); end generate; end;
gpl-3.0
99a67a0f5732f32e028be5c3f8927f55
0.547377
2.825221
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/Checkers/Control_Part_Checkers/FIFO_one_hot_credit_based_packet_drop_classifier_support_checkers/RTL/FIFO_one_hot_credit_based_packet_drop_classifier_support_checkers_with_checkers_top.vhd
3
52,963
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity FIFO_credit_based_control_part_with_checkers_top is port ( valid_in : in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; read_pointer: in std_logic_vector(3 downto 0); write_pointer: in std_logic_vector(3 downto 0); state_out: in std_logic_vector(4 downto 0); faulty_packet_out: in std_logic; fake_credit_counter: in std_logic_vector(1 downto 0); flit_type: in std_logic_vector(2 downto 0); fault_out: in std_logic; credit_out: out std_logic; empty_out: out std_logic; full_out: out std_logic; fault_info: out std_logic; health_info: out std_logic; read_en_out: out std_logic; write_en_out: out std_logic; read_pointer_in: out std_logic_vector(3 downto 0); write_pointer_in: out std_logic_vector(3 downto 0); state_in: out std_logic_vector(4 downto 0); faulty_packet_in: out std_logic; fake_credit_out: out std_logic; write_fake_flit_out: out std_logic; fake_credit_counter_in: out std_logic_vector(1 downto 0); -- Checker outputs -- Functional checkers err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot, err_read_pointer_in_onehot, err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full, err_read_pointer_increment, err_read_pointer_not_increment, err_write_en, err_not_write_en, err_not_write_en1, err_not_write_en2, err_read_en_mismatch, err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, --err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out, --err_valid_in_state_out_state_in_not_change, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info, err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, --err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info, err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info, --err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, --err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info, err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_fault_info, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change : out std_logic --err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change --err_state_out_invalid_state_in_state_out_not_change, --err_state_out_invalid_not_fault_info, --err_state_out_invalid_not_health_info, --err_state_out_invalid_not_fake_credit, --err_state_out_invalid_not_write_fake_flit, --err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change: out std_logic ); end FIFO_credit_based_control_part_with_checkers_top; architecture behavior of FIFO_credit_based_control_part_with_checkers_top is component FIFO_credit_based_pseudo is port ( valid_in: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; read_pointer: in std_logic_vector(3 downto 0); write_pointer: in std_logic_vector(3 downto 0); state_out: in std_logic_vector(4 downto 0); faulty_packet_out: in std_logic; fake_credit_counter: in std_logic_vector(1 downto 0); flit_type: in std_logic_vector(2 downto 0); fault_out: in std_logic; credit_out: out std_logic; -- credit_out removed due to creation of pseudo-combinational register, credit_out directly taken to the output interface. empty_out: out std_logic; full_out: out std_logic; fault_info: out std_logic; health_info: out std_logic; read_en_out: out std_logic; write_en_out: out std_logic; read_pointer_in: out std_logic_vector(3 downto 0); write_pointer_in: out std_logic_vector(3 downto 0); state_in: out std_logic_vector(4 downto 0); faulty_packet_in: out std_logic; fake_credit_out: out std_logic; write_fake_flit_out: out std_logic; fake_credit_counter_in: out std_logic_vector(1 downto 0) ); end component; component FIFO_credit_based_control_part_checkers is port ( valid_in: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; read_pointer: in std_logic_vector(3 downto 0); read_pointer_in: in std_logic_vector(3 downto 0); write_pointer: in std_logic_vector(3 downto 0); write_pointer_in: in std_logic_vector(3 downto 0); credit_out: in std_logic; empty_out: in std_logic; full_out: in std_logic; read_en_out: in std_logic; write_en_out: in std_logic; fake_credit: in std_logic; fake_credit_counter: in std_logic_vector(1 downto 0); fake_credit_counter_in: in std_logic_vector(1 downto 0); state_out: in std_logic_vector(4 downto 0); state_in: in std_logic_vector(4 downto 0); fault_info: in std_logic; health_info: in std_logic; faulty_packet_out: in std_logic; faulty_packet_in: in std_logic; flit_type: in std_logic_vector(2 downto 0); fault_out: in std_logic; write_fake_flit: in std_logic; -- Functional checkers err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot, err_read_pointer_in_onehot, err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full, err_read_pointer_increment, err_read_pointer_not_increment, err_write_en, err_not_write_en, err_not_write_en1, err_not_write_en2, err_read_en_mismatch, err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, --err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out, --err_valid_in_state_out_state_in_not_change, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info, err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, --err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info, err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info, --err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, --err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info, err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_fault_info, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change : out std_logic --err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change --err_state_out_invalid_state_in_state_out_not_change, --err_state_out_invalid_not_fault_info, --err_state_out_invalid_not_health_info, --err_state_out_invalid_not_fake_credit, --err_state_out_invalid_not_write_fake_flit, --err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change: out std_logic ); end component; signal credit_out_sig: std_logic; signal empty_out_sig, full_out_sig, fault_info_sig, health_info_sig, read_en_out_sig, write_en_out_sig: std_logic; signal read_pointer_in_sig, write_pointer_in_sig: std_logic_vector(3 downto 0); signal state_in_sig: std_logic_vector(4 downto 0); signal faulty_packet_in_sig: std_logic; signal fake_credit_out_sig: std_logic; signal write_fake_flit_out_sig: std_logic; signal fake_credit_counter_in_sig: std_logic_vector(1 downto 0); begin credit_out <= credit_out_sig; empty_out <= empty_out_sig; full_out <= full_out_sig; fault_info <= fault_info_sig; health_info <= health_info_sig; read_en_out <= read_en_out_sig; write_en_out <= write_en_out_sig; read_pointer_in <= read_pointer_in_sig; write_pointer_in <= write_pointer_in_sig; state_in <= state_in_sig; faulty_packet_in <= faulty_packet_in_sig; fake_credit_out <= fake_credit_out_sig; write_fake_flit_out <= write_fake_flit_out_sig; fake_credit_counter_in <= fake_credit_counter_in_sig; -- Credit-Based FIFO Control Part with Packet dropping instantiation FIFO_CREDIT_BASED_CONTROL_PART_PSEUDO: FIFO_credit_based_pseudo port map ( valid_in => valid_in, read_en_N => read_en_N, read_en_E => read_en_E, read_en_W => read_en_W, read_en_S => read_en_S, read_en_L => read_en_L, read_pointer => read_pointer, write_pointer => write_pointer, state_out => state_out, faulty_packet_out => faulty_packet_out, fake_credit_counter => fake_credit_counter, flit_type => flit_type, fault_out => fault_out, credit_out => credit_out_sig, empty_out => empty_out_sig, full_out => full_out_sig, fault_info => fault_info_sig, health_info => health_info_sig, read_en_out => read_en_out_sig, write_en_out => write_en_out_sig, read_pointer_in => read_pointer_in_sig, write_pointer_in => write_pointer_in_sig, state_in => state_in_sig, faulty_packet_in => faulty_packet_in_sig, fake_credit_out => fake_credit_out_sig, write_fake_flit_out => write_fake_flit_out_sig, fake_credit_counter_in => fake_credit_counter_in_sig ); -- Checkers instantiation CHECKERS: FIFO_credit_based_control_part_checkers port map ( valid_in => valid_in, read_en_N => read_en_N, read_en_E => read_en_E, read_en_W => read_en_W, read_en_S => read_en_S, read_en_L => read_en_L, read_pointer => read_pointer, read_pointer_in => read_pointer_in_sig, write_pointer => write_pointer, write_pointer_in => write_pointer_in_sig, credit_out => credit_out_sig, empty_out => empty_out_sig, full_out => full_out_sig, read_en_out => read_en_out_sig, write_en_out => write_en_out_sig, fake_credit => fake_credit_out_sig, fake_credit_counter => fake_credit_counter, fake_credit_counter_in => fake_credit_counter_in_sig, state_out => state_out, state_in => state_in_sig, fault_info => fault_info_sig, health_info => health_info_sig, faulty_packet_out => faulty_packet_out, faulty_packet_in => faulty_packet_in_sig, flit_type => flit_type, fault_out => fault_out, write_fake_flit => write_fake_flit_out_sig, -- Functional checkers err_empty_full => err_empty_full, err_empty_read_en => err_empty_read_en, err_full_write_en => err_full_write_en, err_state_in_onehot => err_state_in_onehot, err_read_pointer_in_onehot => err_read_pointer_in_onehot, err_write_pointer_in_onehot => err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => err_write_en_write_pointer, err_not_write_en_write_pointer => err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full, err_read_pointer_increment => err_read_pointer_increment, err_read_pointer_not_increment => err_read_pointer_not_increment, err_write_en => err_write_en, err_not_write_en => err_not_write_en, err_not_write_en1 => err_not_write_en1, err_not_write_en2 => err_not_write_en2, err_read_en_mismatch => err_read_en_mismatch, err_read_en_mismatch1 => err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, --err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out, --err_valid_in_state_out_state_in_not_change => err_valid_in_state_out_state_in_not_change, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info => err_state_out_Idle_not_fault_out_not_fault_info, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info => err_state_out_Idle_fault_out_fault_info, err_state_out_Idle_fault_out_faulty_packet_in => err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, --err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info => err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info => err_state_out_Header_flit_valid_in_fault_out_fault_info, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info => err_state_out_Header_flit_not_valid_in_not_fault_info, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => err_state_out_Body_flit_valid_in_not_fault_out_health_info, --err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info => err_state_out_Body_flit_valid_in_not_fault_out_fault_info, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info => err_state_out_Body_flit_valid_in_fault_out_fault_info, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info => err_state_out_Body_flit_not_valid_in_not_fault_info, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, --err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info => err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info => err_state_out_Tail_flit_valid_in_fault_out_fault_info, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info => err_state_out_Tail_flit_not_valid_in_not_fault_info, err_state_out_Tail_flit_not_valid_in_not_fake_credit => err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_fault_info => err_state_out_Packet_drop_not_fault_info, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change --err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change, --err_state_out_invalid_state_in_state_out_not_change => err_state_out_invalid_state_in_state_out_not_change, --err_state_out_invalid_not_fault_info => err_state_out_invalid_not_fault_info, --err_state_out_invalid_not_health_info => err_state_out_invalid_not_health_info, --err_state_out_invalid_not_fake_credit => err_state_out_invalid_not_fake_credit, --err_state_out_invalid_not_write_fake_flit => err_state_out_invalid_not_write_fake_flit, --err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change => err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change ); end behavior;
gpl-3.0
7a0f0b24a741d7988702ad9069e78757
0.544342
3.662978
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/Checkers/Control_Part_Checkers/LBDR_packet_drop_checkers/Rxy_Reconf/RTL/Rxy_Reconf_pseudo.vhd
3
1,147
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity Rxy_Reconf_pseudo is port ( Rxy_reconf: in std_logic_vector(7 downto 0); ReConf_FF_out: in std_logic; Rxy: in std_logic_vector(7 downto 0); Reconfig : in std_logic; flit_type: in std_logic_vector(2 downto 0); grants: in std_logic; empty: in std_logic; Rxy_in: out std_logic_vector(7 downto 0); ReConf_FF_in: out std_logic ); end Rxy_Reconf_pseudo; architecture behavior of Rxy_Reconf_pseudo is begin process(Rxy_reconf, ReConf_FF_out, Rxy, Reconfig, flit_type, grants, empty) begin if ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' then Rxy_in <= Rxy_reconf; ReConf_FF_in <= '0'; else Rxy_in <= Rxy; if Reconfig = '1' then ReConf_FF_in <= '1'; else ReConf_FF_in <= ReConf_FF_out; end if; end if; end process; end;
gpl-3.0
9192a5196ee3e7c834edde2433fa5ff1
0.605057
3.212885
false
true
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/RTL/New_SHMU_on_Node/plasma.vhd
3
15,290
--------------------------------------------------------------------- -- TITLE: Plasma (CPU core with memory) -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 6/4/02 -- FILENAME: plasma.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- This entity combines the CPU core with memory and a UART. -- -- Memory Map: -- 0x00000000 - 0x0000ffff Internal RAM (8KB) -- 0x10000000 - 0x100fffff External RAM (1MB) -- Access all Misc registers with 32-bit accesses -- 0x20000000 Uart Write (will pause CPU if busy) -- 0x20000000 Uart Read -- 0x20000010 IRQ Mask -- 0x20000020 IRQ Status -- 0x20000030 GPIO0 Out Set bits -- 0x20000040 GPIO0 Out Clear bits -- 0x20000050 GPIOA In -- 0x20000060 Counter -- 0x20000070 Ethernet transmit count -- IRQ bits: -- 7 GPIO31 -- 6 ^GPIO31 -- 5 EthernetSendDone -- 4 EthernetReceive -- 3 Counter(18) -- 2 ^Counter(18) -- 1 ^UartWriteBusy -- 0 UartDataAvailable -- modified by: Siavoosh Payandeh Azad -- Change logs: -- * An NI has been instantiated! -- * some changes has been applied to the ports of the CPU to facilitate the new NI! --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity plasma is generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM"; log_file : string := "UNUSED"; ethernet : std_logic := '0'; use_cache : std_logic := '0'; current_address : integer := 0; stim_file: string :="code.txt"); port(clk : in std_logic; reset : in std_logic; uart_write : out std_logic; uart_read : in std_logic; address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_write : out std_logic_vector(31 downto 0); data_read : in std_logic_vector(31 downto 0); mem_pause_in : in std_logic; no_ddr_start : out std_logic; no_ddr_stop : out std_logic; gpio0_out : out std_logic_vector(31 downto 0); gpioA_in : in std_logic_vector(31 downto 0); credit_in : in std_logic; valid_out: out std_logic; TX: out std_logic_vector(31 downto 0); credit_out : out std_logic; valid_in: in std_logic; RX: in std_logic_vector(31 downto 0); link_faults: in std_logic_vector(4 downto 0); turn_faults: in std_logic_vector(7 downto 0); Rxy_reconf_PE: out std_logic_vector(7 downto 0); Cx_reconf_PE: out std_logic_vector(3 downto 0); Reconfig_command : out std_logic ); end; --entity plasma architecture logic of plasma is signal address_next : std_logic_vector(31 downto 2); signal byte_we_next : std_logic_vector(3 downto 0); signal cpu_address : std_logic_vector(31 downto 0); signal cpu_byte_we : std_logic_vector(3 downto 0); signal cpu_data_w : std_logic_vector(31 downto 0); signal cpu_data_r : std_logic_vector(31 downto 0); signal cpu_pause : std_logic; signal data_read_uart : std_logic_vector(7 downto 0); signal write_enable : std_logic; signal eth_pause_in : std_logic; signal eth_pause : std_logic; signal mem_busy : std_logic; signal enable_misc : std_logic; signal enable_uart : std_logic; signal enable_uart_read : std_logic; signal enable_uart_write : std_logic; signal enable_eth : std_logic; signal gpio0_reg : std_logic_vector(31 downto 0); signal uart_write_busy : std_logic; signal uart_data_avail : std_logic; signal irq_mask_reg : std_logic_vector(7 downto 0); signal irq_status : std_logic_vector(7 downto 0); signal irq : std_logic; signal irq_eth_rec : std_logic; signal irq_eth_send : std_logic; signal counter_reg : std_logic_vector(31 downto 0); signal ram_enable : std_logic; signal ram_byte_we : std_logic_vector(3 downto 0); signal ram_address, ram_address_late : std_logic_vector(31 downto 2); signal ram_data_w : std_logic_vector(31 downto 0); signal ram_data_r, ram_data_r_ni : std_logic_vector(31 downto 0); signal NI_irq_out : std_logic; --signal NI_read_flag : std_logic; --signal NI_write_flag : std_logic; signal cache_access : std_logic; signal cache_checking : std_logic; signal cache_miss : std_logic; signal cache_hit : std_logic; constant reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111"; constant reserved_flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; constant reserved_counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001"; begin --architecture write_enable <= '1' when cpu_byte_we /= "0000" else '0'; mem_busy <= eth_pause or mem_pause_in; cache_hit <= cache_checking and not cache_miss; cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy cache_miss or --Cache wait (cpu_address(28) and not cache_hit and mem_busy); --DDR or flash irq_status <= gpioA_in(31) & not gpioA_in(31) & irq_eth_send & irq_eth_rec & counter_reg(18) & not counter_reg(18) & not uart_write_busy & uart_data_avail; irq <= '1' when ((irq_status and irq_mask_reg) /= ZERO(7 downto 0) or (NI_irq_out = '1')) else '0'; -- modified by Behrad gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29); gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0); enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0'; enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0'; enable_uart_read <= enable_uart and not write_enable; enable_uart_write <= enable_uart and write_enable; enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0'; cpu_address(1 downto 0) <= "00"; u1_cpu: mlite_cpu generic map (memory_type => memory_type) PORT MAP ( clk => clk, reset_in => reset, intr_in => irq, --NI_read_flag => NI_read_flag, --NI_write_flag => NI_write_flag, address_next => address_next, --before rising_edge(clk) byte_we_next => byte_we_next, address => cpu_address(31 downto 2), --after rising_edge(clk) byte_we => cpu_byte_we, data_w => cpu_data_w, data_r => cpu_data_r, mem_pause => cpu_pause); opt_cache: if use_cache = '0' generate cache_access <= '0'; cache_checking <= '0'; cache_miss <= '0'; end generate; opt_cache2: if use_cache = '1' generate --Control 4KB unified cache that uses the upper 4KB of the 8KB --internal RAM. Only lowest 2MB of DDR is cached. u_cache: cache generic map (memory_type => memory_type) PORT MAP ( clk => clk, reset => reset, address_next => address_next, byte_we_next => byte_we_next, cpu_address => cpu_address(31 downto 2), mem_busy => mem_busy, cache_access => cache_access, --access 4KB cache cache_checking => cache_checking, --checking if cache hit cache_miss => cache_miss); --cache miss end generate; --opt_cache2 no_ddr_start <= not eth_pause and cache_checking; no_ddr_stop <= not eth_pause and cache_miss; eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking); misc_proc: process(clk, reset, cpu_address, enable_misc, ram_data_r, ram_address_late, ram_data_r_ni, data_read, data_read_uart, cpu_pause, irq_mask_reg, irq_status, gpio0_reg, write_enable, cache_checking, gpioA_in, counter_reg, cpu_data_w) begin case cpu_address(30 downto 28) is when "000" => --internal RAM if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address) or (ram_address_late = reserved_counter_address)) then cpu_data_r <= ram_data_r_ni; else cpu_data_r <= ram_data_r; end if; when "001" => --external RAM if cache_checking = '1' then --cpu_data_r <= ram_data_r; --cache if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address) or (ram_address_late = reserved_counter_address)) then cpu_data_r <= ram_data_r_ni; else cpu_data_r <= ram_data_r; --cache end if; else cpu_data_r <= data_read; --DDR end if; when "010" => --misc case cpu_address(6 downto 4) is when "000" => --uart cpu_data_r <= ZERO(31 downto 8) & data_read_uart; when "001" => --irq_mask cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg; when "010" => --irq_status cpu_data_r <= ZERO(31 downto 8) & irq_status; when "011" => --gpio0 cpu_data_r <= gpio0_reg; when "101" => --gpioA cpu_data_r <= gpioA_in; when "110" => --counter cpu_data_r <= counter_reg; when others => cpu_data_r <= gpioA_in; end case; when "011" => --flash cpu_data_r <= data_read; when others => cpu_data_r <= ZERO; end case; if reset = '1' then irq_mask_reg <= ZERO(7 downto 0); gpio0_reg <= ZERO; counter_reg <= ZERO; elsif rising_edge(clk) then counter_reg <= bv_inc(counter_reg); if cpu_pause = '0' then if enable_misc = '1' and write_enable = '1' then if cpu_address(6 downto 4) = "001" then irq_mask_reg <= cpu_data_w(7 downto 0); elsif cpu_address(6 downto 4) = "011" then gpio0_reg <= gpio0_reg or cpu_data_w; elsif cpu_address(6 downto 4) = "100" then gpio0_reg <= gpio0_reg and not cpu_data_w; elsif cpu_address(6 downto 4) = "110" then counter_reg <= cpu_data_w; end if; end if; end if; end if; end process; process(ram_address, reset, clk)begin if reset = '1' then ram_address_late <= (others => '0'); elsif clk'event and clk = '1' then ram_address_late <= ram_address; end if; end process; ram_proc: process(cache_access, cache_miss, address_next, cpu_address, byte_we_next, cpu_data_w, data_read) begin if cache_access = '1' then --Check if cache hit or write through ram_enable <= '1'; ram_byte_we <= byte_we_next; ram_address(31 downto 2) <= ZERO(31 downto 16) & "0001" & address_next(11 downto 2); ram_data_w <= cpu_data_w; elsif cache_miss = '1' then --Update cache after cache miss ram_enable <= '1'; ram_byte_we <= "1111"; ram_address(31 downto 2) <= ZERO(31 downto 16) & "0001" & cpu_address(11 downto 2); ram_data_w <= data_read; else --Normal non-cache access if address_next(30 downto 28) = "000" then ram_enable <= '1'; else ram_enable <= '0'; end if; ram_byte_we <= byte_we_next; ram_address(31 downto 2) <= address_next(31 downto 2); ram_data_w <= cpu_data_w; end if; end process; u2_ram: ram generic map (memory_type => memory_type, stim_file => stim_file) port map ( clk => clk, reset => reset, enable => ram_enable, write_byte_enable => ram_byte_we, address => ram_address, data_write => ram_data_w, data_read => ram_data_r); u3_uart: uart generic map (log_file => log_file) port map( clk => clk, reset => reset, enable_read => enable_uart_read, enable_write => enable_uart_write, data_in => cpu_data_w(7 downto 0), data_out => data_read_uart, uart_read => uart_read, uart_write => uart_write, busy_write => uart_write_busy, data_avail => uart_data_avail); dma_gen: if ethernet = '0' generate address <= cpu_address(31 downto 2); byte_we <= cpu_byte_we; data_write <= cpu_data_w; eth_pause <= '0'; gpio0_out(28 downto 24) <= ZERO(28 downto 24); irq_eth_rec <= '0'; irq_eth_send <= '0'; end generate; dma_gen2: if ethernet = '1' generate u4_eth: eth_dma port map( clk => clk, reset => reset, enable_eth => gpio0_reg(24), select_eth => enable_eth, rec_isr => irq_eth_rec, send_isr => irq_eth_send, address => address, --to DDR byte_we => byte_we, data_write => data_write, data_read => data_read, pause_in => eth_pause_in, mem_address => cpu_address(31 downto 2), --from CPU mem_byte_we => cpu_byte_we, data_w => cpu_data_w, pause_out => eth_pause, E_RX_CLK => gpioA_in(20), E_RX_DV => gpioA_in(19), E_RXD => gpioA_in(18 downto 15), E_TX_CLK => gpioA_in(14), E_TX_EN => gpio0_out(28), E_TXD => gpio0_out(27 downto 24)); end generate; u4_ni: NI generic map(current_address => current_address, SHMU_address => 0) port map ( clk => clk, reset => reset, enable => ram_enable, write_byte_enable => ram_byte_we, address => ram_address, data_write => ram_data_w, data_read => ram_data_r_ni, --NI_read_flag => NI_read_flag, --NI_write_flag => NI_write_flag, irq_out => NI_irq_out, credit_in => credit_in, valid_out => valid_out, TX => TX, credit_out => credit_out, valid_in => valid_in, RX => RX, link_faults => link_faults, turn_faults => turn_faults, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command => Reconfig_command ); end; --architecture logic
gpl-3.0
5dc70c6f4847480c32aff047803782be
0.531785
3.547564
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/RTL/counter_threshold.vhd
3
4,650
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand -- This design is based on the proposed method, discussed in the following publication: -- "A Fault Prediction Module for a Fault Tolerant NoC Operation" -- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C. library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity counter_threshold_classifier is generic ( counter_depth: integer := 8; healthy_counter_threshold: integer := 4; faulty_counter_threshold: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; faulty_packet, Healthy_packet: in std_logic; Healthy, Intermittent, Faulty:out std_logic ); end counter_threshold_classifier; architecture behavior of counter_threshold_classifier is signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0); -- faulty counter register signals signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0); -- Healthy counter register signals signal NET: std_logic; --no error threshold signal DET: std_logic; --detected error threshold signal reset_counters: std_logic; -- reset signal generated when a threshold is reached! TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state); SIGNAL state, next_state : STATE_TYPE := Healthy_state; begin -- clock block process(clk, reset)begin if reset = '0' then faulty_counter_out <= (others => '0'); healthy_counter_out <= (others => '0'); state <= Healthy_state; -- It is assumed that the link is always healthy in the beginning elsif clk'event and clk = '1' then faulty_counter_out <= faulty_counter_in; healthy_counter_out <= healthy_counter_in; state <= next_state; end if; end process; --- everything below this line is pure combinatorial! -- updating the faulty counter process(faulty_packet, reset_counters, faulty_counter_out)begin if reset_counters = '1' then faulty_counter_in <= (others => '0'); elsif faulty_packet = '1' then faulty_counter_in <= faulty_counter_out + 1; else faulty_counter_in <= faulty_counter_out; end if; end process; -- updating the healthy counter process(Healthy_packet, reset_counters, healthy_counter_out)begin if reset_counters = '1' then healthy_counter_in <= (others => '0'); elsif Healthy_packet = '1' then healthy_counter_in <= healthy_counter_out + 1; else healthy_counter_in <= healthy_counter_out; end if; end process; -- checking the counters against threshold values! -- if a counter reaches threshold value it resets both signals! process(healthy_counter_out, faulty_counter_out) begin reset_counters <= '0'; DET <= '0'; NET <= '0'; if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then NET <= '1'; reset_counters <= '1'; end if; if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then DET <= '1'; reset_counters <= '1'; end if; end process; -- Counter threshold FSM -- .__________. DET/Intermittent .---------------. DET/Faulty .---------------. -- | HEALTHY | -----------------> | INTERMITTENT | -------------->| FAULTY | -- | STATE | <----------------- | STATE | | STATE | -- '----------' NET/healthy '---------------' '---------------' -- process (NET, DET, state)begin -- Default values Healthy <= '0'; Intermittent <= '0'; Faulty <= '0'; case state is when Healthy_state => if NET = '1' then next_state <= Healthy_state; elsif DET = '1' then next_state <= Intermittent_state; Intermittent <= '1'; else next_state <= Healthy_state; end if; when Intermittent_state => if NET = '1' then next_state <= Healthy_state; Healthy <= '1'; elsif DET = '1' then next_state <= Faulty_state; Faulty <= '1'; else next_state <= Intermittent_state; end if; when Faulty_state => next_state <= Faulty_state; when others => -- just for sysnthesis tools next_state <= Healthy_state; Healthy <= '1'; end case; end process; END;
gpl-3.0
b4eda1ce1a95baecc7b3ac415b0458d1
0.604086
3.814602
false
false
false
false
AndyMcC0/UVVM_All
bitvis_uart/src/uart_pkg.vhd
3
3,191
--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <[email protected]>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package uart_pkg is function find_num_hits( vector : std_logic_vector; pattern : std_logic) return integer; function find_most_repeated_bit( vector : std_logic_vector) return std_logic; function transient_error( vector : std_logic_vector; limit : integer) return boolean; function f_log2 (x : positive) return natural; function odd_parity ( signal data : std_logic_vector(7 downto 0)) return std_logic; end package uart_pkg; package body uart_pkg is function find_num_hits( vector : std_logic_vector; pattern : std_logic) return integer is variable hitcount : natural := 0; begin for i in 0 to vector'length-1 loop if (vector(i) = pattern) then hitcount := hitcount+1; end if; end loop; return hitcount; end function; function find_most_repeated_bit( vector : std_logic_vector) return std_logic is begin if (find_num_hits(vector,'1') > find_num_hits(vector,'0')) then return '1'; else return '0'; end if; end function; function transient_error( vector : std_logic_vector; limit : integer) return boolean is begin if ((find_num_hits(vector,'1') < limit) and (find_num_hits(vector,'0') < limit)) then return true; else return false; end if; end function; function f_log2 (x : positive) return natural is variable i : natural; begin i := 0; while (2**i < x) and i < 31 loop i := i + 1; end loop; return i; end function; function odd_parity ( signal data : std_logic_vector(7 downto 0)) return std_logic is variable odd : std_logic; begin odd := '1'; for i in data'range loop odd := odd xor data(i); end loop; return odd; end odd_parity; end package body uart_pkg;
mit
2d0248197e4da608c43d5cf0282f7e6a
0.555312
4.300539
false
false
false
false
FlatTargetInk/Spartan-HW
Top_Level.vhd
1
2,510
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 21:35:50 03/25/2017 -- Design Name: -- Module Name: Top_Level - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Top_Level is Port( CLK : in STD_LOGIC; BTN_NORTH : in STD_LOGIC; BTN_SOUTH : in STD_LOGIC; BTN_EAST : in STD_LOGIC; BTN_WEST : in STD_LOGIC; ROT_CENTER : in STD_LOGIC; ROT_A : in STD_LOGIC; ROT_B : in STD_LOGIC; SW : in STD_LOGIC_VECTOR(3 downto 0); LED : out STD_LOGIC_VECTOR(7 downto 0)); end Top_Level; architecture Structural of Top_Level is ----> Management <---- signal RESET : STD_LOGIC := '0'; signal BTNS : STD_LOGIC_VECTOR(3 downto 0); signal T_ROTIN : STD_LOGIC_VECTOR(1 downto 0); ----> Inputs <---- signal SCLK : STD_LOGIC := '0'; signal ENABLE : STD_LOGIC := '1'; -- May want to drive this signal with a switch signal DBTN : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0'); signal ROTARY : STD_LOGIC_VECTOR (1 downto 0) := (OTHERS => '0'); -- 1 means left, 0 means right, signaled by state transition ----> Outputs <---- signal LED_OUT : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0'); begin ------ Place UUT Here ------ ---------------------------- -- Incrementer: entity work.led_increment -- port map(INPUT => ROTARY(0), -- EN => ENABLE, -- RST => RESET, -- LEDS => LED_OUT); LED_OUT <= "000000" & ROTARY; ------ Hardware Units ------ ---------------------------- BTNS <= BTN_EAST & ROT_CENTER & BTN_NORTH & BTN_WEST; Button_Debounce: entity work.button_debounce port map(CLK => CLK, EN => ENABLE, BTN => BTNS, DBTN => DBTN); T_ROTIN <= ROT_A & ROT_B; Rotary_Encoder: entity work.rotary_debounce port map(CLK => CLK, EN => ENABLE, ROTIN => T_ROTIN, ROUT => ROTARY); LED <= LED_OUT; RESET <= BTN_SOUTH; end Structural; -- vim:set ts=3 sw=3 noexpandtab:
mit
d049f6adc6b3ea52cfb15ec74247de66
0.5749
3.1375
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/SIB_mux_pre.vhd
3
3,021
--Copyright (C) 2017 Dmitri Mihhailov library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity SIB_mux_pre is Port ( -- Scan Interface client -------------- SI : in STD_LOGIC; -- ScanInPort CE : in STD_LOGIC; -- CaptureEnPort SE : in STD_LOGIC; -- ShiftEnPort UE : in STD_LOGIC; -- UpdateEnPort SEL : in STD_LOGIC; -- SelectPort RST : in STD_LOGIC; -- ResetPort TCK : in STD_LOGIC; -- TCKPort SO : out STD_LOGIC; -- ScanOutPort -- Scan Interface host ---------------- fromSO : in STD_LOGIC; -- ScanInPort toCE : out STD_LOGIC; -- ToCaptureEnPort toSE : out STD_LOGIC; -- ToShiftEnPort toUE : out STD_LOGIC; -- ToUpdateEnPort toSEL : out STD_LOGIC; -- ToSelectPort toRST : out STD_LOGIC; -- ToResetPort toTCK : out STD_LOGIC; -- ToTCKPort toSI : out STD_LOGIC); -- ScanOutPort end SIB_mux_pre; architecture SIB_mux_pre_arch of SIB_mux_pre is component ScanRegister is Generic (Size : positive; BitOrder : string; -- MSBLSB / LSBMSB SOSource : natural; ResetValue : STD_LOGIC_VECTOR); Port ( SI : in STD_LOGIC; CE : in STD_LOGIC; SE : in STD_LOGIC; UE : in STD_LOGIC; SEL : in STD_LOGIC; RST : in STD_LOGIC; TCK : in STD_LOGIC; SO : out STD_LOGIC; CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0); ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0)); end component; signal SR_so : STD_LOGIC; signal SR_do : STD_LOGIC_VECTOR (0 downto 0); component ScanMux is Generic (ControlSize : positive); Port ( ScanMux_in : in STD_LOGIC_VECTOR((2**ControlSize)-1 downto 0); SelectedBy : in STD_LOGIC_VECTOR(ControlSize-1 downto 0); ScanMux_out : out STD_LOGIC); end component; signal SIBmux_out : STD_LOGIC; begin SO <= SR_so; -- Source SR toCE <= CE; toSE <= SE; toUE <= UE; toSEL <= SEL and SR_do(0); -- SEL & SR.DO toRST <= RST; toTCK <= TCK; toSI <= SI; -- Source SI SR : ScanRegister Generic map (Size => 1, BitOrder => "MSBLSB", -- MSBLSB / LSBMSB SOSource => 0, ResetValue => "0") -- ResetValue 1'b0 Port map ( SI => SIBmux_out, -- ScanInSource SIBmux_out CE => CE, SE => SE, UE => UE, SEL => SEL, RST => RST, TCK => TCK, SO => SR_so, CaptureSource => SR_do, -- CaptureSource SR ScanRegister_out => SR_do); SIBmux : ScanMux Generic map ( ControlSize => 1) Port map ( ScanMux_in(0) => SI, -- 1'b0 : SI ScanMux_in(1) => fromSO, -- 1'b1 : fromSO SelectedBy => SR_do, --SelectedBy SR ScanMux_out => SIBmux_out); end SIB_mux_pre_arch;
gpl-3.0
91f47c4c7c9ac0b742d8a20146814f1e
0.520357
3.928479
false
false
false
false
simoesusp/Processador-ICMC
Processor_FPGA/Processor_Template_VHDL_DE115/cpu.vhd
1
30,535
-- Processador Versao 3: 08/07/2022 -- Video com 16 cores e tela de 40 colunas por 30 linhas libraRY ieee; use ieee.std_LOGIC_1164.all; use ieee.std_LOGIC_ARITH.all; use ieee.std_LOGIC_unsigned.all; entity cpu is port( clk : in std_LOGIC; reset : in std_LOGIC; Mem : in STD_LOGIC_VECTOR(15 downto 0); M5 : out STD_LOGIC_VECTOR(15 downto 0); M1 : out STD_LOGIC_VECTOR(15 downto 0); RW : out std_LOGIC; key : in STD_LOGIC_VECTOR(7 downto 0); videoflag : out std_LOGIC; vga_pos : out STD_LOGIC_VECTOR(15 downto 0); vga_char : out STD_LOGIC_VECTOR(15 downto 0); Ponto : out STD_LOGIC_VECTOR(2 downto 0); halt_ack : out std_LOGIC; halt_req : in std_LOGIC; PC_data : out STD_LOGIC_VECTOR(15 downto 0); break : out STD_LOGIC ); end cpu; ARCHITECTURE main of cpu is TYPE STATES is (fetch, decode, exec, exec2, halted); -- Estados da Maquina de Controle do Processador TYPE Registers is array(0 to 7) of STD_LOGIC_VECTOR(15 downto 0); -- Banco de Registradores TYPE LoadRegisters is array(0 to 7) of std_LOGIC; -- Sinais de LOAD dos Registradores do Banco -- INSTRUCTION SET: 29 INSTRUCTIONS -- Data Manipulation Instructions: -- Usage -- Action -- Format CONSTANT LOAD : STD_LOGIC_VECTOR(5 downto 0) := "110000"; -- LOAD RX END -- RX <- M[END] Format: < inst(6) | RX(3) | xxxxxxx > + 16bit END CONSTANT STORE : STD_LOGIC_VECTOR(5 downto 0) := "110001"; -- STORE END RX -- M[END] <- RX Format: < inst(6) | RX(3) | xxxxxxx > + 16bit END CONSTANT LOADIMED : STD_LOGIC_VECTOR(5 downto 0) := "111000"; -- LOADN RX Nr -- RX <- Nr Format: < inst(6) | RX(3) | xxxxxxb0 > + 16bit Numero CONSTANT LOADINDEX : STD_LOGIC_VECTOR(5 downto 0) := "111100"; -- LOADI RX RY -- RX <- M[RY] Format: < inst(6) | RX(3) | RY(3) | xxxx > CONSTANT STOREINDEX : STD_LOGIC_VECTOR(5 downto 0) := "111101"; -- STOREI RX RY -- M[RX] <- RY Format: < inst(6) | RX(3) | RY(3) | xxxx > CONSTANT MOV : STD_LOGIC_VECTOR(5 downto 0) := "110011"; -- MOV RX RY -- RX <- RY Format: < inst(6) | RX(3) | RY(3) | xx | x0 > -- MOV RX SP RX <- SP Format: < inst(6) | RX(3) | xxx | xx | 01 > -- MOV SP RX SP <- RX Format: < inst(6) | RX(3) | xxx | xx | 11 > -- I/O Instructions: CONSTANT OUTCHAR : STD_LOGIC_VECTOR(5 downto 0) := "110010"; -- OUTCHAR RX RY -- Video[RY] <- Char(RX) Format: < inst(6) | RX(3) | RY(3) | xxxx > -- RX contem o codigo do caracter de 0 a 127, sendo que 96 iniciais estao prontos com a tabela ASCII -- RX(6 downto 0) + 32 = Caractere da tabela ASCII - Ver Manual PDF -- RX(10 downto 7) = Cor : 0-branco, 1-marrom, 2-verde, 3-oliva, 4-azul marinho, 5-roxo, 6-teal, 7-prata, 8-cinza, 9-vermelho, 10-lima, 11-amarelo, 12-azul, 13-rosa, 14-aqua, 15-preto -- RY(10 downto 0) = tamanho da tela = 30 linhas x 40 colunas: posicao continua de 0 a 1199 no RY CONSTANT INCHAR : STD_LOGIC_VECTOR(5 downto 0) := "110101"; -- INCHAR RX -- RX[5..0] <- KeyPressed RX[15..6] <- 0's Format: < inst(6) | RX(3) | xxxxxxx > -- Se nao pressionar nenhuma tecla, RX recebe 00FF CONSTANT ARITH : STD_LOGIC_VECTOR(1 downto 0) := "10"; -- Aritmethic Instructions(All should begin wiht "10"): CONSTANT ADD : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- ADD RX RY RZ / ADDC RX RY RZ -- RX <- RY + RZ / RX <- RY + RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C > CONSTANT SUB : STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- SUB RX RY RZ / SUBC RX RY RZ -- RX <- RY - RZ / RX <- RY - RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C > CONSTANT MULT : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- MUL RX RY RZ / MUL RX RY RZ -- RX <- RY * RZ / RX <- RY * RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C > CONSTANT DIV : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- DIV RX RY RZ -- RX <- RY / RZ / RX <- RY / RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C > CONSTANT INC : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- INC RX / DEC RX -- RX <- RX + 1 / RX <- RX - 1 -- b6= INC/DEC : 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx > CONSTANT LMOD : STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- MOD RX RY RZ -- RX <- RY MOD RZ Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x > CONSTANT LOGIC : STD_LOGIC_VECTOR(1 downto 0) := "01"; -- LOGIC Instructions (All should begin wiht "01"): CONSTANT LAND : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- AND RX RY RZ -- RZ <- RX AND RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x > CONSTANT LOR : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- OR RX RY RZ -- RZ <- RX OR RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x > CONSTANT LXOR : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- XOR RX RY RZ -- RZ <- RX XOR RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x > CONSTANT LNOT : STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- NOT RX RY -- RX <- NOT(RY) Format: < inst(6) | RX(3) | RY(3) | xxxx > CONSTANT SHIFT : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- SHIFTL0 RX,n / SHIFTL1 RX,n / SHIFTR0 RX,n / SHIFTR1 RX,n / ROTL RX,n / ROTR RX,n -- SHIFT/Rotate RX -- b6=shif/rotate: 0/1 b5=left/right: 0/1; b4=fill; -- Format: < inst(6) | RX(3) | b6 b5 b4 | nnnn > CONSTANT CMP : STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- CMP RX RY -- Compare RX and RY and set FR : Format: < inst(6) | RX(3) | RY(3) | xxxx > Flag Register: <...DIVbyZero|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater> -- JMP Condition: (UNconditional, EQual, Not Equal, Zero, Not Zero, CarRY, Not CarRY, GReater, LEsser, Equal or Greater, Equal or Lesser, OVerflow, Not OVerflow, Negative, DIVbyZero, NOT USED) -- FLOW CONTROL Instructions: CONSTANT JMP : STD_LOGIC_VECTOR(5 downto 0) := "000010"; -- JMP END -- PC <- 16bit END : b9-b6 = COND Format: < inst(6) | COND(4) | xxxxxx > + 16bit END CONSTANT CALL : STD_LOGIC_VECTOR(5 downto 0) := "000011"; -- CALL END -- M[SP] <- PC | SP-- | PC <- 16bit END : b9-b6 = COND Format: < inst(6) | COND(4) | xxxxxx > + 16bit END CONSTANT RTS : STD_LOGIC_VECTOR(5 downto 0) := "000100"; -- RTS -- SP++ | PC <- M[SP] | b6=RX/FR: 1/0 Format: < inst(6) | xxxxxxxxxx > CONSTANT PUSH : STD_LOGIC_VECTOR(5 downto 0) := "000101"; -- PUSH RX / PUSH FR -- M[SP] <- RX / M[SP] <- FR | SP-- : b6=RX/FR: 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx > CONSTANT POP : STD_LOGIC_VECTOR(5 downto 0) := "000110"; -- POP RX / POP FR -- SP++ | RX <- M[SP] / FR <- M[SP] : b6=RX/FR: 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx > -- Control Instructions: CONSTANT NOP : STD_LOGIC_VECTOR(5 downto 0) := "000000"; -- NOP -- Do Nothing Format: < inst(6) | xxxxxxxxxx > CONSTANT HALT : STD_LOGIC_VECTOR(5 downto 0) := "001111"; -- HALT -- StOP Here Format: < inst(6) | xxxxxxxxxx > CONSTANT SETC : STD_LOGIC_VECTOR(5 downto 0) := "001000"; -- CLEARC / SETC -- Set/Clear CarRY: b9 = 1-set; 0-clear Format: < inst(6) | b9 | xxxxxxxxx > CONSTANT BREAKP : STD_LOGIC_VECTOR(5 downto 0) := "001110"; -- BREAK POINT -- Switch to manual clock Format: < inst(6) | xxxxxxxxxx > -- CONSTANTes para controle do Mux2: Estes sinais selecionam as respectivas entradas para o Mux2 CONSTANT sULA : STD_LOGIC_VECTOR (2 downto 0) := "000"; CONSTANT sMem : STD_LOGIC_VECTOR (2 downto 0) := "001"; CONSTANT sM4 : STD_LOGIC_VECTOR (2 downto 0) := "010"; CONSTANT sTECLADO : STD_LOGIC_VECTOR (2 downto 0) := "011"; -- nao tinha CONSTANT sSP : STD_LOGIC_VECTOR (2 downto 0) := "100"; -- Sinais para o Processo da ULA signal OP : STD_LOGIC_VECTOR(6 downto 0); -- OP(6) deve ser setado para OPeracoes com carRY signal x, y, result : STD_LOGIC_VECTOR(15 downto 0); signal FR : STD_LOGIC_VECTOR(15 downto 0); -- Flag Register: <...DIVbyZero|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater> signal auxFR : STD_LOGIC_VECTOR(15 downto 0); -- Representa um barramento conectando a ULA ao Mux6 para escrever no FR begin -- Maquina de Controle process(clk, reset) --Register Declaration: variable PC : STD_LOGIC_VECTOR(15 downto 0); -- Program Counter variable IR : STD_LOGIC_VECTOR(15 downto 0); -- Instruction Register variable SP : STD_LOGIC_VECTOR(15 downto 0); -- Stack Pointer variable MAR : STD_LOGIC_VECTOR(15 downto 0); -- Memory address Register VARIABLE TECLADO :STD_LOGIC_VECTOR(15 downto 0); -- Registrador para receber dados do teclado -- nao tinha variable reg : Registers; -- Mux dos barramentos de dados internos VARIABLE M2 :STD_LOGIC_VECTOR(15 downto 0); -- Mux dos barramentos de dados internos para os Registradores VARIABLE M3, M4 :STD_LOGIC_VECTOR(15 downto 0); -- Mux dos Registradores para as entradas da ULA VARIABLE M6 :STD_LOGIC_VECTOR(15 downto 0); -- Mux do Flag Register -- Novos Sinais da Versao 2: Controle dos registradores internos (Load-Inc-Dec) variable LoadReg : LoadRegisters; variable LoadIR : std_LOGIC; variable LoadMAR : std_LOGIC; variable LoadPC : std_LOGIC; variable IncPC : std_LOGIC; VARIABLE LoadSP : STD_LOGIC; variable IncSP : std_LOGIC; variable DecSP : std_LOGIC; variable LoadFR : std_LOGIC; -- Selecao dos Mux 2 e 6 variable selM2 : STD_LOGIC_VECTOR(2 downto 0); variable selM6 : STD_LOGIC_VECTOR(2 downto 0); VARIABLE BreakFlag : STD_LOGIC; -- Para sinalizar a mudanca para Clock manual/Clock Automatico para a nova instrucao Break variable state : STATES; -- Estados do processador: fetch, decode, exec, halted -- Seletores dos registradores para execussao das instrucoes variable RX : integer; variable RY : integer; variable RZ : integer; begin if(reset = '1') then state := fetch; -- inicializa o estado na busca! M1(15 downto 0) <= x"0000"; -- inicializa na linha Zero da memoria -> Programa tem que comecar na linha Zero !! videoflag <= '0'; RX := 0; RY := 0; RZ := 0; RW <= '0'; LoadIR := '0'; LoadMAR := '0'; LoadPC := '0'; IncPC := '0'; IncSP := '0'; DecSP := '0'; LoadSP := '0'; LoadFR := '0'; selM2 := sMem; selM6 := sULA; LoadReg(0) := '0'; LoadReg(1) := '0'; LoadReg(2) := '0'; LoadReg(3) := '0'; LoadReg(4) := '0'; LoadReg(5) := '0'; LoadReg(6) := '0'; LoadReg(7) := '0'; REG(0) := x"0000"; REG(1) := x"0000"; REG(2) := x"0000"; REG(3) := x"0000"; REG(4) := x"0000"; REG(5) := x"0000"; REG(6) := x"0000"; REG(7) := x"0000"; PC := x"0000"; -- inicializa na linha Zero da memoria -> Programa tem que comecar na linha Zero !! SP := x"7ffc"; -- Inicializa a Pilha no final da mem�ria: 7ffc IR := x"0000"; MAR := x"0000"; BreakFlag:= '0'; -- Break Point Flag BREAK <= '0'; -- Break Point output to switch to manual clock -- Novo na Versao 3 HALT_ack <= '0'; elsif(clk'event and clk = '1') then if(LoadIR = '1') then IR := Mem; end if; if(LoadPC = '1') then PC := Mem; end if; if(IncPC = '1') then PC := PC + x"0001"; end if; if(LoadMAR = '1') then MAR := Mem; end if; if(LoadSP = '1') then SP := M4; end if; if(IncSP = '1') then SP := SP + x"0001"; end if; if(DecSP = '1') then SP := SP - x"0001"; end if; -- Selecao do Mux6 if (selM6 = sULA) THEN M6 := auxFR; -- Sempre recebe flags da ULA ELSIF (selM6 = sMem) THEN M6 := Mem; END IF; -- A menos que seja POP FR, quando recebe da Memoria -- So' carrega o FR quando for Pop FR, Cmp, aritmethic, ou logic. if(LoadFR = '1') then FR <= M6; end if; -- Atualiza o nome dos registradores!!! RX := conv_integer(IR(9 downto 7)); RY := conv_integer(IR(6 downto 4)); RZ := conv_integer(IR(3 downto 1)); -- Selecao do Mux2 if (selM2 = sULA) THEN M2 := RESULT; ELSIF (selM2 = sMem) THEN M2 := Mem; ELSIF (selM2 = sM4) THEN M2 := M4; ELSIF (selM2 = sTECLADO)THEN M2 := TECLADO; ELSIF (selM2 = sSP) THEN M2 := SP; END IF; -- Carrega dados do Mux 2 para os registradores if(LoadReg(RX) = '1') then reg(RX) := M2; end if; -- Reseta os sinais de controle APOS usa-los acima -- Zera todos os sinais de controle, para depois ligar um por um nas instrucoes a medida que for necessario: a ultima atribuicao e' a que vale no processo!!! LoadIR := '0'; LoadMAR := '0'; LoadPC := '0'; IncPC := '0'; IncSP := '0'; DecSP := '0'; LoadSP := '0'; LoadFR := '0'; selM6 := sULA; -- Sempre atualiza o FR da ULA, a nao ser que a instrucao seja POP FR LoadReg(0) := '0'; LoadReg(1) := '0'; LoadReg(2) := '0'; LoadReg(3) := '0'; LoadReg(4) := '0'; LoadReg(5) := '0'; LoadReg(6) := '0'; LoadReg(7) := '0'; videoflag <= '0'; -- Abaixa o sinal para a "Placa de Video" : sobe a cada OUTCHAR RW <= '0'; -- Sinal de Letura/Ecrita da mem�ria em Leitura (0 - ler, 1 - escrever) -- Novo na Versao 3 if(halt_req = '1') then state := halted; end if; -- Novo na Versao 3: para escrever PC no LCD da placa PC_data <= PC; case state is --************************************************************************ -- FETCH STATE --************************************************************************ when fetch => PONTO <= "001"; -- Inicio das acoes do ciclo de Busca !! M1 <= PC; RW <= '0'; LoadIR := '1'; IncPC := '1'; STATE := decode; -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX --************************************************************************ -- DECODE STATE --************************************************************************ when decode => PONTO <= "010"; --======================================================================== -- INCHAR RX[7..0] <- KeyPressed RX[15..8] <- 0 --======================================================================== IF(IR(15 DOWNTO 10) = INCHAR) THEN -- Se nenhuma tecla for pressionada no momento da leitura, Rx <- x"00FF" TECLADO(7 downto 0) := key(7 downto 0); TECLADO(15 downto 8) := X"00"; selM2 := sTECLADO; LoadReg(RX) := '1'; state := fetch; END IF; --======================================================================== -- OUTCHAR Video[RY] <- Char(RX) --======================================================================== IF(IR(15 DOWNTO 10) = OUTCHAR) THEN M3 := Reg(Rx); -- M3 <- Rx M4 := Reg(Ry); -- M4 <- Ry -- Este bloco troca a cor do preto pelo branco: agora a cor "0000" = Branco ! if( M3(11 downto 8) = "0000" ) then M3(11 downto 8) := "1111"; elsif( M3(11 downto 8) = "1111" ) then M3(11 downto 8) := "0000"; end if; vga_char <= M3; --vga_char <= M3 : C�digo do Character vem do Rx via M3 vga_pos <= M4; -- Posicao na tela do Character vem do Ry via M4 videoflag <= '1'; -- Sobe o videoflag para gravar o charactere na mem�ria de video state := fetch; END IF; --======================================================================== -- LOAD Imediato RX <- Nr --======================================================================== IF(IR(15 DOWNTO 10) = LOADIMED) THEN M1 <= PC; -- M1 <- PC Rw <= '0'; -- Rw <= '0' selM2 := sMeM; -- M2 <- MEM LoadReg(RX) := '1'; -- LRx <- 1 IncPC := '1'; -- IncPC <- 1 state := fetch; END IF; --======================================================================== -- LOAD Direto RX <- M[End] --======================================================================== IF(IR(15 DOWNTO 10) = LOAD) THEN -- Busca o endereco state := exec; -- Vai para o estado de Executa para buscar o dado do endereco END IF; --======================================================================== -- STORE DIReto M[END] <- RX --======================================================================== IF(IR(15 DOWNTO 10) = STORE) THEN -- Busca o endereco state := exec; -- Vai para o estado de Executa para gravar Registrador no endereco END IF; --======================================================================== -- LOAD Indexado por registrador RX <- M(RY) --======================================================================== IF(IR(15 DOWNTO 10) = LOADINDEX) THEN state := fetch; END IF; --======================================================================== -- STORE indexado por registrador M[RX] <- RY --======================================================================== IF(IR(15 DOWNTO 10) = STOREINDEX) THEN state := fetch; END IF; --======================================================================== -- MOV RX/SP <- RY/SP -- MOV RX RY RX <- RY Format: < inst(6) | RX(3) | RY(3) | xx | x0 > -- MOV RX SP RX <- SP Format: < inst(6) | RX(3) | xxx | xx | 01 > -- MOV SP RX SP <- RX Format: < inst(6) | RX(3) | xxx | xx | 11 > --======================================================================== IF(IR(15 DOWNTO 10) = MOV) THEN state := fetch; END IF; --======================================================================== -- ARITH OPERATION ('INC' NOT INCLUDED) RX <- RY (?) RZ --======================================================================== IF(IR(15 DOWNTO 14) = ARITH AND IR(13 DOWNTO 10) /= INC) THEN state := fetch; END IF; --======================================================================== -- INC/DEC RX <- RX (+ or -) 1 --======================================================================== IF(IR(15 DOWNTO 14) = ARITH AND (IR(13 DOWNTO 10) = INC)) THEN state := fetch; END IF; --======================================================================== -- LOGIC OPERATION ('SHIFT', and 'CMP' NOT INCLUDED) RX <- RY (?) RZ --======================================================================== IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) /= SHIFT AND IR(13 DOWNTO 10) /= CMP) THEN state := fetch; END IF; --======================================================================== -- SHIFT RX, RY RX <- SHIFT[ RY] ROTATE INCluded ! --======================================================================== IF(IR(15 DOWNTO 14) = LOGIC and (IR(13 DOWNTO 10) = SHIFT)) THEN if(IR(6 DOWNTO 4) = "000") then -- SHIFT LEFT 0 Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))sll conv_integer(IR(3 DOWNTO 0))); elsif(IR(6 DOWNTO 4) = "001") then -- SHIFT LEFT 1 Reg(RX) := not (To_StdLOGICVector(to_bitvector(not Reg(RY))sll conv_integer(IR(3 DOWNTO 0)))); elsif(IR(6 DOWNTO 4) = "010") then -- SHIFT RIGHT 0 Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))srl conv_integer(IR(3 DOWNTO 0))); elsif(IR(6 DOWNTO 4) = "011") then -- SHIFT RIGHT 0 Reg(RX) := not (To_StdLOGICVector(to_bitvector(not Reg(RY))srl conv_integer(IR(3 DOWNTO 0)))); elsif(IR(6 DOWNTO 5) = "11") then -- ROTATE RIGHT Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))ror conv_integer(IR(3 DOWNTO 0))); elsif(IR(6 DOWNTO 5) = "10") then -- ROTATE LEFT Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))rol conv_integer(IR(3 DOWNTO 0))); end if; state := fetch; end if; --======================================================================== -- CMP RX, RY --======================================================================== IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) = CMP) THEN state := fetch; END IF; --======================================================================== -- JMP END PC <- 16bit END : b9-b6 = COND -- Flag Register: <...Negative|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater> -- JMP Condition: (UNconditional, EQual, Not Equal, Zero, Not Zero, CarRY, Not CarRY, GReater, LEsser, Equal or Greater, Equal or Lesser, OVerflow, Not OVerflow, Negative, DIVbyZero, NOT USED) --======================================================================== IF(IR(15 DOWNTO 10) = JMP) THEN IF((IR(9 DOWNTO 6) = "0000") OR ((IR(9 DOWNTO 6) = "0111") AND FR(0) = '1') OR ((IR(9 DOWNTO 6) = "1001") AND (FR(2) = '1' OR FR(0) = '1')) OR ((IR(9 DOWNTO 6) = "1000") AND FR(1) = '1') OR ((IR(9 DOWNTO 6) = "1010") AND (FR(2) = '1' OR FR(1) = '1')) OR ((IR(9 DOWNTO 6) = "0001") AND FR(2) = '1') OR ((IR(9 DOWNTO 6) = "0010") AND FR(2) = '0') OR ((IR(9 DOWNTO 6) = "0011") AND FR(3) = '1') OR ((IR(9 DOWNTO 6) = "0100") AND FR(3) = '0') OR ((IR(9 DOWNTO 6) = "0101") AND FR(4) = '1') OR ((IR(9 DOWNTO 6) = "0110") AND FR(4) = '0') OR ((IR(9 DOWNTO 6) = "1011") AND FR(5) = '1') OR ((IR(9 DOWNTO 6) = "1100") AND FR(5) = '0') OR ((IR(9 DOWNTO 6) = "1101") AND FR(6) = '1') OR ((IR(9 DOWNTO 6) = "1110") AND FR(9) = '1')) THEN M1 <= PC; -- M1 <- PC Rw <= '0'; -- Rw <= '0' LoadPC := '1'; -- LoadPC <- 1 ELSE IncPC := '1'; END IF; state := fetch; END IF; --======================================================================== -- CALL END PC <- 16bit END : b9-b6 = COND PUSH(PC) -- Flag Register: <...Negative|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater> -- JMP Condition: (UNconditional, EQual, Not Equal, Zero, Not Zero, CarRY, Not CarRY, GReater, LEsser, Equal or Greater, Equal or Lesser, OVerflow, Not OVerflow, Negative, DIVbyZero, NOT USED) --======================================================================== IF(IR(15 DOWNTO 10) = CALL) THEN END IF; --======================================================================== -- RTS PC <- Mem[SP] --======================================================================== IF(IR(15 DOWNTO 10) = RTS) THEN state := exec; END IF; --======================================================================== -- PUSH RX --======================================================================== IF(IR(15 DOWNTO 10) = PUSH) THEN state := fetch; END IF; --======================================================================== -- POP RX --======================================================================== IF(IR(15 DOWNTO 10) = POP) THEN state := exec; END IF; --======================================================================== -- NOP --======================================================================== IF( IR(15 DOWNTO 10) = NOP) THEN state := fetch; end if; --======================================================================== -- HALT --======================================================================== IF( IR(15 DOWNTO 10) = HALT) THEN state := halted; END IF; --======================================================================== -- SETC/CLEARC --======================================================================== IF( IR(15 DOWNTO 10) = SETC) THEN FR(4) <= IR(9); -- Bit 9 define se vai ser SET ou CLEAR state := fetch; end if; --======================================================================== -- BREAKP --======================================================================== IF( IR(15 DOWNTO 10) = BREAKP) THEN BreakFlag := not(BreakFlag); -- Troca entre clock manual e clock autom�tico BREAK <= BreakFlag; state := fetch; PONTO <= "101"; END IF; -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX --************************************************************************ -- EXECUTE STATE --************************************************************************ when exec => PONTO <= "100"; --======================================================================== -- EXEC LOAD DIReto RX <- M[END] --======================================================================== IF(IR(15 DOWNTO 10) = LOAD) THEN state := fetch; END IF; --======================================================================== -- EXEC STORE DIReto M[END] <- RX --======================================================================== IF(IR(15 DOWNTO 10) = STORE) THEN state := fetch; END IF; --======================================================================== -- EXEC CALL Pilha <- PC e PC <- 16bit END : --======================================================================== IF(IR(15 DOWNTO 10) = CALL) THEN state := fetch; END IF; --======================================================================== -- EXEC RTS PC <- Mem[SP] --======================================================================== IF(IR(15 DOWNTO 10) = RTS) THEN state := exec2; END IF; --======================================================================== -- EXEC POP RX/FR --======================================================================== IF(IR(15 DOWNTO 10) = POP) THEN state := fetch; END IF; -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX --************************************************************************ -- EXECUTE2 STATE --************************************************************************ when exec2 => PONTO <= "100"; --======================================================================== -- EXEC2 RTS PC <- Mem[SP] --======================================================================== IF(IR(15 DOWNTO 10) = RTS) THEN state := fetch; END IF; -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX --************************************************************************ -- HALT STATE --************************************************************************ WHEN halted => PONTO <= "111"; state := halted; halt_ack <= '1'; WHEN OTHERS => state := fetch; videoflag <= '0'; PONTO <= "000"; END CASE; end if; end process; --************************************************************************ -- ULA ---> 3456 (3042) --************************************************************************ PROCESS (OP, X, Y, reset) VARIABLE AUX : STD_LOGIC_VECTOR(15 downto 0); VARIABLE RESULT32 : STD_LOGIC_VECTOR(31 downto 0); BEGIN IF (reset = '1') THEN auxFR <= x"0000"; RESULT <= x"0000"; else auxFR <= FR; --======================================================================== -- ARITH --======================================================================== IF (OP (5 downto 4) = ARITH) THEN CASE OP (3 downto 0) IS WHEN ADD => IF (OP(6) = '1') THEN --Soma com carRY AUX := X + Y + FR(4); RESULT32 := (x"00000000" + X + Y + FR(4)); ELSE --Soma sem carRY AUX := X + Y; RESULT32 := (x"00000000" + X + Y); end if; if(RESULT32 > "01111111111111111") THEN -- CarRY auxFR(4) <= '1'; ELSE auxFR(4) <= '0'; end if; WHEN SUB => AUX := X - Y; WHEN MULT => RESULT32 := X * Y; AUX := RESULT32(15 downto 0); if(RESULT32 > x"0000FFFF") THEN -- ARITHmetic Overflow auxFR(5) <= '1'; ELSE auxFR(5) <= '0'; end if; WHEN DIV => IF(Y = x"0000") THEN AUX := x"0000"; auxFR(6) <= '1'; -- DIV by Zero ELSE AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X)/CONV_INTEGER(Y), 16); auxFR(6) <= '0'; END IF; WHEN LMOD => IF(Y = x"0000") THEN AUX := x"0000"; auxFR(6) <= '1'; -- DIV by Zero ELSE AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X) mod CONV_INTEGER(Y), 16); auxFR(6) <= '0'; END IF; WHEN others => -- invalid operation, defaults to nothing AUX := X; END CASE; if(AUX = x"0000") THEN auxFR(3) <= '1'; -- FR = <...|zero|equal|lesser|greater> ELSE auxFR(3) <= '0'; -- FR = <...|zero|equal|lesser|greater> end if; if(AUX < x"0000") THEN -- NEGATIVO auxFR(9) <= '1'; ELSE auxFR(9) <= '0'; end if; RESULT <= AUX; ELSIF (OP (5 downto 4) = LOGIC) THEN IF (OP (3 downto 0) = CMP) THEN result <= x; IF (x > y) THEN auxFR(2 downto 0) <= "001"; -- FR = <...|zero|equal|lesser|greater> ELSIF (x < y) THEN auxFR(2 downto 0) <= "010"; -- FR = <...|zero|equal|lesser|greater> ELSIF (x = y) THEN auxFR(2 downto 0) <= "100"; -- FR = <...|zero|equal|lesser|greater> END IF; ELSE CASE OP (3 downto 0) IS WHEN LAND => result <= x and y; WHEN LXOR => result <= x xor y; WHEN LOR => result <= x or y; WHEN LNOT => result <= not x; WHEN others => -- invalid operation, defaults to nothing RESULT <= X; END CASE; if(result = x"0000") THEN auxFR(3) <= '1'; -- FR = <...|zero|equal|lesser|greater> ELSE auxFR(3) <= '0'; -- FR = <...|zero|equal|lesser|greater> end if; END IF; END IF; END IF; -- Reset END PROCESS; end main;
gpl-3.0
7262bfdb0b9345f6b725f582542584d5
0.451663
3.51468
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/Checkers/Control_Part_Checkers/Allocator_checkers/Arbiter_in_one_hot_checkers/RTL_and_Synthesis/arbiter_in_one_hot_pseudo.vhd
3
4,141
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; -- Is this like the old arbiter in the router with handshaking FC ?? entity arbiter_in_one_hot_pseudo is port ( req_X_N, req_X_E, req_X_W, req_X_S, req_X_L:in std_logic; -- From LBDR modules state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_in's FSM X_N, X_E, X_W, X_S, X_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot) state_in: out std_logic_vector (5 downto 0) -- 6 states for Arbiter's FSM ); end; architecture behavior of arbiter_in_one_hot_pseudo is CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001"; CONSTANT Local: std_logic_vector (5 downto 0) := "000010"; CONSTANT North: std_logic_vector (5 downto 0) := "000100"; CONSTANT East: std_logic_vector (5 downto 0) := "001000"; CONSTANT West: std_logic_vector (5 downto 0) := "010000"; CONSTANT South: std_logic_vector (5 downto 0) := "100000"; begin -- anything below here is pure combinational process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L) begin X_N <= '0'; X_E <= '0'; X_W <= '0'; X_S <= '0'; X_L <= '0'; case state is when IDLE => -- In the arbiter for hand-shaking FC router, L had the highest priority (L, N, E, W, S) -- Here it seems N has the higest priority, am I correct ? if req_X_N ='1' then state_in <= North; X_N <= '1'; elsif req_X_E = '1' then state_in <= East; X_E <= '1'; elsif req_X_W = '1' then state_in <= West; X_W <= '1'; elsif req_X_S = '1' then state_in <= South; X_S <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L <= '1'; else state_in <= state; end if; when North => if req_X_N ='1' then state_in <= North; X_N <= '1'; elsif req_X_E = '1' then state_in <= East; X_E <= '1'; elsif req_X_W = '1' then state_in <= West; X_W <= '1'; elsif req_X_S = '1' then state_in <= South; X_S <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L <= '1'; else state_in <= state; end if; when East => if req_X_E = '1' then state_in <= East; X_E <= '1'; elsif req_X_W = '1' then state_in <= West; X_W <= '1'; elsif req_X_S = '1' then state_in <= South; X_S <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L <= '1'; elsif req_X_N ='1' then state_in <= North; X_N <= '1'; else state_in <= state; end if; when West => if req_X_W = '1' then state_in <= West; X_W <= '1'; elsif req_X_S = '1' then state_in <= South; X_S <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L <= '1'; elsif req_X_N ='1' then state_in <= North; X_N <= '1'; elsif req_X_E = '1' then state_in <= East; X_E <= '1'; else state_in <= state; end if; when South => if req_X_S = '1' then state_in <= South; X_S <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L <= '1'; elsif req_X_N ='1' then state_in <= North; X_N <= '1'; elsif req_X_E = '1' then state_in <= East; X_E <= '1'; elsif req_X_W = '1' then state_in <= West; X_W <= '1'; else state_in <= state; end if; when others => -- Local state and invalid states if req_X_L = '1' then state_in <= Local; X_L <= '1'; elsif req_X_N ='1' then state_in <= North; X_N <= '1'; elsif req_X_E = '1' then state_in <= East; X_E <= '1'; elsif req_X_W = '1' then state_in <= West; X_W <= '1'; elsif req_X_S = '1' then state_in <= South; X_S <= '1'; else state_in <= state; end if; end case; end process; end;
gpl-3.0
cf0ff96c261e28a131342cdc9ecfdccb
0.474282
2.908006
false
false
false
false
simoesusp/Processador-ICMC
Software_Assembly/IR_Controller/Processor_IR_PWM_DE2_70/AP9_cpu_b.vhd
2
16,087
--SETCARRY NEEDS TO BE FIXED!!! --------------------------------------------------- --APx-ARCH AP9 Micro-processor--------------------- --16-bits width bus-------------------------------- --External clock----------------------------------- --Builded by MicroENIX, copyright (r) 2011--------- --For detailed description about this-------------- --architechture, please refer to the AP9 reference-- --manual.------------------------------------------ --------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY AP9_cpu IS PORT( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; HALT_REQ : IN STD_LOGIC; KEY : IN STD_LOGIC_VECTOR(7 DOWNTO 0); MEM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); MEM_WDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); MEM_ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); MEM_RW : OUT STD_LOGIC; VGA_DRAW : OUT STD_LOGIC; VGA_POS : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); VGA_CC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); PC_DATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); HALT_ACK : OUT STD_LOGIC ); END AP9_cpu; ARCHITECTURE main OF AP9_cpu IS TYPE STATES IS (fetch, decode, exec, halted); TYPE REGISTERS IS ARRAY(0 TO 7) OF STD_LOGIC_VECTOR(15 DOWNTO 0); TYPE LOADREGISTERS IS ARRAY(0 TO 7) OF STD_LOGIC; CONSTANT LOAD : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110000"; CONSTANT STORE : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110001"; CONSTANT LOADIMED : STD_LOGIC_VECTOR(5 DOWNTO 0) := "111000"; CONSTANT LOADINDEX : STD_LOGIC_VECTOR(5 DOWNTO 0) := "111100"; CONSTANT STOREINDEX : STD_LOGIC_VECTOR(5 DOWNTO 0) := "111101"; CONSTANT MOV : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110011"; CONSTANT OUTCHAR : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110010"; CONSTANT INCHAR : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110101"; CONSTANT ARITH : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10"; CONSTANT ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; CONSTANT SUB : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001"; CONSTANT MULT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010"; CONSTANT DIV : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011"; CONSTANT INC : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100"; CONSTANT LMOD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101"; CONSTANT CMP : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0110"; CONSTANT LOGIC : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01"; CONSTANT LAND : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010"; CONSTANT LOR : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011"; CONSTANT LXOR : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100"; CONSTANT LNOT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101"; CONSTANT SHIFT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; CONSTANT JMP : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000010"; CONSTANT CALL : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000011"; CONSTANT RTS : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000100"; CONSTANT PUSH : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000101"; CONSTANT POP : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000110"; CONSTANT NOP : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000"; CONSTANT SETC : STD_LOGIC_VECTOR(5 DOWNTO 0) := "001000"; CONSTANT HALT : STD_LOGIC_VECTOR(5 DOWNTO 0) := "001111"; CONSTANT sULA : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; CONSTANT sMEM : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01"; CONSTANT sM4 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10"; CONSTANT sKEY : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11"; CONSTANT FRGREATER : INTEGER := 0; CONSTANT FRLESSER : INTEGER := 1; CONSTANT FREQUAL : INTEGER := 2; CONSTANT FRZERO : INTEGER := 3; CONSTANT FRCARRY : INTEGER := 4; CONSTANT FRARITHOF : INTEGER := 5; CONSTANT FRDIVZERO : INTEGER := 6; CONSTANT FRSTACKOF : INTEGER := 7; CONSTANT FRSTACKUF : INTEGER := 8; CONSTANT IF1 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; CONSTANT IFE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001"; CONSTANT IFNE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010"; CONSTANT IFZ : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011"; CONSTANT IFNZ : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100"; CONSTANT IFC : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101"; CONSTANT IFNC : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0110"; CONSTANT IFGR : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0111"; CONSTANT IFLE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000"; CONSTANT IFEG : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1001"; CONSTANT IFEL : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1010"; CONSTANT IFOV : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1011"; CONSTANT IFNOV : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1100"; SIGNAL OP : STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL X, Y, RESULT: STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL FR : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL auxFR : STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN PROCESS(CLK, RST) VARIABLE STATE : STATES; VARIABLE PC : STD_LOGIC_VECTOR(15 DOWNTO 0); VARIABLE SP : STD_LOGIC_VECTOR(15 DOWNTO 0); VARIABLE IR : STD_LOGIC_VECTOR(15 DOWNTO 0); VARIABLE MAR : STD_LOGIC_VECTOR(15 DOWNTO 0); VARIABLE M2 : STD_LOGIC_VECTOR(15 DOWNTO 0); VARIABLE M4 : STD_LOGIC_VECTOR(15 DOWNTO 0); VARIABLE RX : INTEGER; VARIABLE RY : INTEGER; VARIABLE RZ : INTEGER; VARIABLE selM2 : STD_LOGIC_VECTOR(1 DOWNTO 0); VARIABLE selM6 : STD_LOGIC_VECTOR(1 DOWNTO 0); VARIABLE IncPC : STD_LOGIC; VARIABLE IncSP : STD_LOGIC; VARIABLE DecSP : STD_LOGIC; VARIABLE LoadPC : STD_LOGIC; VARIABLE LoadMAR : STD_LOGIC; VARIABLE LoadIR : STD_LOGIC; VARIABLE LoadREG : LOADREGISTERS; VARIABLE COND : STD_LOGIC; VARIABLE REG : REGISTERS; BEGIN IF(RST = '1') THEN STATE := fetch; PC := x"0000"; SP := x"3FFC"; IR := x"0000"; MAR := x"0000"; selM2 := sMEM; selM6 := sULA; IncPC := '0'; IncSP := '0'; DecSP := '0'; LoadPC := '0'; LoadMAR := '0'; LoadIR := '0'; LoadREG := x"00"; COND := '0'; MEM_RW <= '0'; VGA_DRAW <= '0'; HALT_ACK <= '0'; ELSIF(CLK'EVENT AND CLK = '1') THEN IF(HALT_REQ = '1') THEN STATE := halted; END IF; IF(LoadPC = '1') THEN PC := MEM_DATA; LoadPC := '0'; END IF; CASE selM2 IS WHEN sMEM => M2 := MEM_DATA; WHEN sM4 => M2 := M4; WHEN sKEY => M2(15 DOWNTO 8) := x"00"; M2(7 DOWNTO 0) := KEY; WHEN sULA => M2 := RESULT; WHEN OTHERS => END CASE; IF(LoadMAR = '1') THEN MAR := MEM_DATA; LoadMAR := '0'; END IF; IF(IncSP = '1') THEN SP := SP + x"1"; IncSP := '0'; END IF; IF(DecSP = '1') THEN SP := SP - x"1"; DecSP := '0'; END IF; IF(LoadIR = '1') THEN IR := MEM_DATA; LoadIR := '0'; END IF; IF(LoadREG(RX) = '1') THEN REG(RX) := M2; LoadREG(RX) := '0'; END IF; IF(IncPC = '1') THEN PC := PC + x"1"; IncPC := '0'; END IF; CASE selM6 IS WHEN sULA => FR <= auxFR; WHEN sMEM => FR <= MEM_DATA; WHEN OTHERS => END CASE; selM6 := sULA; PC_DATA <= PC; COND := '0'; MEM_RW <= '0'; VGA_DRAW <= '0'; RX := conv_integer(IR(9 DOWNTO 7)); RY := conv_integer(IR(6 DOWNTO 4)); RZ := conv_integer(IR(3 DOWNTO 1)); CASE STATE IS WHEN fetch => MEM_ADDR <= PC; LoadIR := '1'; IncPC := '1'; STATE := decode; WHEN decode => IF(IR(15 DOWNTO 14) = ARITH) THEN CASE IR(13 DOWNTO 10) IS WHEN INC => X <= REG(RX); M4 := x"0001"; Y <= M4; IF(IR(6) = '0') THEN OP <= '0' & ARITH & ADD; ELSE OP <= '0' & ARITH & SUB; END IF; selM2 := sULA; LoadREG(RX) := '1'; STATE := fetch; WHEN OTHERS => X <= REG(RY); M4 := REG(RZ); Y <= M4; OP <= IR(0) & ARITH & IR(13 DOWNTO 10); selM2 := sULA; LoadREG(RX) := '1'; STATE := fetch; END CASE; ELSIF(IR(15 DOWNTO 14) = LOGIC) THEN CASE IR(13 DOWNTO 10) IS WHEN LNOT => M4 := REG(RY); Y <= M4; OP <= '0' & LOGIC & LNOT; selM2 := sULA; LoadREG(RX) := '1'; STATE := fetch; WHEN CMP => X <= REG(RX); M4 := REG(RY); Y <= M4; OP <= '0' & LOGIC & CMP; STATE := fetch; WHEN SHIFT => CASE IR(6 DOWNTO 4) IS WHEN "000" => M4 := TO_STDLOGICVECTOR(TO_BITVECTOR(REG(RX)) SLL conv_integer(IR(3 DOWNTO 0))); WHEN "001" => M4 := NOT TO_STDLOGICVECTOR(NOT TO_BITVECTOR(REG(RX)) SLL conv_integer(IR(3 DOWNTO 0))); WHEN "010" => M4 := TO_STDLOGICVECTOR(TO_BITVECTOR(REG(RX)) SRL conv_integer(IR(3 DOWNTO 0))); WHEN "011" => M4 := NOT TO_STDLOGICVECTOR(NOT TO_BITVECTOR(REG(RX)) SRL conv_integer(IR(3 DOWNTO 0))); WHEN "100" => M4 := TO_STDLOGICVECTOR(TO_BITVECTOR(REG(RX)) ROL conv_integer(IR(3 DOWNTO 0))); WHEN "110" => M4 := TO_STDLOGICVECTOR(TO_BITVECTOR(REG(RX)) ROR conv_integer(IR(3 DOWNTO 0))); WHEN OTHERS => END CASE; selM2 := sM4; LoadREG(RX) := '1'; STATE := fetch; WHEN OTHERS => X <= REG(RY); M4 := REG(RZ); Y <= M4; OP <= '0' & LOGIC & IR(13 DOWNTO 10); selM2 := sM4; LoadREG(RX) := '1'; STATE := fetch; END CASE; ELSE CASE IR(15 DOWNTO 10) IS WHEN LOAD => MEM_ADDR <= PC; LoadMAR := '1'; IncPC := '1'; STATE := exec; WHEN STORE => MEM_ADDR <= PC; LoadMAR := '1'; IncPC := '1'; STATE := exec; WHEN LOADIMED => MEM_ADDR <= PC; selM2 := sMEM; LoadREG(RX) := '1'; IncPC := '1'; STATE := fetch; WHEN LOADINDEX => M4 := REG(RY); MEM_ADDR <= M4; selM2 := sMEM; LoadREG(RX) := '1'; STATE := fetch; WHEN STOREINDEX => MEM_ADDR <= REG(RX); M4 := REG(RY); MEM_WDATA <= M4; MEM_RW <= '1'; STATE := fetch; WHEN MOV => M4 := REG(RY); selM2 := sM4; LoadREG(RX) := '1'; STATE := fetch; WHEN OUTCHAR => VGA_CC <= REG(RX); M4 := REG(RY); VGA_POS <= M4; VGA_DRAW <= '1'; STATE := fetch; WHEN INCHAR => selM2 := sKEY; LoadReg(RX) := '1'; STATE := fetch; WHEN JMP => MEM_ADDR <= PC; CASE IR(9 DOWNTO 6) IS WHEN IF1 => COND := '1'; WHEN IFE => COND := FR(FREQUAL); WHEN IFNE => COND := NOT FR(FREQUAL); WHEN IFZ => COND := FR(FRZERO); WHEN IFNZ => COND := NOT FR(FRZERO); WHEN IFC => COND := FR(FRCARRY); WHEN IFNC => COND := NOT FR(FRCARRY); WHEN IFGR => COND := FR(FRGREATER); WHEN IFLE => COND := FR(FRLESSER); WHEN IFEG => COND := FR(FREQUAL) OR FR(FRGREATER); WHEN IFEL => COND := FR(FREQUAL) OR FR(FRLESSER); WHEN IFOV => COND := FR(FRARITHOF); --OR FR(FRSTACKOV); WHEN IFNOV => COND := NOT FR(FRARITHOF); --OR NOT FR(FRSTACKOF); WHEN OTHERS => END CASE; IF(COND = '1') THEN LoadPC := '1'; ELSE IncPC := '1'; END IF; STATE := fetch; WHEN CALL => CASE IR(9 DOWNTO 6) IS WHEN IF1 => COND := '1'; WHEN IFE => COND := FR(FREQUAL); WHEN IFNE => COND := NOT FR(FREQUAL); WHEN IFZ => COND := FR(FRZERO); WHEN IFNZ => COND := NOT FR(FRZERO); WHEN IFC => COND := FR(FRCARRY); WHEN IFNC => COND := NOT FR(FRCARRY); WHEN IFGR => COND := FR(FRGREATER); WHEN IFLE => COND := FR(FRLESSER); WHEN IFEG => COND := FR(FREQUAL) OR FR(FRGREATER); WHEN IFEL => COND := FR(FREQUAL) OR FR(FRLESSER); WHEN IFOV => COND := FR(FRARITHOF); --OR FR(FRSTACKOV); WHEN IFNOV => COND := NOT FR(FRARITHOF); --OR NOT FR(FRSTACKOF); WHEN OTHERS => END CASE; IF(COND = '1') THEN MEM_WDATA <= PC; MEM_ADDR <= SP; MEM_RW <= '1'; DecSP := '1'; STATE := exec; ELSE IncPC := '1'; STATE := fetch; END IF; WHEN RTS => IncSP := '1'; STATE := exec; WHEN PUSH => IF(IR(6) = '0') THEN MEM_WDATA <= REG(RX); ELSE MEM_WDATA <= FR; END IF; MEM_ADDR <= SP; MEM_RW <= '1'; DecSP := '1'; STATE := fetch; WHEN POP => IncSP := '1'; STATE := exec; WHEN NOP => STATE := fetch; WHEN SETC => selM6 := sULA; FR(FRCARRY) <= IR(9); STATE := fetch; WHEN HALT => STATE := halted; WHEN OTHERS => STATE := fetch; END CASE; END IF; WHEN exec => CASE IR(15 DOWNTO 10) IS WHEN LOAD => MEM_ADDR <= MAR; selM2 := sMEM; LoadReg(RX) := '1'; STATE := fetch; WHEN STORE => MEM_ADDR <= MAR; MEM_WDATA <= REG(RX); MEM_RW <= '1'; STATE := fetch; WHEN CALL => MEM_ADDR <= PC; LoadPC := '1'; STATE := fetch; WHEN RTS => MEM_ADDR <= SP; LoadPC := '1'; IncPC := '1'; STATE := fetch; WHEN POP => MEM_ADDR <= SP; selM2 := sMEM; IF(IR(6) = '0') THEN LoadREG(RX) := '1'; ELSE selM6 := sMEM; END IF; STATE := fetch; WHEN OTHERS => STATE := fetch; END CASE; WHEN halted => HALT_ACK <= '1'; WHEN OTHERS => END CASE; END IF; END PROCESS; PROCESS(OP, X, Y, RST) VARIABLE AUX : STD_LOGIC_VECTOR(15 DOWNTO 0); VARIABLE RESULT32 : STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN IF(RST = '1') THEN auxFR <= x"0000"; RESULT <= x"0000"; ELSE auxFR <= FR; IF(OP(5 DOWNTO 4) = ARITH) THEN CASE OP(3 DOWNTO 0) IS WHEN ADD => IF(OP(6) = '1') THEN AUX := X + Y + FR(FRCARRY); RESULT32 := (x"00000000" + X + Y + FR(FRCARRY)); ELSE AUX := X + Y; RESULT32 := (x"00000000" + X + Y); END IF; IF(RESULT32 > "01111111111111111") THEN auxFR(FRCARRY) <= '1'; ELSE auxFR(FRCARRY) <= '0'; END IF; WHEN SUB => AUX := X - Y; WHEN MULT => RESULT32 := X * Y; AUX := RESULT32(15 DOWNTO 0); IF(RESULT32 > x"0000FFFF") THEN auxFR(FRARITHOF) <= '1'; ELSE auxFR(FRARITHOF) <= '0'; END IF; WHEN DIV => IF(Y = x"0000") THEN AUX := x"0000"; auxFR(FRDIVZERO) <= '1'; ELSE AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X)/CONV_INTEGER(Y), 16); auxFR(FRDIVZERO) <= '0'; END IF; WHEN LMOD => AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X) MOD CONV_INTEGER(Y), 16); WHEN OTHERS => AUX := X; END CASE; IF(AUX = x"0000") THEN auxFR(3) <= '1'; ELSE auxFR(3) <= '0'; END IF; RESULT <= AUX; ELSIF(OP (5 DOWNTO 4) = LOGIC) THEN IF(OP (3 DOWNTO 0) = CMP) THEN result <= x; IF(X > Y) THEN auxFR(2 DOWNTO 0) <= "001"; ELSIF (X < Y) THEN auxFR(2 DOWNTO 0) <= "010"; ELSIF (X = Y) THEN auxFR(2 DOWNTO 0) <= "100"; END IF; ELSE CASE OP (3 DOWNTO 0) IS WHEN LAND => RESULT <= X AND Y; WHEN LXOR => RESULT <= X XOR Y; WHEN LOR => RESULT <= X OR Y; WHEN LNOT => RESULT <= NOT Y; WHEN OTHERS => RESULT <= X; END CASE; IF(RESULT = x"0000") THEN auxFR(FRZERO) <= '1'; ELSE auxFR(FRZERO) <= '0'; END IF; END IF; END IF; END IF; END PROCESS; END main;
gpl-3.0
8a55b1f4fced68478c290ef959f4986c
0.499285
3.152459
false
false
false
false
AndyMcC0/UVVM_All
uvvm_vvc_framework/src_target_dependent/td_target_support_pkg.vhd
1
14,794
--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <[email protected]>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use std.textio.all; library uvvm_util; context uvvm_util.uvvm_util_context; library uvvm_vvc_framework; use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all; use work.vvc_cmd_pkg.all; package td_target_support_pkg is signal global_vvc_ack : std_logic; -- ACK on global triggers signal global_vvc_busy : std_logic := 'L'; -- ACK on global triggers shared variable protected_multicast_semaphore : t_protected_semaphore; shared variable protected_acknowledge_index : t_protected_acknowledge_cmd_idx; type t_vvc_target_record_unresolved is record -- VVC dedicated to assure signature differences between equal common methods trigger : std_logic; vvc_name : string(1 to C_LOG_SCOPE_WIDTH-2); -- as scope is vvc_name & ',' and number vvc_instance_idx : integer; vvc_channel : t_channel; end record; constant C_VVC_TARGET_RECORD_DEFAULT : t_vvc_target_record_unresolved := ( trigger => 'L', vvc_name => (others => '?'), vvc_instance_idx => -1, vvc_channel => NA ); -- type t_vvc_target_record_drivers is array (natural range <> ) of t_vvc_target_record_unresolved; function resolved ( input_vector : t_vvc_target_record_drivers) return t_vvc_target_record_unresolved; subtype t_vvc_target_record is resolved t_vvc_target_record_unresolved; ------------------------------------------- -- to_string ------------------------------------------- -- to_string method for VVC name, instance and channel -- - If channel is set to NA, it will not be included in the string function to_string( value : t_vvc_target_record; vvc_instance : integer := -1; vvc_channel : t_channel := NA ) return string; ------------------------------------------- -- format_command_idx ------------------------------------------- -- Returns an encapsulated command index as string impure function format_command_idx( command : t_vvc_cmd_record -- VVC dedicated ) return string; ------------------------------------------- -- send_command_to_vvc ------------------------------------------- -- Sends command to VVC and waits for ACK or timeout -- - Logs with ID_UVVM_SEND_CMD when sending to VVC -- - Logs with ID_UVVM_CMD_ACK when ACK or timeout occurs procedure send_command_to_vvc( -- VVC dedicated shared command used shared_vvc_cmd signal vvc_target : inout t_vvc_target_record; constant timeout : in time := std.env.resolution_limit ); ------------------------------------------- -- set_vvc_target_defaults ------------------------------------------- -- Returns a vvc target record with vvc_name and values specified in C_VVC_TARGET_RECORD_DEFAULT function set_vvc_target_defaults ( constant vvc_name : in string ) return t_vvc_target_record; ------------------------------------------- -- set_general_target_and_command_fields ------------------------------------------- -- Sets target index and channel, and updates shared_vvc_cmd procedure set_general_target_and_command_fields ( -- VVC dedicated shared command used shared_vvc_cmd signal target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant proc_call : in string; constant msg : in string; constant command_type : in t_immediate_or_queued; constant operation : in t_operation ); ------------------------------------------- -- set_general_target_and_command_fields ------------------------------------------- -- Sets target index and channel, and updates shared_vvc_cmd procedure set_general_target_and_command_fields ( -- VVC dedicated shared command used shared_vvc_cmd signal target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant proc_call : in string; constant msg : in string; constant command_type : in t_immediate_or_queued; constant operation : in t_operation ); ------------------------------------------- -- acknowledge_cmd ------------------------------------------- -- Drives global_vvc_ack signal (to '1') for 1 delta cycle, then sets it back to 'Z'. procedure acknowledge_cmd ( signal vvc_ack : inout std_logic; constant command_idx : in natural ); end package td_target_support_pkg; package body td_target_support_pkg is function resolved ( input_vector : t_vvc_target_record_drivers) return t_vvc_target_record_unresolved is -- if none of the drives want to drive the target return value of first driver (which we need to drive at least the target name) constant C_LINE_LENGTH_MAX : natural := 100; -- VVC idx list string length variable v_result : t_vvc_target_record_unresolved := input_vector(input_vector'low); variable v_cnt : integer := 0; variable v_instance_string : string(1 to C_LINE_LENGTH_MAX) := (others => NUL); variable v_line : line; variable v_width : integer := 0; begin if input_vector'length = 1 then return input_vector(input_vector'low); else for i in input_vector'range loop -- The VVC is used if instance_idx is not -1 (which is the default value) if input_vector(i).vvc_instance_idx /= -1 then -- count the number of sequencer trying to access the VVC v_cnt := v_cnt + 1; v_result := input_vector(i); -- generating string with all instance_idx for report in case of failure write(v_line, string'(" ")); write(v_line, input_vector(i).vvc_instance_idx); -- Ensure there is room for the last item and dots v_width := v_line'length; if v_width > (C_LINE_LENGTH_MAX-15) then write(v_line, string'("...")); exit; end if; end if; end loop; if v_width > 0 then v_instance_string(1 to v_width) := v_line.all; end if; deallocate(v_line); check_value(v_cnt < 2, TB_FAILURE, "Arbitration mechanism failed. Check VVC " & to_string(v_result.vvc_name) & " implementation and semaphore handling. Crashing instances with numbers " & v_instance_string(1 to v_width), C_SCOPE, ID_NEVER); return v_result; end if; end resolved; function to_string( value : t_vvc_target_record; vvc_instance : integer := -1; vvc_channel : t_channel:= NA ) return string is variable v_instance : integer; variable v_channel : t_channel; begin if vvc_instance = -1 then v_instance := value.vvc_instance_idx; else v_instance := vvc_instance; end if; if vvc_channel = NA then v_channel := value.vvc_channel; else v_channel := vvc_channel; end if; if v_channel = NA then return to_string(value.vvc_name) & "," & to_string(v_instance); else return to_string(value.vvc_name) & "," & to_string(v_instance) & "," & to_string(v_channel); end if; end; function set_vvc_target_defaults ( constant vvc_name : in string ) return t_vvc_target_record is variable v_rec : t_vvc_target_record := C_VVC_TARGET_RECORD_DEFAULT; begin v_rec.vvc_name := (others => NUL); v_rec.vvc_name(1 to vvc_name'length) := vvc_name; return v_rec; end function; procedure set_general_target_and_command_fields ( signal target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant proc_call : in string; constant msg : in string; constant command_type : in t_immediate_or_queued; constant operation : in t_operation ) is begin -- As shared_vvc_cmd is a shared variable we have to get exclusive access to it. Therefor we have to lock the protected_semaphore here. -- It is unlocked again in await_cmd_from_sequencer after it is copied localy or in send_command_to_vvc if no VVC acknowledges the command. -- It is guaranteed that no time delay occurs, only delta cycle delay. await_semaphore_in_delta_cycles(protected_semaphore); shared_vvc_cmd := C_VVC_CMD_DEFAULT; target.vvc_instance_idx <= vvc_instance_idx; target.vvc_channel <= vvc_channel; shared_vvc_cmd.proc_call := pad_string(proc_call, NUL, shared_vvc_cmd.proc_call'length); shared_vvc_cmd.msg := (others => NUL); -- default empty shared_vvc_cmd.msg(1 to msg'length) := msg; shared_vvc_cmd.command_type := command_type; shared_vvc_cmd.operation := operation; end procedure; procedure set_general_target_and_command_fields ( signal target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant proc_call : in string; constant msg : in string; constant command_type : in t_immediate_or_queued; constant operation : in t_operation ) is begin set_general_target_and_command_fields(target, vvc_instance_idx, NA, proc_call, msg, command_type, operation); end procedure; impure function format_command_idx( command : t_vvc_cmd_record ) return string is begin return format_command_idx(command.cmd_idx); end; procedure send_command_to_vvc( signal vvc_target : inout t_vvc_target_record; constant timeout : in time := std.env.resolution_limit ) is constant C_SCOPE : string := C_TB_SCOPE_DEFAULT & "(uvvm)"; constant C_CMD_INFO : string := "uvvm cmd " & format_command_idx(shared_cmd_idx+1) & ": "; variable v_ack_cmd_idx : integer := -1; variable v_start_time : time; variable v_local_vvc_cmd : t_vvc_cmd_record; variable v_local_cmd_idx : integer; variable v_was_multicast : boolean := false; begin check_value((shared_uvvm_state /= IDLE), TB_FAILURE, "UVVM will not work without uvvm_vvc_framework.ti_uvvm_engine instantiated in the test harness", C_SCOPE, ID_NEVER); -- increment shared_cmd_inx. It is protected by the protected_semaphore and only one sequencer can access the variable at a time. shared_cmd_idx := shared_cmd_idx + 1; shared_vvc_cmd.cmd_idx := shared_cmd_idx; if global_show_msg_for_uvvm_cmd then log(ID_UVVM_SEND_CMD, to_string(shared_vvc_cmd.proc_call) & ": " & add_msg_delimiter(to_string(shared_vvc_cmd.msg)) & "." & format_command_idx(shared_cmd_idx), C_SCOPE); else log(ID_UVVM_SEND_CMD, to_string(shared_vvc_cmd.proc_call) & format_command_idx(shared_cmd_idx), C_SCOPE); end if; wait for 0 ns; if (vvc_target.vvc_instance_idx = C_VVCT_ALL_INSTANCES) then await_semaphore_in_delta_cycles(protected_multicast_semaphore); if global_vvc_busy /= 'L' then wait until global_vvc_busy = 'L'; end if; v_was_multicast := true; end if; v_start_time := now; -- semaphore "protected_semaphore" gets released after "wait for 0 ns" in await_cmd_from_sequencer -- Before the semaphore is released copy shared_vvc_cmd to local variable, so that the shared_vvc_cmd can be used by other VVCs. v_local_vvc_cmd := shared_vvc_cmd; -- copy the shared_cmd_idx as it can be changed during this function after the semaphore is released v_local_cmd_idx := shared_cmd_idx; -- trigger the target -> vvc continues in await_cmd_from_sequencer vvc_target.trigger <= '1'; wait for 0 ns; -- the default value of vvc_target drives trigger to 'L' again vvc_target <= set_vvc_target_defaults(vvc_target.vvc_name); while v_ack_cmd_idx /= v_local_cmd_idx loop wait until global_vvc_ack = '1' for ((v_start_time + timeout) - now); v_ack_cmd_idx := protected_acknowledge_index.get_index; if not (global_vvc_ack'event) then tb_error("Time out for " & C_CMD_INFO & " '" & to_string(v_local_vvc_cmd.proc_call) & "' while waiting for acknowledge from VVC", C_SCOPE); -- lock the sequencer for 5 delta cycles as it can take so long to get every VVC in normal mode again wait for 0 ns; wait for 0 ns; wait for 0 ns; wait for 0 ns; wait for 0 ns; -- release the semaphore as no VVC can do this release_semaphore(protected_semaphore); return; end if; end loop; if (v_was_multicast = true) then release_semaphore(protected_multicast_semaphore); end if; log(ID_UVVM_CMD_ACK, "ACK received. " & format_command_idx(v_local_cmd_idx), C_SCOPE); -- clean up and prepare for next wait for 0 ns; -- wait for executor to stop driving global_vvc_ack end procedure; procedure acknowledge_cmd ( signal vvc_ack : inout std_logic; constant command_idx : in natural ) is begin -- Drive ack signal for 1 delta cycle only one command index can be acknowledged simultaneously. while(protected_acknowledge_index.set_index(command_idx) = false) loop -- if it can't set the acknowledge_index wait for one delta cycle and try again wait for 0 ns; end loop; vvc_ack <= '1'; wait until vvc_ack = '1'; vvc_ack <= 'Z'; wait for 0 ns; protected_acknowledge_index.release_index; end procedure; end package body td_target_support_pkg;
mit
a30ab25e139003a9cb52856998e8bb9c
0.604164
3.931438
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/SIB_mux_pre_FCX.vhd
3
4,775
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity SIB_mux_pre_FCX is Port ( -- Scan Interface client -------------- SI : in STD_LOGIC; -- ScanInPort CE : in STD_LOGIC; -- CaptureEnPort SE : in STD_LOGIC; -- ShiftEnPort UE : in STD_LOGIC; -- UpdateEnPort SEL : in STD_LOGIC; -- SelectPort RST : in STD_LOGIC; -- ResetPort TCK : in STD_LOGIC; -- TCKPort SO : out STD_LOGIC; -- ScanOutPort toF : out STD_LOGIC; -- To F flag of the upper hierarchical level toC : out STD_LOGIC; -- To C flag of the upper hierarchical level -- Scan Interface host ---------------- fromSO : in STD_LOGIC; -- ScanInPort toCE : out STD_LOGIC; -- ToCaptureEnPort toSE : out STD_LOGIC; -- ToShiftEnPort toUE : out STD_LOGIC; -- ToUpdateEnPort toSEL : out STD_LOGIC; -- ToSelectPort toRST : out STD_LOGIC; -- ToResetPort toTCK : out STD_LOGIC; -- ToTCKPort toSI : out STD_LOGIC; -- ScanOutPort fromF : in STD_LOGIC; -- From an OR of all F flags in the underlying network segment fromC : in STD_LOGIC -- From an AND of all C flags in the underlying network segment ); end SIB_mux_pre_FCX; architecture SIB_mux_pre_FCX_arch of SIB_mux_pre_FCX is component ScanRegister_for_SIBFCX is Generic (Size : positive; BitOrder : string; -- MSBLSB / LSBMSB SOSource : natural; ResetValue : STD_LOGIC_VECTOR); Port ( SI : in STD_LOGIC; CE : in STD_LOGIC; SE : in STD_LOGIC; UE : in STD_LOGIC; SEL : in STD_LOGIC; RST : in STD_LOGIC; TCK : in STD_LOGIC; SO : out STD_LOGIC; CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0); ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0); ue_mux_out : out STD_LOGIC_VECTOR (Size-1 downto 0)); end component; component ScanMux is Generic (ControlSize : positive); Port ( ScanMux_in : in STD_LOGIC_VECTOR((2**ControlSize)-1 downto 0); SelectedBy : in STD_LOGIC_VECTOR(ControlSize-1 downto 0); ScanMux_out : out STD_LOGIC); end component; signal SIBmux_out : STD_LOGIC; signal SR_so : STD_LOGIC; signal SR_do : STD_LOGIC_VECTOR (3 downto 0); signal SR_ci : STD_LOGIC_VECTOR (3 downto 0); signal sr_update_mux_out : STD_LOGIC_VECTOR (3 downto 0); signal C_sync, F_sync : STD_LOGIC; signal C_sync_first, F_sync_first : STD_LOGIC; signal F_sync_delayed_copy, sticky_f_posedge : STD_LOGIC; begin SO <= SR_so; -- Source SR toCE <= CE; toSE <= SE; toUE <= UE; toSEL <= SEL and SR_do(3); -- SEL & S bit toRST <= RST; toTCK <= TCK; toSI <= SI; -- Source SI SR_ci(3) <= SR_do(3); -- Sxcf SR_ci(2) <= SR_do(2); -- sXcf SR_ci(1) <= C_sync; -- sxCf SR_ci(0) <= sticky_f_posedge; -- sxcF toF <= fromF and SR_do(2); -- F flag from lower levels AND X bit toC <= fromC or not SR_do(2); -- C flag from lower levels OR NOT X bit f_edge_detector : process (TCK, RST) begin if RST = '1' then sticky_f_posedge <= '0'; elsif TCK'event and TCK = '0' then if F_sync_delayed_copy = '0' and F_sync = '1' then -- edge detector sticky_f_posedge <= '1'; elsif UE = '1' and SEL = '1' and sr_update_mux_out(0) = '0' then -- clear sticky F flag when F is updated with 0 sticky_f_posedge <= '0'; end if; end if; end process; -- f_edge_detector synchronizer : process( TCK ) begin if TCK'event and TCK = '0' then F_sync_first <= fromF; F_sync <= F_sync_first; F_sync_delayed_copy <= F_sync; C_sync_first <= fromC; C_sync <= C_sync_first; end if ; end process ; -- synchronizer SR : ScanRegister_for_SIBFCX Generic map (Size => 4, BitOrder => "MSBLSB", -- MSBLSB / LSBMSB SOSource => 0, ResetValue => "0110") -- ResetValue S=0, X=1, C=1, F=0 Port map ( SI => SIBmux_out, -- ScanInSource SIBmux_out CE => CE, SE => SE, UE => UE, SEL => SEL, RST => RST, TCK => TCK, SO => SR_so, CaptureSource => SR_ci, -- CaptureSource SR ScanRegister_out => SR_do, ue_mux_out => sr_update_mux_out); SIBmux : ScanMux Generic map ( ControlSize => 1) Port map ( ScanMux_in(0) => SI, -- 1'b0 : SI ScanMux_in(1) => fromSO, -- 1'b1 : fromSO SelectedBy => SR_do(3 downto 3), --SelectedBy SR ScanMux_out => SIBmux_out); end SIB_mux_pre_FCX_arch;
gpl-3.0
79ae212ad7164bf1019f6afcc5acc2a5
0.548901
3.544915
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/mlite_pack.vhd
3
30,184
--------------------------------------------------------------------- -- TITLE: Plasma Misc. Package -- Main AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 2/15/01 -- FILENAME: mlite_pack.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Data types, constants, and add functions needed for the Plasma CPU. -- modified by: Siavoosh Payandeh Azad -- Change logs: -- * An NI has been added to the file as a new module -- * some changes has been applied to the ports of the older modules -- to facilitate the new module! -- * memory mapped addresses are added! --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package mlite_pack is constant ZERO : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; constant ONES : std_logic_vector(31 downto 0) := "11111111111111111111111111111111"; --make HIGH_Z equal to ZERO if compiler complains constant HIGH_Z : std_logic_vector(31 downto 0) := "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; subtype alu_function_type is std_logic_vector(3 downto 0); constant ALU_NOTHING : alu_function_type := "0000"; constant ALU_ADD : alu_function_type := "0001"; constant ALU_SUBTRACT : alu_function_type := "0010"; constant ALU_LESS_THAN : alu_function_type := "0011"; constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100"; constant ALU_OR : alu_function_type := "0101"; constant ALU_AND : alu_function_type := "0110"; constant ALU_XOR : alu_function_type := "0111"; constant ALU_NOR : alu_function_type := "1000"; subtype shift_function_type is std_logic_vector(1 downto 0); constant SHIFT_NOTHING : shift_function_type := "00"; constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01"; constant SHIFT_RIGHT_SIGNED : shift_function_type := "11"; constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10"; subtype mult_function_type is std_logic_vector(3 downto 0); constant MULT_NOTHING : mult_function_type := "0000"; constant MULT_READ_LO : mult_function_type := "0001"; constant MULT_READ_HI : mult_function_type := "0010"; constant MULT_WRITE_LO : mult_function_type := "0011"; constant MULT_WRITE_HI : mult_function_type := "0100"; constant MULT_MULT : mult_function_type := "0101"; constant MULT_SIGNED_MULT : mult_function_type := "0110"; constant MULT_DIVIDE : mult_function_type := "0111"; constant MULT_SIGNED_DIVIDE : mult_function_type := "1000"; subtype a_source_type is std_logic_vector(1 downto 0); constant A_FROM_REG_SOURCE : a_source_type := "00"; constant A_FROM_IMM10_6 : a_source_type := "01"; constant A_FROM_PC : a_source_type := "10"; subtype b_source_type is std_logic_vector(1 downto 0); constant B_FROM_REG_TARGET : b_source_type := "00"; constant B_FROM_IMM : b_source_type := "01"; constant B_FROM_SIGNED_IMM : b_source_type := "10"; constant B_FROM_IMMX4 : b_source_type := "11"; subtype c_source_type is std_logic_vector(2 downto 0); constant C_FROM_NULL : c_source_type := "000"; constant C_FROM_ALU : c_source_type := "001"; constant C_FROM_SHIFT : c_source_type := "001"; --same as alu constant C_FROM_MULT : c_source_type := "001"; --same as alu constant C_FROM_MEMORY : c_source_type := "010"; constant C_FROM_PC : c_source_type := "011"; constant C_FROM_PC_PLUS4 : c_source_type := "100"; constant C_FROM_IMM_SHIFT16: c_source_type := "101"; constant C_FROM_REG_SOURCEN: c_source_type := "110"; subtype pc_source_type is std_logic_vector(1 downto 0); constant FROM_INC4 : pc_source_type := "00"; constant FROM_OPCODE25_0 : pc_source_type := "01"; constant FROM_BRANCH : pc_source_type := "10"; constant FROM_LBRANCH : pc_source_type := "11"; subtype branch_function_type is std_logic_vector(2 downto 0); constant BRANCH_LTZ : branch_function_type := "000"; constant BRANCH_LEZ : branch_function_type := "001"; constant BRANCH_EQ : branch_function_type := "010"; constant BRANCH_NE : branch_function_type := "011"; constant BRANCH_GEZ : branch_function_type := "100"; constant BRANCH_GTZ : branch_function_type := "101"; constant BRANCH_YES : branch_function_type := "110"; constant BRANCH_NO : branch_function_type := "111"; -- mode(32=1,16=2,8=3), signed, write subtype mem_source_type is std_logic_vector(3 downto 0); constant MEM_FETCH : mem_source_type := "0000"; constant MEM_READ32 : mem_source_type := "0100"; constant MEM_WRITE32 : mem_source_type := "0101"; constant MEM_READ16 : mem_source_type := "1000"; constant MEM_READ16S : mem_source_type := "1010"; constant MEM_WRITE16 : mem_source_type := "1001"; constant MEM_READ8 : mem_source_type := "1100"; constant MEM_READ8S : mem_source_type := "1110"; constant MEM_WRITE8 : mem_source_type := "1101"; -- memory mapped addresses constant NI_reserved_data_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111"; constant NI_flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; constant NI_counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001"; constant NI_reconfiguration_address : std_logic_vector(29 downto 0) := "000000000000000010000000000010"; constant NI_self_diagnosis_address : std_logic_vector(29 downto 0) := "000000000000000010000000000011"; constant uart_count_value_address : std_logic_vector(29 downto 0) := "000000000000000010000000000100"; function bv_adder(a : in std_logic_vector; b : in std_logic_vector; do_add: in std_logic) return std_logic_vector; function bv_negate(a : in std_logic_vector) return std_logic_vector; function bv_increment(a : in std_logic_vector(31 downto 2) ) return std_logic_vector; function bv_inc(a : in std_logic_vector ) return std_logic_vector; -- For Altera COMPONENT lpm_ram_dp generic ( LPM_WIDTH : natural; -- MUST be greater than 0 LPM_WIDTHAD : natural; -- MUST be greater than 0 LPM_NUMWORDS : natural := 0; LPM_INDATA : string := "REGISTERED"; LPM_OUTDATA : string := "REGISTERED"; LPM_RDADDRESS_CONTROL : string := "REGISTERED"; LPM_WRADDRESS_CONTROL : string := "REGISTERED"; LPM_FILE : string := "UNUSED"; LPM_TYPE : string := "LPM_RAM_DP"; USE_EAB : string := "OFF"; INTENDED_DEVICE_FAMILY : string := "UNUSED"; RDEN_USED : string := "TRUE"; LPM_HINT : string := "UNUSED"); port ( RDCLOCK : in std_logic := '0'; RDCLKEN : in std_logic := '1'; RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0); RDEN : in std_logic := '1'; DATA : in std_logic_vector(LPM_WIDTH-1 downto 0); WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0); WREN : in std_logic; WRCLOCK : in std_logic := '0'; WRCLKEN : in std_logic := '1'; Q : out std_logic_vector(LPM_WIDTH-1 downto 0)); END COMPONENT; -- For Altera component LPM_RAM_DQ generic ( LPM_WIDTH : natural; -- MUST be greater than 0 LPM_WIDTHAD : natural; -- MUST be greater than 0 LPM_NUMWORDS : natural := 0; LPM_INDATA : string := "REGISTERED"; LPM_ADDRESS_CONTROL: string := "REGISTERED"; LPM_OUTDATA : string := "REGISTERED"; LPM_FILE : string := "UNUSED"; LPM_TYPE : string := "LPM_RAM_DQ"; USE_EAB : string := "OFF"; INTENDED_DEVICE_FAMILY : string := "UNUSED"; LPM_HINT : string := "UNUSED"); port ( DATA : in std_logic_vector(LPM_WIDTH-1 downto 0); ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0); INCLOCK : in std_logic := '0'; OUTCLOCK : in std_logic := '0'; WE : in std_logic; Q : out std_logic_vector(LPM_WIDTH-1 downto 0)); end component; -- For Xilinx component RAM16X1D -- synthesis translate_off generic (INIT : bit_vector := X"0000"); -- synthesis translate_on port (DPO : out STD_ULOGIC; SPO : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; D : in STD_ULOGIC; DPRA0 : in STD_ULOGIC; DPRA1 : in STD_ULOGIC; DPRA2 : in STD_ULOGIC; DPRA3 : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; -- For Xilinx Virtex-5 component RAM32X1D -- synthesis translate_off generic (INIT : bit_vector := X"00000000"); -- synthesis translate_on port (DPO : out STD_ULOGIC; SPO : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; A4 : in STD_ULOGIC; D : in STD_ULOGIC; DPRA0 : in STD_ULOGIC; DPRA1 : in STD_ULOGIC; DPRA2 : in STD_ULOGIC; DPRA3 : in STD_ULOGIC; DPRA4 : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; component pc_next port(clk : in std_logic; reset_in : in std_logic; pc_new : in std_logic_vector(31 downto 2); take_branch : in std_logic; pause_in : in std_logic; opcode25_0 : in std_logic_vector(25 downto 0); pc_source : in pc_source_type; pc_future : out std_logic_vector(31 downto 2); pc_current : out std_logic_vector(31 downto 2); pc_plus4 : out std_logic_vector(31 downto 2)); end component; component mem_ctrl port(clk : in std_logic; reset_in : in std_logic; pause_in : in std_logic; nullify_op : in std_logic; address_pc : in std_logic_vector(31 downto 2); opcode_out : out std_logic_vector(31 downto 0); address_in : in std_logic_vector(31 downto 0); mem_source : in mem_source_type; data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); pause_out : out std_logic; address_next : out std_logic_vector(31 downto 2); byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0)); end component; component control port(opcode : in std_logic_vector(31 downto 0); intr_signal : in std_logic; --NI_read_flag : in std_logic; --NI_write_flag : in std_logic; rs_index : out std_logic_vector(5 downto 0); rt_index : out std_logic_vector(5 downto 0); rd_index : out std_logic_vector(5 downto 0); imm_out : out std_logic_vector(15 downto 0); alu_func : out alu_function_type; shift_func : out shift_function_type; mult_func : out mult_function_type; branch_func : out branch_function_type; a_source_out : out a_source_type; b_source_out : out b_source_type; c_source_out : out c_source_type; pc_source_out: out pc_source_type; mem_source_out:out mem_source_type; exception_out: out std_logic); end component; component reg_bank generic(memory_type : string := "XILINX_16X"); port(clk : in std_logic; reset_in : in std_logic; pause : in std_logic; interrupt_in : in std_logic; -- modified rs_index : in std_logic_vector(5 downto 0); rt_index : in std_logic_vector(5 downto 0); rd_index : in std_logic_vector(5 downto 0); reg_source_out : out std_logic_vector(31 downto 0); reg_target_out : out std_logic_vector(31 downto 0); reg_dest_new : in std_logic_vector(31 downto 0); intr_enable : out std_logic); end component; component bus_mux port(imm_in : in std_logic_vector(15 downto 0); reg_source : in std_logic_vector(31 downto 0); a_mux : in a_source_type; a_out : out std_logic_vector(31 downto 0); reg_target : in std_logic_vector(31 downto 0); b_mux : in b_source_type; b_out : out std_logic_vector(31 downto 0); c_bus : in std_logic_vector(31 downto 0); c_memory : in std_logic_vector(31 downto 0); c_pc : in std_logic_vector(31 downto 2); c_pc_plus4 : in std_logic_vector(31 downto 2); c_mux : in c_source_type; reg_dest_out : out std_logic_vector(31 downto 0); branch_func : in branch_function_type; take_branch : out std_logic); end component; component alu generic(alu_type : string := "DEFAULT"); port(a_in : in std_logic_vector(31 downto 0); b_in : in std_logic_vector(31 downto 0); alu_function : in alu_function_type; c_alu : out std_logic_vector(31 downto 0)); end component; component shifter generic(shifter_type : string := "DEFAULT" ); port(value : in std_logic_vector(31 downto 0); shift_amount : in std_logic_vector(4 downto 0); shift_func : in shift_function_type; c_shift : out std_logic_vector(31 downto 0)); end component; component mult generic(mult_type : string := "DEFAULT"); port(clk : in std_logic; reset_in : in std_logic; a, b : in std_logic_vector(31 downto 0); mult_func : in mult_function_type; c_mult : out std_logic_vector(31 downto 0); pause_out : out std_logic); end component; component pipeline port(clk : in std_logic; reset : in std_logic; a_bus : in std_logic_vector(31 downto 0); a_busD : out std_logic_vector(31 downto 0); b_bus : in std_logic_vector(31 downto 0); b_busD : out std_logic_vector(31 downto 0); alu_func : in alu_function_type; alu_funcD : out alu_function_type; shift_func : in shift_function_type; shift_funcD : out shift_function_type; mult_func : in mult_function_type; mult_funcD : out mult_function_type; reg_dest : in std_logic_vector(31 downto 0); reg_destD : out std_logic_vector(31 downto 0); rd_index : in std_logic_vector(5 downto 0); rd_indexD : out std_logic_vector(5 downto 0); rs_index : in std_logic_vector(5 downto 0); rt_index : in std_logic_vector(5 downto 0); pc_source : in pc_source_type; mem_source : in mem_source_type; a_source : in a_source_type; b_source : in b_source_type; c_source : in c_source_type; c_bus : in std_logic_vector(31 downto 0); pause_any : in std_logic; pause_pipeline : out std_logic); end component; component mlite_cpu generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_ mult_type : string := "DEFAULT"; shifter_type : string := "DEFAULT"; alu_type : string := "DEFAULT"; pipeline_stages : natural := 2); --2 or 3 port(clk : in std_logic; reset_in : in std_logic; intr_in : in std_logic; --NI_read_flag : in std_logic; --NI_write_flag : in std_logic; address_next : out std_logic_vector(31 downto 2); --for synch ram byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0); mem_pause : in std_logic); end component; component cache generic(memory_type : string := "DEFAULT"); port(clk : in std_logic; reset : in std_logic; address_next : in std_logic_vector(31 downto 2); byte_we_next : in std_logic_vector(3 downto 0); cpu_address : in std_logic_vector(31 downto 2); mem_busy : in std_logic; cache_access : out std_logic; --access 4KB cache cache_checking : out std_logic; --checking if cache hit cache_miss : out std_logic); --cache miss end component; --cache -- change this if you want to use behavioral ram! --component ram -- generic(memory_type : string := "DEFAULT"; -- stim_file: string :="code.txt"); -- port(clk : in std_logic; -- enable : in std_logic; -- reset : in std_logic; -- write_byte_enable : in std_logic_vector(3 downto 0); -- address : in std_logic_vector(31 downto 2); -- data_write : in std_logic_vector(31 downto 0); -- data_read : out std_logic_vector(31 downto 0)); -- end component; --ram component ram is generic(memory_type : string := "DEFAULT"; stim_file: string :="code.txt"); port(clk : in std_logic; reset : in std_logic; enable : in std_logic; write_byte_enable : in std_logic_vector(3 downto 0); address : in std_logic_vector(31 downto 2); data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); IJTAG_select : in std_logic; IJTAG_clk : in std_logic; IJTAG_reset : in std_logic; IJTAG_enable : in std_logic; IJTAG_write_byte_enable : in std_logic_vector(3 downto 0); IJTAG_address : in std_logic_vector(31 downto 2); IJTAG_data_write : in std_logic_vector(31 downto 0); IJTAG_data_read : out std_logic_vector(31 downto 0)); end component; -- ram component NI generic(current_address : integer := 10; -- the current node's address SHMU_address : integer := 0); -- reserved address for self diagnosis register port(clk : in std_logic; reset : in std_logic; enable : in std_logic; write_byte_enable : in std_logic_vector(3 downto 0); address : in std_logic_vector(31 downto 2); data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); -- Flags used by JNIFR and JNIFW instructions --NI_read_flag : out std_logic; -- One if the N2P fifo is empty. No read should be performed if one. --NI_write_flag : out std_logic; -- One if P2N fifo is full. no write should be performed if one. -- interrupt signal: generated evertime a packet is recieved! irq_out : out std_logic; -- signals for sending packets to network credit_in : in std_logic; valid_out: out std_logic; TX: out std_logic_vector(31 downto 0); -- data sent to the NoC -- signals for reciving packets from the network credit_out : out std_logic; valid_in: in std_logic; RX: in std_logic_vector(31 downto 0); -- data recieved form the NoC -- fault information signals from the router link_faults: in std_logic_vector(4 downto 0); turn_faults: in std_logic_vector(19 downto 0); Rxy_reconf_PE: out std_logic_vector(7 downto 0); Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits) Reconfig_command : out std_logic ); end component; --entity NI component uart generic(log_file : string := "UNUSED"); port(clk : in std_logic; reset : in std_logic; enable_read : in std_logic; enable_write : in std_logic; data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); uart_read : in std_logic; uart_write : out std_logic; busy_write : out std_logic; data_avail : out std_logic; reg_enable : in std_logic; reg_write_byte_enable : in std_logic_vector(3 downto 0); reg_address : in std_logic_vector(31 downto 2); reg_data_write : in std_logic_vector(31 downto 0); reg_data_read : out std_logic_vector(31 downto 0) ); end component; --uart component eth_dma port(clk : in std_logic; --25 MHz reset : in std_logic; enable_eth : in std_logic; select_eth : in std_logic; rec_isr : out std_logic; send_isr : out std_logic; address : out std_logic_vector(31 downto 2); --to DDR byte_we : out std_logic_vector(3 downto 0); data_write : out std_logic_vector(31 downto 0); data_read : in std_logic_vector(31 downto 0); pause_in : in std_logic; mem_address : in std_logic_vector(31 downto 2); --from CPU mem_byte_we : in std_logic_vector(3 downto 0); data_w : in std_logic_vector(31 downto 0); pause_out : out std_logic; E_RX_CLK : in std_logic; --2.5 MHz receive E_RX_DV : in std_logic; --data valid E_RXD : in std_logic_vector(3 downto 0); --receive nibble E_TX_CLK : in std_logic; --2.5 MHz transmit E_TX_EN : out std_logic; --transmit enable E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble end component; --eth_dma component plasma generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM"; log_file : string := "UNUSED"; ethernet : std_logic := '0'; use_cache : std_logic := '0'; current_address : integer := 10; stim_file: string :="code.txt"); port(clk : in std_logic; reset : in std_logic; uart_write : out std_logic; uart_read : in std_logic; address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_write : out std_logic_vector(31 downto 0); data_read : in std_logic_vector(31 downto 0); mem_pause_in : in std_logic; no_ddr_start : out std_logic; no_ddr_stop : out std_logic; gpio0_out : out std_logic_vector(31 downto 0); gpioA_in : in std_logic_vector(31 downto 0); credit_in : in std_logic; valid_out: out std_logic; TX: out std_logic_vector(31 downto 0); credit_out : out std_logic; valid_in: in std_logic; RX: in std_logic_vector(31 downto 0); link_faults: in std_logic_vector(4 downto 0); turn_faults: in std_logic_vector(19 downto 0); Rxy_reconf_PE: out std_logic_vector(7 downto 0); Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits) Reconfig_command : out std_logic; -- remove this part if you are using behavioral memory IJTAG_select : in std_logic; IJTAG_clk : in std_logic; IJTAG_reset : in std_logic; IJTAG_enable : in std_logic; IJTAG_write_byte_enable : in std_logic_vector(3 downto 0); IJTAG_address : in std_logic_vector(31 downto 2); IJTAG_data_write : in std_logic_vector(31 downto 0); IJTAG_data_read : out std_logic_vector(31 downto 0) ); end component; --plasma component ddr_ctrl port(clk : in std_logic; clk_2x : in std_logic; reset_in : in std_logic; address : in std_logic_vector(25 downto 2); byte_we : in std_logic_vector(3 downto 0); data_w : in std_logic_vector(31 downto 0); data_r : out std_logic_vector(31 downto 0); active : in std_logic; no_start : in std_logic; no_stop : in std_logic; pause : out std_logic; SD_CK_P : out std_logic; --clock_positive SD_CK_N : out std_logic; --clock_negative SD_CKE : out std_logic; --clock_enable SD_BA : out std_logic_vector(1 downto 0); --bank_address SD_A : out std_logic_vector(12 downto 0); --address(row or col) SD_CS : out std_logic; --chip_select SD_RAS : out std_logic; --row_address_strobe SD_CAS : out std_logic; --column_address_strobe SD_WE : out std_logic; --write_enable SD_DQ : inout std_logic_vector(15 downto 0); --data SD_UDM : out std_logic; --upper_byte_enable SD_UDQS : inout std_logic; --upper_data_strobe SD_LDM : out std_logic; --low_byte_enable SD_LDQS : inout std_logic); --low_data_strobe end component; --ddr component memory generic(address_width : natural := 16); port(clk : in std_logic; address : in std_logic_vector(31 downto 2); data_write : in std_logic_vector(31 downto 0); pause : in std_logic; byte_we : in std_logic_vector(3 downto 0); data_read : out std_logic_vector(31 downto 0) ); end component; --entity memory end; --package mlite_pack package body mlite_pack is --function bv_adder(a : in std_logic_vector; -- b : in std_logic_vector; -- do_add: in std_logic) return std_logic_vector is -- variable carry_in : std_logic; -- variable bb : std_logic_vector(a'length-1 downto 0); -- variable result : std_logic_vector(a'length downto 0); --begin -- if do_add = '1' then -- bb := b; -- carry_in := '0'; -- else -- bb := not b; -- carry_in := '1'; -- end if; -- for index in 0 to a'length-1 loop -- result(index) := a(index) xor bb(index) xor carry_in; -- carry_in := (carry_in and (a(index) or bb(index))) or -- (a(index) and bb(index)); -- end loop; -- result(a'length) := carry_in xnor do_add; -- return result; --end; --function function bv_adder(a : in std_logic_vector; b : in std_logic_vector; do_add: in std_logic) return std_logic_vector is variable A1, B1, S : UNSIGNED(a'length downto 0); begin A1 := resize(unsigned(a), A1'length); B1 := resize(unsigned(b), B1'length); if do_add = '1' then S := A1 + B1; else S := A1 - B1; end if; return std_logic_vector(S); end; --function function bv_negate(a : in std_logic_vector) return std_logic_vector is variable carry_in : std_logic; variable not_a : std_logic_vector(a'length-1 downto 0); variable result : std_logic_vector(a'length-1 downto 0); begin not_a := not a; carry_in := '1'; for index in a'reverse_range loop result(index) := not_a(index) xor carry_in; carry_in := carry_in and not_a(index); end loop; return result; end; --function function bv_increment(a : in std_logic_vector(31 downto 2) ) return std_logic_vector is variable carry_in : std_logic; variable result : std_logic_vector(31 downto 2); begin carry_in := '1'; for index in 2 to 31 loop result(index) := a(index) xor carry_in; carry_in := a(index) and carry_in; end loop; return result; end; --function function bv_inc(a : in std_logic_vector ) return std_logic_vector is variable carry_in : std_logic; variable result : std_logic_vector(a'length-1 downto 0); begin carry_in := '1'; for index in 0 to a'length-1 loop result(index) := a(index) xor carry_in; carry_in := a(index) and carry_in; end loop; return result; end; --function end; --package body
gpl-3.0
da72fad99827d7754b0b3a39054128cb
0.548469
3.673807
false
false
false
false
AndyMcC0/UVVM_All
uvvm_vvc_framework/src_target_dependent/td_queue_pkg.vhd
3
2,199
--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <[email protected]>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ --=============================================================================================== -- td_cmd_queue_pkg -- - Target dependent command queue package --=============================================================================================== library uvvm_vvc_framework; use uvvm_vvc_framework.ti_generic_queue_pkg; use work.vvc_cmd_pkg.all; package td_cmd_queue_pkg is new uvvm_vvc_framework.ti_generic_queue_pkg generic map (t_generic_element => t_vvc_cmd_record); --=============================================================================================== -- td_result_queue_pkg -- - Target dependent result queue package --=============================================================================================== library uvvm_vvc_framework; use uvvm_vvc_framework.ti_generic_queue_pkg; use work.vvc_cmd_pkg.all; package td_result_queue_pkg is new uvvm_vvc_framework.ti_generic_queue_pkg generic map (t_generic_element => t_vvc_result_queue_element);
mit
df4e1d28017188e645117c4cecbdf4d2
0.471123
5.59542
false
false
false
false
FlatTargetInk/Spartan-HW
button_debounce.vhd
1
1,680
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:16:23 04/28/2017 -- Design Name: -- Module Name: button_debounce - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity button_debounce is Port( CLK : in STD_LOGIC; EN : in STD_LOGIC; BTN : in STD_LOGIC_VECTOR (3 downto 0); DBTN : out STD_LOGIC_VECTOR (3 downto 0)); end button_debounce; architecture Structural of button_debounce is signal DEBOUNCED : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0'); begin DBTN <= DEBOUNCED; BTN_0: entity work.debounce port map(CLK => CLK, EN => EN, INPUT => BTN(0), OUTPUT => DEBOUNCED(0)); BTN_1: entity work.debounce port map(CLK => CLK, EN => EN, INPUT => BTN(1), OUTPUT => DEBOUNCED(1)); BTN_2: entity work.debounce port map(CLK => CLK, EN => EN, INPUT => BTN(2), OUTPUT => DEBOUNCED(2)); BTN_3: entity work.debounce port map(CLK => CLK, EN => EN, INPUT => BTN(3), OUTPUT => DEBOUNCED(3)); end Structural; -- vim:set ts=3 sw=3 noexpandtab:
mit
159b76295cf70ab450fea086a09dab53
0.577976
3.307087
false
false
false
false
simoesusp/Processador-ICMC
Processor_FPGA/Processor_Template_VHDL_DE70/TEXT_DRAWER.vhd
3
3,502
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; ENTITY TEXT_DRAWER IS PORT( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; DRAW : IN STD_LOGIC; CHAR : IN STD_LOGIC_VECTOR(6 DOWNTO 0); XPOS : IN STD_LOGIC_VECTOR(5 DOWNTO 0); YPOS : IN STD_LOGIC_VECTOR(4 DOWNTO 0); COLOR : IN STD_LOGIC_VECTOR(3 DOWNTO 0); SIZE : IN STD_LOGIC; CHARLINEDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CHARADDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); DATA : OUT STD_LOGIC_VECTOR(20 DOWNTO 0); DATA_QUEUE : OUT STD_LOGIC ); END TEXT_DRAWER; ARCHITECTURE main OF TEXT_DRAWER IS SIGNAL STATE : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK, RST) VARIABLE PREVCHAR : STD_LOGIC_VECTOR(6 DOWNTO 0); VARIABLE PREVXPOS : STD_LOGIC_VECTOR(5 DOWNTO 0); VARIABLE PREVYPOS : STD_LOGIC_VECTOR(4 DOWNTO 0); VARIABLE PREVCOLOR : STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE PREVSIZE : STD_LOGIC; VARIABLE OUTDATA: STD_LOGIC_VECTOR(20 DOWNTO 0); VARIABLE PIXCNT : STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE PIXAUX : STD_LOGIC_VECTOR(2 DOWNTO 0); VARIABLE LNCNT : STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE LNAUX : STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE XP : STD_LOGIC_VECTOR(8 DOWNTO 0); VARIABLE YP : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN IF(RST = '1') THEN OUTDATA := "000000000000000000000"; PIXCNT := x"0"; LNCNT := x"0"; PREVXPOS := "111111"; XP := "000000000"; YP := "00000000"; STATE <= x"0"; DATA_QUEUE <= '0'; ELSIF(CLK'EVENT AND CLK = '1') THEN CASE STATE IS WHEN x"0" => --DEFINIR BOUNDARIES PARA O CARACTER IF(DRAW = '1' AND NOT(PREVCHAR = CHAR AND PREVXPOS = XPOS AND PREVYPOS = YPOS AND PREVCOLOR = COLOR AND PREVSIZE = SIZE)) THEN PREVCHAR := CHAR; PREVXPOS := XPOS; PREVYPOS := YPOS; PREVCOLOR := COLOR; PREVSIZE := SIZE; LNCNT := x"0"; IF(SIZE = '1') THEN XP := XPOS(4 DOWNTO 0) & "0000"; YP := YPOS(3 DOWNTO 0) & "0000"; IF(XP <= 304 AND YP <= 224) THEN STATE <= x"1"; END IF; ELSE XP := XPOS & "000"; YP := YPOS & "000"; IF(XP <= 312 AND YP <= 232) THEN STATE <= x"1"; END IF; END IF; END IF; WHEN x"1" => IF(SIZE = '1') THEN LNAUX := '0' & LNCNT(3 DOWNTO 1); ELSE LNAUX := LNCNT(3 DOWNTO 0); END IF; CHARADDR <= CHAR & LNAUX(2 DOWNTO 0); PIXCNT := x"0"; STATE <= x"2"; WHEN x"2" => IF(SIZE = '1') THEN PIXAUX := PIXCNT(3 DOWNTO 1); ELSE PIXAUX := PIXCNT(2 DOWNTO 0); END IF; OUTDATA(16 DOWNTO 0) := conv_std_logic_vector(conv_integer(PIXCNT + XP) + (320 * conv_integer(YP + LNCNT)), 17); IF(CHARLINEDATA(conv_integer(NOT PIXAUX)) = '1') THEN OUTDATA(20 DOWNTO 17) := COLOR; ELSE OUTDATA(20 DOWNTO 17) := x"0"; END IF; DATA_QUEUE <= '1'; IF((PIXAUX = 7 AND SIZE = '0') OR (PIXCNT = 15 AND SIZE = '1')) THEN IF((LNAUX = 7 AND SIZE = '0') OR (LNCNT = 15 AND SIZE = '1')) THEN STATE <= x"5"; ELSE LNCNT := LNCNT + '1'; STATE <= x"4"; END IF; ELSE PIXCNT := PIXCNT + '1'; STATE <= x"3"; END IF; WHEN x"3" => DATA_QUEUE <= '0'; STATE <= x"2"; WHEN x"4" => DATA_QUEUE <= '0'; STATE <= x"1"; WHEN x"5" => DATA_QUEUE <= '0'; STATE <= x"0"; WHEN OTHERS => STATE <= x"0"; END CASE; DATA <= OUTDATA; END IF; END PROCESS; END main;
gpl-3.0
a821b8a93cfd071fdbabaf043e2fb26e
0.56996
2.879934
false
false
false
false
simoesusp/Processador-ICMC
Processor_FPGA/Processor_Template_VHDL_DE70/LCD_MOD.vhd
3
6,526
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; ENTITY LCD_MOD IS PORT( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; PC : IN STD_LOGIC_VECTOR(15 DOWNTO 0); KEYB : IN STD_LOGIC_VECTOR(7 DOWNTO 0); H_STATE : IN STD_LOGIC; LCD_DATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); LCD_ENABLE: OUT STD_LOGIC; LCD_RW : OUT STD_LOGIC; LCD_RS : OUT STD_LOGIC ); END LCD_MOD; ARCHITECTURE main OF LCD_MOD IS CONSTANT RUNNING : STD_LOGIC_VECTOR(55 DOWNTO 0) := x"676E696E6E7552"; CONSTANT HALTED : STD_LOGIC_VECTOR(55 DOWNTO 0) := x"206465746C6148"; CONSTANT PCS : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"203A4350"; CONSTANT KEYBS : STD_LOGIC_VECTOR(47 DOWNTO 0) := x"203A4259454B"; CONSTANT AP9S : STD_LOGIC_VECTOR(23 DOWNTO 0) := x"395041"; SIGNAL MAINSTATE : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL STATE : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL STATEA : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK, RST) VARIABLE COUNTER : INTEGER RANGE 0 TO 2500000; VARIABLE ITER : INTEGER RANGE 0 TO 256; VARIABLE INPC : STD_LOGIC_VECTOR(15 DOWNTO 0); VARIABLE INKEYB : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN IF(RST = '1') THEN ITER := 0; INPC := x"FFFF"; INKEYB := x"FF"; LCD_ENABLE <= '0'; LCD_DATA <= x"00"; MAINSTATE <= x"0"; STATE <= x"F"; STATEA <= x"0"; ELSIF(CLK'EVENT AND CLK = '1') THEN CASE STATE IS --CLEAR SCREEN WHEN x"0" => LCD_DATA <= x"01"; LCD_RS <= '0'; LCD_RW <= '0'; LCD_ENABLE <= '1'; STATEA <= x"D"; STATE <= x"E"; --PREPARE TO WRITE RUNNING WHEN x"1" => LCD_DATA <= x"80"; LCD_RS <= '0'; LCD_RW <= '0'; LCD_ENABLE <= '1'; STATEA <= x"2"; STATE <= x"E"; --WRITE RUNNING WHEN x"2" => LCD_DATA <= RUNNING(ITER + 7 DOWNTO ITER); LCD_RS <= '1'; LCD_RW <= '0'; LCD_ENABLE <= '1'; ITER := ITER + 8; IF(ITER = 56) THEN ITER := 0; STATEA <= x"D"; ELSE STATEA <= x"2"; END IF; STATE <= x"F"; --PREPARE TO WRITE PC: XXXX WHEN x"3" => LCD_DATA <= x"88"; LCD_RS <= '0'; LCD_RW <= '0'; LCD_ENABLE <= '1'; STATEA <= x"4"; STATE <= x"E"; --WRITE PC: XXXX WHEN x"4" => IF(ITER < 32) THEN LCD_DATA <= PCS(ITER + 7 DOWNTO ITER); ELSE CASE ITER IS WHEN 32 => IF(PC(15 DOWNTO 12) < x"A") THEN LCD_DATA <= PC(15 DOWNTO 12) + x"30"; ELSE LCD_DATA <= PC(15 DOWNTO 12) + x"37"; END IF; WHEN 40 => IF(PC(11 DOWNTO 8) < x"A") THEN LCD_DATA <= PC(11 DOWNTO 8) + x"30"; ELSE LCD_DATA <= PC(11 DOWNTO 8) + x"37"; END IF; WHEN 48 => IF(PC(7 DOWNTO 4) < x"A") THEN LCD_DATA <= PC(7 DOWNTO 4) + x"30"; ELSE LCD_DATA <= PC(7 DOWNTO 4) + x"37"; END IF; WHEN 56 => IF(PC(3 DOWNTO 0) < x"A") THEN LCD_DATA <= PC(3 DOWNTO 0) + x"30"; ELSE LCD_DATA <= PC(3 DOWNTO 0) + x"37"; END IF; WHEN OTHERS => END CASE; END IF; LCD_RS <= '1'; LCD_RW <= '0'; LCD_ENABLE <= '1'; ITER := ITER + 8; IF(ITER = 64) THEN ITER := 0; STATEA <= x"D"; ELSE STATEA <= x"4"; END IF; STATE <= x"F"; --PREPARE TO WRITE KEYB: XX WHEN x"5" => LCD_DATA <= x"C8"; LCD_RS <= '0'; LCD_RW <= '0'; LCD_ENABLE <= '1'; STATEA <= x"6"; STATE <= x"E"; --WRITE KEYB: XX WHEN x"6" => IF(ITER < 48) THEN LCD_DATA <= KEYBS(ITER + 7 DOWNTO ITER); ELSE CASE ITER IS WHEN 48 => IF(KEYB(7 DOWNTO 4) < x"A") THEN LCD_DATA <= KEYB(7 DOWNTO 4) + x"30"; ELSE LCD_DATA <= KEYB(7 DOWNTO 4) + x"37"; END IF; WHEN 56 => IF(KEYB(3 DOWNTO 0) < x"A") THEN LCD_DATA <= KEYB(3 DOWNTO 0) + x"30"; ELSE LCD_DATA <= KEYB(3 DOWNTO 0) + x"37"; END IF; WHEN OTHERS => END CASE; END IF; LCD_RS <= '1'; LCD_RW <= '0'; LCD_ENABLE <= '1'; ITER := ITER + 8; IF(ITER = 64) THEN ITER := 0; STATEA <= x"D"; ELSE STATEA <= x"6"; END IF; STATE <= x"F"; --PREPARE TO WRITE AP9 WHEN x"7" => LCD_DATA <= x"C0"; LCD_RS <= '0'; LCD_RW <= '0'; LCD_ENABLE <= '1'; STATEA <= x"8"; STATE <= x"E"; --WRITE AP9 WHEN x"8" => LCD_DATA <= AP9S(ITER + 7 DOWNTO ITER); LCD_RS <= '1'; LCD_RW <= '0'; LCD_ENABLE <= '1'; ITER := ITER + 8; IF(ITER = 24) THEN ITER := 0; STATEA <= x"D"; ELSE STATEA <= x"8"; END IF; STATE <= x"F"; --PREPARE TO WRITE HALTED WHEN x"9" => LCD_DATA <= x"80"; LCD_RS <= '0'; LCD_RW <= '0'; LCD_ENABLE <= '1'; STATEA <= x"A"; STATE <= x"E"; --WRITE HALTED WHEN x"A" => LCD_DATA <= HALTED(ITER + 7 DOWNTO ITER); LCD_RS <= '1'; LCD_RW <= '0'; LCD_ENABLE <= '1'; ITER := ITER + 8; IF(ITER = 56) THEN ITER := 0; STATEA <= x"D"; ELSE STATEA <= x"A"; END IF; STATE <= x"F"; --LOOP STATE, ALMOST A MAIN FUNCTION WHEN x"D" => CASE MAINSTATE IS --DRAW AP9 WHEN x"0" => STATE <= x"7"; MAINSTATE <= x"1"; --DRAW STATE RUNNING WHEN x"1" => STATE <= x"1"; MAINSTATE <= x"2"; --DRAW PC (IF NECESSARY) WHEN x"2" => IF(NOT (INPC = PC)) THEN INPC := PC; STATE <= x"3"; END IF; MAINSTATE <= x"3"; --DRAW KEYB (IF NECESSARY) WHEN x"3" => IF(NOT (INKEYB = KEYB)) THEN INKEYB := KEYB; STATE <= x"5"; END IF; MAINSTATE <= x"4"; --DRAW STATE HALTED (IF HALTED) WHEN x"4" => IF(H_STATE = '1') THEN STATE <= x"9"; MAINSTATE <= x"5"; ELSE MAINSTATE <= x"1"; END IF; WHEN OTHERS => END CASE; --WAIT STATE FOR INSTRUCTIONS WHEN x"E" => IF(COUNTER = 250000) THEN COUNTER := 0; LCD_ENABLE <= '0'; STATE <= STATEA; ELSE COUNTER := COUNTER + 1; END IF; --WAIT STATE FOR DATA WHEN x"F" => IF(COUNTER = 25000) THEN COUNTER := 0; LCD_ENABLE <= '0'; STATE <= STATEA; ELSE COUNTER := COUNTER + 1; END IF; WHEN OTHERS => STATE <= x"0"; END CASE; END IF; END PROCESS; END;
gpl-3.0
7a070855ee2f8e04c08558fffa952e6e
0.479926
2.791275
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/IMMORTAL_Chip_2017/Testbenches/immortal_volt_monitor_tb.vhd
3
6,841
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 06/21/2017 05:18:09 PM -- Design Name: -- Module Name: immortal_volt_monitor_tb - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity immortal_volt_monitor_tb is end immortal_volt_monitor_tb; architecture Behavioral of immortal_volt_monitor_tb is constant tck_period : time := 10 ns; constant HALF_SEPARATOR : time := 2*tck_period; constant FULL_SEPARATOR : time := 8*tck_period; signal toSI : STD_LOGIC; signal fromSO : STD_LOGIC; signal SE : STD_LOGIC; signal CE : STD_LOGIC; signal UE : STD_LOGIC; signal TCK : STD_LOGIC; signal RST : STD_LOGIC; signal SEL : STD_LOGIC; signal toF : STD_LOGIC; signal toC : STD_LOGIC; signal volt_control : std_logic_vector (2 downto 0); signal volt_data : std_logic_vector (31 downto 0); component immortal_volt_monitor_instrument is port ( -- IJTAG connection TCK : in std_logic; RST : in std_logic; SEL : in std_logic; SI : in std_logic; SE : in std_logic; UE : in std_logic; CE : in std_logic; SO : out std_logic; toF : out std_logic; toC : out std_logic; -- Monitor connections control : out std_logic_vector(2 downto 0); data : in std_logic_vector(31 downto 0) ); end component; begin volt_monitor : immortal_volt_monitor_instrument port map ( -- IJTAG connection TCK => TCK, RST => RST, SEL => SEL, SI => toSI, SE => SE, UE => UE, CE => CE, SO => fromSO, toF => toF, toC => toC, -- Monitor connections control => volt_control, data => volt_data ); ijtag_shift_proc: process -- Generate a number of TCK ticks procedure tck_tick (number_of_tick : in positive) is begin for i in 1 to number_of_tick loop TCK <= '0'; wait for TCK_period/2; TCK <= '1'; wait for TCK_period/2; end loop; end procedure tck_tick; procedure tck_halftick_high is begin TCK <= '1'; wait for TCK_period/2; end procedure tck_halftick_high; procedure tck_halftick_low is begin TCK <= '0'; wait for TCK_period/2; end procedure tck_halftick_low; -- Shifts in specified data (Capture -> Shift -> Update) procedure shift_data (data : in std_logic_vector) is begin --Capture phase CE <= '1'; tck_tick(1); CE <= '0'; --Shift phase SE <= '1'; for i in data'range loop toSI <= data(i); tck_tick(1); end loop; SE <= '0'; -- Update phase --tck_tick(1); tck_halftick_low; UE <= '1'; tck_halftick_high; tck_halftick_low; UE <= '0'; tck_halftick_high; end procedure shift_data; -- Returns all zeroes std_logic_vector of specified size function all_zeroes (number_of_zeroes : in positive) return std_logic_vector is variable zero_array : std_logic_vector(0 to number_of_zeroes-1); begin for i in zero_array'range loop zero_array(i) := '0'; end loop; return zero_array; end function all_zeroes; begin volt_data <= "00000000000000000000000000001111"; UE <= '0'; CE <= '0'; SE <= '0'; toSI <= '0'; -- Reset iJTAG chain and Instruments RST <= '1'; wait for tck_period; RST <= '0'; SEL <= '1'; tck_tick(4); --shift_data("00000000000000000000000000000000"); --shift_data("11100000000000000000000000000000"); -- shift in threshold H without update enable shift_data("00001"&"11100"&"1"&"1"&"1"&"0000000000000001111"); -- shift in threshold H without update tck_tick(4); volt_data <= "00000000000000000000000000000000"; tck_tick(1); volt_data <= "00000000000000000000000000000001"; tck_tick(1); volt_data <= "00000000000000000000000000000011"; tck_tick(1); volt_data <= "00000000000000000000000000000111"; tck_tick(1); volt_data <= "00000000000000000000000000001111"; tck_tick(1); volt_data <= "00000000000000000000000000011111"; tck_tick(1); volt_data <= "00000000000000000000000000111111"; tck_tick(1); volt_data <= "00000000000000000000000001111111"; tck_tick(1); volt_data <= "00000000000000000000000011111111"; tck_tick(1); volt_data <= "00000000000000000000000111111111"; tck_tick(1); volt_data <= "00000000000000000000001111111111"; tck_tick(1); volt_data <= "00000000000000000000011111111111"; tck_tick(1); volt_data <= "00000000000000000000111111111111"; tck_tick(1); volt_data <= "00000000000000000001111111111111"; tck_tick(1); volt_data <= "00000000000000000011111111111111"; tck_tick(1); volt_data <= "00000000000000000111111111111111"; tck_tick(1); volt_data <= "00000000000000001111111111111111"; tck_tick(1); volt_data <= "00000000000000011111111111111111"; tck_tick(1); volt_data <= "00000000000000111111111111111111"; tck_tick(1); volt_data <= "00000000000001111111111111111111"; tck_tick(1); volt_data <= "00000000000011111111111111111111"; tck_tick(1); volt_data <= "00000000000111111111111111111111"; tck_tick(1); volt_data <= "00000000001111111111111111111111"; tck_tick(1); volt_data <= "00000000011111111111111111111111"; tck_tick(1); volt_data <= "00000000111111111111111111111111"; tck_tick(1); volt_data <= "00000001111111111111111111111111"; tck_tick(1); volt_data <= "00000011111111111111111111111111"; tck_tick(1); volt_data <= "00000111111111111111111111111111"; tck_tick(1); volt_data <= "00001111111111111111111111111111"; tck_tick(1); volt_data <= "00011111111111111111111111111111"; tck_tick(1); volt_data <= "00111111111111111111111111111111"; tck_tick(1); volt_data <= "01111111111111111111111111111111"; tck_tick(1); volt_data <= "11111111111111111111111111111111"; tck_tick(1); wait; end process; end Behavioral;
gpl-3.0
294cad5f258e41f781a6d87556953730
0.60459
4.024118
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Processor_NI/memory_sim.vhd
6
1,924
library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; use ieee.std_logic_unsigned.all; entity memory is generic(address_width : natural := 16); port(clk : in std_logic; address : in std_logic_vector(31 downto 2); data_write : in std_logic_vector(31 downto 0); pause : in std_logic; byte_we : in std_logic_vector(3 downto 0); data_read : out std_logic_vector(31 downto 0) ); end; --entity memory architecture rtl of memory is signal data : std_logic_vector(31 downto 0); signal index : integer := 0; type storage_array is array(natural range 0 to (2 ** address_width) / 4 - 1) of std_logic_vector(31 downto 0); signal storage : storage_array; begin index <= conv_integer(address(address_width-1 downto 2)); data(7 downto 0) <= data_write(7 downto 0) when byte_we(0) = '1' else storage(index)(7 downto 0) when byte_we(0) = '0'; data(15 downto 8) <= data_write(15 downto 8) when byte_we(1) = '1' else storage(index)(15 downto 8) when byte_we(1) = '0'; data(23 downto 16) <= data_write(23 downto 16) when byte_we(2) = '1' else storage(index)(23 downto 16) when byte_we(2) = '0'; data(31 downto 24) <= data_write(31 downto 24) when byte_we(3) = '1' else storage(index)(31 downto 24) when byte_we(3) = '0'; dram_proc: process(clk, address, byte_we, pause, data) begin if rising_edge(clk) then if address(30 downto 28) = "001" and byte_we /= "0000" then storage(index) <= data; end if; if pause = '0' then data_read <= data; end if; end if; end process; end; --architecture logic
gpl-3.0
6ec91df54fdcd1c2eeae4566dc46e13f
0.538462
3.589552
false
false
false
false
SKravitsky/ECEC412
MUX3Way.vhd
1
535
library ieee; use ieee.std_logic_1164.all; entity MUX3Way is port( w, x, y: in std_logic_vector(31 downto 0); sel: in std_logic_vector(1 downto 0); z: out std_logic_vector(31 downto 0) ); end MUX3Way; Architecture Structural of MUX3Way is begin process(w, x, y, sel) begin case sel is when "00" => z <= w; when "01" => z <= x; when "10" => z <= y; when others => z <= X"00000000"; end case; end process; end Structural;
apache-2.0
992ce77b5fe8884928c8e058ecd0efc8
0.528972
3.184524
false
false
false
false
FlatTargetInk/Spartan-HW
debounce.vhd
1
1,669
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:26:32 04/28/2017 -- Design Name: -- Module Name: debounce - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity debounce is Generic(wait_time : INTEGER := 20); Port( CLK : in STD_LOGIC; EN : in STD_LOGIC; INPUT : in STD_LOGIC; OUTPUT : out STD_LOGIC); end debounce; architecture Logic of debounce is signal D_STATE : STD_LOGIC_VECTOR (1 downto 0); signal D_SET : STD_LOGIC; signal COUNT : STD_LOGIC_VECTOR (wait_time downto 0) := (others => '0'); begin -- If state change exists, set D_SET high D_SET <= D_STATE(0) xor D_STATE(1); input_monitor: process(EN, CLK) begin if (CLK'event and CLK = '1' and EN = '1') then D_STATE(0) <= INPUT; D_STATE(1) <= D_STATE(0); if (D_SET = '1') then COUNT <= (others => '0'); elsif (Count(wait_time) = '0') then COUNT <= COUNT + 1; else OUTPUT <= D_STATE(1); end if; end if; end process; end Logic; -- vim:set ts=3 sw=3 noexpandtab:
mit
5d67b0ba88f23e7fd0fac98b8466b73d
0.584781
3.259766
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/Checkers/Control_Part_Checkers/Allocator_checkers/Allocator_credit_counter_logic_checkers/allocator_credit_counter_logic_pseudo_with_checkers_top.vhd
3
18,336
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity allocator_credit_counter_logic_pseudo_with_checkers_top is port ( -- flow control credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic; credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0); grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : out std_logic_vector(1 downto 0); -- Checker outputs err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_N_credit_counter_N_out_increment, err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change, err_grant_N_credit_counter_N_out_decrement, err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change, err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_E_credit_counter_E_out_increment, err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change, err_grant_E_credit_counter_E_out_decrement, err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change, err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_W_credit_counter_W_out_increment, err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change, err_grant_W_credit_counter_W_out_decrement, err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change, err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_S_credit_counter_S_out_increment, err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change, err_grant_S_credit_counter_S_out_decrement, err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change, err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal, err_credit_in_L_credit_counter_L_out_increment, err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change, err_grant_L_credit_counter_L_out_decrement, err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change, err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic ); end allocator_credit_counter_logic_pseudo_with_checkers_top; architecture behavior of allocator_credit_counter_logic_pseudo_with_checkers_top is component allocator_credit_counter_logic_pseudo is port ( -- flow control credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic; credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0); grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : out std_logic_vector(1 downto 0) ); end component; component allocator_credit_counter_logic_pseudo_checkers is port ( -- flow control credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic; credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0); valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid ! credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0); -- Checker outputs -- Not complete yet ! err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_N_credit_counter_N_out_increment, err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change, err_grant_N_credit_counter_N_out_decrement, err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change, err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_E_credit_counter_E_out_increment, err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change, err_grant_E_credit_counter_E_out_decrement, err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change, err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_W_credit_counter_W_out_increment, err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change, err_grant_W_credit_counter_W_out_decrement, err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change, err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_S_credit_counter_S_out_increment, err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change, err_grant_S_credit_counter_S_out_decrement, err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change, err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal, err_credit_in_L_credit_counter_L_out_increment, err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change, err_grant_L_credit_counter_L_out_decrement, err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change, err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic ); end component; -- Signal(s) definition(s) for checkers signal credit_counter_N_in_sig, credit_counter_E_in_sig, credit_counter_W_in_sig, credit_counter_S_in_sig, credit_counter_L_in_sig : std_logic_vector (1 downto 0); begin -- We did this because of the checkers credit_counter_N_in <= credit_counter_N_in_sig; credit_counter_E_in <= credit_counter_E_in_sig; credit_counter_W_in <= credit_counter_W_in_sig; credit_counter_S_in <= credit_counter_S_in_sig; credit_counter_L_in <= credit_counter_L_in_sig; -- Allocator logic (pseudo-combinational) module instantiation ALLOCATOR_CREDIT_COUNTER_LOGIC_PSEUDO0: allocator_credit_counter_logic_pseudo PORT MAP ( credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L, credit_counter_N_out => credit_counter_N_out, credit_counter_E_out => credit_counter_E_out, credit_counter_W_out => credit_counter_W_out, credit_counter_S_out => credit_counter_S_out, credit_counter_L_out => credit_counter_L_out, grant_N => grant_N, grant_E => grant_E, grant_W => grant_W, grant_S => grant_S, grant_L => grant_L, credit_counter_N_in => credit_counter_N_in_sig, credit_counter_E_in => credit_counter_E_in_sig, credit_counter_W_in => credit_counter_W_in_sig, credit_counter_S_in => credit_counter_S_in_sig, credit_counter_L_in => credit_counter_L_in_sig ); -- Allocator logic (pseudo-combinational) checkers instantiation CHECKERS: allocator_credit_counter_logic_pseudo_checkers PORT MAP ( credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L, credit_counter_N_out => credit_counter_N_out, credit_counter_E_out => credit_counter_E_out, credit_counter_W_out => credit_counter_W_out, credit_counter_S_out => credit_counter_S_out, credit_counter_L_out => credit_counter_L_out, valid_N => grant_N, -- ?? Valid or grant ?? valid_E => grant_E, -- ?? Valid or grant ?? valid_W => grant_W, -- ?? Valid or grant ?? valid_S => grant_S, -- ?? Valid or grant ?? valid_L => grant_L, -- ?? Valid or grant ?? credit_counter_N_in => credit_counter_N_in_sig, credit_counter_E_in => credit_counter_E_in_sig, credit_counter_W_in => credit_counter_W_in_sig, credit_counter_S_in => credit_counter_S_in_sig, credit_counter_L_in => credit_counter_L_in_sig, -- Checker Outputs -- Not complete yet ! err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_N_credit_counter_N_out_increment => err_credit_in_N_credit_counter_N_out_increment, err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change => err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change, err_grant_N_credit_counter_N_out_decrement => err_grant_N_credit_counter_N_out_decrement, err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change => err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change, err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_E_credit_counter_E_out_increment => err_credit_in_E_credit_counter_E_out_increment, err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change => err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change, err_grant_E_credit_counter_E_out_decrement => err_grant_E_credit_counter_E_out_decrement, err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change => err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change, err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_W_credit_counter_W_out_increment => err_credit_in_W_credit_counter_W_out_increment, err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change => err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change, err_grant_W_credit_counter_W_out_decrement => err_grant_W_credit_counter_W_out_decrement, err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change => err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change, err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_S_credit_counter_S_out_increment => err_credit_in_S_credit_counter_S_out_increment, err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change => err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change, err_grant_S_credit_counter_S_out_decrement => err_grant_S_credit_counter_S_out_decrement, err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change => err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change, err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal, err_credit_in_L_credit_counter_L_out_increment => err_credit_in_L_credit_counter_L_out_increment, err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change => err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change, err_grant_L_credit_counter_L_out_decrement => err_grant_L_credit_counter_L_out_decrement, err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change => err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change, err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal ); END;
gpl-3.0
d8a71830698061404509b300b440cbf6
0.51178
3.729862
false
false
false
false
Wynjones1/gbvhdl
src/load_logic.vhd
1
5,604
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.types.all; use work.interfaces.all; entity load_logic is port( clk : in std_logic; reset : in std_logic; input : in load_logic_in_if; output : out load_logic_out_if); end entity; architecture rtl of load_logic is type state_t is (load_idle, load_n_0, load_nn_0, load_r_0, load_indirect, load_have_b, load_n_1, load_nn_1, load_r_1, load_have_a); signal state : state_t := load_idle; signal a16 : word_t := (others => '0'); -- write address begin main: process(clk) variable d16 : word_t; -- write data begin if reset = '1' then output.mem.address <= (others => '0'); state <= load_idle; elsif rising_edge(clk) then output.mem.we <= '0'; output.reg.we <= '0'; output.done <= '0'; case state is when load_idle => if input.en = '1' then if input.r1 = register_d8 or input.r1 = register_d16 then state <= load_n_0; output.mem.address <= std_logic_vector(unsigned(input.reg.pc) + 1); else state <= load_r_0; output.reg.rsel0 <= input.r1; end if; else state <= load_idle; end if; when load_n_0 => d16(LO_BYTE) := input.mem.data; if input.r1 = register_d16 then state <= load_nn_0; output.mem.address <= std_logic_vector(unsigned(input.reg.pc) + 2); elsif input.indirect = "10" then state <= load_indirect; output.mem.address <= x"ff" & input.mem.data; else state <= load_have_b; end if; when load_nn_0 => d16(HI_BYTE) := input.mem.data; if input.indirect = "10" then state <= load_indirect; output.mem.address <= d16; else state <= load_have_b; end if; when load_r_0 => if input.indirect = "10" then state <= load_indirect; if input.r0(3) = '1' then -- 16bit register output.mem.address <= input.reg.d0; else output.mem.address <= x"ff" & input.reg.d0(LO_BYTE); end if; else state <= load_have_b; d16 := input.reg.d0; end if; when load_indirect => state <= load_have_b; d16(LO_BYTE) := input.mem.data; when load_have_b => if input.r0 = register_d8 or input.r0 = register_d16 then state <= load_n_1; output.mem.address <= std_logic_vector(unsigned(input.reg.pc) + 1); else state <= load_r_1; output.reg.rsel0 <= input.r0; end if; when load_n_1 => if input.r0 = register_d16 then state <= load_have_a; output.mem.address <= x"ff" & input.mem.data; else state <= load_nn_1; a16(LO_BYTE) <= input.mem.data; output.mem.address <= std_logic_vector(unsigned(input.reg.pc) + 2); end if; when load_nn_1 => state <= load_have_a; a16(HI_BYTE) <= input.mem.data; when load_r_1 => if input.indirect = "01" then state <= load_have_a; if input.r0(3) = '1' then -- 16bit output.mem.address <= input.reg.d0; else output.mem.address <= x"ff" & input.reg.d0(LO_BYTE); end if; else state <= load_idle; output.reg.we <= '1'; output.reg.wsel <= input.r0; output.reg.data <= d16; output.done <= '1'; end if; when load_have_a => state <= load_idle; output.mem.we <= '1'; output.mem.address <= a16; output.mem.data <= d16(LO_BYTE); output.done <= '1'; if input.inc_dec = "01" then output.reg.we <= '1'; output.reg.wsel <= input.r0; output.reg.data <= std_logic_vector(unsigned(input.reg.hl) + 1); elsif input.inc_dec = "10" then output.reg.we <= '1'; output.reg.wsel <= input.r0; output.reg.data <= std_logic_vector(unsigned(input.reg.hl) - 1); end if; end case; end if; end process; end architecture;
mit
5733c0f2a4fa84498d3995c67b4416d9
0.391506
4.307456
false
false
false
false
AndyMcC0/UVVM_All
bitvis_uart/src/uart_pif_pkg.vhd
3
2,395
--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <[email protected]>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package uart_pif_pkg is -- Notation for regs: (Included in constant name as info to SW) -- - RW: Readable and writable reg. -- - RO: Read only reg. (output from IP) -- - WO: Write only reg. (typically single cycle strobe to IP) -- Notation for signals (or fields in record) going between PIF and core: -- Same notations as for register-constants above, but -- a preceeding 'a' (e.g. awo) means the register is auxiliary to the PIF. -- This means no flop in the PIF, but in the core. (Or just a dummy-register with no flop) constant C_ADDR_RX_DATA : integer := 0; constant C_ADDR_RX_DATA_VALID : integer := 1; constant C_ADDR_TX_DATA : integer := 2; constant C_ADDR_TX_READY : integer := 3; -- Signals from pif to core type t_p2c is record awo_tx_data : std_logic_vector(7 downto 0); awo_tx_data_we : std_logic; aro_rx_data_re : std_logic; end record t_p2c; -- Signals from core to PIF type t_c2p is record aro_rx_data : std_logic_vector(7 downto 0); aro_rx_data_valid : std_logic; aro_tx_ready : std_logic; end record t_c2p; end package uart_pif_pkg;
mit
72d9f558dd0a2bff27b3d1b45b5fde17
0.5762
4.201754
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/IMMORTAL_Chip_2017/Testbenches/ijtag_ram_access_tb.vhd
3
11,749
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 06/21/2017 05:18:09 PM -- Design Name: -- Module Name: ijtag_ram_access_tb - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity ijtag_ram_access_tb is end ijtag_ram_access_tb; architecture Behavioral of ijtag_ram_access_tb is constant ram_clk_period : time := 5 ns; constant tck_period : time := 10 ns; constant HALF_SEPARATOR : time := 2*tck_period; constant FULL_SEPARATOR : time := 8*tck_period; constant RAMDataSize : positive := 32; constant RAMAddrSize : positive := 12; signal toSI : STD_LOGIC; signal fromSO : STD_LOGIC; signal SE : STD_LOGIC; signal CE : STD_LOGIC; signal UE : STD_LOGIC; signal TCK : STD_LOGIC; signal RST : STD_LOGIC; signal SEL : STD_LOGIC; signal MEM_SIB_SEL : STD_LOGIC; signal RAM_data_read : STD_LOGIC_VECTOR (RAMDataSize-1 downto 0); signal RAM_data_write : STD_LOGIC_VECTOR (RAMDataSize-1 downto 0); signal RAM_address_out : STD_LOGIC_VECTOR (RAMAddrSize-1 downto 0); signal RAM_write_enable : STD_LOGIC; signal ram_enable : STD_LOGIC; signal wbe_shorted : STD_LOGIC_VECTOR (3 downto 0); signal RAM_address_out_padded : STD_LOGIC_VECTOR (31 downto 2); signal RAM_readout: std_logic_vector(RAMDataSize-1 downto 0); signal RAM_clk : STD_LOGIC := '0'; component ram is port(clk : in std_logic; reset : in std_logic; enable : in std_logic; write_byte_enable : in std_logic_vector(3 downto 0); address : in std_logic_vector(31 downto 2); data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0)); end component; component RAMAccessInstrument is Generic ( DataSize : positive := 8; AddressSize : positive := 8); Port ( -- Scan Interface scan_client ---------- SI : in STD_LOGIC; -- ScanInPort SO : out STD_LOGIC; -- ScanOutPort SEL : in STD_LOGIC; -- SelectPort ---------------------------------------- SE : in STD_LOGIC; -- ShiftEnPort CE : in STD_LOGIC; -- CaptureEnPort UE : in STD_LOGIC; -- UpdateEnPort RST : in STD_LOGIC; -- ResetPort TCK : in STD_LOGIC; -- TCKPort MEM_SIB_SEL : out STD_LOGIC; -- RAM interface RAM_data_read : in STD_LOGIC_VECTOR (DataSize-1 downto 0); RAM_data_write : out STD_LOGIC_VECTOR (DataSize-1 downto 0); RAM_address_out : out STD_LOGIC_VECTOR (AddressSize-1 downto 0); RAM_write_enable : out STD_LOGIC); end component; begin RAM_tsmc : ram port map(clk => TCK, --also possible with separate RAM_clk reset => RST, enable => ram_enable, write_byte_enable => wbe_shorted, address => RAM_address_out_padded, data_write => RAM_data_write, data_read => RAM_data_read ); RAM_clk <= not RAM_clk after ram_clk_period/2; ram_enable <= '1'; wbe_shorted <= (others => RAM_write_enable); RAM_address_out_padded <= "000000000000000000" & RAM_address_out; RAM_instr : RAMAccessInstrument generic map ( DataSize => RAMDataSize, AddressSize => RAMAddrSize) port map ( SI => toSI, SO => fromSO, SEL => SEL, SE => SE, CE => CE, UE => UE, RST => RST, TCK => TCK, MEM_SIB_SEL => MEM_SIB_SEL, RAM_data_read => RAM_data_read, RAM_data_write => RAM_data_write, RAM_address_out => RAM_address_out, RAM_write_enable => RAM_write_enable); --RAM_data_read <= "00000000000000001111000100000000"; ijtag_shift_proc: process -- Generate a number of TCK ticks procedure tck_tick (number_of_tick : in positive) is begin for i in 1 to number_of_tick loop TCK <= '0'; wait for TCK_period/2; TCK <= '1'; wait for TCK_period/2; end loop; end procedure tck_tick; procedure tck_halftick_high is begin TCK <= '1'; wait for TCK_period/2; end procedure tck_halftick_high; procedure tck_halftick_low is begin TCK <= '0'; wait for TCK_period/2; end procedure tck_halftick_low; -- Shifts in specified data (Capture -> Shift -> Update) procedure shift_data (data : in std_logic_vector) is begin --Capture phase CE <= '1'; tck_tick(1); CE <= '0'; --Shift phase SE <= '1'; for i in data'range loop toSI <= data(i); tck_tick(1); end loop; SE <= '0'; -- Update phase --tck_tick(1); tck_halftick_low; UE <= '1'; tck_halftick_high; tck_halftick_low; UE <= '0'; tck_halftick_high; end procedure shift_data; -- Shifts in specified data (Capture -> Shift -> Update) procedure shift_data_with_readout (data : in std_logic_vector; capture_data : out std_logic_vector) is begin --Capture phase CE <= '1'; tck_tick(1); CE <= '0'; --Shift phase SE <= '1'; for i in data'range loop toSI <= data(i); capture_data(i) := fromSO; tck_tick(1); end loop; SE <= '0'; -- Update phase --tck_tick(1); tck_halftick_low; UE <= '1'; tck_halftick_high; tck_halftick_low; UE <= '0'; tck_halftick_high; end procedure shift_data_with_readout; -- Returns all zeroes std_logic_vector of specified size function all_zeroes (number_of_zeroes : in positive) return std_logic_vector is variable zero_array : std_logic_vector(0 to number_of_zeroes-1); begin for i in zero_array'range loop zero_array(i) := '0'; end loop; return zero_array; end function all_zeroes; function reverse_vector (a: in std_logic_vector) return std_logic_vector is variable result: std_logic_vector(a'RANGE); alias aa: std_logic_vector(a'REVERSE_RANGE) is a; begin for i in aa'RANGE loop result(i) := aa(i); end loop; return result; end; procedure set_ram_address (address : in std_logic_vector(RAMAddrSize-1 downto 0); autoinc : in boolean; write_en : in boolean) is -- This function should be called in simulation when sib_mem is already opened, but sib_addr and sib_data are still closed -- After shifting in the provided bit vector, address sib is closed and data sib is opened constant open_mem_close_addr_sibs : std_logic_vector := "10"; constant open_sib_data : std_logic := '1'; variable autoincrement_bit : std_logic; variable writeen_bit : std_logic; variable bitstream_vector : std_logic_vector(0 to RAMAddrSize+4); begin if autoinc then autoincrement_bit := '1'; else autoincrement_bit := '0'; end if; if write_en then writeen_bit := '1'; else writeen_bit := '0'; end if; shift_data("11"&"0"); -- open sib_mem and sib_addr and close sib_data bitstream_vector(0 to 1) := open_mem_close_addr_sibs; bitstream_vector(2 to RAMAddrSize+1) := reverse_vector(address); bitstream_vector(RAMAddrSize+2) := autoincrement_bit; bitstream_vector(RAMAddrSize+3) := writeen_bit; bitstream_vector(RAMAddrSize+4) := open_sib_data; shift_data(bitstream_vector); end procedure set_ram_address; procedure get_set_data (write_data: in std_logic_vector (RAMDataSize-1 downto 0); read_data: out std_logic_vector (RAMDataSize-1 downto 0); leave_data_sib_open: in boolean) is -- This function should be called in simulation when sib_mem and sib_data is opened, but sib_addr is closed. constant open_mem_close_addr_sibs : std_logic_vector := "10"; variable leavedatasibopen_bit : std_logic; variable read_data_vector : std_logic_vector (RAMDataSize-1 downto 0) := (others => '0'); variable bitstream_vector : std_logic_vector (0 to RAMDataSize+2); variable readout_vector : std_logic_vector (0 to RAMDataSize+2); begin if leave_data_sib_open then leavedatasibopen_bit := '1'; else leavedatasibopen_bit := '0'; end if; tck_tick(3); --otherwise previous data can be captured bitstream_vector(0 to 1) := open_mem_close_addr_sibs; bitstream_vector(2) := leavedatasibopen_bit; bitstream_vector(3 to RAMDataSize+2) := reverse_vector(write_data); shift_data_with_readout(bitstream_vector, readout_vector); read_data := reverse_vector(readout_vector(3 to RAMDataSize+2)); end procedure get_set_data; variable read_out_data: std_logic_vector(RAMDataSize-1 downto 0); begin -- Reset iJTAG chain and Instruments RST <= '1'; wait for tck_period; RST <= '0'; SEL <= '1'; tck_tick(4); shift_data("1"); -- open sib_mem tck_tick(4); -- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA closed set_ram_address(X"003", true, true); -- Set WORD address to 0x003, autoincrement on, RAM write on -- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open get_set_data(X"0AA0F0F0", read_out_data, true); -- Shift in some data to write to address 0x003, increment address and leave SIB_DATA open -- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open get_set_data(X"0BB0FF00", read_out_data, true); -- Shift in some data to write to address 0x004, increment address and leave SIB_DATA open -- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open get_set_data(X"0CC0F00F", read_out_data, false); -- Shift in some data to write to address 0x005, increment address and close SIB_DATA -- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA closed set_ram_address(X"033", true, true); -- Set WORD address to 0x033, autoincrement on, RAM write on -- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open get_set_data(X"0000F0F0", read_out_data, true); -- Shift in some data to write to address 0x033, increment address and leave SIB_DATA open -- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open get_set_data(X"0000FF00", read_out_data, false); -- Shift in some data to write to address 0x034, increment address and close SIB_DATA -- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA closed set_ram_address(X"003", true, false); -- Set WORD address to 0x003, autoincrement off, RAM write off -- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open get_set_data(X"00000000", read_out_data, true); -- Shift in some data (no write) and leave SIB_DATA open, possible to read out data from address 0x003 -- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA open get_set_data(X"00000000", read_out_data, false); -- Shift in some data (no write) and close SIB_DATA, possible to read out data from address 0x004 -- Now SIB_MEM open, SIB_ADDR closed, SIB_DATA closed RAM_readout <= read_out_data; -- put data from word address 0x004 tck_tick(4); wait; end process; end Behavioral;
gpl-3.0
a53904c40623188701ac46efea70e356
0.612052
3.681918
false
false
false
false
SKravitsky/ECEC412
Registers.vhd
1
1,798
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Registers is port( RR1, RR2, WR : in std_logic_vector(4 downto 0); WD : in std_logic_vector(31 downto 0); RegWrite, Clk : in std_logic; RD1, RD2 : out std_logic_vector(31 downto 0) ); end Registers; architecture Structural of Registers is type mem_array is array(0 to 31) of std_logic_vector(31 downto 0); signal reg_mem: mem_array :=( X"00000000", --0 $zero (constant value 0) X"00000000", -- $at (reserved for the assembler) X"00000000", -- $v0 (value for results and expression) X"00000000", -- $v1 X"00000000", -- $a0 (arguments) X"00000000", --5 $a1 X"00000000", -- $a2 X"00000000", -- $a3 X"00000004", -- $t0 (temporaries) X"00000000", -- $t1 X"00000000", --10 $t2 X"00000000", -- $t3 X"00000000", -- $t4 X"00000000", -- $t5 X"00000000", -- $t6 X"00000000", --15 $t7 X"00000000", -- $s0 (saved) X"00000000", -- $s1 X"0000000D", -- $s2 X"00000004", -- $s3 X"00000000", --20 $s4 X"00000000", -- $s5 X"00000000", -- $s6 X"00000000", -- $s7 X"00000000", -- $t8 (more temporaries) X"00000000", --25 $t9 X"00000000", -- $k0 (reserved for the operating system) X"00000000", -- $k1 X"00000000", -- $gp (global pointer) X"00000000", -- $sp (stack pointer) X"00000000", --30 $fp (frame pointer) X"00000000" -- $ra (return address) ); begin RD1 <= reg_mem(to_integer(unsigned(RR1))); RD2 <= reg_mem(to_integer(unsigned(RR2))); process(Clk) begin if rising_edge(Clk) then if RegWrite = '1' then reg_mem(to_integer(unsigned(WR))) <= WD; end if; end if; end process; end Structural;
apache-2.0
2ce214b895ca4d202f98b2b6721938ab
0.569522
2.942717
false
false
false
false
AndyMcC0/UVVM_All
uvvm_util/src/alert_hierarchy_pkg.vhd
1
7,695
--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <[email protected]>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use std.textio.all; use std.env.all; use work.types_pkg.all; use work.protected_types_pkg.all; use work.hierarchy_linked_list_pkg.all; use work.string_methods_pkg.all; use work.adaptations_pkg.all; package alert_hierarchy_pkg is shared variable global_hierarchy_tree : t_hierarchy_linked_list; procedure initialize_hierarchy( constant base_scope : string := C_BASE_HIERARCHY_LEVEL; constant stop_limit : t_alert_counters := (others => 0) ); procedure add_to_alert_hierarchy( constant scope : string; constant parent_scope : string := C_BASE_HIERARCHY_LEVEL; constant stop_limit : t_alert_counters := (others => 0) ); procedure set_hierarchical_alert_top_level_stop_limit( constant alert_level : t_alert_level; constant value : natural ); impure function get_hierarchical_alert_top_level_stop_limit( constant alert_level : t_alert_level ) return natural; procedure hierarchical_alert( constant alert_level: t_alert_level; constant msg : string; constant scope : string; constant attention : t_attention ); procedure increment_expected_alerts( constant scope : string; constant alert_level: t_alert_level; constant amount : natural := 1 ); procedure set_expected_alerts( constant scope : string; constant alert_level: t_alert_level; constant expected_alerts : natural ); procedure increment_stop_limit( constant scope : string; constant alert_level: t_alert_level; constant amount : natural := 1 ); procedure set_stop_limit( constant scope : string; constant alert_level: t_alert_level; constant stop_limit : natural ); procedure print_hierarchical_log( constant order : t_order := FINAL ); procedure clear_hierarchy( constant VOID : t_void ); end package alert_hierarchy_pkg; package body alert_hierarchy_pkg is procedure initialize_hierarchy( constant base_scope : string := C_BASE_HIERARCHY_LEVEL; constant stop_limit : t_alert_counters := (others => 0) ) is begin global_hierarchy_tree.initialize_hierarchy(justify(base_scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH), stop_limit); end procedure; procedure add_to_alert_hierarchy( constant scope : string; constant parent_scope : string := C_BASE_HIERARCHY_LEVEL; constant stop_limit : t_alert_counters := (others => 0) ) is variable v_scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH) := justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH); variable v_parent_scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH) := justify(parent_scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH); variable v_hierarchy_node : t_hierarchy_node; variable v_found : boolean := false; begin global_hierarchy_tree.contains_scope_return_data(v_scope, v_found, v_hierarchy_node); if v_found then -- Scope already in tree. -- If the new parent is not C_BASE_HIERARCHY_LEVEL, change parent. -- The reason is that a child should be able to register itself -- with C_BASE_HIERARCHY_LEVEL as parent. The actual parent can then -- override the registration with a new parent_scope. However, the other -- way should not be possible. I.e., a child registration should not be able -- to override a parent registration later. That means that parents can't be -- changed back to base level once another parent_scope has been chosen. if v_parent_scope /= justify(C_BASE_HIERARCHY_LEVEL, LEFT, C_HIERARCHY_NODE_NAME_LENGTH) then -- Verify that new parent is in tree. If not, the old parent will be kept. global_hierarchy_tree.change_parent(v_scope, v_parent_scope); end if; else -- Scope not in tree. Check if parent is in tree. Set node data if -- parent is in tree. v_hierarchy_node := (v_scope, (others => (others => 0)), stop_limit, (others => true)); global_hierarchy_tree.insert_in_tree(v_hierarchy_node, v_parent_scope); end if; end procedure; procedure set_hierarchical_alert_top_level_stop_limit( constant alert_level : t_alert_level; constant value : natural ) is begin global_hierarchy_tree.set_top_level_stop_limit(alert_level, value); end procedure; impure function get_hierarchical_alert_top_level_stop_limit( constant alert_level : t_alert_level ) return natural is begin return global_hierarchy_tree.get_top_level_stop_limit(alert_level); end function; procedure hierarchical_alert( constant alert_level: t_alert_level; constant msg : string; constant scope : string; constant attention : t_attention ) is begin global_hierarchy_tree.alert(justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH), alert_level, attention, msg); end procedure; procedure increment_expected_alerts( constant scope : string; constant alert_level: t_alert_level; constant amount : natural := 1 ) is begin global_hierarchy_tree.increment_expected_alerts(justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH), alert_level, amount); end procedure; procedure set_expected_alerts( constant scope : string; constant alert_level: t_alert_level; constant expected_alerts : natural ) is begin global_hierarchy_tree.set_expected_alerts(justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH), alert_level, expected_alerts); end procedure; procedure increment_stop_limit( constant scope : string; constant alert_level: t_alert_level; constant amount : natural := 1 ) is begin global_hierarchy_tree.increment_stop_limit(justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH), alert_level, amount); end procedure; procedure set_stop_limit( constant scope : string; constant alert_level: t_alert_level; constant stop_limit : natural ) is begin global_hierarchy_tree.set_stop_limit(justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH), alert_level, stop_limit); end procedure; procedure print_hierarchical_log( constant order : t_order := FINAL ) is begin global_hierarchy_tree.print_hierarchical_log(order); end procedure; procedure clear_hierarchy( constant VOID : t_void ) is begin global_hierarchy_tree.clear; end procedure; end package body alert_hierarchy_pkg;
mit
5dd77c17c0011a0f03fd583d96818053
0.65601
4.114973
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/IMMORTAL_Chip_2017/Testbenches/immortal_slack_monitor_tb.vhd
3
4,459
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 06/21/2017 05:18:09 PM -- Design Name: -- Module Name: immortal_slack_monitor_tb - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity immortal_slack_monitor_tb is end immortal_slack_monitor_tb; architecture Behavioral of immortal_slack_monitor_tb is constant tck_period : time := 10 ns; constant HALF_SEPARATOR : time := 2*tck_period; constant FULL_SEPARATOR : time := 8*tck_period; signal toSI : STD_LOGIC; signal fromSO : STD_LOGIC; signal SE : STD_LOGIC; signal CE : STD_LOGIC; signal UE : STD_LOGIC; signal TCK : STD_LOGIC; signal RST : STD_LOGIC; signal SEL : STD_LOGIC; signal toF : STD_LOGIC; signal toC : STD_LOGIC; signal slack_control : std_logic_vector (2 downto 0); signal slack_data : std_logic_vector (31 downto 0); component immortal_slack_monitor_instrument is port ( -- IJTAG connection TCK : in std_logic; RST : in std_logic; SEL : in std_logic; SI : in std_logic; SE : in std_logic; UE : in std_logic; CE : in std_logic; SO : out std_logic; toF : out std_logic; toC : out std_logic; -- Monitor connections control : out std_logic_vector(2 downto 0); data : in std_logic_vector(31 downto 0) ); end component; begin slack_monitor : immortal_slack_monitor_instrument port map ( -- IJTAG connection TCK => TCK, RST => RST, SEL => SEL, SI => toSI, SE => SE, UE => UE, CE => CE, SO => fromSO, toF => toF, toC => toC, -- Monitor connections control => slack_control, data => slack_data ); ijtag_shift_proc: process -- Generate a number of TCK ticks procedure tck_tick (number_of_tick : in positive) is begin for i in 1 to number_of_tick loop TCK <= '0'; wait for TCK_period/2; TCK <= '1'; wait for TCK_period/2; end loop; end procedure tck_tick; procedure tck_halftick_high is begin TCK <= '1'; wait for TCK_period/2; end procedure tck_halftick_high; procedure tck_halftick_low is begin TCK <= '0'; wait for TCK_period/2; end procedure tck_halftick_low; -- Shifts in specified data (Capture -> Shift -> Update) procedure shift_data (data : in std_logic_vector) is begin --Capture phase CE <= '1'; tck_tick(1); CE <= '0'; --Shift phase SE <= '1'; for i in data'range loop toSI <= data(i); tck_tick(1); end loop; SE <= '0'; -- Update phase --tck_tick(1); tck_halftick_low; UE <= '1'; tck_halftick_high; tck_halftick_low; UE <= '0'; tck_halftick_high; end procedure shift_data; -- Returns all zeroes std_logic_vector of specified size function all_zeroes (number_of_zeroes : in positive) return std_logic_vector is variable zero_array : std_logic_vector(0 to number_of_zeroes-1); begin for i in zero_array'range loop zero_array(i) := '0'; end loop; return zero_array; end function all_zeroes; begin slack_data <= "01010101010101010101010101001010"; UE <= '0'; CE <= '0'; SE <= '0'; toSI <= '0'; -- Reset iJTAG chain and Instruments RST <= '1'; wait for tck_period; RST <= '0'; SEL <= '1'; tck_tick(4); shift_data("11100"&"00000"&"0"&"1"&"1"&"0000000000000001111"); -- shift in threshold H without update tck_tick(4); slack_data <= "00101010101010101010101010101010"; tck_tick(4); wait; end process; end Behavioral;
gpl-3.0
43788d0b4f3ba6c0fcb6806c6dc19e5a
0.559542
3.794894
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/Allocator_with_checkers_with_FI/Arbiter_in_one_hot_with_checkers_with_FI.vhd
3
13,338
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use work.component_pack.all; -- Is this like the old arbiter in the router with handshaking FC ?? entity Arbiter_in is port ( reset: in std_logic; clk: in std_logic; Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L: in std_logic; -- From LBDR modules X_N, X_E, X_W, X_S, X_L: out std_logic; -- Grants given to LBDR requests (encoded as one-hot) -- fault injector shift register with serial input signals TCK: in std_logic; SE: in std_logic; -- shift enable UE: in std_logic; -- update enable SI: in std_logic; -- serial Input SO: out std_logic; -- serial output -- Checker outputs err_Requests_state_in_state_not_equal, err_IDLE_Req_N, err_IDLE_grant_N,err_North_Req_N, err_North_grant_N, err_East_Req_E, err_East_grant_E, err_West_Req_W, err_West_grant_W, err_South_Req_S,err_South_grant_S,err_Local_Req_L, err_Local_grant_L, err_IDLE_Req_E, err_IDLE_grant_E, err_North_Req_E, err_North_grant_E, err_East_Req_W, err_East_grant_W, err_West_Req_S, err_West_grant_S, err_South_Req_L, err_South_grant_L, err_Local_Req_N, err_Local_grant_N, err_IDLE_Req_W, err_IDLE_grant_W, err_North_Req_W, err_North_grant_W, err_East_Req_S, err_East_grant_S, err_West_Req_L, err_West_grant_L, err_South_Req_N, err_South_grant_N, err_Local_Req_E, err_Local_grant_E, err_IDLE_Req_S, err_IDLE_grant_S, err_North_Req_S, err_North_grant_S, err_East_Req_L, err_East_grant_L, err_West_Req_N, err_West_grant_N, err_South_Req_E, err_South_grant_E, err_Local_Req_W, err_Local_grant_W, err_IDLE_Req_L, err_IDLE_grant_L, err_North_Req_L, err_North_grant_L, err_East_Req_N, err_East_grant_N, err_West_Req_E, err_West_grant_E, err_South_Req_W, err_South_grant_W, err_Local_Req_S, err_Local_grant_S, err_state_in_onehot, err_no_request_grants, err_request_no_grants, err_no_Req_N_grant_N, err_no_Req_E_grant_E, err_no_Req_W_grant_W, err_no_Req_S_grant_S, err_no_Req_L_grant_L : out std_logic ); end Arbiter_in; architecture behavior of Arbiter_in is component shift_register_serial_in is generic ( REG_WIDTH: integer := 32 ); port ( TCK, reset : in std_logic; SE: in std_logic; -- shift enable UE: in std_logic; -- update enable SI: in std_logic; -- serial Input SO: out std_logic; -- serial output data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0) ); end component; ---------------------------------------- -- Signals related to fault injection -- ---------------------------------------- -- Total: 7 bits signal FI_add_sta: std_logic_vector (6 downto 0); -- 5 bits for fault injection location address (ceil of log2(17) = 5) -- 2 bits for type of fault (SA0 or SA1) signal non_faulty_signals: std_logic_vector (16 downto 0); -- 17 bits for internal- and output-related signals (non-faulty) signal faulty_signals: std_logic_vector(16 downto 0); -- 17 bits for internal- and output-related signals (with single stuck-at fault injected in one of them) ---------------------------------------- ---------------------------------------- --TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local); --SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0); --SIGNAL state, state_in : STATE_TYPE := IDLE; SIGNAL state, state_in : STD_LOGIC_VECTOR (5 downto 0) := IDLE; SIGNAL X_N_sig, X_E_sig, X_W_sig, X_S_sig, X_L_sig: std_logic; -- needed for connecting output ports -- of Arbiter_in to checker inputs -- Signal(s) used for creating the chain of injected fault locations -- Total: 17 bits ??!! -- Arbiter_in internal-related signals signal state_faulty, state_in_faulty: std_logic_vector(5 downto 0); -- Arbiter_in output-related signals signal X_N_sig_faulty, X_E_sig_faulty, X_W_sig_faulty, X_S_sig_faulty, X_L_sig_faulty: std_logic; begin ------------------------------------- ---- Related to fault injection ----- ------------------------------------- -- Total: 17 bits -- for X_N, ... , X_L output signals, not sure whether to include them or the signals with _sig suffix in their names ??!! non_faulty_signals <= state & state_in & X_N_sig & X_E_sig & X_W_sig & X_S_sig & X_L_sig; -- Fault injector module instantiation FI: fault_injector generic map(DATA_WIDTH => 17, ADDRESS_WIDTH => 5) port map (data_in=> non_faulty_signals , address => FI_add_sta(6 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals ); -- Extracting faulty values for internal- and output-related signals -- Total: 17 bits state_faulty <= faulty_signals (16 downto 11); state_in_faulty <= faulty_signals (10 downto 5); X_N_sig_faulty <= faulty_signals (4); X_E_sig_faulty <= faulty_signals (3); X_W_sig_faulty <= faulty_signals (2); X_S_sig_faulty <= faulty_signals (1); X_L_sig_faulty <= faulty_signals (0); -- Total: 7 bits SR: shift_register_serial_in generic map(REG_WIDTH => 7) port map ( TCK=> TCK, reset=>reset, SE=> SE, UE=> UE, SI=> SI, SO=> SO, data_out_parallel=> FI_add_sta ); ------------------------------------- ------------------------------------- -- Becuase of checkers we did this X_N <= X_N_sig; X_E <= X_E_sig; X_W <= X_W_sig; X_S <= X_S_sig; X_L <= X_L_sig; -- Arbiter_in Checkers module instantiation ARBITER_IN_CHECKERS: Arbiter_in_one_hot_checkers port map ( req_X_N => req_X_N, -- _sig not needed, because it is an input port req_X_E => req_X_E, -- _sig not needed, because it is an input port req_X_W => req_X_W, -- _sig not needed, because it is an input port req_X_S => req_X_S, -- _sig not needed, because it is an input port req_X_L => req_X_L, -- _sig not needed, because it is an input port state => state_faulty, -- _sig not needed, because it is an input port state_in => state_in_faulty, -- _sig not needed, because it is an internal signal X_N => X_N_sig_faulty, X_E => X_E_sig_faulty, X_W => X_W_sig_faulty, X_S => X_S_sig_faulty, X_L => X_L_sig_faulty, -- Checker outputs err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal, err_IDLE_Req_N => err_IDLE_Req_N, err_IDLE_grant_N => err_IDLE_grant_N, err_North_Req_N => err_North_Req_N, err_North_grant_N => err_North_grant_N, err_East_Req_E => err_East_Req_E, err_East_grant_E => err_East_grant_E, err_West_Req_W => err_West_Req_W, err_West_grant_W => err_West_grant_W, err_South_Req_S => err_South_Req_S, err_South_grant_S => err_South_grant_S, err_Local_Req_L => err_Local_Req_L, err_Local_grant_L => err_Local_grant_L, err_IDLE_Req_E => err_IDLE_Req_E, err_IDLE_grant_E => err_IDLE_grant_E, err_North_Req_E => err_North_Req_E, err_North_grant_E => err_North_grant_E, err_East_Req_W => err_East_Req_W, err_East_grant_W => err_East_grant_W, err_West_Req_S => err_West_Req_S, err_West_grant_S => err_West_grant_S, err_South_Req_L => err_South_Req_L, err_South_grant_L => err_South_grant_L, err_Local_Req_N => err_Local_Req_N, err_Local_grant_N => err_Local_grant_N, err_IDLE_Req_W => err_IDLE_Req_W, err_IDLE_grant_W => err_IDLE_grant_W, err_North_Req_W => err_North_Req_W, err_North_grant_W => err_North_grant_W, err_East_Req_S => err_East_Req_S, err_East_grant_S => err_East_grant_S, err_West_Req_L => err_West_Req_L, err_West_grant_L => err_West_grant_L, err_South_Req_N => err_South_Req_N, err_South_grant_N => err_South_grant_N, err_Local_Req_E => err_Local_Req_E, err_Local_grant_E => err_Local_grant_E, err_IDLE_Req_S => err_IDLE_Req_S, err_IDLE_grant_S => err_IDLE_grant_S, err_North_Req_S => err_North_Req_S, err_North_grant_S => err_North_grant_S, err_East_Req_L => err_East_Req_L, err_East_grant_L => err_East_grant_L, err_West_Req_N => err_West_Req_N, err_West_grant_N => err_West_grant_N, err_South_Req_E => err_South_Req_E, err_South_grant_E => err_South_grant_E, err_Local_Req_W => err_Local_Req_W, err_Local_grant_W => err_Local_grant_W, err_IDLE_Req_L => err_IDLE_Req_L, err_IDLE_grant_L => err_IDLE_grant_L, err_North_Req_L => err_North_Req_L, err_North_grant_L => err_North_grant_L, err_East_Req_N => err_East_Req_N, err_East_grant_N => err_East_grant_N, err_West_Req_E => err_West_Req_E, err_West_grant_E => err_West_grant_E, err_South_Req_W => err_South_Req_W, err_South_grant_W => err_South_grant_W, err_Local_Req_S => err_Local_Req_S, err_Local_grant_S => err_Local_grant_S, err_state_in_onehot => err_state_in_onehot, err_no_request_grants => err_no_request_grants, err_request_no_grants => err_request_no_grants, err_no_Req_N_grant_N => err_no_Req_N_grant_N, err_no_Req_E_grant_E => err_no_Req_E_grant_E, err_no_Req_W_grant_W => err_no_Req_W_grant_W, err_no_Req_S_grant_S => err_no_Req_S_grant_S, err_no_Req_L_grant_L => err_no_Req_L_grant_L ); -- Sequential part process (clk, reset)begin if reset = '0' then state <= IDLE; elsif clk'event and clk ='1'then state <= state_in; end if; end process; -- anything below here is pure combinational -- Main Logic of Arbiter_in process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L) begin X_N_sig <= '0'; X_E_sig <= '0'; X_W_sig <= '0'; X_S_sig <= '0'; X_L_sig <= '0'; case state is when IDLE => -- In the arbiter for hand-shaking FC router, L had the highest priority (L, N, E, W, S) -- Here it seems N has the higest priority, is it fine ? if req_X_N ='1' then state_in <= North; X_N_sig <= '1'; elsif req_X_E = '1' then state_in <= East; X_E_sig <= '1'; elsif req_X_W = '1' then state_in <= West; X_W_sig <= '1'; elsif req_X_S = '1' then state_in <= South; X_S_sig <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; else state_in <= state; end if; when North => if req_X_N ='1' then state_in <= North; X_N_sig <= '1'; elsif req_X_E = '1' then state_in <= East; X_E_sig <= '1'; elsif req_X_W = '1' then state_in <= West; X_W_sig <= '1'; elsif req_X_S = '1' then state_in <= South; X_S_sig <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; else state_in <= state; end if; when East => if req_X_E = '1' then state_in <= East; X_E_sig <= '1'; elsif req_X_W = '1' then state_in <= West; X_W_sig <= '1'; elsif req_X_S = '1' then state_in <= South; X_S_sig <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; elsif req_X_N ='1' then state_in <= North; X_N_sig <= '1'; else state_in <= state; end if; when West => if req_X_W = '1' then state_in <= West; X_W_sig <= '1'; elsif req_X_S = '1' then state_in <= South; X_S_sig <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; elsif req_X_N ='1' then state_in <= North; X_N_sig <= '1'; elsif req_X_E = '1' then state_in <= East; X_E_sig <= '1'; else state_in <= state; end if; when South => if req_X_S = '1' then state_in <= South; X_S_sig <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; elsif req_X_N ='1' then state_in <= North; X_N_sig <= '1'; elsif req_X_E = '1' then state_in <= East; X_E_sig <= '1'; elsif req_X_W = '1' then state_in <= West; X_W_sig <= '1'; else state_in <= state; end if; when others => if req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; elsif req_X_N ='1' then state_in <= North; X_N_sig <= '1'; elsif req_X_E = '1' then state_in <= East; X_E_sig <= '1'; elsif req_X_W = '1' then state_in <= West; X_W_sig <= '1'; elsif req_X_S = '1' then state_in <= South; X_S_sig <= '1'; else state_in <= state; end if; end case; end process; end;
gpl-3.0
ede3f9ad31280be45f325f9a04870c71
0.535163
2.956117
false
false
false
false
ashtonchase/logic_analyzer
src/sump_comms.vhd
1
6,565
------------------------------------------------------------------------------- -- Title : Top module for serial comms with sump gui -- Project : fpga_logic_analyzer ------------------------------------------------------------------------------- -- File : SUMPComms.vhd -- Created : 2016-02-22 -- Last update: 2016-04-10 -- Standard : VHDL'08 ------------------------------------------------------------------------------- -- Description: This is the top module for comms between the SUMP module and -- the logic analyzer. It will handle the RS232 communication. It will handle -- coordination with the message passing and memory modules using data lines -- and handshaking. -- The clock rate and baud rate need to be specified in this module. -- This will be converted to a state machine ------------------------------------------------------------------------------- -- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt ------------------------------------------------------------------------------- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-02-22 1.0 ian Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.all; entity SUMPComms is generic (baud_rate : positive := 9600; clock_freq : positive := 100_000_000); -- Make sure we keep integer division here port(clk : in std_logic; -- clock rst : in std_logic; -- reset rx : in std_logic; -- data line from top level tx : out std_logic; tx_command : in std_logic_vector(7 downto 0); -- data from storage command_ready : out std_logic; -- flags for data message collect data_ready : in std_logic; -- flag for transmit message data_sent : out std_logic; -- flag for transmit message command : out std_logic_vector(7 downto 0)); -- commands for message handler end entity SUMPComms; architecture comms of SUMPComms is type states is (Init, Wait_State, Drop_Wait, Command_Received, Wait_For_Ready, Shift_Data, Send_Data, Send_Complete); signal rx_curr_state, rx_next_state, tx_curr_state, tx_next_state : states := INIT; signal rx_get_more_data : std_logic; -- stop bit found for stream in signal rx_data_ready : std_logic; -- stream out ready signal data_out : std_logic_vector(7 downto 0) := (others => '0'); signal tx_data_in : std_logic_vector(7 downto 0) := (others => '0'); -- data to be transmitted signal tx_data_ready : std_logic; -- stream out stop bit sent signal tx_data_sent : std_logic; -- ready for rx signal tx_send_counter : integer range 0 to 4 := 0; -- signal tx_data_buffer : std_logic_vector(31 downto 0); signal comm_signal : std_logic_vector(7 downto 0); -- commands for message handler begin u1 : entity work.uart_comms generic map (clock_freq => clock_freq, baud_rate => baud_rate) port map ( clk => clk, rst => rst, rx_get_more_data => rx_get_more_data, rx_data_ready => rx_data_ready, rx => rx, data_in => tx_data_in, tx_data_ready => tx_data_ready, tx_data_sent => tx_data_sent, tx => tx, data_out => data_out); command_reciever : process (clk) begin clock_entry : if rst = '1' then rx_next_state <= Init; elsif (clk = '1' and clk'event) then rx_get_more_data <= '1'; command_ready <= '0'; state_selector : case rx_curr_state is when Init => rx_next_state <= Wait_State; command_ready <= '0'; when Wait_State => rx_next_state <= Wait_State; if rx_data_ready = '1' then rx_next_state <= Command_Received; -- comm_signal <= data_out; command <= data_out; command_ready <= '1'; end if; when Command_Received => rx_next_state <= Command_Received; if rx_data_ready = '0' then rx_next_state <= Wait_State; end if; when others => rx_next_state <= Init; end case state_selector; end if clock_entry; rx_curr_state <= rx_next_state; end process command_reciever; command_sender : process (clk) begin clock_entry : if rst = '1' then tx_next_state <= Init; elsif (clk = '1' and clk'event) then data_sent <= '0'; tx_data_ready <= '0'; state_selector : case tx_curr_state is when Init => tx_next_state <= Wait_State; -- data_sent <= '1'; when Wait_State => tx_next_state <= Wait_State; data_sent <= '1'; if data_ready = '1' then data_sent <= '0'; tx_data_ready <= '1'; tx_data_in <= tx_command; tx_next_state <= Send_Data; end if; when Send_Data => tx_data_ready <= '1'; tx_next_state <= Send_Data; if tx_data_sent = '1' then tx_next_state <= Drop_Wait; end if; when Drop_Wait => tx_next_state <= Drop_Wait; if tx_data_sent = '0' then tx_next_state <= Send_Complete; end if; when Send_Complete => tx_next_state <= Wait_State; --data_sent <= '1'; when others => tx_next_state <= Init; end case state_selector; end if clock_entry; tx_curr_state <= tx_next_state; end process command_sender; end architecture comms;
gpl-2.0
7572902d5171b8007a11d4c3090875cc
0.531607
4.052469
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/Allocator_with_checkers_with_FI/Arbiter_out_one_hot_pseudo_checkers.vhd
3
18,996
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; use work.component_pack.all; entity Arbiter_out_one_hot_pseudo_checkers is port ( credit: in std_logic_vector(1 downto 0); req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : in std_logic; -- Grants given to LBDR requests (encoded as one-hot) state_in: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM -- Checker outputs err_Requests_state_in_state_not_equal, err_IDLE_req_X_N, err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N, err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E, err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W, err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S, err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L, err_IDLE_req_X_E, err_North_req_X_E, err_East_req_X_W, err_West_req_X_S, err_South_req_X_L, err_Local_req_X_N, err_IDLE_req_X_W, err_North_req_X_W, err_East_req_X_S, err_West_req_X_L, err_South_req_X_N, err_Local_req_X_E, err_IDLE_req_X_S, err_North_req_X_S, err_East_req_X_L, err_West_req_X_N, err_South_req_X_E, err_Local_req_X_W, err_IDLE_req_X_L, err_North_req_X_L, err_East_req_X_N, err_West_req_X_E, err_South_req_X_W, err_Local_req_X_S, err_state_in_onehot, err_no_request_grants, err_request_IDLE_state, err_request_IDLE_not_Grants, err_state_North_Invalid_Grant, err_state_East_Invalid_Grant, err_state_West_Invalid_Grant, err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant, err_Grants_onehot_or_all_zero : out std_logic ); end Arbiter_out_one_hot_pseudo_checkers; architecture behavior of Arbiter_out_one_hot_pseudo_checkers is SIGNAL Requests: std_logic_vector (4 downto 0); SIGNAL Grants: std_logic_vector (4 downto 0); begin Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L; Grants <= grant_Y_N & grant_Y_E & grant_Y_W & grant_Y_S & grant_Y_L; -- Checkers process (Requests, state_in) begin err_Requests_state_in_state_not_equal <= '0'; if (Requests = "00000" and state_in /= IDLE ) then err_Requests_state_in_state_not_equal <= '1'; end if; end process; ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- -- Round 1 -- N has highest priority, then E, W, S and L (and then again N). process (state, req_X_N, state_in) begin err_IDLE_req_X_N <= '0'; if ( state = IDLE and req_X_N = '1' and state_in /= North ) then err_IDLE_req_X_N <= '1'; end if; end process; process (state, req_X_N, state_in) begin err_North_req_X_N <= '0'; if (state = North and req_X_N = '1' and state_in /= North) then err_North_req_X_N <= '1'; end if; end process; process (state, credit, req_X_N, grant_Y_N) begin err_North_credit_not_zero_req_X_N_grant_N <= '0'; if ( state = North and credit /= "00" and req_X_N = '1' and grant_Y_N /= '1' ) then err_North_credit_not_zero_req_X_N_grant_N <= '1'; end if; end process; process (state, credit, req_X_N, grant_Y_N) begin err_North_credit_zero_or_not_req_X_N_not_grant_N <= '0'; if ( state = North and (credit = "00" or req_X_N = '0') and grant_Y_N /= '0' ) then err_North_credit_zero_or_not_req_X_N_not_grant_N <= '1'; end if; end process; process (state, req_X_E, state_in) begin err_East_req_X_E <= '0'; if (state = East and req_X_E = '1' and state_in /= East) then err_East_req_X_E <= '1'; end if; end process; process (state, credit, req_X_E, grant_Y_E) begin err_East_credit_not_zero_req_X_E_grant_E <= '0'; if ( state = East and credit /= "00" and req_X_E = '1' and grant_Y_E = '0' ) then err_East_credit_not_zero_req_X_E_grant_E <= '1'; end if; end process; process (state, credit, req_X_E, grant_Y_E) begin err_East_credit_zero_or_not_req_X_E_not_grant_E <= '0'; if ( state = East and (credit = "00" or req_X_E = '0') and grant_Y_E /= '0' ) then err_East_credit_zero_or_not_req_X_E_not_grant_E <= '1'; end if; end process; process (state, req_X_W, state_in) begin err_West_req_X_W <= '0'; if (state = West and req_X_W = '1' and state_in /= West) then err_West_req_X_W <= '1'; end if; end process; process (state, credit, req_X_W, grant_Y_W) begin err_West_credit_not_zero_req_X_W_grant_W <= '0'; if ( state = West and credit /= "00" and req_X_W = '1' and grant_Y_W = '0') then err_West_credit_not_zero_req_X_W_grant_W <= '1'; end if; end process; process (state, credit, req_X_W, grant_Y_W) begin err_West_credit_zero_or_not_req_X_W_not_grant_W <= '0'; if ( state = West and (credit = "00" or req_X_W = '0') and grant_Y_W /= '0' ) then err_West_credit_zero_or_not_req_X_W_not_grant_W <= '1'; end if; end process; process (state, req_X_S, state_in) begin err_South_req_X_S <= '0'; if (state = South and req_X_S = '1' and state_in /= South) then err_South_req_X_S <= '1'; end if; end process; process (state, credit, req_X_S, grant_Y_S) begin err_South_credit_not_zero_req_X_S_grant_S <= '0'; if ( state = South and credit /= "00" and req_X_S = '1' and grant_Y_S = '0' ) then err_South_credit_not_zero_req_X_S_grant_S <= '1'; end if; end process; process (state, credit, req_X_S, grant_Y_S) begin err_South_credit_zero_or_not_req_X_S_not_grant_S <= '0'; if ( state = South and (credit = "00" or req_X_S = '0') and grant_Y_S /= '0' ) then err_South_credit_zero_or_not_req_X_S_not_grant_S <= '1'; end if; end process; -- Local is a bit different (including others case) process (state, req_X_L, state_in) begin err_Local_req_X_L <= '0'; if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and req_X_L = '1' and state_in /= Local) then err_Local_req_X_L <= '1'; end if; end process; process (state, credit, req_X_L, grant_Y_L) begin err_Local_credit_not_zero_req_X_L_grant_L <= '0'; if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and credit /= "00" and req_X_L = '1' and grant_Y_L = '0' ) then err_Local_credit_not_zero_req_X_L_grant_L <= '1'; end if; end process; process (state, credit, req_X_L, grant_Y_L) begin err_Local_credit_zero_or_not_req_X_L_not_grant_L <= '0'; if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and ( credit = "00" or req_X_L = '0') and grant_Y_L /= '0' ) then err_Local_credit_zero_or_not_req_X_L_not_grant_L <= '1'; end if; end process; ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- -- Round 2 -- IDLE process (state, req_X_N, req_X_E, state_in) begin err_IDLE_req_X_E <= '0'; if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then err_IDLE_req_X_E <= '1'; end if; end process; -- North process (state, req_X_N, req_X_E, state_in) begin err_North_req_X_E <= '0'; if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then err_North_req_X_E <= '1'; end if; end process; -- East process (state, req_X_E, req_X_W, state_in) begin err_East_req_X_W <= '0'; if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then err_East_req_X_W <= '1'; end if; end process; -- West process (state, req_X_W, req_X_S, state_in) begin err_West_req_X_S <= '0'; if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then err_West_req_X_S <= '1'; end if; end process; -- South -- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers -- for the router with CTS/RTS handshaking Flow Control process (state, req_X_S, req_X_L, state_in) begin err_South_req_X_L <= '0'; if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then err_South_req_X_L <= '1'; end if; end process; -- Local and invalid states (others case) process (state, req_X_L, req_X_N, state_in) begin err_Local_req_X_N <= '0'; if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and req_X_L = '0' and req_X_N = '1' and state_in /= North) then err_Local_req_X_N <= '1'; end if; end process; ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- -- Round 3 process (state, req_X_N, req_X_E, req_X_W, state_in) begin err_IDLE_req_X_W <= '0'; if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then err_IDLE_req_X_W <= '1'; end if; end process; process (state, req_X_N, req_X_E, req_X_W, state_in) begin err_North_req_X_W <= '0'; if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then err_North_req_X_W <= '1'; end if; end process; process (state, req_X_E, req_X_W, req_X_S, state_in) begin err_East_req_X_S <= '0'; if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then err_East_req_X_S <= '1'; end if; end process; process (state, req_X_W, req_X_S, req_X_L, state_in) begin err_West_req_X_L <= '0'; if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then err_West_req_X_L <= '1'; end if; end process; process (state, req_X_S, req_X_L, req_X_N, state_in) begin err_South_req_X_N <= '0'; if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then err_South_req_X_N <= '1'; end if; end process; -- Local and invalid state(s) (others case) process (state, req_X_L, req_X_N, req_X_E, state_in) begin err_Local_req_X_E <= '0'; if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then err_Local_req_X_E <= '1'; end if; end process; ----------------------------------------------------------------------------------------------------------------------- -- Round 4 process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in) begin err_IDLE_req_X_S <= '0'; if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then err_IDLE_req_X_S <= '1'; end if; end process; process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in) begin err_North_req_X_S <= '0'; if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then err_North_req_X_S <= '1'; end if; end process; process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in) begin err_East_req_X_L <= '0'; if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then err_East_req_X_L <= '1'; end if; end process; process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in) begin err_West_req_X_N <= '0'; if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then err_West_req_X_N <= '1'; end if; end process; process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in) begin err_South_req_X_E <= '0'; if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then err_South_req_X_E <= '1'; end if; end process; -- Local state or invalid state(s) (others case) process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in) begin err_Local_req_X_W <= '0'; if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then err_Local_req_X_W <= '1'; end if; end process; ----------------------------------------------------------------------------------------------------------------------- -- Round 5 process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in) begin err_IDLE_req_X_L <= '0'; if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then err_IDLE_req_X_L <= '1'; end if; end process; process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in) begin err_North_req_X_L <= '0'; if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then err_North_req_X_L <= '1'; end if; end process; process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in) begin err_East_req_X_N <= '0'; if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then err_East_req_X_N <= '1'; end if; end process; process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in) begin err_West_req_X_E <= '0'; if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then err_West_req_X_E <= '1'; end if; end process; process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in) begin err_South_req_X_W <= '0'; if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then err_South_req_X_W <= '1'; end if; end process; -- Local state or invalid state(s) (others case) process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in) begin err_Local_req_X_S <= '0'; if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then err_Local_req_X_S <= '1'; end if; end process; ----------------------------------------------------------------------------------------------------------------------- process (state_in) begin err_state_in_onehot <= '0'; if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and state_in /= South and state_in /= Local) then err_state_in_onehot <= '1'; end if; end process; process (Requests, Grants) begin err_no_request_grants <= '0'; if ( Requests = "00000" and Grants /= "00000") then err_no_request_grants <= '1'; end if; end process; process (Requests, state_in) begin err_request_IDLE_state <= '0'; if (Requests /= "00000" and state_in = IDLE) then err_request_IDLE_state <= '1'; end if; end process; ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- process (state, Grants) begin err_request_IDLE_not_Grants <= '0'; if (state = IDLE and Grants /= "00000") then err_request_IDLE_not_Grants <= '1'; end if; end process; process (state, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L) begin err_state_North_Invalid_Grant <= '0'; if (state = North and (grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then err_state_North_Invalid_Grant <= '1'; end if; end process; process (state, grant_Y_N, grant_Y_W, grant_Y_S, grant_Y_L) begin err_state_East_Invalid_Grant <= '0'; if (state = East and (grant_Y_N = '1' or grant_Y_W = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then err_state_East_Invalid_Grant <= '1'; end if; end process; process (state, grant_Y_N, grant_Y_E, grant_Y_S, grant_Y_L) begin err_state_West_Invalid_Grant <= '0'; if (state = West and (grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then err_state_West_Invalid_Grant <= '1'; end if; end process; process (state, grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_L) begin err_state_South_Invalid_Grant <= '0'; if (state = South and (grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_L = '1') ) then err_state_South_Invalid_Grant <= '1'; end if; end process; -- Local or invalid state(s) (a bit different logic!) process (state, grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S) begin err_state_Local_Invalid_Grant <= '0'; if (state /= IDLE and state /= North and state /= East and state /= West and state /= South and (grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_S = '1') ) then err_state_Local_Invalid_Grant <= '1'; end if; end process; -- Because we do not have multi-casting, Grants must always be one-hot or all zeros, no other possible combination for them ! process (Grants) begin err_Grants_onehot_or_all_zero <= '0'; if (Grants /= "00000" and Grants /= "00001" and Grants /= "00010" and Grants /= "00100" and Grants /= "01000" and Grants /= "10000") then err_Grants_onehot_or_all_zero <= '1'; end if; end process; end behavior;
gpl-3.0
b23c6b4777f74432c9178791acdb1fb1
0.533428
2.668352
false
false
false
false
elainemielas/CVUT_BI-PNO
cvika/had/counter.vhd
1
1,598
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; use IEEE.std_logic_arith.all; use WORK.CONSCTANS.ALL; entity COUNTER is port ( CLK : in std_logic; RESET : in std_logic; UP : in std_logic; CNT_OUT : out std_logic_vector (OUTPUT_WIDTH - 1 downto 0); TOP : out std_logic; BOTTOM : out std_logic ); end COUNTER; architecture COUNTER_BODY of COUNTER is signal COUNTER_VALUE : std_logic_vector (COUNTER_WIDTH - 1 downto 0); begin COUNT : process (CLK) begin if CLK = '1' and CLK'event then if RESET = '1' then COUNTER_VALUE <= conv_std_logic_vector (0, COUNTER_WIDTH); elsif UP = '1' then COUNTER_VALUE <= COUNTER_VALUE + 1; else COUNTER_VALUE <= COUNTER_VALUE - 1; end if; end if; end process; ASSIGN : process (COUNTER_VALUE) begin CNT_OUT <= COUNTER_VALUE (COUNTER_WIDTH - 1 downto COUNTER_WIDTH - OUTPUT_WIDTH); end process; -- kombinacni logika, ktera nastavuje TOP TOP_PROC : process(COUNTER_VALUE) variable auxTOP : std_logic; begin auxTOP := '1'; for I in 0 to COUNTER_WIDTH-1 loop auxTOP := auxTOP and COUNTER_VALUE(I); end loop; TOP <= auxTOP after 10 ns; end process TOP_PROC; -- kombinacni logika, ktera nastavuje BOTTOM BOTTOM_PROC : process(COUNTER_VALUE) variable auxBOTTOM : std_logic; begin auxBOTTOM := '0'; for I in 0 to COUNTER_WIDTH-1 loop auxBOTTOM := auxBOTTOM or COUNTER_VALUE(I); end loop; BOTTOM <= not auxBOTTOM after 10 ns; end process BOTTOM_PROC; end COUNTER_BODY;
mit
6fa2d77038c04a5d86f2e7501dfc067f
0.648936
3.202405
false
false
false
false
FlatTargetInk/Spartan-HW
uart_transmit.vhd
1
3,920
---------------------------------------------------------------------- -- File Downloaded from http://www.nandland.com ---------------------------------------------------------------------- -- This file contains the UART Transmitter. This transmitter is able -- to transmit 8 bits of serial data, one start bit, one stop bit, -- and no parity bit. When transmit is complete o_TX_Done will be -- driven high for one clock cycle. -- -- Set Generic g_CLKS_PER_BIT as follows: -- g_CLKS_PER_BIT = (Frequency of i_Clk)/(Frequency of UART) -- Example: 10 MHz Clock, 115200 baud UART -- (10000000)/(115200) = 87 -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity UART_TX is generic ( g_CLKS_PER_BIT : integer := 5208 -- Needs to be set correctly ); port ( i_Clk : in std_logic; i_TX_DV : in std_logic; i_TX_Byte : in std_logic_vector(7 downto 0); o_TX_Active : out std_logic; o_TX_Serial : out std_logic; o_TX_Done : out std_logic ); end UART_TX; architecture RTL of UART_TX is type t_SM_Main is (s_Idle, s_TX_Start_Bit, s_TX_Data_Bits, s_TX_Stop_Bit, s_Cleanup); signal r_SM_Main : t_SM_Main := s_Idle; signal r_Clk_Count : integer range 0 to g_CLKS_PER_BIT-1 := 0; signal r_Bit_Index : integer range 0 to 7 := 0; -- 8 Bits Total signal r_TX_Data : std_logic_vector(7 downto 0) := (others => '0'); signal r_TX_Done : std_logic := '0'; begin p_UART_TX : process (i_Clk) begin if rising_edge(i_Clk) then case r_SM_Main is when s_Idle => o_TX_Active <= '0'; o_TX_Serial <= '1'; -- Drive Line High for Idle r_TX_Done <= '0'; r_Clk_Count <= 0; r_Bit_Index <= 0; if i_TX_DV = '1' then r_TX_Data <= i_TX_Byte; r_SM_Main <= s_TX_Start_Bit; else r_SM_Main <= s_Idle; end if; -- Send out Start Bit. Start bit = 0 when s_TX_Start_Bit => o_TX_Active <= '1'; o_TX_Serial <= '0'; -- Wait g_CLKS_PER_BIT-1 clock cycles for start bit to finish if r_Clk_Count < g_CLKS_PER_BIT-1 then r_Clk_Count <= r_Clk_Count + 1; r_SM_Main <= s_TX_Start_Bit; else r_Clk_Count <= 0; r_SM_Main <= s_TX_Data_Bits; end if; -- Wait g_CLKS_PER_BIT-1 clock cycles for data bits to finish when s_TX_Data_Bits => o_TX_Serial <= r_TX_Data(r_Bit_Index); if r_Clk_Count < g_CLKS_PER_BIT-1 then r_Clk_Count <= r_Clk_Count + 1; r_SM_Main <= s_TX_Data_Bits; else r_Clk_Count <= 0; -- Check if we have sent out all bits if r_Bit_Index < 7 then r_Bit_Index <= r_Bit_Index + 1; r_SM_Main <= s_TX_Data_Bits; else r_Bit_Index <= 0; r_SM_Main <= s_TX_Stop_Bit; end if; end if; -- Send out Stop bit. Stop bit = 1 when s_TX_Stop_Bit => o_TX_Serial <= '1'; -- Wait g_CLKS_PER_BIT-1 clock cycles for Stop bit to finish if r_Clk_Count < g_CLKS_PER_BIT-1 then r_Clk_Count <= r_Clk_Count + 1; r_SM_Main <= s_TX_Stop_Bit; else r_TX_Done <= '1'; r_Clk_Count <= 0; r_SM_Main <= s_Cleanup; end if; -- Stay here 1 clock when s_Cleanup => o_TX_Active <= '0'; r_TX_Done <= '1'; r_SM_Main <= s_Idle; when others => r_SM_Main <= s_Idle; end case; end if; end process p_UART_TX; o_TX_Done <= r_TX_Done; end RTL;
mit
206e9d2058022ed63d8420ca5dd99773
0.472959
3.350427
false
false
false
false
AndyMcC0/UVVM_All
bitvis_uart/tb/uart_vvc_th.vhd
2
4,644
--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <[email protected]>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library uvvm_vvc_framework; use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all; library bitvis_vip_sbi; library bitvis_vip_uart; library bitvis_uart; -- Test harness entity entity uart_vvc_th is end entity; -- Test harness architecture architecture struct of uart_vvc_th is -- DSP interface and general control signals signal clk : std_logic := '0'; signal arst : std_logic := '0'; -- SBI VVC signals signal cs : std_logic; signal addr : unsigned(2 downto 0); signal wr : std_logic; signal rd : std_logic; signal wdata : std_logic_vector(7 downto 0); signal rdata : std_logic_vector(7 downto 0); signal ready : std_logic; -- UART VVC signals signal uart_vvc_rx : std_logic := '1'; signal uart_vvc_tx : std_logic := '1'; constant C_CLK_PERIOD : time := 10 ns; -- 100 MHz begin ----------------------------------------------------------------------------- -- Instantiate the concurrent procedure that initializes UVVM ----------------------------------------------------------------------------- i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine; ----------------------------------------------------------------------------- -- Instantiate DUT ----------------------------------------------------------------------------- i_uart: entity work.uart port map ( -- DSP interface and general control signals clk => clk, arst => arst, -- CPU interface cs => cs, addr => addr, wr => wr, rd => rd, wdata => wdata, rdata => rdata, -- UART signals rx_a => uart_vvc_tx, tx => uart_vvc_rx ); ----------------------------------------------------------------------------- -- SBI VVC ----------------------------------------------------------------------------- i1_sbi_vvc: entity bitvis_vip_sbi.sbi_vvc generic map( GC_ADDR_WIDTH => 3, GC_DATA_WIDTH => 8, GC_INSTANCE_IDX => 1 ) port map( clk => clk, sbi_vvc_master_if.cs => cs, sbi_vvc_master_if.rena => rd, sbi_vvc_master_if.wena => wr, sbi_vvc_master_if.addr => addr, sbi_vvc_master_if.wdata => wdata, sbi_vvc_master_if.ready => ready, sbi_vvc_master_if.rdata => rdata ); ----------------------------------------------------------------------------- -- UART VVC ----------------------------------------------------------------------------- i1_uart_vvc: entity bitvis_vip_uart.uart_vvc generic map( GC_DATA_WIDTH => 8, GC_INSTANCE_IDX => 1 ) port map( uart_vvc_rx => uart_vvc_rx, uart_vvc_tx => uart_vvc_tx ); -- Static '1' ready signal for the SBI VVC ready <= '1'; -- Toggle the reset after 5 clock periods p_arst: arst <= '1', '0' after 5 *C_CLK_PERIOD; ----------------------------------------------------------------------------- -- Clock process ----------------------------------------------------------------------------- p_clk: process begin clk <= '0', '1' after C_CLK_PERIOD / 2; wait for C_CLK_PERIOD; end process; end struct;
mit
f55af1bcf0681db651cf8672836d6ece
0.436262
4.807453
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/FIFO_one_hot_credit_based_packet_drop_classifier_support_with_checkers/FIFO_one_hot_credit_based_packet_drop_classifier_support_checkers.vhd
3
54,498
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity FIFO_credit_based_control_part_checkers is port ( valid_in: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; read_pointer: in std_logic_vector(3 downto 0); read_pointer_in: in std_logic_vector(3 downto 0); write_pointer: in std_logic_vector(3 downto 0); write_pointer_in: in std_logic_vector(3 downto 0); credit_out: in std_logic; empty_out: in std_logic; full_out: in std_logic; read_en_out: in std_logic; write_en_out: in std_logic; fake_credit: in std_logic; fake_credit_counter: in std_logic_vector(1 downto 0); fake_credit_counter_in: in std_logic_vector(1 downto 0); state_out: in std_logic_vector(4 downto 0); state_in: in std_logic_vector(4 downto 0); fault_info: in std_logic; health_info: in std_logic; faulty_packet_out: in std_logic; faulty_packet_in: in std_logic; flit_type: in std_logic_vector(2 downto 0); fault_out: in std_logic; write_fake_flit: in std_logic; -- Functional checkers err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot, err_read_pointer_in_onehot, err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full, err_read_pointer_increment, err_read_pointer_not_increment, err_write_en, err_not_write_en, err_not_write_en1, err_not_write_en2, err_read_en_mismatch, err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info, err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info, err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info, err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_fault_info, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change : out std_logic ); end FIFO_credit_based_control_part_checkers; architecture behavior of FIFO_credit_based_control_part_checkers is CONSTANT Idle: std_logic_vector (4 downto 0) := "00001"; CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010"; CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100"; CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000"; CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000"; begin --------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------- -- Functional Checkers (Might cover or be covered by some of the structural checkers) ------------------- --------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------- -- Empty and full cannot be high at the same time! process (empty_out, full_out) begin if (empty_out = '1' and full_out = '1') then err_empty_full <= '1'; else err_empty_full <= '0'; end if; end process; -- Reading from an empty FIFO is not possible! process (empty_out, read_en_out) begin if (empty_out = '1' and read_en_out = '1') then err_empty_read_en <= '1'; else err_empty_read_en <= '0'; end if; end process; -- Writing to a full FIFO is not possible! process (full_out, write_en_out) begin if (full_out = '1' and write_en_out = '1') then err_full_write_en <= '1'; else err_full_write_en <= '0'; end if; end process; -- The states of the packet dropping FSM of FIFO must always be one-hot (state_in)! process (state_in) begin if (state_in /= Idle and state_in /= Header_flit and state_in /= Body_flit and state_in /= Tail_flit and state_in /= Packet_drop) then err_state_in_onehot <= '1'; else err_state_in_onehot <= '0'; end if; end process; -- Read pointer must always be one-hot! process (read_pointer_in) begin if (read_pointer_in /= "0001" and read_pointer_in /= "0010" and read_pointer_in /= "0100" and read_pointer_in /= "1000") then err_read_pointer_in_onehot <= '1'; else err_read_pointer_in_onehot <= '0'; end if; end process; -- Write pointer must always be one-hot! process (write_pointer_in) begin if (write_pointer_in /= "0001" and write_pointer_in /= "0010" and write_pointer_in /= "0100" and write_pointer_in /= "1000") then err_write_pointer_in_onehot <= '1'; else err_write_pointer_in_onehot <= '0'; end if; end process; --------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------- -- Structural Checkers ---------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------- -- Write pointer and Read pointer checkers process (write_en_out, write_pointer_in, write_pointer) begin if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then err_write_en_write_pointer <= '1'; else err_write_en_write_pointer <= '0'; end if; end process; -- Checked ! process (write_en_out, write_pointer_in, write_pointer) begin if (write_en_out = '0' and write_pointer_in /= write_pointer ) then err_not_write_en_write_pointer <= '1'; else err_not_write_en_write_pointer <= '0'; end if; end process; -- Checked ! process (read_pointer, write_pointer, empty_out) begin if (read_pointer = write_pointer and empty_out = '0' ) then err_read_pointer_write_pointer_not_empty <= '1'; else err_read_pointer_write_pointer_not_empty <= '0'; end if; end process; -- Checked ! process (read_pointer, write_pointer, empty_out) begin if (read_pointer /= write_pointer and empty_out = '1' ) then err_read_pointer_write_pointer_empty <= '1'; else err_read_pointer_write_pointer_empty <= '0'; end if; end process; -- Checked ! process (write_pointer, read_pointer, full_out) begin if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then err_read_pointer_write_pointer_not_full <= '1'; else err_read_pointer_write_pointer_not_full <= '0'; end if; end process; -- Checked ! process (write_pointer, read_pointer, full_out) begin if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then err_read_pointer_write_pointer_full <= '1'; else err_read_pointer_write_pointer_full <= '0'; end if; end process; -- Checked ! process (read_en_out, empty_out, read_pointer_in, read_pointer) begin if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then err_read_pointer_increment <= '1'; else err_read_pointer_increment <= '0'; end if; end process; -- Checked ! process (read_en_out, empty_out, read_pointer_in, read_pointer) begin if ( (read_en_out = '0' or empty_out = '1') and read_pointer_in /= read_pointer ) then err_read_pointer_not_increment <= '1'; else err_read_pointer_not_increment <= '0'; end if; end process; -- Checked ! process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out) begin if (valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out ='0' and write_en_out = '0') then err_write_en <= '1'; else err_write_en <= '0'; end if; end process; -- Updated ! process (valid_in, write_en_out) begin if (valid_in = '0' and write_en_out = '1') then err_not_write_en <= '1'; else err_not_write_en <= '0'; end if; end process; process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out) begin if ( valid_in = '1' and ((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0') and write_en_out = '1') then err_not_write_en1 <= '1'; else err_not_write_en1 <= '0'; end if; end process; process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out) begin if ( valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out = '1' and write_en_out = '1') then err_not_write_en2 <= '1'; else err_not_write_en2 <= '0'; end if; end process; -- Updated ! process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out) begin if ( (read_en_N = '1' or read_en_E = '1' or read_en_W = '1' or read_en_S = '1' or read_en_L = '1') and empty_out = '0' and read_en_out = '0' ) then err_read_en_mismatch <= '1'; else err_read_en_mismatch <= '0'; end if; end process; process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out) begin if ( ((read_en_N = '0' and read_en_E = '0' and read_en_W = '0' and read_en_S = '0' and read_en_L = '0') or empty_out = '1') and read_en_out = '1' ) then err_read_en_mismatch1 <= '1'; else err_read_en_mismatch1 <= '0'; end if; end process; -- Newly added checkers for FIFO with packet drop and fault classifier support! process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter) begin if (fake_credit = '1' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter + 1) then err_fake_credit_read_en_fake_credit_counter_in_increment <= '1'; else err_fake_credit_read_en_fake_credit_counter_in_increment <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in) begin if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and fake_credit_counter_in /= fake_credit_counter - 1 ) then err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '1'; else err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter) begin if (fake_credit = '0' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter) then err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '1'; else err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter) begin if (fake_credit = '1' and read_en_out = '0' and fake_credit_counter_in /= fake_credit_counter) then err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '1'; else err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in) begin if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter = 0 and fake_credit_counter_in /= fake_credit_counter) then err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '1'; else err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '0'; end if; end process; process (fake_credit, read_en_out, credit_out) begin if ((fake_credit = '1' or read_en_out ='1') and credit_out = '0') then err_fake_credit_read_en_credit_out <= '1'; else err_fake_credit_read_en_credit_out <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter, credit_out) begin if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and credit_out = '0') then err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '1'; else err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter, credit_out) begin if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter = 0 and credit_out = '1') then err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '1'; else err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '0'; end if; end process; --process (fake_credit, read_en_out, credit_out) --begin -- if (fake_credit = '1' and read_en_out = '1' and credit_out = '1') then -- err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out <= '1'; -- else -- err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out <= '0'; -- end if; --end process; -- Checkers for Packet Dropping FSM of FIFO --process (valid_in, state_out, state_in) --begin -- if (valid_in = '0' and (state_out = Idle or state_out = Header_flit or state_out = Body_flit or state_out = Packet_drop) and state_in /= state_out) then -- err_valid_in_state_out_state_in_not_change <= '1'; -- else -- err_valid_in_state_out_state_in_not_change <= '0'; -- end if; --end process; -- Idle state -- fault_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, fault_out, valid_in, state_in) begin if (state_out = Idle and fault_out = '0' and valid_in = '1' and state_in /= Header_flit) then err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '1'; else err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '0'; end if; end process; process (state_out, fault_out, valid_in, state_in, state_out) begin if (state_out = Idle and fault_out = '0' and valid_in = '0' and state_in /= state_out) then err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '1'; else err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '0'; end if; end process; process (state_out, fault_out, fake_credit) begin if (state_out = Idle and fault_out = '0' and fake_credit = '1') then err_state_out_Idle_not_fault_out_not_fake_credit <= '1'; else err_state_out_Idle_not_fault_out_not_fake_credit <= '0'; end if; end process; process (state_out, fault_out, fault_info) begin if (state_out = Idle and fault_out = '0' and fault_info = '1') then err_state_out_Idle_not_fault_out_not_fault_info <= '1'; else err_state_out_Idle_not_fault_out_not_fault_info <= '0'; end if; end process; process (state_out, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Idle and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '1'; else err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '0'; end if; end process; -- fault_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, fault_out, fake_credit) begin if (state_out = Idle and fault_out = '1' and fake_credit = '0') then err_state_out_Idle_fault_out_fake_credit <= '1'; else err_state_out_Idle_fault_out_fake_credit <= '0'; end if; end process; process (state_out, fault_out, state_in) begin if (state_out = Idle and fault_out = '1' and state_in /= Packet_drop) then err_state_out_Idle_fault_out_state_in_Packet_drop <= '1'; else err_state_out_Idle_fault_out_state_in_Packet_drop <= '0'; end if; end process; process (state_out, fault_out, fault_info) begin if (state_out = Idle and fault_out = '1' and fault_info = '0') then err_state_out_Idle_fault_out_fault_info <= '1'; else err_state_out_Idle_fault_out_fault_info <= '0'; end if; end process; process (state_out, fault_out, faulty_packet_in) begin if (state_out = Idle and fault_out = '1' and faulty_packet_in /= '1') then err_state_out_Idle_fault_out_faulty_packet_in <= '1'; else err_state_out_Idle_fault_out_faulty_packet_in <= '0'; end if; end process; process (state_out, write_fake_flit) begin if (state_out = Idle and write_fake_flit = '1') then err_state_out_Idle_not_write_fake_flit <= '1'; else err_state_out_Idle_not_write_fake_flit <= '0'; end if; end process; -- Other properties for Idle state -------------------------------------------------------------------------------------------------- process (state_out, health_info) begin if ( (state_out = Idle or state_out = Header_flit or state_out = Tail_flit or state_out = Packet_drop) and health_info = '1') then err_state_out_Idle_not_health_info <= '1'; else err_state_out_Idle_not_health_info <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------- -- Header_flit state -- fault_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, flit_type, state_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= Body_flit) then err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, state_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '0'; end if; end process; --process (state_out, valid_in, fault_out, flit_type, state_in, state_out) --begin -- if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type /= "010" and flit_type /= "100" and state_in /= state_out) then -- err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1'; -- else -- err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0'; -- end if; --end process; process (state_out, valid_in, fault_out, write_fake_flit) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; -- fault_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, write_fake_flit) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '1'; else err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, state_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '1'; else err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then err_state_out_Header_flit_valid_in_fault_out_fault_info <= '1'; else err_state_out_Header_flit_valid_in_fault_out_fault_info <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '1'; else err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '0'; end if; end process; process (state_out, valid_in, state_in, state_out) begin if (state_out = Header_flit and valid_in = '0' and state_in /= state_out) then err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '1'; else err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, valid_in, faulty_packet_in, faulty_packet_out) begin if (state_out = Header_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; process (state_out, valid_in, fault_info) begin if (state_out = Header_flit and valid_in = '0' and fault_info = '1') then err_state_out_Header_flit_not_valid_in_not_fault_info <= '1'; else err_state_out_Header_flit_not_valid_in_not_fault_info <= '0'; end if; end process; process (state_out, valid_in, write_fake_flit) begin if (state_out = Header_flit and valid_in = '0' and write_fake_flit = '1') then err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '1'; else err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '0'; end if; end process; process (state_out, fake_credit) begin if ( (state_out = Header_flit or state_out = Body_flit) and fake_credit /= '0') then err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '1'; else err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------- -- Body_flit state -- fault_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, flit_type, state_in, state_out) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= state_out) then err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, state_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, health_info) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and health_info = '0') then err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, health_info) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "100" and health_info = '1') then err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '0'; end if; end process; process (state_out, valid_in, fault_out, health_info) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and health_info = '1') then err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '1'; else err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '0'; end if; end process; process (state_out, valid_in, health_info) begin if (state_out = Body_flit and valid_in = '0' and health_info = '1') then err_state_out_Body_flit_valid_in_not_health_info <= '1'; else err_state_out_Body_flit_valid_in_not_health_info <= '0'; end if; end process; --process (state_out, valid_in, fault_out, flit_type, state_in, state_out) --begin -- if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "010" and flit_type /= "100" and state_in /= state_out) then -- err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1'; -- else -- err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0'; -- end if; --end process; process (state_out, valid_in, fault_out, write_fake_flit) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then err_state_out_Body_flit_valid_in_not_fault_out_fault_info <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_fault_info <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; -- fault_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, write_fake_flit) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '1'; else err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, state_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '1'; else err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then err_state_out_Body_flit_valid_in_fault_out_fault_info <= '1'; else err_state_out_Body_flit_valid_in_fault_out_fault_info <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '1'; else err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '0'; end if; end process; process (state_out, valid_in, state_in) begin if (state_out = Body_flit and valid_in = '0' and state_in /= state_out) then err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '1'; else err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, valid_in, faulty_packet_in, faulty_packet_out) begin if (state_out = Body_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; process (state_out, valid_in, fault_info) begin if (state_out = Body_flit and valid_in = '0' and fault_info = '1') then err_state_out_Body_flit_not_valid_in_not_fault_info <= '1'; else err_state_out_Body_flit_not_valid_in_not_fault_info <= '0'; end if; end process; process (state_out, fake_credit) begin if (state_out = Body_flit and fake_credit = '1') then err_state_out_Body_flit_not_fake_credit <= '1'; else err_state_out_Body_flit_not_fake_credit <= '0'; end if; end process; process (state_out, valid_in, write_fake_flit) begin if (state_out = Body_flit and valid_in = '0' and write_fake_flit = '1') then err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '1'; else err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------- -- Tail_flit state -- fault_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, flit_type, state_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type = "001" and state_in /= Header_flit) then err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '0'; end if; end process; --process (state_out, valid_in, fault_out, flit_type, state_in, state_out) --begin -- if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type /= "001" and state_in /= state_out) then -- err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1'; -- else -- err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0'; -- end if; --end process; process (state_out, valid_in, fault_out, fake_credit) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fake_credit = '1') then err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; -- fault_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, fake_credit) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fake_credit /= '1') then err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '1'; else err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '0'; end if; end process; process (state_out, valid_in, fault_out, state_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '1'; else err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then err_state_out_Tail_flit_valid_in_fault_out_fault_info <= '1'; else err_state_out_Tail_flit_valid_in_fault_out_fault_info <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '1'; else err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '0'; end if; end process; process (state_out, valid_in, state_in) begin if (state_out = Tail_flit and valid_in = '0' and state_in /= Idle) then err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '1'; else err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '0'; end if; end process; process (state_out, valid_in, faulty_packet_in, faulty_packet_out) begin if (state_out = Tail_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '1'; else err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '0'; end if; end process; process (state_out, valid_in, fault_info) begin if (state_out = Tail_flit and valid_in = '0' and fault_info = '1') then err_state_out_Tail_flit_not_valid_in_not_fault_info <= '1'; else err_state_out_Tail_flit_not_valid_in_not_fault_info <= '0'; end if; end process; process (state_out, valid_in, fake_credit) begin if (state_out = Tail_flit and valid_in = '0' and fake_credit /= '0') then err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '1'; else err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '0'; end if; end process; process (state_out, write_fake_flit) begin if (state_out = Tail_flit and write_fake_flit = '1') then err_state_out_Tail_flit_not_write_fake_flit <= '1'; else err_state_out_Tail_flit_not_write_fake_flit <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------- -- Packet_drop state -- faulty_packet_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and fake_credit /= '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and faulty_packet_in /= '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and state_in /= Header_flit) then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and write_fake_flit = '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '1' and state_in /= state_out) then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and faulty_packet_in /= '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '1' and state_in /= state_out) then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and state_in /= Idle) then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and fake_credit = '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and fake_credit = '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and ( valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1' ) and faulty_packet_in /= faulty_packet_out) then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, faulty_packet_in, faulty_packet_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and state_in /= state_out) then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, write_fake_flit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and write_fake_flit = '1') then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and fake_credit = '1') then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '0'; end if; end process; -- faulty_packet_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, faulty_packet_out, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '0' and state_in /= state_out) then err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Packet_drop and faulty_packet_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; process (state_out, fault_info) begin if (state_out = Packet_drop and fault_info = '1') then err_state_out_Packet_drop_not_fault_info <= '1'; else err_state_out_Packet_drop_not_fault_info <= '0'; end if; end process; process (state_out, faulty_packet_out, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '0' and fake_credit = '1') then err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '1'; else err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001" or fault_out = '1') and write_fake_flit = '1') then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '0'; end if; end process; process (state_out, faulty_packet_out, write_fake_flit) begin if (state_out = Packet_drop and faulty_packet_out = '0' and write_fake_flit = '1') then err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '1'; else err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '0'; end if; end process; --process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out) --begin -- if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then -- err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change <= '1'; -- else -- err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change <= '0'; -- end if; --end process; -- Invalid state --process (state_out, state_in) --begin -- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and state_in /= state_out) then -- err_state_out_invalid_state_in_state_out_not_change <= '1'; -- else -- err_state_out_invalid_state_in_state_out_not_change <= '0'; -- end if; --end process; --process (state_out, fault_info) --begin -- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and fault_info = '1') then -- err_state_out_invalid_not_fault_info <= '1'; -- else -- err_state_out_invalid_not_fault_info <= '0'; -- end if; --end process; --process (state_out, health_info) --begin -- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and health_info = '1') then -- err_state_out_invalid_not_health_info <= '1'; -- else -- err_state_out_invalid_not_health_info <= '0'; -- end if; --end process; --process (state_out, fake_credit) --begin -- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and fake_credit = '1') then -- err_state_out_invalid_not_fake_credit <= '1'; -- else -- err_state_out_invalid_not_fake_credit <= '0'; -- end if; --end process; --process (state_out, write_fake_flit) --begin -- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and write_fake_flit = '1') then -- err_state_out_invalid_not_write_fake_flit <= '1'; -- else -- err_state_out_invalid_not_write_fake_flit <= '0'; -- end if; --end process; --process (state_out, faulty_packet_in, faulty_packet_out) --begin -- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and faulty_packet_in /= faulty_packet_out) then -- err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change <= '1'; -- else -- err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change <= '0'; -- end if; --end process; end behavior;
gpl-3.0
361773a7b1ce9856e49631f07aea0f62
0.655345
2.754093
false
false
false
false
AndyMcC0/UVVM_All
bitvis_uart/src/uart_core.vhd
1
13,866
--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <[email protected]>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- Description : This is NOT an example of how to implement a UART core. This is just -- a simple test vehicle that can be used to demonstrate the functionality -- of the UVVM VVC Framework. -- -- See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.uart_pif_pkg.all; use work.uart_pkg.all; entity uart_core is generic ( GC_START_BIT : std_logic := '0'; GC_STOP_BIT : std_logic := '1'; GC_CLOCKS_PER_BIT : integer := 16); port( -- DSP interface and general control signals clk : in std_logic; arst : in std_logic; -- PIF-core interface p2c : in t_p2c; c2p : out t_c2p; -- Interrupt related signals rx_a : in std_logic; tx : out std_logic ); end entity uart_core; architecture rtl of uart_core is type t_slv_array is array (3 downto 0) of std_logic_vector(7 downto 0); -- tx signals signal tx_data : t_slv_array:= (others => (others => '0')); signal tx_buffer : std_logic_vector(7 downto 0) := (others => '0'); signal tx_data_valid : std_logic := '0'; signal tx_ready : std_logic := '0'; signal tx_active : std_logic := '0'; signal tx_clk_counter : unsigned(f_log2(GC_CLOCKS_PER_BIT)-1 downto 0) := (others => '0'); -- count through the bits (12 total) signal tx_bit_counter : unsigned(3 downto 0) := (others => '0'); -- receive signals signal rx_buffer : std_logic_vector(7 downto 0) := (others => '0'); signal rx_active : std_logic := '0'; signal rx_clk_counter : unsigned(f_log2(GC_CLOCKS_PER_BIT)-1 downto 0) := (others => '0'); -- count through the bits (12 total) signal rx_bit_counter : unsigned(3 downto 0) := (others => '0'); signal rx_bit_samples : std_logic_vector(GC_CLOCKS_PER_BIT-1 downto 0) := (others => '0'); signal rx_data : t_slv_array := (others => (others => '0')); signal rx_data_valid : std_logic := '0'; signal rx_data_full : std_logic := '0'; -- rx synced to clk signal rx_s : std_logic_vector(1 downto 0) := (others => '1'); -- synchronized serial data input signal rx_just_active : boolean; -- helper signal when we start receiving signal parity_err : std_logic := '0'; -- parity error detected signal stop_err : std_logic := '0'; -- stop error detected signal transient_err : std_logic := '0'; -- data value is transient signal c2p_i : t_c2p; -- Internal version of output begin c2p <= c2p_i; c2p_i.aro_tx_ready <= tx_ready; c2p_i.aro_rx_data_valid <= rx_data_valid; -- synchronize rx input (async) p_rx_s : process(clk, arst) is begin if arst = '1' then rx_s <= (others => '1'); elsif rising_edge(clk) then rx_s <= rx_s(0) & rx_a; end if; end process p_rx_s; --------------------------------------------------------------------------- -- Transmit process; drives tx serial output. -- -- Stores 4 pending bytes in the tx_data array, and the byte currently -- being output in the tx_buffer register. -- -- Tx_buffer is filled with data from tx_data(0) if there is valid data -- available (tx_data_valid is active), and no other byte is currently -- being output (tx_active is inactive). -- -- Data received via SBI is inserted in tx_data at the index pointed to -- by vr_tx_data_idx. vr_tx_data_idx is incremented when a new byte is -- received via SBI, and decremented when a new byte is loaded into -- tx_buffer. --------------------------------------------------------------------------- uart_tx : process (clk, arst) is variable vr_tx_data_idx : unsigned(2 downto 0) := (others => '0'); begin -- process uart_tx if arst = '1' then -- asynchronous reset (active high) tx_data <= (others => (others => '0')); tx_buffer <= (others => '0'); tx_data_valid <= '0'; tx_ready <= '1'; tx_active <= '0'; tx_bit_counter <= (others => '0'); tx_clk_counter <= (others => '0'); tx <= '1'; vr_tx_data_idx := (others => '0'); elsif rising_edge(clk) then -- rising clock edge -- There is valid data in tx_data. -- Load the tx_buffer and activate TX operation. -- Decrement vr_tx_data_idx. if tx_data_valid = '1' and tx_active = '0' then tx_active <= '1'; tx_buffer <= tx_data(0); tx_data <= x"00" & tx_data(3 downto 1); if vr_tx_data_idx > 0 then -- Decrement idx if vr_tx_data_idx < 3 then vr_tx_data_idx := vr_tx_data_idx - 1; else -- vr_tx_data_idx = 3 -- Special case for idx=3 (max). -- When tx_data is full (tx_ready = '0'), we do not wish to -- decrement the idx. The reason is that the idx points -- to where the next incoming data byte shall be stored, -- which is still idx 3. -- Therefore, only decrement when tx_ready = '1'. if tx_ready = '1' then vr_tx_data_idx := vr_tx_data_idx - 1; end if; end if; else -- vr_tx_data_idx already at 0, -- which means that the final byte in tx_data -- was just loaded into tx_buffer, no more valid -- data left in tx_data. tx_data_valid <= '0'; tx_active <= '0'; end if; -- Tx is now ready to receive another byte. tx_ready <= '1'; end if; -- loading the tx_data shift reg if tx_ready = '1' then if p2c.awo_tx_data_we = '1' then tx_data(to_integer(vr_tx_data_idx)) <= p2c.awo_tx_data; tx_data_valid <= '1'; -- Increment idx if tx_data not full. if vr_tx_data_idx < 3 then vr_tx_data_idx := vr_tx_data_idx + 1; else -- tx_data full tx_ready <= '0'; end if; end if; end if; if tx_active = '0' then -- default tx_clk_counter <= (others => '0'); tx_bit_counter <= (others => '0'); tx <= '1'; -- idle as default else -- tx clock counter keeps running when active if tx_clk_counter <= GC_CLOCKS_PER_BIT - 1 then tx_clk_counter <= tx_clk_counter + 1; else tx_clk_counter <= (others => '0'); end if; -- GC_CLOCKS_PER_BIT tx clocks per tx bit if tx_clk_counter >= GC_CLOCKS_PER_BIT - 1 then tx_bit_counter <= tx_bit_counter + 1; end if; case to_integer(tx_bit_counter) is when 0 => tx <= GC_START_BIT; when 1 to 8 => -- mux out the correct tx bit tx <= tx_buffer(to_integer(tx_bit_counter)-1); when 9 => tx <= odd_parity(tx_buffer); when 10 => tx <= GC_STOP_BIT; when others => tx <= '1'; tx_active <= '0'; end case; end if; end if; end process uart_tx; -- Data is set on the output when available on rx_data(0) c2p_i.aro_rx_data <= rx_data(0); --------------------------------------------------------------------------- -- Receive process --------------------------------------------------------------------------- uart_rx : process (clk, arst) is variable vr_rx_data_idx : unsigned(2 downto 0) := (others => '0'); begin -- process uart_tx if arst = '1' then -- asynchronous reset (active high) rx_active <= '0'; rx_just_active <= false; rx_data <= (others => (others => '0')); rx_data_valid <= '0'; rx_bit_samples <= (others => '1'); rx_buffer <= (others => '0'); rx_clk_counter <= (others => '0'); rx_bit_counter <= (others => '0'); stop_err <= '0'; parity_err <= '0'; transient_err <= '0'; vr_rx_data_idx := (others => '0'); rx_data_full <= '1'; elsif rising_edge(clk) then -- rising clock edge -- Perform read. -- When there is data available in rx_data, -- output the data when read enable detected. if p2c.aro_rx_data_re = '1' and rx_data_valid = '1' then rx_data <= x"00" & rx_data(3 downto 1); rx_data_full <= '0'; if vr_rx_data_idx > 0 then vr_rx_data_idx := vr_rx_data_idx - 1; if vr_rx_data_idx = 0 then -- rx_data empty rx_data_valid <= '0'; end if; end if; end if; -- always shift in new synchronized serial data rx_bit_samples <= rx_bit_samples(GC_CLOCKS_PER_BIT-2 downto 0) & rx_s(1); -- look for enough GC_START_BITs in rx_bit_samples vector if rx_active = '0' and (find_num_hits(rx_bit_samples, GC_START_BIT) >= GC_CLOCKS_PER_BIT-1) then rx_active <= '1'; rx_just_active <= true; end if; if rx_active = '0' then -- defaults stop_err <= '0'; parity_err <= '0'; transient_err <= '0'; rx_clk_counter <= (others => '0'); rx_bit_counter <= (others => '0'); else -- We could check when we first enter whether we find the full number -- of start samples and adjust the time we start rx_clk_counter by a -- clock cycle - to hit the eye of the rx data best possible. if rx_just_active then if find_num_hits(rx_bit_samples, GC_START_BIT) = GC_CLOCKS_PER_BIT then -- reset rx_clk_counter rx_clk_counter <= (others => '0'); end if; rx_just_active <= false; else -- loop clk counter if rx_clk_counter <= GC_CLOCKS_PER_BIT - 1 then rx_clk_counter <= rx_clk_counter + 1; else rx_clk_counter <= (others => '0'); end if; end if; -- shift in data, check for consistency and forward if rx_clk_counter >= GC_CLOCKS_PER_BIT - 1 then rx_bit_counter <= rx_bit_counter + 1; if transient_error(rx_bit_samples, GC_CLOCKS_PER_BIT - 2) then transient_err <= '1'; end if; -- are we done? not counting the start bit if to_integer(rx_bit_counter) >= 9 then rx_active <= '0'; end if; case to_integer(rx_bit_counter) is when 0 to 7 => -- mux in new bit rx_buffer(to_integer(rx_bit_counter)) <= find_most_repeated_bit(rx_bit_samples); when 8 => -- check parity if (odd_parity(rx_buffer) /= find_most_repeated_bit(rx_bit_samples)) then parity_err <= '1'; end if; when 9 => -- check stop bit, and end byte receive if find_most_repeated_bit(rx_bit_samples) /= GC_STOP_BIT then stop_err <= '1'; end if; rx_data(to_integer(vr_rx_data_idx)) <= rx_buffer; rx_data_valid <= '1'; -- ready for higher level protocol if vr_rx_data_idx < 3 then vr_rx_data_idx := vr_rx_data_idx + 1; else rx_data_full <= '1'; end if; when others => rx_active <= '0'; end case; end if; end if; end if; end process uart_rx; p_busy_assert : process(clk) is begin if rising_edge(clk) then assert not (p2c.awo_tx_data_we = '1' and tx_ready = '0') report "Trying to transmit new UART data while transmitter is busy" severity error; end if; end process; assert stop_err /= '1' report "Stop bit error detected!" severity error; assert parity_err /= '1' report "Parity error detected!" severity error; assert transient_err /= '1' report "Transient error detected!" severity error; end architecture rtl;
mit
ffead0c1f25b18a2a0d5eb494d899c2b
0.488389
3.877517
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/Checkers/Control_Part_Checkers/LBDR_packet_drop_checkers/Rxy_Reconf/RTL/Rxy_Reconf_pseudo_with_checkers_top.vhd
3
5,452
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity Rxy_Reconf_pseudo_with_checkers_top is port ( Rxy_reconf: in std_logic_vector(7 downto 0); ReConf_FF_out: in std_logic; Rxy: in std_logic_vector(7 downto 0); Reconfig : in std_logic; flit_type: in std_logic_vector(2 downto 0); grants: in std_logic; empty: in std_logic; Rxy_in_out: out std_logic_vector(7 downto 0); ReConf_FF_in_out: out std_logic; -- Checker outputs err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal : out std_logic ); end Rxy_Reconf_pseudo_with_checkers_top; architecture behavior of Rxy_Reconf_pseudo_with_checkers_top is component Rxy_Reconf_pseudo is port ( Rxy_reconf: in std_logic_vector(7 downto 0); ReConf_FF_out: in std_logic; Rxy: in std_logic_vector(7 downto 0); Reconfig : in std_logic; flit_type: in std_logic_vector(2 downto 0); grants: in std_logic; empty: in std_logic; Rxy_in: out std_logic_vector(7 downto 0); ReConf_FF_in: out std_logic ); end component; component Rxy_Reconf_pseudo_checkers is port ( ReConf_FF_out: in std_logic; flit_type: in std_logic_vector(2 downto 0); empty: in std_logic; grants: in std_logic; Rxy_in: in std_logic_vector(7 downto 0); Rxy_reconf: in std_logic_vector(7 downto 0); ReConf_FF_in: in std_logic; Rxy: in std_logic_vector(7 downto 0); Reconfig : in std_logic; err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal : out std_logic ); end component; signal Rxy_in_sig: std_logic_vector (7 downto 0); signal ReConf_FF_in_sig: std_logic; begin Rxy_in_out <= Rxy_in_sig; ReConf_FF_in_out <= ReConf_FF_in_sig; -- Rxy Reconfiguration (pseudo-combinational) module instantiation Rxy_Reconf_pseudo0 : Rxy_Reconf_pseudo port map ( Rxy_reconf => Rxy_reconf, ReConf_FF_out => ReConf_FF_out, Rxy => Rxy, Reconfig => Reconfig, flit_type => flit_type, grants => grants, empty => empty, Rxy_in => Rxy_in_sig, ReConf_FF_in => ReConf_FF_in_sig ); CHECKERS : Rxy_Reconf_pseudo_checkers port map ( ReConf_FF_out => ReConf_FF_out, flit_type => flit_type, empty => empty, grants => grants, Rxy_in => Rxy_in_sig, Rxy_reconf => Rxy_reconf, ReConf_FF_in => ReConf_FF_in_sig, Rxy => Rxy, Reconfig => Reconfig, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal ); end;
gpl-3.0
8678779a399198499e4e5754c9038033
0.524028
3.734247
false
true
false
false
ashtonchase/logic_analyzer
src/msg_processor.vhd
1
7,195
------------------------------------------------------------------------------- -- Title : Message Processor -- Project : fpga_logic_analyzer ------------------------------------------------------------------------------- -- File : msg_processor.vhd -- Created : 2016-03-17 -- Last update: 2016-04-09 -- Standard : VHDL'08 ------------------------------------------------------------------------------- -- Description: The message processor waits for the UART module to provide -- commands and data from the SUMP software. When the command is ready, it is -- read, the ready flag is driven low, and the command is decoded. After the -- command is decoded, appropiate lines are set to control the sample rate, -- trigger mask, and sample counts. ------------------------------------------------------------------------------- -- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt ------------------------------------------------------------------------------- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-03-17 0.0 David Created -- 2016-03-31 0.1 David Entity done -- 2016-04-04 0.2 David State machine in progress -- 2016-04-05 1.0 David Complete -- 2016-04-07 1.1 David Handles unrecognized commands -- 2016-04-08 1.2 Ashton Changed READ_CMD check of cmd_in from -- invalid if statement to case statement. -- Beautified.. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity msg_processor is port( -- Global Signals clk : in std_logic; -- Clock rst : in std_logic; -- Synchronous reset -- UART Interface byte_in : in std_logic_vector(7 downto 0); -- Byte of command/data from UART byte_new : in std_logic; -- Strobe to indicate new byte -- Sample Rate Control Interface sample_f : out std_logic_vector(23 downto 0); -- Sampling frequency to Sample Rate Control -- Capture Control Interface reset : out std_logic; -- Reset capture control armed : out std_logic; -- Arm capture control send_ID : out std_logic; -- Send device ID send_debug : out std_logic; -- Send debug status read_cnt : out std_logic_vector(15 downto 0); -- Number of samples (divided by 4) to send to memory delay_cnt : out std_logic_vector(15 downto 0); -- Number of samples (divided by 4) to capture after trigger trig_msk : out std_logic_vector(31 downto 0); -- Define which trigger values must match trig_vals : out std_logic_vector(31 downto 0) -- Set the trigger's individual bit values ); -- port end entity msg_processor; architecture behave of msg_processor is signal cmd_in : std_logic_vector(7 downto 0) := (others => '0'); signal data_in : std_logic_vector(31 downto 0) := (others => '0'); type state_t is (INIT, READ_CMD, DO_CMD, BYTE1, BYTE2, BYTE3, BYTE4); signal state : state_t; begin process(clk) begin if rising_edge(clk) then reset <= '0'; armed <= '0'; send_ID <= '0'; send_debug <= '0'; if rst = '1' then read_cnt <= x"0000"; delay_cnt <= x"0000"; sample_f <= x"000000"; trig_msk <= x"00000000"; trig_vals <= x"00000000"; state <= INIT; else case state is when INIT => if byte_new = '1' then cmd_in <= byte_in; state <= READ_CMD; end if; when READ_CMD => case cmd_in is when x"C0" | x"C4" | x"C8" | x"CC" | -- Trig Mask x"C1" | x"C5" | x"C9" | x"CD" | -- Trig Vals x"C2" | x"C6" | x"CA" | x"CE" | -- Trig Config x"80" | x"81" | x"82" => state <= BYTE1; -- Recognized long command when others => state <= DO_CMD; -- Unrecognized command or short command end case; when BYTE1 => if byte_new = '1' then data_in(7 downto 0) <= byte_in; state <= BYTE2; end if; when BYTE2 => if byte_new = '1' then data_in(15 downto 8) <= byte_in; state <= BYTE3; end if; when BYTE3 => if byte_new = '1' then data_in(23 downto 16) <= byte_in; state <= BYTE4; end if; when BYTE4 => if byte_new = '1' then data_in(31 downto 24) <= byte_in; state <= DO_CMD; end if; when DO_CMD => case cmd_in is when x"00" => -- Reset reset <= '1'; when x"01" => -- Run armed <= '1'; when x"02" => -- Send ID send_ID <= '1'; when x"11" => -- XON (unimplemented) when x"13" => -- XOFF (unimplemented) -- when x"C0" | x"C4" | x"C8" | x"CC" => -- Set Trigger Mask when x"C0" => -- Set Trigger Mask trig_msk <= data_in; --when x"C1" | x"C5" | x"C9" | x"CD" => -- Set Trigger Values when x"C1" => -- Set Trigger Values trig_vals <= data_in; when x"C2" | x"C6" | x"CA" | x"CE" => -- Set Trigger Configuration (unimplemented) when x"80" => -- Set Divider sample_f <= data_in(23 downto 0); when x"81" => -- Set Read & Delay Count read_cnt <= data_in(15 downto 0); delay_cnt <= data_in(31 downto 16); when x"82" => -- Set Flags (unimplemented) when x"FF" => -- Debug send_debug <= '1'; when others => end case; state <= INIT; end case; end if; end if; end process; end architecture;
gpl-2.0
5afd646259fc730e161a0fd14af9970c
0.474496
4.195335
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/Arbiter_out_one_hot_with_checkers/Arbiter_out_one_hot_pseudo_checkers.vhd
3
21,948
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity Arbiter_out_one_hot_pseudo_checkers is port ( credit: in std_logic_vector(1 downto 0); req_X_E, req_X_N, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : in std_logic; -- Grants given to LBDR requests (encoded as one-hot) state_in: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM -- Checker outputs err_Requests_state_in_state_not_equal, err_IDLE_req_X_N, err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N, err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E, err_West_req_X_W, err_West_credit_not_zero_req_X_E_grant_E, err_West_credit_zero_or_not_req_X_W_not_grant_W, err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S, err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L, err_IDLE_req_X_E, err_North_req_X_E, err_East_req_X_W, err_West_req_X_S, err_South_req_X_L, err_Local_req_X_N, err_IDLE_req_X_W, err_North_req_X_W, err_East_req_X_S, err_West_req_X_L, err_South_req_X_N, err_Local_req_X_E, err_IDLE_req_X_S, err_North_req_X_S, err_East_req_X_L, err_West_req_X_N, err_South_req_X_E, err_Local_req_X_W, err_IDLE_req_X_L, err_North_req_X_L, err_East_req_X_N, err_West_req_X_E, err_South_req_X_W, err_Local_req_X_S, err_state_in_onehot, err_no_request_grants, err_request_IDLE_state, err_request_IDLE_not_Grants, err_state_North_Invalid_Grant, err_state_East_Invalid_Grant, err_state_West_Invalid_Grant, err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant, err_Grants_onehot_or_all_zero : out std_logic ); end Arbiter_out_one_hot_pseudo_checkers; architecture behavior of Arbiter_out_one_hot_pseudo_checkers is CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001"; CONSTANT Local: std_logic_vector (5 downto 0) := "000010"; CONSTANT North: std_logic_vector (5 downto 0) := "000100"; CONSTANT East: std_logic_vector (5 downto 0) := "001000"; CONSTANT West: std_logic_vector (5 downto 0) := "010000"; CONSTANT South: std_logic_vector (5 downto 0) := "100000"; SIGNAL Requests: std_logic_vector (4 downto 0); SIGNAL Grants: std_logic_vector (4 downto 0); begin Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L; Grants <= grant_Y_N & grant_Y_E & grant_Y_W & grant_Y_S & grant_Y_L; -- Checkers --checked process (Requests, state_in) begin if (Requests = "00000" and state_in /= IDLE ) then err_Requests_state_in_state_not_equal <= '1'; else err_Requests_state_in_state_not_equal <= '0'; end if; end process; ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- -- Round 1 --checked -- N has highest priority, then E, W, S and L (and then again N). process (state, req_X_N, state_in) begin if ( state = IDLE and req_X_N = '1' and state_in /= North ) then err_IDLE_req_X_N <= '1'; else err_IDLE_req_X_N <= '0'; end if; end process; --checked process (state, req_X_N, state_in) begin if (state = North and req_X_N = '1' and state_in /= North) then err_North_req_X_N <= '1'; else err_North_req_X_N <= '0'; end if; end process; --checked process (state, credit, req_X_N, grant_Y_N) begin if ( state = North and credit /= "00" and req_X_N = '1' and grant_Y_N /= '1' ) then err_North_credit_not_zero_req_X_N_grant_N <= '1'; else err_North_credit_not_zero_req_X_N_grant_N <= '0'; end if; end process; --checked process (state, credit, req_X_N, grant_Y_N) begin if ( state = North and (credit = "00" or req_X_N = '0') and grant_Y_N /= '0' ) then err_North_credit_zero_or_not_req_X_N_not_grant_N <= '1'; else err_North_credit_zero_or_not_req_X_N_not_grant_N <= '0'; end if; end process; --checked process (state, req_X_E, state_in) begin if (state = East and req_X_E = '1' and state_in /= East) then err_East_req_X_E <= '1'; else err_East_req_X_E <= '0'; end if; end process; --checked process (state, credit, req_X_E, grant_Y_E) begin if ( state = East and credit /= "00" and req_X_E = '1' and grant_Y_E = '0' ) then err_East_credit_not_zero_req_X_E_grant_E <= '1'; else err_East_credit_not_zero_req_X_E_grant_E <= '0'; end if; end process; --checked process (state, credit, req_X_E, grant_Y_E) begin if ( state = East and (credit = "00" or req_X_E = '0') and grant_Y_E /= '0' ) then err_East_credit_zero_or_not_req_X_E_not_grant_E <= '1'; else err_East_credit_zero_or_not_req_X_E_not_grant_E <= '0'; end if; end process; --checked process (state, req_X_W, state_in) begin if (state = West and req_X_W = '1' and state_in /= West) then err_West_req_X_W <= '1'; else err_West_req_X_W <= '0'; end if; end process; --checked process (state, credit, req_X_W, grant_Y_W) begin if ( state = West and credit /= "00" and req_X_W = '1' and grant_Y_W = '0') then err_West_credit_not_zero_req_X_E_grant_E <= '1'; else err_West_credit_not_zero_req_X_E_grant_E <= '0'; end if; end process; --checked process (state, credit, req_X_W, grant_Y_W) begin if ( state = West and (credit = "00" or req_X_W = '0') and grant_Y_W /= '0' ) then err_West_credit_zero_or_not_req_X_W_not_grant_W <= '1'; else err_West_credit_zero_or_not_req_X_W_not_grant_W <= '0'; end if; end process; --checked process (state, req_X_S, state_in) begin if (state = South and req_X_S = '1' and state_in /= South) then err_South_req_X_S <= '1'; else err_South_req_X_S <= '0'; end if; end process; --checked process (state, credit, req_X_S, grant_Y_S) begin if ( state = South and credit /= "00" and req_X_S = '1' and grant_Y_S = '0' ) then err_South_credit_not_zero_req_X_S_grant_S <= '1'; else err_South_credit_not_zero_req_X_S_grant_S <= '0'; end if; end process; --checked process (state, credit, req_X_S, grant_Y_S) begin if ( state = South and (credit = "00" or req_X_S = '0') and grant_Y_S /= '0' ) then err_South_credit_zero_or_not_req_X_S_not_grant_S <= '1'; else err_South_credit_zero_or_not_req_X_S_not_grant_S <= '0'; end if; end process; --checked -- Local is a bit different (including others case) process (state, req_X_L, state_in) begin if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and req_X_L = '1' and state_in /= Local) then err_Local_req_X_L <= '1'; else err_Local_req_X_L <= '0'; end if; end process; --checked process (state, credit, req_X_L, grant_Y_L) begin if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and credit /= "00" and req_X_L = '1' and grant_Y_L = '0' ) then err_Local_credit_not_zero_req_X_L_grant_L <= '1'; else err_Local_credit_not_zero_req_X_L_grant_L <= '0'; end if; end process; --checked process (state, credit, req_X_L, grant_Y_L) begin if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and ( credit = "00" or req_X_L = '0') and grant_Y_L /= '0' ) then err_Local_credit_zero_or_not_req_X_L_not_grant_L <= '1'; else err_Local_credit_zero_or_not_req_X_L_not_grant_L <= '0'; end if; end process; -- Checked -- Double checked! ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- -- Round 2 --checked -- IDLE process (state, req_X_N, req_X_E, state_in) begin if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then err_IDLE_req_X_E <= '1'; else err_IDLE_req_X_E <= '0'; end if; end process; -- North process (state, req_X_N, req_X_E, state_in) begin if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then err_North_req_X_E <= '1'; else err_North_req_X_E <= '0'; end if; end process; -- East process (state, req_X_E, req_X_W, state_in) begin if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then err_East_req_X_W <= '1'; else err_East_req_X_W <= '0'; end if; end process; -- West process (state, req_X_W, req_X_S, state_in) begin if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then err_West_req_X_S <= '1'; else err_West_req_X_S <= '0'; end if; end process; -- South -- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers -- for the router with CTS/RTS handshaking Flow Control process (state, req_X_S, req_X_L, state_in) begin if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then err_South_req_X_L <= '1'; else err_South_req_X_L <= '0'; end if; end process; -- Local and invalid states (others case) process (state, req_X_L, req_X_N, state_in) begin if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and req_X_L = '0' and req_X_N = '1' and state_in /= North) then err_Local_req_X_N <= '1'; else err_Local_req_X_N <= '0'; end if; end process; ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- -- Round 3 process (state, req_X_N, req_X_E, req_X_W, state_in) begin if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then err_IDLE_req_X_W <= '1'; else err_IDLE_req_X_W <= '0'; end if; end process; process (state, req_X_N, req_X_E, req_X_W, state_in) begin if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then err_North_req_X_W <= '1'; else err_North_req_X_W <= '0'; end if; end process; process (state, req_X_E, req_X_W, req_X_S, state_in) begin if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then err_East_req_X_S <= '1'; else err_East_req_X_S <= '0'; end if; end process; process (state, req_X_W, req_X_S, req_X_L, state_in) begin if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then err_West_req_X_L <= '1'; else err_West_req_X_L <= '0'; end if; end process; process (state, req_X_S, req_X_L, req_X_N, state_in) begin if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then err_South_req_X_N <= '1'; else err_South_req_X_N <= '0'; end if; end process; -- Local and invalid state(s) (others case) process (state, req_X_L, req_X_N, req_X_E, state_in) begin if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then err_Local_req_X_E <= '1'; else err_Local_req_X_E <= '0'; end if; end process; ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- -- Round 4 process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in) begin if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then err_IDLE_req_X_S <= '1'; else err_IDLE_req_X_S <= '0'; end if; end process; process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in) begin if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then err_North_req_X_S <= '1'; else err_North_req_X_S <= '0'; end if; end process; process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in) begin if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then err_East_req_X_L <= '1'; else err_East_req_X_L <= '0'; end if; end process; process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in) begin if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then err_West_req_X_N <= '1'; else err_West_req_X_N <= '0'; end if; end process; process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in) begin if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then err_South_req_X_E <= '1'; else err_South_req_X_E <= '0'; end if; end process; -- Local state or invalid state(s) (others case) process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in) begin if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then err_Local_req_X_W <= '1'; else err_Local_req_X_W <= '0'; end if; end process; -- Checked ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- -- Round 5 process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in) begin if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then err_IDLE_req_X_L <= '1'; else err_IDLE_req_X_L <= '0'; end if; end process; process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in) begin if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then err_North_req_X_L <= '1'; else err_North_req_X_L <= '0'; end if; end process; process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in) begin if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then err_East_req_X_N <= '1'; else err_East_req_X_N <= '0'; end if; end process; process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in) begin if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then err_West_req_X_E <= '1'; else err_West_req_X_E <= '0'; end if; end process; process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in) begin if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then err_South_req_X_W <= '1'; else err_South_req_X_W <= '0'; end if; end process; -- Local state or invalid state(s) (others case) process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in) begin if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then err_Local_req_X_S <= '1'; else err_Local_req_X_S <= '0'; end if; end process; -- Checked ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- process (state_in) begin if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and state_in /= South and state_in /= Local) then err_state_in_onehot <= '1'; else err_state_in_onehot <= '0'; end if; end process; -- Checked process (Requests, Grants) begin if ( Requests = "00000" and Grants /= "00000") then err_no_request_grants <= '1'; else err_no_request_grants <= '0'; end if; end process; -- Checked process (Requests, state_in) begin if (Requests /= "00000" and state_in = IDLE) then err_request_IDLE_state <= '1'; else err_request_IDLE_state <= '0'; end if; end process; ----------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------- process (state, Grants) begin if (state = IDLE and Grants /= "00000") then err_request_IDLE_not_Grants <= '1'; else err_request_IDLE_not_Grants <= '0'; end if; end process; process (state, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L) begin if (state = North and (grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then err_state_North_Invalid_Grant <= '1'; else err_state_North_Invalid_Grant <= '0'; end if; end process; process (state, grant_Y_N, grant_Y_W, grant_Y_S, grant_Y_L) begin if (state = East and (grant_Y_N = '1' or grant_Y_W = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then err_state_East_Invalid_Grant <= '1'; else err_state_East_Invalid_Grant <= '0'; end if; end process; process (state, grant_Y_N, grant_Y_E, grant_Y_S, grant_Y_L) begin if (state = West and (grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then err_state_West_Invalid_Grant <= '1'; else err_state_West_Invalid_Grant <= '0'; end if; end process; process (state, grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_L) begin if (state = South and (grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_L = '1') ) then err_state_South_Invalid_Grant <= '1'; else err_state_South_Invalid_Grant <= '0'; end if; end process; -- Local or invalid state(s) (a bit different logic!) process (state, grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S) begin if (state /= IDLE and state /= North and state /= East and state /= West and state /= South and (grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_S = '1') ) then err_state_Local_Invalid_Grant <= '1'; else err_state_Local_Invalid_Grant <= '0'; end if; end process; -- Because we do not have multi-casting, Grants must always be one-hot or all zeros, no other possible combination for them ! process (Grants) begin if (Grants /= "00000" and Grants /= "00001" and Grants /= "00010" and Grants /= "00100" and Grants /= "01000" and Grants /= "10000") then err_Grants_onehot_or_all_zero <= '1'; else err_Grants_onehot_or_all_zero <= '0'; end if; end process; end behavior;
gpl-3.0
61aa94d28b913b50f3576cd8eafb7347
0.488928
2.915128
false
false
false
false
elainemielas/CVUT_BI-PNO
project1/mux.vhd
1
673
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity MUX is port ( SHOWA1A0 : in std_logic; SHOWA3A2 : in std_logic; OUTPUT : in std_logic_vector (15 downto 0); SHOW1OUT : in std_logic_vector (15 downto 0); SHOW2OUT : in std_logic_vector (15 downto 0); DATAOUT : out std_logic_vector (15 downto 0) ); end MUX; architecture MUX_BODY of MUX is begin PRIDEL : process (SHOWA1A0, SHOWA3A2, SHOW1OUT, SHOW2OUT, OUTPUT) begin if SHOWA1A0 = '1' then DATAOUT <= SHOW1OUT; elsif SHOWA3A2 = '1' then DATAOUT <= SHOW2OUT; else DATAOUT <= OUTPUT; end if; end process; end architecture;
mit
9f999de736c7eb36aaa7a162f586cad2
0.692422
2.724696
false
false
false
false
siavooshpayandehazad/NoC_Router
RTL/Processor_NI/NoC_Node.vhd
3
4,074
------------------------------------------------------------------- -- TITLE: NoC_Node -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 4/21/01 -- ORIGNAL FILENAME: tbench.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- This entity provides a simple NoC node with plasma as its processor --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; use ieee.std_logic_unsigned.all; entity NoC_Node is generic( current_address : integer := 0; stim_file: string :="code.txt"; mem_address_width : natural := 16; log_file : string := "output.txt"; memory_type : string := "TRI_PORT_X" -- "DUAL_PORT_" -- "ALTERA_LPM" -- "XILINX_16X" ); port( reset : in std_logic; clk : in std_logic; credit_in : in std_logic; valid_out: out std_logic; TX: out std_logic_vector(31 downto 0); credit_out : out std_logic; valid_in: in std_logic; RX: in std_logic_vector(31 downto 0) ); end; --entity NoC_Node architecture messed_up of NoC_Node is signal interrupt : std_logic := '0'; signal mem_write : std_logic; signal address : std_logic_vector(31 downto 2); signal data_write : std_logic_vector(31 downto 0); signal data_read : std_logic_vector(31 downto 0); signal pause1 : std_logic := '0'; signal pause2 : std_logic := '0'; signal pause : std_logic; signal no_ddr_start: std_logic; signal no_ddr_stop : std_logic; signal byte_we : std_logic_vector(3 downto 0); signal uart_write : std_logic; signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0'); --signal credit_in, valid_in: std_logic := '0'; --signal credit_out, valid_out: std_logic := '0'; --signal RX: std_logic_vector(31 downto 0) := (others => '0'); --signal TX: std_logic_vector(31 downto 0) := (others => '0'); -- signal credit_counter_out_0: std_logic_vector (1 downto 0); begin --architecture --pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns; pause1 <= '0'; --pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns; pause2 <= '0'; pause <= pause1 or pause2; --gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK --gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV --gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD --gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK u1_plasma: plasma generic map (memory_type => memory_type, ethernet => '0', use_cache => '0', log_file => log_file, current_address => current_address, stim_file => stim_file) PORT MAP ( clk => clk, reset => reset, uart_read => uart_write, uart_write => uart_write, address => address, byte_we => byte_we, data_write => data_write, data_read => data_read, mem_pause_in => pause, no_ddr_start => no_ddr_start, no_ddr_stop => no_ddr_stop, gpio0_out => open, gpioA_in => gpioA_in, credit_in => credit_in, valid_out => valid_out, TX => TX, credit_out => credit_out, valid_in => valid_in, RX => RX ); memory_impl: memory generic map (address_width => mem_address_width) port map ( clk => clk, address => address, data_write => data_write, pause => pause, byte_we => byte_we, data_read => data_read ); end; --architecture logic
gpl-3.0
8bc6632f2f898655a81304862bec1d34
0.517673
3.558079
false
false
false
false
AndyMcC0/UVVM_All
uvvm_util/src/hierarchy_linked_list_pkg.vhd
1
41,905
--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <[email protected]>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use std.textio.all; use work.types_pkg.all; use work.string_methods_pkg.all; use work.adaptations_pkg.all; package hierarchy_linked_list_pkg is type t_hierarchy_linked_list is protected procedure initialize_hierarchy( base_scope : string := ""; stop_limit : t_alert_counters); procedure insert_in_tree( hierarchy_node : t_hierarchy_node; parent_scope : string); impure function is_empty return boolean; impure function is_not_empty return boolean; impure function get_size return natural; procedure clear; impure function contains_scope( scope : string ) return boolean; procedure contains_scope_return_data( scope : string; variable result : out boolean; variable hierarchy_node : out t_hierarchy_node); procedure alert ( constant scope : string; constant alert_level : t_alert_level; constant attention : t_attention := REGARD; constant msg : string := ""); procedure increment_expected_alerts( scope : string; alert_level: t_alert_level; amount : natural := 1); procedure set_expected_alerts( scope : string; alert_level: t_alert_level; expected_alerts : natural); impure function get_expected_alerts( scope : string; alert_level : t_alert_level ) return natural; procedure increment_stop_limit( scope : string; alert_level: t_alert_level; amount : natural := 1); procedure set_stop_limit( scope : string; alert_level: t_alert_level; stop_limit : natural); impure function get_stop_limit( scope : string; alert_level : t_alert_level ) return natural; procedure print_hierarchical_log( order : t_order := FINAL); impure function get_parent_scope( scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH)) return string; procedure change_parent( scope : string; parent_scope : string ); procedure set_top_level_stop_limit( alert_level : t_alert_level; value : natural ); impure function get_top_level_stop_limit( alert_level : t_alert_level ) return natural; procedure enable_alert_level( scope : string; alert_level : t_alert_level ); procedure disable_alert_level( scope : string; alert_level : t_alert_level ); procedure enable_all_alert_levels( scope : string ); procedure disable_all_alert_levels( scope : string ); end protected; end package hierarchy_linked_list_pkg; package body hierarchy_linked_list_pkg is type t_hierarchy_linked_list is protected body -- Types and control variables for the linked list implementation type t_element; type t_element_ptr is access t_element; type t_element is record first_child : t_element_ptr; -- Pointer to the first element in a linked list of children next_sibling : t_element_ptr; -- Pointer to the next element in a linked list of siblings prev_sibling : t_element_ptr; -- Pointer to the previous element in a linked list of siblings parent : t_element_ptr; element_data : t_hierarchy_node; hierarchy_level : natural; -- How far down the tree this node is. Used when printing summary. end record; variable vr_top_element_ptr : t_element_ptr; variable vr_num_elements_in_tree : natural := 0; variable vr_max_hierarchy_level : natural := 0; -- Initialization variables variable vr_has_been_initialized : boolean := false; variable vr_base_scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH); procedure initialize_hierarchy( base_scope : string := ""; stop_limit : t_alert_counters) is variable v_base_scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH) := justify(base_scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH); variable base_node : t_hierarchy_node := (v_base_scope, (others => (others => 0)), stop_limit, (others => true)); begin if not vr_has_been_initialized then -- Generate a base node. insert_in_tree(base_node, ""); vr_base_scope := v_base_scope; vr_has_been_initialized := true; end if; end procedure; procedure search_for_scope( variable starting_node : in t_element_ptr; scope : string; variable result_node : out t_element_ptr; variable found : out boolean ) is variable v_current_ptr : t_element_ptr := null; variable v_found : boolean := false; variable v_scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH) := justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH); begin found := false; -- is this the correct scope? if starting_node.element_data.name = v_scope then result_node := starting_node; found := true; return; end if; -- Go downwards in the tree. if starting_node.first_child /= null then search_for_scope(starting_node.first_child, v_scope, v_current_ptr, v_found); if v_found then result_node := v_current_ptr; found := true; return; end if; end if; -- Go sideways in the tree if starting_node.next_sibling /= null then search_for_scope(starting_node.next_sibling, v_scope, v_current_ptr, v_found); if v_found then result_node := v_current_ptr; found := true; return; end if; end if; -- No candidate found end procedure; procedure search_for_scope( variable starting_node : in t_element_ptr; hierarchy_node : t_hierarchy_node; variable result_node : out t_element_ptr; variable found : out boolean ) is variable v_current_ptr : t_element_ptr := null; variable v_found : boolean := false; begin found := false; -- is this the correct node? if starting_node.element_data = hierarchy_node then result_node := starting_node; found := true; return; end if; -- Go downwards in the tree. if starting_node.first_child /= null then search_for_scope(starting_node.first_child, hierarchy_node, v_current_ptr, v_found); if v_found then result_node := v_current_ptr; found := true; return; end if; end if; -- Go sideways in the tree if starting_node.next_sibling /= null then search_for_scope(starting_node.next_sibling, hierarchy_node, v_current_ptr, v_found); if v_found then result_node := v_current_ptr; found := true; return; end if; end if; -- No candidate found end procedure; -- -- insert_in_tree -- -- Insert a new element in the tree. -- -- procedure insert_in_tree( hierarchy_node : t_hierarchy_node; parent_scope : string ) is variable v_parent_ptr : t_element_ptr; variable v_child_ptr : t_element_ptr; variable v_found : boolean := false; variable v_parent_scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH) := justify(parent_scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH); variable v_hierarchy_node : t_hierarchy_node; begin v_hierarchy_node := hierarchy_node; v_hierarchy_node.name := justify(hierarchy_node.name, LEFT, C_HIERARCHY_NODE_NAME_LENGTH); -- Set read and write pointers when appending element to existing list if vr_num_elements_in_tree > 0 and vr_has_been_initialized then -- Search for the parent. search_for_scope(vr_top_element_ptr, v_parent_scope, v_parent_ptr, v_found); if v_found then -- Parent found. if v_parent_ptr.first_child = null then -- Parent has no children. This node shall be the first child. v_parent_ptr.first_child := new t_element'(first_child => null, next_sibling => null, prev_sibling => null, parent => v_parent_ptr, element_data => v_hierarchy_node, hierarchy_level => v_parent_ptr.hierarchy_level + 1); else -- Parent has at least one child. This node shall be a sibling of the other child(ren). v_child_ptr := v_parent_ptr.first_child; -- Find last current sibling while v_child_ptr.next_sibling /= null loop v_child_ptr := v_child_ptr.next_sibling; end loop; -- Insert this node as a new sibling v_child_ptr.next_sibling := new t_element'(first_child => null, next_sibling => null, prev_sibling => v_child_ptr, parent => v_parent_ptr, element_data => v_hierarchy_node, hierarchy_level => v_parent_ptr.hierarchy_level + 1); end if; -- Update max hierarchy level if vr_max_hierarchy_level < v_parent_ptr.hierarchy_level + 1 then vr_max_hierarchy_level := v_parent_ptr.hierarchy_level + 1; end if; else -- parent not in tree -- Register to top level insert_in_tree(v_hierarchy_node, C_BASE_HIERARCHY_LEVEL); end if; else -- tree is empty, create top element in tree vr_top_element_ptr := new t_element'(first_child => null, next_sibling => null, prev_sibling => null, parent => null, element_data => v_hierarchy_node, hierarchy_level => 0); end if; -- Increment number of elements vr_num_elements_in_tree := vr_num_elements_in_tree + 1; end procedure; procedure clear_recursively(variable element_ptr : inout t_element_ptr) is begin assert element_ptr /= null report "Attempting to clear null pointer!" severity error ; if element_ptr.first_child /= null then clear_recursively(element_ptr.first_child); end if; if element_ptr.next_sibling /= null then clear_recursively(element_ptr.next_sibling); end if; DEALLOCATE(element_ptr); end procedure; procedure clear is variable v_to_be_deallocated_ptr : t_element_ptr; begin -- Deallocate all nodes in the tree if vr_top_element_ptr /= null then clear_recursively(vr_top_element_ptr); end if; -- Reset the linked_list counter vr_num_elements_in_tree := 0; -- Reset the hierarchy variables vr_max_hierarchy_level := 0; vr_has_been_initialized := false; end procedure; impure function is_empty return boolean is begin if vr_num_elements_in_tree = 0 then return true; else return false; end if; end function; impure function is_not_empty return boolean is begin return not is_empty; end function; impure function get_size return natural is begin return vr_num_elements_in_tree; end function; impure function contains_scope( scope : string ) return boolean is variable v_candidate_ptr : t_element_ptr := null; variable v_found : boolean := false; begin search_for_scope(vr_top_element_ptr, scope, v_candidate_ptr, v_found); return v_found; end function; procedure contains_scope_return_data( scope : string; variable result : out boolean; variable hierarchy_node : out t_hierarchy_node ) is variable v_candidate_ptr : t_element_ptr := null; variable v_found : boolean := false; begin search_for_scope(vr_top_element_ptr, scope, v_candidate_ptr, v_found); result := v_found; if v_found then hierarchy_node := v_candidate_ptr.element_data; end if; end procedure; procedure tee ( file file_handle : text; variable my_line : inout line ) is variable v_line : line; begin write (v_line, my_line.all); writeline(file_handle, v_line); end procedure tee; procedure alert ( constant scope : string; constant alert_level : t_alert_level; constant attention : t_attention := REGARD; constant msg : string := "" ) is variable v_starting_node_ptr : t_element_ptr; variable v_current_ptr : t_element_ptr; variable v_found : boolean := false; variable v_is_in_tree : boolean := false; variable v_msg : line; -- msg after pot. replacement of \n variable v_info : line; variable v_hierarchy : line; -- stores the hierarchy propagation variable v_parent_node : t_hierarchy_node; variable v_do_print : boolean := false; -- Enable/disable print of alert message begin if vr_num_elements_in_tree > 0 and vr_has_been_initialized then -- search for tree node that contains scope search_for_scope(vr_top_element_ptr, scope, v_starting_node_ptr, v_found); if not v_found then -- If the scope was not found, register automatically -- with the default base level scope as parent. -- Stop limit set to default. insert_in_tree((scope, (others => (others => 0)), (others => 0), (others => true)), justify(C_BASE_HIERARCHY_LEVEL, LEFT, C_HIERARCHY_NODE_NAME_LENGTH)); -- Search again to get ptr search_for_scope(vr_top_element_ptr, scope, v_starting_node_ptr, v_found); end if; v_current_ptr := v_starting_node_ptr; assert v_found report "Node not found!" severity failure; write(v_msg, replace_backslash_n_with_lf(msg)); -- Only print of alert level print is enabled for this alert level -- for the node where the alert is called. if attention /= IGNORE then if v_current_ptr.element_data.alert_level_print(alert_level) = true then v_do_print := true; end if; -- Write first part of alert message -- Serious alerts need more attention - thus more space and lines if (alert_level > MANUAL_CHECK) then write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH)); end if; write(v_info, LF & "*** "); end if; -- 4. Propagate alert and build alert message while v_current_ptr /= null loop if attention = IGNORE then -- Increment alert counter for this node at alert attention IGNORE v_current_ptr.element_data.alert_attention_counters(alert_level)(IGNORE) := v_current_ptr.element_data.alert_attention_counters(alert_level)(IGNORE)+ 1; else -- Increment alert counter for this node at alert attention REGARD v_current_ptr.element_data.alert_attention_counters(alert_level)(REGARD) := v_current_ptr.element_data.alert_attention_counters(alert_level)(REGARD)+ 1; write(v_hierarchy, v_current_ptr.element_data.name(1 to pos_of_rightmost_non_whitespace(v_current_ptr.element_data.name))); if v_current_ptr.parent /= null then write(v_hierarchy, string'(" -> ")); end if; -- Exit loop if stop-limit is reached for number of this alert if (v_current_ptr.element_data.alert_stop_limit(alert_level) /= 0) and (v_current_ptr.element_data.alert_attention_counters(alert_level)(REGARD) >= v_current_ptr.element_data.alert_stop_limit(alert_level)) then exit; end if; end if; v_current_ptr := v_current_ptr.parent; end loop; if v_current_ptr = null then -- Nothing went wrong in the previous loop v_current_ptr := v_starting_node_ptr; end if; if attention /= IGNORE then -- 3. Write body of alert message -- Remove line feed character (LF) -- if single line alert enabled. if not C_SINGLE_LINE_ALERT then write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(v_current_ptr.element_data.alert_attention_counters(alert_level)(REGARD)) & " ***" & LF & justify( to_string(now, C_LOG_TIME_BASE), RIGHT, C_LOG_TIME_WIDTH) & " " & v_hierarchy.all & LF & wrap_lines(v_msg.all, C_LOG_TIME_WIDTH + 4, C_LOG_TIME_WIDTH + 4, C_LOG_INFO_WIDTH)); else replace(v_msg, LF, ' '); write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(v_current_ptr.element_data.alert_attention_counters(alert_level)(REGARD)) & " ***" & justify( to_string(now, C_LOG_TIME_BASE), RIGHT, C_LOG_TIME_WIDTH) & " " & v_hierarchy.all & " " & v_msg.all); end if; end if; if v_msg /= null then deallocate(v_msg); end if; -- Write stop message if stop-limit is reached for number of this alert if (v_current_ptr.element_data.alert_stop_limit(alert_level) /= 0) and (v_current_ptr.element_data.alert_attention_counters(alert_level)(REGARD) >= v_current_ptr.element_data.alert_stop_limit(alert_level)) then v_do_print := true; -- If the alert limit has been reached, print alert message anyway. write(v_info, LF & LF & "Simulator has been paused as requested after " & to_string(v_current_ptr.element_data.alert_attention_counters(alert_level)(REGARD)) & " " & to_upper(to_string(alert_level)) & LF); if (alert_level = MANUAL_CHECK) then write(v_info, "Carry out above check." & LF & "Then continue simulation from within simulator." & LF); else write(v_info, string'("*** To find the root cause of this alert, " & "step out the HDL calling stack in your simulator. ***" & LF & "*** For example, step out until you reach the call from the test sequencer. ***")); end if; end if; if v_hierarchy /= null then deallocate(v_hierarchy); end if; -- 5. Write last part of alert message if (alert_level > MANUAL_CHECK) then write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH) & LF & LF); else write(v_info, LF); end if; prefix_lines(v_info); if v_do_print then -- Only print if alert level print enabled for this alert level. tee(OUTPUT, v_info); tee(ALERT_FILE, v_info); writeline(LOG_FILE, v_info); else if v_info /= null then deallocate(v_info); end if; end if; -- Stop simulation if stop-limit is reached for number of this alert if v_current_ptr /= null then if (v_current_ptr.element_data.alert_stop_limit(alert_level) /= 0) then if (v_current_ptr.element_data.alert_attention_counters(alert_level)(REGARD) >= v_current_ptr.element_data.alert_stop_limit(alert_level)) then assert false report "This single Failure line has been provoked to stop the simulation. See alert-message above" severity failure; end if; end if; end if; end if; end procedure; procedure increment_expected_alerts( scope : string; alert_level: t_alert_level; amount : natural := 1 ) is variable v_current_ptr : t_element_ptr; variable v_new_expected_alerts : natural; variable v_found : boolean := false; begin if vr_num_elements_in_tree > 0 and vr_has_been_initialized then -- search for tree node that contains scope search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found); assert v_found report "Scope not found!" severity warning; if v_found then -- Increment expected alerts for this node. v_new_expected_alerts := v_current_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) + amount; v_current_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) := v_new_expected_alerts; -- Change pointer to parent element v_current_ptr := v_current_ptr.parent; -- Propagate expected alerts while v_current_ptr /= null loop if v_current_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) < v_new_expected_alerts then v_current_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) := v_new_expected_alerts; end if; v_current_ptr := v_current_ptr.parent; end loop; end if; end if; end procedure; procedure set_expected_alerts( scope : string; alert_level: t_alert_level; expected_alerts : natural ) is variable v_current_ptr : t_element_ptr; variable v_found : boolean := false; variable v_scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH) := justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH); begin if vr_num_elements_in_tree > 0 and vr_has_been_initialized then -- search for tree node that contains scope search_for_scope(vr_top_element_ptr, v_scope, v_current_ptr, v_found); assert v_found report "Scope not found!" severity warning; if v_found then -- Set stop limit for this node v_current_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) := expected_alerts; -- Change pointer to parent element v_current_ptr := v_current_ptr.parent; -- Propagate stop limit while v_current_ptr /= null loop if v_current_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) < expected_alerts then v_current_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) := expected_alerts; end if; v_current_ptr := v_current_ptr.parent; end loop; end if; end if; end procedure; impure function get_expected_alerts( scope : string; alert_level : t_alert_level ) return natural is variable v_current_ptr : t_element_ptr; variable v_found : boolean := false; variable v_scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH) := justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH); begin search_for_scope(vr_top_element_ptr, v_scope, v_current_ptr, v_found); if v_found then return v_current_ptr.element_data.alert_attention_counters(alert_level)(EXPECT); else return 0; end if; end function; procedure increment_stop_limit( scope : string; alert_level: t_alert_level; amount : natural := 1 ) is variable v_current_ptr : t_element_ptr; variable v_new_stop_limit : natural; variable v_found : boolean := false; begin if vr_num_elements_in_tree > 0 and vr_has_been_initialized then -- search for tree node that contains scope search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found); assert v_found report "Scope not found!" severity warning; if v_found then -- Increment stop limit for this node. v_new_stop_limit := v_current_ptr.element_data.alert_stop_limit(alert_level) + amount; v_current_ptr.element_data.alert_stop_limit(alert_level) := v_new_stop_limit; -- Change pointer to parent element v_current_ptr := v_current_ptr.parent; -- Propagate stop limit while v_current_ptr /= null loop if v_current_ptr.element_data.alert_stop_limit(alert_level) < v_new_stop_limit then v_current_ptr.element_data.alert_stop_limit(alert_level) := v_new_stop_limit; end if; v_current_ptr := v_current_ptr.parent; end loop; end if; end if; end procedure; procedure set_stop_limit( scope : string; alert_level: t_alert_level; stop_limit : natural ) is variable v_current_ptr : t_element_ptr; variable v_found : boolean := false; begin if vr_num_elements_in_tree > 0 and vr_has_been_initialized then -- search for tree node that contains scope search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found); assert v_found report "Scope not found!" severity warning; if v_found then -- Set stop limit for this node v_current_ptr.element_data.alert_stop_limit(alert_level) := stop_limit; v_current_ptr := v_current_ptr.parent; -- Propagate stop limit while v_current_ptr /= null loop if v_current_ptr.element_data.alert_stop_limit(alert_level) < stop_limit then v_current_ptr.element_data.alert_stop_limit(alert_level) := stop_limit; end if; v_current_ptr := v_current_ptr.parent; end loop; end if; end if; end procedure; impure function get_stop_limit( scope : string; alert_level : t_alert_level ) return natural is variable v_current_ptr : t_element_ptr; variable v_found : boolean := false; begin search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found); if v_found then return v_current_ptr.element_data.alert_stop_limit(alert_level); else return 0; end if; end function; procedure generate_hierarchy_prefix( variable starting_node_ptr : in t_element_ptr; variable calling_node_ptr : in t_element_ptr; variable origin_node_ptr : in t_element_ptr; variable v_line : inout line ) is variable v_indent_correction_amount : natural := 0; begin if starting_node_ptr.parent = null then -- This is the top level -- Write a '|' as first character if the calling node (child) -- has another sibling, else nothing. if origin_node_ptr.parent /= starting_node_ptr and calling_node_ptr.next_sibling /= null then write(v_line, string'("|")); end if; else -- This starting_node is not the top node -- Create prefix for parent first. generate_hierarchy_prefix(starting_node_ptr.parent, starting_node_ptr, origin_node_ptr, v_line); -- All that have received a '|' as the first character in the buffer -- has one space too many afterwards. Special case for the first character. if starting_node_ptr.parent.parent = null then if starting_node_ptr.next_sibling /= null then v_indent_correction_amount := 1; end if; end if; if starting_node_ptr.next_sibling /= null then -- Has another sibling if calling_node_ptr.next_sibling /= null then write(v_line, fill_string(' ', 2 - v_indent_correction_amount)); write(v_line, string'("|")); else write(v_line, fill_string(' ', 3 - v_indent_correction_amount)); end if; else -- No next sibling write(v_line, fill_string(' ', 3 - v_indent_correction_amount)); end if; end if; end procedure; procedure print_node( variable starting_node_ptr : in t_element_ptr; variable v_status_ok : inout boolean; variable v_mismatch : inout boolean; variable v_line : inout line ) is variable v_current_ptr : t_element_ptr; begin -- Write indentation according to hierarchy level if starting_node_ptr.hierarchy_level > 0 then generate_hierarchy_prefix(starting_node_ptr.parent, starting_node_ptr, starting_node_ptr, v_line); if starting_node_ptr.next_sibling /= null then write(v_line, string'("|- ")); else write(v_line, string'("`- ")); end if; end if; -- Print name of node write(v_line, starting_node_ptr.element_data.name); -- Adjust the columns according to max hierarchy level if vr_max_hierarchy_level > 0 then if starting_node_ptr.hierarchy_level /= vr_max_hierarchy_level then write(v_line, fill_string(' ', (vr_max_hierarchy_level - starting_node_ptr.hierarchy_level)*3)); end if; end if; -- Print colon to signify the end of the name write(v_line, string'(":")); -- Print counters for each of the alert levels. for alert_level in NOTE to t_alert_level'right loop write(v_line, justify(integer'image(starting_node_ptr.element_data.alert_attention_counters(alert_level)(REGARD)) & "/" & integer'image(starting_node_ptr.element_data.alert_attention_counters(alert_level)(EXPECT)) & "/" & integer'image(starting_node_ptr.element_data.alert_attention_counters(alert_level)(IGNORE)) ,RIGHT, 11) & " "); if v_status_ok = true then if starting_node_ptr.element_data.alert_attention_counters(alert_level)(REGARD) /= starting_node_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) then if alert_level > MANUAL_CHECK then if starting_node_ptr.element_data.alert_attention_counters(alert_level)(REGARD) < starting_node_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) then v_mismatch := true; else v_status_ok := false; end if; end if; end if; end if; end loop; write(v_line, LF); if starting_node_ptr.first_child /= null then print_node(starting_node_ptr.first_child, v_status_ok, v_mismatch, v_line); end if; if starting_node_ptr.next_sibling /= null then print_node(starting_node_ptr.next_sibling, v_status_ok, v_mismatch, v_line); end if; end procedure; procedure print_hierarchical_log( order : t_order := FINAL ) is variable v_header : string(1 to 80); variable v_line : line; variable v_line_copy : line; constant prefix : string := C_LOG_PREFIX & " "; variable v_status_ok : boolean := true; variable v_mismatch : boolean := false; begin if order = INTERMEDIATE then v_header := "*** INTERMEDIATE SUMMARY OF ALL ALERTS *** Format: REGARDED/EXPECTED/IGNORED"; else -- order=FINAL v_header := "*** FINAL SUMMARY OF ALL ALERTS *** Format: REGARDED/EXPECTED/IGNORED "; end if; -- Write header write(v_line, LF & fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & v_header & LF & fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & " " & justify(" ", RIGHT, 3+ C_HIERARCHY_NODE_NAME_LENGTH + vr_max_hierarchy_level*3) & "NOTE" & justify(" ", RIGHT, 6) & "TB_NOTE" & justify(" ", RIGHT, 5) & "WARNING" & justify(" ", RIGHT, 3) & "TB_WARNING" & justify(" ", RIGHT, 2) & "MANUAL_CHECK" & justify(" ", RIGHT, 3) & "ERROR" & justify(" ", RIGHT, 5) & "TB_ERROR" & justify(" ", RIGHT, 5) & "FAILURE" & justify(" ", RIGHT, 3) & "TB_FAILURE" & LF); -- Print all nodes if vr_num_elements_in_tree > 0 and vr_has_been_initialized then print_node(vr_top_element_ptr, v_status_ok, v_mismatch, v_line); end if; write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF); -- Print a conclusion when called from the FINAL part of the test sequencer -- but not when called from in the middle of the test sequence (order=INTERMEDIATE) if order = FINAL then if not v_status_ok then write(v_line, ">> Simulation FAILED, with unexpected serious alert(s)" & LF); elsif v_mismatch then write(v_line, ">> Simulation FAILED: Mismatch between counted and expected serious alerts" & LF); else write(v_line, ">> Simulation SUCCESS: No mismatch between counted and expected serious alerts" & LF); end if; write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & LF); end if; wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length); prefix_lines(v_line, prefix); -- Write the info string to the target file write (v_line_copy, v_line.all & lf); -- copy line writeline(OUTPUT, v_line); writeline(LOG_FILE, v_line_copy); end procedure; impure function get_parent_scope( scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH)) return string is variable v_current_ptr : t_element_ptr := null; variable v_found : boolean := false; begin if vr_num_elements_in_tree > 0 and vr_has_been_initialized then search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found); assert v_found report "Scope not found. Exiting get_parent_scope()..." severity warning; if not v_found then return justify("", LEFT, C_HIERARCHY_NODE_NAME_LENGTH); end if; if v_current_ptr.parent /= null then return v_current_ptr.parent.element_data.name; end if; end if; return ""; end function; procedure propagate_hierarchy_level( variable node_ptr : inout t_element_ptr ) is begin if node_ptr /= null then if node_ptr.parent /= null then node_ptr.hierarchy_level := node_ptr.parent.hierarchy_level + 1; else -- No parent node_ptr.hierarchy_level := 0; end if; if vr_max_hierarchy_level < node_ptr.hierarchy_level then vr_max_hierarchy_level := node_ptr.hierarchy_level; end if; if node_ptr.next_sibling /= null then propagate_hierarchy_level(node_ptr.next_sibling); end if; if node_ptr.first_child /= null then propagate_hierarchy_level(node_ptr.first_child); end if; end if; end procedure; procedure change_parent( scope : string; parent_scope : string ) is variable v_old_parent_ptr : t_element_ptr := null; variable v_new_parent_ptr : t_element_ptr := null; variable v_child_ptr : t_element_ptr := null; variable v_current_ptr : t_element_ptr := null; variable v_found : boolean := false; begin if vr_num_elements_in_tree > 0 and vr_has_been_initialized then search_for_scope(vr_top_element_ptr, scope, v_child_ptr, v_found); assert v_found report "Child not found. Exiting change_parent()..." severity warning; if not v_found then return; end if; search_for_scope(vr_top_element_ptr, parent_scope, v_new_parent_ptr, v_found); assert v_found report "Parent not found. Exiting change_parent()..." severity warning; if not v_found then return; end if; if v_child_ptr.first_child /= null then search_for_scope(v_child_ptr.first_child, parent_scope, v_current_ptr, v_found); assert not v_found report "New parent is the descendant of the node that shall be moved! Illegal operation!" severity failure; end if; -- Clean up -- Need to check the current parent of the child for any other children, -- then clean up the next_sibling, prev_sibling and first_child pointers. v_old_parent_ptr := v_child_ptr.parent; if v_old_parent_ptr /= null then if v_old_parent_ptr.first_child = v_child_ptr then -- First_child is this child. Check if any siblings. -- Prev_sibling is null since this is first child. -- Next sibling can be something else. -- Correct first_child for old parent if v_child_ptr.next_sibling /= null then -- Set next_sibling to be first child v_old_parent_ptr.first_child := v_child_ptr.next_sibling; -- Clear prev_sibling for the sibling that will now be first_child of old_parent v_child_ptr.next_sibling.prev_sibling := null; else -- No siblings, clear first_child v_old_parent_ptr.first_child := null; end if; else -- This child must be one of the siblings. -- Remove this child and glue together the other siblings -- Create pointer from previous sibling to next sibling v_child_ptr.prev_sibling.next_sibling := v_child_ptr.next_sibling; -- Create pointer from next sibling to previous sibling if v_child_ptr.next_sibling /= null then v_child_ptr.next_sibling.prev_sibling := v_child_ptr.prev_sibling; end if; end if; -- Clear siblings to prepare for another parent v_child_ptr.prev_sibling := null; v_child_ptr.next_sibling := null; end if; -- Set new parent and prev_sibling for the child. if v_new_parent_ptr.first_child = null then -- No children previously created for this parent v_new_parent_ptr.first_child := v_child_ptr; else -- There is at least 1 child belonging to the new parent v_current_ptr := v_new_parent_ptr.first_child; while v_current_ptr.next_sibling /= null loop v_current_ptr := v_current_ptr.next_sibling; end loop; -- v_current_ptr is now the final sibling belonging to -- the new parent v_current_ptr.next_sibling := v_child_ptr; v_child_ptr.prev_sibling := v_current_ptr; end if; -- Set parent correctly v_child_ptr.parent := v_new_parent_ptr; -- Update hierarchy levels for the whole tree vr_max_hierarchy_level := 0; propagate_hierarchy_level(vr_top_element_ptr); end if; end procedure; procedure set_top_level_stop_limit( alert_level : t_alert_level; value : natural ) is begin -- -- vr_top_element_ptr.element_data.alert_stop_limit(alert_level) := value; -- Evaluate new stop limit in case it is less than or equal to the current alert counter for this alert level -- If that is the case, a new alert with the same alert level shall be triggered. if vr_top_element_ptr.element_data.alert_stop_limit(alert_level) /= 0 and (vr_top_element_ptr.element_data.alert_attention_counters(alert_level)(REGARD) >= vr_top_element_ptr.element_data.alert_stop_limit(alert_level)) then assert false report "Alert stop limit for scope " & vr_top_element_ptr.element_data.name & " at alert level " & to_upper(to_string(alert_level)) & " set to " & to_string(value) & ", which is lower than the current " & to_upper(to_string(alert_level)) & " count (" & to_string(vr_top_element_ptr.element_data.alert_attention_counters(alert_level)(REGARD)) & ")." severity failure; end if; end procedure; impure function get_top_level_stop_limit( alert_level : t_alert_level ) return natural is begin return vr_top_element_ptr.element_data.alert_stop_limit(alert_level); end function; procedure propagate_alert_level( variable node_ptr : inout t_element_ptr; constant alert_level : t_alert_level; constant setting : boolean ) is begin if node_ptr /= null then node_ptr.element_data.alert_level_print(alert_level) := setting; if node_ptr.next_sibling /= null then propagate_alert_level(node_ptr.next_sibling, alert_level, setting); end if; if node_ptr.first_child /= null then propagate_alert_level(node_ptr.first_child, alert_level, setting); end if; end if; end procedure; procedure enable_alert_level( scope : string; alert_level : t_alert_level ) is variable v_current_ptr : t_element_ptr := null; variable v_found : boolean := false; begin search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found); if v_found then propagate_alert_level(v_current_ptr, alert_level, true); end if; end procedure; procedure disable_alert_level( scope : string; alert_level : t_alert_level ) is variable v_current_ptr : t_element_ptr := null; variable v_found : boolean := false; begin search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found); if v_found then propagate_alert_level(v_current_ptr, alert_level, false); end if; end procedure; procedure enable_all_alert_levels( scope : string ) is variable v_current_ptr : t_element_ptr := null; variable v_found : boolean := false; begin search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found); if v_found then for alert_level in NOTE to t_alert_level'right loop propagate_alert_level(v_current_ptr, alert_level, true); end loop; end if; end procedure; procedure disable_all_alert_levels( scope : string ) is variable v_current_ptr : t_element_ptr := null; variable v_found : boolean := false; begin search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found); if v_found then for alert_level in NOTE to t_alert_level'right loop propagate_alert_level(v_current_ptr, alert_level, false); end loop; end if; end procedure; end protected body; end package body hierarchy_linked_list_pkg;
mit
768884556ff7a431ee82e23a029e0b38
0.617325
3.810238
false
false
false
false