repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
AndyMcC0/UVVM_All | bitvis_vip_spi/src/vvc_cmd_pkg.vhd | 1 | 7,098 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_cmd_pkg is
--===============================================================================================
-- t_operation
-- - Bitvis defined BFM operations
--===============================================================================================
type t_operation is (
-- UVVM common
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
MASTER_TRANSMIT_AND_RECEIVE, MASTER_TRANSMIT_AND_CHECK, MASTER_TRANSMIT_ONLY, MASTER_RECEIVE_ONLY, MASTER_CHECK_ONLY,
SLAVE_TRANSMIT_AND_RECEIVE, SLAVE_TRANSMIT_AND_CHECK, SLAVE_TRANSMIT_ONLY, SLAVE_RECEIVE_ONLY, SLAVE_CHECK_ONLY);
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 32;
--===============================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--===============================================================================================
type t_vvc_cmd_record is record
-- VVC dedicated fields
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
data_exp : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
-- Common VVC fields (Used by td_vvc_framework_common_methods_pkg procedures, and thus mandatory)
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued; -- QUEUED/IMMEDIATE
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
data => (others => '0'),
data_exp => (others => '0'),
-- Common VVC fields
operation => NO_OPERATION,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_COMMAND_TYPE,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
alert_level => failure,
delay => 0 ns,
quietness => NON_QUIET
);
--===============================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--===============================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--===============================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>, natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1));
end package vvc_cmd_pkg;
--=================================================================================================
--=================================================================================================
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
| mit | e5951c801a753eef44135ed073502076 | 0.457171 | 5.091822 | false | false | false | false |
simoesusp/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE70/KEYCONST.vhd | 4 | 3,379 | -- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: KEYCONST.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 10.1 Build 153 11/29/2010 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY KEYCONST IS
PORT
(
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END KEYCONST;
ARCHITECTURE SYN OF keyconst IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(7 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "LPM_CONSTANT",
lpm_width => 8
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL KEYCONST.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL KEYCONST.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL KEYCONST.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL KEYCONST.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL KEYCONST_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| gpl-3.0 | 33007c83a6e1ec3a8ddeee25693d982d | 0.642202 | 3.861714 | false | false | false | false |
simoesusp/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE70/dec_keyboard.vhd | 3 | 5,375 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY dec_keyboard IS
PORT( hex_bus : IN STD_LOGIC_VECTOR(7 downto 0);
scan_rd : IN STD_LOGIC;
clk : IN STD_LOGIC;
bin_digit : OUT STD_LOGIC_VECTOR(7 downto 0)
);
END dec_keyboard;
-------------------------- -- ------------------------------------
ARCHITECTURE a OF dec_keyboard IS
signal f, f2, f3, state : STD_LOGIC;
signal cc : STD_LOGIC_VECTOR(1 downto 0);
BEGIN
------------------------ -- ----------------------------------------
PROCESS (f3, hex_bus)
variable saida : STD_LOGIC_VECTOR (7 downto 0);
BEGIN
if(f3'EVENT AND f3='1') then
if(cc = "00") then
cc <= "01";
end if;
if( (cc = "01") and (hex_bus = x"F0") ) then
cc <= "10";
end if;
if(cc = "10") then
cc <= "00";
end if;
case hex_bus is --bloco das teclas normais (n�o e' case sensitive)
when x"1c" => saida := x"41"; --A
when x"32" => saida := x"42"; --B
when x"21" => saida := x"43"; --C
when x"23" => saida := x"44"; --D
when x"24" => saida := x"45"; --E
when x"2b" => saida := x"46"; --F
when x"34" => saida := x"47"; --G
when x"33" => saida := x"48"; --H
when x"43" => saida := x"49"; --I
when x"3b" => saida := x"4a"; --J
when x"42" => saida := x"4b"; --K
when x"4b" => saida := x"4c"; --L
when x"3a" => saida := x"4d"; --M
when x"31" => saida := x"4e"; --N
when x"44" => saida := x"4f"; --O
when x"4d" => saida := x"50"; --P
when x"15" => saida := x"51"; --Q
when x"2d" => saida := x"52"; --R
when x"1b" => saida := x"53"; --S
when x"2c" => saida := x"54"; --T
when x"3c" => saida := x"55"; --U
when x"2a" => saida := x"56"; --V
when x"1d" => saida := x"57"; --W
when x"22" => saida := x"58"; --X
when x"35" => saida := x"59"; --Y
when x"1a" => saida := x"5a"; --Z
when x"29" => saida := x"20"; --space
when x"66" => saida := x"08"; --backspace
when x"5a" => saida := x"0d"; --enter
when x"12" => saida := x"0e"; --shift esquerdo
when x"59" => saida := x"0f"; --shift direito
when x"14" => saida := x"fd"; --ctrl Codigo Inventado
when x"11" => saida := x"fe"; --alt Codigo Inventado
when x"0d" => saida := x"09"; --tab
when x"76" => saida := x"1b"; --ESC
when x"41" => saida := x"3c"; -- <
when x"49" => saida := x"3e"; -- >
when x"61" => saida := x"5c"; -- \
when x"4a" => saida := x"3f"; -- ?
when x"51" => saida := x"2f"; -- /
when x"4c" => saida := x"3b"; -- ;
when x"52" => saida := x"7e"; -- ~
when x"5d" => saida := x"5d"; -- ]
when x"54" => saida := x"60"; -- `
when x"5b" => saida := x"5b"; -- [
when x"69" => saida := x"e1"; --num1 Codigo Inventado
when x"72" => saida := x"e2"; --num2 Codigo Inventado
when x"7a" => saida := x"e3"; --num3 Codigo Inventado
when x"6b" => saida := x"e4"; --num4 Codigo Inventado
when x"73" => saida := x"e5"; --num5 Codigo Inventado
when x"74" => saida := x"e6"; --num6 Codigo Inventado
when x"6c" => saida := x"e7"; --num7 Codigo Inventado
when x"75" => saida := x"e8"; --num8 Codigo Inventado
when x"7d" => saida := x"e9"; --num9 Codigo Inventado
when x"16" => saida := x"31"; --1
when x"1e" => saida := x"32"; --2
when x"26" => saida := x"33"; --3
when x"25" => saida := x"34"; --4
when x"2e" => saida := x"35"; --5
when x"36" => saida := x"36"; --6
when x"3d" => saida := x"37"; --7
when x"3e" => saida := x"38"; --8
when x"46" => saida := x"39"; --9
when x"45" => saida := x"30"; --0
when x"05" => saida := x"f1"; --F1 Codigo Inventado
when x"06" => saida := x"f2"; --F2 Codigo Inventado
when x"04" => saida := x"f3"; --F3 Codigo Inventado
when x"0C" => saida := x"f4"; --F4 Codigo Inventado
when x"03" => saida := x"f5"; --F5 Codigo Inventado
when x"0B" => saida := x"f6"; --F6 Codigo Inventado
when x"83" => saida := x"f7"; --F7 Codigo Inventado
when x"0A" => saida := x"f8"; --F8 Codigo Inventado
when x"01" => saida := x"f9"; --F9 Codigo Inventado
when x"09" => saida := x"fa"; --F10 Codigo Inventado
when x"78" => saida := x"fb"; --F11 Codigo Inventado
when x"07" => saida := x"fc"; --F12 Codigo Inventado
when others => saida := x"ff"; -- Se nao for nenhum desses, responde FF
end case;
if( (saida > x"40") AND (saida < x"5b") ) then -- Isso transfora as letras maiusculas em minusculas
saida := saida + x"20";
end if;
if( (cc = "00") OR (cc = "01") ) then
bin_digit <= saida;
else
bin_digit <= x"ff";
end if;
end if;
END PROCESS;
------------------- -- ---------------------------
PROCESS (f2, scan_rd)
BEGIN
if(f2='0') then
if(scan_rd'EVENT AND scan_rd='1') then
f<='1';
end if;
else
f<='0';
end if;
END PROCESS;
----------------- -- -------------------------------
PROCESS
BEGIN
WAIT UNTIL (clk'EVENT AND clk='1');
if(f='1') then
case state is
when '0' =>
f3 <= '1';
state <= '1';
when '1' =>
f3 <= '0';
f2 <= '1';
state <= '0';
end case;
else
f2 <='0';
end if;
END PROCESS;
--------------- -- ----------------------------------
END a;
| gpl-3.0 | 5a49fc7d16cf4b3ba7844bd331906134 | 0.472548 | 2.77818 | false | false | false | false |
ashtonchase/logic_analyzer | test/capture_ctrl+storage_tb.vhd | 1 | 6,671 | -------------------------------------------------------------------------------
-- Title : Testbench for design "capture_ctrl" and "storage"
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : capture_ctrl+storage_tb.vhd
-- Created : 2016-03-11
-- Last update: 2016-03-11
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: Functional testbench for the integeration of the capture
-- control block and the storage FIFO.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-----------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-03-11 1.0 ashton Created
-------------------------------------------------------------------------------
USE std.textio.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
---------------------------------------------
ENTITY capture_ctrl_storage_tb IS
END ENTITY capture_ctrl_storage_tb;
-------------------------------------------------------------------------------
ARCHITECTURE acj_func_test OF capture_ctrl_storage_tb IS
-- component generics
CONSTANT DATA_WIDTH : POSITIVE RANGE 1 TO 32 := 8;
-- component ports
SIGNAL rst : STD_LOGIC := '1';
SIGNAL din : STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL armed : STD_LOGIC;
SIGNAL triggered : STD_LOGIC;
SIGNAL rst_cmd : STD_LOGIC := '0';
SIGNAL arm_cmd : STD_LOGIC := '0';
SIGNAL sample_enable : STD_LOGIC := '0';
SIGNAL sample_cnt_rst : STD_LOGIC;
SIGNAL read_cnt_4x : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := (OTHERS => '1');-- := STD_LOGIC_VECTOR(to_unsigned(1000, 16));
SIGNAL par_trig_msk : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := X"FE_6B_28_40";
SIGNAL par_trig_val : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL capture_rdy : STD_LOGIC;
--
SIGNAL in_fifo_tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL in_fifo_tvalid : STD_LOGIC;
SIGNAL in_fifo_tlast : STD_LOGIC;
SIGNAL in_fifo_tready : STD_LOGIC;
SIGNAL in_fifo_tfull : STD_LOGIC;
SIGNAL in_fifo_tempty : STD_LOGIC;
SIGNAL in_fifo_tflush : STD_LOGIC;
--
SIGNAL out_fifo_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL out_fifo_tvalid : STD_LOGIC;
SIGNAL out_fifo_tlast : STD_LOGIC;
SIGNAL out_fifo_tready : STD_LOGIC;
-- clock
SIGNAL Clk : STD_LOGIC := '1';
BEGIN -- ARCHITECTURE acj_func_test
-- component instantiation
DUT : ENTITY work.capture_ctrl
GENERIC MAP (
DATA_WIDTH => DATA_WIDTH)
PORT MAP (
clk => clk,
rst => rst,
din => din,
armed => armed,
triggered => triggered,
rst_cmd => rst_cmd,
arm_cmd => arm_cmd,
--sample_enable => sample_enable,
sample_cnt_rst => sample_cnt_rst,
delay_cnt_4x => read_cnt_4x,
read_cnt_4x => read_cnt_4x,
par_trig_msk => par_trig_msk,
par_trig_val => par_trig_val,
capture_rdy => capture_rdy,
--
fifo_tdata => in_fifo_tdata,
fifo_tvalid => in_fifo_tvalid,
fifo_tlast => in_fifo_tlast,
fifo_tready => in_fifo_tready,
fifo_tfull => in_fifo_tfull,
fifo_tempty => in_fifo_tempty,
fifo_aresetn => in_fifo_tflush);
sample_storage_block : ENTITY work.storage
GENERIC MAP (
FIFO_SIZE => 2**18)
PORT MAP (
clk => clk,
reset => rst,
--
in_fifo_tdata => in_fifo_tdata,
in_fifo_tvalid => in_fifo_tvalid,
in_fifo_tlast => in_fifo_tlast,
in_fifo_tready => in_fifo_tready,
in_fifo_tfull => in_fifo_tfull,
in_fifo_tempty => in_fifo_tempty,
in_fifo_tflush => in_fifo_tflush,
--
out_fifo_tdata => out_fifo_tdata,
out_fifo_tvalid => out_fifo_tvalid,
out_fifo_tlast => out_fifo_tlast,
out_fifo_tready => out_fifo_tready);
rst <= '0' AFTER 5 US;
-- clock generation
Clk <= NOT Clk AFTER 2 NS;
-- waveform generation
WaveGen_Proc : PROCESS
BEGIN
-- insert signal assignments here
WAIT UNTIL rst = '0';
WAIT UNTIL capture_rdy='1';
WAIT UNTIL rising_edge(clk);
arm_cmd <= '1';
WAIT UNTIL rising_edge(clk);
arm_cmd <= '0';
WAIT;
END PROCESS WaveGen_Proc;
din_gen : PROCESS (clk) IS
BEGIN -- PROCESS din_gen
IF rising_edge(clk) THEN -- rising clock edge
IF rst = '1' THEN -- synchronous reset (active high)
din <= (OTHERS => '0');
ELSE
din <= STD_LOGIC_VECTOR(UNSIGNED(din)+1);
END IF;
END IF;
END PROCESS din_gen;
PROCESS (armed) IS
BEGIN -- PROCESS
IF rising_edge(armed) THEN
REPORT "system has armed" SEVERITY NOTE;
END IF;
END PROCESS;
PROCESS (triggered) IS
BEGIN -- PROCESS
IF rising_edge(triggered) THEN
REPORT "system has triggered" SEVERITY NOTE;
ASSERT din = X"40" REPORT "system triggered on incorrect value" SEVERITY ERROR;
END IF;
END PROCESS;
PROCESS IS
BEGIN -- PROCESS
WAIT UNTIL falling_edge(rst);
WAIT FOR 1 US;
out_fifo_tready <= '1';
WAIT;
END PROCESS;
END ARCHITECTURE acj_func_test;
-------------------------------------------------------------------------------
------------------------------------------------
| gpl-2.0 | 0f98500d7eea03ffc3a4ae9cfedb6521 | 0.520612 | 4.050395 | false | false | false | false |
simoesusp/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE70/KB_RECEIVER.vhd | 4 | 2,013 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY KB_RECEIVER IS
PORT( CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
KBCLK : IN STD_LOGIC;
KBDATA : IN STD_LOGIC;
KEYSTATE : OUT STD_LOGIC;
KEY : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
EXTENDED : OUT STD_LOGIC
);
END KB_RECEIVER;
ARCHITECTURE main OF KB_RECEIVER IS
SIGNAL KBCLKF : STD_LOGIC;
BEGIN
PROCESS(KBCLKF, RST)
VARIABLE REC_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE ITERATOR : INTEGER RANGE 0 TO 10;
VARIABLE UNPRESSING : STD_LOGIC;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
ITERATOR := 0;
UNPRESSING := '0';
KEY <= x"FF";
KEYSTATE <= '0';
EXTENDED <= '0';
ELSIF(KBCLKF'EVENT AND KBCLKF = '0') THEN
CASE STATE IS
WHEN x"0" =>
KEYSTATE <= '1';
STATE := x"1";
-- carrega rec_data com 8 bits vindos do teclado
-- cada bit chega em um pulso do clock
WHEN x"1" =>
REC_DATA(ITERATOR) := KBDATA;
ITERATOR := ITERATOR + 1;
IF(ITERATOR = 8) THEN
STATE := x"2";
END IF;
WHEN x"2" =>
IF(REC_DATA = x"E0") THEN
EXTENDED <= '1';
ELSIF(REC_DATA = x"F0") THEN
UNPRESSING := '1';
ELSIF(UNPRESSING = '1') THEN
UNPRESSING := '0';
KEYSTATE <= '0';
EXTENDED <= '0';
KEY <= x"FF";
ELSE
KEY <= REC_DATA;
END IF;
ITERATOR := 0;
STATE := x"3";
WHEN x"3" =>
STATE := x"0";
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
PROCESS(CLK)
VARIABLE CLK_FILTER : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF(CLK'EVENT AND CLK = '1') THEN
CLK_FILTER(6 DOWNTO 0) := CLK_FILTER(7 DOWNTO 1); -- shifta para a direita
CLK_FILTER(7) := KBCLK;
IF(CLK_FILTER = "11111111") THEN
KBCLKF <= '1';
ELSIF(CLK_FILTER = "00000000") THEN
KBCLKF <= '0';
END IF;
END IF;
END PROCESS;
END main; | gpl-3.0 | 42b4612222f745d9d5490f9d5a7529c6 | 0.563835 | 2.795833 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Processor_NI/uart_synth.vhd | 3 | 10,243 | ---------------------------------------------------------------------
-- TITLE: Synthesizable UART.
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the UART.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * added a memory mapped register for counter value
-- * added necessary signals for the above mentioned register to the interface!
-- * COUNT_VALUE is replaced with count_value_sig which comes from the above mentioned register
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.mlite_pack.all;
entity uart is
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic;
reg_enable : in std_logic;
reg_write_byte_enable : in std_logic_vector(3 downto 0);
reg_address : in std_logic_vector(31 downto 2);
reg_data_write : in std_logic_vector(31 downto 0);
reg_data_read : out std_logic_vector(31 downto 0)
);
end; --entity uart
architecture logic of uart is
signal delay_write_reg : std_logic_vector(9 downto 0);
signal bits_write_reg : std_logic_vector(3 downto 0);
signal data_write_reg : std_logic_vector(8 downto 0);
signal delay_read_reg : std_logic_vector(9 downto 0);
signal bits_read_reg : std_logic_vector(3 downto 0);
signal data_read_reg : std_logic_vector(7 downto 0);
signal data_save_reg : std_logic_vector(17 downto 0);
signal busy_write_sig : std_logic;
signal count_value_reg_in, count_value_reg: std_logic_vector(31 downto 0);
signal old_address : std_logic_vector(31 downto 2);
signal count_value_sig : std_logic_vector(9 downto 0);
begin
-- added by siavoosh payandeh azad
update_count_value: process(count_value_reg, reg_data_write, reg_write_byte_enable, reg_address, reg_enable)begin
count_value_reg_in <= count_value_reg ;
if reg_enable = '1' and reg_address = uart_count_value_address then
if reg_write_byte_enable(0) = '1' then
count_value_reg_in(7 downto 0) <= reg_data_write(7 downto 0);
end if;
if reg_write_byte_enable(1) = '1' then
count_value_reg_in(15 downto 8) <= reg_data_write(15 downto 8);
end if;
if reg_write_byte_enable(2) = '1' then
count_value_reg_in(23 downto 16) <= reg_data_write(23 downto 16);
end if;
if reg_write_byte_enable(3) = '1' then
count_value_reg_in(31 downto 24) <= reg_data_write(31 downto 24);
end if;
end if;
end process;
process(count_value_reg, old_address) begin
if old_address = uart_count_value_address then
reg_data_read <= count_value_reg;
else
reg_data_read <= (others => 'U');
end if;
end process;
process(clk, reset, count_value_reg_in, reg_address)begin
if reset = '1' then
old_address <= (others => '0');
count_value_reg <= (others => '0');
elsif rising_edge(clk) then
old_address <= reg_address;
count_value_reg <= count_value_reg_in;
end if;
end process;
count_value_sig <= count_value_reg(9 downto 0);
-- end of updates by Siavoosh Payandeh Azad
uart_proc: process(clk, reset, enable_read, enable_write, data_in,
data_write_reg, bits_write_reg, delay_write_reg,
data_read_reg, bits_read_reg, delay_read_reg,
data_save_reg,
busy_write_sig, uart_read)
-----------------------------------------------
--- MUST BE EDITED BASED ON THE FREQUENCY! ----
-----------------------------------------------
-- constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
-- "0100011110"; --33MHz/2/57600Hz = 0x11e
-- "1101100100"; --50MHz/57600Hz = 0x364
-- "0110110010"; --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2
-- "0011011001"; --12.5MHz/57600Hz = 0xd9
-- "0000000100"; --for debug (shorten read_value_reg)
begin
if reset = '1' then
data_write_reg <= ZERO(8 downto 1) & '1';
bits_write_reg <= "0000";
delay_write_reg <= ZERO(9 downto 0);
data_read_reg <= ZERO(7 downto 0);
bits_read_reg <= "0000";
delay_read_reg <= ZERO(9 downto 0);
data_save_reg <= ZERO(17 downto 0);
elsif rising_edge(clk) then
--Write UART
if bits_write_reg = "0000" then --nothing left to write?
if enable_write = '1' then
delay_write_reg <= ZERO(9 downto 0); --delay before next bit
bits_write_reg <= "1010"; --number of bits to write
data_write_reg <= data_in & '0'; --remember data & start bit
end if;
else
--if delay_write_reg /= COUNT_VALUE then
if delay_write_reg /= count_value_sig then
delay_write_reg <= delay_write_reg + 1; --delay before next bit
else
delay_write_reg <= ZERO(9 downto 0); --reset delay
bits_write_reg <= bits_write_reg - 1; --bits left to write
data_write_reg <= '1' & data_write_reg(8 downto 1);
end if;
end if;
--Read UART
if delay_read_reg = ZERO(9 downto 0) then --done delay for read?
if bits_read_reg = "0000" then --nothing left to read?
if uart_read = '0' then --wait for start bit
--delay_read_reg <= '0' & COUNT_VALUE(9 downto 1); --half period
delay_read_reg <= '0' & count_value_sig(9 downto 1); --half period
bits_read_reg <= "1001"; --bits left to read
end if;
else
--delay_read_reg <= COUNT_VALUE; --initialize delay
delay_read_reg <= count_value_sig; --initialize delay
bits_read_reg <= bits_read_reg - 1; --bits left to read
data_read_reg <= uart_read & data_read_reg(7 downto 1);
end if;
else
delay_read_reg <= delay_read_reg - 1; --delay
end if;
--Control character buffer
--if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
if bits_read_reg = "0000" and delay_read_reg = count_value_sig then
if data_save_reg(8) = '0' or
(enable_read = '1' and data_save_reg(17) = '0') then
--Empty buffer
data_save_reg(8 downto 0) <= '1' & data_read_reg;
else
--Second character in buffer
data_save_reg(17 downto 9) <= '1' & data_read_reg;
if enable_read = '1' then
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if;
elsif enable_read = '1' then
data_save_reg(17) <= '0'; --data_available
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if; --rising_edge(clk)
uart_write <= data_write_reg(0);
if bits_write_reg /= "0000"
-- Comment out the following line for full UART simulation (much slower)
--and log_file = "UNUSED"
then
busy_write_sig <= '1';
else
busy_write_sig <= '0';
end if;
busy_write <= busy_write_sig;
data_avail <= data_save_reg(8);
data_out <= data_save_reg(7 downto 0);
end process; --uart_proc
-- synthesis_off
uart_logger:
if log_file /= "UNUSED" generate
uart_proc: process(clk, enable_write, data_in)
file store_file : text open write_mode is log_file;
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if rising_edge(clk) and busy_write_sig = '0' then
if enable_write = '1' then
index := conv_integer(data_in(6 downto 0));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
--The following line may have to be commented out for synthesis
writeline(store_file, hex_file_line);
line_length := 0;
end if;
end if; --uart_sel
end if; --rising_edge(clk)
end process; --uart_proc
end generate; --uart_logger
-- synthesis_on
--
-- -- synthesis_off
-- uart_logger:
-- if log_file /= "UNUSED" generate
-- uart_proc: process(clk, enable_read, data_save_reg)
-- file store_file : text open write_mode is log_file;
-- variable hex_file_line : line;
-- variable c : character;
-- variable index : natural;
-- variable line_length : natural := 0;
-- begin
-- if rising_edge(clk) and enable_read = '1' then
-- if data_save_reg(8) = '1' then
-- index := conv_integer(data_save_reg(7 downto 0));
-- if index /= 10 then
-- c := character'val(index);
-- write(hex_file_line, c);
-- line_length := line_length + 1;
-- end if;
-- if index = 10 or line_length >= 72 then
-- --The following line may have to be commented out for synthesis
-- writeline(store_file, hex_file_line);
-- line_length := 0;
-- end if;
-- end if; --uart_sel
-- end if; --rising_edge(clk)
-- end process; --uart_proc
-- end generate; --uart_logger
-- ----synthesis_on
end; --architecture logic
| gpl-3.0 | e74f6b40ec1876de0c9b1a4e5cdcd69a | 0.557161 | 3.547974 | false | false | false | false |
Joozty/FIT-VUT | 3. Semester/INP - Design of Computer Systems/1. Project/fpga/ledc8x8.vhd | 1 | 2,979 | -------------------------------------
-- vypracoval xharag01 --
-------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity ledc8x8 is
--rozhranie
port (
LED, ROW : out std_logic_vector (7 downto 0);
RESET, SMCLK : in std_logic
);
end ledc8x8;
architecture main of ledc8x8 is
-- definicia vnutornych signalov
signal riadky_pocitanie :std_logic_vector (7 downto 0) := "00000001";
signal meno :std_logic_vector (7 downto 0);
signal switch :std_logic;
signal ctr_cnt :std_logic_vector (22 downto 0);
signal ce :std_logic;
begin
-- Sem doplnte popis funkce obvodu (zakladni konstrukce VHDL jako napr.
-- prirazeni signalu, multiplexory, dekodery, procesy...).
-- DODRZUJTE ZASADY PSANI SYNTETIZOVATELNEHO VHDL UVEDENE NA WEBU:
-- http://merlin.fit.vutbr.cz/FITkit/docs/navody/synth_templates.html
-- Nezapomente take doplnit mapovani signalu rozhrani na piny FPGA
-- v souboru ledc8x8.ucf.
citac: process (RESET, SMCLK) is
begin
if (RESET = '1') then
ctr_cnt <= "00000000000000000000000";
elsif (SMCLK'event) and (SMCLK = '1') then
ctr_cnt <= ctr_cnt + '1';
end if;
end process;
switch <= ctr_cnt(22);
ce <='1' when ctr_cnt(7 downto 0) = "11111111" else '0';
pocitanieriadkov: process (SMCLK,ce,RESET)
begin
if (RESET = '1') then
riadky_pocitanie <= "00000001";
elsif (SMCLK'event and SMCLK = '1' and ce = '1') then
riadky_pocitanie <= riadky_pocitanie(0) & riadky_pocitanie(7 downto 1);
end if;
end process pocitanieriadkov;
dekoder: process (riadky_pocitanie, switch) is
begin
case (riadky_pocitanie) is
--prvy riadok
when "00000001" =>
if switch='0' then
meno <= "11111111";
else
meno <= "11111111";
end if;
--druhy riadok
when "00000010" =>
if switch='0' then
meno <= "11000011";
else
meno <= "11011011";
end if;
--treti riadok
when "00000100" =>
if switch='0' then
meno <= "11111011";
else
meno <= "11011011";
end if;
--stvrty riadok
when "00001000" =>
if switch='0' then
meno <= "11111011";
else
meno <= "11000011";
end if;
--piaty riadok
when "00010000" =>
if switch='0' then
meno <= "11011011";
else
meno <= "11011011";
end if;
--siesty riadok
when "00100000" =>
if switch='0' then
meno <= "11011011";
else
meno <= "11011011";
end if;
--siedmy riadok
when "01000000" =>
if switch='0' then
meno <= "11000011";
else
meno <= "11011011";
end if;
--osmy riadok
when "10000000" =>
if switch='0' then
meno <= "11111111";
else
meno <= "11111111";
end if;
when others =>
meno <= "00000000";
end case;
end process;
multiplexor: for i in 0 to 7 generate
ROW(i) <= riadky_pocitanie(i);
LED(i) <= meno(i);
end generate;
end main;
--------------------
--koniec programu --
--------------------
| gpl-3.0 | a5df8e405dcc718d7dce3cb60df79e66 | 0.603223 | 2.926326 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/SIB_mux_pre_FCX_SELgate.vhd | 3 | 4,908 | --Copyright (C) 2017 Konstantin Shibin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SIB_mux_pre_FCX_SELgate is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
toF : out STD_LOGIC; -- To F flag of the upper hierarchical level
toC : out STD_LOGIC; -- To C flag of the upper hierarchical level
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC; -- ScanOutPort
fromF : in STD_LOGIC; -- From an OR of all F flags in the underlying network segment
fromC : in STD_LOGIC -- From an AND of all C flags in the underlying network segment
);
end SIB_mux_pre_FCX_SELgate;
architecture SIB_mux_pre_FCX_arch of SIB_mux_pre_FCX_SELgate is
component ScanRegister_for_SIBFCX is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0);
ue_mux_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end component;
component ScanMux is
Generic (ControlSize : positive);
Port ( ScanMux_in : in STD_LOGIC_VECTOR((2**ControlSize)-1 downto 0);
SelectedBy : in STD_LOGIC_VECTOR(ControlSize-1 downto 0);
ScanMux_out : out STD_LOGIC);
end component;
signal SIBmux_out : STD_LOGIC;
signal SR_so : STD_LOGIC;
signal SR_do : STD_LOGIC_VECTOR (3 downto 0);
signal SR_ci : STD_LOGIC_VECTOR (3 downto 0);
signal sr_update_mux_out : STD_LOGIC_VECTOR (3 downto 0);
signal C_sync, F_sync : STD_LOGIC;
signal C_sync_first, F_sync_first : STD_LOGIC;
signal F_sync_delayed_copy, sticky_f_posedge : STD_LOGIC;
begin
SO <= SR_so; -- Source SR
toCE <= SEL and SR_do(3) and CE;
toSE <= SEL and SR_do(3) and SE;
toUE <= SEL and SR_do(3) and UE;
toSEL <= SEL and SR_do(3); -- SEL & S bit
toRST <= RST;
toTCK <= TCK;
toSI <= SI; -- Source SI
SR_ci(3) <= SR_do(3); -- Sxcf
SR_ci(2) <= SR_do(2); -- sXcf
SR_ci(1) <= C_sync; -- sxCf
SR_ci(0) <= sticky_f_posedge; -- sxcF
toF <= fromF and SR_do(2); -- F flag from lower levels AND X bit
toC <= fromC or not SR_do(2); -- C flag from lower levels OR NOT X bit
f_edge_detector : process (TCK, RST)
begin
if RST = '1' then
sticky_f_posedge <= '0';
elsif TCK'event and TCK = '0' then
if F_sync_delayed_copy = '0' and F_sync = '1' then -- edge detector
sticky_f_posedge <= '1';
elsif UE = '1' and SEL = '1' and sr_update_mux_out(0) = '0' then -- clear sticky F flag when F is updated with 0
sticky_f_posedge <= '0';
end if;
end if;
end process; -- f_edge_detector
synchronizer : process( TCK )
begin
if TCK'event and TCK = '0' then
F_sync_first <= fromF;
F_sync <= F_sync_first;
F_sync_delayed_copy <= F_sync;
C_sync_first <= fromC;
C_sync <= C_sync_first;
end if ;
end process ; -- synchronizer
SR : ScanRegister_for_SIBFCX
Generic map (Size => 4,
BitOrder => "MSBLSB", -- MSBLSB / LSBMSB
SOSource => 0,
ResetValue => "0110") -- ResetValue S=0, X=1, C=1, F=0
Port map ( SI => SIBmux_out, -- ScanInSource SIBmux_out
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SR_so,
CaptureSource => SR_ci, -- CaptureSource SR
ScanRegister_out => SR_do,
ue_mux_out => sr_update_mux_out);
SIBmux : ScanMux
Generic map ( ControlSize => 1)
Port map ( ScanMux_in(0) => SI, -- 1'b0 : SI
ScanMux_in(1) => fromSO, -- 1'b1 : fromSO
SelectedBy => SR_do(3 downto 3), --SelectedBy SR
ScanMux_out => SIBmux_out);
end SIB_mux_pre_FCX_arch; | gpl-3.0 | b6d097a043f731dda2fee575ac683c70 | 0.552975 | 3.523331 | false | false | false | false |
kiwih/subleq-vhdl | core.vhd | 1 | 2,690 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
--A single-cycle core for running a one-instruction computer
--Instructions are 24 bits
--[00000000] [00000000] [00000000]
-- A B C
--Executes
----(1) [B] = [B] - [A]
----(2) if [B] - [A] <= 0 GOTO C
entity core is
generic(
ADDR_SIZE : integer := 8;
INSTRUCTION_SIZE : integer := 24; --should be 3x ADDR_SIZE
DATA_SIZE: integer := 16
);
port(
CLK : in std_logic;
RESET : in std_logic;
INSTRUCTION_MEMORY_ADDR : out std_logic_vector(ADDR_SIZE - 1 downto 0);
INSTRUCTION_MEMORY_DATA_OUT: in std_logic_vector(INSTRUCTION_SIZE - 1 downto 0);
DATA_MEMORY_ADDR_A : out std_logic_vector(ADDR_SIZE - 1 downto 0);
DATA_MEMORY_DATA_OUT_A : in std_logic_vector(DATA_SIZE - 1 downto 0);
DATA_MEMORY_ADDR_B : out std_logic_vector(ADDR_SIZE - 1 downto 0);
DATA_MEMORY_DATA_OUT_B : in std_logic_vector(DATA_SIZE - 1 downto 0);
DATA_MEMORY_DATA_IN_B : out std_logic_vector(DATA_SIZE - 1 downto 0);
DATA_MEMORY_WRITE_EN_B : out std_logic
);
end entity core;
architecture beh of core is
signal pc : std_logic_vector(ADDR_SIZE - 1 downto 0) := (others => '0');
signal current_instruction : std_logic_vector(INSTRUCTION_SIZE - 1 downto 0);
signal op_a : std_logic_vector(INSTRUCTION_SIZE/3 - 1 downto 0);
signal op_b : std_logic_vector(INSTRUCTION_SIZE/3 - 1 downto 0);
signal op_c : std_logic_vector(INSTRUCTION_SIZE/3 - 1 downto 0);
signal data_a : std_logic_vector(DATA_SIZE - 1 downto 0);
signal data_b : std_logic_vector(DATA_SIZE - 1 downto 0);
signal data_out : std_logic_vector(DATA_SIZE - 1 downto 0);
begin
INSTRUCTION_MEMORY_ADDR <= pc;
current_instruction <= INSTRUCTION_MEMORY_DATA_OUT;
op_c <= current_instruction(1 * INSTRUCTION_SIZE/3 - 1 downto 0 * INSTRUCTION_SIZE/3);
op_b <= current_instruction(2 * INSTRUCTION_SIZE/3 - 1 downto 1 * INSTRUCTION_SIZE/3);
op_a <= current_instruction(3 * INSTRUCTION_SIZE/3 - 1 downto 2 * INSTRUCTION_SIZE/3);
-- op_c <= current_instruction(7 downto 0);
-- op_b <= current_instruction(15 downto 8);
-- op_a <= current_instruction(23 downto 16);
DATA_MEMORY_ADDR_A <= op_a;
DATA_MEMORY_ADDR_B <= op_b;
DATA_MEMORY_WRITE_EN_B <= '1';
DATA_MEMORY_DATA_IN_B <= data_out;
data_a <= DATA_MEMORY_DATA_OUT_A;
data_b <= DATA_MEMORY_DATA_OUT_B;
data_out <= data_b - data_a;
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
pc <= (others => '0');
elsif (data_b - data_a) <= 0 then
pc <= op_c;
else
pc <= pc + 1;
end if;
end if;
end process;
end architecture; | mit | 544dcdd3052291df26e5494890f7df1f | 0.644981 | 2.747702 | false | false | false | false |
AndyMcC0/UVVM_All | bitvis_uart/src/uart.vhd | 1 | 3,101 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.uart_pif_pkg.all;
entity uart is
generic (
GC_START_BIT : std_logic := '0';
GC_STOP_BIT : std_logic := '1';
GC_CLOCKS_PER_BIT : integer := 16);
port(
-- DSP interface and general control signals
clk : in std_logic;
arst : in std_logic;
-- CPU interface
cs : in std_logic;
addr : in unsigned(2 downto 0);
wr : in std_logic;
rd : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0) := (others => '0');
-- UART related signals
rx_a : in std_logic;
tx : out std_logic
);
end uart;
architecture rtl of uart is
-- PIF-core interface
signal p2c : t_p2c; --
signal c2p : t_c2p; --
begin
i_uart_pif : entity work.uart_pif
port map (
arst => arst, --
clk => clk, --
-- CPU interface
cs => cs, --
addr => addr, --
wr => wr, --
rd => rd, --
wdata => wdata, --
rdata => rdata, --
--
p2c => p2c, --
c2p => c2p --
);
i_uart_core : entity work.uart_core
generic map(
GC_START_BIT => GC_START_BIT,
GC_STOP_BIT => GC_STOP_BIT,
GC_CLOCKS_PER_BIT => GC_CLOCKS_PER_BIT
)
port map (
clk => clk, --
arst => arst, --
-- PIF-core interface
p2c => p2c, --
c2p => c2p, --
-- Interrupt related signals
rx_a => rx_a, --
tx => tx
);
end rtl;
| mit | 15a7be271d44d34a51908c6a0fb45f4a | 0.437601 | 4.379944 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/ram_wrapper_65.vhd | 3 | 6,377 | ---------------------------------------------------------------------
-- TITLE: RAM wrapper
-- AUTHOR: Siavoosh Payandeh Azad
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
IJTAG_select : in std_logic;
IJTAG_clk : in std_logic;
IJTAG_reset : in std_logic;
IJTAG_enable : in std_logic;
IJTAG_write_byte_enable : in std_logic_vector(3 downto 0);
IJTAG_address : in std_logic_vector(31 downto 2);
IJTAG_data_write : in std_logic_vector(31 downto 0);
IJTAG_data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
component SHKA65_4096X32X1CM4
port(A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11 : in std_logic;
DO0,DO1,DO2,
DO3,DO4,DO5,DO6,DO7,DO8,DO9,DO10,DO11,DO12,
DO13,DO14,DO15,DO16,DO17,DO18,DO19,DO20,
DO21,DO22,DO23,DO24,DO25,DO26,DO27,DO28,
DO29,DO30,DO31 : out std_logic;
DI0,DI1,DI2,DI3,DI4,DI5,
DI6,DI7,DI8,DI9,DI10,DI11,DI12,DI13,DI14,
DI15,DI16,DI17,DI18,DI19,DI20,DI21,DI22,
DI23,DI24,DI25,DI26,DI27,DI28,DI29,DI30,
DI31,CK,WEB,DVSE,DVS0,DVS1,DVS2,CSB: in std_logic);
end component;
signal write_enable: std_logic;
signal not_clock: std_logic;
signal Mem_clk : std_logic;
signal Mem_reset : std_logic;
signal Mem_enable : std_logic;
signal Mem_write_byte_enable : std_logic_vector(3 downto 0);
signal Mem_address : std_logic_vector(31 downto 2);
signal Mem_data_write : std_logic_vector(31 downto 0);
signal Mem_data_read : std_logic_vector(31 downto 0);
begin
write_enable <= not(Mem_write_byte_enable(0) or Mem_write_byte_enable(1) or Mem_write_byte_enable(2) or Mem_write_byte_enable(3));
not_clock <= not Mem_clk;
process(IJTAG_select, clk, reset, enable, write_byte_enable, address,
data_write, Mem_data_read, IJTAG_clk, IJTAG_reset, IJTAG_enable,
IJTAG_write_byte_enable, IJTAG_address, IJTAG_data_write)
begin
case( IJTAG_select) is
when '0' =>
Mem_clk <= clk;
Mem_reset <= reset;
Mem_enable <= enable;
Mem_write_byte_enable <= write_byte_enable;
Mem_address <= address;
Mem_data_write <= data_write;
data_read <= Mem_data_read;
IJTAG_data_read <= (others =>'0');
when others =>
Mem_clk <= IJTAG_clk;
Mem_reset <= IJTAG_reset;
Mem_enable <= IJTAG_enable;
Mem_write_byte_enable <= IJTAG_write_byte_enable;
Mem_address <= IJTAG_address;
Mem_data_write <= IJTAG_data_write;
IJTAG_data_read <= Mem_data_read;
data_read <= (others =>'0');
end case;
end process;
RAM_unit: SHKA65_4096X32X1CM4
generic map (cdeFileInit => stim_file)
port map(
A0 => Mem_address(2),
A1 => Mem_address(3),
A2 => Mem_address(4),
A3 => Mem_address(5),
A4 => Mem_address(6),
A5 => Mem_address(7),
A6 => Mem_address(8),
A7 => Mem_address(9),
A8 => Mem_address(10),
A9 => Mem_address(11),
A10 => Mem_address(12),
A11 => Mem_address(13),
DO0 => Mem_data_read(0),
DO1 => Mem_data_read(1),
DO2 => Mem_data_read(2),
DO3 => Mem_data_read(3),
DO4 => Mem_data_read(4),
DO5 => Mem_data_read(5),
DO6 => Mem_data_read(6),
DO7 => Mem_data_read(7),
DO8 => Mem_data_read(8),
DO9 => Mem_data_read(9),
DO10 => Mem_data_read(10),
DO11 => Mem_data_read(11),
DO12 => Mem_data_read(12),
DO13 => Mem_data_read(13),
DO14 => Mem_data_read(14),
DO15 => Mem_data_read(15),
DO16 => Mem_data_read(16),
DO17 => Mem_data_read(17),
DO18 => Mem_data_read(18),
DO19 => Mem_data_read(19),
DO20 => Mem_data_read(20),
DO21 => Mem_data_read(21),
DO22 => Mem_data_read(22),
DO23 => Mem_data_read(23),
DO24 => Mem_data_read(24),
DO25 => Mem_data_read(25),
DO26 => Mem_data_read(26),
DO27 => Mem_data_read(27),
DO28 => Mem_data_read(28),
DO29 => Mem_data_read(29),
DO30 => Mem_data_read(30),
DO31 => Mem_data_read(31),
DI0 => Mem_data_write(0),
DI1 => Mem_data_write(1),
DI2 => Mem_data_write(2),
DI3 => Mem_data_write(3),
DI4 => Mem_data_write(4),
DI5 => Mem_data_write(5),
DI6 => Mem_data_write(6),
DI7 => Mem_data_write(7),
DI8 => Mem_data_write(8),
DI9 => Mem_data_write(9),
DI10 => Mem_data_write(10),
DI11 => Mem_data_write(11),
DI12 => Mem_data_write(12),
DI13 => Mem_data_write(13),
DI14 => Mem_data_write(14),
DI15 => Mem_data_write(15),
DI16 => Mem_data_write(16),
DI17 => Mem_data_write(17),
DI18 => Mem_data_write(18),
DI19 => Mem_data_write(19),
DI20 => Mem_data_write(20),
DI21 => Mem_data_write(21),
DI22 => Mem_data_write(22),
DI23 => Mem_data_write(23),
DI24 => Mem_data_write(24),
DI25 => Mem_data_write(25),
DI26 => Mem_data_write(26),
DI27 => Mem_data_write(27),
DI28 => Mem_data_write(28),
DI29 => Mem_data_write(29),
DI30 => Mem_data_write(30),
DI31 => Mem_data_write(31),
CK => Mem_clk,
WEB => write_enable,
DVSE => '0',
DVS0 => '0',
DVS1 => '0',
DVS2 => '0',
CSB => '0'
);
end; --architecture logic
| gpl-3.0 | d5b0ce1e676f1287d944946a8da0aafb | 0.529873 | 2.946858 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/Checkers/Control_Part_Checkers/LBDR_packet_drop_checkers/LBDR_routing_part/RTL/LBDR_packet_drop_routing_part_pseudo.vhd | 3 | 4,772 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port ( empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
packet_drop_order: out std_logic;
packet_drop_in: out std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: out std_logic;
N1_out, E1_out, W1_out, S1_out: out std_logic;
grants_out: out std_logic
);
end LBDR_packet_drop_routing_part_pseudo;
architecture behavior of LBDR_packet_drop_routing_part_pseudo is
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic;
signal grants: std_logic;
--signal packet_drop, packet_drop_in: std_logic;
--signal ReConf_FF_in, ReConf_FF_out: std_logic;
begin
grants <= grant_N or grant_E or grant_W or grant_S or grant_L;
grants_out <= grants;
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
-- Taking X1 signals to the output interface for checking with checkers
N1_out <= N1;
E1_out <= E1;
W1_out <= W1;
S1_out <= S1;
--process(clk, reset)
--begin
--if reset = '0' then
-- Rxy <= Rxy_reconf;
-- Req_N_FF <= '0';
-- Req_E_FF <= '0';
-- Req_W_FF <= '0';
-- Req_S_FF <= '0';
-- Req_L_FF <= '0';
-- Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
-- Temp_Cx <= (others => '0');
-- ReConf_FF_out <= '0';
-- reconfig_cx <= '0';
-- packet_drop <= '0';
--elsif clk'event and clk = '1' then
-- Rxy <= Rxy_in;
-- Req_N_FF <= Req_N_in;
-- Req_E_FF <= Req_E_in;
-- Req_W_FF <= Req_W_in;
-- Req_S_FF <= Req_S_in;
-- Req_L_FF <= Req_L_in;
-- ReConf_FF_out <= ReConf_FF_in;
-- Cx <= Cx_in;
-- reconfig_cx <= reconfig_cx_in;
-- Temp_Cx <= Temp_Cx_in;
-- packet_drop <= packet_drop_in;
--end if;
--end process;
-- The combionational part
process(N1, E1, W1, S1, Rxy, Cx, flit_type, dst_addr, cur_addr, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants, packet_drop) begin
packet_drop_in <= packet_drop;
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
if dst_addr = cur_addr then
Req_L_in <= '1';
else
Req_L_in <= Req_L_FF;
end if;
if ((((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0)) or
(((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1)) or
(((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2)) or
(((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3))) ='0' and
(dst_addr /= cur_addr) then
packet_drop_in <= '1';
end if;
elsif flit_type = "100" and empty = '0' and grants = '1' then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
if flit_type = "100" and empty = '0' then
if packet_drop = '1' then
packet_drop_in <= '0';
end if;
end if;
end process;
packet_drop_order <= packet_drop;
END; | gpl-3.0 | 09204b012d65e19c49904e2b174613ef | 0.560142 | 2.606226 | false | false | false | false |
simoesusp/Processador-ICMC | Software_Assembly/IR_Controller/Processor_IR_PWM_DE2_70/color_bridge.vhd | 3 | 2,640 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY COLOR_BRIDGE IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
BRG_EN : IN STD_LOGIC;
COLOR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
R : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
G : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
B : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COLOR_BRIDGE;
ARCHITECTURE main OF COLOR_BRIDGE IS
BEGIN
PROCESS(CLK, RST)
BEGIN
IF(RST = '1') THEN
R <= "0000000000";
G <= "0000000000";
B <= "0000000000";
ELSIF(CLK'EVENT AND CLK = '1') THEN
IF(BRG_EN = '1') THEN
CASE COLOR IS
--BLACK
WHEN x"0" =>
R <= "0000000000";
G <= "0000000000";
B <= "0000000000";
--DARK RED
WHEN x"1" =>
R <= "0111111111";
G <= "0000000000";
B <= "0000000000";
--DARK GREEN
WHEN x"2" =>
R <= "0000000000";
G <= "0111111111";
B <= "0000000000";
--DARK YELLOW
WHEN x"3" =>
R <= "0111111111";
G <= "0111111111";
B <= "0000000000";
--DARK BLUE
WHEN x"4" =>
R <= "0000000000";
G <= "0000000000";
B <= "0111111111";
--PURPLE
WHEN x"5" =>
R <= "0111111111";
G <= "0000000000";
B <= "0111111111";
--GREENISH BLUE
WHEN x"6" =>
R <= "0000000000";
G <= "0111111111";
B <= "0111111111";
--LIGHT GRAY
WHEN x"7" =>
R <= "1011111111";
G <= "1011111111";
B <= "1011111111";
--GRAY
WHEN x"8" =>
R <= "0111111111";
G <= "0111111111";
B <= "0111111111";
--RED
WHEN x"9" =>
R <= "1111111111";
G <= "0000000000";
B <= "0000000000";
--GREEN
WHEN x"A" =>
R <= "0000000000";
G <= "1111111111";
B <= "0000000000";
--YELLOW
WHEN x"B" =>
R <= "1111111111";
G <= "1111111111";
B <= "0000000000";
--BLUE
WHEN x"C" =>
R <= "0000000000";
G <= "0000000000";
B <= "1111111111";
--PINK
WHEN x"D" =>
R <= "1111111111";
G <= "0000000000";
B <= "1111111111";
--SKY BLUE
WHEN x"E" =>
R <= "0000000000";
G <= "1111111111";
B <= "1111111111";
--WHITE
WHEN x"F" =>
R <= "1111111111";
G <= "1111111111";
B <= "1111111111";
WHEN OTHERS =>
END CASE;
ELSE
R <= "0000000000";
G <= "0000000000";
B <= "0000000000";
END IF;
END IF;
END PROCESS;
END main;
| gpl-3.0 | 3afb8881834e1b1f692cd7a81dfc4d38 | 0.462121 | 3.161677 | false | false | false | false |
ashtonchase/logic_analyzer | test/tb_top.vhd | 1 | 8,626 | -------------------------------------------------------------------------------
-- Title : Top Level Test Bench
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : tb_top.vhd
-- Created : 2016-02-22
-- Last update: 2016-02-22
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: Testbench for la_top
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-22 0.1 henny Created UART Transmitter
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_top is
end tb_top;
architecture behav of tb_top is
signal clk : std_logic := '0';
signal rst : std_logic;
signal logic_in : std_logic_vector(31 downto 0) := x"deadbeef";
signal msg_finish : std_logic;
signal poll_count : integer;
signal poll_enable : std_logic;
signal poll_start : std_logic;
signal uart_rx : std_logic := '1';
signal uart_tx : std_logic := '1';
constant BAUD_DIVIDER : integer := 100;
-- Data type
type slv8_arr is array (natural range <>) of std_logic_vector(7 downto 0);
type cmd_record is record
mess : slv8_arr(0 to 4);
length : integer range 0 to 5;
end record cmd_record;
begin
-- LA Top instance
la_top_inst : entity work.la_top
port map (
clk => clk,
rst => rst,
--data input. default to zeros so you don't have to hook all 32 lines up.
din(31 downto 0) => logic_in,
--UART INTERFACES
uart_rx => uart_rx, -- UART Receive Data
uart_tx => uart_tx); -- UART Transmit Data
clk_proc : process
variable counter: natural range 0 to 256;
begin
clk <= '0';
wait for 5ns;
loop
wait for 5ns;
clk <= '1';
wait for 5ns;
clk <= '0';
counter:=(counter+1) mod 256;
logic_in<=std_logic_vector(to_unsigned(counter,32));
end loop;
end process clk_proc;
-------------------------------------------------------
-- Baudrate Generator
-------------------------------------------------------
output_bl : block is
signal baud_counter : integer;
signal baud_enable : std_logic;
constant c_reset : cmd_record := ((x"00", others => x"00"), 1);
constant c_run : cmd_record := ((x"01", others => x"00"), 1);
constant c_test_byte : cmd_record := ((x"A5", others => x"00"), 1);
constant c_trig_mask : cmd_record := ((x"C0", x"0C", x"00", x"00", x"00", others => x"00"), 5);
constant c_trig_val : cmd_record := ((x"C1", x"07", x"00", x"00", x"00", others => x"00"), 5);
constant c_read_cnt : cmd_record := ((x"81", x"04", x"00", x"04", x"00", others => x"00"), 5);
constant c_set_divide : cmd_record := ((x"80", x"08", x"00", x"00", x"00", others => x"00"), 5);
signal resp_to_send : cmd_record;
begin
baudrate_p : process(clk) is
begin
if rising_edge(clk) then
if rst='1' then
baud_enable <= '0';
baud_counter <= BAUD_DIVIDER-1;
else
if baud_counter=0 then
baud_enable <= '1';
baud_counter <= BAUD_DIVIDER-1;
else
baud_counter <= baud_counter - 1;
baud_enable <= '0';
end if;
end if;
end if;
end process baudrate_p;
---------------------------------------------------------------
-- Rx Control Block
---------------------------------------------------------------
status_out_p : process(clk) is
variable count : integer range -1 to 9;
variable byte_count : integer;
variable resp_count : integer;
begin
if rising_edge(clk) then
if rst='1' then
count := 8;
byte_count := 0;
uart_rx <= '1';
resp_count := 0;
msg_finish <= '1';
else
-- Where you control what messages are sent
case resp_count is
when 0 => resp_to_send <= c_reset;
when 1 => resp_to_send <= c_trig_mask;
when 2 => resp_to_send <= c_trig_val;
when 3 => resp_to_send <= c_read_cnt;
when 4 => resp_to_send <= c_set_divide;
when 5 => resp_to_send <= c_run;
when 6 => resp_to_send <= c_trig_mask;
when 7 => resp_to_send <= c_reset;
when 8 => resp_to_send <= c_reset;
when others =>
end case;
if msg_finish='0' then
if baud_enable='1' then
if count=8 then
uart_rx <= '0';
elsif count=-1 then
uart_rx <= '1';
byte_count := byte_count + 1;
count := 9;
if byte_count=resp_to_send.length then
byte_count := 0;
resp_count := resp_count+1;
msg_finish <= '1';
end if;
else
uart_rx <= resp_to_send.mess(byte_count)(7-count);
end if;
count := count-1;
end if;
else
poll_start <= '1';
if poll_enable='1' then
poll_start <= '0';
msg_finish <= '0';
end if;
end if;
end if;
end if;
end process status_out_p;
end block output_bl;
---------------------------------------------------------------
-- How often commands are sent to the LA
---------------------------------------------------------------
polling_p : process(clk) is
constant poll_max : integer := 100;
begin
if rising_edge(clk) then
if rst='1' then
poll_enable <= '0';
poll_count <= poll_max;
else
if poll_start='1' then
if poll_count=0 then
poll_enable <= '1';
poll_count <= poll_max;
else
poll_enable <= '0';
poll_count <= poll_count - 1;
end if;
else
poll_enable <= '0';
poll_count <= poll_max;
end if;
end if;
end if;
end process polling_p;
---------------------------------------------------------------
-- Main Control of Testbench
---------------------------------------------------------------
main_p : process
begin
rst <= '1';
wait for 20ns;
rst <= '0';
wait;
end process main_p;
end architecture behav; | gpl-2.0 | 88e14b8197f566179df48c007e5a226f | 0.407257 | 4.776301 | false | false | false | false |
AndyMcC0/UVVM_All | uvvm_util/src/methods_pkg.vhd | 1 | 237,364 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
use work.license_pkg.all;
use work.alert_hierarchy_pkg.all;
use work.protected_types_pkg.all;
use std.env.all;
package methods_pkg is
-- Shared variables
shared variable shared_initialised_util : boolean := false;
shared variable shared_msg_id_panel : t_msg_id_panel := C_MSG_ID_PANEL_DEFAULT;
shared variable shared_log_file_name_is_set : boolean := false;
shared variable shared_alert_file_name_is_set : boolean := false;
shared variable shared_warned_time_stamp_trunc : boolean := false;
shared variable shared_alert_attention : t_alert_attention:= C_DEFAULT_ALERT_ATTENTION;
shared variable shared_stop_limit : t_alert_counters := C_DEFAULT_STOP_LIMIT;
shared variable shared_log_hdr_for_waveview : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
shared variable shared_current_log_hdr : t_current_log_hdr;
shared variable shared_seed1 : positive;
shared variable shared_seed2 : positive;
shared variable shared_flag_array : t_sync_flag_record_array := (others => C_SYNC_FLAG_DEFAULT);
shared variable protected_semaphore : t_protected_semaphore;
shared variable protected_broadcast_semaphore : t_protected_semaphore;
shared variable protected_response_semaphore : t_protected_semaphore;
shared variable shared_uvvm_status : t_uvvm_status;
signal global_trigger : std_logic := 'L';
signal global_barrier : std_logic := 'X';
-- -- ============================================================================
-- -- Initialisation and license
-- -- ============================================================================
-- procedure initialise_util(
-- constant dummy : in t_void
-- );
--
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string
);
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME
);
-- msg_id is unused. This is a deprecated overload
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id
);
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME
);
-- msg_id is unused. This is a deprecated overload
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id
);
-- ============================================================================
-- Log-related
-- ============================================================================
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
);
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
);
procedure write_to_file (
file_name : string;
open_mode : file_open_kind;
variable my_line : inout line
);
-- Enable and Disable do not have a Scope parameter as they are only allowed from main test sequencer
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
);
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET
) ;
procedure enable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET
) ;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
);
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET
);
procedure disable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET
);
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean;
procedure set_log_destination(
constant log_destination : t_log_destination;
constant quietness : t_quietness := NON_QUIET
);
-- ============================================================================
-- Alert-related
-- ============================================================================
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure report_alert_counters(
constant order : in t_order
);
procedure report_alert_counters(
constant dummy : in t_void
);
procedure report_global_ctrl(
constant dummy : in t_void
);
procedure report_msg_id_panel(
constant dummy : in t_void
);
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
);
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
);
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural;
impure function get_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD
) return natural;
procedure increment_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
);
-- ============================================================================
-- Deprecate message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
);
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean;
function matching_widths(
value1: unsigned;
value2: unsigned
) return boolean;
function matching_widths(
value1: signed;
value2: signed
) return boolean;
-- function version of check_value (with return value)
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean ;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean ;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean ;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean ;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
-- procedure version of check_value (no return value)
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
);
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
-- Check_value_in_range
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean;
-- Procedure overloads for check_value_in_range
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
-- Check_stable
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "boolean"
);
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "slv"
);
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "unsigned"
);
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "signed"
);
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "std_logic"
);
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "integer"
);
procedure check_stable(
signal target : real;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "real"
);
impure function random (
constant length : integer
) return std_logic_vector;
impure function random (
constant VOID : t_void
) return std_logic;
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer;
impure function random (
constant min_value : real;
constant max_value : real
) return real;
impure function random (
constant min_value : time;
constant max_value : time
) return time;
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
);
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
);
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
);
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
);
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
);
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- Warning! This function should NOT be used outside the UVVM library.
-- Function is only included to support internal functionality.
-- The function can be removed without notification.
function matching_values(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean;
-- ============================================================================
-- Time consuming checks
-- ============================================================================
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
);
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
);
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
);
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
);
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
);
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
);
procedure await_change(
signal target : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "real"
);
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : real;
constant exp : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : real;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with duty cycle in time
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_time : in time
);
-- Overloaded version with clock count
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock count and duty cycle in time
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_time : in time
);
-- Overloaded version with clock enable and clock name
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock enable, clock name
-- and duty cycle in time.
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
);
-- Overloaded version with clock enable, clock name
-- and clock count
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock enable, clock name,
-- clock count and duty cycle in time.
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
);
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
);
-- ============================================================================
-- Synchronisation methods
-- ============================================================================
-- method to block a global flag with the name flag_name
procedure block_flag(
constant flag_name : in string;
constant msg : in string
);
-- method to unblock a global flag with the name flag_name
procedure unblock_flag(
constant flag_name : in string;
constant msg : in string;
signal trigger : inout std_logic
);
-- method to wait for the global flag with the name flag_name
procedure await_unblock_flag(
constant flag_name : in string;
constant timeout : in time;
constant msg : in string;
constant flag_returning : in t_flag_returning := KEEP_UNBLOCKED;
constant timeout_severity : in t_alert_level := ERROR
);
procedure await_barrier(
signal barrier_signal : inout std_logic;
constant timeout : in time;
constant msg : in string;
constant timeout_severity : in t_alert_level := ERROR
);
-------------------------------------------
-- await_semaphore_in_delta_cycles
-------------------------------------------
-- tries to lock the semaphore for C_NUM_SEMAPHORE_LOCK_TRIES in adaptations_pkg
procedure await_semaphore_in_delta_cycles(
variable semaphore : inout t_protected_semaphore
);
-------------------------------------------
-- release_semaphore
-------------------------------------------
-- releases the semaphore
procedure release_semaphore(
variable semaphore : inout t_protected_semaphore
);
end package methods_pkg;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package body methods_pkg is
constant C_BURIED_SCOPE : string := "(Util buried)";
-- The following constants are not used. Report statements in the given functions allow elaboration time messages
constant C_BITVIS_LICENSE_INITIALISED : boolean := show_license(VOID);
constant C_BITVIS_LIBRARY_INFO_SHOWN : boolean := show_uvvm_utility_library_info(VOID);
constant C_BITVIS_LIBRARY_RELEASE_INFO_SHOWN : boolean := show_uvvm_utility_library_release_info(VOID);
-- ============================================================================
-- Initialisation and license
-- ============================================================================
-- -- Executed a single time ONLY
-- procedure pot_show_license(
-- constant dummy : in t_void
-- ) is
-- begin
-- if not shared_license_shown then
-- show_license(v_trial_license);
-- shared_license_shown := true;
-- end if;
-- end;
-- -- Executed a single time ONLY
-- procedure initialise_util(
-- constant dummy : in t_void
-- ) is
-- begin
-- set_log_file_name(C_LOG_FILE_NAME);
-- set_alert_file_name(C_ALERT_FILE_NAME);
-- shared_license_shown.set(1);
-- shared_initialised_util.set(true);
-- end;
procedure pot_initialise_util(
constant dummy : in t_void
) is
variable v_minimum_log_line_width : natural := 0;
begin
if not shared_initialised_util then
shared_initialised_util := true;
if not shared_log_file_name_is_set then
set_log_file_name(C_LOG_FILE_NAME);
end if;
if not shared_alert_file_name_is_set then
set_alert_file_name(C_ALERT_FILE_NAME);
end if;
if C_ENABLE_HIERARCHICAL_ALERTS then
initialize_hierarchy;
end if;
-- Check that all log widths are valid
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_PREFIX_WIDTH + C_LOG_TIME_WIDTH + 5; -- Add 5 for spaces
if not (C_SHOW_LOG_ID or C_SHOW_LOG_SCOPE) then
v_minimum_log_line_width := v_minimum_log_line_width + 10; -- Minimum length in order to wrap lines properly
else
if C_SHOW_LOG_ID then
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_MSG_ID_WIDTH;
end if;
if C_SHOW_LOG_SCOPE then
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_SCOPE_WIDTH;
end if;
end if;
bitvis_assert(C_LOG_LINE_WIDTH >= v_minimum_log_line_width, failure, "C_LOG_LINE_WIDTH is too low. Needs to higher than " & to_string(v_minimum_log_line_width) & ". ", C_SCOPE);
--show_license(VOID);
-- if C_SHOW_uvvm_utilITY_LIBRARY_INFO then
-- show_uvvm_utility_library_info(VOID);
-- end if;
-- if C_SHOW_uvvm_utilITY_LIBRARY_RELEASE_INFO then
-- show_uvvm_utility_library_release_info(VOID);
-- end if;
end if;
end;
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
) is
begin
if line_to_be_deallocated /= NULL then
deallocate(line_to_be_deallocated);
end if;
end procedure deallocate_line_if_exists;
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string
) is
begin
case status is
when open_ok =>
null; --**** logmsg (if log is open for write)
when status_error =>
alert(tb_warning, "File: " & file_name & " is already open", "SCOPE_TBD");
when name_error =>
alert(tb_error, "Cannot create file: " & file_name, "SCOPE TBD");
when mode_error =>
alert(tb_error, "File: " & file_name & " exists, but cannot be opened in write mode", "SCOPE TBD");
end case;
end;
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME
) is
variable v_file_open_status: file_open_status;
begin
if C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME and shared_alert_file_name_is_set then
warning("alert file name already set. Setting new alert file " & file_name);
end if;
shared_alert_file_name_is_set := true;
file_close(ALERT_FILE);
file_open(v_file_open_status, ALERT_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the log file and therefore blocking subsequent set_log_file_name().
report "alert file name set: " & file_name;
end if;
end;
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id
) is
variable v_file_open_status: file_open_status;
begin
deprecate(get_procedure_name_from_instance_name(file_name'instance_name), "msg_id parameter is no longer in use. Please call this procedure without the msg_id parameter.");
set_alert_file_name(file_name);
end;
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME
) is
variable v_file_open_status: file_open_status;
begin
if C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME and shared_log_file_name_is_set then
warning("log file name already set. Setting new log file " & file_name);
end if;
shared_log_file_name_is_set := true;
file_close(LOG_FILE);
file_open(v_file_open_status, LOG_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the alert file and therefore blocking subsequent set_alert_file_name().
report "log file name set: " & file_name;
end if;
end;
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id
) is
begin
-- msg_id is no longer in use. However, can not call deprecate() since Util may not
-- have opened a log file yet. Attempting to call deprecate() when there is no open
-- log file will cause a fatal error. Leaving this alone with no message.
set_log_file_name(file_name);
end;
-- ============================================================================
-- Log-related
-- ============================================================================
impure function align_log_time(
value : time
) return string is
variable v_line : line;
variable v_value_width : natural;
variable v_result : string(1 to 50); -- sufficient for any relevant time value
variable v_result_width : natural;
variable v_delimeter_pos : natural;
variable v_time_number_width : natural;
variable v_time_width : natural;
variable v_num_initial_blanks : integer;
variable v_found_decimal_point : boolean;
begin
-- 1. Store normal write (to string) and note width
write(v_line, value, LEFT, 0, C_LOG_TIME_BASE); -- required as width is unknown
v_value_width := v_line'length;
v_result(1 to v_value_width) := v_line.all;
deallocate(v_line);
-- 2. Search for decimal point or space between number and unit
v_found_decimal_point := true; -- default
v_delimeter_pos := pos_of_leftmost('.', v_result(1 to v_value_width), 0);
if v_delimeter_pos = 0 then -- No decimal point found
v_found_decimal_point := false;
v_delimeter_pos := pos_of_leftmost(' ', v_result(1 to v_value_width), 0);
end if;
-- Potentially alert if time stamp is truncated.
if C_LOG_TIME_TRUNC_WARNING then
if not shared_warned_time_stamp_trunc then
if (C_LOG_TIME_DECIMALS < (v_value_width - 3 - v_delimeter_pos)) THEN
alert(TB_WARNING, "Time stamp has been truncated to " & to_string(C_LOG_TIME_DECIMALS) &
" decimal(s) in the next log message - settable in adaptations_pkg." &
" (Actual time stamp has more decimals than displayed) " &
"\nThis alert is shown once only.",
C_BURIED_SCOPE);
shared_warned_time_stamp_trunc := true;
end if;
end if;
end if;
-- 3. Derive Time number (integer or real)
if C_LOG_TIME_DECIMALS = 0 then
v_time_number_width := v_delimeter_pos - 1;
-- v_result as is
else -- i.e. a decimal value is required
if v_found_decimal_point then
v_result(v_value_width - 2 to v_result'right) := (others => '0'); -- Zero extend
else -- Shift right after integer part and add point
v_result(v_delimeter_pos + 1 to v_result'right) := v_result(v_delimeter_pos to v_result'right - 1);
v_result(v_delimeter_pos) := '.';
v_result(v_value_width - 1 to v_result'right) := (others => '0'); -- Zero extend
end if;
v_time_number_width := v_delimeter_pos + C_LOG_TIME_DECIMALS;
end if;
-- 4. Add time unit for full time specification
v_time_width := v_time_number_width + 3;
if C_LOG_TIME_BASE = ns then
v_result(v_time_number_width + 1 to v_time_width) := " ns";
else
v_result(v_time_number_width + 1 to v_time_width) := " ps";
end if;
-- 5. Prefix
v_num_initial_blanks := maximum(0, (C_LOG_TIME_WIDTH - v_time_width));
if v_num_initial_blanks > 0 then
v_result(v_num_initial_blanks + 1 to v_result'right) := v_result(1 to v_result'right - v_num_initial_blanks);
v_result(1 to v_num_initial_blanks) := fill_string(' ', v_num_initial_blanks);
v_result_width := C_LOG_TIME_WIDTH;
else
-- v_result as is
v_result_width := v_time_width;
end if;
return v_result(1 to v_result_width);
end function align_log_time;
-- Writes Line to a file without modifying the contents of the line
-- Not yet available in VHDL
procedure tee (
file file_handle : text;
variable my_line : inout line
) is
variable v_line : line;
begin
write (v_line, my_line.all);
writeline(file_handle, v_line);
end procedure tee;
-- Open, append/write to and close file. Also deallocates contents of the line
procedure write_to_file (
file_name : string;
open_mode : file_open_kind;
variable my_line : inout line
) is
file v_specified_file_pointer : text;
begin
file_open(v_specified_file_pointer, file_name, open_mode);
writeline(v_specified_file_pointer, my_line);
file_close(v_specified_file_pointer);
end procedure write_to_file;
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel; -- compatible with old code
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
) is
variable v_msg : line;
variable v_msg_indent : line;
variable v_msg_indent_width : natural;
variable v_info : line;
variable v_info_final : line;
variable v_log_msg_id : string(1 to C_LOG_MSG_ID_WIDTH);
variable v_log_scope : string(1 to C_LOG_SCOPE_WIDTH);
variable v_log_pre_msg_width : natural;
begin
-- Check if message ID is enabled
if (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
-- Prepare strings for msg_id and scope
v_log_msg_id := to_upper(justify(to_string(msg_id), LEFT, C_LOG_MSG_ID_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE));
if (scope = "") then
v_log_scope := justify("(non scoped)", LEFT, C_LOG_SCOPE_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
else
v_log_scope := justify(to_string(scope), LEFT, C_LOG_SCOPE_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
end if;
-- Handle actual log info line
-- First write all fields preceeding the actual message - in order to measure their width
-- (Prefix is taken care of later)
write(v_info,
return_string_if_true(v_log_msg_id, C_SHOW_LOG_ID) & -- Optional
" " & align_log_time(now) & " " &
return_string_if_true(v_log_scope, C_SHOW_LOG_SCOPE) & " "); -- Optional
v_log_pre_msg_width := v_info'length; -- Width of string preceeding the actual message
-- Handle \r as potential initial open line
if msg'length > 1 then
if C_USE_BACKSLASH_R_AS_LF and (msg(1 to 2) = "\r") then
write(v_info_final, LF); -- Start transcript with an empty line
write(v_msg, remove_initial_chars(msg, 2));
else
write(v_msg, msg);
end if;
end if;
-- Handle dedicated ID indentation.
write(v_msg_indent, to_string(C_MSG_ID_INDENT(msg_id)));
v_msg_indent_width := v_msg_indent'length;
write(v_info, v_msg_indent.all);
deallocate_line_if_exists(v_msg_indent);
-- Then add the message it self (after replacing \n with LF
if msg'length > 1 then
write(v_info, to_string(replace_backslash_n_with_lf(v_msg.all)));
end if;
deallocate_line_if_exists(v_msg);
if not C_SINGLE_LINE_LOG then
-- Modify and align info-string if additional lines are required (after wrapping lines)
wrap_lines(v_info, 1, v_log_pre_msg_width + v_msg_indent_width + 1, C_LOG_LINE_WIDTH-C_LOG_PREFIX_WIDTH);
else
-- Remove line feed character if
-- single line log/alert enabled
replace(v_info, LF, ' ');
end if;
-- Handle potential log header by including info-lines inside the log header format and update of waveview header.
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & LF);
-- also update the Log header string
shared_current_log_hdr.normal := justify(msg, LEFT, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
shared_log_hdr_for_waveview := justify(msg, LEFT, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & LF);
shared_current_log_hdr.large := justify(msg, LEFT, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
write(v_info_final, fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF);
shared_current_log_hdr.xl := justify(msg, LEFT, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
write(v_info_final, LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH))& LF & LF);
end if;
write(v_info_final, v_info.all); -- include actual info
deallocate_line_if_exists(v_info);
-- Handle rest of potential log header
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF & LF);
end if;
-- Add prefix to all lines
prefix_lines(v_info_final);
-- Write the info string to the target file
if log_file_name = "" and (log_destination = LOG_ONLY or log_destination = CONSOLE_AND_LOG) then
-- Output file specified, but file name was invalid.
alert(TB_ERROR, "log called with log_destination " & to_upper(to_string(log_destination)) & ", but log file name was empty.");
else
case log_destination is
when CONSOLE_AND_LOG =>
tee(OUTPUT, v_info_final); -- write to transcript, while keeping the line contents
-- write to file
if log_file_name = C_LOG_FILE_NAME then
-- If the log file is the default file, it is not necessary to open and close it again
writeline(LOG_FILE, v_info_final);
else
-- If the log file is a custom file name, the file will have to be opened.
write_to_file(log_file_name, open_mode, v_info_final);
end if;
when CONSOLE_ONLY =>
writeline(OUTPUT, v_info_final); -- Write to console and deallocate line
when LOG_ONLY =>
if log_file_name = C_LOG_FILE_NAME then
-- If the log file is the default file, it is not necessary to open and close it again
writeline(LOG_FILE, v_info_final);
else
-- If the log file is a custom file name, the file will have to be opened.
write_to_file(log_file_name, open_mode, v_info_final);
end if;
end case;
end if;
end if;
end;
-- Logging for multi line text. Also deallocates the text_block, for consistency.
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
) is
variable v_text_block_empty_note : string(1 to 26) := "Note: Text block was empty";
variable v_header_line : line;
variable v_log_body : line;
variable v_text_block_is_empty : boolean;
begin
if ((log_file_name = "") and ((log_destination = CONSOLE_AND_LOG) or (log_destination = LOG_ONLY))) then
alert(TB_ERROR, "log_text_block called with log_destination " & to_upper(to_string(log_destination)) & ", but log file name was empty.");
-- Check if message ID is enabled
elsif (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
v_text_block_is_empty := (text_block = NULL);
if(formatting = UNFORMATTED) then
if(not v_text_block_is_empty) then
-- Write the info string to the target file without any header, footer or indentation
case log_destination is
when CONSOLE_AND_LOG =>
tee(OUTPUT, text_block); -- Write to console, but keep text_block
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, text_block);
else
write_to_file(log_file_name, open_mode, text_block);
end if;
when CONSOLE_ONLY =>
writeline(OUTPUT, text_block); -- Write to console and deallocate text_block
when LOG_ONLY =>
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, text_block);
else
write_to_file(log_file_name, open_mode, text_block);
end if;
end case;
end if;
elsif not (v_text_block_is_empty and (log_if_block_empty = SKIP_LOG_IF_BLOCK_EMPTY)) then
-- Add and print header
write(v_header_line, LF & LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
prefix_lines(v_header_line);
-- Add header underline, body and footer
write(v_log_body, fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
if v_text_block_is_empty then
if log_if_block_empty = NOTIFY_IF_BLOCK_EMPTY then
write(v_log_body, v_text_block_empty_note); -- Notify that the text block was empty
end if;
else
write(v_log_body, text_block.all); -- include input text
end if;
write(v_log_body, LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
prefix_lines(v_log_body);
case log_destination is
when CONSOLE_AND_LOG =>
-- Write header to console
tee(OUTPUT, v_header_line);
-- Write header to file, and open/close if not default log file
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_header_line);
else
write_to_file(log_file_name, open_mode, v_header_line);
end if;
-- Write header message to specified destination
log(msg_id, msg_header, scope, msg_id_panel, CONSOLE_AND_LOG, log_file_name, append_mode);
-- Write log body to console
tee(OUTPUT, v_log_body);
-- Write log body to specified file
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_log_body);
else
write_to_file(log_file_name, append_mode, v_log_body);
end if;
when CONSOLE_ONLY =>
-- Write to console and deallocate all lines
writeline(OUTPUT, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, CONSOLE_ONLY);
writeline(OUTPUT, v_log_body);
when LOG_ONLY =>
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, LOG_ONLY);
writeline(LOG_FILE, v_log_body);
else
write_to_file(log_file_name, open_mode, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, LOG_ONLY, log_file_name, append_mode);
write_to_file(log_file_name, append_mode, v_log_body);
end if;
end case;
-- Deallocate text block to give writeline()-like behaviour
-- for formatted output
deallocate(text_block);
end if;
end if;
end;
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
) is
begin
case msg_id is
when ID_NEVER =>
null; -- Shall not be possible to enable
tb_warning("enable_log_msg() ignored for " & to_upper(to_string(msg_id)) & " (not allowed). " & add_msg_delimiter(msg), scope);
when ALL_MESSAGES =>
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := ENABLED;
end loop;
msg_id_panel(ID_NEVER) := DISABLED;
msg_id_panel(ID_BITVIS_DEBUG) := DISABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
when others =>
msg_id_panel(msg_id) := ENABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
end case;
end;
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET
) is
begin
enable_log_msg(msg_id, shared_msg_id_panel, msg, C_TB_SCOPE_DEFAULT, quietness);
end;
procedure enable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET
) is
begin
enable_log_msg(msg_id, shared_msg_id_panel, "", C_TB_SCOPE_DEFAULT, quietness);
end;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
) is
begin
case msg_id is
when ALL_MESSAGES =>
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := DISABLED;
end loop;
when others =>
msg_id_panel(msg_id) := DISABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
end case;
end;
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET
) is
begin
disable_log_msg(msg_id, shared_msg_id_panel, msg, C_TB_SCOPE_DEFAULT, quietness);
end;
procedure disable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET
) is
begin
disable_log_msg(msg_id, shared_msg_id_panel, "", C_TB_SCOPE_DEFAULT, quietness);
end;
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean is
begin
if msg_id_panel(msg_id) = ENABLED then
return true;
else
return false;
end if;
end;
procedure set_log_destination(
constant log_destination : t_log_destination;
constant quietness : t_quietness := NON_QUIET
) is
begin
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "Changing log destination to " & to_string(log_destination) & ". Was " & to_string(shared_default_log_destination) & ". ", C_TB_SCOPE_DEFAULT);
end if;
shared_default_log_destination := log_destination;
end;
-- ============================================================================
-- Alert-related
-- ============================================================================
-- Shared variable for all the alert counters for different attention
shared variable protected_alert_attention_counters : t_protected_alert_attention_counters;
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
variable v_msg : line; -- msg after pot. replacement of \n
variable v_info : line;
constant C_ATTENTION : t_attention := get_alert_attention(alert_level);
begin
if alert_level /= NO_ALERT then
pot_initialise_util(VOID); -- Only executed the first time called
if C_ENABLE_HIERARCHICAL_ALERTS then
-- Call the hierarchical alert function
hierarchical_alert(alert_level, to_string(msg), to_string(scope), C_ATTENTION);
else
-- Perform the non-hierarchical alert function
write(v_msg, replace_backslash_n_with_lf(to_string(msg)));
-- 1. Increase relevant alert counter. Exit if ignore is set for this alert type.
if get_alert_attention(alert_level) = IGNORE then
-- protected_alert_counters.increment(alert_level, IGNORE);
increment_alert_counter(alert_level, IGNORE);
else
--protected_alert_counters.increment(alert_level, REGARD);
increment_alert_counter(alert_level, REGARD);
-- 2. Write first part of alert message
-- Serious alerts need more attention - thus more space and lines
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH));
end if;
write(v_info, LF & "*** ");
-- 3. Remove line feed character (LF)
-- if single line alert enabled.
if not C_SINGLE_LINE_ALERT then
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" & LF &
justify( to_string(now, C_LOG_TIME_BASE), RIGHT, C_LOG_TIME_WIDTH) & " " & to_string(scope) & LF &
wrap_lines(v_msg.all, C_LOG_TIME_WIDTH + 4, C_LOG_TIME_WIDTH + 4, C_LOG_INFO_WIDTH));
else
replace(v_msg, LF, ' ');
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" &
justify( to_string(now, C_LOG_TIME_BASE), RIGHT, C_LOG_TIME_WIDTH) & " " & to_string(scope) &
" " & v_msg.all);
end if;
deallocate_line_if_exists(v_msg);
-- 4. Write stop message if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
write(v_info, LF & LF & "Simulator has been paused as requested after " &
to_string(get_alert_counter(alert_level)) & " " &
to_upper(to_string(alert_level)) & LF);
if (alert_level = MANUAL_CHECK) then
write(v_info, "Carry out above check." & LF &
"Then continue simulation from within simulator." & LF);
else
write(v_info, string'("*** To find the root cause of this alert, " &
"step out the HDL calling stack in your simulator. ***" & LF &
"*** For example, step out until you reach the call from the test sequencer. ***"));
end if;
end if;
-- 5. Write last part of alert message
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH) & LF & LF);
else
write(v_info, LF);
end if;
prefix_lines(v_info);
tee(OUTPUT, v_info);
tee(ALERT_FILE, v_info);
writeline(LOG_FILE, v_info);
-- 6. Stop simulation if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) then
if (get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
assert false
report "This single Failure line has been provoked to stop the simulation. See alert-message above"
severity failure;
end if;
end if;
end if;
end if;
end if;
end;
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(note, msg, scope);
end;
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_note, msg, scope);
end;
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(warning, msg, scope);
end;
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_warning, msg, scope);
end;
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(manual_check, msg, scope);
end;
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(error, msg, scope);
end;
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_error, msg, scope);
end;
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(failure, msg, scope);
end;
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_failure, msg, scope);
end;
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
if alert_level = NO_ALERT then
alert(TB_WARNING, "increment_expected_alerts not allowed for alert_level NO_ALERT. " & add_msg_delimiter(msg), scope);
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
increment_alert_counter(alert_level, EXPECT, number);
log(ID_UTIL_SETUP, "incremented expected " & to_upper(to_string(alert_level)) & "s by " & to_string(number) & ". " & add_msg_delimiter(msg), scope);
else
increment_expected_alerts(C_BASE_HIERARCHY_LEVEL, alert_level, number);
end if;
end if;
end;
-- Arguments:
-- - order = FINAL : print out Simulation Success/Fail
procedure report_alert_counters(
constant order : in t_order
) is
begin
pot_initialise_util(VOID); -- Only executed the first time called
if not C_ENABLE_HIERARCHICAL_ALERTS then
protected_alert_attention_counters.to_string(order);
else
print_hierarchical_log(order);
end if;
end;
-- This version (with the t_void argument) is kept for backwards compatibility
procedure report_alert_counters(
constant dummy : in t_void
) is
begin
report_alert_counters(FINAL); -- Default when calling this old method is order=FINAL
end;
procedure report_global_ctrl(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF GLOBAL CTRL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" IGNORE STOP_LIMIT " & LF);
for i in NOTE to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity
write(v_line, to_string(get_alert_attention(i), 7, RIGHT) & " "); -- column 1
write(v_line, to_string(integer'(get_alert_stop_limit(i)), 6, RIGHT, KEEP_LEADING_SPACE) & " " & LF); -- column 2
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
end;
procedure report_msg_id_panel(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF MSG ID PANEL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" " & justify("ID", LEFT, C_LOG_MSG_ID_WIDTH) & " Status" & LF &
" " & fill_string('-', C_LOG_MSG_ID_WIDTH) & " ------" & LF);
for i in t_msg_id'left to t_msg_id'right loop
if ((i /= ALL_MESSAGES) and ((i /= NO_ID) and (i /= ID_NEVER))) then -- report all but ID_NEVER, NO_ID and ALL_MESSAGES
write(v_line, " " & to_upper(to_string(i, C_LOG_MSG_ID_WIDTH+5, LEFT)) & ": "); -- MSG_ID
write(v_line,to_upper(to_string(shared_msg_id_panel(i))) & " " & LF); -- Enabled/disabled
end if;
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
end;
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
) is
begin
if alert_level = NO_ALERT then
tb_warning("set_alert_attention not allowed for alert_level NO_ALERT (always IGNORE).");
else
check_value(attention = IGNORE or attention = REGARD, TB_WARNING,
"set_alert_attention only supported for IGNORE and REGARD", C_BURIED_SCOPE, ID_NEVER);
shared_alert_attention(alert_level) := attention;
log(ID_ALERT_CTRL, "set_alert_attention(" & to_upper(to_string(alert_level)) & ", " & to_string(attention) & "). " & add_msg_delimiter(msg));
end if;
end;
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention is
begin
if alert_level = NO_ALERT then
return IGNORE;
else
return shared_alert_attention(alert_level);
end if;
end;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
) is
begin
if alert_level = NO_ALERT then
tb_warning("set_alert_stop_limit not allowed for alert_level NO_ALERT (stop limit always 0).");
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
shared_stop_limit(alert_level) := value;
-- Evaluate new stop limit in case it is less than or equal to the current alert counter for this alert level
-- If that is the case, a new alert with the same alert level shall be triggered.
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
alert(alert_level, "Alert stop limit for " & to_upper(to_string(alert_level)) & " set to " & to_string(value) &
", which is lower than the current " & to_upper(to_string(alert_level)) & " count (" & to_string(get_alert_counter(alert_level)) & ").");
end if;
else
-- If hierarchical alerts enabled, update top level
-- alert stop limit.
set_hierarchical_alert_top_level_stop_limit(alert_level, value);
end if;
end if;
end;
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural is
begin
if alert_level = NO_ALERT then
return 0;
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
return shared_stop_limit(alert_level);
else
return get_hierarchical_alert_top_level_stop_limit(alert_level);
end if;
end if;
end;
impure function get_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD
) return natural is
begin
return protected_alert_attention_counters.get(alert_level, attention);
end;
procedure increment_alert_counter(
alert_level : t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
) is
type alert_array is array (1 to 6) of t_alert_level;
constant alert_check_array : alert_array := (WARNING, TB_WARNING, ERROR, TB_ERROR, FAILURE, TB_FAILURE);
alias warning_and_worse is shared_uvvm_status.no_unexpected_simulation_warnings_or_worse;
alias error_and_worse is shared_uvvm_status.no_unexpected_simulation_errors_or_worse;
begin
protected_alert_attention_counters.increment(alert_level, attention, number);
-- Update simulation status
if (attention = REGARD) or (attention = EXPECT) then
if (alert_level /= NO_ALERT) and (alert_level /= NOTE) and (alert_level /= TB_NOTE) and (alert_level /= MANUAL_CHECK) then
warning_and_worse := 1; -- default
error_and_worse := 1; -- default
-- Compare expected and current allerts
for i in 1 to alert_check_array'high loop
if (get_alert_counter(alert_check_array(i), REGARD) > get_alert_counter(alert_check_array(i), EXPECT)) then
-- warning and worse
warning_and_worse := 0;
-- error and worse
if not(alert_check_array(i) = WARNING) and not(alert_check_array(i) = TB_WARNING) then
error_and_worse := 0;
end if;
end if;
end loop;
end if;
end if;
end;
-- ============================================================================
-- Deprecation message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
) is
variable v_found : boolean;
begin
v_found := false;
if C_DEPRECATE_SETTING /= NO_DEPRECATE then -- only perform if deprecation enabled
l_find_caller_name_in_list:
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify(caller_name, RIGHT, 100) then
v_found := true;
exit l_find_caller_name_in_list;
end if;
end loop;
if v_found then
-- Has already been printed.
if C_DEPRECATE_SETTING = ALWAYS_DEPRECATE then
log(ID_UTIL_SETUP, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
else -- C_DEPRECATE_SETTING = DEPRECATE_ONCE
null;
end if;
else
-- Has not been printed yet.
l_insert_caller_name_in_first_available:
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify("", RIGHT, 100) then
deprecated_subprogram_list(i) := justify(caller_name, RIGHT, 100);
exit l_insert_caller_name_in_first_available;
end if;
end loop;
log(ID_UTIL_SETUP, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
end if;
end if;
end;
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- NOTE: Index in range N downto 0, with -1 meaning not found
function idx_leftmost_p1_in_p2(
target : std_logic;
vector : std_logic_vector
) return integer is
alias a_vector : std_logic_vector(vector'length - 1 downto 0) is vector;
constant result_if_not_found : integer := -1; -- To indicate not found
begin
bitvis_assert(vector'length > 0, ERROR, "idx_leftmost_p1_in_p2()", "String input is empty");
for i in a_vector'left downto a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1: std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2: std_logic_vector(value2'length - 1 downto 0) is value2;
begin
if (a_value1'left >= maximum( idx_leftmost_p1_in_p2('1', a_value2), 0)) and
(a_value2'left >= maximum( idx_leftmost_p1_in_p2('1', a_value1), 0)) then
return true;
else
return false;
end if;
end;
function matching_widths(
value1: unsigned;
value2: unsigned
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
function matching_widths(
value1: signed;
value2: signed
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
-- Compare values, but ignore any leading zero's at higher indexes than v_min_length-1.
function matching_values(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1 : std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2 : std_logic_vector(value2'length - 1 downto 0) is value2;
variable v_min_length : natural := minimum(a_value1'length, a_value2'length);
variable v_match : boolean := true; -- as default prior to checking
begin
if matching_widths(a_value1, a_value2) then
if not std_match( a_value1(v_min_length-1 downto 0), a_value2(v_min_length-1 downto 0) ) then
v_match := false;
end if;
else
v_match := false;
end if;
return v_match;
end;
function matching_values(
value1: unsigned;
value2: unsigned
) return boolean is
begin
return matching_values(std_logic_vector(value1),std_logic_vector(value2));
end;
function matching_values(
value1: signed;
value2: signed
) return boolean is
begin
return matching_values(std_logic_vector(value1),std_logic_vector(value2));
end;
-- Function check_value,
-- returning 'true' if OK
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
begin
if value then
log(msg_id, caller_name & " => OK, for boolean true. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Boolean was false. " & add_msg_delimiter(msg), scope);
end if;
return value;
end;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, caller_name & " => OK, for boolean " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. Boolean was " & v_value_str & ". Expected " & v_exp_str & ". " & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "std_logic";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if std_match(value, exp) then
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & v_value_str & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
if match_strictness = MATCH_STD then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & v_value_str & "' (exp: '" & v_exp_str & "'). " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was '" & v_value_str & "'. Expected '" & v_exp_str & "'" & LF & msg, scope);
return false;
end if;
end if;
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was '" & v_value_str & "'. Expected '" & v_exp_str & "'" & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "std_logic";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
return check_value(value, exp, MATCH_STD, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
-- Normalise vectors to (N downto 0)
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_exp : std_logic_vector(exp'length - 1 downto 0) is exp;
constant v_value_str : string := to_string(a_value, radix, format,INCL_RADIX);
constant v_exp_str : string := to_string(a_exp, radix, format,INCL_RADIX);
variable v_check_ok : boolean := true; -- as default prior to checking
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(value'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
v_check_ok := matching_values(a_value, a_exp);
if v_check_ok then
if v_value_str = v_exp_str then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- H,L or - is present in v_exp_str
if match_strictness = MATCH_STD then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & "' (exp: " & v_exp_str & "'). " & add_msg_delimiter(msg),
scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & "'. Expected " & v_exp_str & "'" & LF & msg, scope);
end if;
end if;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & "'. Expected " & v_exp_str & "'" & LF & msg, scope);
end if;
return v_check_ok;
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
-- Normalise vectors to (N downto 0)
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_exp : std_logic_vector(exp'length - 1 downto 0) is exp;
constant v_value_str : string := to_string(a_value, radix, format);
constant v_exp_str : string := to_string(a_exp, radix, format);
variable v_check_ok : boolean := true; -- as default prior to checking
begin
return check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "int";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "real";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "string";
begin
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & value & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was '" & value & "'. Expected '" & exp & "'" & LF & msg, scope);
return false;
end if;
end;
----------------------------------------------------------------------
-- Overloads for check_value functions,
-- to allow for no return value
----------------------------------------------------------------------
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, match_strictness, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
------------------------------------------------------------------------
-- check_value_in_range
------------------------------------------------------------------------
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "real";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, scope,
ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
--------------------------------------------------------------------------------
-- check_value_in_range procedures :
-- Call the corresponding function and discard the return value
--------------------------------------------------------------------------------
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
--------------------------------------------------------------------------------
-- check_stable
--------------------------------------------------------------------------------
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "boolean"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "slv"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "unsigned"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "signed"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "std_logic"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "integer"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK." & value_string & " stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : real;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "real"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK." & value_string & " stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
-- check_time_window is used to check if a given condition occurred between
-- min_time and max_time
-- Usage: wait for requested condition until max_time is reached, then call check_time_window().
-- The input 'success' is needed to distinguish between the following cases:
-- - the signal reached success condition at max_time,
-- - max_time was reached with no success condition
procedure check_time_window(
constant success : boolean; -- F.ex target'event, or target=exp
constant elapsed_time : time;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant name : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
-- Sanity check
check_value(max_time >= min_time, TB_ERROR, name & " => min_time must be less than max_time." & LF & msg, scope, ID_NEVER, msg_id_panel, name);
if elapsed_time < min_time then
alert(alert_level, name & " => Failed. Condition occurred too early, after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope);
elsif success then
log(msg_id, name & " => OK. Condition occurred after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else -- max_time reached with no success
alert(alert_level, name & " => Failed. Timed out after " &
to_string(max_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope);
end if;
end;
----------------------------------------------------------------------------
-- Random functions
----------------------------------------------------------------------------
-- Return a random std_logic_vector, using overload for the integer version of random()
impure function random (
constant length : integer
) return std_logic_vector is
variable random_vec : std_logic_vector(length-1 downto 0);
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to length-1 loop
random_vec(i downto i) := std_logic_vector(to_unsigned(random(0,1), 1));
end loop;
return random_vec;
end;
-- Return a random std_logic, using overload for the SLV version of random()
impure function random (
constant VOID : t_void
) return std_logic is
variable v_random_bit : std_logic_vector(0 downto 0);
begin
-- randomly set bit to 0 or 1
v_random_bit := random(1);
return v_random_bit(0);
end;
-- Return a random integer between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer is
variable v_rand_scaled : integer;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random real between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : real;
constant max_value : real
) return real is
variable v_rand_scaled : real;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random time between min time and max time, using overload for the integer version of random()
impure function random (
constant min_value : time;
constant max_value : time
) return time is
begin
return random(min_value/1 ns, max_value/1 ns) * 1 ns;
end;
--
-- Procedure versions of random(), where seeds can be specified
--
-- Set target to a random SLV, using overload for the integer version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
) is
variable v_length : integer := v_target'length;
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to v_length-1 loop
v_target(i downto i) := std_logic_vector(to_unsigned(random(0,1),1));
end loop;
end;
-- Set target to a random SL, using overload for the integer version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
) is
variable v_random_slv : std_logic_vector(0 downto 0);
begin
v_random_slv := std_logic_vector(to_unsigned(random(0,1),1));
v_target := v_random_slv(0);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + integer(trunc(v_rand*real(1+max_value-min_value)));
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + v_rand*(max_value-min_value);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
) is
variable v_rand : real;
variable v_rand_int : integer;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_rand_int := min_value/1 ns + integer(trunc(v_rand*real(1 + max_value/1 ns - min_value / 1 ns)));
v_target := v_rand_int * 1 ns;
end;
-- Set global seeds
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- Set global seeds
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
deprecate(get_procedure_name_from_instance_name(seed1'instance_name), "Use randomize().");
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- ============================================================================
-- Time consuming checks
-- ============================================================================
--------------------------------------------------------------------------------
-- await_change
-- A signal change is required, but may happen already after 1 delta if min_time = 0 ns
--------------------------------------------------------------------------------
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
-- Note that overloading by casting target to slv without creating a new signal doesn't work
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "real"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
--------------------------------------------------------------------------------
-- await_value
--------------------------------------------------------------------------------
-- Potential improvements
-- - Adding an option that the signal must last for more than one delta cycle
-- or a specified time
-- - Adding an "AS_IS" option that does not allow the signal to change to other values
-- before it changes to the expected value
--
-- The input signal is allowed to change to other values before ending up on the expected value,
-- as long as it changes to the expected value within the time window (min_time to max_time).
-- Wait for target = expected or timeout after max_time.
-- Then check if (and when) the value changed to the expected
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
variable success : boolean := false;
begin
success := false;
if match_strictness = MATCH_EXACT then
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
if (target = exp) then
success := true;
end if;
else
if ((exp = '1' or exp = 'H') and (target /= '1') and (target /= 'H')) then
wait until (target = '1' or target = 'H') for max_time;
elsif ((exp = '0' or exp = 'L') and (target /= '0') and (target /= 'L')) then
wait until (target = '0' or target = 'L') for max_time;
end if;
if ((exp = '1' or exp = 'H') and (target = '1' or target = 'H')) then
success := true;
elsif ((exp = '0' or exp = 'L') and (target = '0' or target = 'L')) then
success := true;
end if;
end if;
check_time_window(success, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
await_value(target, exp, MATCH_EXACT, min_time, max_time, alert_level, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "slv";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if match_strictness = MATCH_STD then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end if;
else
alert(alert_level, name & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
end if;
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "slv";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
await_value(target, exp, MATCH_STD, min_time, max_time, alert_level, msg, scope, radix, format, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
end if;
end;
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
end if;
end;
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : real;
constant exp : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "real";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
-- Helper procedure:
-- Convert time from 'FROM_LAST_EVENT' to 'FROM_NOW'
procedure await_stable_calc_time (
constant target_last_event : time;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
variable stable_req_from_now : inout time; -- Calculated stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Calculated timeout from procedure entry
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "await_stable_calc_time()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
begin
stable_req_met := false;
-- Convert stable_req so that it points to "time_from_now"
if stable_req_from = FROM_NOW then
stable_req_from_now := stable_req;
elsif stable_req_from = FROM_LAST_EVENT then
-- Signal has already been stable for target'last_event,
-- so we can subtract this in the FROM_NOW version.
stable_req_from_now := stable_req - target_last_event;
else
alert(tb_error, caller_name & " => Unknown stable_req_from. " & add_msg_delimiter(msg), scope);
end if;
-- Convert timeout so that it points to "time_from_now"
if timeout_from = FROM_NOW then
timeout_from_await_stable_entry := timeout;
elsif timeout_from = FROM_LAST_EVENT then
timeout_from_await_stable_entry := timeout - target_last_event;
else
alert(tb_error, caller_name & " => Unknown timeout_from. " & add_msg_delimiter(msg), scope);
end if;
-- Check if requirement is already OK
if (stable_req_from_now <= 0 ns) then
log(msg_id, caller_name & " => OK. Condition occurred immediately. " & add_msg_delimiter(msg), scope, msg_id_panel);
stable_req_met := true;
end if;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > timeout_from_await_stable_entry) then
alert(alert_level, caller_name & " => Failed immediately: Stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
". " & add_msg_delimiter(msg), scope);
stable_req_met := true;
end if;
end;
-- Helper procedure:
procedure await_stable_checks (
constant start_time : time; -- Time at await_stable() procedure entry
constant stable_req : time; -- Minimum stable requirement
variable stable_req_from_now : inout time; -- Minimum stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Timeout value converted to FROM_NOW
constant time_since_last_event : time; -- Time since previous event
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "await_stable_checks()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
variable v_time_left : time; -- Remaining time until timeout
variable v_elapsed_time : time := 0 ns; -- Time since procedure entry
begin
stable_req_met := false;
v_elapsed_time := now - start_time;
v_time_left := timeout_from_await_stable_entry - v_elapsed_time;
-- Check if target has been stable for stable_req
if (time_since_last_event >= stable_req_from_now) then
log(msg_id, caller_name & " => OK. Condition occurred after " &
to_string(v_elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
stable_req_met := true;
end if;
--
-- Prepare for the next iteration in the loop in await_stable() procedure:
--
if not stable_req_met then
-- Now that an event has occurred, the stable requirement is stable_req from now (regardless of stable_req_from)
stable_req_from_now := stable_req;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > v_time_left) then
alert(alert_level, caller_name & " => Failed. After " & to_string(v_elapsed_time, C_LOG_TIME_BASE) &
", stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
"(time since last event = " & to_string(time_since_last_event, ns) &
". " & add_msg_delimiter(msg), scope);
stable_req_met := true;
end if;
end if;
end;
-- Wait until the target signal has been stable for at least 'stable_req'
-- Report an error if this does not occurr within the time specified by 'timeout'.
-- Note : 'Stable' refers to that the signal has not had an event (i.e. not changed value).
-- Description of arguments:
-- stable_req_from = FROM_NOW : Target must be stable 'stable_req' from now
-- stable_req_from = FROM_LAST_EVENT : Target must be stable 'stable_req' from the last event of target.
-- timeout_from = FROM_NOW : The timeout argument is given in time from now
-- timeout_from = FROM_LAST_EVENT : The timeout argument is given in time the last event of target.
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-- Note that the waiting for target'event can't be called from overloaded procedures where 'target' is a different type.
-- Instead, the common code is put in helper procedures
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic_vector";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occur
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : real;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "real";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occur
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-----------------------------------------------------------------------------------
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain amount of time
--
-- If blocking_mode = BLOCKING : Procedure waits until the pulse is done before returning to the caller.
-- If blocking_mode = NON_BLOCKING : Procedure starts the pulse, schedules the end of the pulse, then returns to the caller immediately.
--
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic := target;
begin
log(msg_id, "Pulse to " & to_string(pulse_value) &
" for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Start pulse
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
target <= transport init_value after pulse_duration;
end if;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain number of clock cycles
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic := target;
begin
log(msg_id, "Pulse to " & to_string(pulse_value) &
" for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
if (num_periods > 0) then
wait until falling_edge(clock_signal);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value;
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else -- Pulse for one delta cycle only
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value;
wait for 0 ns;
end if;
target <= init_value;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = '1' by default
end;
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : boolean := target;
begin
log(msg_id, "Pulse to " & to_string(pulse_value) &
" for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Start pulse
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
target <= transport init_value after pulse_duration;
end if;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Generate a pulse on a boolean for a certain number of clock cycles
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : boolean := target;
begin
log(msg_id, "Pulse to " & to_string(pulse_value) &
" for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
if (num_periods > 0) then
wait until falling_edge(clock_signal);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value;
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else -- Pulse for one delta cycle only
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value;
wait for 0 ns;
end if;
target <= init_value;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = '1' by default
end;
-- gen_pulse(slv)
-- Generate a pulse on a std_logic_vector for a certain amount of time
--
-- If blocking_mode = BLOCKING : Procedure waits until the pulse is done before returning to the caller.
-- If blocking_mode = NON_BLOCKING : Procedure starts the pulse, schedules the end of the pulse, then returns to the caller immediately.
--
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic_vector(target'range) := target;
variable v_target : std_logic_vector(target'length-1 downto 0) := target;
variable v_pulse : std_logic_vector(pulse_value'length-1 downto 0) := pulse_value;
begin
log(msg_id, "Pulse to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) &
" for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
for i in 0 to (v_target'length-1) loop
if pulse_value(i) /= '-' then
v_target(i) := v_pulse(i); -- Generate pulse
end if;
end loop;
target <= v_target;
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
target <= transport init_value after pulse_duration;
end if;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- gen_pulse(slv)
-- Generate a pulse on a std_logic_vector for a certain number of clock cycles
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic_vector(target'range) := target;
constant v_pulse : std_logic_vector(pulse_value'length-1 downto 0) := pulse_value;
variable v_target : std_logic_vector(target'length-1 downto 0) := target;
begin
log(msg_id, "Pulse to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) &
" for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
if (num_periods > 0) then
wait until falling_edge(clock_signal);
for i in 0 to (v_target'length-1) loop
if v_pulse(i) /= '-' then
v_target(i) := v_pulse(i); -- Generate pulse
end if;
end loop;
target <= v_target;
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else -- Pulse for one delta cycle only
for i in 0 to (v_target'length-1) loop
if v_pulse(i) /= '-' then
v_target(i) := v_pulse(i); -- Generate pulse
end if;
end loop;
target <= v_target;
wait for 0 ns;
end if;
target <= init_value;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = (others => '1') by default
end;
--------------------------------------------
-- Clock generators :
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
-- Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
loop
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
-- Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_time : in time
) is
begin
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
clock_count <= 0;
loop
clock_signal <= '0'; -- Should start on 0
wait for C_FIRST_HALF_CLK_PERIOD;
-- Update clock_count when clock_signal is set to '1'
if clock_count < natural'right then
clock_count <= clock_count + 1;
else -- Wrap when reached max value of natural
clock_count <= 0;
end if;
clock_signal <= '1';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Counter clock_count is given as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_time : in time
) is
begin
clock_count <= 0;
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
clock_signal <= '0';
wait for clock_high_time;
if clock_count < natural'right then
clock_count <= clock_count + 1;
else -- Wrap when reached max value of natural
clock_count <= 0;
end if;
clock_signal <= '1';
wait for (clock_period - clock_high_time);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- inferred to be low time.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
) is
begin
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
variable v_clock_count : natural := 0;
begin
clock_count <= v_clock_count;
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
if v_clock_count < natural'right then
v_clock_count := v_clock_count + 1;
else -- Wrap when reached max value of natural
v_clock_count := 0;
end if;
clock_count <= v_clock_count;
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- inferred to be low time.
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
) is
variable v_clock_count : natural := 0;
begin
clock_count <= v_clock_count;
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
if v_clock_count < natural'right then
v_clock_count := v_clock_count + 1;
else -- Wrap when reached max value of natural
v_clock_count := 0;
end if;
clock_count <= v_clock_count;
end loop;
end;
-- ============================================================================
-- Synchronisation methods
-- ============================================================================
procedure block_flag(
constant flag_name : in string;
constant msg : in string
) is
begin
-- Block the flag if it was used before
for i in shared_flag_array'range loop
if shared_flag_array(i).flag_name(flag_name'range) = flag_name or shared_flag_array(i).flag_name = (shared_flag_array(i).flag_name'range => ' ') then
shared_flag_array(i).flag_name(flag_name'range) := flag_name;
shared_flag_array(i).is_active := true;
exit;
end if;
end loop;
log(ID_BLOCKING, "Blocking " & flag_name & ". " & add_msg_delimiter(msg), C_SCOPE);
end procedure;
procedure unblock_flag(
constant flag_name : in string;
constant msg : in string;
signal trigger : inout std_logic
) is
variable found : boolean := false;
begin
-- check if the flag has already been added. If not add it.
for i in shared_flag_array'range loop
if shared_flag_array(i).flag_name(flag_name'range) = flag_name or shared_flag_array(i).flag_name = (shared_flag_array(i).flag_name'range => ' ') then
shared_flag_array(i).flag_name(flag_name'range) := flag_name;
shared_flag_array(i).is_active := false;
found := true;
log(ID_BLOCKING, "Unblocking " & flag_name & ". " & add_msg_delimiter(msg), C_SCOPE);
gen_pulse(trigger, 0 ns, "pulsing global_trigger. " & add_msg_delimiter(msg), C_TB_SCOPE_DEFAULT, ID_NEVER);
exit;
end if;
end loop;
if found = false then
log(ID_BLOCKING, "The flag " & flag_name & " was not found and the maximum of flags were used. Configure in adaptations_pkg. " & add_msg_delimiter(msg), C_SCOPE);
end if;
end procedure;
procedure await_unblock_flag(
constant flag_name : in string;
constant timeout : in time;
constant msg : in string;
constant flag_returning : in t_flag_returning := KEEP_UNBLOCKED;
constant timeout_severity : in t_alert_level := ERROR
) is
variable v_flag_is_active : boolean := true;
constant start_time : time := now;
begin
-- check if flag was not unblocked before
for i in shared_flag_array'range loop
-- check if the flag was already in the global_flag array. If it was not -> add it to the first free space
if shared_flag_array(i).flag_name(flag_name'range) = flag_name or shared_flag_array(i).flag_name = (shared_flag_array(i).flag_name'range => ' ') then
shared_flag_array(i).flag_name(flag_name'range) := flag_name;
v_flag_is_active := shared_flag_array(i).is_active;
if v_flag_is_active = false then
log(ID_BLOCKING, flag_name & " was not blocked. " & add_msg_delimiter(msg), C_SCOPE);
if flag_returning = RETURN_TO_BLOCK then
-- wait for all sequencer that are waiting for that flag before reseting it
wait for 0 ns;
shared_flag_array(i).is_active := true;
end if;
end if;
exit;
end if;
end loop;
if v_flag_is_active = true then
-- log before while loop. Otherwise the message will be printed everytime the global_trigger was triggered.
log(ID_BLOCKING, "Waiting for " & flag_name & " to be unblocked. " & add_msg_delimiter(msg), C_SCOPE);
end if;
while v_flag_is_active = true loop
if timeout /= 0 ns then
wait until rising_edge(global_trigger) for ((start_time + timeout) - now);
check_value(global_trigger = '1', timeout_severity, flag_name & " timed out" & add_msg_delimiter(msg), C_SCOPE, ID_NEVER);
if global_trigger /= '1' then
exit;
end if;
else
wait until rising_edge(global_trigger);
end if;
for i in shared_flag_array'range loop
if shared_flag_array(i).flag_name(flag_name'range) = flag_name then
v_flag_is_active := shared_flag_array(i).is_active;
if v_flag_is_active = false then
log(ID_BLOCKING, flag_name & " was unblocked. " & add_msg_delimiter(msg), C_SCOPE);
if flag_returning = RETURN_TO_BLOCK then
-- wait for all sequencer that are waiting for that flag before reseting it
wait for 0 ns;
shared_flag_array(i).is_active := true;
end if;
end if;
end if;
end loop;
end loop;
end procedure;
procedure await_barrier(
signal barrier_signal : inout std_logic;
constant timeout : in time;
constant msg : in string;
constant timeout_severity : in t_alert_level := ERROR
)is
begin
-- set barrier signal to 0
barrier_signal <= '0';
log(ID_BLOCKING, "Waiting for barrier. " & add_msg_delimiter(msg), C_SCOPE);
-- wait until all sequencer using that barrier_signal wait for it
if timeout = 0 ns then
wait until barrier_signal = '0';
else
wait until barrier_signal = '0' for timeout;
end if;
if barrier_signal /= '0' then
-- timeout
alert(timeout_severity, "Timeout while waiting for barrier signal. " & add_msg_delimiter(msg), C_SCOPE);
else
log(ID_BLOCKING, "Barrier received. " & add_msg_delimiter(msg), C_SCOPE);
end if;
barrier_signal <= '1';
end procedure;
procedure await_semaphore_in_delta_cycles(
variable semaphore : inout t_protected_semaphore
) is
variable v_cnt_lock_tries : natural := 0;
begin
while semaphore.get_semaphore = false and v_cnt_lock_tries < C_NUM_SEMAPHORE_LOCK_TRIES loop
wait for 0 ns;
v_cnt_lock_tries := v_cnt_lock_tries + 1;
end loop;
if v_cnt_lock_tries = C_NUM_SEMAPHORE_LOCK_TRIES then
tb_error("Failed to acquire semaphore when sending command to VVC", C_SCOPE);
end if;
end procedure;
procedure release_semaphore(
variable semaphore : inout t_protected_semaphore
) is
begin
semaphore.release_semaphore;
end procedure;
end package body methods_pkg;
| mit | a1591ede633acf0faeffb2c3aa323b7e | 0.569046 | 3.776134 | false | false | false | false |
elainemielas/CVUT_BI-PNO | project2/tb_allinall.vhd | 1 | 2,724 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TB_ALLINALL is
end entity TB_ALLINALL;
architecture TB_ALLINALL_BODY of TB_ALLINALL is
component ALLINALL is
port (
PS2_DATA : in std_logic; -- serial PS2 input
PS2_CLK : in std_logic; -- serial PS2 clock
CLK : in std_logic; -- standard 50MHz clock
RESET : in std_logic;
JCHYBA : out std_logic; -- detekovano s 1 chybou
SHODA : out std_logic -- detekovana uplna shoda
);
end component;
signal T_PS2_DATA, T_PS2_CLK, T_CLK, T_RESET, T_JCHYBA, T_SHODA : std_logic;
signal TS1, TS2, TS3, TS4 : std_logic_vector(7 downto 0); -- testove data
begin
UUT : ALLINALL port map (PS2_DATA => T_PS2_DATA, PS2_CLK => T_PS2_CLK, RESET => T_RESET,
JCHYBA => T_JCHYBA, SHODA => T_SHODA, CLK => T_CLK);
-- hodiny
HOD : process
begin
T_CLK <= '0';
wait for 10 ns;
T_CLK <= '1';
wait for 10 ns;
end process;
RES : process
begin
T_RESET <= '1';
wait for 100 ns;
T_RESET <= '0';
wait;
end process;
TESTOVANI : process
procedure TEST (TS: in std_logic_vector(7 downto 0)) is
begin
T_PS2_DATA <= '1';
T_PS2_CLK <= '1';
--T_RESET <= '1';
--wait for 100 ns;
--T_RESET <= '0';
wait for 20 us;
-- pocatecni bit
T_PS2_DATA <= '0';
wait for 10 us;
T_PS2_CLK <= '0';
wait for 40 us;
T_PS2_CLK <= '1';
wait for 30 us;
-- data bity
for I in 0 to 7 loop
T_PS2_DATA <= TS(I);
wait for 10 us;
T_PS2_CLK <= '0';
wait for 40 us;
T_PS2_CLK <= '1';
wait for 30 us;
end loop;
-- paritni bit
T_PS2_DATA <= '1';
wait for 10 us;
T_PS2_CLK <= '0';
wait for 40 us;
T_PS2_CLK <= '1';
wait for 30 us;
-- stop bit
T_PS2_DATA <= '1';
wait for 10 us;
T_PS2_CLK <= '0';
wait for 40 us;
T_PS2_CLK <= '1';
wait for 30 us;
-- overujeme, jestli se nastavil KEY_PRESS
--assert not T_KEY_PRESS'stable(100 us) report "chybne nastaven KEY_PRESS" severity error;
end procedure;
begin
TS1 <= "00101011"; -- F
TS2 <= "00111100"; -- U
TS3 <= "01001011"; -- L
TS4 <= "00111010"; -- M
-- vysilame KEY F
TEST(TS1);
wait for 1 ms;
-- vysilame KEY U
TEST(TS2);
wait for 1 ms;
-- vysilame KEY L
TEST(TS3);
wait for 1 ms;
-- vysilame KEY L
TEST(TS3);
wait for 5 ms;
assert T_SHODA = '1' report "neni detekovana shoda" severity error;
-- vysilame KEY F
TEST(TS1);
wait for 1 ms;
-- vysilame KEY U
TEST(TS2);
wait for 1 ms;
-- vysilame KEY M
TEST(TS4);
wait for 1 ms;
-- vysilame KEY L
TEST(TS3);
wait for 5 ms;
assert T_JCHYBA <= '1' report "neni detekovana jedna chyba" severity error;
wait;
end process;
end architecture; | mit | e516bb78181e54a73dec5b4cb6f66e0a | 0.589207 | 2.548176 | false | true | false | false |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/allocator_logic_pseudo_checkers.vhd | 12 | 24,829 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_logic_pseudo_checkers is
port (
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: in std_logic;
grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: in std_logic;
grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: in std_logic;
grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: in std_logic;
grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: in std_logic;
valid_N, valid_E, valid_W, valid_S, valid_L : in std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: in std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: in std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: in std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: in std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L : in std_logic;
-- Checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N,
err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E,
err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W,
err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S,
err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L,
err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match : out std_logic
);
end allocator_logic_pseudo_checkers;
architecture behavior of allocator_logic_pseudo_checkers is
begin
-- The combionational part
-- Checkers
-- Grant_N checkers
process (grant_N_N_sig, empty_N, grant_N_N)
begin
if (grant_N_N_sig = '1' and empty_N = '0' and grant_N_N = '0') then
err_grant_N_N_sig_not_empty_N_grant_N_N <= '1';
else
err_grant_N_N_sig_not_empty_N_grant_N_N <= '0';
end if;
end process;
process (grant_N_N_sig, empty_N, grant_N_N)
begin
if ( (grant_N_N_sig = '0' or empty_N = '1') and grant_N_N = '1') then
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N <= '1';
else
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N <= '0';
end if;
end process;
process (grant_N_E_sig, empty_E, grant_N_E)
begin
if (grant_N_E_sig = '1' and empty_E = '0' and grant_N_E = '0') then
err_grant_N_E_sig_not_empty_E_grant_N_E <= '1';
else
err_grant_N_E_sig_not_empty_E_grant_N_E <= '0';
end if;
end process;
process (grant_N_E_sig, empty_E, grant_N_E)
begin
if ( (grant_N_E_sig = '0' or empty_E = '1') and grant_N_E = '1') then
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E <= '1';
else
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E <= '0';
end if;
end process;
process (grant_N_W_sig, empty_W, grant_N_W)
begin
if (grant_N_W_sig = '1' and empty_W = '0' and grant_N_W = '0') then
err_grant_N_W_sig_not_empty_W_grant_N_W <= '1';
else
err_grant_N_W_sig_not_empty_W_grant_N_W <= '0';
end if;
end process;
process (grant_N_W_sig, empty_W, grant_N_W)
begin
if ( (grant_N_W_sig = '0' or empty_W = '1') and grant_N_W = '1') then
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W <= '1';
else
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W <= '0';
end if;
end process;
process (grant_N_S_sig, empty_S, grant_N_S)
begin
if (grant_N_S_sig = '1' and empty_S = '0' and grant_N_S = '0') then
err_grant_N_S_sig_not_empty_S_grant_N_S <= '1';
else
err_grant_N_S_sig_not_empty_S_grant_N_S <= '0';
end if;
end process;
process (grant_N_S_sig, empty_S, grant_N_S)
begin
if ( (grant_N_S_sig = '0' or empty_S = '1') and grant_N_S = '1') then
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S <= '1';
else
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S <= '0';
end if;
end process;
process (grant_N_L_sig, empty_L, grant_N_L)
begin
if (grant_N_L_sig = '1' and empty_L = '0' and grant_N_L = '0') then
err_grant_N_L_sig_not_empty_L_grant_N_L <= '1';
else
err_grant_N_L_sig_not_empty_L_grant_N_L <= '0';
end if;
end process;
process (grant_N_L_sig, empty_L, grant_N_L)
begin
if ( (grant_N_L_sig = '0' or empty_L = '1') and grant_N_L = '1') then
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L <= '1';
else
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Grant_E checkers
process (grant_E_N_sig, empty_N, grant_E_N)
begin
if (grant_E_N_sig = '1' and empty_N = '0' and grant_E_N = '0') then
err_grant_E_N_sig_not_empty_N_grant_E_N <= '1';
else
err_grant_E_N_sig_not_empty_N_grant_E_N <= '0';
end if;
end process;
process (grant_E_N_sig, empty_N, grant_E_N)
begin
if ( (grant_E_N_sig = '0' or empty_N = '1') and grant_E_N = '1') then
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N <= '1';
else
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N <= '0';
end if;
end process;
process (grant_E_E_sig, empty_E, grant_E_E)
begin
if (grant_E_E_sig = '1' and empty_E = '0' and grant_E_E = '0') then
err_grant_E_E_sig_not_empty_E_grant_E_E <= '1';
else
err_grant_E_E_sig_not_empty_E_grant_E_E <= '0';
end if;
end process;
process (grant_E_E_sig, empty_E, grant_E_E)
begin
if ( (grant_E_E_sig = '0' or empty_E = '1') and grant_E_E = '1') then
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E <= '1';
else
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E <= '0';
end if;
end process;
process (grant_E_W_sig, empty_W, grant_E_W)
begin
if (grant_E_W_sig = '1' and empty_W = '0' and grant_E_W = '0') then
err_grant_E_W_sig_not_empty_W_grant_E_W <= '1';
else
err_grant_E_W_sig_not_empty_W_grant_E_W <= '0';
end if;
end process;
process (grant_E_W_sig, empty_W, grant_E_W)
begin
if ( (grant_E_W_sig = '0' or empty_W = '1') and grant_E_W = '1') then
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W <= '1';
else
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W <= '0';
end if;
end process;
process (grant_E_S_sig, empty_S, grant_E_S)
begin
if (grant_E_S_sig = '1' and empty_S = '0' and grant_E_S = '0') then
err_grant_E_S_sig_not_empty_S_grant_E_S <= '1';
else
err_grant_E_S_sig_not_empty_S_grant_E_S <= '0';
end if;
end process;
process (grant_E_S_sig, empty_S, grant_E_S)
begin
if ( (grant_E_S_sig = '0' or empty_S = '1') and grant_E_S = '1') then
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S <= '1';
else
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S <= '0';
end if;
end process;
process (grant_E_L_sig, empty_L, grant_E_L)
begin
if (grant_E_L_sig = '1' and empty_L = '0' and grant_E_L = '0') then
err_grant_E_L_sig_not_empty_L_grant_E_L <= '1';
else
err_grant_E_L_sig_not_empty_L_grant_E_L <= '0';
end if;
end process;
process (grant_E_L_sig, empty_L, grant_E_L)
begin
if ( (grant_E_L_sig = '0' or empty_L = '1') and grant_E_L = '1') then
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L <= '1';
else
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Grant_W checkers
process (grant_W_N_sig, empty_N, grant_W_N)
begin
if (grant_W_N_sig = '1' and empty_N = '0' and grant_W_N = '0') then
err_grant_W_N_sig_not_empty_N_grant_W_N <= '1';
else
err_grant_W_N_sig_not_empty_N_grant_W_N <= '0';
end if;
end process;
process (grant_W_N_sig, empty_N, grant_W_N)
begin
if ( (grant_W_N_sig = '0' or empty_N = '1') and grant_W_N = '1') then
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N <= '1';
else
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N <= '0';
end if;
end process;
process (grant_W_E_sig, empty_E, grant_W_E)
begin
if (grant_W_E_sig = '1' and empty_E = '0' and grant_W_E = '0') then
err_grant_W_E_sig_not_empty_E_grant_W_E <= '1';
else
err_grant_W_E_sig_not_empty_E_grant_W_E <= '0';
end if;
end process;
process (grant_W_E_sig, empty_E, grant_W_E)
begin
if ( (grant_W_E_sig = '0' or empty_E = '1') and grant_W_E = '1') then
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E <= '1';
else
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E <= '0';
end if;
end process;
process (grant_W_W_sig, empty_W, grant_W_W)
begin
if (grant_W_W_sig = '1' and empty_W = '0' and grant_W_W = '0') then
err_grant_W_W_sig_not_empty_W_grant_W_W <= '1';
else
err_grant_W_W_sig_not_empty_W_grant_W_W <= '0';
end if;
end process;
process (grant_W_W_sig, empty_W, grant_W_W)
begin
if ( (grant_W_W_sig = '0' or empty_W = '1') and grant_W_W = '1') then
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W <= '1';
else
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W <= '0';
end if;
end process;
process (grant_W_S_sig, empty_S, grant_W_S)
begin
if (grant_W_S_sig = '1' and empty_S = '0' and grant_W_S = '0') then
err_grant_W_S_sig_not_empty_S_grant_W_S <= '1';
else
err_grant_W_S_sig_not_empty_S_grant_W_S <= '0';
end if;
end process;
process (grant_W_S_sig, empty_S, grant_W_S)
begin
if ( (grant_W_S_sig = '0' or empty_S = '1') and grant_W_S = '1') then
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S <= '1';
else
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S <= '0';
end if;
end process;
process (grant_W_L_sig, empty_L, grant_W_L)
begin
if (grant_W_L_sig = '1' and empty_L = '0' and grant_W_L = '0') then
err_grant_W_L_sig_not_empty_L_grant_W_L <= '1';
else
err_grant_W_L_sig_not_empty_L_grant_W_L <= '0';
end if;
end process;
process (grant_W_L_sig, empty_L, grant_W_L)
begin
if ( (grant_W_L_sig = '0' or empty_L = '1') and grant_W_L = '1') then
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L <= '1';
else
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Grant_S checkers
process (grant_S_N_sig, empty_N, grant_S_N)
begin
if (grant_S_N_sig = '1' and empty_N = '0' and grant_S_N = '0') then
err_grant_S_N_sig_not_empty_N_grant_S_N <= '1';
else
err_grant_S_N_sig_not_empty_N_grant_S_N <= '0';
end if;
end process;
process (grant_S_N_sig, empty_N, grant_S_N)
begin
if ( (grant_S_N_sig = '0' or empty_N = '1') and grant_S_N = '1') then
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N <= '1';
else
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N <= '0';
end if;
end process;
process (grant_S_E_sig, empty_E, grant_S_E)
begin
if (grant_S_E_sig = '1' and empty_E = '0' and grant_S_E = '0') then
err_grant_S_E_sig_not_empty_E_grant_S_E <= '1';
else
err_grant_S_E_sig_not_empty_E_grant_S_E <= '0';
end if;
end process;
process (grant_S_E_sig, empty_E, grant_S_E)
begin
if ( (grant_S_E_sig = '0' or empty_E = '1') and grant_S_E = '1') then
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E <= '1';
else
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E <= '0';
end if;
end process;
process (grant_S_W_sig, empty_W, grant_S_W)
begin
if (grant_S_W_sig = '1' and empty_W = '0' and grant_S_W = '0') then
err_grant_S_W_sig_not_empty_W_grant_S_W <= '1';
else
err_grant_S_W_sig_not_empty_W_grant_S_W <= '0';
end if;
end process;
process (grant_S_W_sig, empty_W, grant_S_W)
begin
if ( (grant_S_W_sig = '0' or empty_W = '1') and grant_S_W = '1') then
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W <= '1';
else
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W <= '0';
end if;
end process;
process (grant_S_S_sig, empty_S, grant_S_S)
begin
if (grant_S_S_sig = '1' and empty_S = '0' and grant_S_S = '0') then
err_grant_S_S_sig_not_empty_S_grant_S_S <= '1';
else
err_grant_S_S_sig_not_empty_S_grant_S_S <= '0';
end if;
end process;
process (grant_S_S_sig, empty_S, grant_S_S)
begin
if ( (grant_S_S_sig = '0' or empty_S = '1') and grant_S_S = '1') then
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S <= '1';
else
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S <= '0';
end if;
end process;
process (grant_S_L_sig, empty_L, grant_S_L)
begin
if (grant_S_L_sig = '1' and empty_L = '0' and grant_S_L = '0') then
err_grant_S_L_sig_not_empty_L_grant_S_L <= '1';
else
err_grant_S_L_sig_not_empty_L_grant_S_L <= '0';
end if;
end process;
process (grant_S_L_sig, empty_L, grant_S_L)
begin
if ( (grant_S_L_sig = '0' or empty_L = '1') and grant_S_L = '1') then
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L <= '1';
else
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Grant_L checkers
process (grant_L_N_sig, empty_N, grant_L_N)
begin
if (grant_L_N_sig = '1' and empty_N = '0' and grant_L_N = '0') then
err_grant_L_N_sig_not_empty_N_grant_L_N <= '1';
else
err_grant_L_N_sig_not_empty_N_grant_L_N <= '0';
end if;
end process;
process (grant_L_N_sig, empty_N, grant_L_N)
begin
if ( (grant_L_N_sig = '0' or empty_N = '1') and grant_L_N = '1') then
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N <= '1';
else
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N <= '0';
end if;
end process;
process (grant_L_E_sig, empty_E, grant_L_E)
begin
if (grant_L_E_sig = '1' and empty_E = '0' and grant_L_E = '0') then
err_grant_L_E_sig_not_empty_E_grant_L_E <= '1';
else
err_grant_L_E_sig_not_empty_E_grant_L_E <= '0';
end if;
end process;
process (grant_L_E_sig, empty_E, grant_L_E)
begin
if ( (grant_L_E_sig = '0' or empty_E = '1') and grant_L_E = '1') then
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E <= '1';
else
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E <= '0';
end if;
end process;
process (grant_L_W_sig, empty_W, grant_L_W)
begin
if (grant_L_W_sig = '1' and empty_W = '0' and grant_L_W = '0') then
err_grant_L_W_sig_not_empty_W_grant_L_W <= '1';
else
err_grant_L_W_sig_not_empty_W_grant_L_W <= '0';
end if;
end process;
process (grant_L_W_sig, empty_W, grant_L_W)
begin
if ( (grant_L_W_sig = '0' or empty_W = '1') and grant_L_W = '1') then
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W <= '1';
else
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W <= '0';
end if;
end process;
process (grant_L_S_sig, empty_S, grant_L_S)
begin
if (grant_L_S_sig = '1' and empty_S = '0' and grant_L_S = '0') then
err_grant_L_S_sig_not_empty_S_grant_L_S <= '1';
else
err_grant_L_S_sig_not_empty_S_grant_L_S <= '0';
end if;
end process;
process (grant_L_S_sig, empty_S, grant_L_S)
begin
if ( (grant_L_S_sig = '0' or empty_S = '1') and grant_L_S = '1') then
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S <= '1';
else
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S <= '0';
end if;
end process;
process (grant_L_L_sig, empty_L, grant_L_L)
begin
if (grant_L_L_sig = '1' and empty_L = '0' and grant_L_L = '0') then
err_grant_L_L_sig_not_empty_L_grant_L_L <= '1';
else
err_grant_L_L_sig_not_empty_L_grant_L_L <= '0';
end if;
end process;
process (grant_L_L_sig, empty_L, grant_L_L)
begin
if ( (grant_L_L_sig = '0' or empty_L = '1') and grant_L_L = '1') then
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L <= '1';
else
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Final Grant output checkers
-- North
process (grant_N_N_sig, empty_N, grant_N_E_sig, empty_E, grant_N_W_sig, empty_W, grant_N_S_sig, empty_S, grant_N_L_sig, empty_L, grant_N)
begin
if ( ( (grant_N_N_sig = '1' and empty_N = '0' ) or (grant_N_E_sig = '1' and empty_E = '0') or (grant_N_W_sig = '1' and empty_W = '0') or
(grant_N_S_sig = '1' and empty_S = '0') or (grant_N_L_sig = '1' and empty_L = '0') ) and grant_N = '0' ) then
err_grant_signals_not_empty_grant_N <= '1';
else
err_grant_signals_not_empty_grant_N <= '0';
end if;
end process;
process (grant_N_N_sig, empty_N, grant_N_E_sig, empty_E, grant_N_W_sig, empty_W, grant_N_S_sig, empty_S, grant_N_L_sig, empty_L, grant_N)
begin
if ( ( (grant_N_N_sig = '0' or empty_N = '1' ) and (grant_N_E_sig = '0' and empty_E = '1') and (grant_N_W_sig = '0' or empty_W = '1') and
(grant_N_S_sig = '0' or empty_S = '1') and (grant_N_L_sig = '0' or empty_L = '1') ) and grant_N /= '0' ) then
err_not_grant_signals_empty_not_grant_N <= '1';
else
err_not_grant_signals_empty_not_grant_N <= '0';
end if;
end process;
-- East
process (grant_E_N_sig, empty_N, grant_E_E_sig, empty_E, grant_E_W_sig, empty_W, grant_E_S_sig, empty_S, grant_E_L_sig, empty_L, grant_E)
begin
if ( ( (grant_E_N_sig = '1' and empty_N = '0' ) or (grant_E_E_sig = '1' and empty_E = '0') or (grant_E_W_sig = '1' and empty_W = '0') or
(grant_E_S_sig = '1' and empty_S = '0') or (grant_E_L_sig = '1' and empty_L = '0') ) and grant_E = '0' ) then
err_grant_signals_not_empty_grant_E <= '1';
else
err_grant_signals_not_empty_grant_E <= '0';
end if;
end process;
process (grant_E_N_sig, empty_N, grant_E_E_sig, empty_E, grant_E_W_sig, empty_W, grant_E_S_sig, empty_S, grant_E_L_sig, empty_L, grant_E)
begin
if ( ( (grant_E_N_sig = '0' or empty_N = '1' ) and (grant_E_E_sig = '0' and empty_E = '1') and (grant_E_W_sig = '0' or empty_W = '1') and
(grant_E_S_sig = '0' or empty_S = '1') and (grant_E_L_sig = '0' or empty_L = '1') ) and grant_E /= '0' ) then
err_not_grant_signals_empty_not_grant_E <= '1';
else
err_not_grant_signals_empty_not_grant_E <= '0';
end if;
end process;
-- West
process (grant_W_N_sig, empty_N, grant_W_E_sig, empty_E, grant_W_W_sig, empty_W, grant_W_S_sig, empty_S, grant_W_L_sig, empty_L, grant_W)
begin
if ( ( (grant_W_N_sig = '1' and empty_N = '0' ) or (grant_W_E_sig = '1' and empty_E = '0') or (grant_W_W_sig = '1' and empty_W = '0') or
(grant_W_S_sig = '1' and empty_S = '0') or (grant_W_L_sig = '1' and empty_L = '0') ) and grant_W = '0' ) then
err_grant_signals_not_empty_grant_W <= '1';
else
err_grant_signals_not_empty_grant_W <= '0';
end if;
end process;
process (grant_W_N_sig, empty_N, grant_W_E_sig, empty_E, grant_W_W_sig, empty_W, grant_W_S_sig, empty_S, grant_W_L_sig, empty_L, grant_W)
begin
if ( ( (grant_W_N_sig = '0' or empty_N = '1' ) and (grant_W_E_sig = '0' and empty_E = '1') and (grant_W_W_sig = '0' or empty_W = '1') and
(grant_W_S_sig = '0' or empty_S = '1') and (grant_W_L_sig = '0' or empty_L = '1') ) and grant_W /= '0' ) then
err_not_grant_signals_empty_not_grant_W <= '1';
else
err_not_grant_signals_empty_not_grant_W <= '0';
end if;
end process;
-- South
process (grant_S_N_sig, empty_N, grant_S_E_sig, empty_E, grant_S_W_sig, empty_W, grant_S_S_sig, empty_S, grant_S_L_sig, empty_L, grant_S)
begin
if ( ( (grant_S_N_sig = '1' and empty_N = '0' ) or (grant_S_E_sig = '1' and empty_E = '0') or (grant_S_W_sig = '1' and empty_W = '0') or
(grant_S_S_sig = '1' and empty_S = '0') or (grant_S_L_sig = '1' and empty_L = '0') ) and grant_S = '0' ) then
err_grant_signals_not_empty_grant_S <= '1';
else
err_grant_signals_not_empty_grant_S <= '0';
end if;
end process;
process (grant_S_N_sig, empty_N, grant_S_E_sig, empty_E, grant_S_W_sig, empty_W, grant_S_S_sig, empty_S, grant_S_L_sig, empty_L, grant_S)
begin
if ( ( (grant_S_N_sig = '0' or empty_N = '1' ) and (grant_S_E_sig = '0' and empty_E = '1') and (grant_S_W_sig = '0' or empty_W = '1') and
(grant_S_S_sig = '0' or empty_S = '1') and (grant_S_L_sig = '0' or empty_L = '1') ) and grant_S /= '0' ) then
err_not_grant_signals_empty_not_grant_S <= '1';
else
err_not_grant_signals_empty_not_grant_S <= '0';
end if;
end process;
-- Local
process (grant_L_N_sig, empty_N, grant_L_E_sig, empty_E, grant_L_W_sig, empty_W, grant_L_S_sig, empty_S, grant_L_L_sig, empty_L, grant_L)
begin
if ( ( (grant_L_N_sig = '1' and empty_N = '0' ) or (grant_L_E_sig = '1' and empty_E = '0') or (grant_L_W_sig = '1' and empty_W = '0') or
(grant_L_S_sig = '1' and empty_S = '0') or (grant_L_L_sig = '1' and empty_L = '0') ) and grant_L = '0' ) then
err_grant_signals_not_empty_grant_L <= '1';
else
err_grant_signals_not_empty_grant_L <= '0';
end if;
end process;
process (grant_L_N_sig, empty_N, grant_L_E_sig, empty_E, grant_L_W_sig, empty_W, grant_L_S_sig, empty_S, grant_L_L_sig, empty_L, grant_L)
begin
if ( ( (grant_L_N_sig = '0' or empty_N = '1' ) and (grant_L_E_sig = '0' and empty_E = '1') and (grant_L_W_sig = '0' or empty_W = '1') and
(grant_L_S_sig = '0' or empty_S = '1') and (grant_L_L_sig = '0' or empty_L = '1') ) and grant_L /= '0' ) then
err_not_grant_signals_empty_not_grant_L <= '1';
else
err_not_grant_signals_empty_not_grant_L <= '0';
end if;
end process;
----------------------------------------------------------------
-- Valid output checkers
process (valid_N, valid_E, valid_W, valid_S, valid_L, grant_N, grant_E, grant_W, grant_S, grant_L)
begin
if (valid_N /= grant_N or valid_E /= grant_E or valid_W /= grant_W or valid_S /= grant_S or valid_L /= grant_L) then
err_grants_valid_not_match <= '1';
else
err_grants_valid_not_match <= '0';
end if;
end process;
END;
| gpl-3.0 | 1e298431759bec897014eac3138fbf01 | 0.572717 | 2.290287 | false | false | false | false |
Wynjones1/gbvhdl | testing/load_logic_tb.vhd | 1 | 2,998 | library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.types.all;
use work.interfaces.all;
entity load_logic_tb is
end;
architecture rtl of load_logic_tb is
component load_logic is
port( clk : in std_logic;
reset : in std_logic;
input : in load_logic_in_if;
output : out load_logic_out_if);
end component;
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal input : load_in_if;
signal output : load_out_if;
signal read_data_cmp : byte_t;
signal lineno : integer := 0;
begin
reset_gen : process
begin
reset <= '1';
wait for 40 ns;
reset <= '0';
wait;
end process;
clk_gen : process
begin
if clk = '1' then
clk <= '0';
wait for 10 ns;
else
clk <= '1';
wait for 10 ns;
end if;
end process;
run_test : process(clk, reset)
type state_t is (s0, s1, s2, s3);
variable state : state_t := s0;
file fp : text open read_mode is "/home/stuart/VHDL/gbvhdl/testing/tests/load_store.txt";
variable address_s : string(16 downto 1);
variable we_s : string( 1 downto 1);
variable wdata_s : string( 8 downto 1);
variable rdata_s : string( 8 downto 1);
variable dummy : string( 1 downto 1);
variable l : line;
begin
if reset = '1' then
input.address <= (others => '0');
elsif rising_edge(clk) then
case state is
when s0 =>
if endfile(fp) then
state := s3;
else
readline(fp, l);
read(l, address_s);
read(l, dummy);
read(l, we_s);
read(l, dummy);
read(l, wdata_s);
read(l, dummy);
read(l, rdata_s);
if we_s(1) = '1' then
input.we <= '1';
else
input.we <= '0';
end if;
input.address <= to_std_logic_vector(address_s);
input.data <= to_std_logic_vector(wdata_s);
read_data_cmp <= to_std_logic_vector(rdata_s);
state := s1;
end if;
when s1 =>
state := s0;
assert read_data_cmp = output.data;
lineno <= lineno + 1;
when s2 =>
state := s0;
when s3 =>
report "End of simulation" severity failure;
end case;
end if;
end process;
load_logic_0: load_logic
port map (clk, reset, input, output);
end rtl;
| mit | 9adfcbd4dd8b9ff984f7c64d5381fe12 | 0.45497 | 3.924084 | false | false | false | false |
SKravitsky/ECEC412 | MulticycleControl.vhd | 1 | 3,128 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MulticycleControl is
port(
Opcode: in std_logic_vector(5 downto 0);
clk: in std_logic;
RegDst, RegWrite, ALUSrcA, IRWrite, MemtoReg, MemWrite, MemRead, IorD, PCWrite, PCWriteCond: out std_logic;
ALUSrcB, ALUOp, PCSource: out std_logic_vector(1 downto 0)
);
end MulticycleControl;
architecture Structural of MulticycleControl is
signal reset: std_logic := '0';
signal memWriteLatch: std_logic := '0';
signal regWriteLatch: std_logic := '0';
begin
process(clk)
variable state: integer := 0;
begin
case state is
-- IF
when 0 =>
MemRead <= '1';
memWriteLatch <= '0';
MemtoReg <= '0';
ALUSrcA <= '0';
IorD <= '0';
IRWrite <= '1';
ALUSrcB <= "01";
ALUOp <= "00";
regWriteLatch <= '0';
RegDst <= '0';
PCWrite <= '1';
PCWriteCond <= '0';
PCSource <= "00";
-- ID
when 1 =>
ALUSrcA <= '0';
ALUSrcB <= "11";
ALUOp <= "00";
PCWrite <= '0';
IRWrite <= '0';
-- EX
when 2 =>
case Opcode is
-- R-Type
when "000000" =>
ALUSrcA <= '1';
ALUSrcB <= "00";
ALUOp <= "10";
-- LW/SW
when "100011" | "101011" =>
ALUSrcA <= '1';
ALUSrcB <= "10";
ALUOp <= "00";
-- BEQ
when "000100" =>
ALUSrcA <= '1';
ALUSrcB <= "00";
ALUOp <= "01";
PCWriteCond <= '1';
PCSource <= "01";
reset <= '1';
-- J
when "000010" =>
PCWrite <= '1';
PCSource <= "10";
reset <= '1';
when others =>
null;
end case;
-- MEM
when 3 =>
case Opcode is
-- R-Type
when "000000" =>
RegDst <= '1';
regWriteLatch <= '1';
MemtoReg <= '0';
reset <= '1';
-- LW
when "100011" =>
MemRead <= '1';
IorD <= '1';
-- SW
when "101011" =>
memWriteLatch <= '1';
IorD <= '1';
when others =>
null;
end case;
-- WB
when 4 =>
case Opcode is
-- LW
when "100011" =>
regWriteLatch <= '1';
MemtoReg <= '1';
RegDst <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
if falling_edge(clk) then
if memWriteLatch='1' then
MemWrite <= '1';
end if;
if regWriteLatch='1' then
RegWrite <= '1';
end if;
if state = 4 or reset = '1' then
-- Wrap back from WB to IF
state := 0;
reset <= '0';
else
-- Proceed to next stage
state := state + 1;
end if;
end if;
if rising_edge(clk) then
MemWrite <= '0';
RegWrite <= '0';
end if;
end process;
end Structural;
| apache-2.0 | b4a16f768e5687e34393889cb3f19424 | 0.427749 | 4.176235 | false | false | false | false |
siavooshpayandehazad/NoC_Router | FPGA-integration/RTL/NI_AXI_handshake_wrapper.vhd | 3 | 5,784 | -- Copyright (C) Karl Janson 2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AXI_handshake_wrapper is
generic (
DATA_WIDTH : integer := 32;
NI_DEPTH : integer := 16
);
port (
reset : in std_logic;
clk : in std_logic;
--Router connection
R_RX : in std_logic_vector(DATA_WIDTH-1 downto 0);
R_TX : out std_logic_vector(DATA_WIDTH-1 downto 0);
R_DRTS : in std_logic;
R_DCTS : in std_logic;
R_RTS : out std_logic;
R_CTS : out std_logic;
-- Abstraction signals for AXI
AXI_RX_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
AXI_RX_IRQ_out : out std_logic;
AXI_data_read_in : in std_logic;
AXI_TX_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
AXI_send_en : in std_logic
);
end AXI_handshake_wrapper;
architecture Behavioral of AXI_handshake_wrapper is
component NI is
generic (
DATA_WIDTH : integer := 32;
NI_DEPTH : integer := 16
);
port (
reset : in std_logic;
clk : in std_logic;
RX1 : in std_logic_vector(DATA_WIDTH-1 downto 0);
TX1 : out std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS1 : in std_logic;
DCTS1 : in std_logic;
RTS1 : out std_logic;
CTS1 : out std_logic;
RX2 : in std_logic_vector(DATA_WIDTH-1 downto 0);
TX2 : out std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS2 : in std_logic;
DCTS2 : in std_logic;
RTS2 : out std_logic;
CTS2 : out std_logic
);
end component;
signal PE_TX : std_logic_vector(DATA_WIDTH-1 downto 0);
signal PE_RX : std_logic_vector(DATA_WIDTH-1 downto 0);
signal PE_DRTS : std_logic;
signal PE_DCTS : std_logic;
signal PE_RTS : std_logic;
signal PE_CTS : std_logic;
type send_state_type is (S_IDLE, S_SEND);
type recv_state_type is (S_IDLE, S_RECV, S_WAIT);
signal send_state : send_state_type;
signal recv_state : recv_state_type;
signal RX_en : std_logic;
signal TX_en : std_logic;
signal axi_data_read : std_logic;
signal AXI_RX_IRQ : std_logic;
signal AXI_RX : std_logic_vector(DATA_WIDTH-1 downto 0);
signal AXI_data_read_prev : std_logic;
begin
Network_interface: NI
generic map(
DATA_WIDTH => DATA_WIDTH,
NI_DEPTH => NI_DEPTH)
port map (
reset => reset,
clk => clk,
-- Router connection
RX1 => R_RX,
DRTS1 => R_DRTS,
CTS1 => R_CTS,
TX2 => R_TX,
DCTS2 => R_DCTS,
RTS2 => R_RTS,
-- AXI PE emulation connection
TX1 => PE_RX,
DCTS1 => PE_CTS,
RTS1 => PE_DRTS,
RX2 => PE_TX,
DRTS2 => PE_RTS,
CTS2 => PE_DCTS
);
-- FSM for sending data from AXI to the NI
AXI_TX_FSM: process (clk, reset)
begin
if (reset = '0') then
PE_RTS <= '0';
TX_en <= '0';
send_state <= S_IDLE;
elsif (clk'event and clk = '1') then
case send_state is
when S_IDLE =>
if (AXI_send_en = '1') then
PE_RTS <= '1';
TX_en <= '1';
send_state <= S_SEND;
else
TX_en <= '0';
end if;
when S_SEND =>
if (PE_DCTS = '1') then
PE_RTS <= '0';
send_state <= S_IDLE;
end if;
when others =>
PE_RTS <= '0';
TX_en <= '0';
send_state <= S_IDLE;
end case;
end if;
end process AXI_TX_FSM;
-- FSM for receiving data from the NI to teh AXI bus
AXI_RX_FSM: process (clk, reset)
begin
if (reset = '0') then
PE_CTS <= '0';
RX_en <= '0';
AXI_RX_IRQ <= '0';
recv_state <= S_IDLE;
AXI_data_read <= '1';
elsif (clk'event and clk = '1') then
case recv_state is
when S_IDLE =>
if (AXI_data_read = '1') then
if (PE_DRTS = '1') then
PE_CTS <= '1';
RX_en <= '1';
AXI_RX_IRQ <= '0';
recv_state <= S_RECV;
end if;
else
if (AXI_data_read_in = '1') then
AXI_data_read <= '1';
end if;
end if;
when S_RECV =>
RX_en <= '0';
PE_CTS <= '0';
AXI_RX_IRQ <= '1';
AXI_data_read <= '0';
recv_state <= S_IDLE;
when others =>
PE_CTS <= '0';
RX_en <= '0';
AXI_RX_IRQ <= '0';
recv_state <= S_IDLE;
end case;
end if;
end process AXI_RX_FSM;
RX_store: process (clk, reset)
begin
if (reset = '0') then
AXI_RX <= (others => '0');
elsif (clk'event and clk = '1') then
if (RX_en = '1') then
AXI_RX <= PE_RX;
else
AXI_RX <= AXI_RX;
end if;
end if;
end process RX_store;
PE_TX <= AXI_TX_in when TX_en = '1' else
(others => '0') when TX_en = '0';
AXI_RX_IRQ_out <= AXI_RX_IRQ;
AXI_RX_out <= AXI_RX;
end Behavioral;
| gpl-3.0 | 3a2b086b339e88e52177e1d50dc35141 | 0.435685 | 3.467626 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/Testbenches/ram_stub_xilinx_for_questa.vhd | 3 | 3,024 | -- In Questasim simulation. because i cant add actual xilinx rams, since they use unisim libraries. I can export libraries but can not put it on git for license issues.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
entity ram_0 is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 8);
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram_0 is
begin
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
entity ram_1 is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 8);
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram_1 is
begin
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
entity ram_2 is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 8);
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram_2 is
begin
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
entity ram_3 is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 8);
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram_3 is
begin
end;
| gpl-3.0 | fb84c26d31059ea5497a3844c7d9907c | 0.588955 | 3.591449 | false | false | false | false |
SKravitsky/ECEC412 | PipelineControl.vhd | 1 | 1,551 | library ieee;
use ieee.std_logic_1164.all;
entity PipelineControl is
port(
Opcode: in std_logic_vector(5 downto 0);
ALUSrc, Branch, MemRead, MemWrite, MemtoReg, RegDst, RegWrite: out std_logic;
ALUOp: out std_logic_vector(1 downto 0)
);
end PipelineControl;
architecture Structural of PipelineControl is
begin
process(Opcode)
begin
case Opcode is
when "000000" => --add/sub
RegDst <= '1';
Branch <= '0';
MemRead <= '0';
MemtoReg <= '0';
MemWrite <= '0';
ALUSrc <= '0';
RegWrite <= '1';
ALUOp <= "10";
when "100011" => --lw
RegDst <= '0';
Branch <= '0';
MemRead <= '1';
MemtoReg <= '1';
MemWrite <= '0';
ALUSrc <= '1';
RegWrite <= '1';
ALUOp <= "00";
when "000100" => --beq
RegDst <= '0';
Branch <= '1';
MemRead <= '0';
MemtoReg <= '0';
MemWrite <= '0';
ALUSrc <= '0';
RegWrite <= '0';
ALUOp <= "01";
when "000010" => --j
RegDst <= '0';
Branch <= '1';
MemRead <= '0';
MemtoReg <= '0';
MemWrite <= '0';
ALUSrc <= '0';
RegWrite <= '0';
ALUOp <= "00";
when "101011" => --sw
RegDst <= '0';
Branch <= '0';
MemRead <= '0';
MemtoReg <= '0';
MemWrite <= '1';
ALUSrc <= '1';
RegWrite <= '0';
ALUOp <= "00";
when others =>
null;
end case;
end process;
end Structural;
| apache-2.0 | 3d0306cf81e615e65d19a8134537c4c8 | 0.449387 | 3.858209 | false | false | false | false |
elainemielas/CVUT_BI-PNO | cvika/scit1/tb_scit1.vhd | 1 | 783 | library IEEE;
use IEEE.std_logic_1164.all;
entity TB_SCIT1 is
end entity TB_SCIT1;
architecture TB_SCIT1_BODY of TB_SCIT1 is
signal T_A, T_B, T_CIN, T_S, T_COUT : std_logic;
component SCIT1 is
port (A, B, CIN : in std_logic;
COUT, S : out std_logic
);
end component SCIT1;
begin
UUT : SCIT1 port map ( A => T_A, B => T_B, CIN => T_CIN, COUT => T_COUT, S => T_S );
SIGNAL_A : process
begin
wait for 400 ns;
T_A <= '1';
wait for 400 ns;
T_A <= '0';
end process SIGNAL_A;
SIGNAL_B : process
begin
wait for 200 ns;
T_B <= '1';
wait for 200 ns;
T_B <= '0';
end process SIGNAL_B;
SIGNAL_CIN : process
begin
wait for 100 ns;
T_CIN <= '1';
wait for 100 ns;
T_CIN <= '0';
end process SIGNAL_CIN;
end architecture TB_SCIT1_BODY; | mit | 32ed7b8d2f1e944f51697799d1801dce | 0.60281 | 2.462264 | false | false | false | false |
simoesusp/Processador-ICMC | Software_Assembly/IR_Controller/Processor_IR_PWM_DE2_70/cpu.vhd | 1 | 36,812 | libraRY ieee;
use ieee.std_LOGIC_1164.all;
use ieee.std_LOGIC_ARITH.all;
use ieee.std_LOGIC_unsigned.all;
--use IEEE.NUMERIC_STD.all;
entity cpu is
port( clk : in std_LOGIC;
reset : in std_LOGIC;
Mem : in STD_LOGIC_VECTOR(15 downto 0);
M5 : out STD_LOGIC_VECTOR(15 downto 0);
M1 : out STD_LOGIC_VECTOR(15 downto 0);
RW : out std_LOGIC;
key : in STD_LOGIC_VECTOR(7 downto 0);
videoflag : out std_LOGIC;
vga_pos : out STD_LOGIC_VECTOR(15 downto 0);
vga_char : out STD_LOGIC_VECTOR(15 downto 0);
Ponto : out STD_LOGIC_VECTOR(2 downto 0);
halt_ack : out std_LOGIC;
halt_req : in std_LOGIC;
PC_data : out STD_LOGIC_VECTOR(15 downto 0);
break : out STD_LOGIC;
pwm_out : out std_logic;
pwm_out2 : out std_logic;
ir_in : in std_logic_vector(7 downto 0);
DISPLAY1 : out std_logic_VECTOR(3 downto 0);
DISPLAY2 : out std_logic_VECTOR(3 downto 0);
DISPLAY3 : out std_logic_VECTOR(3 downto 0);
DISPLAY4 : out std_logic_VECTOR(3 downto 0);
DISPLAY5 : out std_logic_VECTOR(3 downto 0);
DISPLAY6 : out std_logic_VECTOR(3 downto 0);
DISPLAY7 : out std_logic_VECTOR(3 downto 0);
DISPLAY8 : out std_logic_VECTOR(3 downto 0)
);
end cpu;
ARCHITECTURE main of cpu is
TYPE STATES is (fetch, decode, exec, halted); -- Estados da Maquina de Controle do Processador
TYPE Registers is array(0 to 7) of STD_LOGIC_VECTOR(15 downto 0); -- Banco de Registradores
TYPE LoadRegisters is array(0 to 7) of std_LOGIC; -- Sinais de LOAD dos Registradores do Banco
-- INSTRUCTION SET: 29 INSTRUCTIONS
-- Data Manipulation Instructions: -- Usage -- Action -- Format
CONSTANT LOAD : STD_LOGIC_VECTOR(5 downto 0) := "110000"; -- LOAD RX END -- RX <- M[END] Format: < inst(6) | RX(3) | xxxxxxx > + 16bit END
CONSTANT STORE : STD_LOGIC_VECTOR(5 downto 0) := "110001"; -- STORE END RX -- M[END] <- RX Format: < inst(6) | RX(3) | xxxxxxx > + 16bit END
CONSTANT LOADIMED : STD_LOGIC_VECTOR(5 downto 0) := "111000"; -- LOADN RX Nr -- RX <- Nr Format: < inst(6) | RX(3) | xxxxxxb0 > + 16bit Numero
CONSTANT LOADINDEX : STD_LOGIC_VECTOR(5 downto 0) := "111100"; -- LOADI RX RY -- RX <- M[RY] Format: < inst(6) | RX(3) | RY(3) | xxxx >
CONSTANT STOREINDEX : STD_LOGIC_VECTOR(5 downto 0) := "111101"; -- STOREI RX RY -- M[RX] <- RY Format: < inst(6) | RX(3) | RY(3) | xxxx >
CONSTANT MOV : STD_LOGIC_VECTOR(5 downto 0) := "110011"; -- MOV RX RY -- RX <- RY Format: < inst(6) | RX(3) | RY(3) | xx | x0 >
-- MOV RX SP RX <- SP Format: < inst(6) | RX(3) | xxx | xx | 01 >
-- MOV SP RX SP <- RX Format: < inst(6) | RX(3) | xxx | xx | 11 >
-- I/O Instructions:
CONSTANT OUTCHAR : STD_LOGIC_VECTOR(5 downto 0) := "110010"; -- OUTCHAR RX RY -- Video[RY] <- Char(RX) Format: < inst(6) | RX(3) | RY(3) | xxxx >
-- RX contem o codigo do caracter de 0 a 127, sendo que 96 iniciais estao prontos com a tabela ASCII
-- RX(6 downto 0) + 32 = Caractere da tabela ASCII - Ver Manual PDF
-- RX(10 downto 7) = Cor : 0-branco, 1-marrom, 2-verde, 3-oliva, 4-azul marinho, 5-roxo, 6-teal, 7-prata, 8-cinza, 9-vermelho, 10-lima, 11-amarelo, 12-azul, 13-rosa, 14-aqua, 15-preto
-- RY(10 downto 0) = tamanho da tela = 30 linhas x 40 colunas: posicao continua de 0 a 1199 no RY
CONSTANT INCHAR : STD_LOGIC_VECTOR(5 downto 0) := "110101"; -- INCHAR RX -- RX[5..0] <- KeyPressed RX[15..6] <- 0's Format: < inst(6) | RX(3) | xxxxxxx >
-- Se nao pressionar nenhuma tecla, RX recebe 00FF
CONSTANT ARITH : STD_LOGIC_VECTOR(1 downto 0) := "10";
-- Aritmethic Instructions(All should begin wiht "10"):
CONSTANT ADD : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- ADD RX RY RZ / ADDC RX RY RZ -- RX <- RY + RZ / RX <- RY + RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT SUB : STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- SUB RX RY RZ / SUBC RX RY RZ -- RX <- RY - RZ / RX <- RY - RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT MULT : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- MUL RX RY RZ / MUL RX RY RZ -- RX <- RY * RZ / RX <- RY * RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT DIV : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- DIV RX RY RZ -- RX <- RY / RZ / RX <- RY / RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT INC : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- INC RX / DEC RX -- RX <- RX + 1 / RX <- RX - 1 -- b6= INC/DEC : 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx >
CONSTANT LMOD : STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- MOD RX RY RZ -- RX <- RY MOD RZ Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LOGIC : STD_LOGIC_VECTOR(1 downto 0) := "01";
-- LOGIC Instructions (All should begin wiht "01"):
CONSTANT LAND : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- AND RX RY RZ -- RZ <- RX AND RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LOR : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- OR RX RY RZ -- RZ <- RX OR RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LXOR : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- XOR RX RY RZ -- RZ <- RX XOR RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LNOT : STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- NOT RX RY -- RX <- NOT(RY) Format: < inst(6) | RX(3) | RY(3) | xxxx >
CONSTANT SHIFT : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- SHIFTL0 RX,n / SHIFTL1 RX,n / SHIFTR0 RX,n / SHIFTR1 RX,n / ROTL RX,n / ROTR RX,n
-- SHIFT/Rotate RX -- b6=shif/rotate: 0/1 b5=left/right: 0/1; b4=fill;
-- Format: < inst(6) | RX(3) | b6 b5 b4 | nnnn >
CONSTANT CMP : STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- CMP RX RY -- Compare RX and RY and set FR : Format: < inst(6) | RX(3) | RY(3) | xxxx > Flag Register: <...DIVbyZero|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
-- JMP Condition: (UNconditional, EQual, Not Equal, Zero, Not Zero, CarRY, Not CarRY, GReater, LEsser, Equal or Greater, Equal or Lesser, OVerflow, Not OVerflow, Negative, DIVbyZero, NOT USED)
-- FLOW CONTROL Instructions:
CONSTANT JMP : STD_LOGIC_VECTOR(5 downto 0) := "000010"; -- JMP END -- PC <- 16bit END : b9-b6 = COND Format: < inst(6) | COND(4) | xxxxxx > + 16bit END
CONSTANT CALL : STD_LOGIC_VECTOR(5 downto 0) := "000011"; -- CALL END -- M[SP] <- PC | SP-- | PC <- 16bit END : b9-b6 = COND Format: < inst(6) | COND(4) | xxxxxx > + 16bit END
CONSTANT RTS : STD_LOGIC_VECTOR(5 downto 0) := "000100"; -- RTS -- SP++ | PC <- M[SP] | b6=RX/FR: 1/0 Format: < inst(6) | xxxxxxxxxx >
CONSTANT PUSH : STD_LOGIC_VECTOR(5 downto 0) := "000101"; -- PUSH RX / PUSH FR -- M[SP] <- RX / M[SP] <- FR | SP-- : b6=RX/FR: 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx >
CONSTANT POP : STD_LOGIC_VECTOR(5 downto 0) := "000110"; -- POP RX / POP FR -- SP++ | RX <- M[SP] / FR <- M[SP] : b6=RX/FR: 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx >
-- Control Instructions:
CONSTANT NOP : STD_LOGIC_VECTOR(5 downto 0) := "000000"; -- NOP -- Do Nothing Format: < inst(6) | xxxxxxxxxx >
CONSTANT HALT : STD_LOGIC_VECTOR(5 downto 0) := "001111"; -- HALT -- StOP Here Format: < inst(6) | xxxxxxxxxx >
CONSTANT SETC : STD_LOGIC_VECTOR(5 downto 0) := "001000"; -- CLEARC / SETC -- Set/Clear CarRY: b9 = 1-set; 0-clear Format: < inst(6) | b9 | xxxxxxxxx >
CONSTANT BREAKP : STD_LOGIC_VECTOR(5 downto 0) := "001110"; -- BREAK POINT -- Switch to manual clock Format: < inst(6) | xxxxxxxxxx >
-- Instrucoes Novas:
CONSTANT STORE2 : STD_LOGIC_VECTOR(5 downto 0) := "111111";
CONSTANT LOAD2 : STD_LOGIC_VECTOR(5 downto 0) := "111110";
-- instrucao nova do IR
constant IR_instr : std_logic_vector(5 downto 0) := "100111";
-- CONSTANTes para controle do Mux2
CONSTANT sULA : STD_LOGIC_VECTOR (2 downto 0) := "000";
CONSTANT sMem : STD_LOGIC_VECTOR (2 downto 0) := "001";
CONSTANT sM4 : STD_LOGIC_VECTOR (2 downto 0) := "010";
--CONSTANT skey : STD_LOGIC_VECTOR (2 downto 0) := "011";
CONSTANT sTECLADO : STD_LOGIC_VECTOR (2 downto 0) := "011"; -- nao tinha
CONSTANT sSP : STD_LOGIC_VECTOR (2 downto 0) := "100";
-- CONSTANTes para controle do Mux2
-- CONSTANT sULA : STD_LOGIC_VECTOR(1 downto 0) := "00";
-- CONSTANT sMem : STD_LOGIC_VECTOR(1 downto 0) := "01";
-- CONSTANT sM4 : STD_LOGIC_VECTOR(1 downto 0) := "10";
-- CONSTANT skey : STD_LOGIC_VECTOR(1 downto 0) := "11";
-- Sinais para o Processo da ULA
signal OP : STD_LOGIC_VECTOR(6 downto 0); -- OP(6) deve ser setado para OPeracoes com carRY
signal x, y, result : STD_LOGIC_VECTOR(15 downto 0);
signal FR : STD_LOGIC_VECTOR(15 downto 0); -- Flag Register: <...DIVbyZero|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
signal auxFR : STD_LOGIC_VECTOR(15 downto 0); -- Representa um barramento conectando a ULA ao Mux6 para escrever no FR
------------- Registradores de uso especifico ------------
TYPE Registers2 is array(0 to 15) of STD_LOGIC_VECTOR(15 downto 0); -- Banco de Registradores
signal reg2 : Registers2;
------------- Registradores de uso especifico ------------
begin
-- Maquina de Controle
process(clk, reset)
--Register Declaration:
variable PC : STD_LOGIC_VECTOR(15 downto 0); -- Program Counter
variable IR : STD_LOGIC_VECTOR(15 downto 0); -- Instruction Register
variable SP : STD_LOGIC_VECTOR(15 downto 0); -- Stack Pointer
variable MAR : STD_LOGIC_VECTOR(15 downto 0); -- Memory address Register
VARIABLE TECLADO :STD_LOGIC_VECTOR(15 downto 0); -- Registrador para receber dados do teclado -- nao tinha
variable reg : Registers;
-- Mux dos barramentos de dados internos
VARIABLE M2 :STD_LOGIC_VECTOR(15 downto 0); -- Mux dos barramentos de dados internos para os Registradores
VARIABLE M3, M4 :STD_LOGIC_VECTOR(15 downto 0); -- Mux dos Registradores para as entradas da ULA
-- Novos Sinais da V2
variable LoadReg : LoadRegisters;
variable LoadIR : std_LOGIC;
variable LoadMAR : std_LOGIC;
variable LoadPC : std_LOGIC;
variable IncPC : std_LOGIC;
VARIABLE LoadSP : STD_LOGIC;
variable IncSP : std_LOGIC;
variable DecSP : std_LOGIC;
variable selM2 : STD_LOGIC_VECTOR(2 downto 0); -- VARIABLE selM2 :STD_LOGIC_VECTOR (2 downto 0);
variable selM6 : STD_LOGIC_VECTOR(2 downto 0); -- VARIABLE selM6 :STD_LOGIC_VECTOR (2 downto 0);
VARIABLE BreakFlag : STD_LOGIC;
variable state : STATES;
variable RX : integer;
variable RY : integer;
variable RZ : integer;
variable fixColor : std_logic_vector(15 downto 0);
begin
DISPLAY5 <= REG(7)(3 DOWNTO 0);
DISPLAY6 <= REG(7)(7 DOWNTO 4);
if(reset = '1') then
state := fetch;
M1(15 downto 0) <= x"0000";
videoflag <= '0';
RX := 0;
RY := 0;
RZ := 0;
RW <= '0';
LoadIR := '0';
LoadMAR := '0';
LoadPC := '0';
IncPC := '0';
IncSP := '0';
DecSP := '0';
selM2 := sMem;
selM6 := sULA;
LoadReg(0) := '0';
LoadReg(1) := '0';
LoadReg(2) := '0';
LoadReg(3) := '0';
LoadReg(4) := '0';
LoadReg(5) := '0';
LoadReg(6) := '0';
LoadReg(7) := '0';
REG(0) := x"0000";
REG(1) := x"0000";
REG(2) := x"0000";
REG(3) := x"0000";
REG(4) := x"0000";
REG(5) := x"0000";
REG(6) := x"0000";
REG(7) := x"0000";
PC := x"0000";
SP := x"3ffc"; -- 7ffc
IR := x"0000";
MAR := x"0000";
-- TECLADO := x"0000";
BreakFlag:= '0'; -- Break Point Flag
BREAK <= '0'; -- Break Point output to switch to manual clock
-- nao tinha
HALT_ack <= '0';
elsif(clk'event and clk = '1') then
if(LoadIR = '1') then IR := Mem; end if;
if(LoadPC = '1') then PC := Mem; end if;
if(IncPC = '1') then PC := PC + x"0001"; end if;
if(LoadMAR = '1') then MAR := Mem; end if;
if(LoadSP = '1') then SP := M3; end if;
if(IncSP = '1') then SP := SP + x"0001"; end if;
if(DecSP = '1') then SP := SP - x"0001"; end if;
-- Selecao do Mux6
if (selM6 = sULA) THEN FR <= auxFR; -- Sempre recebe flags da ULA
ELSIF (selM6 = sMem) THEN FR <= Mem; END IF; -- A menos que seja POP FR, quando recebe da Memoria
-- Atualiza o nome dos registradores!!!
RX := conv_integer(IR(9 downto 7));
RY := conv_integer(IR(6 downto 4));
RZ := conv_integer(IR(3 downto 1));
-- Selecao do Mux2
if (selM2 = sULA) THEN M2 := RESULT;
ELSIF (selM2 = sMem) THEN M2 := Mem;
ELSIF (selM2 = sM4) THEN M2 := M4;
--ELSIF (selM2 = skey) THEN M2(15 downto 8) := x"00";
-- M2(7 downto 0) := key;
ELSIF (selM2 = sTECLADO)THEN M2 := TECLADO;
ELSIF (selM2 = sSP) THEN M2 := SP;
END IF;
-- if (LoadReg(RX) = '1') then REG(RX) := M2; end if;
if(LoadReg(RX) = '1') then reg(RX) := m2; end if;
-- Reseta os sinais de controle APOS usa-los acima
-- Zera todos os sinais de controle, para depois ligar um por um a medida que for necessario: a ultima atribuicao e' a que vale no processo!!!
LoadIR := '0';
LoadMAR := '0';
LoadPC := '0';
IncPC := '0';
IncSP := '0';
DecSP := '0';
LoadSP := '0';
selM6 := sULA; -- Sempre atualiza o FR da ULA, a nao ser que a instrucao seja POP FR
LoadReg(0) := '0';
LoadReg(1) := '0';
LoadReg(2) := '0';
LoadReg(3) := '0';
LoadReg(4) := '0';
LoadReg(5) := '0';
LoadReg(6) := '0';
LoadReg(7) := '0';
videoflag <= '0';
RW <= '0';
-- nao tinha
if(halt_req = '1') then state := halted; end if;
PC_data <= PC;
case state is
--************************************************************************
-- FETCH STATE
--************************************************************************
when fetch =>
PONTO <= "001";
-- Inicio das acoes do ciclo de Busca !!
M1 <= PC;
RW <= '0';
LoadIR := '1';
IncPC := '1';
STATE := decode;
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--************************************************************************
-- DECODE STATE
--************************************************************************
when decode =>
PONTO <= "010";
--========================================================================
-- INCHAR RX[5..0] <- KeyPressed RX[15..6] <- 0
--========================================================================
IF(IR(15 DOWNTO 10) = INCHAR) THEN
--selM2 := skey;
--LoadReg(RX) := '1';
--state := fetch;
TECLADO(7 downto 0) := key(7 downto 0);
TECLADO(15 downto 8) := X"00";
-- copia somente os 6 bits da tecla, os bits 7 e 6 sao a cor do caractere
if(key(7 downto 0) /= X"FF") then
--TECLADO(7 downto 6) := "00";
TECLADO(7) := '0';
end if;
selM2 := sTECLADO;
LoadReg(RX) := '1';
state := fetch;
END IF;
--========================================================================
-- OUTCHAR Video[RY] <- Char(RX)
--========================================================================
IF(IR(15 DOWNTO 10) = OUTCHAR) THEN
M3 := Reg(Rx); -- M3 <- Rx
M4 := Reg(Ry); -- M4 <- Ry
fixColor := M3;
if( fixColor(11 downto 8) = "0000" ) then
fixColor(11 downto 8) := "1111";
elsif( fixColor(11 downto 8) = "1111" ) then
fixColor(11 downto 8) := "0000";
end if;
vga_char <= fixColor; --vga_char <= M3;
vga_pos <= M4;
videoflag <= '1';
state := fetch;
END IF;
--========================================================================
-- MOV RX/SP <- RY/SP
-- MOV RX RY RX <- RY Format: < inst(6) | RX(3) | RY(3) | xx | x0 >
-- MOV RX SP RX <- SP Format: < inst(6) | RX(3) | xxx | xx | 01 >
-- MOV SP RX SP <- RX Format: < inst(6) | RX(3) | xxx | xx | 11 >
--========================================================================
IF(IR(15 DOWNTO 10) = MOV) THEN
IF(IR(0) = '0') THEN
M4 := REG(RY);
selM2 := sM4;
LoadReg(RX) := '1';
ELSE
IF(IR(1) = '0') THEN
selM2 := sSP;
LoadReg(RX) := '1';
ELSE
M3 := REG(RX);
LoadSP := '1';
END IF;
END IF;
state := fetch;
END IF;
--========================================================================
-- STORE DIReto M[END] <- RX
--========================================================================
IF(IR(15 DOWNTO 10) = STORE) THEN -- Busca o endereco
M1 <= PC;
RW <= '0';
LoadMAR := '1';
IncPC := '1';
state := exec;
END IF;
--========================================================================
-- STORE indexado por registrador M[RX] <- RY
--========================================================================
IF(IR(15 DOWNTO 10) = STOREINDEX) THEN
M4 := Reg(Rx); -- M4 <- Rx
M1 <= M4; -- M1 <- M4
M3 := Reg(Ry); -- M3 <- Ry
M5 <= M3;
Rw <= '1'; -- Rw <- 1
state := fetch;
END IF;
--========================================================================
-- LOAD Direto RX <- M[End]
--========================================================================
IF(IR(15 DOWNTO 10) = LOAD) THEN -- Busca o endereco
M1 <= PC; -- M1 <- PC
Rw <= '0'; -- Rw <- 0
LoadMAR := '1';-- LMAR <- 1
IncPC := '1';
state := exec;
END IF;
--========================================================================
-- LOAD Imediato RX <- Nr
--========================================================================
IF(IR(15 DOWNTO 10) = LOADIMED) THEN
M1 <= PC; -- M1 <- PC
Rw <= '0'; -- Rw <= '0'
selM2 := sMeM; -- LRx <- 1
LoadReg(RX) := '1'; -- IncPC <- 1
IncPC := '1'; -- M2 <- MEM
state := fetch;
END IF;
--========================================================================
-- LOAD Indexado por registrador RX <- M(RY)
--========================================================================
IF(IR(15 DOWNTO 10) = LOADINDEX) THEN
M4 := Reg(Ry); -- M4 <- Ry
M1 <= M4; -- M1 <- M4
Rw <= '0'; -- Rw <- 0
selM2 := sMEM; -- M2 <- MEM
LoadReg(Rx) := '1'; -- LRx <- 1
state := fetch;
END IF;
--========================================================================
-- LOGIC OPERATION ('SHIFT', 'CMP' AND 'NOT' NOT INCLUDED) RX <- RY (?) RZ
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) /= SHIFT AND IR(13 DOWNTO 10) /= LNOT AND IR(13 DOWNTO 10) /= CMP) THEN
M3 := Reg(Ry);
M4 := Reg(Rz);
X <= M3;
Y <= M4;
OP(5 downto 0 ) <= IR(15 downto 10);
selM2 := sULA;
LoadReg(Rx) := '1';
state := fetch;
END IF;
--========================================================================
-- NOT RX, RY RX <- NOT(RY)
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) = LNOT) THEN
M3 := REG(RX);
M4 := REG(RY);
X <= M3;
Y <= M4;
OP(5 downto 0) <= IR(15 downto 10);
selM2 := sULA;
LoadReg(Rx) := '1';
state := fetch;
END IF;
--========================================================================
-- CMP RX, RY
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) = CMP) THEN
M3 := Reg(Rx);
M4 := Reg(Ry);
X <= M3;
Y <= M4;
OP(5 downto 0 ) <= IR(15 downto 10);
state := fetch;
END IF;
--========================================================================
-- SHIFT RX, RY RX <- SHIFT[ RY] ROTATE INCluded !
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC and (IR(13 DOWNTO 10) = SHIFT)) THEN
if(IR(6 DOWNTO 4) = "000") then -- SHIFT LEFT 0
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))sll conv_integer(IR(3 DOWNTO 0)));
elsif(IR(6 DOWNTO 4) = "001") then -- SHIFT LEFT 1
Reg(RX) := not (To_StdLOGICVector(to_bitvector(not Reg(RY))sll conv_integer(IR(3 DOWNTO 0))));
elsif(IR(6 DOWNTO 4) = "010") then -- SHIFT RIGHT 0
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))srl conv_integer(IR(3 DOWNTO 0)));
elsif(IR(6 DOWNTO 4) = "011") then -- SHIFT RIGHT 0
Reg(RX) := not (To_StdLOGICVector(to_bitvector(not Reg(RY))srl conv_integer(IR(3 DOWNTO 0))));
elsif(IR(6 DOWNTO 5) = "11") then -- ROTATE RIGHT
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))ror conv_integer(IR(3 DOWNTO 0)));
elsif(IR(6 DOWNTO 5) = "10") then -- ROTATE LEFT
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))rol conv_integer(IR(3 DOWNTO 0)));
end if;
state := fetch;
end if;
--========================================================================
-- JMP END PC <- 16bit END : b9-b6 = COND
-- Flag Register: <...|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
--========================================================================
IF(IR(15 DOWNTO 10) = JMP) THEN
if((IR(9 downto 6) = "0000") or -- NO COND
(IR(9 downto 6) = "0111" and FR(0) = '1') or -- GREATER
(IR(9 downto 6) = "1001" and FR(2 downto 0) = "101") or -- greater equal
(IR(9 downto 6) = "1000" and FR(1) = '1') or -- lesser
(IR(9 downto 6) = "1010" and FR(2 downto 0) = "110") or -- lesser equal
(IR(9 downto 6) = "0001" and FR(2) = '1') or -- equal
(IR(9 downto 6) = "0010" and FR(2) = '0') or -- not equal
(IR(9 downto 6) = "0011" and FR(3) = '1') or -- zero
(IR(9 downto 6) = "0100" and FR(3) = '0') or -- not zero
(IR(9 downto 6) = "0101" and FR(4) = '1') or -- carry
(IR(9 downto 6) = "0110" and FR(4) = '0') or -- not carry
(IR(9 downto 6) = "1011" and FR(5) = '1') or -- overflow
(IR(9 downto 6) = "1100" and FR(5) = '0') or -- not overflow
(IR(9 downto 6) = "1101" and FR(6) = '1') or -- DIV0
(IR(9 downto 6) = "1110" and FR(9) = '1')) then -- result negative
M1 <= PC;
RW <= '0';
LoadPC := '1';
else
IncPC := '1';
end if;
state := fetch;
END IF;
--========================================================================
-- PUSH RX
--========================================================================
IF(IR(15 DOWNTO 10) = PUSH) THEN
M1 <= SP; -- M1 <- SP
Rw <= '1'; -- R/W <- 1
if(IR(6) = '0') then
M3 := Reg(Rx); -- M3 <- Rx
elsif(IR(6) = '1') then
M3 := FR;
end if;
M5 <= M3; -- M5 <- M3
DecSP := '1'; -- DecSP <- 1
state := fetch;
END IF;
--========================================================================
-- POP RX
--========================================================================
IF(IR(15 DOWNTO 10) = POP) THEN
IncSP := '1';
state := exec;
END IF;
--========================================================================
-- CALL END PC <- 16bit END : b9-b6 = COND PUSH(PC)
-- Flag Register: <...|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
--========================================================================
IF(IR(15 DOWNTO 10) = CALL) THEN
if((IR(9 downto 6) = "0000") or -- NO COND
(IR(9 downto 6) = "0111" and FR(0) = '1') or -- GREATER
(IR(9 downto 6) = "1001" and FR(2 downto 0) = "101") or -- greater equal
(IR(9 downto 6) = "1000" and FR(1) = '1') or -- lesser
(IR(9 downto 6) = "1010" and FR(2 downto 0) = "110") or -- lesser equal
(IR(9 downto 6) = "0001" and FR(2) = '1') or -- equal
(IR(9 downto 6) = "0010" and FR(2) = '0') or -- not equal
(IR(9 downto 6) = "0011" and FR(3) = '1') or -- zero
(IR(9 downto 6) = "0100" and FR(3) = '0') or -- not zero
(IR(9 downto 6) = "0101" and FR(4) = '1') or -- carry
(IR(9 downto 6) = "0110" and FR(4) = '0') or -- not carry
(IR(9 downto 6) = "1011" and FR(5) = '1') or -- overflow
(IR(9 downto 6) = "1100" and FR(5) = '0') or -- not overflow
(IR(9 downto 6) = "1101" and FR(6) = '1') or -- DIV0
(IR(9 downto 6) = "1110" and FR(9) = '1')) then -- result negative
RW <= '1'; -- Escreve PC na Pilha (M[SP] <- PC)
M5 <= PC;
M1 <= SP;
DecSP := '1';
state := exec;
ELSE
IncPC := '1';
state := fetch;
END IF;
END IF;
--========================================================================
-- RTS PC <- Mem[SP]
--========================================================================
IF(IR(15 DOWNTO 10) = RTS) THEN
IncSP := '1';
state := exec;
END IF;
--========================================================================
-- ARITH OPERATION ('INC' NOT INCLUDED) RX <- RY (?) RZ
--========================================================================
IF(IR(15 DOWNTO 14) = ARITH AND IR(13 DOWNTO 10) /= INC) THEN
M3 := Reg(Ry);
M4 := Reg(RZ);
X <= M3;
Y <= M4;
OP(5 downto 0 ) <= IR(15 downto 10);
OP(6) <= IR(0);
selM2 := sULA;
LoadReg(Rx) := '1';
state := fetch;
END IF;
--========================================================================
-- INC RX <- RX (+ or -) 1
--========================================================================
IF(IR(15 DOWNTO 14) = ARITH AND IR(13 DOWNTO 10) = INC) THEN
M3 := Reg(Rx);
M4 := x"0001";
X <= M3;
Y <= M4;
OP(5 downto 4) <= ARITH;
IF(IR(6) = '0') THEN
OP(3 downto 0) <= ADD;
ELSE
OP(3 downto 0) <= SUB;
END IF;
selM2 := sULA;
LoadReg(Rx) := '1';
state := fetch;
END IF;
--========================================================================
-- NOP
--========================================================================
IF( IR(15 DOWNTO 10) = NOP) THEN
state := fetch;
end if;
--========================================================================
-- HALT
--========================================================================
IF( IR(15 DOWNTO 10) = HALT) THEN
state := halted;
END IF;
--========================================================================
-- SETC/CLEARC
--========================================================================
IF( IR(15 DOWNTO 10) = SETC) THEN
FR(4) <= IR(9);
state := fetch;
end if;
--========================================================================
-- BREAKP
--========================================================================
IF( IR(15 DOWNTO 10) = BREAKP) THEN
BreakFlag := not(BreakFlag);
BREAK <= BreakFlag;
state := fetch;
PONTO <= "101";
END IF;
--========================================================================
-- STORE2 Reg2(Rx) <- Ry
--========================================================================
if( IR(15 downto 10) = STORE2 ) then
if(Reg(Rx) < 8) then
Reg2( CONV_INTEGER( unsigned( Reg(Rx)(7 downto 0) ) ) ) <= Reg(Ry);
end if;
state := fetch;
pwm_out2 <= '1';
end if;
--========================================================================
-- LOAD2 Rx <- Reg(Ry)
--========================================================================
if( IR(15 downto 10) = LOAD2 ) then
if(Reg(Rx) < 8) then
Reg(Rx) := Reg2( CONV_INTEGER( unsigned( Reg(Ry)(7 downto 0) ) ) );
end if;
state := fetch;
end if;
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--========================================================================
-- IR RX[5..0] <- KeyPressed RX[15..6] <- 0
--========================================================================
IF(IR(15 DOWNTO 10) = IR_instr) THEN
TECLADO(7 downto 0) := ir_in(7 downto 0);
TECLADO(15 downto 8) := X"00";
selM2 := sTECLADO;
LoadReg(RX) := '1';
state := fetch;
END IF;
--************************************************************************
-- EXECUTE STATE
--************************************************************************
when exec =>
PONTO <= "100";
--========================================================================
-- EXEC STORE DIReto M[END] <- RX
--========================================================================
IF(IR(15 DOWNTO 10) = STORE) THEN
M1 <= MAR;
Rw <= '1';
M3 := Reg(Rx);
M5 <= M3;
state := fetch;
END IF;
--========================================================================
-- EXEC LOAD DIReto RX <- M[END]
--========================================================================
IF(IR(15 DOWNTO 10) = LOAD) THEN
M1 <= Mar;
Rw <= '0';
selM2 := sMem;
LoadReg(Rx) := '1';
state := fetch;
END IF;
--========================================================================
-- EXEC POP RX
--========================================================================
IF(IR(15 DOWNTO 10) = POP) THEN
M1 <= SP; -- M1 <- SP
Rw <= '0'; -- R/W <- 0
if(IR(6) = '0') then
selM2 := sMem; -- M2 <- MEM
LoadReg(Rx) := '1'; -- LRx <- 1
elsif(IR(6) = '1') then
selM6 := sMem;
end if;
state := fetch;
END IF;
--========================================================================
-- EXEC CALL Pilha <- PC e PC <- 16bit END :
--========================================================================
IF(IR(15 DOWNTO 10) = CALL) THEN
M1 <= PC; -- M1 <- PC
Rw <= '0'; -- R/W <- 0
LoadPC := '1'; -- LPC <- 1
state := fetch;
END IF;
--========================================================================
-- EXEC RTS PC <- Mem[SP]
--========================================================================
IF(IR(15 DOWNTO 10) = RTS) THEN
M1 <= SP;
Rw <= '0';
LoadPC := '1';
IncPC := '1'; -- fazer em outro estado pq INCrementar e LOAD sao na SUBida de clock
state := fetch;
END IF;
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--************************************************************************
-- HALT STATE
--************************************************************************
WHEN halted =>
PONTO <= "111";
state := halted;
halt_ack <= '1';
WHEN OTHERS =>
state := fetch;
videoflag <= '0';
PONTO <= "000";
END CASE;
end if;
end process;
--************************************************************************
-- ULA ---> 3456 (3042)
--************************************************************************
PROCESS (OP, X, Y, reset)
VARIABLE AUX : STD_LOGIC_VECTOR(15 downto 0);
VARIABLE RESULT32 : STD_LOGIC_VECTOR(31 downto 0);
BEGIN
IF (reset = '1') THEN
auxFR <= x"0000";
RESULT <= x"0000";
else
auxFR <= FR;
--========================================================================
-- ARITH
--========================================================================
IF (OP (5 downto 4) = ARITH) THEN
CASE OP (3 downto 0) IS
WHEN ADD =>
IF (OP(6) = '1') THEN --Soma com carRY
AUX := X + Y + FR(4);
RESULT32 := (x"00000000" + X + Y + FR(4));
ELSE --Soma sem carRY
AUX := X + Y;
RESULT32 := (x"00000000" + X + Y);
end if;
if(RESULT32 > "01111111111111111") THEN -- CarRY
auxFR(4) <= '1';
ELSE
auxFR(4) <= '0';
end if;
WHEN SUB =>
AUX := X - Y;
WHEN MULT =>
RESULT32 := X * Y;
AUX := RESULT32(15 downto 0);
if(RESULT32 > x"0000FFFF") THEN -- ARITHmetic Overflow
auxFR(5) <= '1';
ELSE
auxFR(5) <= '0';
end if;
WHEN DIV =>
IF(Y = x"0000") THEN
AUX := x"0000";
auxFR(6) <= '1'; -- DIV by Zero
ELSE
AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X)/CONV_INTEGER(Y), 16);
auxFR(6) <= '0';
END IF;
WHEN LMOD =>
IF(Y = x"0000") THEN
AUX := x"0000";
auxFR(6) <= '1'; -- DIV by Zero
ELSE
AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X) mod CONV_INTEGER(Y), 16);
auxFR(6) <= '0';
END IF;
WHEN others => -- invalid operation, defaults to nothing
AUX := X;
END CASE;
if(AUX = x"0000") THEN
auxFR(3) <= '1'; -- FR = <...|zero|equal|lesser|greater>
ELSE
auxFR(3) <= '0'; -- FR = <...|zero|equal|lesser|greater>
end if;
if(AUX < x"0000") THEN -- NEGATIVO
auxFR(9) <= '1';
ELSE
auxFR(9) <= '0';
end if;
RESULT <= AUX;
ELSIF (OP (5 downto 4) = LOGIC) THEN
IF (OP (3 downto 0) = CMP) THEN
result <= x;
IF (x > y) THEN
auxFR(2 downto 0) <= "001"; -- FR = <...|zero|equal|lesser|greater>
ELSIF (x < y) THEN
auxFR(2 downto 0) <= "010"; -- FR = <...|zero|equal|lesser|greater>
ELSIF (x = y) THEN
auxFR(2 downto 0) <= "100"; -- FR = <...|zero|equal|lesser|greater>
END IF;
ELSE
CASE OP (3 downto 0) IS
WHEN LAND => result <= x and y;
WHEN LXOR => result <= x xor y;
WHEN LOR => result <= x or y;
WHEN LNOT => result <= not y;
WHEN others => -- invalid operation, defaults to nothing
RESULT <= X;
END CASE;
if(result = x"0000") THEN
auxFR(3) <= '1'; -- FR = <...|zero|equal|lesser|greater>
ELSE
auxFR(3) <= '0'; -- FR = <...|zero|equal|lesser|greater>
end if;
END IF;
END IF;
END IF; -- Reset
END PROCESS;
-- PWM 1
process(clk, reset) -- precisa mudar o clock para um menor
variable contador : std_logic_vector(15 downto 0);
begin
if(reset = '1') then
pwm_out <= '1';
contador := x"0000";
elsif(clk'event and clk = '1') then
if(contador = x"0001") then -- se contador = 0, entao desce o pwm
pwm_out <= '1';
elsif(contador = reg2(0)) then -- se contador = reg2, entao sobe o pwm
pwm_out <= '0';
elsif(contador = x"FFFF") then -- atingiu o maximo, volta para 00
contador := x"0000";
end if;
contador := contador + x"0001";
end if;
DISPLAY1 <= reg2(0)(3 downto 0);
DISPLAY2 <= reg2(0)(7 DOWNTO 4);
DISPLAY3 <= reg2(0)(11 DOWNTO 8);
DISPLAY4 <= reg2(0)(15 DOWNTO 12);
end process;
-- PWM 2
process(clk, reset) -- precisa mudar o clock para um menor
variable contador : std_logic_vector(15 downto 0);
begin
if(reset = '1') then
--pwm_out2 <= '1';
contador := x"0000";
elsif(clk'event and clk = '1') then
if(contador = x"0001") then -- se contador = 0, entao desce o pwm
--pwm_out2 <= '1';
elsif(contador = reg2(1)) then -- se contador = reg2, entao sobe o pwm
--pwm_out2 <= '0';
elsif(contador = x"FFFF") then -- atingiu o maximo, volta para 00
contador := x"0000";
end if;
contador := contador + x"0001";
end if;
-- DISPLAY5 <= contador(3 DOWNTO 0);
-- DISPLAY6 <= contador(7 DOWNTO 4);
DISPLAY7 <= contador(11 DOWNTO 8);
DISPLAY8 <= contador(15 DOWNTO 12);
end process;
end main;
| gpl-3.0 | 896d6fb6215ccc5520b87fc6541723fc | 0.440373 | 3.298566 | false | false | false | false |
domagalski/pocketcorr | fpga/snap/pfb_fir_2048ch_core.vhd | 1 | 4,209 | -- Generated from Simulink block
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity pfb_fir_2048ch_core_ip is
port (
pol0_in0 : in std_logic_vector( 8-1 downto 0 );
pol1_in0 : in std_logic_vector( 8-1 downto 0 );
sync : in std_logic_vector( 32-1 downto 0 );
pol2_in0 : in std_logic_vector( 8-1 downto 0 );
pol2_in1 : in std_logic_vector( 8-1 downto 0 );
pol3_in0 : in std_logic_vector( 8-1 downto 0 );
pol3_in1 : in std_logic_vector( 8-1 downto 0 );
pol0_in1 : in std_logic_vector( 8-1 downto 0 );
pol1_in1 : in std_logic_vector( 8-1 downto 0 );
pol0_out0 : out std_logic_vector( 18-1 downto 0 );
pol1_out0 : out std_logic_vector( 18-1 downto 0 );
sync_out : out std_logic_vector( 1-1 downto 0 );
pol2_out0 : out std_logic_vector( 18-1 downto 0 );
pol3_out0 : out std_logic_vector( 18-1 downto 0 );
pol0_out1 : out std_logic_vector( 18-1 downto 0 );
pol1_out1 : out std_logic_vector( 18-1 downto 0 );
pol2_out1 : out std_logic_vector( 18-1 downto 0 );
pol3_out1 : out std_logic_vector( 18-1 downto 0 );
clk : in std_logic
);
end pfb_fir_2048ch_core_ip;
-- Generated from Simulink block
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity pfb_fir_2048ch_core_ip_struct is
port (
pol0_in0 : in std_logic_vector( 8-1 downto 0 );
pol1_in0 : in std_logic_vector( 8-1 downto 0 );
sync : in std_logic_vector( 32-1 downto 0 );
pol2_in0 : in std_logic_vector( 8-1 downto 0 );
pol2_in1 : in std_logic_vector( 8-1 downto 0 );
pol3_in0 : in std_logic_vector( 8-1 downto 0 );
pol3_in1 : in std_logic_vector( 8-1 downto 0 );
pol0_in1 : in std_logic_vector( 8-1 downto 0 );
pol1_in1 : in std_logic_vector( 8-1 downto 0 );
clk_1 : in std_logic;
ce_1 : in std_logic;
pol0_out0 : out std_logic_vector( 18-1 downto 0 );
pol1_out0 : out std_logic_vector( 18-1 downto 0 );
sync_out : out std_logic_vector( 1-1 downto 0 );
pol2_out0 : out std_logic_vector( 18-1 downto 0 );
pol3_out0 : out std_logic_vector( 18-1 downto 0 );
pol0_out1 : out std_logic_vector( 18-1 downto 0 );
pol1_out1 : out std_logic_vector( 18-1 downto 0 );
pol2_out1 : out std_logic_vector( 18-1 downto 0 );
pol3_out1 : out std_logic_vector( 18-1 downto 0 )
);
end pfb_fir_2048ch_core_ip_struct;
architecture structural of pfb_fir_2048ch_core_ip_struct is
component pfb_fir_2048ch_core_ip
port (
pol0_in0 : in std_logic_vector( 8-1 downto 0 );
pol1_in0 : in std_logic_vector( 8-1 downto 0 );
sync : in std_logic_vector( 32-1 downto 0 );
pol2_in0 : in std_logic_vector( 8-1 downto 0 );
pol2_in1 : in std_logic_vector( 8-1 downto 0 );
pol3_in0 : in std_logic_vector( 8-1 downto 0 );
pol3_in1 : in std_logic_vector( 8-1 downto 0 );
pol0_in1 : in std_logic_vector( 8-1 downto 0 );
pol1_in1 : in std_logic_vector( 8-1 downto 0 );
pol0_out0 : out std_logic_vector( 18-1 downto 0 );
pol1_out0 : out std_logic_vector( 18-1 downto 0 );
sync_out : out std_logic_vector( 1-1 downto 0 );
pol2_out0 : out std_logic_vector( 18-1 downto 0 );
pol3_out0 : out std_logic_vector( 18-1 downto 0 );
pol0_out1 : out std_logic_vector( 18-1 downto 0 );
pol1_out1 : out std_logic_vector( 18-1 downto 0 );
pol2_out1 : out std_logic_vector( 18-1 downto 0 );
pol3_out1 : out std_logic_vector( 18-1 downto 0 );
clk : in std_logic
);
end component;
begin
pfb_fir_2048ch_core_ip_inst : pfb_fir_2048ch_core_ip
port map (
pol0_in0 => pol0_in0,
pol1_in0 => pol1_in0,
sync => sync,
pol2_in0 => pol2_in0,
pol2_in1 => pol2_in1,
pol3_in0 => pol3_in0,
pol3_in1 => pol3_in1,
pol0_in1 => pol0_in1,
pol1_in1 => pol1_in1,
clk => clk_1,
pol0_out0 => pol0_out0,
pol1_out0 => pol1_out0,
sync_out => sync_out,
pol2_out0 => pol2_out0,
pol3_out0 => pol3_out0,
pol0_out1 => pol0_out1,
pol1_out1 => pol1_out1,
pol2_out1 => pol2_out1,
pol3_out1 => pol3_out1
);
end structural;
| gpl-3.0 | 2415198566a12690e9d12f904b53f141 | 0.617962 | 2.713733 | false | false | false | false |
AndyMcC0/UVVM_All | bitvis_vip_avalon_mm/src/vvc_methods_pkg.vhd | 2 | 19,753 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.avalon_mm_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_methods_pkg is
--===============================================================================================
-- Types and constants for the SBI VVC
--===============================================================================================
constant C_VVC_NAME : string := "AVALON_MM_VVC";
signal AVALON_MM_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is AVALON_MM_VVCT;
alias t_bfm_config is t_avalon_mm_bfm_config;
-- Type found in UVVM-Util types_pkg
constant C_AVALON_MM_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => WARNING
);
type t_vvc_config is
record
inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity cmd_queue_count_threshold_severity will be issued if command queue exceeds this count. Used for early warning if command queue is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full.
result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if result queue is almost full. Will be ignored if set to 0.
result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold
bfm_config : t_bfm_config; -- Configuration for Avalon-MM BFM. See quick reference for Avalon-MM BFM
use_read_pipeline : boolean; -- When true, allows sending multiple read_requests before receiving a read_response
num_pipeline_stages : natural; -- Max read_requests in pipeline
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_AVALON_MM_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_AVALON_MM_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX, -- from adaptation package
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_AVALON_MM_BFM_CONFIG_DEFAULT,
use_read_pipeline => TRUE,
num_pipeline_stages => 5,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT
);
type t_vvc_status is
record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
-- Transaction information to include in the wave view during simulation
type t_transaction_info is
record
operation : t_operation;
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0);
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
byte_enable : std_logic_vector(C_VVC_CMD_BYTE_ENABLE_MAX_LENGTH-1 downto 0);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
operation => NO_OPERATION,
addr => (others => '0'),
data => (others => '0'),
byte_enable => (others => '1'),
msg => (others => ' ')
);
shared variable shared_avalon_mm_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_AVALON_MM_VVC_CONFIG_DEFAULT);
shared variable shared_avalon_mm_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_avalon_mm_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_TRANSACTION_INFO_DEFAULT);
--==============================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order to queue BFM calls
-- in the VVC command queue. The VVC will store and forward these calls to the
-- SBI BFM when the command is at the from of the VVC command queue.
-- - For details on how the BFM procedures work, see sbi_bfm_pkg.vhd or the
-- quickref.
--==============================================================================
-- Without byte enable
procedure avalon_mm_write (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string
);
-- With byte enable
procedure avalon_mm_write (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant byte_enable : in std_logic_vector;
constant msg : in string
);
procedure avalon_mm_read (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string
);
procedure avalon_mm_check (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR
);
procedure avalon_mm_reset (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant num_rst_cycles : in integer;
constant msg : in string
);
procedure avalon_mm_lock (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string
);
procedure avalon_mm_unlock (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string
);
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--==============================================================================
-- Methods dedicated to this VVC
-- Notes:
-- - shared_vvc_cmd is initialised to C_VVC_CMD_DEFAULT, and also reset to this after every command
--==============================================================================
procedure avalon_mm_write(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string
) is
constant proc_name : string := "avalon_mm_write";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, WRITE);
shared_vvc_cmd.addr := v_normalised_addr;
shared_vvc_cmd.data := v_normalised_data;
send_command_to_vvc(VVCT);
end procedure;
procedure avalon_mm_write(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant byte_enable : in std_logic_vector;
constant msg : in string
) is
constant proc_name : string := "avalon_mm_write";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX)
& ", " & to_string(byte_enable, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
variable v_normalised_byte_ena : std_logic_vector(shared_vvc_cmd.byte_enable'length-1 downto 0) :=
normalize_and_check(byte_enable, shared_vvc_cmd.byte_enable, ALLOW_WIDER_NARROWER, "byte_enable", "shared_vvc_cmd.byte_enable", proc_call & " called with to wide byte_enable. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, WRITE);
shared_vvc_cmd.addr := v_normalised_addr;
shared_vvc_cmd.data := v_normalised_data;
shared_vvc_cmd.byte_enable := v_normalised_byte_ena;
send_command_to_vvc(VVCT);
end procedure;
procedure avalon_mm_read(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string
) is
constant proc_name : string := "avalon_mm_read";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr",proc_call & " called with to wide address. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, READ);
shared_vvc_cmd.operation := READ;
shared_vvc_cmd.addr := v_normalised_addr;
send_command_to_vvc(VVCT);
end procedure;
procedure avalon_mm_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR
) is
constant proc_name : string := "avalon_mm_check";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, CHECK);
shared_vvc_cmd.addr := v_normalised_addr;
shared_vvc_cmd.data := v_normalised_data;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT);
end procedure;
procedure avalon_mm_reset(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant num_rst_cycles : in integer;
constant msg : in string
) is
constant proc_name : string := "avalon_mm_reset";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(num_rst_cycles) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, RESET);
shared_vvc_cmd.gen_integer_array(0) := num_rst_cycles;
send_command_to_vvc(VVCT);
end procedure;
procedure avalon_mm_lock (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string
) is
constant proc_name : string := "avalon_mm_lock";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, LOCK);
send_command_to_vvc(VVCT);
end procedure;
procedure avalon_mm_unlock (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string
) is
constant proc_name : string := "avalon_mm_unlock";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, UNLOCK);
send_command_to_vvc(VVCT);
end procedure;
end package body vvc_methods_pkg;
| mit | a96bbfd157d320481308c899427228b7 | 0.594846 | 4.055225 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/RTL/New_SHMU_on_Node/FIFO_one_hot_credit_based_packet_drop_classifier_support.vhd | 6 | 17,242 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3);
signal fault_info_in, fault_info_out: std_logic;
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop);
signal state_out, state_in : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop state machine
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
fault_info_out <= '0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
fault_info_out <= fault_info_in;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
fault_info <= fault_info_out;
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if fake_credit = '1' or read_en ='1' then
credit_in <= '1';
end if;
if fake_credit = '0' and read_en = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
process(valid_in, RX) begin
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
else
xor_all <= '0';
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out <= '1';
end if;
end process;
process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, flit_type, valid_in)begin
-- this is the default value of the memory!
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
--some defaults
fault_info_in <= '0';
health_info <= '0';
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_out = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "010" then
state_in <= Body_flit;
elsif flit_type ="100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "010" then
state_in <= state_out;
elsif flit_type = "100" then
state_in <= Tail_flit;
health_info <= '1';
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else -- fault_out = '1'
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
if faulty_packet_out = '1' then
if valid_in = '1' and flit_type = "001" and fault_out = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
elsif valid_in = '1' and flit_type ="100" and fault_out = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else -- fault_out might have been '1'
if valid_in = '1' and flit_type = "001" then
fault_info_in <= '1';
end if;
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
else
-- we should not be here!
state_in <= state_out;
end if;
when others => state_in <= state_out;
end case;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin
if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
| gpl-3.0 | 7265317dcb324019ec20e3f866889b90 | 0.407319 | 3.692077 | false | false | false | false |
Wynjones1/gbvhdl | scripts/conversion.vhd | 1 | 14,576 | elsif instruction = x"0" then return "NOP............";
elsif instruction = x"1" then return "LD.BC.d16......";
elsif instruction = x"2" then return "LD.(BC).A......";
elsif instruction = x"3" then return "INC.BC.........";
elsif instruction = x"4" then return "INC.B..........";
elsif instruction = x"5" then return "DEC.B..........";
elsif instruction = x"6" then return "LD.B.n.........";
elsif instruction = x"7" then return "RLCA...........";
elsif instruction = x"8" then return "LD.(d16).SP....";
elsif instruction = x"9" then return "ADD.BC.ss......";
elsif instruction = x"a" then return "LD.A.(BC)......";
elsif instruction = x"b" then return "DEC.BC.........";
elsif instruction = x"c" then return "INC.C..........";
elsif instruction = x"d" then return "DEC.C..........";
elsif instruction = x"e" then return "LD.C.n.........";
elsif instruction = x"f" then return "RRCA...........";
elsif instruction = x"10" then return "STOP...........";
elsif instruction = x"11" then return "LD.DE.d16......";
elsif instruction = x"12" then return "LD..(DE).A.....";
elsif instruction = x"13" then return "INC.DE.........";
elsif instruction = x"14" then return "INC.D..........";
elsif instruction = x"15" then return "DEC.D..........";
elsif instruction = x"16" then return "LD.D.n.........";
elsif instruction = x"17" then return "RLA............";
elsif instruction = x"18" then return "JR.r8..........";
elsif instruction = x"19" then return "ADD.DE.ss......";
elsif instruction = x"1a" then return "LD.A.(DE)......";
elsif instruction = x"1b" then return "DEC.DE.........";
elsif instruction = x"1c" then return "INC.E..........";
elsif instruction = x"1d" then return "DEC.E..........";
elsif instruction = x"1e" then return "LD.E.n.........";
elsif instruction = x"1f" then return "RRA............";
elsif instruction = x"20" then return "JR.NZ.r8.......";
elsif instruction = x"21" then return "LD.HL.d16......";
elsif instruction = x"22" then return "LD.(HL++).A....";
elsif instruction = x"23" then return "INC.HL.........";
elsif instruction = x"24" then return "INC.H..........";
elsif instruction = x"25" then return "DEC.H..........";
elsif instruction = x"26" then return "LD.H.n.........";
elsif instruction = x"27" then return "DDA............";
elsif instruction = x"28" then return "JR.Z.r8........";
elsif instruction = x"29" then return "ADD.HL.ss......";
elsif instruction = x"2a" then return "LD.A.(HL++)....";
elsif instruction = x"2b" then return "DEC.HL.........";
elsif instruction = x"2c" then return "INC.L..........";
elsif instruction = x"2d" then return "DEC.L..........";
elsif instruction = x"2e" then return "LD.L.n.........";
elsif instruction = x"2f" then return "CPL............";
elsif instruction = x"30" then return "JR.NC.r8.......";
elsif instruction = x"31" then return "LD.SP.d16......";
elsif instruction = x"32" then return "LD.(HL--)..A...";
elsif instruction = x"33" then return "INC.SP.........";
elsif instruction = x"34" then return "INC.(HL).......";
elsif instruction = x"35" then return "DEC.(HL).......";
elsif instruction = x"36" then return "LD.(HL).d8.....";
elsif instruction = x"37" then return "SCF............";
elsif instruction = x"38" then return "JR.C.r8........";
elsif instruction = x"39" then return "ADD.SP.ss......";
elsif instruction = x"3a" then return "LD.A.(HL--)....";
elsif instruction = x"3b" then return "DEC.SP.........";
elsif instruction = x"3c" then return "INC.A..........";
elsif instruction = x"3d" then return "DEC.A..........";
elsif instruction = x"3e" then return "LD.A.n.........";
elsif instruction = x"3f" then return "CCF............";
elsif instruction = x"40" then return "LD.B.B.........";
elsif instruction = x"41" then return "LD.B.C.........";
elsif instruction = x"42" then return "LD.B.D.........";
elsif instruction = x"43" then return "LD.B.E.........";
elsif instruction = x"44" then return "LD.B.H.........";
elsif instruction = x"45" then return "LD.B.L.........";
elsif instruction = x"46" then return "LD.B.(HL)......";
elsif instruction = x"47" then return "LD.B.A.........";
elsif instruction = x"48" then return "LD.C.B.........";
elsif instruction = x"49" then return "LD.C.C.........";
elsif instruction = x"4a" then return "LD.C.D.........";
elsif instruction = x"4b" then return "LD.C.E.........";
elsif instruction = x"4c" then return "LD.C.H.........";
elsif instruction = x"4d" then return "LD.C.L.........";
elsif instruction = x"4e" then return "LD.C.(HL)......";
elsif instruction = x"4f" then return "LD.C.A.........";
elsif instruction = x"50" then return "LD.D.B.........";
elsif instruction = x"51" then return "LD.D.C.........";
elsif instruction = x"52" then return "LD.D.D.........";
elsif instruction = x"53" then return "LD.D.E.........";
elsif instruction = x"54" then return "LD.D.H.........";
elsif instruction = x"55" then return "LD.D.L.........";
elsif instruction = x"56" then return "LD.D.(HL)......";
elsif instruction = x"57" then return "LD.D.A.........";
elsif instruction = x"58" then return "LD.E.B.........";
elsif instruction = x"59" then return "LD.E.C.........";
elsif instruction = x"5a" then return "LD.E.D.........";
elsif instruction = x"5b" then return "LD.E.E.........";
elsif instruction = x"5c" then return "LD.E.H.........";
elsif instruction = x"5d" then return "LD.E.L.........";
elsif instruction = x"5e" then return "LD.E.(HL)......";
elsif instruction = x"5f" then return "LD.E.A.........";
elsif instruction = x"60" then return "LD.H.B.........";
elsif instruction = x"61" then return "LD.H.C.........";
elsif instruction = x"62" then return "LD.H.D.........";
elsif instruction = x"63" then return "LD.H.E.........";
elsif instruction = x"64" then return "LD.H.H.........";
elsif instruction = x"65" then return "LD.H.L.........";
elsif instruction = x"66" then return "LD.H.(HL)......";
elsif instruction = x"67" then return "LD.H.A.........";
elsif instruction = x"68" then return "LD.L.B.........";
elsif instruction = x"69" then return "LD.L.C.........";
elsif instruction = x"6a" then return "LD.L.D.........";
elsif instruction = x"6b" then return "LD.L.E.........";
elsif instruction = x"6c" then return "LD.L.H.........";
elsif instruction = x"6d" then return "LD.L.L.........";
elsif instruction = x"6e" then return "LD.L.(HL)......";
elsif instruction = x"6f" then return "LD.L.A.........";
elsif instruction = x"70" then return "LD.(HL).B......";
elsif instruction = x"71" then return "LD.(HL).C......";
elsif instruction = x"72" then return "LD.(HL).D......";
elsif instruction = x"73" then return "LD.(HL).E......";
elsif instruction = x"74" then return "LD.(HL).H......";
elsif instruction = x"75" then return "LD.(HL).L......";
elsif instruction = x"76" then return "HALT...........";
elsif instruction = x"77" then return "LD.(HL).A......";
elsif instruction = x"78" then return "LD.A.B.........";
elsif instruction = x"79" then return "LD.A.C.........";
elsif instruction = x"7a" then return "LD.A.D.........";
elsif instruction = x"7b" then return "LD.A.E.........";
elsif instruction = x"7c" then return "LD.A.H.........";
elsif instruction = x"7d" then return "LD.A.L.........";
elsif instruction = x"7e" then return "LD.A.(HL)......";
elsif instruction = x"7f" then return "LD.A.A.........";
elsif instruction = x"80" then return "ADD.A.B........";
elsif instruction = x"81" then return "ADD.A.C........";
elsif instruction = x"82" then return "ADD.A.D........";
elsif instruction = x"83" then return "ADD.A.E........";
elsif instruction = x"84" then return "ADD.A.H........";
elsif instruction = x"85" then return "ADD.A.L........";
elsif instruction = x"86" then return "ADD.A.(HL).....";
elsif instruction = x"87" then return "ADD.A.A........";
elsif instruction = x"88" then return "ADC.A.B........";
elsif instruction = x"89" then return "ADC.A.C........";
elsif instruction = x"8a" then return "ADC.A.D........";
elsif instruction = x"8b" then return "ADC.A.E........";
elsif instruction = x"8c" then return "ADC.A.H........";
elsif instruction = x"8d" then return "ADC.A.L........";
elsif instruction = x"8e" then return "ADC.A.(HL).....";
elsif instruction = x"8f" then return "ADC.A.A........";
elsif instruction = x"90" then return "SUB.A.B........";
elsif instruction = x"91" then return "SUB.A.C........";
elsif instruction = x"92" then return "SUB.A.D........";
elsif instruction = x"93" then return "SUB.A.E........";
elsif instruction = x"94" then return "SUB.A.H........";
elsif instruction = x"95" then return "SUB.A.L........";
elsif instruction = x"96" then return "SUB.A.(HL).....";
elsif instruction = x"97" then return "SUB.A.A........";
elsif instruction = x"98" then return "SBC.A.B........";
elsif instruction = x"99" then return "SBC.A.C........";
elsif instruction = x"9a" then return "SBC.A.D........";
elsif instruction = x"9b" then return "SBC.A.E........";
elsif instruction = x"9c" then return "SBC.A.H........";
elsif instruction = x"9d" then return "SBC.A.L........";
elsif instruction = x"9e" then return "SBC.A.(HL).....";
elsif instruction = x"9f" then return "SBC.A.A........";
elsif instruction = x"a0" then return "AND.A.B........";
elsif instruction = x"a1" then return "AND.A.C........";
elsif instruction = x"a2" then return "AND.A.D........";
elsif instruction = x"a3" then return "AND.A.E........";
elsif instruction = x"a4" then return "AND.A.H........";
elsif instruction = x"a5" then return "AND.A.L........";
elsif instruction = x"a6" then return "AND.A.(HL).....";
elsif instruction = x"a7" then return "AND.A.A........";
elsif instruction = x"a8" then return "XOR.A.B........";
elsif instruction = x"a9" then return "XOR.A.C........";
elsif instruction = x"aa" then return "XOR.A.D........";
elsif instruction = x"ab" then return "XOR.A.E........";
elsif instruction = x"ac" then return "XOR.A.H........";
elsif instruction = x"ad" then return "XOR.A.L........";
elsif instruction = x"ae" then return "XOR.A.(HL).....";
elsif instruction = x"af" then return "XOR.A.A........";
elsif instruction = x"b0" then return "OR.A.B.........";
elsif instruction = x"b1" then return "OR.A.C.........";
elsif instruction = x"b2" then return "OR.A.D.........";
elsif instruction = x"b3" then return "OR.A.E.........";
elsif instruction = x"b4" then return "OR.A.H.........";
elsif instruction = x"b5" then return "OR.A.L.........";
elsif instruction = x"b6" then return "OR.A.(HL)......";
elsif instruction = x"b7" then return "OR.A.A.........";
elsif instruction = x"b8" then return "CP.A.B.........";
elsif instruction = x"b9" then return "CP.A.C.........";
elsif instruction = x"ba" then return "CP.A.D.........";
elsif instruction = x"bb" then return "CP.A.E.........";
elsif instruction = x"bc" then return "CP.A.H.........";
elsif instruction = x"bd" then return "CP.A.L.........";
elsif instruction = x"be" then return "CP.A.(HL)......";
elsif instruction = x"bf" then return "CP.A.A.........";
elsif instruction = x"c0" then return "RET.NZ.........";
elsif instruction = x"c1" then return "POP.BC.........";
elsif instruction = x"c2" then return "JP.NZ.d16......";
elsif instruction = x"c3" then return "JP.d16.........";
elsif instruction = x"c4" then return "CALL.NZ.d16....";
elsif instruction = x"c5" then return "PUSH.BC........";
elsif instruction = x"c6" then return "ADD.A.n........";
elsif instruction = x"c7" then return "RST.00H........";
elsif instruction = x"c8" then return "RET.Z..........";
elsif instruction = x"c9" then return "RET............";
elsif instruction = x"ca" then return "JP.Z.d16.......";
elsif instruction = x"cb" then return "CB.............";
elsif instruction = x"cc" then return "CALL.Z.d16.....";
elsif instruction = x"cd" then return "CALL.d16.......";
elsif instruction = x"ce" then return "ADC.A.n........";
elsif instruction = x"cf" then return "RST.08H........";
elsif instruction = x"d0" then return "RET.NC.........";
elsif instruction = x"d1" then return "POP.DE.........";
elsif instruction = x"d2" then return "JP.NC.d16......";
elsif instruction = x"d3" then return "INVALID........";
elsif instruction = x"d4" then return "CALL.NC.d16....";
elsif instruction = x"d5" then return "PUSH.DE........";
elsif instruction = x"d6" then return "SUB.A.n........";
elsif instruction = x"d7" then return "RST.10H........";
elsif instruction = x"d8" then return "RET.C..........";
elsif instruction = x"d9" then return "RETI...........";
elsif instruction = x"da" then return "JP.C.d16.......";
elsif instruction = x"db" then return "INVALID........";
elsif instruction = x"dc" then return "CALL.C.d16.....";
elsif instruction = x"dd" then return "INVALID........";
elsif instruction = x"de" then return "SBC.A.n........";
elsif instruction = x"df" then return "RST.18H........";
elsif instruction = x"e0" then return "LDH.(d8).A.....";
elsif instruction = x"e1" then return "POP.HL.........";
elsif instruction = x"e2" then return "LD.(C).A.......";
elsif instruction = x"e3" then return "INVALID........";
elsif instruction = x"e4" then return "INVALID........";
elsif instruction = x"e5" then return "PUSH.HL........";
elsif instruction = x"e6" then return "AND.A.n........";
elsif instruction = x"e7" then return "RST.20H........";
elsif instruction = x"e8" then return "ADD.SP.r8......";
elsif instruction = x"e9" then return "JP.PC.(HL).....";
elsif instruction = x"ea" then return "LD.(d16).A.....";
elsif instruction = x"eb" then return "INVALID........";
elsif instruction = x"ec" then return "INVALID........";
elsif instruction = x"ed" then return "INVALID........";
elsif instruction = x"ee" then return "XOR.A.n........";
elsif instruction = x"ef" then return "RST.28H........";
elsif instruction = x"f0" then return "LDH.A.(d8).....";
elsif instruction = x"f1" then return "POP.AF.........";
elsif instruction = x"f2" then return "LD.A.(C).......";
elsif instruction = x"f3" then return "DI.............";
elsif instruction = x"f4" then return "INVALID........";
elsif instruction = x"f5" then return "PUSH.AF........";
elsif instruction = x"f6" then return "OR.A.n.........";
elsif instruction = x"f7" then return "RST.30H........";
elsif instruction = x"f8" then return "LD.HL.SP.+.r8..";
elsif instruction = x"f9" then return "LD.SP.HL.......";
elsif instruction = x"fa" then return "LD.A.(d16).....";
elsif instruction = x"fb" then return "EI.............";
elsif instruction = x"fc" then return "INVALID........";
elsif instruction = x"fd" then return "INVALID........";
elsif instruction = x"fe" then return "CP.A.n.........";
elsif instruction = x"ff" then return "RST.48H........";
| mit | 79e05ea53a61f784b056b3b0d3fd8540 | 0.594196 | 3.359299 | false | false | false | false |
kiwih/subleq-vhdl | subleq.vhd | 1 | 5,389 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.defs.all;
--a one-instruction-set instruction computer
entity subleq is
port(
CLK_50: in std_logic;
LED: out std_logic_vector(7 downto 2);
SEVENSEG_SEL: out std_logic_vector(3 downto 0); --which 7seg display is active
SEVENSEG_DAT: out std_logic_vector(0 to 7) --what 7seg data should be displayed
);
end entity;
architecture beh of subleq is
--memory mapped addresses
constant SEVENSEG_01_ADDR : std_logic_vector := x"F0";
constant SEVENSEG_23_ADDR : std_logic_vector := x"F1";
signal instruction_memory_addr : std_logic_vector(ADDR_BUS_SIZE - 1 downto 0);
signal instruction_memory_data_out: std_logic_vector(INSTRUCTION_BUS_SIZE - 1 downto 0);
signal data_memory_addr_a : std_logic_vector(ADDR_BUS_SIZE - 1 downto 0);
signal data_memory_data_out_a : std_logic_vector(DATA_BUS_SIZE - 1 downto 0);
signal data_a : std_logic_vector(DATA_BUS_SIZE - 1 downto 0);
signal data_memory_addr_b : std_logic_vector(ADDR_BUS_SIZE - 1 downto 0);
signal data_memory_data_out_b : std_logic_vector(DATA_BUS_SIZE - 1 downto 0);
signal data_memory_write_en_b : std_logic;
signal data_b : std_logic_vector(DATA_BUS_SIZE - 1 downto 0);
signal data_processor_out : std_logic_vector(DATA_BUS_SIZE - 1 downto 0);
signal data_write : std_logic;
signal sevenseg_01_write : std_logic;
signal sevenseg_23_write : std_logic;
signal sevenseg_01_data : std_logic_vector(7 downto 0);
signal sevenseg_23_data : std_logic_vector(7 downto 0);
signal reset : std_logic;
signal clk : std_logic;
signal cur_count : std_logic_vector(27 downto 0);
begin
--LED(7 downto 2) <= not(cur_count(27 downto 22));
LED(7 downto 2) <= not(cur_count(5 downto 0));
reset <= '0';
--All the components
clock_divider: entity work.clk_div
port map(
CLK_50 => CLK_50,
CLK_SLOW => clk
);
process(clk)
begin
if rising_edge(clk) then
cur_count <= cur_count + 1;
end if;
end process;
processor_core: entity work.core
generic map(
ADDR_SIZE => ADDR_BUS_SIZE,
INSTRUCTION_SIZE => INSTRUCTION_BUS_SIZE,
DATA_SIZE => DATA_BUS_SIZE
)
port map(
CLK => clk,
RESET => reset,
INSTRUCTION_MEMORY_ADDR => instruction_memory_addr,
INSTRUCTION_MEMORY_DATA_OUT => instruction_memory_data_out,
DATA_MEMORY_ADDR_A => data_memory_addr_a,
DATA_MEMORY_DATA_OUT_A => data_a,
DATA_MEMORY_ADDR_B => data_memory_addr_b,
DATA_MEMORY_DATA_OUT_B => data_b,
DATA_MEMORY_DATA_IN_B => data_processor_out,
DATA_MEMORY_WRITE_EN_B => data_write
);
instruction_memory: entity work.single_port_memfile
generic map(
ADDR_WIDTH => ADDR_BUS_SIZE,
DATA_WIDTH => INSTRUCTION_BUS_SIZE,
MEM_LENGTH => INSTRUCTION_MEMORY_LENGTH
)
port map(
CLK => clk,
WRITE_EN => '0',
ADDR => instruction_memory_addr,
DATA_IN => (others => '0'),
DATA_OUT => instruction_memory_data_out
);
data_memory: entity work.dual_port_memfile
generic map(
ADDR_WIDTH => ADDR_BUS_SIZE,
DATA_WIDTH => DATA_BUS_SIZE,
MEM_LENGTH => DATA_MEMORY_LENGTH
)
port map(
CLK => clk,
WRITE_EN_A => '0',
ADDR_A => data_memory_addr_a,
DATA_IN_A => (others => '0'),
DATA_OUT_A => data_memory_data_out_a,
WRITE_EN_B => data_memory_write_en_b,
ADDR_B => data_memory_addr_b,
DATA_IN_B => data_processor_out,
DATA_OUT_B => data_memory_data_out_b
);
seg01 : entity work.genericregister
generic map(
NUMBITS => 8
)
port map(
CLK => clk,
EN => sevenseg_01_write,
RESET => reset,
DATA_IN => data_processor_out(7 downto 0),
DATA_OUT => sevenseg_01_data
);
seg23 : entity work.genericregister
generic map(
NUMBITS => 8
)
port map(
CLK => clk,
EN => sevenseg_23_write,
RESET => reset,
DATA_IN => data_processor_out(7 downto 0),
DATA_OUT => sevenseg_23_data
);
segdecoder : entity work.hex_lcd_driver
port map(
CLK => CLK_50, --needs fast clock due to persistence of vision
DIG0 => sevenseg_01_data(3 downto 0),
DIG1 => sevenseg_01_data(7 downto 4),
DIG2 => instruction_memory_addr(3 downto 0),
DIG3 => instruction_memory_addr(7 downto 4),
SEVENSEG_SELECT => SEVENSEG_SEL,
SEVENSEG_DATA => SEVENSEG_DAT
);
--the address translation stuff
data_memory_write_en_b <= '1' when data_memory_addr_b < DATA_MEMORY_LENGTH and data_write = '1' else '0';
sevenseg_01_write <= '1' when data_memory_addr_b = SEVENSEG_01_ADDR and data_write = '1' else '0';
sevenseg_23_write <= '1' when data_memory_addr_b = SEVENSEG_23_ADDR and data_write = '1' else '0';
data_a <=
data_memory_data_out_a when data_memory_addr_a < DATA_MEMORY_LENGTH else
x"00" & sevenseg_01_data when data_memory_addr_a = SEVENSEG_01_ADDR else
x"00" & sevenseg_23_data when data_memory_addr_a = SEVENSEG_23_ADDR else
(others => '0');
data_b <=
data_memory_data_out_b when data_memory_addr_b < DATA_MEMORY_LENGTH else
x"00" & sevenseg_01_data when data_memory_addr_b = SEVENSEG_01_ADDR else
x"00" & sevenseg_23_data when data_memory_addr_b = SEVENSEG_23_ADDR else
(others => '0');
end architecture beh;
| mit | 963dbe12b8afc1741ef19dbfe653c048 | 0.640193 | 2.757932 | false | false | false | false |
ashtonchase/logic_analyzer | src/storage.vhd | 1 | 11,671 | -------------------------------------------------------------------------------
-- Title : Logic Analyzer Storage Entity
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : storage.vhd
-- Created : 2016-02-29
-- Last update: 2016-02-29
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Summary: This is a RAM storage for recorded data and the input and
-- output interface. It is responsible for generating RAM blocks to store
-- the large amount of data needed for a logic analyzer.
--
-- Functional: The main component of this entity is an array of std logic vectors
-- 32 bits wide. All data will be stored in this addressed array. There are
-- three pointer controlling its functionality: in_point, out_point, and last_point.
-- In_point will store incoming data into the inferred RAM. It will stop storing
-- data when in_point equal the max size or if it receives a word with tlast high.
-- Then it will sit until the RAM is empty.
--
-- The out_point controls where data is being read out of the RAM. It will read
-- out a word at a time. It will pass a byte at a time to the UART interface.
-- When out_point equals in_point, the RAM is empty. When this occurs, all pointers
-- will be re-initialized to 0. When the last word of the RAM is fed out, the
-- last_out bit will be pulled high on the last byte.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-29 0.1 Henny Created Entity
-- 2016-03-06 0.2 Henny Wrote initial architecture
-- 2016-03-09 1.0 Henny Tested with initial testbench
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity storage is
generic ( FIFO_SIZE : integer := 1024
);
port(
clk --! global clock, ?? MHz
: in std_logic;
reset --! Global reset
: in std_logic;
-- If we are not always 32 channels of storage, need an input telling me how many channels
--Input FIFO interface from capture
in_fifo_tdata --! Captured Data
: in std_logic_vector(31 downto 0);
in_fifo_tvalid --! indicating tdata has valid data
: in std_logic;
in_fifo_tlast -- no planned usage
: in std_logic;
in_fifo_tready --! outputted by FIFO saying it is ready for more data
: out std_logic;
in_fifo_tfull --! tell capture to stop capturing data
: out std_logic;
in_fifo_tempty --! indicating all data has been transmitted to GUI, can do another capture
: out std_logic;
in_fifo_tflush --! clear all stored data in the FIFO
: in std_logic;
--Output FIFO interface to UART
out_fifo_tdata --! Captured Data, fed LSByte to UART
: out std_logic_vector(7 downto 0);
out_fifo_tvalid --! indicating data has valid data to transmit out
: out std_logic;
out_fifo_tlast --! indicating that the end of this capture data
: out std_logic;
out_fifo_tready --! received from UART, indicating to feed next byte out
: in std_logic
);
end storage;
architecture behave of storage is
-- FIFO storage
type fifo_bank is array (0 to FIFO_SIZE-1) of std_logic_vector(31 downto 0);
signal fifo_data : fifo_bank;
signal in_point : natural range 0 to FIFO_SIZE;
signal out_point : natural range 0 to FIFO_SIZE;
signal last_point : natural range 0 to FIFO_SIZE-1; -- assuming there will only be one last in the fifo at a time
signal fifo_empty : std_logic;
signal in_fifo_tready_int : std_logic;
-- Control signal to re-initialize all the pointers
signal reset_points : std_logic;
begin
in_fifo_tready <= in_fifo_tready_int;
in_store_blk : block
type state_in is (STORE, WAIT_FOR_EMPTY);
signal in_state : state_in;
begin
in_store_pr : process(clk)
begin
if rising_edge(clk) then
if reset='1' or in_fifo_tflush='1' then
in_point <= 0;
in_state <= STORE;
last_point <= 0;
in_fifo_tfull <= '0';
else
-----------------------------
-- TLast Control
if reset_points='1' then
last_point <= 0;
elsif in_fifo_tlast='1' and in_fifo_tvalid='1' and in_state=STORE then
last_point <= in_point;
end if;
-----------------------------
-- TFull Control
if in_point=FIFO_SIZE or (in_point-1=last_point and last_point/=0) then
in_fifo_tfull <= '1';
else
in_fifo_tfull <= '0';
end if;
-----------------------------
-- Input Storage Control
case in_state is
when STORE =>
-- Assert ready whenever I am ready to accept data
in_fifo_tready_int <= '1';
-- Accept data only in ready has been high one clock, and not at end of array
if in_fifo_tvalid='1' and last_point=0 and in_point<FIFO_SIZE and in_fifo_tready_int='1' then
fifo_data(in_point) <= in_fifo_tdata;
in_point <= in_point + 1;
elsif (in_point-1=last_point and last_point/=0) or in_point=FIFO_SIZE then -- last word or last word in the FIFO
in_state <= WAIT_FOR_EMPTY;
in_fifo_tready_int <= '0';
end if;
when WAIT_FOR_EMPTY =>
if reset_points='1' then
in_state <= STORE;
in_point <= 0;
end if;
end case;
end if;
end if;
end process in_store_pr;
end block in_store_blk;
output_blk : block
type state_out is (INIT, GRAB_WORD, OUT_BYTE, NEXT_BYTE, UPDATE_POINT, WAIT_UPDATE);
signal out_state : state_out;
signal data_to_out : std_logic_vector(31 downto 0);
signal idx : natural range 0 to 3;
begin
output_pr : process(clk)
begin
if rising_edge(clk) then
if reset='1' or in_fifo_tflush='1' then
out_point <= 0;
out_state <= INIT;
out_fifo_tvalid <= '0';
out_fifo_tlast <= '0';
out_fifo_tdata <= x"00";
idx <= 0;
fifo_empty <= '1';
reset_points <= '0';
else
-- TEmpty Control
-- De-asserts FIFO empty if input starts increasing again.
if in_point > out_point then
fifo_empty <= '0';
else
fifo_empty <= '1';
end if;
case out_state is
when INIT =>
idx <= 0;
if out_fifo_tready='1' and fifo_empty='0' then
out_state <= GRAB_WORD;
end if;
when GRAB_WORD =>
if out_point < in_point then
data_to_out <= fifo_data(out_point);
out_state <= NEXT_BYTE;
else -- in case they pull before empty updates
out_state <= INIT;
end if;
when NEXT_BYTE =>
out_fifo_tdata <= data_to_out(idx*8 + 7 downto idx*8);
if out_fifo_tready='1' then
out_fifo_tvalid <= '1';
out_state <= OUT_BYTE;
if idx=3 and (last_point=out_point and last_point/=0) then
out_fifo_tlast <= '1';
else
out_fifo_tlast <= '0';
end if;
end if;
when OUT_BYTE =>
-- valid is only high one clock cycle
out_fifo_tvalid <= '0';
if idx=3 then -- get next word
out_state <= UPDATE_POINT;
else
idx <= idx + 1;
out_state <= NEXT_BYTE;
end if;
when UPDATE_POINT =>
-- reset pointers if at tlast or if read out last entry in FIFO
if (out_point = last_point and last_point/=0) or out_point=FIFO_SIZE-1 then
reset_points <= '1';
out_state <= WAIT_UPDATE;
else
out_point <= out_point + 1;
out_state <= INIT;
end if;
when WAIT_UPDATE =>
out_point <= 0;
-- waiting until the input stream is pointing at the beginning again
if in_point=0 then
reset_points <= '0';
out_state <= INIT;
end if;
end case;
end if;
end if;
end process output_pr;
end block output_blk;
in_fifo_tempty <= fifo_empty;
-- Process to take Deep FIFO output, break it down to 8-bit stream to UART
end architecture behave;
| gpl-2.0 | a2e04a45063c5252da8db61c6b7bcb70 | 0.450433 | 4.951633 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/FIFO_one_hot_credit_based_packet_drop_classifier_support_with_checkers/FIFO_one_hot_credit_based_packet_drop_classifier_support_with_checkers.vhd | 3 | 61,663 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic;
-- Checker outputs
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
component FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
fault_info_out: in std_logic;
fault_info_in: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end component;
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
-- Packet Dropping FSM states encoded as one-hot (because of checkers for one-bit error detection)
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
--alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3);
signal fault_info_in, fault_info_out: std_logic;
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
--type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop);
--signal state_out, state_in : state_type;
signal state_out, state_in : std_logic_vector(4 downto 0); -- : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
-- Signal(s) needed for FIFO control part checkers
signal fault_info_sig, health_info_sig : std_logic;
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop state machine
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
-- FIFO control part with packet drop and fault classifier support checkers instantiation
FIFO_control_part_checkers: FIFO_credit_based_control_part_checkers
port map (
valid_in => valid_in,
read_en_N => read_en_N,
read_en_E => read_en_E,
read_en_W => read_en_W,
read_en_S => read_en_S,
read_en_L => read_en_L,
read_pointer => read_pointer,
read_pointer_in => read_pointer_in,
write_pointer => write_pointer,
write_pointer_in => write_pointer_in,
credit_out => credit_in, -- correct ?
empty_out => empty,
full_out => full,
read_en_out => read_en,
write_en_out => write_en,
fake_credit => fake_credit,
fake_credit_counter => fake_credit_counter,
fake_credit_counter_in => fake_credit_counter_in,
state_out => state_out,
state_in => state_in,
fault_info => fault_info_sig, -- connected to signal
fault_info_out => fault_info_out,
fault_info_in => fault_info_in,
health_info => health_info_sig, -- connected to signal
faulty_packet_out => faulty_packet_out,
faulty_packet_in => faulty_packet_in,
flit_type => RX(DATA_WIDTH-1 downto DATA_WIDTH-3),
fault_out => fault_out,
write_fake_flit => write_fake_flit,
-- Functional checkers
err_empty_full => err_empty_full,
err_empty_read_en => err_empty_read_en,
err_full_write_en => err_full_write_en,
err_state_in_onehot => err_state_in_onehot,
err_read_pointer_in_onehot => err_read_pointer_in_onehot,
err_write_pointer_in_onehot => err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => err_write_en_write_pointer,
err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment,
err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en,
err_not_write_en => err_not_write_en,
err_not_write_en1 => err_not_write_en1,
err_not_write_en2 => err_not_write_en2,
err_read_en_mismatch => err_read_en_mismatch,
err_read_en_mismatch1 => err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
fault_info <= fault_info_sig; -- Not sure yet ?!
health_info <= health_info_sig;
-- Sequential part
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
fault_info_out <= '0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
fault_info_out <= fault_info_in;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
fault_info_sig <= fault_info_out;
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if fake_credit = '1' or read_en ='1' then
credit_in <= '1';
end if;
if fake_credit = '0' and read_en = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
process(valid_in, RX) begin
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
else
xor_all <= '0';
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out <= '1';
end if;
end process;
process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, valid_in) begin
-- this is the default value of the memory!
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
--some defaults
fault_info_in <= '0';
health_info_sig <= '0';
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_out = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= Body_flit;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= state_out;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
health_info_sig <= '1';
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else -- fault_out = '1'
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
if faulty_packet_out = '1' then
if valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" and fault_out = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
elsif valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" and fault_out = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else -- fault_out might have been '1'
if valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
fault_info_in <= '1';
end if;
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
else
-- we should not be here!
state_in <= state_out;
end if;
when others => state_in <= state_out;
end case;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin
if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
| gpl-3.0 | d7d8b8a8fba33a6d3637f632423b9976 | 0.518869 | 3.587352 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/Checkers/Control_Part_Checkers/FIFO_one_hot_credit_based_packet_drop_classifier_support_checkers/RTL/FIFO_one_hot_credit_based_packet_drop_classifier_support_checkers.vhd | 3 | 54,694 | --Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
--err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out,
--err_valid_in_state_out_state_in_not_change,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
--err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
--err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
--err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change : out std_logic
--err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change
--err_state_out_invalid_state_in_state_out_not_change,
--err_state_out_invalid_not_fault_info,
--err_state_out_invalid_not_health_info,
--err_state_out_invalid_not_fake_credit,
--err_state_out_invalid_not_write_fake_flit,
--err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change: out std_logic
);
end FIFO_credit_based_control_part_checkers;
architecture behavior of FIFO_credit_based_control_part_checkers is
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
--signal read_en_signal: std_logic;
begin
--read_en_signal <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty_out;
-- Functional Checkers (Might cover or be covered by some of the structural checkers)
-- Empty and full cannot be high at the same time!
process (empty_out, full_out)
begin
if (empty_out = '1' and full_out = '1') then
err_empty_full <= '1';
else
err_empty_full <= '0';
end if;
end process;
-- Reading from an empty FIFO is not possible!
process (empty_out, read_en_out)
begin
if (empty_out = '1' and read_en_out = '1') then
err_empty_read_en <= '1';
else
err_empty_read_en <= '0';
end if;
end process;
-- Writing to a full FIFO is not possible!
process (full_out, write_en_out)
begin
if (full_out = '1' and write_en_out = '1') then
err_full_write_en <= '1';
else
err_full_write_en <= '0';
end if;
end process;
-- The states of the packet dropping FSM of FIFO must always be one-hot (state_in)!
process (state_in)
begin
if (state_in /= Idle and state_in /= Header_flit and state_in /= Body_flit and state_in /= Tail_flit and state_in /= Packet_drop) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
-- Read pointer must always be one-hot!
process (read_pointer_in)
begin
if (read_pointer_in /= "0001" and read_pointer_in /= "0010" and read_pointer_in /= "0100" and read_pointer_in /= "1000") then
err_read_pointer_in_onehot <= '1';
else
err_read_pointer_in_onehot <= '0';
end if;
end process;
-- Write pointer must always be one-hot!
process (write_pointer_in)
begin
if (write_pointer_in /= "0001" and write_pointer_in /= "0010" and write_pointer_in /= "0100" and write_pointer_in /= "1000") then
err_write_pointer_in_onehot <= '1';
else
err_write_pointer_in_onehot <= '0';
end if;
end process;
---------------------------------------------------------------------------------------------------------
-- Structural Checkers
-- Write pointer and Read pointer checkers
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then
err_write_en_write_pointer <= '1';
else
err_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '0' and write_pointer_in /= write_pointer ) then
err_not_write_en_write_pointer <= '1';
else
err_not_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer = write_pointer and empty_out = '0' ) then
err_read_pointer_write_pointer_not_empty <= '1';
else
err_read_pointer_write_pointer_not_empty <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer /= write_pointer and empty_out = '1' ) then
err_read_pointer_write_pointer_empty <= '1';
else
err_read_pointer_write_pointer_empty <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then
err_read_pointer_write_pointer_not_full <= '1';
else
err_read_pointer_write_pointer_not_full <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then
err_read_pointer_write_pointer_full <= '1';
else
err_read_pointer_write_pointer_full <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then
err_read_pointer_increment <= '1';
else
err_read_pointer_increment <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if ( (read_en_out = '0' or empty_out = '1') and read_pointer_in /= read_pointer ) then
err_read_pointer_not_increment <= '1';
else
err_read_pointer_not_increment <= '0';
end if;
end process;
-- Checked !
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if (valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out ='0' and write_en_out = '0') then
err_write_en <= '1';
else
err_write_en <= '0';
end if;
end process;
-- Updated !
process (valid_in, write_en_out)
begin
if (valid_in = '0' and write_en_out = '1') then
err_not_write_en <= '1';
else
err_not_write_en <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0') and write_en_out = '1') then
err_not_write_en1 <= '1';
else
err_not_write_en1 <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out = '1' and write_en_out = '1') then
err_not_write_en2 <= '1';
else
err_not_write_en2 <= '0';
end if;
end process;
-- Updated !
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( (read_en_N = '1' or read_en_E = '1' or read_en_W = '1' or read_en_S = '1' or read_en_L = '1') and empty_out = '0' and read_en_out = '0' ) then
err_read_en_mismatch <= '1';
else
err_read_en_mismatch <= '0';
end if;
end process;
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( ((read_en_N = '0' and read_en_E = '0' and read_en_W = '0' and read_en_S = '0' and read_en_L = '0') or empty_out = '1') and read_en_out = '1' ) then
err_read_en_mismatch1 <= '1';
else
err_read_en_mismatch1 <= '0';
end if;
end process;
-- Newly added checkers for FIFO with packet drop and fault classifier support!
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter + 1) then
err_fake_credit_read_en_fake_credit_counter_in_increment <= '1';
else
err_fake_credit_read_en_fake_credit_counter_in_increment <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and fake_credit_counter_in /= fake_credit_counter - 1 ) then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '0' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '0' and fake_credit_counter_in /= fake_credit_counter) then
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '1';
else
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, credit_out)
begin
if ((fake_credit = '1' or read_en_out ='1') and credit_out = '0') then
err_fake_credit_read_en_credit_out <= '1';
else
err_fake_credit_read_en_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and credit_out = '0') then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and credit_out = '1') then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '0';
end if;
end process;
--process (fake_credit, read_en_out, credit_out)
--begin
-- if (fake_credit = '1' and read_en_out = '1' and credit_out = '1') then
-- err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out <= '1';
-- else
-- err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out <= '0';
-- end if;
--end process;
-- Checkers for Packet Dropping FSM of FIFO
--process (valid_in, state_out, state_in)
--begin
-- if (valid_in = '0' and (state_out = Idle or state_out = Header_flit or state_out = Body_flit or state_out = Packet_drop) and state_in /= state_out) then
-- err_valid_in_state_out_state_in_not_change <= '1';
-- else
-- err_valid_in_state_out_state_in_not_change <= '0';
-- end if;
--end process;
-- Idle state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, valid_in, state_in)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '1' and state_in /= Header_flit) then
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, fault_out, valid_in, state_in, state_out)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '0' and state_in /= state_out) then
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '0';
end if;
end process;
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '0' and fake_credit = '1') then
err_state_out_Idle_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Idle_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, fault_info)
begin
if (state_out = Idle and fault_out = '0' and fault_info = '1') then
err_state_out_Idle_not_fault_out_not_fault_info <= '1';
else
err_state_out_Idle_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Idle and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '1' and fake_credit = '0') then
err_state_out_Idle_fault_out_fake_credit <= '1';
else
err_state_out_Idle_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, state_in)
begin
if (state_out = Idle and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Idle_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Idle_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, fault_out, fault_info)
begin
if (state_out = Idle and fault_out = '1' and fault_info = '0') then
err_state_out_Idle_fault_out_fault_info <= '1';
else
err_state_out_Idle_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in)
begin
if (state_out = Idle and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Idle_fault_out_faulty_packet_in <= '1';
else
err_state_out_Idle_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Idle and write_fake_flit = '1') then
err_state_out_Idle_not_write_fake_flit <= '1';
else
err_state_out_Idle_not_write_fake_flit <= '0';
end if;
end process;
-- Other properties for Idle state
--------------------------------------------------------------------------------------------------
process (state_out, health_info)
begin
if ( (state_out = Idle or state_out = Header_flit or state_out = Tail_flit or state_out = Packet_drop) and health_info = '1') then
err_state_out_Idle_not_health_info <= '1';
else
err_state_out_Idle_not_health_info <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Header_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= Body_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type /= "010" and flit_type /= "100" and state_in /= state_out) then
-- err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Header_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in, state_out)
begin
if (state_out = Header_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Header_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Header_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Header_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if ( (state_out = Header_flit or state_out = Body_flit) and fake_credit /= '0') then
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '1';
else
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Body_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= state_out) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and health_info = '0') then
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "100" and health_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and health_info = '1') then
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, health_info)
begin
if (state_out = Body_flit and valid_in = '0' and health_info = '1') then
err_state_out_Body_flit_valid_in_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_health_info <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "010" and flit_type /= "100" and state_in /= state_out) then
-- err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_fault_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Body_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Body_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Body_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Body_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Body_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if (state_out = Body_flit and fake_credit = '1') then
err_state_out_Body_flit_not_fake_credit <= '1';
else
err_state_out_Body_flit_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Tail_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type = "001" and state_in /= Header_flit) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type /= "001" and state_in /= state_out) then
-- err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fake_credit = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fake_credit /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Tail_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Tail_flit and valid_in = '0' and state_in /= Idle) then
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '1';
else
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '1';
else
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Tail_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Tail_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '0' and fake_credit /= '0') then
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Tail_flit and write_fake_flit = '1') then
err_state_out_Tail_flit_not_write_fake_flit <= '1';
else
err_state_out_Tail_flit_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Packet_drop state
-- faulty_packet_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and fake_credit /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and state_in /= Header_flit) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and write_fake_flit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and state_in /= Idle) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ( valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1' ) and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and fake_credit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '0';
end if;
end process;
-- faulty_packet_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, fault_info)
begin
if (state_out = Packet_drop and fault_info = '1') then
err_state_out_Packet_drop_not_fault_info <= '1';
else
err_state_out_Packet_drop_not_fault_info <= '0';
end if;
end process;
process (state_out, faulty_packet_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and fake_credit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001" or fault_out = '1') and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '0';
end if;
end process;
--process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
--begin
-- if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
-- err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change <= '0';
-- end if;
--end process;
-- Invalid state
--process (state_out, state_in)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and state_in /= state_out) then
-- err_state_out_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
--process (state_out, fault_info)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and fault_info = '1') then
-- err_state_out_invalid_not_fault_info <= '1';
-- else
-- err_state_out_invalid_not_fault_info <= '0';
-- end if;
--end process;
--process (state_out, health_info)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and health_info = '1') then
-- err_state_out_invalid_not_health_info <= '1';
-- else
-- err_state_out_invalid_not_health_info <= '0';
-- end if;
--end process;
--process (state_out, fake_credit)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and fake_credit = '1') then
-- err_state_out_invalid_not_fake_credit <= '1';
-- else
-- err_state_out_invalid_not_fake_credit <= '0';
-- end if;
--end process;
--process (state_out, write_fake_flit)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and write_fake_flit = '1') then
-- err_state_out_invalid_not_write_fake_flit <= '1';
-- else
-- err_state_out_invalid_not_write_fake_flit <= '0';
-- end if;
--end process;
--process (state_out, faulty_packet_in, faulty_packet_out)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and faulty_packet_in /= faulty_packet_out) then
-- err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change <= '1';
-- else
-- err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change <= '0';
-- end if;
--end process;
end behavior; | gpl-3.0 | ad9fffd538579b394e4cbd9f22a3eb8a | 0.666746 | 2.70977 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/Allocator_with_checkers_with_FI/Arbiter_in_one_hot_checkers.vhd | 3 | 22,792 | --Copyright (C) 2016 Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
use work.component_pack.all;
entity Arbiter_in_one_hot_checkers is
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N, err_IDLE_grant_N,err_North_Req_N, err_North_grant_N, err_East_Req_E, err_East_grant_E,
err_West_Req_W, err_West_grant_W, err_South_Req_S,err_South_grant_S,err_Local_Req_L, err_Local_grant_L,
err_IDLE_Req_E, err_IDLE_grant_E, err_North_Req_E, err_North_grant_E, err_East_Req_W, err_East_grant_W,
err_West_Req_S, err_West_grant_S, err_South_Req_L, err_South_grant_L, err_Local_Req_N, err_Local_grant_N,
err_IDLE_Req_W, err_IDLE_grant_W, err_North_Req_W, err_North_grant_W, err_East_Req_S, err_East_grant_S,
err_West_Req_L, err_West_grant_L, err_South_Req_N, err_South_grant_N, err_Local_Req_E, err_Local_grant_E,
err_IDLE_Req_S, err_IDLE_grant_S, err_North_Req_S, err_North_grant_S, err_East_Req_L, err_East_grant_L,
err_West_Req_N, err_West_grant_N, err_South_Req_E, err_South_grant_E, err_Local_Req_W, err_Local_grant_W,
err_IDLE_Req_L, err_IDLE_grant_L, err_North_Req_L, err_North_grant_L, err_East_Req_N, err_East_grant_N,
err_West_Req_E, err_West_grant_E, err_South_Req_W, err_South_grant_W, err_Local_Req_S, err_Local_grant_S,
err_state_in_onehot, err_no_request_grants, err_request_no_grants, err_no_Req_N_grant_N,
err_no_Req_E_grant_E, err_no_Req_W_grant_W, err_no_Req_S_grant_S, err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_checkers;
architecture behavior of Arbiter_in_one_hot_checkers is
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= X_N & X_E & X_W & X_S & X_L;
-- Checkers
--checked
process (state, Requests, state_in)
begin
--if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and state_in /= state ) then
if (Requests = "00000" and state_in /= state ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
err_IDLE_Req_N <= '0';
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_Req_N <= '1';
end if;
end process;
process (state, req_X_N, X_N)
begin
err_IDLE_grant_N <= '0';
if ( state = IDLE and req_X_N = '1' and X_N = '0' ) then
err_IDLE_grant_N <= '1';
end if;
end process;
process (state, req_X_N, state_in)
begin
err_North_Req_N <= '0';
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_Req_N <= '1';
end if;
end process;
process (state, req_X_N, X_N)
begin
err_North_grant_N <= '0';
if ( state = North and req_X_N = '1' and X_N = '0' ) then
err_North_grant_N <= '1';
end if;
end process;
process (state, req_X_E, state_in)
begin
err_East_Req_E <= '0';
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_Req_E <= '1';
end if;
end process;
process (state, req_X_E, X_E)
begin
err_East_grant_E <= '0';
if ( state = East and req_X_E = '1' and X_E = '0' ) then
err_East_grant_E <= '1';
end if;
end process;
process (state, req_X_W, state_in)
begin
err_West_Req_W <= '0';
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_Req_W <= '1';
end if;
end process;
process (state, req_X_W, X_W)
begin
err_West_grant_W <= '0';
if ( state = West and req_X_W = '1' and X_W = '0' ) then
err_West_grant_W <= '1';
end if;
end process;
process (state, req_X_S, state_in)
begin
err_South_Req_S <= '0';
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_Req_S <= '1';
end if;
end process;
process (state, req_X_S, X_S)
begin
err_South_grant_S <= '0';
if ( state = South and req_X_S = '1' and X_S = '0' ) then
err_South_grant_S <= '1';
end if;
end process;
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
err_Local_Req_L <= '0';
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_Req_L <= '1';
end if;
end process;
process (state, req_X_L, X_L)
begin
err_Local_grant_L <= '0';
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and X_L = '0' ) then
err_Local_grant_L <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 2
--checked
process (state, req_X_N, req_X_E, state_in)
begin
err_IDLE_Req_E <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_Req_E <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
err_IDLE_grant_E <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_IDLE_grant_E <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, state_in)
begin
err_North_Req_E <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_Req_E <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
err_North_grant_E <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_North_grant_E <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, state_in)
begin
err_East_Req_W <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_Req_W <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, X_W)
begin
err_East_grant_W <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_East_grant_W <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, state_in)
begin
err_West_Req_S <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_Req_S <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, X_S)
begin
err_West_grant_S <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_West_grant_S <= '1';
end if;
end process;
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
err_South_Req_L <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_Req_L <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, X_L)
begin
err_South_grant_L <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_South_grant_L <= '1';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
err_Local_Req_N <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_Req_N <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, X_N)
begin
err_Local_grant_N <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_Local_grant_N <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
err_IDLE_Req_W <= '0';
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_Req_W <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
err_IDLE_grant_W <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_IDLE_grant_W <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
err_North_Req_W <= '0';
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_Req_W <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
err_North_grant_W <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_North_grant_W <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
err_East_Req_S <= '0';
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_Req_S <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, X_S)
begin
err_East_grant_S <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_East_grant_S <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
err_West_Req_L <= '0';
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_Req_L <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, X_L)
begin
err_West_grant_L <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_West_grant_L <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
err_South_Req_N <= '0';
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_Req_N <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, X_N)
begin
err_South_grant_N <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_South_grant_N <= '1';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
err_Local_Req_E <= '0';
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_Req_E <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, X_E)
begin
err_Local_grant_E <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_Local_grant_E <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_IDLE_Req_S <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_Req_S <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
err_IDLE_grant_S <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_IDLE_grant_S <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_North_Req_S <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_Req_S <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
err_North_grant_S <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_North_grant_S <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_East_Req_L <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_Req_L <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
err_East_grant_L <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0') then
err_East_grant_L <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
err_West_Req_N <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_Req_N <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
err_West_grant_N <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0') then
err_West_grant_N <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
err_South_Req_E <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_Req_E <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
err_South_grant_E <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0') then
err_South_grant_E <= '1';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
err_Local_Req_W <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_Req_W <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
err_Local_grant_W <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0') then
err_Local_grant_W <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_IDLE_Req_L <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_Req_L <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
err_IDLE_grant_L <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_IDLE_grant_L <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_North_Req_L <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_Req_L <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
err_North_grant_L <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_North_grant_L <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
err_East_Req_N <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_Req_N <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
err_East_grant_N <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0' ) then
err_East_grant_N <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
err_West_Req_E <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_Req_E <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
err_West_grant_E <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0' ) then
err_West_grant_E <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
err_South_Req_W <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_Req_W <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
err_South_grant_W <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0' ) then
err_South_grant_W <= '1';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_Local_Req_S <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_Req_S <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
err_Local_grant_S <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0' ) then
err_Local_grant_S <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
process (state_in)
begin
err_state_in_onehot <= '0';
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
end if;
end process;
process (Requests, Grants)
begin
err_no_request_grants <= '0';
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
end if;
end process;
process (Requests, Grants)
begin
err_request_no_grants <= '0';
if ( Requests /= "00000" and Grants = "00000") then
err_request_no_grants <= '1';
end if;
end process;
process (req_X_N, X_N)
begin
err_no_Req_N_grant_N <= '0';
if (req_X_N = '0' and X_N = '1') then
err_no_Req_N_grant_N <= '1';
end if;
end process;
process (req_X_E, X_E)
begin
err_no_Req_E_grant_E <= '0';
if (req_X_E = '0' and X_E = '1') then
err_no_Req_E_grant_E <= '1';
end if;
end process;
process (req_X_W, X_W)
begin
err_no_Req_W_grant_W <= '0';
if (req_X_W = '0' and X_W = '1') then
err_no_Req_W_grant_W <= '1';
end if;
end process;
process (req_X_S, X_S)
begin
err_no_Req_S_grant_S <= '0';
if (req_X_S = '0' and X_S = '1') then
err_no_Req_S_grant_S <= '1';
end if;
end process;
process (req_X_L, X_L)
begin
err_no_Req_L_grant_L <= '0';
if (req_X_L = '0' and X_L = '1') then
err_no_Req_L_grant_L <= '1';
end if;
end process;
end behavior; | gpl-3.0 | 54debfd3d51b12ac5cbf1b92f8843c71 | 0.495261 | 2.608676 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/RTL/New_SHMU_on_Node/Router_32_bit_credit_based_packet_drop_classifier_SHMU.vhd | 3 | 20,957 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(7 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end router_credit_based_PD_C_SHMU;
architecture behavior of router_credit_based_PD_C_SHMU is
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic
);
end COMPONENT;
COMPONENT counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, intermittent, Faulty: out std_logic
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR_packet_drop is
generic (
cur_addr_rst: integer := 0;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic;
signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic;
signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic;
signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic;
begin
turn_faults <= "00000000";
--link_faults <= sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L;
link_faults <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L;
Faulty_N_out <= sig_Faulty_N_out;
Faulty_E_out <= sig_Faulty_E_out;
Faulty_W_out <= sig_Faulty_W_out;
Faulty_S_out <= sig_Faulty_S_out;
-- all the counter_threshold modules
CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N,
Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out);
CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E,
Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out);
CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W,
Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out);
CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S,
Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out);
CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L,
Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
--- all the LBDRs
LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_N,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_E,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_W,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_S,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_L,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
| gpl-3.0 | f7ced6c3601d2b107775d71420ae75ce | 0.564919 | 3.046076 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/Testbenches/immortal_temp_iddt_monitor_tb.vhd | 3 | 5,070 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 26.09.2017
-- Design Name:
-- Module Name: immortal_temp_iddt_monitor_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity immortal_temp_iddt_monitor_tb is
end immortal_temp_iddt_monitor_tb;
architecture Behavioral of immortal_temp_iddt_monitor_tb is
constant tck_period : time := 10 ns;
constant HALF_SEPARATOR : time := 2*tck_period;
constant FULL_SEPARATOR : time := 8*tck_period;
signal toSI : STD_LOGIC;
signal fromSO : STD_LOGIC;
signal SE : STD_LOGIC;
signal CE : STD_LOGIC;
signal UE : STD_LOGIC;
signal TCK : STD_LOGIC;
signal RST : STD_LOGIC;
signal SEL : STD_LOGIC;
signal toF : STD_LOGIC;
signal toC : STD_LOGIC;
signal temp_control : std_logic_vector (2 downto 0);
signal temp_adc_data : std_logic_vector (11 downto 0);
signal temp_adc_drdy : std_logic;
component immortal_temp_iddt_monitor_instrument is
port (
-- IJTAG connection
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- Monitor connections
control : out std_logic_vector(2 downto 0);
adc_data : in std_logic_vector(11 downto 0);
adc_drdy : in std_logic
);
end component;
begin
temp_monitor : immortal_temp_iddt_monitor_instrument
port map (
-- IJTAG connection
TCK => TCK,
RST => RST,
SEL => SEL,
SI => toSI,
SE => SE,
UE => UE,
CE => CE,
SO => fromSO,
toF => toF,
toC => toC,
-- Monitor connections
control => temp_control,
adc_data => temp_adc_data,
adc_drdy => temp_adc_drdy
);
ijtag_shift_proc: process
-- Generate a number of TCK ticks
procedure tck_tick (number_of_tick : in positive) is
begin
for i in 1 to number_of_tick loop
TCK <= '0';
wait for TCK_period/2;
TCK <= '1';
wait for TCK_period/2;
end loop;
end procedure tck_tick;
procedure tck_halftick_high is
begin
TCK <= '1';
wait for TCK_period/2;
end procedure tck_halftick_high;
procedure tck_halftick_low is
begin
TCK <= '0';
wait for TCK_period/2;
end procedure tck_halftick_low;
-- Shifts in specified data (Capture -> Shift -> Update)
procedure shift_data (data : in std_logic_vector) is
begin
--Capture phase
CE <= '1';
tck_tick(1);
CE <= '0';
--Shift phase
SE <= '1';
for i in data'range loop
toSI <= data(i);
tck_tick(1);
end loop;
SE <= '0';
-- Update phase
--tck_tick(1);
tck_halftick_low;
UE <= '1';
tck_halftick_high;
tck_halftick_low;
UE <= '0';
tck_halftick_high;
end procedure shift_data;
-- Returns all zeroes std_logic_vector of specified size
function all_zeroes (number_of_zeroes : in positive) return std_logic_vector is
variable zero_array : std_logic_vector(0 to number_of_zeroes-1);
begin
for i in zero_array'range loop
zero_array(i) := '0';
end loop;
return zero_array;
end function all_zeroes;
begin
temp_adc_data <= "000000000000";
temp_adc_drdy <= '0';
UE <= '0';
CE <= '0';
SE <= '0';
toSI <= '0';
-- Reset iJTAG chain and Instruments
RST <= '1';
wait for tck_period;
RST <= '0';
SEL <= '1';
tck_tick(4);
shift_data("001000000000"&"010000000000"&"0"&"1"&"1"&"01111"); -- shift in threshold H without update
tck_tick(4);
temp_adc_data <= "000000000011";
tck_tick(1);
temp_adc_drdy <= '1';
tck_tick(1);
temp_adc_drdy <= '0';
tck_tick(4);
temp_adc_data <= "000000000100";
tck_tick(1);
temp_adc_drdy <= '1';
tck_tick(1);
temp_adc_drdy <= '0';
tck_tick(4);
temp_adc_data <= "000000001100";
tck_tick(1);
temp_adc_drdy <= '1';
tck_tick(1);
temp_adc_drdy <= '0';
tck_tick(4);
shift_data("001000000000"&"010000000000"&"0"&"0"&"1"&"01011"); -- shift in threshold H without update
tck_tick(10);
wait;
end process;
end Behavioral;
| gpl-3.0 | 9c745a656b251f3f10d60b2a90448845 | 0.554241 | 3.621429 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/TB_Package_32_bit_credit_based.vhd | 9 | 15,781 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integer ) return std_logic_vector ;
function Body_gen(Packet_length, Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0));
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector);
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(Packet_length, source, destination, packet_id: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
begin
Header_flit := Header_type & std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)) & XOR_REDUCE(Header_type &
std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)));
return Header_flit;
end Header_gen;
function Body_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0)) is
variable credit_counter: std_logic_vector (1 downto 0);
begin
credit_counter := "11";
while true loop
credit_counter_out<= credit_counter;
wait until clk'event and clk ='1';
if valid_out = '1' and credit_in ='1' then
credit_counter := credit_counter;
elsif credit_in = '1' then
credit_counter := credit_counter + 1;
elsif valid_out = '1' and credit_counter > 0 then
credit_counter := credit_counter - 1;
else
credit_counter := credit_counter;
end if;
end loop;
end credit_counter_control;
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive ;
variable seed2 :positive ;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive ;
variable seed2 :positive ;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_bit_reversed_packet;
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
begin
credit_out <= '1', '0' after 26 us;
counter := 0;
while true loop
wait until clk'event and clk ='1';
if valid_in = '1' then
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
P_length := to_integer(unsigned(port_in(28 downto 17)));
destination_node := to_integer(unsigned(port_in(16 downto 13)));
source_node := to_integer(unsigned(port_in(12 downto 9)));
packet_id := to_integer(unsigned(port_in(8 downto 1)));
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then
--report "flit type: " &integer'image(to_integer(unsigned(port_in(DATA_WIDTH-1 downto DATA_WIDTH-3)))) ;
--report "counter: " & integer'image(counter);
counter := counter+1;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then
counter := counter+1;
report "Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter);
assert (P_length=counter) report "wrong packet size" severity warning;
assert (Node_ID=destination_node) report "wrong packet destination " severity warning;
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(VEC_FILE, LINEVARIABLE);
counter := 0;
end if;
end if;
end loop;
end get_packet;
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer) is
variable seed1 :positive := seed_1;
variable seed2 :positive := seed_2;
variable rand : real;
variable stuck: integer;
begin
sta_0 <= '0';
sta_1 <= '0';
while true loop
sta_0 <= '0';
sta_1 <= '0';
for I in 0 to delay loop
wait for 1 ns;
end loop;
uniform(seed1, seed2, rand);
address <= std_logic_vector(to_unsigned(integer(rand*31.0), 5));
uniform(seed1, seed2, rand);
stuck := integer(rand*11.0);
if stuck > 5 then
sta_0 <= '1';
sta_1 <= '0';
else
sta_0 <= '0';
sta_1 <= '1';
end if;
wait for 1 ns;
end loop;
end gen_fault;
end TB_Package;
| gpl-3.0 | 9e2a0db58a77c6cd43b2bfaa45379291 | 0.59578 | 3.777166 | false | false | false | false |
ashtonchase/logic_analyzer | src/UART.vhd | 1 | 8,267 | -------------------------------------------------------------------------------
-- Title : UART
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : UART.vhd
-- Created : 2016-02-22
-- Last update: 2016-03-28
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: This is the UART the sump comms module will use. It is capable
-- of taking an input baud rate and clock frequency to run a baud clock using a
-- clock divider. It transmits data when the transmit data (data_out)changes and
-- recieves data when it recieves a low signal on the rx line.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-22 1.0 ian Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity uart_comms is
generic (baud_rate : positive := 115_200;
clock_freq : positive := 100_000_000); -- Make sure we keep integer division here
port(clk : in std_logic; -- clock
rst : in std_logic; -- reset logic
rx_get_more_data : in std_logic; -- stop bit found for stream in
rx_data_ready : out std_logic; -- stream out ready
rx : in std_logic; -- recieve line
data_in : in std_logic_vector(7 downto 0) := (others => '0'); -- data to be transmitted
tx_data_ready : in std_logic; -- stream out stop bit sent
tx_data_sent : out std_logic; -- ready for rx
tx : out std_logic; -- transmit line
data_out : out std_logic_vector(7 downto 0));
--state : out integer;
-- baud16 : out std_logic); -- data recieved from rx line
begin --added comment
assert(clock_freq mod baud_rate = 0) report ("Non Integer Division") severity(error);
end entity uart_comms;
architecture pass_through of uart_comms is
type states is (Init, Wait_State, Get_Data, Send_Data, Data_Ready, Send_Complete);
signal rx_current_state, rx_next_state, tx_current_state, tx_next_state : states;
signal rx_counter, tx_counter : integer range 0 to 255 := 0;
signal trans_data : std_logic_vector(7 downto 0) := (others => '0');
signal data_out_sig : std_logic_vector(7 downto 0) := (others => '0');
signal baud_clock, baud_clock_x16 : std_logic := '0';
signal baud_counter, baud_counter_x16 : integer range 0 to 1024 := 0;
signal sampling_counter, zero_counter : integer range 0 to 16 := 0;
signal baud_reset, baud_reset_last : std_logic := '0';
constant baud_total : integer := (clock_freq/baud_rate)/2;
constant baud_total_x16 : integer := (clock_freq/baud_rate)/16/2;
begin
-- Create baud clock
baud_clocking : process (clk)
begin
if(clk = '1' and clk'event) then
if (baud_counter < baud_total - 1) then
baud_counter <= baud_counter + 1;
else
baud_counter <= 0;
baud_clock <= not baud_clock;
end if;
end if;
end process baud_clocking;
baud_clocking_x16 : process (clk)
begin
if (clk = '1' and clk'event) then
baud_reset_last <= baud_reset;
if(baud_reset = '1' and baud_reset_last = '0') then
baud_counter_x16 <= 0;
baud_clock_x16 <= '0';
elsif (baud_counter_x16 < ((baud_total_x16) - 1)) then
baud_counter_x16 <= baud_counter_x16 + 1;
else
baud_counter_x16 <= 0;
baud_clock_x16 <= not baud_clock_x16;
end if;
end if;
end process baud_clocking_x16;
-- baud16 <= baud_clock_x16;
-- State transition logic for RX
rx_moore : process (baud_clock_x16)
begin
if rst = '1' then
rx_next_state <= Init;
elsif baud_clock_x16 = '1' and baud_clock_x16'event then
baud_reset <= '0';
rx_data_ready <= '0';
case rx_current_state is
when Init =>
rx_next_state <= Wait_State;
baud_reset <= '1';
sampling_counter <= 0;
rx_counter <= 0;
zero_counter <= 0;
when Wait_State =>
rx_next_state <= Wait_State;
if rx = '0' then
zero_counter <= zero_counter + 1;
else
zero_counter <= 0;
end if;
if zero_counter > 9 then
rx_next_state <= Get_Data;
baud_reset <= '1';
sampling_counter <= 0;
rx_counter <= 0;
zero_counter <= 0;
end if;
when Get_Data =>
rx_next_state <= Get_Data;
if sampling_counter < 15 then
sampling_counter <= sampling_counter + 1;
else
sampling_counter <= 0;
if rx_counter < 8 then
rx_counter <= rx_counter + 1;
data_out_sig <= rx & data_out_sig(7 downto 1); -- shift right
else
rx_counter <= 0;
rx_next_state <= Data_Ready;
end if;
end if;
when Data_Ready =>
rx_next_state <= Data_Ready;
data_out <= data_out_sig;
rx_data_ready <= '1';
if rx_get_more_data <= '1' then
rx_next_state <= Wait_State;
end if;
when others => null;
end case;
end if;
rx_current_state <= rx_next_state;
end process rx_moore;
-- State transition logic for TX
tx_moore : process (baud_clock)
begin
if rst = '1' then
tx_next_state <= Init;
elsif baud_clock = '1' and baud_clock'event then
tx <= '1';
tx_data_sent <= '0';
case tx_current_state is
when Init =>
tx_next_state <= Wait_State;
tx_data_sent <= '0';
trans_data <= data_in;
tx_counter <= 0;
when Wait_State =>
tx_next_state <= Wait_State;
if tx_data_ready = '1' then
tx_next_state <= Send_Data;
trans_data <= data_in;
tx_counter <= 0;
tx <= '0';
end if;
when Send_Data =>
tx_next_state <= Send_Data;
if tx_counter < 8 then -- transmit 8 bits
tx <= trans_data(tx_counter);
tx_counter <= tx_counter + 1;
else -- transmit high end bit
tx <= '1';
tx_next_state <= Send_Complete;
end if;
when Send_Complete =>
tx_next_state <= Wait_State;
tx_data_sent <= '1';
when others => null;
end case;
end if;
tx_current_state <= tx_next_state;
end process tx_moore;
end architecture pass_through;
| gpl-2.0 | fc2c73ef2df90deda13549d6b72ecda8 | 0.49619 | 4.032683 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/RTL/NI_Test/ParityChecker_for_LBDR.vhd | 9 | 681 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
entity parity_checker_for_LBDR is
generic(DATA_WIDTH : integer := 32);
port(
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
empty: in std_logic;
faulty: out std_logic
);
end parity_checker_for_LBDR;
architecture behavior of parity_checker_for_LBDR is
signal xor_all: std_logic;
begin
process(empty, RX) begin
if empty = '0' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
else
xor_all <= '0';
end if;
end process;
process(RX, xor_all)begin
faulty <= '0';
if xor_all /= RX(0) then
faulty <= '1';
end if;
end process;
end;
| gpl-3.0 | 62a4daa489ef25ec222dcb0780042bdf | 0.679883 | 2.724 | false | false | false | false |
AndyMcC0/UVVM_All | uvvm_vvc_framework/src/ti_vvc_framework_support_pkg.vhd | 1 | 17,006 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package ti_vvc_framework_support_pkg is
------------------------------------------------------------------------
-- Common support types for UVVM
------------------------------------------------------------------------
type t_immediate_or_queued is (NO_command_type, IMMEDIATE, QUEUED);
type t_flag_record is record
set : std_logic;
reset : std_logic;
is_active : std_logic;
end record;
type t_uvvm_state is (IDLE, PHASE_A, PHASE_B, INIT_COMPLETED);
type t_lastness is (LAST, NOT_LAST);
type t_broadcastable_cmd is (NO_CMD, ENABLE_LOG_MSG, DISABLE_LOG_MSG, FLUSH_COMMAND_QUEUE, INSERT_DELAY, AWAIT_COMPLETION, TERMINATE_CURRENT_COMMAND);
constant C_BROADCAST_CMD_STRING_MAX_LENGTH : natural := 300;
type t_vvc_broadcast_cmd_record is record
operation : t_broadcastable_cmd;
msg_id : t_msg_id;
msg : string(1 to C_BROADCAST_CMD_STRING_MAX_LENGTH);
proc_call : string(1 to C_BROADCAST_CMD_STRING_MAX_LENGTH);
quietness : t_quietness;
delay : time;
timeout : time;
gen_integer : integer;
end record;
constant C_VVC_BROADCAST_CMD_DEFAULT : t_vvc_broadcast_cmd_record := (
operation => NO_CMD,
msg_id => NO_ID,
msg => (others => NUL),
proc_call => (others => NUL),
quietness => NON_QUIET,
delay => 0 ns,
timeout => 0 ns,
gen_integer => -1
);
------------------------------------------------------------------------
-- Common signals for acknowledging a pending command
------------------------------------------------------------------------
shared variable shared_vvc_broadcast_cmd : t_vvc_broadcast_cmd_record := C_VVC_BROADCAST_CMD_DEFAULT;
signal VVC_BROADCAST : std_logic := 'L';
------------------------------------------------------------------------
-- Common signal for signalling between VVCs, used during await_any_completion()
-- Default (when not active): Z
-- Awaiting: 1:
-- Completed: 0
-- This signal is a vector to support multiple sequencers calling await_any_completion simultaneously:
-- - When calling await_any_completion, each sequencer specifies which bit in this global signal the VVCs shall use.
------------------------------------------------------------------------
signal global_awaiting_completion : std_logic_vector(C_MAX_NUM_SEQUENCERS-1 downto 0); -- ACK on global triggers
------------------------------------------------------------------------
-- Shared variables for UVVM framework
------------------------------------------------------------------------
shared variable shared_cmd_idx : integer := 0;
shared variable shared_uvvm_state : t_uvvm_state := IDLE;
-------------------------------------------
-- flag_handler
-------------------------------------------
-- Flag handler is a general flag/semaphore handling mechanism between two separate processes/threads
-- The idea is to allow one process to set a flag and another to reset it. The flag may then be used by both - or others
-- May be used for a message from process 1 to process 2 with acknowledge; - like do-something & done, or valid & ack
procedure flag_handler(
signal flag : inout t_flag_record
);
-------------------------------------------
-- set_flag
-------------------------------------------
-- Sets reset and is_active to 'Z' and pulses set_flag
procedure set_flag(
signal flag : inout t_flag_record
);
-------------------------------------------
-- reset_flag
-------------------------------------------
-- Sets set and is_active to 'Z' and pulses reset_flag
procedure reset_flag(
signal flag : inout t_flag_record
);
-------------------------------------------
-- await_uvvm_initialization
-------------------------------------------
-- Waits until uvvm has been initialized
procedure await_uvvm_initialization(
constant dummy : in t_void
);
-------------------------------------------
-- format_command_idx
-------------------------------------------
-- Converts the command index to string, enclused by
-- C_CMD_IDX_PREFIX and C_CMD_IDX_SUFFIX
impure function format_command_idx(
command_idx : integer
) return string;
--***********************************************
-- BROADCAST COMMANDS
--***********************************************
-------------------------------------------
-- enable_log_msg (Broadcast)
-------------------------------------------
-- Enables a log message for all VVCs
procedure enable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET
);
-------------------------------------------
-- disable_log_msg (Broadcast)
-------------------------------------------
-- Disables a log message for all VVCs
procedure disable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET
);
-------------------------------------------
-- flush_command_queue (Broadcast)
-------------------------------------------
-- Flushes the command queue for all VVCs
procedure flush_command_queue(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := ""
);
-------------------------------------------
-- insert_delay (Broadcast)
-------------------------------------------
-- Inserts delay into all VVCs (specified as number of clock cycles)
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in natural; -- in clock cycles
constant msg : in string := ""
);
-------------------------------------------
-- insert_delay (Broadcast)
-------------------------------------------
-- Inserts delay into all VVCs (specified as time)
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in time;
constant msg : in string := ""
);
-------------------------------------------
-- await_completion (Broadcast)
-------------------------------------------
-- Wait for all VVCs to finish (specified as time)
procedure await_completion(
signal VVC_BROADCAST : inout std_logic;
constant timeout : in time;
constant msg : in string := ""
);
-------------------------------------------
-- terminate_current_command (Broadcast)
-------------------------------------------
-- terminates all current tasks
procedure terminate_current_command(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := ""
);
-------------------------------------------
-- terminate_all_commands (Broadcast)
-------------------------------------------
-- terminates all tasks
procedure terminate_all_commands(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := ""
);
-------------------------------------------
-- transmit_broadcast
-------------------------------------------
-- Common broadcast transmission routine
procedure transmit_broadcast(
signal VVC_BROADCAST : inout std_logic;
constant operation : in t_broadcastable_cmd;
constant proc_call : in string;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant delay : in time := 0 ns;
constant delay_int : in integer := -1;
constant timeout : in time := std.env.resolution_limit
);
end package ti_vvc_framework_support_pkg;
package body ti_vvc_framework_support_pkg is
------------------------------------------------------------------------
--
------------------------------------------------------------------------
-- Flag handler is a general flag/semaphore handling mechanism between two separate processes/threads
-- The idea is to allow one process to set a flag and another to reset it. The flag may then be used by both - or others
-- May be used for a message from process 1 to process 2 with acknowledge; - like do-something & done, or valid & ack
procedure flag_handler(
signal flag : inout t_flag_record
) is
begin
flag.reset <= 'Z';
flag.set <= 'Z';
flag.is_active <= '0';
wait until flag.set = '1';
flag.is_active <= '1';
wait until flag.reset = '1';
flag.is_active <= '0';
end procedure;
procedure set_flag(
signal flag : inout t_flag_record
) is
begin
flag.reset <= 'Z';
flag.is_active <= 'Z';
gen_pulse(flag.set, 0 ns, "set flag");
end procedure;
procedure reset_flag(
signal flag : inout t_flag_record
) is
begin
flag.set <= 'Z';
flag.is_active <= 'Z';
gen_pulse(flag.reset, 0 ns, "reset flag", C_TB_SCOPE_DEFAULT, ID_NEVER);
end procedure;
-- This procedure checks the shared_uvvm_state on each delta cycle
procedure await_uvvm_initialization(
constant dummy : in t_void) is
begin
while (shared_uvvm_state /= INIT_COMPLETED) loop
wait for 0 ns;
end loop;
end procedure;
impure function format_command_idx(
command_idx : integer
) return string is
begin
return C_CMD_IDX_PREFIX & to_string(command_idx) & C_CMD_IDX_SUFFIX;
end;
procedure enable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET
) is
constant proc_name : string := "enable_log_msg";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_upper(to_string(msg_id)) & ")";
begin
transmit_broadcast(VVC_BROADCAST, ENABLE_LOG_MSG, proc_call, msg_id, msg, quietness);
end procedure;
procedure disable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET
) is
constant proc_name : string := "disable_log_msg";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_upper(to_string(msg_id)) & ")";
begin
transmit_broadcast(VVC_BROADCAST, DISABLE_LOG_MSG, proc_call, msg_id, msg, quietness);
end procedure;
procedure flush_command_queue(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := ""
) is
constant proc_name : string := "flush_command_queue";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
transmit_broadcast(VVC_BROADCAST, FLUSH_COMMAND_QUEUE, proc_call, NO_ID, msg);
end procedure;
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in natural; -- in clock cycles
constant msg : in string := ""
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_string(delay) & ")";
begin
transmit_broadcast(VVC_BROADCAST, FLUSH_COMMAND_QUEUE, proc_call, NO_ID, msg, NON_QUIET, 0 ns, delay);
end procedure;
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in time;
constant msg : in string := ""
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_string(delay) & ")";
begin
transmit_broadcast(VVC_BROADCAST, INSERT_DELAY, proc_call, NO_ID, msg, NON_QUIET, delay);
end procedure;
procedure await_completion(
signal VVC_BROADCAST : inout std_logic;
constant timeout : in time;
constant msg : in string := ""
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
transmit_broadcast(VVC_BROADCAST, AWAIT_COMPLETION, proc_call, NO_ID, msg, NON_QUIET, 0 ns, -1, timeout);
end procedure;
procedure terminate_current_command(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := ""
) is
constant proc_name : string := "terminate_current_command";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
transmit_broadcast(VVC_BROADCAST, TERMINATE_CURRENT_COMMAND, proc_call, NO_ID, msg);
end procedure;
procedure terminate_all_commands(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := ""
) is
constant proc_name : string := "terminate_all_commands";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
flush_command_queue(VVC_BROADCAST, msg);
terminate_current_command(VVC_BROADCAST, msg);
end procedure;
procedure transmit_broadcast(
signal VVC_BROADCAST : inout std_logic;
constant operation : in t_broadcastable_cmd;
constant proc_call : in string;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant delay : in time := 0 ns;
constant delay_int : in integer := -1;
constant timeout : in time := std.env.resolution_limit) is
begin
await_semaphore_in_delta_cycles(protected_semaphore);
shared_vvc_broadcast_cmd.operation := operation;
shared_vvc_broadcast_cmd.msg_id := msg_id;
shared_vvc_broadcast_cmd.msg := (others => NUL); -- default empty
shared_vvc_broadcast_cmd.msg(1 to msg'length) := msg;
shared_vvc_broadcast_cmd.quietness := quietness;
shared_vvc_broadcast_cmd.timeout := timeout;
shared_vvc_broadcast_cmd.delay := delay;
shared_vvc_broadcast_cmd.gen_integer := delay_int;
shared_vvc_broadcast_cmd.proc_call := (others => NUL); -- default empty
shared_vvc_broadcast_cmd.proc_call(1 to proc_call'length) := proc_call;
if VVC_BROADCAST /= 'L' then
-- a VVC is waiting for example in await_completion
wait until VVC_BROADCAST = 'L';
end if;
-- Trigger the broadcast
VVC_BROADCAST <= '1';
wait for 0 ns;
-- set back to 'L' and wait until all VVCs have set it back
VVC_BROADCAST <= 'L';
wait until VVC_BROADCAST = 'L' for timeout; -- Wait for executor
if not (VVC_BROADCAST'event) and VVC_BROADCAST /= 'L' then -- Indicates timeout
tb_error("Timeout while waiting for the broadcast command to be ACK'ed", C_SCOPE);
else
log(ID_UVVM_CMD_ACK, "ACK received for broadcast command", C_SCOPE);
end if;
shared_vvc_broadcast_cmd := C_VVC_BROADCAST_CMD_DEFAULT;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
release_semaphore(protected_semaphore);
end procedure;
end package body ti_vvc_framework_support_pkg;
| mit | 51f70b201234b1d4ba116febb85cc6f2 | 0.528284 | 4.567822 | false | false | false | false |
AndyMcC0/UVVM_All | bitvis_vip_gpio/src/gpio_vvc.vhd | 1 | 17,927 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.gpio_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--========================================================================================================================
entity gpio_vvc is
generic (
GC_DATA_WIDTH : natural range 1 to C_VVC_CMD_DATA_MAX_LENGTH;
GC_INSTANCE_IDX : natural;
GC_DEFAULT_LINE_VALUE : std_logic_vector(GC_DATA_WIDTH-1 downto 0);
GC_GPIO_BFM_CONFIG : t_gpio_bfm_config := C_GPIO_BFM_CONFIG_DEFAULT;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning
);
port (
gpio_vvc_if : inout std_logic_vector(GC_DATA_WIDTH-1 downto 0) := GC_DEFAULT_LINE_VALUE
);
end entity gpio_vvc;
--========================================================================================================================
--========================================================================================================================
architecture behave of gpio_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated Queue
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_gpio_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_gpio_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_gpio_transaction_info(GC_INSTANCE_IDX);
begin
--========================================================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--========================================================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_GPIO_BFM_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--========================================================================================================================
--========================================================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--========================================================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, shared_vvc_cmd, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack, v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
wait for 0 ns;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack, v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--========================================================================================================================
--========================================================================================================================
-- Command executor
-- - Fetch and execute the commands
--========================================================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean;
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Check if command is a BFM access
if v_cmd.operation = SET or v_cmd.operation = GET or v_cmd.operation = CHECK or v_cmd.operation = EXPECT then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_command_is_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
log(ID_BFM, "Running : " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd) & ".", C_SCOPE, vvc_config.msg_id_panel);
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is
when SET =>
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "gpio_set() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH-1 downto 0) := v_normalised_data;
gpio_set(data_value => v_normalised_data,
msg => format_msg(v_cmd),
data_port => gpio_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel);
when GET =>
gpio_get(data_value => v_read_data(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
data_port => gpio_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel);
work.td_vvc_entity_support_pkg.store_result(result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data);
when CHECK =>
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data_exp, v_normalised_data, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", "gpio_check() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH-1 downto 0) := v_normalised_data;
gpio_check(data_exp => v_normalised_data,
msg => format_msg(v_cmd),
data_port => gpio_vvc_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel);
when EXPECT =>
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data_exp, v_normalised_data, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", "gpio_expect() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH-1 downto 0) := v_normalised_data;
gpio_expect(data_exp => v_normalised_data,
timeout => v_cmd.timeout,
msg => format_msg(v_cmd),
data_port => gpio_vvc_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
config => vvc_config.bfm_config,
msg_id_panel => vvc_config.msg_id_panel);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, vvc_config.msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--========================================================================================================================
--========================================================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--========================================================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--========================================================================================================================
end behave;
| mit | 6f52be17c8eee78de3d202d35c6d583a | 0.51375 | 4.341729 | false | true | false | false |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/Checkers/Control_Part_Checkers/Allocator_checkers/Allocator_credit_counter_logic_checkers/allocator_credit_counter_logic_pseudo.vhd | 3 | 3,136 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : out std_logic_vector(1 downto 0)
);
end allocator_credit_counter_logic_pseudo;
architecture behavior of allocator_credit_counter_logic_pseudo is
begin
-- The combionational part
-- this process handels the credit counters!
process(credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L, grant_N, grant_E, grant_W, grant_S, grant_L,
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out)
begin
credit_counter_N_in <= credit_counter_N_out;
credit_counter_E_in <= credit_counter_E_out;
credit_counter_W_in <= credit_counter_W_out;
credit_counter_S_in <= credit_counter_S_out;
credit_counter_L_in <= credit_counter_L_out;
if credit_in_N = '1' and grant_N = '1' then
credit_counter_N_in <= credit_counter_N_out;
elsif credit_in_N = '1' and credit_counter_N_out < 3 then
credit_counter_N_in <= credit_counter_N_out + 1;
elsif grant_N = '1' and credit_counter_N_out > 0 then
credit_counter_N_in <= credit_counter_N_out - 1;
end if;
if credit_in_E = '1' and grant_E = '1' then
credit_counter_E_in <= credit_counter_E_out;
elsif credit_in_E = '1' and credit_counter_E_out < 3 then
credit_counter_E_in <= credit_counter_E_out + 1;
elsif grant_E = '1' and credit_counter_E_out > 0 then
credit_counter_E_in <= credit_counter_E_out - 1;
end if;
if credit_in_W = '1' and grant_W = '1' then
credit_counter_W_in <= credit_counter_W_out;
elsif credit_in_W = '1' and credit_counter_W_out < 3 then
credit_counter_W_in <= credit_counter_W_out + 1;
elsif grant_W = '1' and credit_counter_W_out > 0 then
credit_counter_W_in <= credit_counter_W_out - 1;
end if;
if credit_in_S = '1' and grant_S = '1' then
credit_counter_S_in <= credit_counter_S_out;
elsif credit_in_S = '1' and credit_counter_S_out < 3 then
credit_counter_S_in <= credit_counter_S_out + 1;
elsif grant_S = '1' and credit_counter_S_out > 0 then
credit_counter_S_in <= credit_counter_S_out - 1;
end if;
if credit_in_L = '1' and grant_L = '1' then
credit_counter_L_in <= credit_counter_L_out;
elsif credit_in_L = '1' and credit_counter_L_out < 3 then
credit_counter_L_in <= credit_counter_L_out + 1;
elsif grant_L = '1' and credit_counter_L_out > 0 then
credit_counter_L_in <= credit_counter_L_out - 1;
end if;
end process;
END;
| gpl-3.0 | ab5e691c800c7e836c628a0e0d1ab093 | 0.651786 | 2.84058 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/counter_threshold.vhd | 6 | 3,894 | --Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state, Reset_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Reset_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out,faulty_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' and faulty_counter_out /= std_logic_vector(to_unsigned(0, faulty_counter_out'length)) then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when Reset_state =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END; | gpl-3.0 | 0d50f778ca94b517307316c940fd4252 | 0.624551 | 3.646067 | false | false | false | false |
Wynjones1/gbvhdl | src/types.vhd | 1 | 27,269 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package types is
subtype byte_t is std_logic_vector( 7 downto 0);
subtype word_t is std_logic_vector(15 downto 0);
subtype op_t is std_logic_vector( 5 downto 0);
subtype alu_op_t is std_logic_vector( 4 downto 0);
subtype alu_mode_t is std_logic_vector( 1 downto 0);
subtype register_t is std_logic_vector( 3 downto 0);
subtype HI_BYTE is natural range 15 downto 8;
subtype LO_BYTE is natural range 7 downto 0;
-- register access
constant register_a : register_t := "0000";
constant register_f : register_t := "0001";
constant register_b : register_t := "0010";
constant register_c : register_t := "0011";
constant register_d : register_t := "0100";
constant register_e : register_t := "0101";
constant register_h : register_t := "0110";
constant register_l : register_t := "0111";
constant register_af : register_t := "1000";
constant register_bc : register_t := "1001";
constant register_de : register_t := "1010";
constant register_hl : register_t := "1011";
constant register_sp : register_t := "1100";
constant register_pc : register_t := "1101";
constant register_d8 : register_t := "1110"; -- not actually a register
constant register_d16 : register_t := "1111"; -- not actually a register
constant op_add : op_t := "000000";
constant op_and : op_t := "000001";
constant op_bit : op_t := "000010";
constant op_call : op_t := "000011";
constant op_ccf : op_t := "000100";
constant op_cp : op_t := "000101";
constant op_cpl : op_t := "000110";
constant op_daa : op_t := "000111";
constant op_dec : op_t := "001000";
constant op_di : op_t := "001001";
constant op_ei : op_t := "001010";
constant op_halt : op_t := "001011";
constant op_inc : op_t := "001100";
constant op_jp : op_t := "001101";
constant op_jr : op_t := "001110";
constant op_ld : op_t := "001111";
constant op_lhd : op_t := "010000";
constant op_nop : op_t := "010001";
constant op_or : op_t := "010010";
constant op_pop : op_t := "010011";
constant op_prefix : op_t := "010100";
constant op_push : op_t := "010101";
constant op_res : op_t := "010110";
constant op_ret : op_t := "010111";
constant op_reti : op_t := "011000";
constant op_rla : op_t := "011001";
constant op_rl : op_t := "011010";
constant op_rlca : op_t := "011011";
constant op_rlc : op_t := "011100";
constant op_rra : op_t := "011101";
constant op_rr : op_t := "011110";
constant op_rrca : op_t := "011111";
constant op_rrc : op_t := "100000";
constant op_rst : op_t := "100001";
constant op_sbc : op_t := "100010";
constant op_scf : op_t := "100011";
constant op_set : op_t := "100100";
constant op_sla : op_t := "100101";
constant op_sra : op_t := "100110";
constant op_srl : op_t := "100111";
constant op_stop : op_t := "101000";
constant op_sub : op_t := "101001";
constant op_swap : op_t := "101010";
constant op_xor : op_t := "101011";
constant alu_op_adc : alu_op_t := "00000";
constant alu_op_add : alu_op_t := "00001";
constant alu_op_and : alu_op_t := "00010";
constant alu_op_bit : alu_op_t := "00011";
constant alu_op_cp : alu_op_t := "00100";
constant alu_op_cpl : alu_op_t := "00101";
constant alu_op_daa : alu_op_t := "00110";
constant alu_op_or : alu_op_t := "00111";
constant alu_op_rl : alu_op_t := "01000";
constant alu_op_rr : alu_op_t := "01001";
constant alu_op_rrc : alu_op_t := "01010";
constant alu_op_sla : alu_op_t := "01011";
constant alu_op_rlc : alu_op_t := "01100";
constant alu_op_sra : alu_op_t := "01101";
constant alu_op_srl : alu_op_t := "01110";
constant alu_op_sub : alu_op_t := "01111";
constant alu_op_sbc : alu_op_t := "10000";
constant alu_op_swap : alu_op_t := "10001";
constant alu_op_set : alu_op_t := "10010";
constant alu_op_reset : alu_op_t := "10011";
constant alu_op_xor : alu_op_t := "10100";
constant alu_op_inc : alu_op_t := "10101"; -- Dummy op
constant alu_op_dec : alu_op_t := "10110"; -- Dummy op
constant alu_op_cb : alu_op_t := "10111"; -- Dummp op
constant alu_op_invalid : alu_op_t := "11111";
constant alu_mode_register : alu_mode_t := "00";
constant alu_mode_immediate : alu_mode_t := "01";
constant alu_mode_indirect : alu_mode_t := "10";
constant alu_mode_cb : alu_mode_t := "11";
constant CARRY_BIT : integer := 4;
constant HALF_CARRY_BIT : integer := 5;
constant SUBTRACT_BIT : integer := 6;
constant ZERO_BIT : integer := 7;
function alu_op_to_string( in_op : alu_op_t ) return string;
function op_to_string( in_op : op_t ) return string;
function instruction_to_string(instruction : byte_t) return string;
function to_std_logic_vector(s: string) return std_logic_vector;
end;
package body types is
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
if s(i) = '1' then
slv(k) := '1';
else
slv(k) := '0';
end if;
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
function alu_op_to_string( in_op : alu_op_t ) return string is
begin
case in_op is
when alu_op_adc => return "alu_op_adc";
when alu_op_add => return "alu_op_add";
when alu_op_and => return "alu_op_and";
when alu_op_bit => return "alu_op_bit";
when alu_op_cp => return "alu_op_cp";
when alu_op_cpl => return "alu_op_cpl";
when alu_op_daa => return "alu_op_daa";
when alu_op_or => return "alu_op_or";
when alu_op_rl => return "alu_op_rl";
when alu_op_rr => return "alu_op_rr";
when alu_op_rrc => return "alu_op_rrc";
when alu_op_sla => return "alu_op_sla";
when alu_op_rlc => return "alu_op_rlc";
when alu_op_sra => return "alu_op_sra";
when alu_op_srl => return "alu_op_srl";
when alu_op_sub => return "alu_op_sub";
when alu_op_sbc => return "alu_op_sbc";
when alu_op_swap => return "alu_op_swap";
when alu_op_set => return "alu_op_set";
when alu_op_reset => return "alu_op_reset";
when alu_op_xor => return "alu_op_xor";
when others => return "INVALID";
end case;
end alu_op_to_string;
function op_to_string( in_op : op_t ) return string is
begin
case in_op is
when op_add => return "op_add";
when op_and => return "op_and";
when op_bit => return "op_bit";
when op_call => return "op_call";
when op_ccf => return "op_ccf";
when op_cp => return "op_cp";
when op_cpl => return "op_cpl";
when op_daa => return "op_daa";
when op_dec => return "op_dec";
when op_di => return "op_di";
when op_ei => return "op_ei";
when op_halt => return "op_halt";
when op_inc => return "op_inc";
when op_jp => return "op_jp";
when op_jr => return "op_jr";
when op_ld => return "op_ld";
when op_lhd => return "op_lhd";
when op_nop => return "op_nop";
when op_or => return "op_or";
when op_pop => return "op_pop";
when op_prefix => return "op_prefix";
when op_push => return "op_push";
when op_res => return "op_res";
when op_ret => return "op_ret";
when op_reti => return "op_reti";
when op_rla => return "op_rla";
when op_rl => return "op_rl";
when op_rlca => return "op_rlca";
when op_rlc => return "op_rlc";
when op_rra => return "op_rra";
when op_rr => return "op_rr";
when op_rrca => return "op_rrca";
when op_rrc => return "op_rrc";
when op_rst => return "op_rst";
when op_sbc => return "op_sbc";
when op_scf => return "op_scf";
when op_set => return "op_set";
when op_sla => return "op_sla";
when op_sra => return "op_sra";
when op_srl => return "op_srl";
when op_stop => return "op_stop";
when op_sub => return "op_sub";
when op_swap => return "op_swap";
when op_xor => return "op_xor";
when others => return "INVALID";
end case;
end op_to_string;
function instruction_to_string(instruction : byte_t) return string is
begin
if instruction = x"00" then return "NOP ";
elsif instruction = x"01" then return "LD BC d16 ";
elsif instruction = x"02" then return "LD (BC) A ";
elsif instruction = x"03" then return "INC BC ";
elsif instruction = x"04" then return "INC B ";
elsif instruction = x"05" then return "DEC B ";
elsif instruction = x"06" then return "LD B n ";
elsif instruction = x"07" then return "RLCA ";
elsif instruction = x"08" then return "LD (d16) SP ";
elsif instruction = x"09" then return "ADD BC ss ";
elsif instruction = x"0a" then return "LD A (BC) ";
elsif instruction = x"0b" then return "DEC BC ";
elsif instruction = x"0c" then return "INC C ";
elsif instruction = x"0d" then return "DEC C ";
elsif instruction = x"0e" then return "LD C n ";
elsif instruction = x"0f" then return "RRCA ";
elsif instruction = x"10" then return "STOP ";
elsif instruction = x"11" then return "LD DE d16 ";
elsif instruction = x"12" then return "LD (DE) A ";
elsif instruction = x"13" then return "INC DE ";
elsif instruction = x"14" then return "INC D ";
elsif instruction = x"15" then return "DEC D ";
elsif instruction = x"16" then return "LD D n ";
elsif instruction = x"17" then return "RLA ";
elsif instruction = x"18" then return "JR r8 ";
elsif instruction = x"19" then return "ADD DE ss ";
elsif instruction = x"1a" then return "LD A (DE) ";
elsif instruction = x"1b" then return "DEC DE ";
elsif instruction = x"1c" then return "INC E ";
elsif instruction = x"1d" then return "DEC E ";
elsif instruction = x"1e" then return "LD E n ";
elsif instruction = x"1f" then return "RRA ";
elsif instruction = x"20" then return "JR NZ r8 ";
elsif instruction = x"21" then return "LD HL d16 ";
elsif instruction = x"22" then return "LD (HL++) A ";
elsif instruction = x"23" then return "INC HL ";
elsif instruction = x"24" then return "INC H ";
elsif instruction = x"25" then return "DEC H ";
elsif instruction = x"26" then return "LD H n ";
elsif instruction = x"27" then return "DDA ";
elsif instruction = x"28" then return "JR Z r8 ";
elsif instruction = x"29" then return "ADD HL ss ";
elsif instruction = x"2a" then return "LD A (HL++) ";
elsif instruction = x"2b" then return "DEC HL ";
elsif instruction = x"2c" then return "INC L ";
elsif instruction = x"2d" then return "DEC L ";
elsif instruction = x"2e" then return "LD L n ";
elsif instruction = x"2f" then return "CPL ";
elsif instruction = x"30" then return "JR NC r8 ";
elsif instruction = x"31" then return "LD SP d16 ";
elsif instruction = x"32" then return "LD (HL--) A ";
elsif instruction = x"33" then return "INC SP ";
elsif instruction = x"34" then return "INC (HL) ";
elsif instruction = x"35" then return "DEC (HL) ";
elsif instruction = x"36" then return "LD (HL) d8 ";
elsif instruction = x"37" then return "SCF ";
elsif instruction = x"38" then return "JR C r8 ";
elsif instruction = x"39" then return "ADD SP ss ";
elsif instruction = x"3a" then return "LD A (HL--) ";
elsif instruction = x"3b" then return "DEC SP ";
elsif instruction = x"3c" then return "INC A ";
elsif instruction = x"3d" then return "DEC A ";
elsif instruction = x"3e" then return "LD A n ";
elsif instruction = x"3f" then return "CCF ";
elsif instruction = x"40" then return "LD B B ";
elsif instruction = x"41" then return "LD B C ";
elsif instruction = x"42" then return "LD B D ";
elsif instruction = x"43" then return "LD B E ";
elsif instruction = x"44" then return "LD B H ";
elsif instruction = x"45" then return "LD B L ";
elsif instruction = x"46" then return "LD B (HL) ";
elsif instruction = x"47" then return "LD B A ";
elsif instruction = x"48" then return "LD C B ";
elsif instruction = x"49" then return "LD C C ";
elsif instruction = x"4a" then return "LD C D ";
elsif instruction = x"4b" then return "LD C E ";
elsif instruction = x"4c" then return "LD C H ";
elsif instruction = x"4d" then return "LD C L ";
elsif instruction = x"4e" then return "LD C (HL) ";
elsif instruction = x"4f" then return "LD C A ";
elsif instruction = x"50" then return "LD D B ";
elsif instruction = x"51" then return "LD D C ";
elsif instruction = x"52" then return "LD D D ";
elsif instruction = x"53" then return "LD D E ";
elsif instruction = x"54" then return "LD D H ";
elsif instruction = x"55" then return "LD D L ";
elsif instruction = x"56" then return "LD D (HL) ";
elsif instruction = x"57" then return "LD D A ";
elsif instruction = x"58" then return "LD E B ";
elsif instruction = x"59" then return "LD E C ";
elsif instruction = x"5a" then return "LD E D ";
elsif instruction = x"5b" then return "LD E E ";
elsif instruction = x"5c" then return "LD E H ";
elsif instruction = x"5d" then return "LD E L ";
elsif instruction = x"5e" then return "LD E (HL) ";
elsif instruction = x"5f" then return "LD E A ";
elsif instruction = x"60" then return "LD H B ";
elsif instruction = x"61" then return "LD H C ";
elsif instruction = x"62" then return "LD H D ";
elsif instruction = x"63" then return "LD H E ";
elsif instruction = x"64" then return "LD H H ";
elsif instruction = x"65" then return "LD H L ";
elsif instruction = x"66" then return "LD H (HL) ";
elsif instruction = x"67" then return "LD H A ";
elsif instruction = x"68" then return "LD L B ";
elsif instruction = x"69" then return "LD L C ";
elsif instruction = x"6a" then return "LD L D ";
elsif instruction = x"6b" then return "LD L E ";
elsif instruction = x"6c" then return "LD L H ";
elsif instruction = x"6d" then return "LD L L ";
elsif instruction = x"6e" then return "LD L (HL) ";
elsif instruction = x"6f" then return "LD L A ";
elsif instruction = x"70" then return "LD (HL) B ";
elsif instruction = x"71" then return "LD (HL) C ";
elsif instruction = x"72" then return "LD (HL) D ";
elsif instruction = x"73" then return "LD (HL) E ";
elsif instruction = x"74" then return "LD (HL) H ";
elsif instruction = x"75" then return "LD (HL) L ";
elsif instruction = x"76" then return "HALT ";
elsif instruction = x"77" then return "LD (HL) A ";
elsif instruction = x"78" then return "LD A B ";
elsif instruction = x"79" then return "LD A C ";
elsif instruction = x"7a" then return "LD A D ";
elsif instruction = x"7b" then return "LD A E ";
elsif instruction = x"7c" then return "LD A H ";
elsif instruction = x"7d" then return "LD A L ";
elsif instruction = x"7e" then return "LD A (HL) ";
elsif instruction = x"7f" then return "LD A A ";
elsif instruction = x"80" then return "ADD A B ";
elsif instruction = x"81" then return "ADD A C ";
elsif instruction = x"82" then return "ADD A D ";
elsif instruction = x"83" then return "ADD A E ";
elsif instruction = x"84" then return "ADD A H ";
elsif instruction = x"85" then return "ADD A L ";
elsif instruction = x"86" then return "ADD A (HL) ";
elsif instruction = x"87" then return "ADD A A ";
elsif instruction = x"88" then return "ADC A B ";
elsif instruction = x"89" then return "ADC A C ";
elsif instruction = x"8a" then return "ADC A D ";
elsif instruction = x"8b" then return "ADC A E ";
elsif instruction = x"8c" then return "ADC A H ";
elsif instruction = x"8d" then return "ADC A L ";
elsif instruction = x"8e" then return "ADC A (HL) ";
elsif instruction = x"8f" then return "ADC A A ";
elsif instruction = x"90" then return "SUB A B ";
elsif instruction = x"91" then return "SUB A C ";
elsif instruction = x"92" then return "SUB A D ";
elsif instruction = x"93" then return "SUB A E ";
elsif instruction = x"94" then return "SUB A H ";
elsif instruction = x"95" then return "SUB A L ";
elsif instruction = x"96" then return "SUB A (HL) ";
elsif instruction = x"97" then return "SUB A A ";
elsif instruction = x"98" then return "SBC A B ";
elsif instruction = x"99" then return "SBC A C ";
elsif instruction = x"9a" then return "SBC A D ";
elsif instruction = x"9b" then return "SBC A E ";
elsif instruction = x"9c" then return "SBC A H ";
elsif instruction = x"9d" then return "SBC A L ";
elsif instruction = x"9e" then return "SBC A (HL) ";
elsif instruction = x"9f" then return "SBC A A ";
elsif instruction = x"a0" then return "AND A B ";
elsif instruction = x"a1" then return "AND A C ";
elsif instruction = x"a2" then return "AND A D ";
elsif instruction = x"a3" then return "AND A E ";
elsif instruction = x"a4" then return "AND A H ";
elsif instruction = x"a5" then return "AND A L ";
elsif instruction = x"a6" then return "AND A (HL) ";
elsif instruction = x"a7" then return "AND A A ";
elsif instruction = x"a8" then return "XOR A B ";
elsif instruction = x"a9" then return "XOR A C ";
elsif instruction = x"aa" then return "XOR A D ";
elsif instruction = x"ab" then return "XOR A E ";
elsif instruction = x"ac" then return "XOR A H ";
elsif instruction = x"ad" then return "XOR A L ";
elsif instruction = x"ae" then return "XOR A (HL) ";
elsif instruction = x"af" then return "XOR A A ";
elsif instruction = x"b0" then return "OR A B ";
elsif instruction = x"b1" then return "OR A C ";
elsif instruction = x"b2" then return "OR A D ";
elsif instruction = x"b3" then return "OR A E ";
elsif instruction = x"b4" then return "OR A H ";
elsif instruction = x"b5" then return "OR A L ";
elsif instruction = x"b6" then return "OR A (HL) ";
elsif instruction = x"b7" then return "OR A A ";
elsif instruction = x"b8" then return "CP A B ";
elsif instruction = x"b9" then return "CP A C ";
elsif instruction = x"ba" then return "CP A D ";
elsif instruction = x"bb" then return "CP A E ";
elsif instruction = x"bc" then return "CP A H ";
elsif instruction = x"bd" then return "CP A L ";
elsif instruction = x"be" then return "CP A (HL) ";
elsif instruction = x"bf" then return "CP A A ";
elsif instruction = x"c0" then return "RET NZ ";
elsif instruction = x"c1" then return "POP BC ";
elsif instruction = x"c2" then return "JP NZ d16 ";
elsif instruction = x"c3" then return "JP d16 ";
elsif instruction = x"c4" then return "CALL NZ d16 ";
elsif instruction = x"c5" then return "PUSH BC ";
elsif instruction = x"c6" then return "ADD A n ";
elsif instruction = x"c7" then return "RST 00H ";
elsif instruction = x"c8" then return "RET Z ";
elsif instruction = x"c9" then return "RET ";
elsif instruction = x"ca" then return "JP Z d16 ";
elsif instruction = x"cb" then return "CB ";
elsif instruction = x"cc" then return "CALL Z d16 ";
elsif instruction = x"cd" then return "CALL d16 ";
elsif instruction = x"ce" then return "ADC A n ";
elsif instruction = x"cf" then return "RST 08H ";
elsif instruction = x"d0" then return "RET NC ";
elsif instruction = x"d1" then return "POP DE ";
elsif instruction = x"d2" then return "JP NC d16 ";
elsif instruction = x"d3" then return "INVALID ";
elsif instruction = x"d4" then return "CALL NC d16 ";
elsif instruction = x"d5" then return "PUSH DE ";
elsif instruction = x"d6" then return "SUB A n ";
elsif instruction = x"d7" then return "RST 10H ";
elsif instruction = x"d8" then return "RET C ";
elsif instruction = x"d9" then return "RETI ";
elsif instruction = x"da" then return "JP C d16 ";
elsif instruction = x"db" then return "INVALID ";
elsif instruction = x"dc" then return "CALL C d16 ";
elsif instruction = x"dd" then return "INVALID ";
elsif instruction = x"de" then return "SBC A n ";
elsif instruction = x"df" then return "RST 18H ";
elsif instruction = x"e0" then return "LDH (d8) A ";
elsif instruction = x"e1" then return "POP HL ";
elsif instruction = x"e2" then return "LD (C) A ";
elsif instruction = x"e3" then return "INVALID ";
elsif instruction = x"e4" then return "INVALID ";
elsif instruction = x"e5" then return "PUSH HL ";
elsif instruction = x"e6" then return "AND A n ";
elsif instruction = x"e7" then return "RST 20H ";
elsif instruction = x"e8" then return "ADD SP r8 ";
elsif instruction = x"e9" then return "JP PC (HL) ";
elsif instruction = x"ea" then return "LD (d16) A ";
elsif instruction = x"eb" then return "INVALID ";
elsif instruction = x"ec" then return "INVALID ";
elsif instruction = x"ed" then return "INVALID ";
elsif instruction = x"ee" then return "XOR A n ";
elsif instruction = x"ef" then return "RST 28H ";
elsif instruction = x"f0" then return "LDH A (d8) ";
elsif instruction = x"f1" then return "POP AF ";
elsif instruction = x"f2" then return "LD A (C) ";
elsif instruction = x"f3" then return "DI ";
elsif instruction = x"f4" then return "INVALID ";
elsif instruction = x"f5" then return "PUSH AF ";
elsif instruction = x"f6" then return "OR A n ";
elsif instruction = x"f7" then return "RST 30H ";
elsif instruction = x"f8" then return "LD HL SP + r8 ";
elsif instruction = x"f9" then return "LD SP HL ";
elsif instruction = x"fa" then return "LD A (d16) ";
elsif instruction = x"fb" then return "EI ";
elsif instruction = x"fc" then return "INVALID ";
elsif instruction = x"fd" then return "INVALID ";
elsif instruction = x"fe" then return "CP A n ";
elsif instruction = x"ff" then return "RST 48H ";
else return "INVALID ";
end if;
end function;
end types;
| mit | b5bf93fe2bc4281e07d1987431ed4ac0 | 0.499578 | 3.827228 | false | false | false | false |
SKravitsky/ECEC412 | CPU.vhd | 1 | 4,481 | library ieee;
use ieee.std_logic_1164.all;
entity CPU is
port(
clk: in std_logic;
Overflow: out std_logic
);
end CPU;
architecture Behavioral of CPU is
component PC
port(
clk: in std_logic;
AddressIn: in std_logic_vector(31 downto 0);
AddressOut: out std_logic_vector(31 downto 0)
);
end component;
component Add
port(
x: in std_logic_vector(31 downto 0);
y: in std_logic_vector(31 downto 0);
z: out std_logic_vector(31 downto 0)
);
end component;
component SignExtend
port(
x: in std_logic_vector(15 downto 0);
y: out std_logic_vector(31 downto 0)
);
end component;
component ShiftLeft2
port(
x: in std_logic_vector(31 downto 0);
y: out std_logic_vector(31 downto 0)
);
end component;
component ShiftLeft2Jump
port(
x: in std_logic_vector(25 downto 0);
y: in std_logic_vector(3 downto 0);
z: out std_logic_vector(31 downto 0)
);
end component;
component Mux5
port(
x, y: in std_logic_vector (4 downto 0);
sel: in std_logic;
z :out std_logic_vector(4 downto 0)
);
end component;
component Mux32
port(
x, y: in std_logic_vector (31 downto 0);
sel: in std_logic;
z: out std_logic_vector(31 downto 0)
);
end component;
component And2
port(
a, b: in std_logic;
y: out std_logic
);
end component;
component ALU
generic(
n: natural := 32
);
port(
a, b: in std_logic_vector(n-1 downto 0);
Oper: in std_logic_vector(3 downto 0);
Result: buffer std_logic_vector(n-1 downto 0);
Zero, CarryOut, Overflow: buffer std_logic
);
end component;
component Registers
port(
RR1, RR2, WR: in std_logic_vector(4 downto 0);
WD: in std_logic_vector(31 downto 0);
RegWrite, Clk: in std_logic;
RD1, RD2: out std_logic_vector(31 downto 0)
);
end component;
component InstructionMemory
port (
Address: in std_logic_vector(31 downto 0);
ReadData: out std_logic_vector(31 downto 0)
);
end component;
component DataMemory
port(
WriteData: in std_logic_vector(31 downto 0);
Address: in std_logic_vector(31 downto 0);
Clk, MemRead, MemWrite: in std_logic;
ReadData: out std_logic_vector(31 downto 0)
);
end component;
component ALUControl
port(
ALUOp: in std_logic_vector(1 downto 0);
Funct: in std_logic_vector(5 downto 0);
Operation: out std_logic_vector(3 downto 0)
);
end component;
component Control
port(
Opcode: in std_logic_vector(5 downto 0);
RegDst, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Jump: out std_logic;
ALUOp: out std_logic_vector(1 downto 0)
);
end component;
signal RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, R, Zero, CarryOut: std_logic := '0';
signal AlUOp: std_logic_vector(1 downto 0) := "00";
signal Operation: std_logic_vector(3 downto 0) := "0000";
signal B: std_logic_vector(4 downto 0) := "00000";
signal A, C, D, E, F, G, H, J, L, K, M, N, P, Q, Instruction: std_logic_vector(31 downto 0) := X"00000000";
begin
PC_instance: PC port map(clk, P, A);
Add_instance_0: Add port map(A, X"00000004", L);
Add_instance_1: Add port map(L, K, M);
SignExtend_instance: SignExtend port map(Instruction(15 downto 0), E);
ShiftLeft2_instance: ShiftLeft2 port map(E, K);
ShiftLeft2Jump_instance: ShiftLeft2Jump port map(Instruction(25 downto 0), L(31 downto 28), Q);
Mux5_instance: Mux5 port map(Instruction(20 downto 16), Instruction(15 downto 11), RegDst, B);
Mux32_instance_0: Mux32 port map(L, M, R, N);
Mux32_instance_1: Mux32 port map(N, Q, Jump, P);
Mux32_instance_2: Mux32 port map(D, E, ALUSrc, F);
Mux32_instance_3: Mux32 port map(G, H, MemToReg, J);
And2_instance: And2 port map(Branch, Zero, R);
ALU_instance: ALU port map(C, F, Operation, G, Zero, CarryOut, Overflow);
Registers_instance: Registers port map(Instruction(25 downto 21), Instruction(20 downto 16), B, J, RegWrite, clk, C, D);
InstructionMemory_instance: InstructionMemory port map(A, Instruction);
DataMemory_instance: DataMemory port map(D, G, clk, MemRead, MemWrite, H);
ALUControl_instance: ALUControl port map(ALUOp, Instruction(5 downto 0), Operation);
Control_instance: Control port map(Instruction(31 downto 26), RegDst, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Jump, ALUOp);
end Behavioral;
| apache-2.0 | c5c697b354a09f1e844a6473c0104e1a | 0.655434 | 3.341536 | false | false | false | false |
SKravitsky/ECEC412 | PipelineCPU.vhd | 1 | 8,042 | library ieee;
use ieee.std_logic_1164.all;
entity PipelineCPU is
port(
clk: in std_logic;
Overflow: out std_logic
);
end PipelineCPU;
architecture Behavioral of PipelineCPU is
component PC
port(
clk: in std_logic;
AddressIn: in std_logic_vector(31 downto 0);
AddressOut: out std_logic_vector(31 downto 0)
);
end component;
component Add
port(
x: in std_logic_vector(31 downto 0);
y: in std_logic_vector(31 downto 0);
z: out std_logic_vector(31 downto 0)
);
end component;
component InstructionMemoryPipeline
port (
Address: in std_logic_vector(31 downto 0);
ReadData: out std_logic_vector(31 downto 0)
);
end component;
component Mux32
port(
x, y: in std_logic_vector (31 downto 0);
sel: in std_logic;
z: out std_logic_vector(31 downto 0)
);
end component;
component IFIDRegister is
port(
clk: in std_logic;
AddressIn, InstructionIn: in std_logic_vector(31 downto 0);
AddressOut, InstructionOut: out std_logic_vector(31 downto 0)
);
end component;
component RegistersPipeline is
port(
RR1, RR2, WR: in std_logic_vector(4 downto 0);
WD: in std_logic_vector(31 downto 0);
RegWrite: in std_logic;
RD1, RD2: out std_logic_vector(31 downto 0)
);
end component;
component PipelineControl is
port(
Opcode: in std_logic_vector(5 downto 0);
ALUSrc, Branch, MemRead, MemWrite, MemtoReg, RegDst, RegWrite: out std_logic;
ALUOp: out std_logic_vector(1 downto 0)
);
end component;
component IDEXRegister is
port(
clk, ALUSrcIn, BranchIn, MemWriteIn, MemReadIn, MemtoRegIn, RegDstIn, RegWriteIn: in std_logic;
ALUOpIn: std_logic_vector(1 downto 0);
AddressIn, InstructionIn, ReadDataOneIn, ReadDataTwoIn: std_logic_vector(31 downto 0);
ALUSrcOut, BranchOut, MemWriteOut, MemReadOut, MemtoRegOut, RegDstOut, RegWriteOut: out std_logic;
ALUOpOut: out std_logic_vector(1 downto 0);
AddressOut, InstructionOut, ReadDataOneOut, ReadDataTwoOut: out std_logic_vector(31 downto 0)
);
end component;
component ALU is
generic(
n: natural := 32
);
port(
a, b: in std_logic_vector(n-1 downto 0);
Oper: in std_logic_vector(3 downto 0);
Result: buffer std_logic_vector(n-1 downto 0);
Zero, CarryOut, Overflow: buffer std_logic
);
end component;
component ALUControl is
port(
ALUOp : in std_logic_vector(1 downto 0);
Funct : in std_logic_vector(5 downto 0);
Operation : out std_logic_vector(3 downto 0)
);
end component;
component Mux5 is
port(
x, y: in std_logic_vector (4 downto 0);
sel: in std_logic;
z: out std_logic_vector(4 downto 0)
);
end component;
component EXMEMRegister is
port(
clk, BranchIn, MemWriteIn, MemReadIn, MemtoRegIn, RegWriteIn, ZeroIn: in std_logic;
WriteRegisterIn: in std_logic_vector(4 downto 0);
AddressIn, ALUResultIn, WriteDataIn: in std_logic_vector(31 downto 0);
BranchOut, MemWriteOut, MemReadOut, MemtoRegOut, RegWriteOut, ZeroOut: out std_logic;
WriteRegisterOut: out std_logic_vector(4 downto 0);
AddressOut, ALUResultOut, WriteDataOut: out std_logic_vector(31 downto 0)
);
end component;
component DataMemoryPipeline is
port(
WriteData: in std_logic_vector(31 downto 0);
Address: in std_logic_vector(31 downto 0);
MemRead, MemWrite: in std_logic;
ReadData: out std_logic_vector(31 downto 0)
);
end component;
component MEMWBRegister is
port(
clk, MemtoRegIn, RegWriteIn: in std_logic;
WriteRegisterIn: in std_logic_vector(4 downto 0);
ReadDataIn, ALUResultIn: in std_logic_vector(31 downto 0);
MemtoRegOut, RegWriteOut: out std_logic;
WriteRegisterOut: out std_logic_vector(4 downto 0);
ReadDataOut, ALUResultOut: out std_logic_vector(31 downto 0)
);
end component;
component ShiftLeft2 is
port(
x: in std_logic_vector(31 downto 0);
y: out std_logic_vector(31 downto 0)
);
end component;
-- Signals
-- IF
signal AddressIF, InstructionIF, PCIn, PCOut: std_logic_vector(31 downto 0) := X"00000000";
-- ID
signal ALUSrcID, BranchID, MemReadID, MemWriteID, MemtoRegID, RegDstID, RegWriteID: std_logic := '0';
signal ALUOpID: std_logic_vector(1 downto 0) := "00";
signal AddressID, InstructionID, ReadDataOneID, ReadDataTwoID: std_logic_vector(31 downto 0) := X"00000000";
-- EX
signal ALUSrcEX, BranchEX, MemReadEX, MemWriteEX, MemtoRegEX, RegDstEX, RegWriteEX, ZeroEX: std_logic := '0';
signal ALUOpEX: std_logic_vector(1 downto 0) := "00";
signal Operation: std_logic_vector(3 downto 0) := "0000";
signal WriteRegisterEX: std_logic_vector(4 downto 0) := "00000";
signal AddressEX, ALUOperand, ALUResultEX, InstructionEX, MaskedInstruction, ReadDataOneEX, ReadDataTwoEX: std_logic_vector(31 downto 0) := X"00000000";
-- MEM
signal PCSrc, BranchMEM, MemWriteMEM, MemReadMEM, MemtoRegMEM, RegWriteMEM, ZeroMEM: std_logic := '0';
signal WriteRegisterMEM: std_logic_vector(4 downto 0) := "00000";
signal AddressMEM, ALUResultMEM, BranchInstruction, ReadDataMEM, ShiftedInstruction, WriteDataMEM: std_logic_vector(31 downto 0) := X"00000000";
-- WB
signal MemtoRegWB, RegWriteWB: std_logic := '0';
signal WriteRegisterWB: std_logic_vector(4 downto 0) := "00000";
signal ALUResultWB, ReadDataWB, WriteRegisterData: std_logic_vector(31 downto 0) := X"00000000";
begin
-- Components
-- IF
Mux32_instance_0: Mux32 port map(AddressIF, AddressMEM, PCSrc, PCIn);
PC_instance: PC port map(clk, PCIn, PCOut);
Add_instance_0: Add port map(PCOut, X"00000004", AddressIF);
InstructionMemory_instance: InstructionMemoryPipeline port map(PCOut, InstructionIF);
IFIDRegister_instance: IFIDRegister port map(clk, AddressIF, InstructionIF, AddressID, InstructionID);
-- ID
Registers_instance: RegistersPipeline port map(InstructionID(25 downto 21), InstructionID(20 downto 16), WriteRegisterWB, WriteRegisterData, RegWriteWB, ReadDataOneID, ReadDataTwoID);
PipelineControl_instance: PipelineControl port map(InstructionID(31 downto 26), ALUSrcID, BranchID, MemReadID, MemWriteID, MemtoRegID, RegDstID, RegWriteID, ALUOpID);
IDEXRegister_instance: IDEXRegister port map(clk, ALUSrcID, BranchID, MemWriteID, MemReadID, MemtoRegID, RegDstID, RegWriteID, ALUOpID, AddressID, InstructionID, ReadDataOneID, ReadDataTwoID, ALUSrcEX, BranchEX, MemWriteEX, MemReadEX, MemtoRegEX, RegDstEX, RegWriteEX, ALUOpEX, AddressEX, InstructionEX, ReadDataOneEX, ReadDataTwoEX);
-- EX
ALUControl_instance: ALUControl port map(ALUOpEX, InstructionEX(5 downto 0), Operation);
MaskedInstruction <= InstructionEX and X"0000FFFF";
ShiftLeft2_instance: ShiftLeft2 port map(MaskedInstruction, ShiftedInstruction);
Add_instance_1: Add port map(AddressEX, ShiftedInstruction, BranchInstruction);
Mux32_instance_1: Mux32 port map(ReadDataTwoEX, MaskedInstruction, ALUSrcEX, ALUOperand);
ALU_instance: ALU port map(ReadDataOneEX, ALUOperand, Operation, ALUResultEX, ZeroEX);
Mux5_instance: Mux5 port map(InstructionEX(20 downto 16), InstructionEX(15 downto 11), RegDstEX, WriteRegisterEX);
EXMEMRegister_instance: EXMEMRegister port map(clk, BranchEX, MemWriteEX, MemReadEX, MemtoRegEX, RegWriteEX, ZeroEX, WriteRegisterEX, BranchInstruction, ALUResultEX, ReadDataTwoEX, BranchMEM, MemWriteMEM, MemReadMEM, MemtoRegMEM, RegWriteMEM, ZeroMEM, WriteRegisterMEM, AddressMEM, ALUResultMEM, WriteDataMEM);
-- MEM
PCSrc <= BranchMEM and ZeroMEM;
DataMemory_instance: DataMemoryPipeline port map(WriteDataMEM, ALUResultMEM, MemReadMEM, MemWriteMEM, ReadDataMEM);
MEMWBRegister_instance: MEMWBRegister port map(clk, MemtoRegMEM, RegWriteMEM, WriteRegisterMEM, ReadDataMEM, ALUResultMEM, MemToRegWB, RegWriteWB, WriteRegisterWB, ReadDataWB, ALUResultWB);
-- WB
Mux32_instance_2: Mux32 port map(ALUResultWB, ReadDataWB, MemtoRegWB, WriteRegisterData);
end Behavioral;
| apache-2.0 | 10afe6f66feee4d906fc1730d5be0195 | 0.7191 | 3.752683 | false | false | false | false |
simoesusp/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE70/CU.vhd | 3 | 1,847 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY CU IS
PORT(
RST : IN STD_LOGIC;
CLK : IN STD_LOGIC;
HALT_REQ : IN STD_LOGIC;
INMEM : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
FRIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
sM1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
sM2 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
sM3 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
sM4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
sM5 : OUT STD_LOGIC;
sM6 : OUT STD_LOGIC;
ULAOP : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
LoadFR : OUT STD_LOGIC;
LoadMAR : OUT STD_LOGIC;
LIDPC : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
LIDSP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
LoadMBR : OUT STD_LOGIC;
LoadREG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
HALT_ACK : OUT STD_LOGIC;
DRAW : OUT STD_LOGIC;
RW : OUT STD_LOGIC
);
END CU;
ARCHITECTURE main OF CU IS
CONSTANT HALT : STD_LOGIC_VECTOR(5 DOWNTO 0) := "001111";
TYPE STATES IS (fetch, decode, exec, halted);
SIGNAL IR : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL STATE : STATES;
BEGIN
PROCESS(CLK, RST)
BEGIN
IF(RST = '1') THEN
STATE <= fetch;
DRAW <= '0';
RW <= '0';
IR <= x"0000";
LoadFR <= '0';
LoadMAR <= '0';
LIDPC <= "000";
LIDSP <= "100";
LoadMBR <= '0';
LoadREG <= x"00";
HALT_ACK <= '0';
ELSIF(CLK'EVENT AND CLK = '1') THEN
CASE STATE IS
WHEN fetch =>
DRAW <= '0';
RW <= '0';
LoadFR <= '0';
LIDSP <= "000";
LoadREG <= x"00";
HALT_ACK <= '0';
sM1 <= "10";
LoadMBR <= '1';
IR <= INMEM;
LIDPC <= "010";
STATE <= decode;
WHEN decode =>
CASE IR(15 DOWNTO 10) IS
WHEN HALT =>
STATE <= halted;
WHEN OTHERS =>
END CASE;
WHEN exec =>
WHEN halted =>
HALT_ACK <= '1';
END CASE;
END IF;
END PROCESS;
END main; | gpl-3.0 | b3d4c28a9ca59c4bec7ad3afbed4629b | 0.576611 | 2.760837 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/LBDR_packet_drop_with_checkers/Rxy_Reconf_pseudo_checkers.vhd | 6 | 3,437 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
empty: in std_logic;
grants: in std_logic;
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_reconf: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end Rxy_Reconf_pseudo_checkers;
architecture behavior of Rxy_Reconf_pseudo_checkers is
begin
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy_reconf)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and Rxy_in /= Rxy_reconf) then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, ReConf_FF_in)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and ReConf_FF_in = '1') then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Rxy_in /= Rxy) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Reconfig, ReConf_FF_in)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig = '1' and ReConf_FF_in = '0') then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Reconfig, ReConf_FF_in, ReConf_FF_out)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig = '0' and ReConf_FF_in /= ReConf_FF_out) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal <= '0';
end if;
end process;
end; | gpl-3.0 | d58658132504df2baa44052274851cd2 | 0.641257 | 2.883389 | false | true | false | false |
siavooshpayandehazad/NoC_Router | RTL/Processor_NI/tbench.vhd | 3 | 5,047 | ---------------------------------------------------------------------
-- TITLE: Test Bench
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity provides a test bench for testing the Plasma CPU core.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
use work.TB_Package.all;
entity tbench is
end; --entity tbench
architecture logic of tbench is
constant memory_type : string :=
"TRI_PORT_X";
-- "DUAL_PORT_";
-- "ALTERA_LPM";
-- "XILINX_16X";
constant log_file : string :=
-- "UNUSED";
"output.txt";
signal clk : std_logic := '1';
signal reset : std_logic := '1';
signal interrupt : std_logic := '0';
signal mem_write : std_logic;
signal address : std_logic_vector(31 downto 2);
signal data_write : std_logic_vector(31 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal pause1 : std_logic := '0';
signal pause2 : std_logic := '0';
signal pause : std_logic;
signal no_ddr_start: std_logic;
signal no_ddr_stop : std_logic;
signal byte_we : std_logic_vector(3 downto 0);
signal uart_write : std_logic;
signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0');
signal credit_in, valid_in: std_logic := '0';
signal credit_out, valid_out: std_logic := '0';
signal RX: std_logic_vector(31 downto 0) := (others => '0');
signal TX: std_logic_vector(31 downto 0) := (others => '0');
signal credit_counter_out_0: std_logic_vector (1 downto 0);
begin --architecture
--Uncomment the line below to test interrupts
--interrupt <= '1' after 20 us when interrupt = '0' else '0' after 445 ns;
-- Added by Behrad
--interrupt <= '1' after 500 ns when interrupt = '0' else '0' after 100 us;
clk <= not clk after 50 ns;
reset <= '0' after 500 ns;
pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns;
pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns;
pause <= pause1 or pause2;
gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK
gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV
gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD
gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK
u1_plasma: plasma
generic map (memory_type => memory_type,
ethernet => '0',
use_cache => '0',
log_file => log_file,
current_address => 10)
PORT MAP (
clk => clk,
reset => reset,
uart_read => uart_write,
uart_write => uart_write,
address => address,
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
mem_pause_in => pause,
no_ddr_start => no_ddr_start,
no_ddr_stop => no_ddr_stop,
gpio0_out => open,
gpioA_in => gpioA_in,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX
);
dram_proc: process(clk, address, byte_we, data_write, pause)
constant ADDRESS_WIDTH : natural := 16;
type storage_array is
array(natural range 0 to (2 ** ADDRESS_WIDTH) / 4 - 1) of
std_logic_vector(31 downto 0);
variable storage : storage_array;
variable data : std_logic_vector(31 downto 0);
variable index : natural := 0;
begin
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if byte_we(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if byte_we(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if byte_we(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if byte_we(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
if rising_edge(clk) then
if address(30 downto 28) = "001" and byte_we /= "0000" then
storage(index) := data;
end if;
end if;
if pause = '0' then
data_read <= data;
end if;
end process;
credit_counter_control(clk, credit_out, valid_in, credit_counter_out_0);
gen_random_packet(4, 10, 0, 24, 8, 8, 10000 ns, clk, credit_counter_out_0, valid_in, RX);
get_packet(32, 5, 0, clk, credit_in, valid_out, TX);
end; --architecture logic
| gpl-3.0 | 59fd6e4278251a1c73454f164fd8f7b8 | 0.538141 | 3.5 | false | false | false | false |
simoesusp/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE70/lpm_ram_dq1.vhd | 3 | 7,084 | -- megafunction wizard: %LPM_RAM_DQ%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_ram_dq1.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_ram_dq1 IS
PORT
(
address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_ram_dq1;
ARCHITECTURE SYN OF lpm_ram_dq1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(3 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "video_mem2.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 16384,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
widthad_a => 14,
width_a => 4,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "video_mem2.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "video_mem2.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL address[13..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL data[3..0]
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL q[3..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
-- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 3776d47e2852ee9551dab9964560d644 | 0.67476 | 3.472549 | false | false | false | false |
ashtonchase/logic_analyzer | src/sample_rate_ctrl.vhd | 1 | 3,668 | -------------------------------------------------------------------------------
-- Title : Sample Rate Control
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : sample_rate_ctrl.vhd
-- Created : 2016-04-05
-- Last update: 2016-04-09
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: The sample rate control simply recieves the sampling frequency
-- from the message processor and then divides the clock to control the rate
-- that the capture control samples the inputs.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-04-05 0.0 David Created
-- 2016-04-06 1.0 David Major functionality complete
-- 2016-04-07 1.1 David Correcting errors in divider generation
-- 2016-04-09 1.2 Ashton removed geneic, updated port x->divder_rate
-- corrected castin from divider rate to integer
-- beautified.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sample_rate_ctrl is
port(
-- Global Signals
clk : in std_logic; -- Clock
rst : in std_logic; -- Synchronous reset
-- Message Processor Interface
divider_rate : in std_logic_vector(23 downto 0); -- Division factor - 1
-- Capture Control Interface
reset : in std_logic; -- Reset rate clock
armed : in std_logic; -- Indicates that capture control is armed
sample_en : out std_logic -- Sample enable
);
end entity sample_rate_ctrl;
architecture behave of sample_rate_ctrl is
signal div : natural := 1; -- Division factor
signal count : natural := 0;
signal sample : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
sample <= '0';
if rst = '1' then
div <= 0;
count <= 0;
sample <= '0';
else
-- Only update sample rate if cap control isn't armed
if armed /= '1' then
div <= to_integer(unsigned(divider_rate));
end if;
if reset = '1' then
count <= 0;
elsif div = 1 then -- No division
sample <= '1';
elsif count < div then -- f = clock/div
count <= count + 1;
else
count <= 0;
sample <= '1';
end if;
end if;
end if;
end process;
sample_en <= sample;
end architecture;
| gpl-2.0 | 96c03b7350476a84ec4c5fe311af0b7f | 0.524809 | 4.714653 | false | false | false | false |
elainemielas/CVUT_BI-PNO | cvika/scit1/CONTROLLER.vhd | 2 | 1,208 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CONTROLLER is
port(
CLK : in std_logic;
RESET : in std_logic;
TOP : in std_logic;
BOTTOM : in std_logic;
UP : out std_logic
);
end CONTROLLER;
architecture CONTROLLER_BODY of CONTROLLER is
type TYP_STAV is (NAHORU, DOLU);
signal STAV, DALSI_STAV : TYP_STAV;
begin
PRECHODY : process (TOP, BOTTOM, STAV)
begin
DALSI_STAV <= STAV;
case STAV is
when NAHORU => if TOP = '1' then DALSI_STAV <= DOLU;
--else DALSI_STAV <= NAHORU;
end if;
when DOLU => if BOTTOM = '1' then DALSI_STAV <= NAHORU;
--else DALSI_STAV <= DOLU;
end if;
end case;
end process;
VYSTUP : process (STAV, TOP, BOTTOM)
begin
case STAV is
when NAHORU => if TOP = '1' then UP <= '0';
else UP <= '1';
end if;
when DOLU => if BOTTOM = '1' then UP <= '1';
else UP <= '0';
end if;
end case;
end process;
REG : process (CLK)
begin
if CLK'event and CLK = '1' then
if RESET = '1' then STAV <= NAHORU;
else STAV <= DALSI_STAV;
end if;
end if;
end process;
end architecture;
| mit | e5443871d2d0a501a6245eefc32ff212 | 0.548013 | 3.073791 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/Checkers/Control_Part_Checkers/Allocator_checkers/Allocator_logic_checkers/allocator_logic_pseudo.vhd | 3 | 4,094 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_logic_pseudo is
port (
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: in std_logic;
grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: in std_logic;
grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: in std_logic;
grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: in std_logic;
grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: in std_logic;
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic;
grant_N_out, grant_E_out, grant_W_out, grant_S_out, grant_L_out : out std_logic
);
end allocator_logic_pseudo;
architecture behavior of allocator_logic_pseudo is
signal grant_N, grant_E, grant_W, grant_S, grant_L: std_logic;
begin
-- The combionational part
-- We did this because of the checkers
grant_N_out <= grant_N;
grant_E_out <= grant_E;
grant_W_out <= grant_W;
grant_S_out <= grant_S;
grant_L_out <= grant_L;
---------------------------------------------
grant_N_N <= grant_N_N_sig and not empty_N;
grant_N_E <= grant_N_E_sig and not empty_E;
grant_N_W <= grant_N_W_sig and not empty_W;
grant_N_S <= grant_N_S_sig and not empty_S;
grant_N_L <= grant_N_L_sig and not empty_L;
grant_E_N <= grant_E_N_sig and not empty_N;
grant_E_E <= grant_E_E_sig and not empty_E;
grant_E_W <= grant_E_W_sig and not empty_W;
grant_E_S <= grant_E_S_sig and not empty_S;
grant_E_L <= grant_E_L_sig and not empty_L;
grant_W_N <= grant_W_N_sig and not empty_N;
grant_W_E <= grant_W_E_sig and not empty_E;
grant_W_W <= grant_W_W_sig and not empty_W;
grant_W_S <= grant_W_S_sig and not empty_S;
grant_W_L <= grant_W_L_sig and not empty_L;
grant_S_N <= grant_S_N_sig and not empty_N;
grant_S_E <= grant_S_E_sig and not empty_E;
grant_S_W <= grant_S_W_sig and not empty_W;
grant_S_S <= grant_S_S_sig and not empty_S;
grant_S_L <= grant_S_L_sig and not empty_L;
grant_L_N <= grant_L_N_sig and not empty_N;
grant_L_E <= grant_L_E_sig and not empty_E;
grant_L_W <= grant_L_W_sig and not empty_W;
grant_L_S <= grant_L_S_sig and not empty_S;
grant_L_L <= grant_L_L_sig and not empty_L;
grant_N <= (grant_N_N_sig and not empty_N )or (grant_N_E_sig and not empty_E) or (grant_N_W_sig and not empty_W) or (grant_N_S_sig and not empty_S) or (grant_N_L_sig and not empty_L);
grant_E <= (grant_E_N_sig and not empty_N )or (grant_E_E_sig and not empty_E) or (grant_E_W_sig and not empty_W) or (grant_E_S_sig and not empty_S) or (grant_E_L_sig and not empty_L);
grant_W <= (grant_W_N_sig and not empty_N )or (grant_W_E_sig and not empty_E) or (grant_W_W_sig and not empty_W) or (grant_W_S_sig and not empty_S) or (grant_W_L_sig and not empty_L);
grant_S <= (grant_S_N_sig and not empty_N )or (grant_S_E_sig and not empty_E) or (grant_S_W_sig and not empty_W) or (grant_S_S_sig and not empty_S) or (grant_S_L_sig and not empty_L);
grant_L <= (grant_L_N_sig and not empty_N )or (grant_L_E_sig and not empty_E) or (grant_L_W_sig and not empty_W) or (grant_L_S_sig and not empty_S) or (grant_L_L_sig and not empty_L);
valid_N <= grant_N;
valid_E <= grant_E;
valid_W <= grant_W;
valid_S <= grant_S;
valid_L <= grant_L;
END;
| gpl-3.0 | 883c289711aa6b0feacc4d19f712f424 | 0.628725 | 2.403993 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/component_pack.vhd | 3 | 78,426 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
package component_pack is
-- constant definitions
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
component router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI (Outputs for classified fault information)
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
---- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
---- Outputs for non-classified fault information
--link_faults_async: out std_logic_vector(4 downto 0);
--turn_faults_async: out std_logic_vector(19 downto 0)
);
end component;
-- component declarations
component network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic;
-- IJTAG network for fault injection and checker status monitoring
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic
);
end component;
component NoC_Node is
generic( current_address : integer := 0;
stim_file: string :="code.txt";
log_file : string := "output.txt";
memory_type : string :=
"TRI_PORT_X"
-- "DUAL_PORT_"
-- "ALTERA_LPM"
-- "XILINX_16X"
);
port( reset : in std_logic;
clk : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic;
GPIO_out: out std_logic_vector(15 downto 0);
GPIO_in: in std_logic_vector(21 downto 0)
);
end component; --entity NoC_Node
COMPONENT counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, intermittent, Faulty: out std_logic
);
end COMPONENT;
--COMPONENT checkers_counter_threshold_classifier is
-- generic (
-- counter_depth: integer := 8;
-- healthy_counter_threshold: integer := 4;
-- faulty_counter_threshold: integer := 4
-- );
-- port ( reset: in std_logic;
-- clk: in std_logic;
-- data_input: in std_logic;
-- Healthy, Intermittent, Faulty: out std_logic
-- );
--end COMPONENT;
component LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order : out std_logic
);
end component;
component Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end component;
component Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Rxy_tmp: in std_logic_vector(7 downto 0);
Reconfig_command : in std_logic;
flit_type: in std_logic_vector(2 downto 0);
grants: in std_logic;
empty: in std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_tmp_in: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end component;
component FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
fault_info_out: in std_logic;
fault_info_in: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot,
err_read_pointer_in_onehot, err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full,
err_read_pointer_increment, err_read_pointer_not_increment, err_write_en, err_not_write_en,
err_not_write_en1, err_not_write_en2, err_read_en_mismatch, err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end component;
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic;
---- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Checker outputs
-- Functional checkers
err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot,
err_read_pointer_in_onehot, err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en, err_not_write_en, err_not_write_en1, err_not_write_en2,
err_read_en_mismatch, err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end COMPONENT;
COMPONENT parity_checker_for_LBDR is
generic(DATA_WIDTH : integer := 32);
port(
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
empty: in std_logic;
faulty: out std_logic
);
end COMPONENT;
COMPONENT LBDR_packet_drop is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic;
---- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Checker outputs
-- Routing part checkers
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order,
-- Cx_Reconf checkers
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
-- Rxy_Reconf checkers
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
--component fault_injector
-- generic(
-- DATA_WIDTH : integer := 32;
-- ADDRESS_WIDTH : integer := 5
-- );
-- port(
-- data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
-- address: in std_logic_vector (ADDRESS_WIDTH-1 downto 0);
-- sta_0: in std_logic;
-- sta_1: in std_logic;
-- data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
-- );
--end component;
--component shift_register_serial_in
-- generic (
-- REG_WIDTH: integer := 32
-- );
-- port (
-- TCK, reset : in std_logic;
-- SE: in std_logic; -- shift enable
-- UE: in std_logic; -- update enable
-- SI: in std_logic; -- serial Input
-- SO: out std_logic; -- serial output
-- data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0)
-- );
--end component;
component Arbiter_in
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L: in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L: out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N, err_IDLE_grant_N,err_North_Req_N, err_North_grant_N, err_East_Req_E, err_East_grant_E,
err_West_Req_W, err_West_grant_W, err_South_Req_S,err_South_grant_S,err_Local_Req_L, err_Local_grant_L,
err_IDLE_Req_E, err_IDLE_grant_E, err_North_Req_E, err_North_grant_E, err_East_Req_W, err_East_grant_W,
err_West_Req_S, err_West_grant_S, err_South_Req_L, err_South_grant_L, err_Local_Req_N, err_Local_grant_N,
err_IDLE_Req_W, err_IDLE_grant_W, err_North_Req_W, err_North_grant_W, err_East_Req_S, err_East_grant_S,
err_West_Req_L, err_West_grant_L, err_South_Req_N, err_South_grant_N, err_Local_Req_E, err_Local_grant_E,
err_IDLE_Req_S, err_IDLE_grant_S, err_North_Req_S, err_North_grant_S, err_East_Req_L, err_East_grant_L,
err_West_Req_N, err_West_grant_N, err_South_Req_E, err_South_grant_E, err_Local_Req_W, err_Local_grant_W,
err_IDLE_Req_L, err_IDLE_grant_L, err_North_Req_L, err_North_grant_L, err_East_Req_N, err_East_grant_N,
err_West_Req_E, err_West_grant_E, err_South_Req_W, err_South_grant_W, err_Local_Req_S, err_Local_grant_S,
err_state_in_onehot, err_no_request_grants, err_request_no_grants,
err_no_Req_N_grant_N, err_no_Req_E_grant_E, err_no_Req_W_grant_W, err_no_Req_S_grant_S, err_no_Req_L_grant_L : out std_logic
);
end component;
component Arbiter_in_one_hot_checkers
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N, err_IDLE_grant_N,err_North_Req_N, err_North_grant_N, err_East_Req_E, err_East_grant_E,
err_West_Req_W, err_West_grant_W, err_South_Req_S,err_South_grant_S,err_Local_Req_L, err_Local_grant_L,
err_IDLE_Req_E, err_IDLE_grant_E, err_North_Req_E, err_North_grant_E, err_East_Req_W, err_East_grant_W,
err_West_Req_S, err_West_grant_S, err_South_Req_L, err_South_grant_L, err_Local_Req_N, err_Local_grant_N,
err_IDLE_Req_W, err_IDLE_grant_W, err_North_Req_W, err_North_grant_W, err_East_Req_S, err_East_grant_S,
err_West_Req_L, err_West_grant_L, err_South_Req_N, err_South_grant_N, err_Local_Req_E, err_Local_grant_E,
err_IDLE_Req_S, err_IDLE_grant_S, err_North_Req_S, err_North_grant_S, err_East_Req_L, err_East_grant_L,
err_West_Req_N, err_West_grant_N, err_South_Req_E, err_South_grant_E, err_Local_Req_W, err_Local_grant_W,
err_IDLE_Req_L, err_IDLE_grant_L, err_North_Req_L, err_North_grant_L, err_East_Req_N, err_East_grant_N,
err_West_Req_E, err_West_grant_E, err_South_Req_W, err_South_grant_W, err_Local_Req_S, err_Local_grant_S,
err_state_in_onehot, err_no_request_grants, err_request_no_grants, err_no_Req_N_grant_N,
err_no_Req_E_grant_E, err_no_Req_W_grant_W, err_no_Req_S_grant_S, err_no_Req_L_grant_L : out std_logic
);
end component;
component Arbiter_out_one_hot_pseudo_checkers
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : in std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N, err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E, err_North_req_X_E, err_East_req_X_W, err_West_req_X_S, err_South_req_X_L, err_Local_req_X_N,
err_IDLE_req_X_W, err_North_req_X_W, err_East_req_X_S, err_West_req_X_L, err_South_req_X_N, err_Local_req_X_E,
err_IDLE_req_X_S, err_North_req_X_S, err_East_req_X_L, err_West_req_X_N, err_South_req_X_E, err_Local_req_X_W,
err_IDLE_req_X_L, err_North_req_X_L, err_East_req_X_N, err_West_req_X_E, err_South_req_X_W, err_Local_req_X_S,
err_state_in_onehot, err_no_request_grants, err_request_IDLE_state,
err_request_IDLE_not_Grants, err_state_North_Invalid_Grant, err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant, err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic
);
end component;
component arbiter_out port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N, err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E, err_North_req_X_E, err_East_req_X_W, err_West_req_X_S, err_South_req_X_L, err_Local_req_X_N,
err_IDLE_req_X_W, err_North_req_X_W, err_East_req_X_S, err_West_req_X_L, err_South_req_X_N, err_Local_req_X_E,
err_IDLE_req_X_S, err_North_req_X_S, err_East_req_X_L, err_West_req_X_N, err_South_req_X_E, err_Local_req_X_W,
err_IDLE_req_X_L, err_North_req_X_L, err_East_req_X_N, err_West_req_X_E, err_South_req_X_W, err_Local_req_X_S,
err_state_in_onehot, err_no_request_grants, err_request_IDLE_state,
err_request_IDLE_not_Grants, err_state_North_Invalid_Grant, err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant, err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic );
end component;
component allocator_logic_pseudo_checkers
port (
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: in std_logic;
grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: in std_logic;
grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: in std_logic;
grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: in std_logic;
grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: in std_logic;
valid_N, valid_E, valid_W, valid_S, valid_L : in std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: in std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: in std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: in std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: in std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L : in std_logic;
-- Checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E, err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L, err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E, err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L, err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E, err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L, err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E, err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L, err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E, err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L, err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E, err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L, err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match : out std_logic
);
end component;
component allocator_credit_counter_logic_pseudo_checkers
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0);
valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid !
credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0);
-- Checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic
);
end component;
component allocator
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic;
-- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
-- Allocator logic checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N, err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E, err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S, err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N, err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E, err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S, err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N, err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E, err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S, err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N, err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E, err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S, err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N, err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E, err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S, err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N, err_grant_signals_not_empty_grant_E,
err_not_grant_signals_empty_not_grant_E, err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S, err_grant_signals_not_empty_grant_L,
err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match,
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change, err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change, err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change, err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change, err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal, err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change, err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
-- Arbiter_in checker outputs
-- North Arbiter_in checker outputs
N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N, N_err_IDLE_grant_N, N_err_North_Req_N, N_err_North_grant_N, N_err_East_Req_E, N_err_East_grant_E,
N_err_West_Req_W, N_err_West_grant_W, N_err_South_Req_S,N_err_South_grant_S,N_err_Local_Req_L, N_err_Local_grant_L,
N_err_IDLE_Req_E, N_err_IDLE_grant_E, N_err_North_Req_E, N_err_North_grant_E, N_err_East_Req_W, N_err_East_grant_W,
N_err_West_Req_S, N_err_West_grant_S, N_err_South_Req_L, N_err_South_grant_L, N_err_Local_Req_N, N_err_Local_grant_N,
N_err_IDLE_Req_W, N_err_IDLE_grant_W, N_err_North_Req_W, N_err_North_grant_W, N_err_East_Req_S, N_err_East_grant_S,
N_err_West_Req_L, N_err_West_grant_L, N_err_South_Req_N, N_err_South_grant_N, N_err_Local_Req_E, N_err_Local_grant_E,
N_err_IDLE_Req_S, N_err_IDLE_grant_S, N_err_North_Req_S, N_err_North_grant_S, N_err_East_Req_L, N_err_East_grant_L,
N_err_West_Req_N, N_err_West_grant_N, N_err_South_Req_E, N_err_South_grant_E, N_err_Local_Req_W, N_err_Local_grant_W,
N_err_IDLE_Req_L, N_err_IDLE_grant_L, N_err_North_Req_L, N_err_North_grant_L, N_err_East_Req_N, N_err_East_grant_N,
N_err_West_Req_E, N_err_West_grant_E, N_err_South_Req_W, N_err_South_grant_W, N_err_Local_Req_S, N_err_Local_grant_S,
N_err_state_in_onehot, N_err_no_request_grants, N_err_request_no_grants,
N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L,
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N, E_err_IDLE_grant_N, E_err_North_Req_N, E_err_North_grant_N, E_err_East_Req_E, E_err_East_grant_E,
E_err_West_Req_W, E_err_West_grant_W, E_err_South_Req_S, E_err_South_grant_S, E_err_Local_Req_L, E_err_Local_grant_L,
E_err_IDLE_Req_E, E_err_IDLE_grant_E, E_err_North_Req_E, E_err_North_grant_E, E_err_East_Req_W, E_err_East_grant_W,
E_err_West_Req_S, E_err_West_grant_S, E_err_South_Req_L, E_err_South_grant_L, E_err_Local_Req_N, E_err_Local_grant_N,
E_err_IDLE_Req_W, E_err_IDLE_grant_W, E_err_North_Req_W, E_err_North_grant_W, E_err_East_Req_S, E_err_East_grant_S,
E_err_West_Req_L, E_err_West_grant_L, E_err_South_Req_N, E_err_South_grant_N, E_err_Local_Req_E, E_err_Local_grant_E,
E_err_IDLE_Req_S, E_err_IDLE_grant_S, E_err_North_Req_S, E_err_North_grant_S, E_err_East_Req_L, E_err_East_grant_L,
E_err_West_Req_N, E_err_West_grant_N, E_err_South_Req_E, E_err_South_grant_E, E_err_Local_Req_W, E_err_Local_grant_W,
E_err_IDLE_Req_L, E_err_IDLE_grant_L, E_err_North_Req_L, E_err_North_grant_L, E_err_East_Req_N, E_err_East_grant_N,
E_err_West_Req_E, E_err_West_grant_E, E_err_South_Req_W, E_err_South_grant_W, E_err_Local_Req_S, E_err_Local_grant_S,
E_err_state_in_onehot, E_err_no_request_grants, E_err_request_no_grants,
E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L,
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N, W_err_IDLE_grant_N, W_err_North_Req_N, W_err_North_grant_N, W_err_East_Req_E, W_err_East_grant_E,
W_err_West_Req_W, W_err_West_grant_W, W_err_South_Req_S, W_err_South_grant_S, W_err_Local_Req_L, W_err_Local_grant_L,
W_err_IDLE_Req_E, W_err_IDLE_grant_E, W_err_North_Req_E, W_err_North_grant_E, W_err_East_Req_W, W_err_East_grant_W,
W_err_West_Req_S, W_err_West_grant_S, W_err_South_Req_L, W_err_South_grant_L, W_err_Local_Req_N, W_err_Local_grant_N,
W_err_IDLE_Req_W, W_err_IDLE_grant_W, W_err_North_Req_W, W_err_North_grant_W, W_err_East_Req_S, W_err_East_grant_S,
W_err_West_Req_L, W_err_West_grant_L, W_err_South_Req_N, W_err_South_grant_N, W_err_Local_Req_E, W_err_Local_grant_E,
W_err_IDLE_Req_S, W_err_IDLE_grant_S, W_err_North_Req_S, W_err_North_grant_S, W_err_East_Req_L, W_err_East_grant_L,
W_err_West_Req_N, W_err_West_grant_N, W_err_South_Req_E, W_err_South_grant_E, W_err_Local_Req_W, W_err_Local_grant_W,
W_err_IDLE_Req_L, W_err_IDLE_grant_L, W_err_North_Req_L, W_err_North_grant_L, W_err_East_Req_N, W_err_East_grant_N,
W_err_West_Req_E, W_err_West_grant_E, W_err_South_Req_W, W_err_South_grant_W, W_err_Local_Req_S, W_err_Local_grant_S,
W_err_state_in_onehot, W_err_no_request_grants, W_err_request_no_grants,
W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L,
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N, S_err_IDLE_grant_N, S_err_North_Req_N, S_err_North_grant_N, S_err_East_Req_E, S_err_East_grant_E,
S_err_West_Req_W, S_err_West_grant_W, S_err_South_Req_S,S_err_South_grant_S,S_err_Local_Req_L, S_err_Local_grant_L,
S_err_IDLE_Req_E, S_err_IDLE_grant_E, S_err_North_Req_E, S_err_North_grant_E, S_err_East_Req_W, S_err_East_grant_W,
S_err_West_Req_S, S_err_West_grant_S, S_err_South_Req_L, S_err_South_grant_L, S_err_Local_Req_N, S_err_Local_grant_N,
S_err_IDLE_Req_W, S_err_IDLE_grant_W, S_err_North_Req_W, S_err_North_grant_W, S_err_East_Req_S, S_err_East_grant_S,
S_err_West_Req_L, S_err_West_grant_L, S_err_South_Req_N, S_err_South_grant_N, S_err_Local_Req_E, S_err_Local_grant_E,
S_err_IDLE_Req_S, S_err_IDLE_grant_S, S_err_North_Req_S, S_err_North_grant_S, S_err_East_Req_L, S_err_East_grant_L,
S_err_West_Req_N, S_err_West_grant_N, S_err_South_Req_E, S_err_South_grant_E, S_err_Local_Req_W, S_err_Local_grant_W,
S_err_IDLE_Req_L, S_err_IDLE_grant_L, S_err_North_Req_L, S_err_North_grant_L, S_err_East_Req_N, S_err_East_grant_N,
S_err_West_Req_E, S_err_West_grant_E, S_err_South_Req_W, S_err_South_grant_W, S_err_Local_Req_S, S_err_Local_grant_S,
S_err_state_in_onehot, S_err_no_request_grants, S_err_request_no_grants,
S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L,
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N, L_err_IDLE_grant_N, L_err_North_Req_N, L_err_North_grant_N, L_err_East_Req_E, L_err_East_grant_E,
L_err_West_Req_W, L_err_West_grant_W, L_err_South_Req_S, L_err_South_grant_S, L_err_Local_Req_L, L_err_Local_grant_L,
L_err_IDLE_Req_E, L_err_IDLE_grant_E, L_err_North_Req_E, L_err_North_grant_E, L_err_East_Req_W, L_err_East_grant_W,
L_err_West_Req_S, L_err_West_grant_S, L_err_South_Req_L, L_err_South_grant_L, L_err_Local_Req_N, L_err_Local_grant_N,
L_err_IDLE_Req_W, L_err_IDLE_grant_W, L_err_North_Req_W, L_err_North_grant_W, L_err_East_Req_S, L_err_East_grant_S,
L_err_West_Req_L, L_err_West_grant_L, L_err_South_Req_N, L_err_South_grant_N, L_err_Local_Req_E, L_err_Local_grant_E,
L_err_IDLE_Req_S, L_err_IDLE_grant_S, L_err_North_Req_S, L_err_North_grant_S, L_err_East_Req_L, L_err_East_grant_L,
L_err_West_Req_N, L_err_West_grant_N, L_err_South_Req_E, L_err_South_grant_E, L_err_Local_Req_W, L_err_Local_grant_W,
L_err_IDLE_Req_L, L_err_IDLE_grant_L, L_err_North_Req_L, L_err_North_grant_L, L_err_East_Req_N, L_err_East_grant_N,
L_err_West_Req_E, L_err_West_grant_E, L_err_South_Req_W, L_err_South_grant_W, L_err_Local_Req_S, L_err_Local_grant_S,
L_err_state_in_onehot, L_err_no_request_grants, L_err_request_no_grants,
L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S, L_err_no_Req_L_grant_L,
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N, N_err_North_req_X_N, N_err_North_credit_not_zero_req_X_N_grant_N, N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E, N_err_East_credit_not_zero_req_X_E_grant_E, N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
N_err_West_req_X_W, N_err_West_credit_not_zero_req_X_W_grant_W, N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
N_err_South_req_X_S, N_err_South_credit_not_zero_req_X_S_grant_S, N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
N_err_Local_req_X_L, N_err_Local_credit_not_zero_req_X_L_grant_L, N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E, N_err_North_req_X_E, N_err_East_req_X_W, N_err_West_req_X_S, N_err_South_req_X_L, N_err_Local_req_X_N,
N_err_IDLE_req_X_W, N_err_North_req_X_W, N_err_East_req_X_S, N_err_West_req_X_L, N_err_South_req_X_N, N_err_Local_req_X_E,
N_err_IDLE_req_X_S, N_err_North_req_X_S, N_err_East_req_X_L, N_err_West_req_X_N, N_err_South_req_X_E, N_err_Local_req_X_W,
N_err_IDLE_req_X_L, N_err_North_req_X_L, N_err_East_req_X_N, N_err_West_req_X_E, N_err_South_req_X_W, N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot, N_arbiter_out_err_no_request_grants, N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant, N_err_state_West_Invalid_Grant,
N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant, N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N, E_err_North_req_X_N, E_err_North_credit_not_zero_req_X_N_grant_N, E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E, E_err_East_credit_not_zero_req_X_E_grant_E, E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
E_err_West_req_X_W, E_err_West_credit_not_zero_req_X_W_grant_W, E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
E_err_South_req_X_S, E_err_South_credit_not_zero_req_X_S_grant_S, E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
E_err_Local_req_X_L, E_err_Local_credit_not_zero_req_X_L_grant_L, E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E, E_err_North_req_X_E, E_err_East_req_X_W, E_err_West_req_X_S, E_err_South_req_X_L, E_err_Local_req_X_N,
E_err_IDLE_req_X_W, E_err_North_req_X_W, E_err_East_req_X_S, E_err_West_req_X_L, E_err_South_req_X_N, E_err_Local_req_X_E,
E_err_IDLE_req_X_S, E_err_North_req_X_S, E_err_East_req_X_L, E_err_West_req_X_N, E_err_South_req_X_E, E_err_Local_req_X_W,
E_err_IDLE_req_X_L, E_err_North_req_X_L, E_err_East_req_X_N, E_err_West_req_X_E, E_err_South_req_X_W, E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot, E_arbiter_out_err_no_request_grants, E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant,E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N, W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N, W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E, W_err_North_req_X_E, W_err_East_req_X_W, W_err_West_req_X_S, W_err_South_req_X_L, W_err_Local_req_X_N,
W_err_IDLE_req_X_W, W_err_North_req_X_W, W_err_East_req_X_S, W_err_West_req_X_L, W_err_South_req_X_N, W_err_Local_req_X_E,
W_err_IDLE_req_X_S, W_err_North_req_X_S, W_err_East_req_X_L, W_err_West_req_X_N, W_err_South_req_X_E, W_err_Local_req_X_W,
W_err_IDLE_req_X_L, W_err_North_req_X_L, W_err_East_req_X_N, W_err_West_req_X_E, W_err_South_req_X_W, W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot, W_arbiter_out_err_no_request_grants, W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant, W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant,
W_err_state_South_Invalid_Grant, W_err_state_Local_Invalid_Grant, W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N, S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N, S_err_North_credit_zero_or_not_req_X_N_not_grant_N,
S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E, S_err_East_credit_zero_or_not_req_X_E_not_grant_E,
S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W, S_err_West_credit_zero_or_not_req_X_W_not_grant_W,
S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S, S_err_South_credit_zero_or_not_req_X_S_not_grant_S,
S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L, S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E, S_err_North_req_X_E, S_err_East_req_X_W, S_err_West_req_X_S, S_err_South_req_X_L, S_err_Local_req_X_N,
S_err_IDLE_req_X_W, S_err_North_req_X_W, S_err_East_req_X_S, S_err_West_req_X_L, S_err_South_req_X_N, S_err_Local_req_X_E,
S_err_IDLE_req_X_S, S_err_North_req_X_S, S_err_East_req_X_L, S_err_West_req_X_N, S_err_South_req_X_E, S_err_Local_req_X_W,
S_err_IDLE_req_X_L, S_err_North_req_X_L, S_err_East_req_X_N, S_err_West_req_X_E, S_err_South_req_X_W, S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N, L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N, L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E, L_err_East_credit_zero_or_not_req_X_E_not_grant_E, L_err_West_req_X_W,
L_err_West_credit_not_zero_req_X_W_grant_W, L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S, L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L, L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E, L_err_North_req_X_E, L_err_East_req_X_W, L_err_West_req_X_S, L_err_South_req_X_L, L_err_Local_req_X_N,
L_err_IDLE_req_X_W, L_err_North_req_X_W, L_err_East_req_X_S, L_err_West_req_X_L, L_err_South_req_X_N, L_err_Local_req_X_E,
L_err_IDLE_req_X_S, L_err_North_req_X_S, L_err_East_req_X_L, L_err_West_req_X_N, L_err_South_req_X_E, L_err_Local_req_X_W,
L_err_IDLE_req_X_L, L_err_North_req_X_L, L_err_East_req_X_N, L_err_West_req_X_E, L_err_South_req_X_W, L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot, L_arbiter_out_err_no_request_grants, L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant, L_err_state_East_Invalid_Grant, L_err_state_West_Invalid_Grant,
L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant, L_err_Grants_onehot_or_all_zero : out std_logic
);
end component;
end; --package body
| gpl-3.0 | 0abae1410c3ef8f9531c118afc96b7ab | 0.623951 | 2.692091 | false | false | false | false |
kiwih/subleq-vhdl | clk_div.vhd | 1 | 580 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clk_div is
generic(
CLOCK_DIVIDE : integer := 5000000
);
port (
CLK_50: in std_logic;
CLK_SLOW: out std_logic
);
end entity clk_div;
architecture beh of clk_div is
begin
-- clk_out <= clk_in;
process (CLK_50)
variable count: integer range 0 to (CLOCK_DIVIDE - 1) := 0;
begin
if(rising_edge(CLK_50)) then
if(count = (CLOCK_DIVIDE - 1)) then
count := 0;
CLK_SLOW <= '1';
else
CLK_SLOW <= '0';
count := count + 1;
end if;
end if;
end process;
end architecture beh; | mit | b1f8085db93a8f267afde514bd0b2176 | 0.636207 | 2.66055 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/Arbiter_in_one_hot_with_checkers.vhd | 12 | 12,952 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
-- Is this like the old arbiter in the router with handshaking FC ??
entity Arbiter_in is
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L: in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L: out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in;
architecture behavior of Arbiter_in is
--TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in : STATE_TYPE := IDLE;
SIGNAL X_N_sig, X_E_sig, X_W_sig, X_S_sig, X_L_sig: std_logic; -- needed for connecting output ports
-- of Arbiter_in to checker inputs
component Arbiter_in_one_hot_checkers is
port (
req_X_N :in std_logic;
req_X_E :in std_logic;
req_X_W :in std_logic;
req_X_S :in std_logic;
req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N :in std_logic;
X_E :in std_logic;
X_W :in std_logic;
X_S :in std_logic;
X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end component;
begin
-- Becuase of checkers we did this
X_N <= X_N_sig;
X_E <= X_E_sig;
X_W <= X_W_sig;
X_S <= X_S_sig;
X_L <= X_L_sig;
-- Sequential part
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
-- Arbiter_in Checkers module instantiation
ARBITER_IN_CHECKERS: Arbiter_in_one_hot_checkers port map (
req_X_N => req_X_N, -- _sig not needed, because it is an input port
req_X_E => req_X_E, -- _sig not needed, because it is an input port
req_X_W => req_X_W, -- _sig not needed, because it is an input port
req_X_S => req_X_S, -- _sig not needed, because it is an input port
req_X_L => req_X_L, -- _sig not needed, because it is an input port
state => state, -- _sig not needed, because it is an input port
state_in => state_in, -- _sig not needed, because it is an internal signal
X_N => X_N_sig,
X_E => X_E_sig,
X_W => X_W_sig,
X_S => X_S_sig,
X_L => X_L_sig,
-- Checker outputs
err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => err_IDLE_Req_N,
err_IDLE_grant_N => err_IDLE_grant_N,
err_North_Req_N => err_North_Req_N,
err_North_grant_N => err_North_grant_N,
err_East_Req_E => err_East_Req_E,
err_East_grant_E => err_East_grant_E,
err_West_Req_W => err_West_Req_W,
err_West_grant_W => err_West_grant_W,
err_South_Req_S => err_South_Req_S,
err_South_grant_S => err_South_grant_S,
err_Local_Req_L => err_Local_Req_L,
err_Local_grant_L => err_Local_grant_L,
err_IDLE_Req_E => err_IDLE_Req_E,
err_IDLE_grant_E => err_IDLE_grant_E,
err_North_Req_E => err_North_Req_E,
err_North_grant_E => err_North_grant_E,
err_East_Req_W => err_East_Req_W,
err_East_grant_W => err_East_grant_W,
err_West_Req_S => err_West_Req_S,
err_West_grant_S => err_West_grant_S,
err_South_Req_L => err_South_Req_L,
err_South_grant_L => err_South_grant_L,
err_Local_Req_N => err_Local_Req_N,
err_Local_grant_N => err_Local_grant_N,
err_IDLE_Req_W => err_IDLE_Req_W,
err_IDLE_grant_W => err_IDLE_grant_W,
err_North_Req_W => err_North_Req_W,
err_North_grant_W => err_North_grant_W,
err_East_Req_S => err_East_Req_S,
err_East_grant_S => err_East_grant_S,
err_West_Req_L => err_West_Req_L,
err_West_grant_L => err_West_grant_L,
err_South_Req_N => err_South_Req_N,
err_South_grant_N => err_South_grant_N,
err_Local_Req_E => err_Local_Req_E,
err_Local_grant_E => err_Local_grant_E,
err_IDLE_Req_S => err_IDLE_Req_S,
err_IDLE_grant_S => err_IDLE_grant_S,
err_North_Req_S => err_North_Req_S,
err_North_grant_S => err_North_grant_S,
err_East_Req_L => err_East_Req_L,
err_East_grant_L => err_East_grant_L,
err_West_Req_N => err_West_Req_N,
err_West_grant_N => err_West_grant_N,
err_South_Req_E => err_South_Req_E,
err_South_grant_E => err_South_grant_E,
err_Local_Req_W => err_Local_Req_W,
err_Local_grant_W => err_Local_grant_W,
err_IDLE_Req_L => err_IDLE_Req_L,
err_IDLE_grant_L => err_IDLE_grant_L,
err_North_Req_L => err_North_Req_L,
err_North_grant_L => err_North_grant_L,
err_East_Req_N => err_East_Req_N,
err_East_grant_N => err_East_grant_N,
err_West_Req_E => err_West_Req_E,
err_West_grant_E => err_West_grant_E,
err_South_Req_W => err_South_Req_W,
err_South_grant_W => err_South_grant_W,
err_Local_Req_S => err_Local_Req_S,
err_Local_grant_S => err_Local_grant_S,
err_state_in_onehot => err_state_in_onehot,
err_no_request_grants => err_no_request_grants,
err_request_no_grants => err_request_no_grants,
err_no_Req_N_grant_N => err_no_Req_N_grant_N,
err_no_Req_E_grant_E => err_no_Req_E_grant_E,
err_no_Req_W_grant_W => err_no_Req_W_grant_W,
err_no_Req_S_grant_S => err_no_Req_S_grant_S,
err_no_Req_L_grant_L => err_no_Req_L_grant_L
);
-- Main Logic of Arbiter_in
process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L)
begin
X_N_sig <= '0';
X_E_sig <= '0';
X_W_sig <= '0';
X_S_sig <= '0';
X_L_sig <= '0';
case state is
when IDLE => -- In the arbiter for hand-shaking FC router, L had the highest priority (L, N, E, W, S)
-- Here it seems N has the higest priority, is it fine ?
if req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
else
state_in <= state;
end if;
when North =>
if req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
else
state_in <= state;
end if;
when East =>
if req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
else
state_in <= state;
end if;
when West =>
if req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
else
state_in <= state;
end if;
when South =>
if req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
else
state_in <= state;
end if;
when others =>
if req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
else
state_in <= state;
end if;
end case;
end process;
end;
| gpl-3.0 | d8499c880ead9430eb6fcf18b7952328 | 0.512817 | 2.733066 | false | false | false | false |
Wynjones1/gbvhdl | src/registers.vhd | 1 | 4,214 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.common.all;
use work.types.all;
use work.interfaces.all;
entity registers is
port( clk : in std_logic;
reset : in std_logic;
input : in registers_in_if;
output : out registers_out_if);
end entity;
architecture rtl of registers is
signal af : word_t;
signal bc : word_t;
signal de : word_t;
signal hl : word_t;
signal sp : word_t;
signal pc : word_t;
begin
write: process(clk, reset)
constant filename : string := "/home/stuart/VHDL/gbvhdl/bin/registers_init.mif";
file input_file : text is in filename;
variable run : boolean := true;
begin
if reset = '1' then
if run then
af <= read_slv(input_file);
bc <= read_slv(input_file);
de <= read_slv(input_file);
hl <= read_slv(input_file);
sp <= read_slv(input_file);
run := false;
end if;
pc <= (others => '0');
elsif rising_edge(clk) then
if input.we = '1' then
case input.wsel is
when register_a => af(HI_BYTE) <= input.data(LO_BYTE);
when register_f => af(LO_BYTE) <= input.data(LO_BYTE);
when register_b => bc(HI_BYTE) <= input.data(LO_BYTE);
when register_c => bc(LO_BYTE) <= input.data(LO_BYTE);
when register_d => de(HI_BYTE) <= input.data(LO_BYTE);
when register_e => de(LO_BYTE) <= input.data(LO_BYTE);
when register_h => hl(HI_BYTE) <= input.data(LO_BYTE);
when register_l => hl(LO_BYTE) <= input.data(LO_BYTE);
when register_af => af <= input.data;
when register_bc => bc <= input.data;
when register_de => de <= input.data;
when register_hl => hl <= input.data;
when register_sp => sp <= input.data;
when register_pc => pc <= input.data;
when others =>
end case;
end if;
end if;
end process;
output_proc : process(af, bc, de, hl, sp, pc, input.rsel0, input.rsel1)
begin
output.d0 <= (others => '0');
output.d1 <= (others => '0');
case input.rsel0 is
when register_a => output.d0(LO_BYTE) <= af(HI_BYTE);
when register_f => output.d0(LO_BYTE) <= af(LO_BYTE);
when register_b => output.d0(LO_BYTE) <= bc(HI_BYTE);
when register_c => output.d0(LO_BYTE) <= bc(LO_BYTE);
when register_d => output.d0(LO_BYTE) <= de(HI_BYTE);
when register_e => output.d0(LO_BYTE) <= de(LO_BYTE);
when register_h => output.d0(LO_BYTE) <= hl(HI_BYTE);
when register_l => output.d0(LO_BYTE) <= hl(LO_BYTE);
when register_af => output.d0 <= af;
when register_bc => output.d0 <= bc;
when register_de => output.d0 <= de;
when register_hl => output.d0 <= hl;
when register_sp => output.d0 <= sp;
when register_pc => output.d0 <= pc;
when others =>
end case;
case input.rsel1 is
when register_a => output.d1(LO_BYTE) <= af(HI_BYTE);
when register_f => output.d1(LO_BYTE) <= af(LO_BYTE);
when register_b => output.d1(LO_BYTE) <= bc(HI_BYTE);
when register_c => output.d1(LO_BYTE) <= bc(LO_BYTE);
when register_d => output.d1(LO_BYTE) <= de(HI_BYTE);
when register_e => output.d1(LO_BYTE) <= de(LO_BYTE);
when register_h => output.d1(LO_BYTE) <= hl(HI_BYTE);
when register_l => output.d1(LO_BYTE) <= hl(LO_BYTE);
when register_af => output.d1 <= af;
when register_bc => output.d1 <= bc;
when register_de => output.d1 <= de;
when register_hl => output.d1 <= hl;
when register_sp => output.d1 <= sp;
when register_pc => output.d1 <= pc;
when others =>
end case;
end process;
output.pc <= pc;
output.a <= af(HI_BYTE);
output.f <= af(LO_BYTE);
output.sp <= sp;
output.hl <= hl;
end rtl;
| mit | c1a0b03e44c38d83d88241e4a6fd5083 | 0.522307 | 3.333861 | false | false | false | false |
elainemielas/CVUT_BI-PNO | project1/datapath.vhd | 1 | 2,563 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.std_logic_arith.all;
entity DATAPATH is
port(
INPUT : in std_logic_vector (7 downto 0);
CLK, RESET, POSUN, SCIT : in std_logic;
OUTPUT : out std_logic_vector (15 downto 0);
SHOW1OUT : out std_logic_vector (15 downto 0);
SHOW2OUT : out std_logic_vector (15 downto 0);
ZERO : out std_logic
);
end DATAPATH;
architecture DATAPATH_BODY of DATAPATH is
signal A0, A1, A2, A3 : std_logic_vector (7 downto 0); -- hodnoty
signal extA0, extA1, extA2, extA3, SUM, AIN : std_logic_vector (9 downto 0);
signal COUNT_VAL : std_logic_vector (2 downto 0); -- counter pro scitani
begin
LOAD : process (CLK)
begin
if CLK = '1' and CLK'event then
if POSUN = '1' then
A3 <= A2;
A2 <= A1;
A1 <= A0;
A0 <= INPUT;
elsif RESET = '1' then
A3 <= (others => '0');
A2 <= (others => '0');
A1 <= (others => '0');
A0 <= (others => '0');
end if;
end if;
end process;
-- rozsirime hodnoty, abysme neztratili znaminko
extA0 <= A0(7) & A0(7) & A0;
extA1 <= A1(7) & A1(7) & A1;
extA2 <= A2(7) & A2(7) & A2;
extA3 <= A3(7) & A3(7) & A3;
-- v registru AIN je hodnota, kterou budeme tedka pricitat k sume,
-- do ni budeme davat postupne vsichni hodnoty od extA0 do extA3 a bude se to ridit countrem
process(RESET, COUNT_VAL, extA0, extA1, extA2, extA3, SCIT)
begin
if RESET = '1' then
AIN <= (others => '0');
elsif SCIT = '1' then
case COUNT_VAL is
when "100" => AIN <= extA3;
when "011" => AIN <= extA2;
when "010" => AIN <= extA1;
when others => AIN <= extA0;
end case;
else
AIN <= (others => '0');
end if;
end process;
-- pocitani sumy
REG_SUM : process (CLK)
begin
if CLK = '1' and CLK'event then
if POSUN = '1' or RESET = '1' then
SUM <= (others => '0'); -- posun nam vysledek zresetuje
COUNT_VAL <= "100"; -- a nastavi counter na 4
elsif SCIT = '1' then
SUM <= SUM + AIN; -- scitame
COUNT_VAL <= COUNT_VAL - 1; -- zmensujeme counter
end if;
end if;
end process;
-- signal, ktery rekne, ze scitani je dodelano
ZERO <= '1' when COUNT_VAL = "001" else '0';
-- deleni 4 (vememe sumu bez 2 dolnich bitu a rozsirime ji pro snadne zobrazeni)
OUTPUT <= SUM(9) & SUM(9) &SUM(9) &SUM(9) &SUM(9) &SUM(9) &SUM(9) &SUM(9) & SUM(9 downto 2);
-- udelame vystup pro ukazani obsahu jednotlivych registru
SHOW1OUT <= A1 & A0;
SHOW2OUT <= A3 & A2;
end architecture;
| mit | c27bc8eb5c756ae8756c7873f2170c23 | 0.589934 | 2.631417 | false | false | false | false |
terfect/Geany-plus | data/filetypes.vhdl | 1 | 3,198 | # For complete documentation of this file, please see Geany's main documentation
[styling]
# foreground;background;bold;italic
default=0x000000;0xffffff;false;false
comment=0xd00000;0xffffff;false;false
comment_line_bang=0x3f5fbf;0xffffff;false;false;
number=0x007f00;0xffffff;false;false
string=0xff901e;0xffffff;false;false
operator=0x301010;0xffffff;false;false
identifier=0x000000;0xffffff;false;false
stringeol=0x000000;0xe0c0e0;false;false
keyword=0x001a7f;0xffffff;true;false
stdoperator=0x007f7f;0xffffff;false;false
attribute=0x804020;0xffffff;false;false
stdfunction=0x808020;0xffffff;true;false
stdpackage=0x208020;0xffffff;false;false
stdtype=0x208080;0xffffff;false;false
userword=0x804020;0xffffff;true;false
[keywords]
# all items must be in one line
keywords=access after alias all architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map new next null of on open others out package port postponed procedure process pure range record register reject report return select severity shared signal subtype then to transport type unaffected units until use variable wait when while with
operators=abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
attributes=left right low high ascending image value pos val succ pred leftof rightof base range reverse_range length delayed stable quiet transaction event active last_event last_active last_value driving driving_value simple_name path_name instance_name
std_functions=now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left rotate_right resize to_integer to_unsigned to_signed std_match to_01
std_packages=std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives vital_timing
std_types=boolean bit character severity_level integer real time delay_length natural positive string bit_vector file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
userwords=
[settings]
# default extension used when saving files
extension=vhd
# the following characters are these which a "word" can contains, see documentation
#wordchars=_abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789
# single comments, like # in this file
comment_single=--
# multiline comments
#comment_open=
#comment_close=
# set to false if a comment character/string should start at column 0 of a line, true uses any
# indentation of the line, e.g. setting to true causes the following on pressing CTRL+d
#command_example();
# setting to false would generate this
# command_example();
# This setting works only for single line comments
comment_use_indent=true
# context action command (please see Geany's main documentation for details)
context_action_cmd=
| gpl-2.0 | f2e709d0a43b0530953d15c4a712e3ed | 0.827392 | 3.853012 | false | false | false | false |
camacazio/de0_nano_DAC | DE0_12bitDAC_controller/adc_data.vhd | 1 | 5,530 | ----------------------------------------------------------------------------------
-- 12 bit input from ADC
-- Serial communication protocol
-- 16 clock cycles for a communication cycle, 3 bits defines the next 'read' data followed by 12 bit data
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Physical ports to the entity
entity ADC_CTRL is
port (
iRST : in std_logic; -- Reset trigger
iCLK : in std_logic; -- Positive clock
oadc_data : out std_logic_vector(11 downto 0); -- ADC read-out from a channel
oadc_chan : out std_logic_vector(2 downto 0); -- relevant channel
oADC_ADDR : out std_logic; -- setting for the desired ADC reading channel
oCS_n : out std_logic; -- activate ADC chip
oSCLK : out std_logic; -- serial clock
iADC_DATA : in std_logic -- incoming serial data from the ADC
);
end entity;
-- Behavioral
architecture rtl of ADC_CTRL is
----------------------------------------------------------------------------------
-- SIGNALS
----------------------------------------------------------------------------------
signal data : std_logic; -- channel select bit
signal go_en : std_logic; -- disabled when reset is triggered
signal count : std_logic_vector(3 downto 0); -- count serial clock edges up to 16
signal n_count : std_logic_vector(3 downto 0); -- count serial clock falling edges up to 16
signal ch_count : std_logic_vector(2 downto 0); -- counting up to NUM_CHANS
signal ch_reading : std_logic_vector(2 downto 0) := (others => '0'); -- the channel currently being read; one read cycle delay
signal adc_data : std_logic_vector(11 downto 0); -- data being read
signal prv_adc_data : std_logic_vector(11 downto 0); -- previous channel, complete data
signal prv_ch_read : std_logic_vector(2 downto 0); -- previous channel, used for data
-- number of channels for scanning read-out
constant NUM_CHANS : std_logic_vector(2 downto 0) := "001";
----------------------------------------------------------------------------------
-- BEGIN
----------------------------------------------------------------------------------
begin
-- latches for ADC line
oCS_n <= not(go_en); -- activate ADC unless reset is flagged
oSCLK <= iCLK when go_en = '1' else '1'; -- Send clock signal to ADC clock if go_en is 1
oADC_ADDR <= data; -- latch channel select bit
-- latches for the data from the ADC
oadc_data <= prv_adc_data; -- latch completed reading
oadc_chan <= prv_ch_read; -- latch completed channel
-- Check for reseting the ADC reading, or to continue
process(iCLK, iRST)
begin
if iRST = '0' then -- If iRST is triggered
go_en <= '0';
else
if rising_edge(iCLK) then -- at the first positive clock edge
go_en <='1';
end if;
end if;
end process;
-- counting positive edges of clock
process(iCLK, go_en) -- At positive clock edge or go_en is turned off.
begin
if(go_en = '0') then -- If go_en = 0 then clear the count
count <= (others => '0');
else
if rising_edge(iCLK) then -- else increment count at each clock cycle, when clock is on HIGH.
count <= count + 1;
end if;
end if;
end process;
-- Latch counting for the negative edges of clock
process(iCLK) -- Update negative count at falling clock edge
begin
if(falling_edge(iCLK)) then -- at clock on LOW.
n_count <= count; -- load count to n_count at each neg clock cycle
end if;
end process;
-- Loops through channels, returning the data
process(iCLK, go_en) -- ch_count will increment at each loop of count 0 to 15 of ADC reading.
begin
if(go_en = '0') then -- If go_en = 0 then reset the channel count
ch_count <= (others => '0');
else
if(falling_edge(iCLK)) then
if(count = 1) then
ch_reading <= ch_count;
if(ch_count < (NUM_CHANS)) then -- count ch_count up to at most 8 channels
ch_count <= ch_count+1;
else
ch_count <= (others => '0');
end if;
end if;
if (count = 2) then
data <= ch_count(2);
elsif (count = 3) then
data <= ch_count(1);
elsif (count = 4) then
data <= ch_count(0);
else
data <= '0';
end if;
end if;
end if;
end process;
-- Take in the ADC data as it gets clocked in on the negative edge
process(iCLK, go_en) -- Take in ADC bit stream
begin
if(go_en = '0') then -- If go_en is low, clear ADC data
adc_data <= (others => '1');
else
if(rising_edge(iCLK)) then -- At positive clock edge
-- retrieve ADC data from MSB to LSB
if (n_count = 4) then
adc_data(11) <= iADC_DATA;
elsif (n_count = 5) then
adc_data(10) <= iADC_DATA;
elsif (n_count = 6) then
adc_data(9) <= iADC_DATA;
elsif (n_count = 7) then
adc_data(8) <= iADC_DATA;
elsif (n_count = 8) then
adc_data(7) <= iADC_DATA;
elsif (n_count = 9) then
adc_data(6) <= iADC_DATA;
elsif (n_count = 10) then
adc_data(5) <= iADC_DATA;
elsif (n_count = 11) then
adc_data(4) <= iADC_DATA;
elsif (n_count = 12) then
adc_data(3) <= iADC_DATA;
elsif (n_count = 13) then
adc_data(2) <= iADC_DATA;
elsif (n_count = 14) then
adc_data(1) <= iADC_DATA;
elsif (n_count = 15) then
adc_data(0) <= iADC_DATA;
elsif (n_count = 0) then
-- update the ADC value and the channel information for the next cycle
prv_ch_read <= ch_reading;
prv_adc_data <= adc_data;
end if;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 25434bfc3982d6f3543eaaae067519fb | 0.589331 | 3.120767 | false | false | false | false |
AndyMcC0/UVVM_All | bitvis_irqc/src/irqc_pif_pkg.vhd | 3 | 3,063 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_pif_pkg
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package irqc_pif_pkg is
-- Change this to a generic when generic in packages is allowed (VHDL 2008)
constant C_NUM_SOURCES : integer := 6; -- 1 <= C_NUM_SOURCES <= Data width
-- Notation for regs: (Included in constant name as info to SW)
-- - RW: Readable and writable reg.
-- - RO: Read only reg. (output from IP)
-- - WO: Write only reg. (typically single cycle strobe to IP)
-- Notation for signals (or fields in record) going between PIF and core:
-- Same notations as for register-constants above, but
-- a preceeding 'a' (e.g. awo) means the register is auxiliary to the PIF.
-- This means no flop in the PIF, but in the core. (Or just a dummy-register with no flop)
constant C_ADDR_IRR : integer := 0;
constant C_ADDR_IER : integer := 1;
constant C_ADDR_ITR : integer := 2;
constant C_ADDR_ICR : integer := 3;
constant C_ADDR_IPR : integer := 4;
constant C_ADDR_IRQ2CPU_ENA : integer := 5;
constant C_ADDR_IRQ2CPU_DISABLE : integer := 6;
constant C_ADDR_IRQ2CPU_ALLOWED : integer := 7;
-- Signals from pif to core
type t_p2c is record
rw_ier : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_itr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_icr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_irq2cpu_ena : std_logic;
awt_irq2cpu_disable : std_logic;
end record t_p2c;
-- Signals from core to PIF
type t_c2p is record
aro_irr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
aro_ipr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
aro_irq2cpu_allowed : std_logic;
end record t_c2p;
end package irqc_pif_pkg;
| mit | b3ac85ab9934442afb145ae9d1e358bb | 0.572968 | 4.133603 | false | false | false | false |
ashtonchase/logic_analyzer | target_hardware/ZedBoard/zed_top.vhd | 1 | 6,103 | -------------------------------------------------------------------------------
-- Title : ZED Board Top Level
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : zed_top.vhd
-- Created : 2016-02-22
-- Last update: 2016-02-22
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: Xilinx Zynq 7000 on a Digilent Zed Board Top Level Module,
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-22 1.0 ashton Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY zed_top IS
PORT (
GCLK : in std_logic; -- 100 MHz clock
--LED Outputs
LD0, LD1, LD2, LD3, LD4, LD5, LD6, LD7 : out std_logic;
--Buttons
BTND : in std_logic;
--Temporary Data Ouput (JA10-JA7, JA4-JA1)
--JA10, JA9, JA8, JA7, JA4, JA3, JA2, JA1 : out std_logic;
--UART SIGNALS
JB4 : in std_logic := 'H'; --RX
JB1 : out std_logic; --TX
--Switches
SW7, SW6, SW5, SW4, SW3, SW2, SW1, SW0 : in std_logic
);
END ENTITY zed_top;
ARCHITECTURE top OF zed_top IS
-----------------------------------------------------------------------------
-- Components
-----------------------------------------------------------------------------
COMPONENT clock_gen
PORT
( -- Clock in ports
clk_in1 : IN STD_LOGIC;
-- Clock out ports
clk_out1 : OUT STD_LOGIC;
-- Status and control signals
reset : IN STD_LOGIC;
locked : OUT STD_LOGIC
);
END COMPONENT;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
SIGNAL reset : STD_LOGIC := '1'; -- reset (async high, sync low)
SIGNAL run_clk : STD_LOGIC := '0'; -- clock output of the clocking wizard
SIGNAL clk_locked : STD_LOGIC := '0'; -- indicator if the clocking wizard has locked
signal debug : std_logic_vector(7 downto 0);
-----------------------------------------------------------------------------
-- Aliases
-----------------------------------------------------------------------------
alias reset_btn : std_logic is BTND;
alias CLK : std_logic is GCLK;
alias UART_RX : std_logic is JB4;
signal UART_TX : std_logic;
BEGIN -- ARCHITECTURE top
LD3<=clk_locked;
LD7<=not UART_RX;--just activity indicator
LD6<=not UART_TX;--just activity indicator
JB1<=UART_TX;--send UART_TX out
-- Debug Testing
-- LD7 <= debug(7);
-- LD6 <= debug(6);
-- LD5 <= debug(5);
-- LD4 <= debug(4);
-- LD3 <= debug(3);
-- LD2 <= debug(2);
-- LD1 <= debug(1);
-- LD0 <= debug(0);
-----------------------------------------------------------------------------
-- Component Instatiations
-----------------------------------------------------------------------------
-- purpose: this component will generate the desired system clock based on
-- the 125 MHz input clock. Not the output is already downstream of a global
-- clock buffer
-- inputs : clk, reset
-- outputs: clk_locked
run_clk_component : clock_gen
PORT MAP (
-- Clock in ports
clk_in1 => clk,
-- Clock out ports
clk_out1 => run_clk,
-- Status and control signals
reset => reset_btn,
locked => clk_locked
);
-- purpose: this process will reset the system when btn0 is pressed
-- type : combinational
-- inputs : reset_btn, clk, clk_locked
-- outputs: reset
reset_proc : PROCESS (reset_btn, clk) IS
BEGIN -- PROCESS reset_proc
IF reset_btn = '1' THEN
reset <= '1';
ELSIF rising_edge(clk) THEN
reset <= '0';
END IF;
END PROCESS reset_proc;
la_top_inst : entity work.la_top
generic map (
BAUD_RATE => 115_200,
INPUT_CLK_RATE_HZ => 100_000_000,
DATA_WIDTH => 8,
SAMPLE_DEPTH => 2**17)
port map (
--COMMON INTERFACES
clk => run_clk,
rst => reset, --reset, (async high/ sync low)
--data input. default to zeros so you don't have to hook all 32 lines up.
din(31 downto 8) => (others => '0'),
din(7) => SW7,
din(6) => SW6,
din(5) => SW5,
din(4) => SW4,
din(3) => SW3,
din(2) => SW2,
din(1) => SW1,
din(0) => SW0,
--UART INTERFACES
uart_rx => UART_RX, -- UART Receive Data
uart_tx => UART_TX, -- UART Transmit Data
armed => LD1,
triggered => LD2,
capture_rdy=>LD0,
--data_sent=> LD5,
command_ready=> LD4,
debug=> debug);
LD5 <= '1';
END ARCHITECTURE top;
| gpl-2.0 | 7031fa286c4becc9fe7d602608f1a8ae | 0.461412 | 4.381192 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/Fault_injector.vhd | 3 | 1,297 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
--use IEEE.math_real."ceil";
--use IEEE.math_real."log2";
entity fault_injector is
generic(
DATA_WIDTH : integer := 32;
ADDRESS_WIDTH : integer := 5
);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector (ADDRESS_WIDTH-1 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end fault_injector;
architecture behavior of fault_injector is
signal mask: std_logic_vector (DATA_WIDTH-1 downto 0);
begin
-- data_in | sta_0 | sta_1 | data_out
-- --------|--------|--------|----------
-- 0 | 0 | 0 | 0
-- 1 | 0 | 0 | 1
-- X | 0 | 1 | 1
-- X | 1 | 0 | 0
process (address) begin
mask <= (others => '0');
mask(to_integer(unsigned(address))) <= '1';
end process;
Gen_faulty:
for i in 0 to DATA_WIDTH-1 generate
data_out(i) <= (not mask(i) and data_in(i)) or (mask(i) and not sta_0 and not sta_1 and data_in(i)) or (mask(i) and sta_1 and not sta_0) ;
--data_out(i) <= data_in(i);
end generate;
end; | gpl-3.0 | 56688004d84c874a385a7bb198c8b49d | 0.54202 | 2.825708 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/Allocator_with_checkers_with_FI/allocator_logic_pseudo_checkers.vhd | 3 | 23,756 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_logic_pseudo_checkers is
port (
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: in std_logic;
grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: in std_logic;
grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: in std_logic;
grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: in std_logic;
grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: in std_logic;
valid_N, valid_E, valid_W, valid_S, valid_L : in std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: in std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: in std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: in std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: in std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L : in std_logic;
-- Checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E, err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L, err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E, err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L, err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E, err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L, err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E, err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L, err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E, err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L, err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E, err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L, err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match : out std_logic
);
end allocator_logic_pseudo_checkers;
architecture behavior of allocator_logic_pseudo_checkers is
begin
-- The combionational part
-- Checkers
-- Grant_N checkers
process (grant_N_N_sig, empty_N, grant_N_N)
begin
err_grant_N_N_sig_not_empty_N_grant_N_N <= '0';
if (grant_N_N_sig = '1' and empty_N = '0' and grant_N_N = '0') then
err_grant_N_N_sig_not_empty_N_grant_N_N <= '1';
end if;
end process;
process (grant_N_N_sig, empty_N, grant_N_N)
begin
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N <= '0';
if ( (grant_N_N_sig = '0' or empty_N = '1') and grant_N_N = '1') then
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N <= '1';
end if;
end process;
process (grant_N_E_sig, empty_E, grant_N_E)
begin
err_grant_N_E_sig_not_empty_E_grant_N_E <= '0';
if (grant_N_E_sig = '1' and empty_E = '0' and grant_N_E = '0') then
err_grant_N_E_sig_not_empty_E_grant_N_E <= '1';
end if;
end process;
process (grant_N_E_sig, empty_E, grant_N_E)
begin
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E <= '0';
if ( (grant_N_E_sig = '0' or empty_E = '1') and grant_N_E = '1') then
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E <= '1';
end if;
end process;
process (grant_N_W_sig, empty_W, grant_N_W)
begin
err_grant_N_W_sig_not_empty_W_grant_N_W <= '0';
if (grant_N_W_sig = '1' and empty_W = '0' and grant_N_W = '0') then
err_grant_N_W_sig_not_empty_W_grant_N_W <= '1';
end if;
end process;
process (grant_N_W_sig, empty_W, grant_N_W)
begin
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W <= '0';
if ( (grant_N_W_sig = '0' or empty_W = '1') and grant_N_W = '1') then
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W <= '1';
end if;
end process;
process (grant_N_S_sig, empty_S, grant_N_S)
begin
err_grant_N_S_sig_not_empty_S_grant_N_S <= '0';
if (grant_N_S_sig = '1' and empty_S = '0' and grant_N_S = '0') then
err_grant_N_S_sig_not_empty_S_grant_N_S <= '1';
end if;
end process;
process (grant_N_S_sig, empty_S, grant_N_S)
begin
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S <= '0';
if ( (grant_N_S_sig = '0' or empty_S = '1') and grant_N_S = '1') then
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S <= '1';
end if;
end process;
process (grant_N_L_sig, empty_L, grant_N_L)
begin
err_grant_N_L_sig_not_empty_L_grant_N_L <= '0';
if (grant_N_L_sig = '1' and empty_L = '0' and grant_N_L = '0') then
err_grant_N_L_sig_not_empty_L_grant_N_L <= '1';
end if;
end process;
process (grant_N_L_sig, empty_L, grant_N_L)
begin
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L <= '0';
if ( (grant_N_L_sig = '0' or empty_L = '1') and grant_N_L = '1') then
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L <= '1';
end if;
end process;
----------------------------------------------------------------
-- Grant_E checkers
process (grant_E_N_sig, empty_N, grant_E_N)
begin
err_grant_E_N_sig_not_empty_N_grant_E_N <= '0';
if (grant_E_N_sig = '1' and empty_N = '0' and grant_E_N = '0') then
err_grant_E_N_sig_not_empty_N_grant_E_N <= '1';
end if;
end process;
process (grant_E_N_sig, empty_N, grant_E_N)
begin
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N <= '0';
if ( (grant_E_N_sig = '0' or empty_N = '1') and grant_E_N = '1') then
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N <= '1';
end if;
end process;
process (grant_E_E_sig, empty_E, grant_E_E)
begin
err_grant_E_E_sig_not_empty_E_grant_E_E <= '0';
if (grant_E_E_sig = '1' and empty_E = '0' and grant_E_E = '0') then
err_grant_E_E_sig_not_empty_E_grant_E_E <= '1';
end if;
end process;
process (grant_E_E_sig, empty_E, grant_E_E)
begin
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E <= '0';
if ( (grant_E_E_sig = '0' or empty_E = '1') and grant_E_E = '1') then
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E <= '1';
end if;
end process;
process (grant_E_W_sig, empty_W, grant_E_W)
begin
err_grant_E_W_sig_not_empty_W_grant_E_W <= '0';
if (grant_E_W_sig = '1' and empty_W = '0' and grant_E_W = '0') then
err_grant_E_W_sig_not_empty_W_grant_E_W <= '1';
end if;
end process;
process (grant_E_W_sig, empty_W, grant_E_W)
begin
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W <= '0';
if ( (grant_E_W_sig = '0' or empty_W = '1') and grant_E_W = '1') then
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W <= '1';
end if;
end process;
process (grant_E_S_sig, empty_S, grant_E_S)
begin
err_grant_E_S_sig_not_empty_S_grant_E_S <= '0';
if (grant_E_S_sig = '1' and empty_S = '0' and grant_E_S = '0') then
err_grant_E_S_sig_not_empty_S_grant_E_S <= '1';
end if;
end process;
process (grant_E_S_sig, empty_S, grant_E_S)
begin
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S <= '0';
if ( (grant_E_S_sig = '0' or empty_S = '1') and grant_E_S = '1') then
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S <= '1';
end if;
end process;
process (grant_E_L_sig, empty_L, grant_E_L)
begin
err_grant_E_L_sig_not_empty_L_grant_E_L <= '0';
if (grant_E_L_sig = '1' and empty_L = '0' and grant_E_L = '0') then
err_grant_E_L_sig_not_empty_L_grant_E_L <= '1';
end if;
end process;
process (grant_E_L_sig, empty_L, grant_E_L)
begin
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L <= '0';
if ( (grant_E_L_sig = '0' or empty_L = '1') and grant_E_L = '1') then
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L <= '1';
end if;
end process;
----------------------------------------------------------------
-- Grant_W checkers
process (grant_W_N_sig, empty_N, grant_W_N)
begin
err_grant_W_N_sig_not_empty_N_grant_W_N <= '0';
if (grant_W_N_sig = '1' and empty_N = '0' and grant_W_N = '0') then
err_grant_W_N_sig_not_empty_N_grant_W_N <= '1';
end if;
end process;
process (grant_W_N_sig, empty_N, grant_W_N)
begin
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N <= '0';
if ( (grant_W_N_sig = '0' or empty_N = '1') and grant_W_N = '1') then
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N <= '1';
end if;
end process;
process (grant_W_E_sig, empty_E, grant_W_E)
begin
err_grant_W_E_sig_not_empty_E_grant_W_E <= '0';
if (grant_W_E_sig = '1' and empty_E = '0' and grant_W_E = '0') then
err_grant_W_E_sig_not_empty_E_grant_W_E <= '1';
end if;
end process;
process (grant_W_E_sig, empty_E, grant_W_E)
begin
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E <= '0';
if ( (grant_W_E_sig = '0' or empty_E = '1') and grant_W_E = '1') then
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E <= '1';
end if;
end process;
process (grant_W_W_sig, empty_W, grant_W_W)
begin
err_grant_W_W_sig_not_empty_W_grant_W_W <= '0';
if (grant_W_W_sig = '1' and empty_W = '0' and grant_W_W = '0') then
err_grant_W_W_sig_not_empty_W_grant_W_W <= '1';
end if;
end process;
process (grant_W_W_sig, empty_W, grant_W_W)
begin
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W <= '0';
if ( (grant_W_W_sig = '0' or empty_W = '1') and grant_W_W = '1') then
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W <= '1';
end if;
end process;
process (grant_W_S_sig, empty_S, grant_W_S)
begin
err_grant_W_S_sig_not_empty_S_grant_W_S <= '0';
if (grant_W_S_sig = '1' and empty_S = '0' and grant_W_S = '0') then
err_grant_W_S_sig_not_empty_S_grant_W_S <= '1';
end if;
end process;
process (grant_W_S_sig, empty_S, grant_W_S)
begin
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S <= '0';
if ( (grant_W_S_sig = '0' or empty_S = '1') and grant_W_S = '1') then
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S <= '1';
end if;
end process;
process (grant_W_L_sig, empty_L, grant_W_L)
begin
err_grant_W_L_sig_not_empty_L_grant_W_L <= '0';
if (grant_W_L_sig = '1' and empty_L = '0' and grant_W_L = '0') then
err_grant_W_L_sig_not_empty_L_grant_W_L <= '1';
end if;
end process;
process (grant_W_L_sig, empty_L, grant_W_L)
begin
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L <= '0';
if ( (grant_W_L_sig = '0' or empty_L = '1') and grant_W_L = '1') then
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L <= '1';
end if;
end process;
----------------------------------------------------------------
-- Grant_S checkers
process (grant_S_N_sig, empty_N, grant_S_N)
begin
err_grant_S_N_sig_not_empty_N_grant_S_N <= '0';
if (grant_S_N_sig = '1' and empty_N = '0' and grant_S_N = '0') then
err_grant_S_N_sig_not_empty_N_grant_S_N <= '1';
end if;
end process;
process (grant_S_N_sig, empty_N, grant_S_N)
begin
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N <= '0';
if ( (grant_S_N_sig = '0' or empty_N = '1') and grant_S_N = '1') then
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N <= '1';
end if;
end process;
process (grant_S_E_sig, empty_E, grant_S_E)
begin
err_grant_S_E_sig_not_empty_E_grant_S_E <= '0';
if (grant_S_E_sig = '1' and empty_E = '0' and grant_S_E = '0') then
err_grant_S_E_sig_not_empty_E_grant_S_E <= '1';
end if;
end process;
process (grant_S_E_sig, empty_E, grant_S_E)
begin
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E <= '0';
if ( (grant_S_E_sig = '0' or empty_E = '1') and grant_S_E = '1') then
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E <= '1';
end if;
end process;
process (grant_S_W_sig, empty_W, grant_S_W)
begin
err_grant_S_W_sig_not_empty_W_grant_S_W <= '0';
if (grant_S_W_sig = '1' and empty_W = '0' and grant_S_W = '0') then
err_grant_S_W_sig_not_empty_W_grant_S_W <= '1';
end if;
end process;
process (grant_S_W_sig, empty_W, grant_S_W)
begin
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W <= '0';
if ( (grant_S_W_sig = '0' or empty_W = '1') and grant_S_W = '1') then
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W <= '1';
end if;
end process;
process (grant_S_S_sig, empty_S, grant_S_S)
begin
err_grant_S_S_sig_not_empty_S_grant_S_S <= '0';
if (grant_S_S_sig = '1' and empty_S = '0' and grant_S_S = '0') then
err_grant_S_S_sig_not_empty_S_grant_S_S <= '1';
end if;
end process;
process (grant_S_S_sig, empty_S, grant_S_S)
begin
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S <= '0';
if ( (grant_S_S_sig = '0' or empty_S = '1') and grant_S_S = '1') then
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S <= '1';
end if;
end process;
process (grant_S_L_sig, empty_L, grant_S_L)
begin
err_grant_S_L_sig_not_empty_L_grant_S_L <= '0';
if (grant_S_L_sig = '1' and empty_L = '0' and grant_S_L = '0') then
err_grant_S_L_sig_not_empty_L_grant_S_L <= '1';
end if;
end process;
process (grant_S_L_sig, empty_L, grant_S_L)
begin
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L <= '0';
if ( (grant_S_L_sig = '0' or empty_L = '1') and grant_S_L = '1') then
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L <= '1';
end if;
end process;
----------------------------------------------------------------
-- Grant_L checkers
process (grant_L_N_sig, empty_N, grant_L_N)
begin
err_grant_L_N_sig_not_empty_N_grant_L_N <= '0';
if (grant_L_N_sig = '1' and empty_N = '0' and grant_L_N = '0') then
err_grant_L_N_sig_not_empty_N_grant_L_N <= '1';
end if;
end process;
process (grant_L_N_sig, empty_N, grant_L_N)
begin
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N <= '0';
if ( (grant_L_N_sig = '0' or empty_N = '1') and grant_L_N = '1') then
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N <= '1';
end if;
end process;
process (grant_L_E_sig, empty_E, grant_L_E)
begin
err_grant_L_E_sig_not_empty_E_grant_L_E <= '0';
if (grant_L_E_sig = '1' and empty_E = '0' and grant_L_E = '0') then
err_grant_L_E_sig_not_empty_E_grant_L_E <= '1';
end if;
end process;
process (grant_L_E_sig, empty_E, grant_L_E)
begin
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E <= '0';
if ( (grant_L_E_sig = '0' or empty_E = '1') and grant_L_E = '1') then
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E <= '1';
end if;
end process;
process (grant_L_W_sig, empty_W, grant_L_W)
begin
err_grant_L_W_sig_not_empty_W_grant_L_W <= '0';
if (grant_L_W_sig = '1' and empty_W = '0' and grant_L_W = '0') then
err_grant_L_W_sig_not_empty_W_grant_L_W <= '1';
end if;
end process;
process (grant_L_W_sig, empty_W, grant_L_W)
begin
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W <= '0';
if ( (grant_L_W_sig = '0' or empty_W = '1') and grant_L_W = '1') then
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W <= '1';
end if;
end process;
process (grant_L_S_sig, empty_S, grant_L_S)
begin
err_grant_L_S_sig_not_empty_S_grant_L_S <= '0';
if (grant_L_S_sig = '1' and empty_S = '0' and grant_L_S = '0') then
err_grant_L_S_sig_not_empty_S_grant_L_S <= '1';
end if;
end process;
process (grant_L_S_sig, empty_S, grant_L_S)
begin
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S <= '0';
if ( (grant_L_S_sig = '0' or empty_S = '1') and grant_L_S = '1') then
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S <= '1';
end if;
end process;
process (grant_L_L_sig, empty_L, grant_L_L)
begin
err_grant_L_L_sig_not_empty_L_grant_L_L <= '0';
if (grant_L_L_sig = '1' and empty_L = '0' and grant_L_L = '0') then
err_grant_L_L_sig_not_empty_L_grant_L_L <= '1';
end if;
end process;
process (grant_L_L_sig, empty_L, grant_L_L)
begin
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L <= '0';
if ( (grant_L_L_sig = '0' or empty_L = '1') and grant_L_L = '1') then
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L <= '1';
end if;
end process;
----------------------------------------------------------------
-- Final Grant output checkers
-- North
process (grant_N_N_sig, empty_N, grant_N_E_sig, empty_E, grant_N_W_sig, empty_W, grant_N_S_sig, empty_S, grant_N_L_sig, empty_L, grant_N)
begin
err_grant_signals_not_empty_grant_N <= '0';
if ( ( (grant_N_N_sig = '1' and empty_N = '0' ) or (grant_N_E_sig = '1' and empty_E = '0') or (grant_N_W_sig = '1' and empty_W = '0') or
(grant_N_S_sig = '1' and empty_S = '0') or (grant_N_L_sig = '1' and empty_L = '0') ) and grant_N = '0' ) then
err_grant_signals_not_empty_grant_N <= '1';
end if;
end process;
process (grant_N_N_sig, empty_N, grant_N_E_sig, empty_E, grant_N_W_sig, empty_W, grant_N_S_sig, empty_S, grant_N_L_sig, empty_L, grant_N)
begin
err_not_grant_signals_empty_not_grant_N <= '0';
if ( ( (grant_N_N_sig = '0' or empty_N = '1' ) and (grant_N_E_sig = '0' and empty_E = '1') and (grant_N_W_sig = '0' or empty_W = '1') and
(grant_N_S_sig = '0' or empty_S = '1') and (grant_N_L_sig = '0' or empty_L = '1') ) and grant_N /= '0' ) then
err_not_grant_signals_empty_not_grant_N <= '1';
end if;
end process;
-- East
process (grant_E_N_sig, empty_N, grant_E_E_sig, empty_E, grant_E_W_sig, empty_W, grant_E_S_sig, empty_S, grant_E_L_sig, empty_L, grant_E)
begin
err_grant_signals_not_empty_grant_E <= '0';
if ( ( (grant_E_N_sig = '1' and empty_N = '0' ) or (grant_E_E_sig = '1' and empty_E = '0') or (grant_E_W_sig = '1' and empty_W = '0') or
(grant_E_S_sig = '1' and empty_S = '0') or (grant_E_L_sig = '1' and empty_L = '0') ) and grant_E = '0' ) then
err_grant_signals_not_empty_grant_E <= '1';
end if;
end process;
process (grant_E_N_sig, empty_N, grant_E_E_sig, empty_E, grant_E_W_sig, empty_W, grant_E_S_sig, empty_S, grant_E_L_sig, empty_L, grant_E)
begin
err_not_grant_signals_empty_not_grant_E <= '0';
if ( ( (grant_E_N_sig = '0' or empty_N = '1' ) and (grant_E_E_sig = '0' and empty_E = '1') and (grant_E_W_sig = '0' or empty_W = '1') and
(grant_E_S_sig = '0' or empty_S = '1') and (grant_E_L_sig = '0' or empty_L = '1') ) and grant_E /= '0' ) then
err_not_grant_signals_empty_not_grant_E <= '1';
end if;
end process;
-- West
process (grant_W_N_sig, empty_N, grant_W_E_sig, empty_E, grant_W_W_sig, empty_W, grant_W_S_sig, empty_S, grant_W_L_sig, empty_L, grant_W)
begin
err_grant_signals_not_empty_grant_W <= '0';
if ( ( (grant_W_N_sig = '1' and empty_N = '0' ) or (grant_W_E_sig = '1' and empty_E = '0') or (grant_W_W_sig = '1' and empty_W = '0') or
(grant_W_S_sig = '1' and empty_S = '0') or (grant_W_L_sig = '1' and empty_L = '0') ) and grant_W = '0' ) then
err_grant_signals_not_empty_grant_W <= '1';
end if;
end process;
process (grant_W_N_sig, empty_N, grant_W_E_sig, empty_E, grant_W_W_sig, empty_W, grant_W_S_sig, empty_S, grant_W_L_sig, empty_L, grant_W)
begin
err_not_grant_signals_empty_not_grant_W <= '0';
if ( ( (grant_W_N_sig = '0' or empty_N = '1' ) and (grant_W_E_sig = '0' and empty_E = '1') and (grant_W_W_sig = '0' or empty_W = '1') and
(grant_W_S_sig = '0' or empty_S = '1') and (grant_W_L_sig = '0' or empty_L = '1') ) and grant_W /= '0' ) then
err_not_grant_signals_empty_not_grant_W <= '1';
end if;
end process;
-- South
process (grant_S_N_sig, empty_N, grant_S_E_sig, empty_E, grant_S_W_sig, empty_W, grant_S_S_sig, empty_S, grant_S_L_sig, empty_L, grant_S)
begin
err_grant_signals_not_empty_grant_S <= '0';
if ( ( (grant_S_N_sig = '1' and empty_N = '0' ) or (grant_S_E_sig = '1' and empty_E = '0') or (grant_S_W_sig = '1' and empty_W = '0') or
(grant_S_S_sig = '1' and empty_S = '0') or (grant_S_L_sig = '1' and empty_L = '0') ) and grant_S = '0' ) then
err_grant_signals_not_empty_grant_S <= '1';
end if;
end process;
process (grant_S_N_sig, empty_N, grant_S_E_sig, empty_E, grant_S_W_sig, empty_W, grant_S_S_sig, empty_S, grant_S_L_sig, empty_L, grant_S)
begin
err_not_grant_signals_empty_not_grant_S <= '0';
if ( ( (grant_S_N_sig = '0' or empty_N = '1' ) and (grant_S_E_sig = '0' and empty_E = '1') and (grant_S_W_sig = '0' or empty_W = '1') and
(grant_S_S_sig = '0' or empty_S = '1') and (grant_S_L_sig = '0' or empty_L = '1') ) and grant_S /= '0' ) then
err_not_grant_signals_empty_not_grant_S <= '1';
end if;
end process;
-- Local
process (grant_L_N_sig, empty_N, grant_L_E_sig, empty_E, grant_L_W_sig, empty_W, grant_L_S_sig, empty_S, grant_L_L_sig, empty_L, grant_L)
begin
err_grant_signals_not_empty_grant_L <= '0';
if ( ( (grant_L_N_sig = '1' and empty_N = '0' ) or (grant_L_E_sig = '1' and empty_E = '0') or (grant_L_W_sig = '1' and empty_W = '0') or
(grant_L_S_sig = '1' and empty_S = '0') or (grant_L_L_sig = '1' and empty_L = '0') ) and grant_L = '0' ) then
err_grant_signals_not_empty_grant_L <= '1';
end if;
end process;
process (grant_L_N_sig, empty_N, grant_L_E_sig, empty_E, grant_L_W_sig, empty_W, grant_L_S_sig, empty_S, grant_L_L_sig, empty_L, grant_L)
begin
err_not_grant_signals_empty_not_grant_L <= '0';
if ( ( (grant_L_N_sig = '0' or empty_N = '1' ) and (grant_L_E_sig = '0' and empty_E = '1') and (grant_L_W_sig = '0' or empty_W = '1') and
(grant_L_S_sig = '0' or empty_S = '1') and (grant_L_L_sig = '0' or empty_L = '1') ) and grant_L /= '0' ) then
err_not_grant_signals_empty_not_grant_L <= '1';
end if;
end process;
----------------------------------------------------------------
-- Valid output checkers
process (valid_N, valid_E, valid_W, valid_S, valid_L, grant_N, grant_E, grant_W, grant_S, grant_L)
begin
err_grants_valid_not_match <= '0';
if (valid_N /= grant_N or valid_E /= grant_E or valid_W /= grant_W or valid_S /= grant_S or valid_L /= grant_L) then
err_grants_valid_not_match <= '1';
end if;
end process;
END;
| gpl-3.0 | ef922d18906c1e96484937d5bf0cb33d | 0.588315 | 2.222472 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/ram_xilinx.vhd | 3 | 181,451 | ---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1);
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
| gpl-3.0 | ca2bb997b69daa23bccbbb0eaad31d68 | 0.843319 | 6.986946 | false | false | false | false |
camacazio/de0_nano_DAC | DE0_12bitDAC_controller/dac_pll.vhd | 1 | 14,822 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: dac_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dac_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END dac_pll;
ARCHITECTURE SYN OF dac_pll IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire2_bv(0 DOWNTO 0) <= "0";
sub_wire2 <= To_stdlogicvector(sub_wire2_bv);
sub_wire0 <= inclk0;
sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0;
sub_wire4 <= sub_wire3(0);
c0 <= sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 25,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=dac_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire1,
clk => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "25"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "dac_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dac_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dac_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dac_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dac_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dac_pll.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dac_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-3.0 | b33b17d968a441ddda754821691c557f | 0.70004 | 3.369402 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/Router_32_bit_credit_based_packet_drop_classifier_SHMU_will_full_set_of_checkers.vhd | 3 | 499,404 | --Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
use work.component_pack.all;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI (Outputs for classified fault information)
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
---- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
---- Outputs for non-classified fault information
--link_faults_async: out std_logic_vector(4 downto 0);
--turn_faults_async: out std_logic_vector(19 downto 0)
);
end router_credit_based_PD_C_SHMU;
architecture behavior of router_credit_based_PD_C_SHMU is
-------------------------------
-- Added because of Checkers --
-------------------------------
--signal combined_error_signals: std_logic_vector(19 downto 0); -- Shall we only consider this for the 20 bits showing the turn faults or individual checkers ?!
--signal shift_parallel_data: std_logic_vector(19 downto 0);
-------------------------------
-------------------------------
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal LBDR_Fault_N, LBDR_Fault_E, LBDR_Fault_W, LBDR_Fault_S, LBDR_Fault_L: std_logic;
signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic;
-- Signals related to link fault classification modules
signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic;
signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic;
signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic;
-- Signals related to Control part checkers fault classification modules
signal Healthy_N2E_turn_fault, intermittent_N2E_turn_fault, faulty_N2E_turn_fault: std_logic;
signal Healthy_N2W_turn_fault, intermittent_N2W_turn_fault, faulty_N2W_turn_fault: std_logic;
signal Healthy_E2N_turn_fault, intermittent_E2N_turn_fault, faulty_E2N_turn_fault: std_logic;
signal Healthy_E2S_turn_fault, intermittent_E2S_turn_fault, faulty_E2S_turn_fault: std_logic;
signal Healthy_W2N_turn_fault, intermittent_W2N_turn_fault, faulty_W2N_turn_fault: std_logic;
signal Healthy_W2S_turn_fault, intermittent_W2S_turn_fault, faulty_W2S_turn_fault: std_logic;
signal Healthy_S2E_turn_fault, intermittent_S2E_turn_fault, faulty_S2E_turn_fault: std_logic;
signal Healthy_S2W_turn_fault, intermittent_S2W_turn_fault, faulty_S2W_turn_fault: std_logic;
signal Healthy_N2S_path_fault, intermittent_N2S_path_fault, faulty_N2S_path_fault: std_logic;
signal Healthy_S2N_path_fault, intermittent_S2N_path_fault, faulty_S2N_path_fault: std_logic;
signal Healthy_E2W_path_fault, intermittent_E2W_path_fault, faulty_E2W_path_fault: std_logic;
signal Healthy_W2E_path_fault, intermittent_W2E_path_fault, faulty_W2E_path_fault: std_logic;
signal Healthy_L2N_fault, intermittent_L2N_fault, faulty_L2N_fault: std_logic;
signal Healthy_L2E_fault, intermittent_L2E_fault, faulty_L2E_fault: std_logic;
signal Healthy_L2W_fault, intermittent_L2W_fault, faulty_L2W_fault: std_logic;
signal Healthy_L2S_fault, intermittent_L2S_fault, faulty_L2S_fault: std_logic;
signal Healthy_N2L_fault, intermittent_N2L_fault, faulty_N2L_fault: std_logic;
signal Healthy_E2L_fault, intermittent_E2L_fault, faulty_E2L_fault: std_logic;
signal Healthy_W2L_fault, intermittent_W2L_fault, faulty_W2L_fault: std_logic;
signal Healthy_S2L_fault, intermittent_S2L_fault, faulty_S2L_fault: std_logic;
-- Signals needed for control part checkers
-- Signals needed for LBDR packet drop checkers
-- North
signal N_err_header_empty_Requests_FF_Requests_in,
N_err_tail_Requests_in_all_zero,
N_err_tail_empty_Requests_FF_Requests_in,
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
N_err_grants_onehot,
N_err_grants_mismatch,
N_err_header_tail_Requests_FF_Requests_in,
N_err_dst_addr_cur_addr_N1,
N_err_dst_addr_cur_addr_not_N1,
N_err_dst_addr_cur_addr_E1,
N_err_dst_addr_cur_addr_not_E1,
N_err_dst_addr_cur_addr_W1,
N_err_dst_addr_cur_addr_not_W1,
N_err_dst_addr_cur_addr_S1,
N_err_dst_addr_cur_addr_not_S1,
N_err_dst_addr_cur_addr_Req_L_in,
N_err_dst_addr_cur_addr_not_Req_L_in,
N_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
N_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--N_err_header_not_empty_Req_L_in, -- added according to new design
N_err_header_not_empty_Req_N_in,
N_err_header_not_empty_Req_E_in,
N_err_header_not_empty_Req_W_in,
N_err_header_not_empty_Req_S_in,
N_err_header_empty_packet_drop_in_packet_drop_equal,
N_err_tail_not_empty_packet_drop_not_packet_drop_in,
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
N_err_packet_drop_order,
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal,
-- East
E_err_header_empty_Requests_FF_Requests_in,
E_err_tail_Requests_in_all_zero,
E_err_tail_empty_Requests_FF_Requests_in,
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
E_err_grants_onehot,
E_err_grants_mismatch,
E_err_header_tail_Requests_FF_Requests_in,
E_err_dst_addr_cur_addr_N1,
E_err_dst_addr_cur_addr_not_N1,
E_err_dst_addr_cur_addr_E1,
E_err_dst_addr_cur_addr_not_E1,
E_err_dst_addr_cur_addr_W1,
E_err_dst_addr_cur_addr_not_W1,
E_err_dst_addr_cur_addr_S1,
E_err_dst_addr_cur_addr_not_S1,
E_err_dst_addr_cur_addr_Req_L_in,
E_err_dst_addr_cur_addr_not_Req_L_in,
E_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
E_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--E_err_header_not_empty_Req_L_in, -- added according to new design
E_err_header_not_empty_Req_N_in,
E_err_header_not_empty_Req_E_in,
E_err_header_not_empty_Req_W_in,
E_err_header_not_empty_Req_S_in,
E_err_header_empty_packet_drop_in_packet_drop_equal,
E_err_tail_not_empty_packet_drop_not_packet_drop_in,
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
E_err_packet_drop_order,
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal,
-- West
W_err_header_empty_Requests_FF_Requests_in,
W_err_tail_Requests_in_all_zero,
W_err_tail_empty_Requests_FF_Requests_in,
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
W_err_grants_onehot,
W_err_grants_mismatch,
W_err_header_tail_Requests_FF_Requests_in,
W_err_dst_addr_cur_addr_N1,
W_err_dst_addr_cur_addr_not_N1,
W_err_dst_addr_cur_addr_E1,
W_err_dst_addr_cur_addr_not_E1,
W_err_dst_addr_cur_addr_W1,
W_err_dst_addr_cur_addr_not_W1,
W_err_dst_addr_cur_addr_S1,
W_err_dst_addr_cur_addr_not_S1,
W_err_dst_addr_cur_addr_Req_L_in,
W_err_dst_addr_cur_addr_not_Req_L_in,
W_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
W_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--W_err_header_not_empty_Req_L_in, -- added according to new design
W_err_header_not_empty_Req_N_in,
W_err_header_not_empty_Req_E_in,
W_err_header_not_empty_Req_W_in,
W_err_header_not_empty_Req_S_in,
W_err_header_empty_packet_drop_in_packet_drop_equal,
W_err_tail_not_empty_packet_drop_not_packet_drop_in,
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
W_err_packet_drop_order,
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal,
-- South
S_err_header_empty_Requests_FF_Requests_in,
S_err_tail_Requests_in_all_zero,
S_err_tail_empty_Requests_FF_Requests_in,
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
S_err_grants_onehot,
S_err_grants_mismatch,
S_err_header_tail_Requests_FF_Requests_in,
S_err_dst_addr_cur_addr_N1,
S_err_dst_addr_cur_addr_not_N1,
S_err_dst_addr_cur_addr_E1,
S_err_dst_addr_cur_addr_not_E1,
S_err_dst_addr_cur_addr_W1,
S_err_dst_addr_cur_addr_not_W1,
S_err_dst_addr_cur_addr_S1,
S_err_dst_addr_cur_addr_not_S1,
S_err_dst_addr_cur_addr_Req_L_in,
S_err_dst_addr_cur_addr_not_Req_L_in,
S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--S_err_header_not_empty_Req_L_in, -- added according to new design
S_err_header_not_empty_Req_N_in,
S_err_header_not_empty_Req_E_in,
S_err_header_not_empty_Req_W_in,
S_err_header_not_empty_Req_S_in,
S_err_header_empty_packet_drop_in_packet_drop_equal,
S_err_tail_not_empty_packet_drop_not_packet_drop_in,
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
S_err_packet_drop_order,
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal,
-- Local
L_err_header_empty_Requests_FF_Requests_in,
L_err_tail_Requests_in_all_zero,
L_err_tail_empty_Requests_FF_Requests_in,
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
L_err_grants_onehot,
L_err_grants_mismatch,
L_err_header_tail_Requests_FF_Requests_in,
L_err_dst_addr_cur_addr_N1,
L_err_dst_addr_cur_addr_not_N1,
L_err_dst_addr_cur_addr_E1,
L_err_dst_addr_cur_addr_not_E1,
L_err_dst_addr_cur_addr_W1,
L_err_dst_addr_cur_addr_not_W1,
L_err_dst_addr_cur_addr_S1,
L_err_dst_addr_cur_addr_not_S1,
L_err_dst_addr_cur_addr_Req_L_in,
L_err_dst_addr_cur_addr_not_Req_L_in,
L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--L_err_header_not_empty_Req_L_in, -- added according to new design
L_err_header_not_empty_Req_N_in,
L_err_header_not_empty_Req_E_in,
L_err_header_not_empty_Req_W_in,
L_err_header_not_empty_Req_S_in,
L_err_header_empty_packet_drop_in_packet_drop_equal,
L_err_tail_not_empty_packet_drop_not_packet_drop_in,
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
L_err_packet_drop_order,
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal: std_logic;
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- Signals needed for FIFO packet drop with fault classifier support checkers
-- North
-- Functional checkers
signal N_err_empty_full, N_err_empty_read_en, N_err_full_write_en, N_err_state_in_onehot, N_err_read_pointer_in_onehot, N_err_write_pointer_in_onehot,
-- Structural checkers
N_err_write_en_write_pointer, N_err_not_write_en_write_pointer, N_err_read_pointer_write_pointer_not_empty, N_err_read_pointer_write_pointer_empty,
N_err_read_pointer_write_pointer_not_full, N_err_read_pointer_write_pointer_full, N_err_read_pointer_increment, N_err_read_pointer_not_increment,
N_err_write_en, N_err_not_write_en, N_err_not_write_en1, N_err_not_write_en2, N_err_read_en_mismatch, N_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
N_err_fake_credit_read_en_fake_credit_counter_in_increment,
N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
N_err_fake_credit_read_en_credit_out,
N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
N_err_state_out_Idle_not_fault_out_not_fake_credit,
N_err_state_out_Idle_not_fault_out_not_fault_info_in,
N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
N_err_state_out_Idle_fault_out_fake_credit,
N_err_state_out_Idle_fault_out_state_in_Packet_drop,
N_err_state_out_Idle_fault_out_fault_info_in,
N_err_state_out_Idle_fault_out_faulty_packet_in,
N_err_state_out_Idle_not_health_info,
N_err_state_out_Idle_not_write_fake_flit,
N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
N_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
N_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
N_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
N_err_state_out_Body_flit_valid_in_not_health_info,
N_err_state_out_Body_flit_not_fake_credit,
N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
N_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
N_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
N_err_state_out_Tail_flit_not_write_fake_flit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
N_err_fault_info_fault_info_out_equal,
N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in,
-- East
-- Functional checkers
E_err_empty_full, E_err_empty_read_en, E_err_full_write_en, E_err_state_in_onehot, E_err_read_pointer_in_onehot, E_err_write_pointer_in_onehot,
-- Structural checkers
E_err_write_en_write_pointer, E_err_not_write_en_write_pointer, E_err_read_pointer_write_pointer_not_empty, E_err_read_pointer_write_pointer_empty,
E_err_read_pointer_write_pointer_not_full, E_err_read_pointer_write_pointer_full, E_err_read_pointer_increment, E_err_read_pointer_not_increment,
E_err_write_en, E_err_not_write_en, E_err_not_write_en1, E_err_not_write_en2, E_err_read_en_mismatch, E_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
E_err_fake_credit_read_en_fake_credit_counter_in_increment,
E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
E_err_fake_credit_read_en_credit_out,
E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
E_err_state_out_Idle_not_fault_out_not_fake_credit,
E_err_state_out_Idle_not_fault_out_not_fault_info_in,
E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
E_err_state_out_Idle_fault_out_fake_credit,
E_err_state_out_Idle_fault_out_state_in_Packet_drop,
E_err_state_out_Idle_fault_out_fault_info_in,
E_err_state_out_Idle_fault_out_faulty_packet_in,
E_err_state_out_Idle_not_health_info,
E_err_state_out_Idle_not_write_fake_flit,
E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
E_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
E_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
E_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
E_err_state_out_Body_flit_valid_in_not_health_info,
E_err_state_out_Body_flit_not_fake_credit,
E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
E_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
E_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
E_err_state_out_Tail_flit_not_write_fake_flit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
E_err_fault_info_fault_info_out_equal,
E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in,
-- West
-- Functional checkers
W_err_empty_full, W_err_empty_read_en, W_err_full_write_en, W_err_state_in_onehot, W_err_read_pointer_in_onehot, W_err_write_pointer_in_onehot,
-- Structural checkers
W_err_write_en_write_pointer, W_err_not_write_en_write_pointer, W_err_read_pointer_write_pointer_not_empty, W_err_read_pointer_write_pointer_empty,
W_err_read_pointer_write_pointer_not_full, W_err_read_pointer_write_pointer_full, W_err_read_pointer_increment, W_err_read_pointer_not_increment,
W_err_write_en, W_err_not_write_en, W_err_not_write_en1, W_err_not_write_en2, W_err_read_en_mismatch, W_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
W_err_fake_credit_read_en_fake_credit_counter_in_increment,
W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
W_err_fake_credit_read_en_credit_out,
W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
W_err_state_out_Idle_not_fault_out_not_fake_credit,
W_err_state_out_Idle_not_fault_out_not_fault_info_in,
W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
W_err_state_out_Idle_fault_out_fake_credit,
W_err_state_out_Idle_fault_out_state_in_Packet_drop,
W_err_state_out_Idle_fault_out_fault_info_in,
W_err_state_out_Idle_fault_out_faulty_packet_in,
W_err_state_out_Idle_not_health_info,
W_err_state_out_Idle_not_write_fake_flit,
W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
W_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
W_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
W_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
W_err_state_out_Body_flit_valid_in_not_health_info,
W_err_state_out_Body_flit_not_fake_credit,
W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
W_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
W_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
W_err_state_out_Tail_flit_not_write_fake_flit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
W_err_fault_info_fault_info_out_equal,
W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in,
-- South
-- Functional checkers
S_err_empty_full, S_err_empty_read_en, S_err_full_write_en, S_err_state_in_onehot, S_err_read_pointer_in_onehot, S_err_write_pointer_in_onehot,
-- Structural checkers
S_err_write_en_write_pointer, S_err_not_write_en_write_pointer, S_err_read_pointer_write_pointer_not_empty, S_err_read_pointer_write_pointer_empty,
S_err_read_pointer_write_pointer_not_full, S_err_read_pointer_write_pointer_full, S_err_read_pointer_increment, S_err_read_pointer_not_increment,
S_err_write_en, S_err_not_write_en, S_err_not_write_en1, S_err_not_write_en2, S_err_read_en_mismatch, S_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
S_err_fake_credit_read_en_fake_credit_counter_in_increment,
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
S_err_fake_credit_read_en_credit_out,
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
S_err_state_out_Idle_not_fault_out_not_fake_credit,
S_err_state_out_Idle_not_fault_out_not_fault_info_in,
S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
S_err_state_out_Idle_fault_out_fake_credit,
S_err_state_out_Idle_fault_out_state_in_Packet_drop,
S_err_state_out_Idle_fault_out_fault_info_in,
S_err_state_out_Idle_fault_out_faulty_packet_in,
S_err_state_out_Idle_not_health_info,
S_err_state_out_Idle_not_write_fake_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
S_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
S_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
S_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
S_err_state_out_Body_flit_valid_in_not_health_info,
S_err_state_out_Body_flit_not_fake_credit,
S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
S_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
S_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
S_err_state_out_Tail_flit_not_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
S_err_fault_info_fault_info_out_equal,
S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in,
-- Local
-- Functional checkers
L_err_empty_full, L_err_empty_read_en, L_err_full_write_en, L_err_state_in_onehot, L_err_read_pointer_in_onehot, L_err_write_pointer_in_onehot,
-- Structural checkers
L_err_write_en_write_pointer, L_err_not_write_en_write_pointer, L_err_read_pointer_write_pointer_not_empty,
L_err_read_pointer_write_pointer_empty, L_err_read_pointer_write_pointer_not_full, L_err_read_pointer_write_pointer_full,
L_err_read_pointer_increment, L_err_read_pointer_not_increment, L_err_write_en, L_err_not_write_en, L_err_not_write_en1,
L_err_not_write_en2, L_err_read_en_mismatch, L_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
L_err_fake_credit_read_en_fake_credit_counter_in_increment,
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
L_err_fake_credit_read_en_credit_out,
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
L_err_state_out_Idle_not_fault_out_not_fake_credit,
L_err_state_out_Idle_not_fault_out_not_fault_info_in,
L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
L_err_state_out_Idle_fault_out_fake_credit,
L_err_state_out_Idle_fault_out_state_in_Packet_drop,
L_err_state_out_Idle_fault_out_fault_info_in,
L_err_state_out_Idle_fault_out_faulty_packet_in,
L_err_state_out_Idle_not_health_info,
L_err_state_out_Idle_not_write_fake_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
L_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
L_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
L_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
L_err_state_out_Body_flit_valid_in_not_health_info,
L_err_state_out_Body_flit_not_fake_credit,
L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
L_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
L_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
L_err_state_out_Tail_flit_not_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
L_err_fault_info_fault_info_out_equal,
L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in: std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Signals needed for Allocator unit
-- Allocator logic checker outputs
signal err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E, err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L, err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E, err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L, err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E, err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L, err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E, err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L, err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E, err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L, err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E, err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L, err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match: std_logic;
-- Allocator credit_counter logic checker outputs
signal err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Arbiter_in Checker signals (part of allocator unit)
-- North Arbiter_in checker outputs
signal N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N, N_err_IDLE_grant_N,N_err_North_Req_N, N_err_North_grant_N, N_err_East_Req_E, N_err_East_grant_E, N_err_West_Req_W,
N_err_West_grant_W, N_err_South_Req_S,N_err_South_grant_S,N_err_Local_Req_L, N_err_Local_grant_L,
N_err_IDLE_Req_E, N_err_IDLE_grant_E, N_err_North_Req_E, N_err_North_grant_E, N_err_East_Req_W, N_err_East_grant_W, N_err_West_Req_S,
N_err_West_grant_S, N_err_South_Req_L, N_err_South_grant_L, N_err_Local_Req_N, N_err_Local_grant_N,
N_err_IDLE_Req_W, N_err_IDLE_grant_W, N_err_North_Req_W, N_err_North_grant_W, N_err_East_Req_S, N_err_East_grant_S, N_err_West_Req_L,
N_err_West_grant_L, N_err_South_Req_N, N_err_South_grant_N, N_err_Local_Req_E, N_err_Local_grant_E,
N_err_IDLE_Req_S, N_err_IDLE_grant_S, N_err_North_Req_S, N_err_North_grant_S, N_err_East_Req_L, N_err_East_grant_L, N_err_West_Req_N,
N_err_West_grant_N, N_err_South_Req_E, N_err_South_grant_E, N_err_Local_Req_W, N_err_Local_grant_W,
N_err_IDLE_Req_L, N_err_IDLE_grant_L, N_err_North_Req_L, N_err_North_grant_L, N_err_East_Req_N, N_err_East_grant_N, N_err_West_Req_E,
N_err_West_grant_E, N_err_South_Req_W, N_err_South_grant_W, N_err_Local_Req_S, N_err_Local_grant_S,
N_err_arbiter_state_in_onehot, N_err_no_request_grants, N_err_request_no_grants,
N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L,
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N, E_err_IDLE_grant_N, E_err_North_Req_N, E_err_North_grant_N, E_err_East_Req_E, E_err_East_grant_E, E_err_West_Req_W,
E_err_West_grant_W, E_err_South_Req_S, E_err_South_grant_S, E_err_Local_Req_L, E_err_Local_grant_L,
E_err_IDLE_Req_E, E_err_IDLE_grant_E, E_err_North_Req_E, E_err_North_grant_E, E_err_East_Req_W, E_err_East_grant_W, E_err_West_Req_S,
E_err_West_grant_S, E_err_South_Req_L, E_err_South_grant_L, E_err_Local_Req_N, E_err_Local_grant_N,
E_err_IDLE_Req_W, E_err_IDLE_grant_W, E_err_North_Req_W, E_err_North_grant_W, E_err_East_Req_S, E_err_East_grant_S, E_err_West_Req_L,
E_err_West_grant_L, E_err_South_Req_N, E_err_South_grant_N, E_err_Local_Req_E, E_err_Local_grant_E,
E_err_IDLE_Req_S, E_err_IDLE_grant_S, E_err_North_Req_S, E_err_North_grant_S, E_err_East_Req_L, E_err_East_grant_L, E_err_West_Req_N,
E_err_West_grant_N, E_err_South_Req_E, E_err_South_grant_E, E_err_Local_Req_W, E_err_Local_grant_W,
E_err_IDLE_Req_L, E_err_IDLE_grant_L, E_err_North_Req_L, E_err_North_grant_L, E_err_East_Req_N, E_err_East_grant_N, E_err_West_Req_E,
E_err_West_grant_E, E_err_South_Req_W, E_err_South_grant_W, E_err_Local_Req_S, E_err_Local_grant_S,
E_err_arbiter_state_in_onehot, E_err_no_request_grants, E_err_request_no_grants,
E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L,
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N, W_err_IDLE_grant_N, W_err_North_Req_N, W_err_North_grant_N, W_err_East_Req_E, W_err_East_grant_E, W_err_West_Req_W,
W_err_West_grant_W, W_err_South_Req_S, W_err_South_grant_S, W_err_Local_Req_L, W_err_Local_grant_L,
W_err_IDLE_Req_E, W_err_IDLE_grant_E, W_err_North_Req_E, W_err_North_grant_E, W_err_East_Req_W, W_err_East_grant_W, W_err_West_Req_S,
W_err_West_grant_S, W_err_South_Req_L, W_err_South_grant_L, W_err_Local_Req_N, W_err_Local_grant_N,
W_err_IDLE_Req_W, W_err_IDLE_grant_W, W_err_North_Req_W, W_err_North_grant_W, W_err_East_Req_S, W_err_East_grant_S, W_err_West_Req_L,
W_err_West_grant_L, W_err_South_Req_N, W_err_South_grant_N, W_err_Local_Req_E, W_err_Local_grant_E,
W_err_IDLE_Req_S, W_err_IDLE_grant_S, W_err_North_Req_S, W_err_North_grant_S, W_err_East_Req_L, W_err_East_grant_L, W_err_West_Req_N,
W_err_West_grant_N, W_err_South_Req_E, W_err_South_grant_E, W_err_Local_Req_W, W_err_Local_grant_W,
W_err_IDLE_Req_L, W_err_IDLE_grant_L, W_err_North_Req_L, W_err_North_grant_L, W_err_East_Req_N, W_err_East_grant_N, W_err_West_Req_E,
W_err_West_grant_E, W_err_South_Req_W, W_err_South_grant_W, W_err_Local_Req_S, W_err_Local_grant_S,
W_err_arbiter_state_in_onehot, W_err_no_request_grants, W_err_request_no_grants,
W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L,
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N, S_err_IDLE_grant_N,S_err_North_Req_N, S_err_North_grant_N, S_err_East_Req_E, S_err_East_grant_E, S_err_West_Req_W,
S_err_West_grant_W, S_err_South_Req_S,S_err_South_grant_S,S_err_Local_Req_L, S_err_Local_grant_L,
S_err_IDLE_Req_E, S_err_IDLE_grant_E, S_err_North_Req_E, S_err_North_grant_E, S_err_East_Req_W, S_err_East_grant_W, S_err_West_Req_S,
S_err_West_grant_S, S_err_South_Req_L, S_err_South_grant_L, S_err_Local_Req_N, S_err_Local_grant_N,
S_err_IDLE_Req_W, S_err_IDLE_grant_W, S_err_North_Req_W, S_err_North_grant_W, S_err_East_Req_S, S_err_East_grant_S, S_err_West_Req_L,
S_err_West_grant_L, S_err_South_Req_N, S_err_South_grant_N, S_err_Local_Req_E, S_err_Local_grant_E,
S_err_IDLE_Req_S, S_err_IDLE_grant_S, S_err_North_Req_S, S_err_North_grant_S, S_err_East_Req_L, S_err_East_grant_L, S_err_West_Req_N,
S_err_West_grant_N, S_err_South_Req_E, S_err_South_grant_E, S_err_Local_Req_W, S_err_Local_grant_W,
S_err_IDLE_Req_L, S_err_IDLE_grant_L, S_err_North_Req_L, S_err_North_grant_L, S_err_East_Req_N, S_err_East_grant_N, S_err_West_Req_E,
S_err_West_grant_E, S_err_South_Req_W, S_err_South_grant_W, S_err_Local_Req_S, S_err_Local_grant_S,
S_err_arbiter_state_in_onehot, S_err_no_request_grants, S_err_request_no_grants,
S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L,
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N, L_err_IDLE_grant_N,L_err_North_Req_N, L_err_North_grant_N, L_err_East_Req_E,
L_err_East_grant_E, L_err_West_Req_W, L_err_West_grant_W, L_err_South_Req_S,L_err_South_grant_S,
L_err_Local_Req_L, L_err_Local_grant_L,
L_err_IDLE_Req_E, L_err_IDLE_grant_E, L_err_North_Req_E, L_err_North_grant_E, L_err_East_Req_W,
L_err_East_grant_W, L_err_West_Req_S, L_err_West_grant_S, L_err_South_Req_L, L_err_South_grant_L,
L_err_Local_Req_N, L_err_Local_grant_N,
L_err_IDLE_Req_W, L_err_IDLE_grant_W, L_err_North_Req_W, L_err_North_grant_W, L_err_East_Req_S,
L_err_East_grant_S, L_err_West_Req_L, L_err_West_grant_L, L_err_South_Req_N, L_err_South_grant_N,
L_err_Local_Req_E, L_err_Local_grant_E,
L_err_IDLE_Req_S, L_err_IDLE_grant_S, L_err_North_Req_S, L_err_North_grant_S, L_err_East_Req_L,
L_err_East_grant_L, L_err_West_Req_N, L_err_West_grant_N, L_err_South_Req_E, L_err_South_grant_E,
L_err_Local_Req_W, L_err_Local_grant_W,
L_err_IDLE_Req_L, L_err_IDLE_grant_L, L_err_North_Req_L, L_err_North_grant_L, L_err_East_Req_N,
L_err_East_grant_N, L_err_West_Req_E, L_err_West_grant_E, L_err_South_Req_W, L_err_South_grant_W,
L_err_Local_Req_S, L_err_Local_grant_S,
L_err_arbiter_state_in_onehot, L_err_no_request_grants, L_err_request_no_grants,
L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S,
L_err_no_Req_L_grant_L : std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Arbiter_out Checker signals (part of allocator unit)
-- North Arbiter_out checker outputs
signal N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N,
N_err_North_req_X_N,
N_err_North_credit_not_zero_req_X_N_grant_N,
N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E,
N_err_East_credit_not_zero_req_X_E_grant_E,
N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
N_err_West_req_X_W,
N_err_West_credit_not_zero_req_X_W_grant_W,
N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
N_err_South_req_X_S,
N_err_South_credit_not_zero_req_X_S_grant_S,
N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
N_err_Local_req_X_L,
N_err_Local_credit_not_zero_req_X_L_grant_L,
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E, N_err_North_req_X_E, N_err_East_req_X_W, N_err_West_req_X_S,
N_err_South_req_X_L, N_err_Local_req_X_N,
N_err_IDLE_req_X_W, N_err_North_req_X_W, N_err_East_req_X_S, N_err_West_req_X_L,
N_err_South_req_X_N, N_err_Local_req_X_E,
N_err_IDLE_req_X_S, N_err_North_req_X_S, N_err_East_req_X_L, N_err_West_req_X_N,
N_err_South_req_X_E, N_err_Local_req_X_W,
N_err_IDLE_req_X_L, N_err_North_req_X_L, N_err_East_req_X_N, N_err_West_req_X_E,
N_err_South_req_X_W, N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot,
N_arbiter_out_err_no_request_grants,
N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant,
N_err_state_West_Invalid_Grant, N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant,
N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N,
E_err_North_req_X_N,
E_err_North_credit_not_zero_req_X_N_grant_N,
E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E,
E_err_East_credit_not_zero_req_X_E_grant_E,
E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
E_err_West_req_X_W,
E_err_West_credit_not_zero_req_X_W_grant_W,
E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
E_err_South_req_X_S,
E_err_South_credit_not_zero_req_X_S_grant_S,
E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
E_err_Local_req_X_L,
E_err_Local_credit_not_zero_req_X_L_grant_L,
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E, E_err_North_req_X_E, E_err_East_req_X_W, E_err_West_req_X_S, E_err_South_req_X_L, E_err_Local_req_X_N,
E_err_IDLE_req_X_W, E_err_North_req_X_W, E_err_East_req_X_S, E_err_West_req_X_L, E_err_South_req_X_N, E_err_Local_req_X_E,
E_err_IDLE_req_X_S, E_err_North_req_X_S, E_err_East_req_X_L, E_err_West_req_X_N, E_err_South_req_X_E, E_err_Local_req_X_W,
E_err_IDLE_req_X_L, E_err_North_req_X_L, E_err_East_req_X_N, E_err_West_req_X_E, E_err_South_req_X_W, E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot,
E_arbiter_out_err_no_request_grants,
E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant, E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N, W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N,
W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E, W_err_North_req_X_E, W_err_East_req_X_W, W_err_West_req_X_S,
W_err_South_req_X_L, W_err_Local_req_X_N,
W_err_IDLE_req_X_W, W_err_North_req_X_W, W_err_East_req_X_S, W_err_West_req_X_L,
W_err_South_req_X_N, W_err_Local_req_X_E,
W_err_IDLE_req_X_S, W_err_North_req_X_S, W_err_East_req_X_L, W_err_West_req_X_N,
W_err_South_req_X_E, W_err_Local_req_X_W,
W_err_IDLE_req_X_L, W_err_North_req_X_L, W_err_East_req_X_N, W_err_West_req_X_E,
W_err_South_req_X_W, W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot,
W_arbiter_out_err_no_request_grants,
W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant,W_err_state_East_Invalid_Grant,
W_err_state_West_Invalid_Grant, W_err_state_South_Invalid_Grant,W_err_state_Local_Invalid_Grant,
W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N, S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N,
S_err_North_credit_zero_or_not_req_X_N_not_grant_N, S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E,
S_err_East_credit_zero_or_not_req_X_E_not_grant_E, S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W,
S_err_West_credit_zero_or_not_req_X_W_not_grant_W, S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S,
S_err_South_credit_zero_or_not_req_X_S_not_grant_S, S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L,
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E, S_err_North_req_X_E, S_err_East_req_X_W, S_err_West_req_X_S, S_err_South_req_X_L, S_err_Local_req_X_N,
S_err_IDLE_req_X_W, S_err_North_req_X_W, S_err_East_req_X_S, S_err_West_req_X_L, S_err_South_req_X_N, S_err_Local_req_X_E,
S_err_IDLE_req_X_S, S_err_North_req_X_S, S_err_East_req_X_L, S_err_West_req_X_N, S_err_South_req_X_E, S_err_Local_req_X_W,
S_err_IDLE_req_X_L, S_err_North_req_X_L, S_err_East_req_X_N, S_err_West_req_X_E, S_err_South_req_X_W, S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N, L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N,
L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E,
L_err_East_credit_zero_or_not_req_X_E_not_grant_E,
L_err_West_req_X_W, L_err_West_credit_not_zero_req_X_W_grant_W,
L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S,
L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L,
L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E, L_err_North_req_X_E, L_err_East_req_X_W, L_err_West_req_X_S, L_err_South_req_X_L, L_err_Local_req_X_N,
L_err_IDLE_req_X_W, L_err_North_req_X_W, L_err_East_req_X_S, L_err_West_req_X_L, L_err_South_req_X_N, L_err_Local_req_X_E,
L_err_IDLE_req_X_S, L_err_North_req_X_S, L_err_East_req_X_L, L_err_West_req_X_N, L_err_South_req_X_E, L_err_Local_req_X_W,
L_err_IDLE_req_X_L, L_err_North_req_X_L, L_err_East_req_X_N, L_err_West_req_X_E, L_err_South_req_X_W, L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot,
L_arbiter_out_err_no_request_grants,
L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant,L_err_state_East_Invalid_Grant,
L_err_state_West_Invalid_Grant, L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant,
L_err_Grants_onehot_or_all_zero : std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Signals needed for grouping checkers to model turn/path faults
signal N_FIFO_checkers_ORed, E_FIFO_checkers_ORed, W_FIFO_checkers_ORed, S_FIFO_checkers_ORed, L_FIFO_checkers_ORed : std_logic;
signal N2E_turn_fault, N2W_turn_fault, E2N_turn_fault, E2S_turn_fault, W2N_turn_fault, W2S_turn_fault, S2E_turn_fault, S2W_turn_fault : std_logic;
signal not_N2E_turn_fault, not_N2W_turn_fault, not_E2N_turn_fault, not_E2S_turn_fault, not_W2N_turn_fault, not_W2S_turn_fault, not_S2E_turn_fault, not_S2W_turn_fault : std_logic;
signal N2S_path_fault, S2N_path_fault, E2W_path_fault, W2E_path_fault : std_logic;
signal not_N2S_path_fault, not_S2N_path_fault, not_E2W_path_fault, not_W2E_path_fault : std_logic;
signal L2N_fault, L2E_fault, L2W_fault, L2S_fault, N2L_fault, E2L_fault, W2L_fault, S2L_fault : std_logic;
signal not_L2N_fault, not_L2E_fault, not_L2W_fault, not_L2S_fault, not_N2L_fault, not_E2L_fault, not_W2L_fault, not_S2L_fault : std_logic;
-- Just used temporarily for debugging purposes!
signal N_LBDR_checkers_ORed, E_LBDR_checkers_ORed, W_LBDR_checkers_ORed, S_LBDR_checkers_ORed, L_LBDR_checkers_ORed : std_logic;
signal Allocator_checkers_ORed : std_logic;
--signal turn_faults_sig : std_logic_vector(19 downto 0);
-------------------------------------------------------------------------------------------------
-- Added because of the chain we make for sending faulty values ---------------------------------
-- The chain is : L, N, E, W and S FIFO, then L, N, E, W and S LBDR, ----------------------------
-- then L, N, E, W and S Arbiter_in, --------------------
-- then L, N, E, W and S Arbiter_out and then Allocator's interlal logic ??!! --
-------------------------------------------------------------------------------------------------
signal fault_DO_serial_L_FIFO_to_N_FIFO, fault_DO_serial_N_FIFO_to_E_FIFO, fault_DO_serial_E_FIFO_to_W_FIFO, fault_DO_serial_W_FIFO_to_S_FIFO: std_logic;
signal fault_DO_serial_S_FIFO_to_L_LBDR, fault_DO_serial_L_LBDR_to_N_LBDR, fault_DO_serial_N_LBDR_to_E_LBDR, fault_DO_serial_E_LBDR_to_W_LBDR: std_logic;
signal fault_DO_serial_W_LBDR_to_S_LBDR, fault_DO_serial_S_LBDR_to_Allocator: std_logic;
------------------------------------------------------------------
------------------------------------------------------------------
begin
not_N2E_turn_fault <= not N2E_turn_fault;
not_N2W_turn_fault <= not N2W_turn_fault;
not_E2N_turn_fault <= not E2N_turn_fault;
not_E2S_turn_fault <= not E2S_turn_fault;
not_W2N_turn_fault <= not W2N_turn_fault;
not_W2S_turn_fault <= not W2S_turn_fault;
not_S2E_turn_fault <= not S2E_turn_fault;
not_S2W_turn_fault <= not W2S_turn_fault;
not_N2S_path_fault <= not N2S_path_fault;
not_S2N_path_fault <= not S2N_path_fault;
not_E2W_path_fault <= not E2W_path_fault;
not_W2E_path_fault <= not W2E_path_fault;
not_L2N_fault <= not L2N_fault;
not_L2E_fault <= not L2E_fault;
not_L2W_fault <= not L2W_fault;
not_L2S_fault <= not L2S_fault;
not_N2L_fault <= not N2L_fault;
not_E2L_fault <= not E2L_fault;
not_W2L_fault <= not W2L_fault;
not_S2L_fault <= not S2L_fault;
-- FIFO contributes to all turns and paths, therefore, for each turn or path (for the input direction), all the outputs of FIFO checkers
-- corresponding to that input are ORed together.
-- North
N_FIFO_checkers_ORed <= N_err_empty_full or
N_err_empty_read_en or
N_err_full_write_en or
N_err_state_in_onehot or
N_err_read_pointer_in_onehot or
N_err_write_pointer_in_onehot or
N_err_write_en_write_pointer or
N_err_not_write_en_write_pointer or
N_err_read_pointer_write_pointer_not_empty or
N_err_read_pointer_write_pointer_empty or
N_err_read_pointer_write_pointer_not_full or
N_err_read_pointer_write_pointer_full or
N_err_read_pointer_increment or
N_err_read_pointer_not_increment or
N_err_write_en or
N_err_not_write_en or
N_err_not_write_en1 or
N_err_not_write_en2 or
N_err_read_en_mismatch or
N_err_read_en_mismatch1 or
N_err_fake_credit_read_en_fake_credit_counter_in_increment or
N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
N_err_fake_credit_read_en_credit_out or
N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
N_err_state_out_Idle_not_fault_out_not_fake_credit or
N_err_state_out_Idle_not_fault_out_not_fault_info_in or
N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
N_err_state_out_Idle_fault_out_fake_credit or
N_err_state_out_Idle_fault_out_state_in_Packet_drop or
N_err_state_out_Idle_fault_out_fault_info_in or
N_err_state_out_Idle_fault_out_faulty_packet_in or
N_err_state_out_Idle_not_health_info or
N_err_state_out_Idle_not_write_fake_flit or
N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
N_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
N_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
N_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
N_err_state_out_Body_flit_valid_in_not_health_info or
N_err_state_out_Body_flit_not_fake_credit or
N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
N_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
N_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
N_err_state_out_Tail_flit_not_write_fake_flit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
N_err_fault_info_fault_info_out_equal or
N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
-- East
E_FIFO_checkers_ORed <= E_err_empty_full or
E_err_empty_read_en or
E_err_full_write_en or
E_err_state_in_onehot or
E_err_read_pointer_in_onehot or
E_err_write_pointer_in_onehot or
E_err_write_en_write_pointer or
E_err_not_write_en_write_pointer or
E_err_read_pointer_write_pointer_not_empty or
E_err_read_pointer_write_pointer_empty or
E_err_read_pointer_write_pointer_not_full or
E_err_read_pointer_write_pointer_full or
E_err_read_pointer_increment or
E_err_read_pointer_not_increment or
E_err_write_en or
E_err_not_write_en or
E_err_not_write_en1 or
E_err_not_write_en2 or
E_err_read_en_mismatch or
E_err_read_en_mismatch1 or
E_err_fake_credit_read_en_fake_credit_counter_in_increment or
E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
E_err_fake_credit_read_en_credit_out or
E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
E_err_state_out_Idle_not_fault_out_not_fake_credit or
E_err_state_out_Idle_not_fault_out_not_fault_info_in or
E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
E_err_state_out_Idle_fault_out_fake_credit or
E_err_state_out_Idle_fault_out_state_in_Packet_drop or
E_err_state_out_Idle_fault_out_fault_info_in or
E_err_state_out_Idle_fault_out_faulty_packet_in or
E_err_state_out_Idle_not_health_info or
E_err_state_out_Idle_not_write_fake_flit or
E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
E_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
E_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
E_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
E_err_state_out_Body_flit_valid_in_not_health_info or
E_err_state_out_Body_flit_not_fake_credit or
E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
E_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
E_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
E_err_state_out_Tail_flit_not_write_fake_flit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
E_err_fault_info_fault_info_out_equal or
E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
-- West
W_FIFO_checkers_ORed <= W_err_empty_full or W_err_empty_read_en or W_err_full_write_en or W_err_state_in_onehot or
W_err_read_pointer_in_onehot or W_err_write_pointer_in_onehot or
W_err_write_en_write_pointer or W_err_not_write_en_write_pointer or W_err_read_pointer_write_pointer_not_empty or
W_err_read_pointer_write_pointer_empty or W_err_read_pointer_write_pointer_not_full or
W_err_read_pointer_write_pointer_full or W_err_read_pointer_increment or W_err_read_pointer_not_increment or
W_err_write_en or W_err_not_write_en or W_err_not_write_en1 or W_err_not_write_en2 or W_err_read_en_mismatch or
W_err_read_en_mismatch1 or
W_err_fake_credit_read_en_fake_credit_counter_in_increment or
W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
W_err_fake_credit_read_en_credit_out or
W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
W_err_state_out_Idle_not_fault_out_not_fake_credit or
W_err_state_out_Idle_not_fault_out_not_fault_info_in or
W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
W_err_state_out_Idle_fault_out_fake_credit or
W_err_state_out_Idle_fault_out_state_in_Packet_drop or
W_err_state_out_Idle_fault_out_fault_info_in or
W_err_state_out_Idle_fault_out_faulty_packet_in or
W_err_state_out_Idle_not_health_info or
W_err_state_out_Idle_not_write_fake_flit or
W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
W_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
W_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
W_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
W_err_state_out_Body_flit_valid_in_not_health_info or
W_err_state_out_Body_flit_not_fake_credit or
W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
W_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
W_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
W_err_state_out_Tail_flit_not_write_fake_flit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
W_err_fault_info_fault_info_out_equal or
W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
-- South
S_FIFO_checkers_ORed <= S_err_empty_full or S_err_empty_read_en or S_err_full_write_en or S_err_state_in_onehot or
S_err_read_pointer_in_onehot or S_err_write_pointer_in_onehot or
S_err_write_en_write_pointer or S_err_not_write_en_write_pointer or
S_err_read_pointer_write_pointer_not_empty or S_err_read_pointer_write_pointer_empty or
S_err_read_pointer_write_pointer_not_full or S_err_read_pointer_write_pointer_full or
S_err_read_pointer_increment or S_err_read_pointer_not_increment or S_err_write_en or
S_err_not_write_en or S_err_not_write_en1 or S_err_not_write_en2 or S_err_read_en_mismatch or
S_err_read_en_mismatch1 or
S_err_fake_credit_read_en_fake_credit_counter_in_increment or
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
S_err_fake_credit_read_en_credit_out or
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
S_err_state_out_Idle_not_fault_out_not_fake_credit or
S_err_state_out_Idle_not_fault_out_not_fault_info_in or
S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
S_err_state_out_Idle_fault_out_fake_credit or
S_err_state_out_Idle_fault_out_state_in_Packet_drop or
S_err_state_out_Idle_fault_out_fault_info_in or
S_err_state_out_Idle_fault_out_faulty_packet_in or
S_err_state_out_Idle_not_health_info or
S_err_state_out_Idle_not_write_fake_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
S_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
S_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
S_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
S_err_state_out_Body_flit_valid_in_not_health_info or
S_err_state_out_Body_flit_not_fake_credit or
S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
S_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
S_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
S_err_state_out_Tail_flit_not_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
S_err_fault_info_fault_info_out_equal or
S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
-- Local
L_FIFO_checkers_ORed <= L_err_empty_full or L_err_empty_read_en or L_err_full_write_en or L_err_state_in_onehot or
L_err_read_pointer_in_onehot or L_err_write_pointer_in_onehot or
L_err_write_en_write_pointer or
L_err_not_write_en_write_pointer or
L_err_read_pointer_write_pointer_not_empty or
L_err_read_pointer_write_pointer_empty or
L_err_read_pointer_write_pointer_not_full or
L_err_read_pointer_write_pointer_full or
L_err_read_pointer_increment or
L_err_read_pointer_not_increment or
L_err_write_en or L_err_not_write_en or L_err_not_write_en1 or L_err_not_write_en2 or
L_err_read_en_mismatch or L_err_read_en_mismatch1 or
L_err_fake_credit_read_en_fake_credit_counter_in_increment or
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
L_err_fake_credit_read_en_credit_out or
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
L_err_state_out_Idle_not_fault_out_not_fake_credit or
L_err_state_out_Idle_not_fault_out_not_fault_info_in or
L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
L_err_state_out_Idle_fault_out_fake_credit or
L_err_state_out_Idle_fault_out_state_in_Packet_drop or
L_err_state_out_Idle_fault_out_fault_info_in or
L_err_state_out_Idle_fault_out_faulty_packet_in or
L_err_state_out_Idle_not_health_info or
L_err_state_out_Idle_not_write_fake_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
L_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
L_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
L_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
L_err_state_out_Body_flit_valid_in_not_health_info or
L_err_state_out_Body_flit_not_fake_credit or
L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
L_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
L_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
L_err_state_out_Tail_flit_not_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
L_err_fault_info_fault_info_out_equal or
L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- Just for debugging purposes of the checkers!
-- LBDR checker outputs ORed
-- North
-- Routing part checkers
N_LBDR_checkers_ORed <= N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_tail_empty_Requests_FF_Requests_in or
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
N_err_grants_onehot or
N_err_grants_mismatch or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_N1 or
N_err_dst_addr_cur_addr_not_N1 or
N_err_dst_addr_cur_addr_E1 or
N_err_dst_addr_cur_addr_not_E1 or
N_err_dst_addr_cur_addr_W1 or
N_err_dst_addr_cur_addr_not_W1 or
N_err_dst_addr_cur_addr_S1 or
N_err_dst_addr_cur_addr_not_S1 or
N_err_dst_addr_cur_addr_Req_L_in or
N_err_dst_addr_cur_addr_not_Req_L_in or
N_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
N_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--N_err_header_not_empty_Req_L_in or -- added according to new design
N_err_header_not_empty_Req_N_in or
N_err_header_not_empty_Req_E_in or
N_err_header_not_empty_Req_W_in or
N_err_header_not_empty_Req_S_in or
N_err_header_empty_packet_drop_in_packet_drop_equal or
N_err_tail_not_empty_packet_drop_not_packet_drop_in or
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
N_err_packet_drop_order or
-- Cx_Reconf checkers
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
-- East
-- Routing part checkers
E_LBDR_checkers_ORed <= E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
E_err_grants_onehot or
E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_N1 or
E_err_dst_addr_cur_addr_not_N1 or
E_err_dst_addr_cur_addr_E1 or
E_err_dst_addr_cur_addr_not_E1 or
E_err_dst_addr_cur_addr_W1 or
E_err_dst_addr_cur_addr_not_W1 or
E_err_dst_addr_cur_addr_S1 or
E_err_dst_addr_cur_addr_not_S1 or
E_err_dst_addr_cur_addr_Req_L_in or
E_err_dst_addr_cur_addr_not_Req_L_in or
E_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
E_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--E_err_header_not_empty_Req_L_in or -- added according to new design
E_err_header_not_empty_Req_N_in or
E_err_header_not_empty_Req_E_in or
E_err_header_not_empty_Req_W_in or
E_err_header_not_empty_Req_S_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or
E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
-- Cx_Reconf checkers
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
-- West
-- Routing part checkers
W_LBDR_checkers_ORed <= W_err_header_empty_Requests_FF_Requests_in or
W_err_tail_Requests_in_all_zero or
W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
W_err_grants_onehot or
W_err_grants_mismatch or
W_err_header_tail_Requests_FF_Requests_in or
W_err_dst_addr_cur_addr_N1 or
W_err_dst_addr_cur_addr_not_N1 or
W_err_dst_addr_cur_addr_E1 or
W_err_dst_addr_cur_addr_not_E1 or
W_err_dst_addr_cur_addr_W1 or
W_err_dst_addr_cur_addr_not_W1 or
W_err_dst_addr_cur_addr_S1 or
W_err_dst_addr_cur_addr_not_S1 or
W_err_dst_addr_cur_addr_Req_L_in or
W_err_dst_addr_cur_addr_not_Req_L_in or
W_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
W_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--W_err_header_not_empty_Req_L_in or -- added according to new design
W_err_header_not_empty_Req_N_in or
W_err_header_not_empty_Req_E_in or
W_err_header_not_empty_Req_W_in or
W_err_header_not_empty_Req_S_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or
W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
W_err_packet_drop_order or
-- Cx_Reconf checkers
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
-- South
-- Routing part checkers
S_LBDR_checkers_ORed <= S_err_header_empty_Requests_FF_Requests_in or
S_err_tail_Requests_in_all_zero or
S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
S_err_grants_onehot or
S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or
S_err_dst_addr_cur_addr_N1 or
S_err_dst_addr_cur_addr_not_N1 or
S_err_dst_addr_cur_addr_E1 or
S_err_dst_addr_cur_addr_not_E1 or
S_err_dst_addr_cur_addr_W1 or
S_err_dst_addr_cur_addr_not_W1 or
S_err_dst_addr_cur_addr_S1 or
S_err_dst_addr_cur_addr_not_S1 or
S_err_dst_addr_cur_addr_Req_L_in or
S_err_dst_addr_cur_addr_not_Req_L_in or
S_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
S_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--S_err_header_not_empty_Req_L_in or -- added according to new design
S_err_header_not_empty_Req_N_in or
S_err_header_not_empty_Req_E_in or
S_err_header_not_empty_Req_W_in or
S_err_header_not_empty_Req_S_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or
S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
-- Cx_Reconf checkers
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
-- Local
-- Routing part checkers
L_LBDR_checkers_ORed <= L_err_header_empty_Requests_FF_Requests_in or
L_err_tail_Requests_in_all_zero or
L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
L_err_grants_onehot or
L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or
L_err_dst_addr_cur_addr_N1 or
L_err_dst_addr_cur_addr_not_N1 or
L_err_dst_addr_cur_addr_E1 or
L_err_dst_addr_cur_addr_not_E1 or
L_err_dst_addr_cur_addr_W1 or
L_err_dst_addr_cur_addr_not_W1 or
L_err_dst_addr_cur_addr_S1 or
L_err_dst_addr_cur_addr_not_S1 or
L_err_dst_addr_cur_addr_Req_L_in or
L_err_dst_addr_cur_addr_not_Req_L_in or
L_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
L_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--L_err_header_not_empty_Req_L_in or -- added according to new design
L_err_header_not_empty_Req_N_in or
L_err_header_not_empty_Req_E_in or
L_err_header_not_empty_Req_W_in or
L_err_header_not_empty_Req_S_in or
L_err_header_empty_packet_drop_in_packet_drop_equal or
L_err_tail_not_empty_packet_drop_not_packet_drop_in or
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
L_err_packet_drop_order or
-- Cx_Reconf checkers
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- Allocator checker outputs ORed !
-- Allocator logic checker outputs
Allocator_checkers_ORed <= err_grant_N_N_sig_not_empty_N_grant_N_N or err_not_grant_N_N_sig_or_empty_N_not_grant_N_N or
err_grant_N_E_sig_not_empty_E_grant_N_E or err_not_grant_N_E_sig_or_empty_E_not_grant_N_E or
err_grant_N_W_sig_not_empty_W_grant_N_W or err_not_grant_N_W_sig_or_empty_W_not_grant_N_W or
err_grant_N_S_sig_not_empty_S_grant_N_S or err_not_grant_N_S_sig_or_empty_S_not_grant_N_S or
err_grant_N_L_sig_not_empty_L_grant_N_L or err_not_grant_N_L_sig_or_empty_L_not_grant_N_L or
err_grant_E_N_sig_not_empty_N_grant_E_N or err_not_grant_E_N_sig_or_empty_N_not_grant_E_N or
err_grant_E_E_sig_not_empty_E_grant_E_E or err_not_grant_E_E_sig_or_empty_E_not_grant_E_E or
err_grant_E_W_sig_not_empty_W_grant_E_W or err_not_grant_E_W_sig_or_empty_W_not_grant_E_W or
err_grant_E_S_sig_not_empty_S_grant_E_S or err_not_grant_E_S_sig_or_empty_S_not_grant_E_S or
err_grant_E_L_sig_not_empty_L_grant_E_L or err_not_grant_E_L_sig_or_empty_L_not_grant_E_L or
err_grant_W_N_sig_not_empty_N_grant_W_N or err_not_grant_W_N_sig_or_empty_N_not_grant_W_N or
err_grant_W_E_sig_not_empty_E_grant_W_E or err_not_grant_W_E_sig_or_empty_E_not_grant_W_E or
err_grant_W_W_sig_not_empty_W_grant_W_W or err_not_grant_W_W_sig_or_empty_W_not_grant_W_W or
err_grant_W_S_sig_not_empty_S_grant_W_S or err_not_grant_W_S_sig_or_empty_S_not_grant_W_S or
err_grant_W_L_sig_not_empty_L_grant_W_L or err_not_grant_W_L_sig_or_empty_L_not_grant_W_L or
err_grant_S_N_sig_not_empty_N_grant_S_N or err_not_grant_S_N_sig_or_empty_N_not_grant_S_N or
err_grant_S_E_sig_not_empty_E_grant_S_E or err_not_grant_S_E_sig_or_empty_E_not_grant_S_E or
err_grant_S_W_sig_not_empty_W_grant_S_W or err_not_grant_S_W_sig_or_empty_W_not_grant_S_W or
err_grant_S_S_sig_not_empty_S_grant_S_S or err_not_grant_S_S_sig_or_empty_S_not_grant_S_S or
err_grant_S_L_sig_not_empty_L_grant_S_L or err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or
err_grant_L_N_sig_not_empty_N_grant_L_N or err_not_grant_L_N_sig_or_empty_N_not_grant_L_N or
err_grant_L_E_sig_not_empty_E_grant_L_E or err_not_grant_L_E_sig_or_empty_E_not_grant_L_E or
err_grant_L_W_sig_not_empty_W_grant_L_W or err_not_grant_L_W_sig_or_empty_W_not_grant_L_W or
err_grant_L_S_sig_not_empty_S_grant_L_S or err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or
err_grant_L_L_sig_not_empty_L_grant_L_L or err_not_grant_L_L_sig_or_empty_L_not_grant_L_L or
err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or
err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or
err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or
err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or
err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or
err_grants_valid_not_match or
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_N_credit_counter_N_out_increment or
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or
err_grant_N_credit_counter_N_out_decrement or
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or
err_credit_in_E_credit_counter_E_out_increment or
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or
err_grant_E_credit_counter_E_out_decrement or
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or
err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or
err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or
err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or
err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or
err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or
err_grant_L_credit_counter_L_out_decrement or
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal or
-- Arbiter_in checker outputs
-- North Arbiter_in checker outputs
N_err_Requests_state_in_state_not_equal or
N_err_IDLE_Req_N or N_err_IDLE_grant_N or N_err_North_Req_N or N_err_North_grant_N or
N_err_East_Req_E or N_err_East_grant_E or N_err_West_Req_W or N_err_West_grant_W or
N_err_South_Req_S or N_err_South_grant_S or N_err_Local_Req_L or N_err_Local_grant_L or
N_err_IDLE_Req_E or N_err_IDLE_grant_E or N_err_North_Req_E or N_err_North_grant_E or
N_err_East_Req_W or N_err_East_grant_W or N_err_West_Req_S or N_err_West_grant_S or
N_err_South_Req_L or N_err_South_grant_L or N_err_Local_Req_N or N_err_Local_grant_N or
N_err_IDLE_Req_W or N_err_IDLE_grant_W or N_err_North_Req_W or N_err_North_grant_W or
N_err_East_Req_S or N_err_East_grant_S or N_err_West_Req_L or N_err_West_grant_L or
N_err_South_Req_N or N_err_South_grant_N or N_err_Local_Req_E or N_err_Local_grant_E or
N_err_IDLE_Req_S or N_err_IDLE_grant_S or N_err_North_Req_S or N_err_North_grant_S or
N_err_East_Req_L or N_err_East_grant_L or N_err_West_Req_N or N_err_West_grant_N or
N_err_South_Req_E or N_err_South_grant_E or N_err_Local_Req_W or N_err_Local_grant_W or
N_err_IDLE_Req_L or N_err_IDLE_grant_L or N_err_North_Req_L or N_err_North_grant_L or
N_err_East_Req_N or N_err_East_grant_N or N_err_West_Req_E or N_err_West_grant_E or
N_err_South_Req_W or N_err_South_grant_W or N_err_Local_Req_S or N_err_Local_grant_S or
N_err_arbiter_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or
N_err_no_Req_N_grant_N or N_err_no_Req_E_grant_E or N_err_no_Req_W_grant_W or
N_err_no_Req_S_grant_S or N_err_no_Req_L_grant_L or
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal or
E_err_IDLE_Req_N or E_err_IDLE_grant_N or E_err_North_Req_N or E_err_North_grant_N or
E_err_East_Req_E or E_err_East_grant_E or E_err_West_Req_W or E_err_West_grant_W or
E_err_South_Req_S or E_err_South_grant_S or E_err_Local_Req_L or E_err_Local_grant_L or
E_err_IDLE_Req_E or E_err_IDLE_grant_E or E_err_North_Req_E or E_err_North_grant_E or
E_err_East_Req_W or E_err_East_grant_W or E_err_West_Req_S or E_err_West_grant_S or
E_err_South_Req_L or E_err_South_grant_L or E_err_Local_Req_N or E_err_Local_grant_N or
E_err_IDLE_Req_W or E_err_IDLE_grant_W or E_err_North_Req_W or E_err_North_grant_W or
E_err_East_Req_S or E_err_East_grant_S or E_err_West_Req_L or E_err_West_grant_L or
E_err_South_Req_N or E_err_South_grant_N or E_err_Local_Req_E or E_err_Local_grant_E or
E_err_IDLE_Req_S or E_err_IDLE_grant_S or E_err_North_Req_S or E_err_North_grant_S or
E_err_East_Req_L or E_err_East_grant_L or E_err_West_Req_N or E_err_West_grant_N or
E_err_South_Req_E or E_err_South_grant_E or E_err_Local_Req_W or E_err_Local_grant_W or
E_err_IDLE_Req_L or E_err_IDLE_grant_L or E_err_North_Req_L or E_err_North_grant_L or
E_err_East_Req_N or E_err_East_grant_N or E_err_West_Req_E or E_err_West_grant_E or
E_err_South_Req_W or E_err_South_grant_W or E_err_Local_Req_S or E_err_Local_grant_S or
E_err_arbiter_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or
E_err_no_Req_N_grant_N or E_err_no_Req_E_grant_E or E_err_no_Req_W_grant_W or
E_err_no_Req_S_grant_S or E_err_no_Req_L_grant_L or
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal or
W_err_IDLE_Req_N or W_err_IDLE_grant_N or W_err_North_Req_N or W_err_North_grant_N or
W_err_East_Req_E or W_err_East_grant_E or W_err_West_Req_W or W_err_West_grant_W or
W_err_South_Req_S or W_err_South_grant_S or W_err_Local_Req_L or W_err_Local_grant_L or
W_err_IDLE_Req_E or W_err_IDLE_grant_E or W_err_North_Req_E or W_err_North_grant_E or
W_err_East_Req_W or W_err_East_grant_W or W_err_West_Req_S or W_err_West_grant_S or
W_err_South_Req_L or W_err_South_grant_L or W_err_Local_Req_N or W_err_Local_grant_N or
W_err_IDLE_Req_W or W_err_IDLE_grant_W or W_err_North_Req_W or W_err_North_grant_W or
W_err_East_Req_S or W_err_East_grant_S or W_err_West_Req_L or W_err_West_grant_L or
W_err_South_Req_N or W_err_South_grant_N or W_err_Local_Req_E or W_err_Local_grant_E or
W_err_IDLE_Req_S or W_err_IDLE_grant_S or W_err_North_Req_S or W_err_North_grant_S or
W_err_East_Req_L or W_err_East_grant_L or W_err_West_Req_N or W_err_West_grant_N or
W_err_South_Req_E or W_err_South_grant_E or W_err_Local_Req_W or W_err_Local_grant_W or
W_err_IDLE_Req_L or W_err_IDLE_grant_L or W_err_North_Req_L or W_err_North_grant_L or
W_err_East_Req_N or W_err_East_grant_N or W_err_West_Req_E or W_err_West_grant_E or
W_err_South_Req_W or W_err_South_grant_W or W_err_Local_Req_S or W_err_Local_grant_S or
W_err_arbiter_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or
W_err_no_Req_N_grant_N or W_err_no_Req_E_grant_E or W_err_no_Req_W_grant_W or
W_err_no_Req_S_grant_S or W_err_no_Req_L_grant_L or
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal or
S_err_IDLE_Req_N or S_err_IDLE_grant_N or S_err_North_Req_N or S_err_North_grant_N or
S_err_East_Req_E or S_err_East_grant_E or S_err_West_Req_W or S_err_West_grant_W or
S_err_South_Req_S or S_err_South_grant_S or S_err_Local_Req_L or S_err_Local_grant_L or
S_err_IDLE_Req_E or S_err_IDLE_grant_E or S_err_North_Req_E or S_err_North_grant_E or
S_err_East_Req_W or S_err_East_grant_W or S_err_West_Req_S or S_err_West_grant_S or
S_err_South_Req_L or S_err_South_grant_L or S_err_Local_Req_N or S_err_Local_grant_N or
S_err_IDLE_Req_W or S_err_IDLE_grant_W or S_err_North_Req_W or S_err_North_grant_W or
S_err_East_Req_S or S_err_East_grant_S or S_err_West_Req_L or S_err_West_grant_L or
S_err_South_Req_N or S_err_South_grant_N or S_err_Local_Req_E or S_err_Local_grant_E or
S_err_IDLE_Req_S or S_err_IDLE_grant_S or S_err_North_Req_S or S_err_North_grant_S or
S_err_East_Req_L or S_err_East_grant_L or S_err_West_Req_N or S_err_West_grant_N or
S_err_South_Req_E or S_err_South_grant_E or S_err_Local_Req_W or S_err_Local_grant_W or
S_err_IDLE_Req_L or S_err_IDLE_grant_L or S_err_North_Req_L or S_err_North_grant_L or
S_err_East_Req_N or S_err_East_grant_N or S_err_West_Req_E or S_err_West_grant_E or
S_err_South_Req_W or S_err_South_grant_W or S_err_Local_Req_S or S_err_Local_grant_S or
S_err_arbiter_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or
S_err_no_Req_N_grant_N or S_err_no_Req_E_grant_E or S_err_no_Req_W_grant_W or
S_err_no_Req_S_grant_S or S_err_no_Req_L_grant_L or
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal or
L_err_IDLE_Req_N or L_err_IDLE_grant_N or L_err_North_Req_N or L_err_North_grant_N or
L_err_East_Req_E or L_err_East_grant_E or L_err_West_Req_W or L_err_West_grant_W or
L_err_South_Req_S or L_err_South_grant_S or L_err_Local_Req_L or L_err_Local_grant_L or
L_err_IDLE_Req_E or L_err_IDLE_grant_E or L_err_North_Req_E or L_err_North_grant_E or
L_err_East_Req_W or L_err_East_grant_W or L_err_West_Req_S or L_err_West_grant_S or
L_err_South_Req_L or L_err_South_grant_L or L_err_Local_Req_N or L_err_Local_grant_N or
L_err_IDLE_Req_W or L_err_IDLE_grant_W or L_err_North_Req_W or L_err_North_grant_W or
L_err_East_Req_S or L_err_East_grant_S or L_err_West_Req_L or L_err_West_grant_L or
L_err_South_Req_N or L_err_South_grant_N or L_err_Local_Req_E or L_err_Local_grant_E or
L_err_IDLE_Req_S or L_err_IDLE_grant_S or L_err_North_Req_S or L_err_North_grant_S or
L_err_East_Req_L or L_err_East_grant_L or L_err_West_Req_N or L_err_West_grant_N or
L_err_South_Req_E or L_err_South_grant_E or L_err_Local_Req_W or L_err_Local_grant_W or
L_err_IDLE_Req_L or L_err_IDLE_grant_L or L_err_North_Req_L or L_err_North_grant_L or
L_err_East_Req_N or L_err_East_grant_N or L_err_West_Req_E or L_err_West_grant_E or
L_err_South_Req_W or L_err_South_grant_W or L_err_Local_Req_S or L_err_Local_grant_S or
L_err_arbiter_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or
L_err_no_Req_N_grant_N or L_err_no_Req_E_grant_E or L_err_no_Req_W_grant_W or
L_err_no_Req_S_grant_S or L_err_no_Req_L_grant_L or
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal or
N_err_IDLE_req_X_N or
N_err_North_req_X_N or
N_err_North_credit_not_zero_req_X_N_grant_N or
N_err_North_credit_zero_or_not_req_X_N_not_grant_N or
N_err_East_req_X_E or
N_err_East_credit_not_zero_req_X_E_grant_E or
N_err_East_credit_zero_or_not_req_X_E_not_grant_E or
N_err_West_req_X_W or
N_err_West_credit_not_zero_req_X_W_grant_W or
N_err_West_credit_zero_or_not_req_X_W_not_grant_W or
N_err_South_req_X_S or
N_err_South_credit_not_zero_req_X_S_grant_S or
N_err_South_credit_zero_or_not_req_X_S_not_grant_S or
N_err_Local_req_X_L or
N_err_Local_credit_not_zero_req_X_L_grant_L or
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
N_err_IDLE_req_X_E or
N_err_North_req_X_E or
N_err_East_req_X_W or
N_err_West_req_X_S or
N_err_South_req_X_L or
N_err_Local_req_X_N or
N_err_IDLE_req_X_W or
N_err_North_req_X_W or
N_err_East_req_X_S or
N_err_West_req_X_L or
N_err_South_req_X_N or
N_err_Local_req_X_E or
N_err_IDLE_req_X_S or
N_err_North_req_X_S or
N_err_East_req_X_L or
N_err_West_req_X_N or
N_err_South_req_X_E or
N_err_Local_req_X_W or
N_err_IDLE_req_X_L or
N_err_North_req_X_L or
N_err_East_req_X_N or
N_err_West_req_X_E or
N_err_South_req_X_W or
N_err_Local_req_X_S or
N_arbiter_out_err_state_in_onehot or
N_arbiter_out_err_no_request_grants or
N_err_request_IDLE_state or
N_err_request_IDLE_not_Grants or
N_err_state_North_Invalid_Grant or
N_err_state_East_Invalid_Grant or
N_err_state_West_Invalid_Grant or
N_err_state_South_Invalid_Grant or
N_err_state_Local_Invalid_Grant or
N_err_Grants_onehot_or_all_zero or
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal or
E_err_IDLE_req_X_N or
E_err_North_req_X_N or
E_err_North_credit_not_zero_req_X_N_grant_N or
E_err_North_credit_zero_or_not_req_X_N_not_grant_N or
E_err_East_req_X_E or
E_err_East_credit_not_zero_req_X_E_grant_E or
E_err_East_credit_zero_or_not_req_X_E_not_grant_E or
E_err_West_req_X_W or
E_err_West_credit_not_zero_req_X_W_grant_W or
E_err_West_credit_zero_or_not_req_X_W_not_grant_W or
E_err_South_req_X_S or
E_err_South_credit_not_zero_req_X_S_grant_S or
E_err_South_credit_zero_or_not_req_X_S_not_grant_S or
E_err_Local_req_X_L or
E_err_Local_credit_not_zero_req_X_L_grant_L or
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
E_err_IDLE_req_X_E or E_err_North_req_X_E or E_err_East_req_X_W or E_err_West_req_X_S or E_err_South_req_X_L or
E_err_Local_req_X_N or
E_err_IDLE_req_X_W or E_err_North_req_X_W or E_err_East_req_X_S or E_err_West_req_X_L or E_err_South_req_X_N or
E_err_Local_req_X_E or
E_err_IDLE_req_X_S or E_err_North_req_X_S or E_err_East_req_X_L or E_err_West_req_X_N or E_err_South_req_X_E or
E_err_Local_req_X_W or
E_err_IDLE_req_X_L or E_err_North_req_X_L or E_err_East_req_X_N or E_err_West_req_X_E or E_err_South_req_X_W or
E_err_Local_req_X_S or
E_arbiter_out_err_state_in_onehot or
E_arbiter_out_err_no_request_grants or
E_err_request_IDLE_state or
E_err_request_IDLE_not_Grants or E_err_state_North_Invalid_Grant or E_err_state_East_Invalid_Grant or
E_err_state_West_Invalid_Grant or E_err_state_South_Invalid_Grant or E_err_state_Local_Invalid_Grant or
E_err_Grants_onehot_or_all_zero or
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal or
W_err_IDLE_req_X_N or
W_err_North_req_X_N or
W_err_North_credit_not_zero_req_X_N_grant_N or
W_err_North_credit_zero_or_not_req_X_N_not_grant_N or
W_err_East_req_X_E or
W_err_East_credit_not_zero_req_X_E_grant_E or
W_err_East_credit_zero_or_not_req_X_E_not_grant_E or
W_err_West_req_X_W or
W_err_West_credit_not_zero_req_X_W_grant_W or
W_err_West_credit_zero_or_not_req_X_W_not_grant_W or
W_err_South_req_X_S or
W_err_South_credit_not_zero_req_X_S_grant_S or
W_err_South_credit_zero_or_not_req_X_S_not_grant_S or
W_err_Local_req_X_L or
W_err_Local_credit_not_zero_req_X_L_grant_L or
W_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
W_err_IDLE_req_X_E or W_err_North_req_X_E or W_err_East_req_X_W or W_err_West_req_X_S or W_err_South_req_X_L or
W_err_Local_req_X_N or
W_err_IDLE_req_X_W or W_err_North_req_X_W or W_err_East_req_X_S or W_err_West_req_X_L or W_err_South_req_X_N or
W_err_Local_req_X_E or
W_err_IDLE_req_X_S or W_err_North_req_X_S or W_err_East_req_X_L or W_err_West_req_X_N or W_err_South_req_X_E or
W_err_Local_req_X_W or
W_err_IDLE_req_X_L or W_err_North_req_X_L or W_err_East_req_X_N or W_err_West_req_X_E or W_err_South_req_X_W or
W_err_Local_req_X_S or
W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or
W_err_request_IDLE_state or
W_err_request_IDLE_not_Grants or W_err_state_North_Invalid_Grant or W_err_state_East_Invalid_Grant or
W_err_state_West_Invalid_Grant or W_err_state_South_Invalid_Grant or W_err_state_Local_Invalid_Grant or
W_err_Grants_onehot_or_all_zero or
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal or
S_err_IDLE_req_X_N or
S_err_North_req_X_N or
S_err_North_credit_not_zero_req_X_N_grant_N or
S_err_North_credit_zero_or_not_req_X_N_not_grant_N or
S_err_East_req_X_E or
S_err_East_credit_not_zero_req_X_E_grant_E or
S_err_East_credit_zero_or_not_req_X_E_not_grant_E or
S_err_West_req_X_W or
S_err_West_credit_not_zero_req_X_W_grant_W or
S_err_West_credit_zero_or_not_req_X_W_not_grant_W or
S_err_South_req_X_S or
S_err_South_credit_not_zero_req_X_S_grant_S or
S_err_South_credit_zero_or_not_req_X_S_not_grant_S or
S_err_Local_req_X_L or
S_err_Local_credit_not_zero_req_X_L_grant_L or
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
S_err_IDLE_req_X_E or S_err_North_req_X_E or S_err_East_req_X_W or
S_err_West_req_X_S or S_err_South_req_X_L or S_err_Local_req_X_N or
S_err_IDLE_req_X_W or S_err_North_req_X_W or S_err_East_req_X_S or
S_err_West_req_X_L or S_err_South_req_X_N or S_err_Local_req_X_E or
S_err_IDLE_req_X_S or S_err_North_req_X_S or S_err_East_req_X_L or
S_err_West_req_X_N or S_err_South_req_X_E or S_err_Local_req_X_W or
S_err_IDLE_req_X_L or S_err_North_req_X_L or S_err_East_req_X_N or
S_err_West_req_X_E or S_err_South_req_X_W or S_err_Local_req_X_S or
S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or
S_err_request_IDLE_not_Grants or S_err_state_North_Invalid_Grant or S_err_state_East_Invalid_Grant or
S_err_state_West_Invalid_Grant or S_err_state_South_Invalid_Grant or S_err_state_Local_Invalid_Grant or
S_err_Grants_onehot_or_all_zero or
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal or
L_err_IDLE_req_X_N or
L_err_North_req_X_N or
L_err_North_credit_not_zero_req_X_N_grant_N or
L_err_North_credit_zero_or_not_req_X_N_not_grant_N or
L_err_East_req_X_E or
L_err_East_credit_not_zero_req_X_E_grant_E or
L_err_East_credit_zero_or_not_req_X_E_not_grant_E or
L_err_West_req_X_W or
L_err_West_credit_not_zero_req_X_W_grant_W or
L_err_West_credit_zero_or_not_req_X_W_not_grant_W or
L_err_South_req_X_S or
L_err_South_credit_not_zero_req_X_S_grant_S or
L_err_South_credit_zero_or_not_req_X_S_not_grant_S or
L_err_Local_req_X_L or
L_err_Local_credit_not_zero_req_X_L_grant_L or
L_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
L_err_IDLE_req_X_E or L_err_North_req_X_E or L_err_East_req_X_W or L_err_West_req_X_S or L_err_South_req_X_L or
L_err_Local_req_X_N or
L_err_IDLE_req_X_W or L_err_North_req_X_W or L_err_East_req_X_S or L_err_West_req_X_L or L_err_South_req_X_N or
L_err_Local_req_X_E or
L_err_IDLE_req_X_S or L_err_North_req_X_S or L_err_East_req_X_L or L_err_West_req_X_N or L_err_South_req_X_E or
L_err_Local_req_X_W or
L_err_IDLE_req_X_L or L_err_North_req_X_L or L_err_East_req_X_N or L_err_West_req_X_E or L_err_South_req_X_W or
L_err_Local_req_X_S or
L_arbiter_out_err_state_in_onehot or
L_arbiter_out_err_no_request_grants or
L_err_request_IDLE_state or
L_err_request_IDLE_not_Grants or L_err_state_North_Invalid_Grant or L_err_state_East_Invalid_Grant or
L_err_state_West_Invalid_Grant or L_err_state_South_Invalid_Grant or L_err_state_Local_Invalid_Grant or
L_err_Grants_onehot_or_all_zero;
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- Turn fault checkers
-- FIFO
N2E_turn_fault <= N_FIFO_checkers_ORed or
-- LBDR
N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_tail_empty_Requests_FF_Requests_in or
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
N_err_grants_onehot or
N_err_grants_mismatch or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_E1 or
N_err_dst_addr_cur_addr_not_E1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
N_err_header_not_empty_Req_E_in or
N_err_header_empty_packet_drop_in_packet_drop_equal or
N_err_tail_not_empty_packet_drop_not_packet_drop_in or
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
N_err_packet_drop_order or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
N_err_Requests_state_in_state_not_equal or N_err_East_Req_E or N_err_East_grant_E or N_err_IDLE_Req_E or N_err_IDLE_grant_E or
N_err_North_Req_E or N_err_North_grant_E or N_err_Local_Req_E or N_err_Local_grant_E or N_err_South_Req_E or N_err_South_grant_E or
N_err_West_Req_E or N_err_West_grant_E or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or
N_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_IDLE_req_X_N or E_err_North_req_X_N or
E_err_North_credit_not_zero_req_X_N_grant_N or E_err_North_credit_zero_or_not_req_X_N_not_grant_N or E_err_Local_req_X_N or
E_err_South_req_X_N or E_err_West_req_X_N or E_err_East_req_X_N or E_arbiter_out_err_state_in_onehot or
E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or
W_err_South_req_X_N or W_err_West_req_X_N or W_err_East_req_X_N or err_grant_E_N_sig_not_empty_N_grant_E_N or
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal;
-- FIFO
N2W_turn_fault <= N_FIFO_checkers_ORed or
-- LBDR
N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_tail_empty_Requests_FF_Requests_in or
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
N_err_grants_onehot or
N_err_grants_mismatch or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_W1 or
N_err_dst_addr_cur_addr_not_W1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
N_err_header_not_empty_Req_W_in or
N_err_header_empty_packet_drop_in_packet_drop_equal or
N_err_tail_not_empty_packet_drop_not_packet_drop_in or
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
N_err_packet_drop_order or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
N_err_Requests_state_in_state_not_equal or
N_err_West_Req_W or
N_err_West_grant_W or
N_err_East_Req_W or
N_err_East_grant_W or
N_err_IDLE_Req_W or
N_err_IDLE_grant_W or
N_err_North_Req_W or
N_err_North_grant_W or
N_err_Local_Req_W or
N_err_Local_grant_W or
N_err_South_Req_W or
N_err_South_grant_W or
N_err_state_in_onehot or
N_err_no_request_grants or
N_err_request_no_grants or
N_err_no_Req_W_grant_W or
W_arbiter_out_err_Requests_state_in_state_not_equal or
W_err_IDLE_req_X_N or
W_err_North_req_X_N or
W_err_North_credit_not_zero_req_X_N_grant_N or
W_err_North_credit_zero_or_not_req_X_N_not_grant_N or
W_err_Local_req_X_N or
W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or
W_err_request_IDLE_state or
W_err_request_IDLE_not_Grants or
W_err_Grants_onehot_or_all_zero or
err_grant_W_N_sig_not_empty_N_grant_W_N or
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N or
err_grant_signals_not_empty_grant_W or
err_not_grant_signals_empty_not_grant_W or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or
err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or
err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal;
E2N_turn_fault <= E_FIFO_checkers_ORed or -- FIFO
-- LBDR
E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
E_err_grants_onehot or
E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_N1 or
E_err_dst_addr_cur_addr_not_N1 or
E_err_header_not_empty_faulty_drop_packet_in or
E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
E_err_header_not_empty_faulty_Req_in_all_zero or
E_err_header_not_empty_Req_N_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or
E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
E_err_Requests_state_in_state_not_equal or E_err_IDLE_Req_N or E_err_IDLE_grant_N or E_err_North_Req_N or
E_err_North_grant_N or E_err_Local_Req_N or E_err_Local_grant_N or E_err_South_Req_N or E_err_South_grant_N or
E_err_West_Req_N or E_err_West_grant_N or E_err_East_Req_N or E_err_East_grant_N or E_err_state_in_onehot or
E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_N_grant_N or
N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_East_req_X_E or
N_err_East_credit_not_zero_req_X_E_grant_E or N_err_East_credit_zero_or_not_req_X_E_not_grant_E or
N_err_IDLE_req_X_E or N_err_North_req_X_E or N_err_Local_req_X_E or N_err_South_req_X_E or N_err_West_req_X_E or
N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or
N_err_Grants_onehot_or_all_zero or err_grant_N_E_sig_not_empty_E_grant_N_E or
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E or err_grant_signals_not_empty_grant_N or
err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_N_credit_counter_N_out_increment or
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or
err_grant_N_credit_counter_N_out_decrement or
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal;
E2S_turn_fault <= E_FIFO_checkers_ORed or -- FIFO
-- LBDR
E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
E_err_grants_onehot or
E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_S1 or
E_err_dst_addr_cur_addr_not_S1 or
E_err_header_not_empty_faulty_drop_packet_in or
E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
E_err_header_not_empty_faulty_Req_in_all_zero or
E_err_header_not_empty_Req_S_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or
E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
E_err_Requests_state_in_state_not_equal or E_err_South_Req_S or E_err_South_grant_S or E_err_West_Req_S or E_err_West_grant_S or
E_err_East_Req_S or E_err_East_grant_S or E_err_IDLE_Req_S or E_err_IDLE_grant_S or E_err_North_Req_S or E_err_North_grant_S or
E_err_Local_Req_S or E_err_Local_grant_S or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or
E_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_East_req_X_E or
S_err_East_credit_not_zero_req_X_E_grant_E or S_err_East_credit_zero_or_not_req_X_E_not_grant_E or S_err_IDLE_req_X_E or
S_err_North_req_X_E or S_err_Local_req_X_E or S_err_South_req_X_E or S_err_West_req_X_E or S_arbiter_out_err_state_in_onehot or
S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or
err_grant_S_E_sig_not_empty_E_grant_S_E or err_not_grant_S_E_sig_or_empty_E_not_grant_S_E or err_grant_signals_not_empty_grant_S or
err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal;
-- FIFO
W2N_turn_fault <= W_FIFO_checkers_ORed or
-- LBDR
W_err_header_empty_Requests_FF_Requests_in or
W_err_tail_Requests_in_all_zero or
W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
W_err_grants_onehot or
W_err_grants_mismatch or
W_err_header_tail_Requests_FF_Requests_in or
W_err_dst_addr_cur_addr_N1 or
W_err_dst_addr_cur_addr_not_N1 or
W_err_header_not_empty_faulty_drop_packet_in or
W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
W_err_header_not_empty_faulty_Req_in_all_zero or
W_err_header_not_empty_Req_N_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or
W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
W_err_packet_drop_order or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
W_err_Requests_state_in_state_not_equal or W_err_IDLE_Req_N or W_err_IDLE_grant_N or W_err_North_Req_N or W_err_North_grant_N or
W_err_Local_Req_N or W_err_Local_grant_N or W_err_South_Req_N or W_err_South_grant_N or W_err_West_Req_N or W_err_West_grant_N or
W_err_East_Req_N or W_err_East_grant_N or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or
W_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_West_req_X_W or
N_err_West_credit_not_zero_req_X_W_grant_W or N_err_West_credit_zero_or_not_req_X_W_not_grant_W or N_err_East_req_X_W or
N_err_IDLE_req_X_W or N_err_North_req_X_W or N_err_Local_req_X_W or N_err_South_req_X_W or N_arbiter_out_err_state_in_onehot or
N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or
err_grant_N_W_sig_not_empty_W_grant_N_W or err_not_grant_N_W_sig_or_empty_W_not_grant_N_W or err_grant_signals_not_empty_grant_N or
err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal;
-- FIFO
W2S_turn_fault <= W_FIFO_checkers_ORed or
-- LBDR
W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or
W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_S1 or W_err_dst_addr_cur_addr_not_S1 or
W_err_header_not_empty_faulty_drop_packet_in or W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
W_err_header_not_empty_faulty_Req_in_all_zero or W_err_header_not_empty_Req_S_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
W_err_packet_drop_order or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
W_err_Requests_state_in_state_not_equal or W_err_South_Req_S or W_err_South_grant_S or W_err_West_Req_S or W_err_West_grant_S or
W_err_East_Req_S or W_err_East_grant_S or W_err_IDLE_Req_S or W_err_IDLE_grant_S or W_err_North_Req_S or W_err_North_grant_S or
W_err_Local_Req_S or W_err_Local_grant_S or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or
W_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_West_req_X_W or
S_err_West_credit_not_zero_req_X_W_grant_W or S_err_West_credit_zero_or_not_req_X_W_not_grant_W or S_err_East_req_X_W or
S_err_IDLE_req_X_W or S_err_North_req_X_W or S_err_Local_req_X_W or S_err_South_req_X_W or S_arbiter_out_err_state_in_onehot or
S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or
err_grant_S_W_sig_not_empty_W_grant_S_W or err_not_grant_S_W_sig_or_empty_W_not_grant_S_W or err_grant_signals_not_empty_grant_S or
err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal;
-- FIFO
S2E_turn_fault <= S_FIFO_checkers_ORed or
-- LBDR
S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_E1 or S_err_dst_addr_cur_addr_not_E1 or
S_err_header_not_empty_faulty_drop_packet_in or S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
S_err_header_not_empty_faulty_Req_in_all_zero or S_err_header_not_empty_Req_E_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
S_err_Requests_state_in_state_not_equal or S_err_East_Req_E or S_err_East_grant_E or S_err_IDLE_Req_E or S_err_IDLE_grant_E or
S_err_North_Req_E or S_err_North_grant_E or S_err_Local_Req_E or S_err_Local_grant_E or S_err_South_Req_E or S_err_South_grant_E or
S_err_West_Req_E or S_err_West_grant_E or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or
S_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_South_req_X_S or
E_err_South_credit_not_zero_req_X_S_grant_S or E_err_South_credit_zero_or_not_req_X_S_not_grant_S or E_err_West_req_X_S or
E_err_East_req_X_S or E_err_IDLE_req_X_S or E_err_North_req_X_S or E_err_Local_req_X_S or E_arbiter_out_err_state_in_onehot or
E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or
err_grant_E_S_sig_not_empty_S_grant_E_S or err_not_grant_E_S_sig_or_empty_S_not_grant_E_S or err_grant_signals_not_empty_grant_E or
err_not_grant_signals_empty_not_grant_E or err_grants_valid_not_match or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or
err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or
err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal;
-- FIFO
S2W_turn_fault <= S_FIFO_checkers_ORed or
-- LBDR
S_err_header_empty_Requests_FF_Requests_in or
S_err_tail_Requests_in_all_zero or
S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
S_err_grants_onehot or
S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or
S_err_dst_addr_cur_addr_W1 or
S_err_dst_addr_cur_addr_not_W1 or
S_err_header_not_empty_faulty_drop_packet_in or
S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
S_err_header_not_empty_faulty_Req_in_all_zero or
S_err_header_not_empty_Req_W_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or
S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
S_err_Requests_state_in_state_not_equal or S_err_West_Req_W or S_err_West_grant_W or S_err_East_Req_W or S_err_East_grant_W or
S_err_IDLE_Req_W or S_err_IDLE_grant_W or S_err_North_Req_W or S_err_North_grant_W or S_err_Local_Req_W or S_err_Local_grant_W or
S_err_South_Req_W or S_err_South_grant_W or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or
S_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_South_req_X_S or
W_err_South_credit_not_zero_req_X_S_grant_S or W_err_South_credit_zero_or_not_req_X_S_not_grant_S or W_err_West_req_X_S or
W_err_East_req_X_S or W_err_IDLE_req_X_S or W_err_North_req_X_S or W_err_Local_req_X_S or W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or
err_grant_W_S_sig_not_empty_S_grant_W_S or err_not_grant_W_S_sig_or_empty_S_not_grant_W_S or err_grant_signals_not_empty_grant_W or
err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal;
-- Path fault checkers
-- FIFO
N2S_path_fault <= N_FIFO_checkers_ORed or
-- LBDR
N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_tail_empty_Requests_FF_Requests_in or
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
N_err_grants_onehot or
N_err_grants_mismatch or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_S1 or
N_err_dst_addr_cur_addr_not_S1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
N_err_header_not_empty_Req_S_in or
N_err_header_empty_packet_drop_in_packet_drop_equal or
N_err_tail_not_empty_packet_drop_not_packet_drop_in or
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
N_err_packet_drop_order or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
N_err_Requests_state_in_state_not_equal or N_err_South_Req_S or N_err_South_grant_S or N_err_West_Req_S or N_err_West_grant_S or
N_err_East_Req_S or N_err_East_grant_S or N_err_IDLE_Req_S or N_err_IDLE_grant_S or N_err_North_Req_S or N_err_North_grant_S or
N_err_Local_Req_S or N_err_Local_grant_S or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or
N_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_IDLE_req_X_N or S_err_North_req_X_N or
S_err_North_credit_not_zero_req_X_N_grant_N or S_err_North_credit_zero_or_not_req_X_N_not_grant_N or S_err_Local_req_X_N or
S_err_South_req_X_N or S_err_West_req_X_N or S_err_East_req_X_N or S_arbiter_out_err_state_in_onehot or
S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or
err_grant_S_N_sig_not_empty_N_grant_S_N or err_not_grant_S_N_sig_or_empty_N_not_grant_S_N or err_grant_signals_not_empty_grant_S or
err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal;
-- FIFO
S2N_path_fault <= S_FIFO_checkers_ORed or
-- LBDR
S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_N1 or S_err_dst_addr_cur_addr_not_N1 or
S_err_header_not_empty_faulty_drop_packet_in or S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
S_err_header_not_empty_faulty_Req_in_all_zero or S_err_header_not_empty_Req_N_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
S_err_Requests_state_in_state_not_equal or S_err_IDLE_Req_N or S_err_IDLE_grant_N or S_err_North_Req_N or S_err_North_grant_N or
S_err_Local_Req_N or S_err_Local_grant_N or S_err_South_Req_N or S_err_South_grant_N or S_err_West_Req_N or S_err_West_grant_N or
S_err_East_Req_N or S_err_East_grant_N or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or
S_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_South_req_X_S or
N_err_South_credit_not_zero_req_X_S_grant_S or N_err_South_credit_zero_or_not_req_X_S_not_grant_S or
N_err_West_req_X_S or N_err_East_req_X_S or N_err_IDLE_req_X_S or N_err_North_req_X_S or N_err_Local_req_X_S or
N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or
N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or err_grant_N_S_sig_not_empty_S_grant_N_S or
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or
err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or
err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal;
-- FIFO
E2W_path_fault <= E_FIFO_checkers_ORed or
-- LBDR
E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_W1 or E_err_dst_addr_cur_addr_not_W1 or
E_err_header_not_empty_faulty_drop_packet_in or E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
E_err_header_not_empty_faulty_Req_in_all_zero or E_err_header_not_empty_Req_W_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
E_err_Requests_state_in_state_not_equal or E_err_West_Req_W or E_err_West_grant_W or E_err_East_Req_W or E_err_East_grant_W or
E_err_IDLE_Req_W or E_err_IDLE_grant_W or E_err_North_Req_W or E_err_North_grant_W or E_err_Local_Req_W or E_err_Local_grant_W or
E_err_South_Req_W or E_err_South_grant_W or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or
E_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_East_req_X_E or
W_err_East_credit_not_zero_req_X_E_grant_E or W_err_East_credit_zero_or_not_req_X_E_not_grant_E or W_err_IDLE_req_X_E or
W_err_North_req_X_E or W_err_Local_req_X_E or W_err_South_req_X_E or W_err_West_req_X_E or W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or
err_grant_W_E_sig_not_empty_E_grant_W_E or err_not_grant_W_E_sig_or_empty_E_not_grant_W_E or err_grant_signals_not_empty_grant_W or
err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal;
-- FIFO
W2E_path_fault <= W_FIFO_checkers_ORed or
-- LBDR
W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or
W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_E1 or W_err_dst_addr_cur_addr_not_E1 or
W_err_header_not_empty_faulty_drop_packet_in or W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
W_err_header_not_empty_faulty_Req_in_all_zero or W_err_header_not_empty_Req_E_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
W_err_Requests_state_in_state_not_equal or W_err_East_Req_E or W_err_East_grant_E or W_err_IDLE_Req_E or
W_err_IDLE_grant_E or W_err_North_Req_E or W_err_North_grant_E or W_err_Local_Req_E or W_err_Local_grant_E or
W_err_South_Req_E or W_err_South_grant_E or W_err_West_Req_E or W_err_West_grant_E or W_err_state_in_onehot or
W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or
W_err_West_req_X_W or E_err_West_credit_not_zero_req_X_W_grant_W or E_err_West_credit_zero_or_not_req_X_W_not_grant_W or
E_err_East_req_X_W or E_err_IDLE_req_X_W or E_err_North_req_X_W or E_err_Local_req_X_W or E_err_South_req_X_W or
E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or
E_err_Grants_onehot_or_all_zero or err_grant_E_W_sig_not_empty_W_grant_E_W or err_not_grant_E_W_sig_or_empty_W_not_grant_E_W or
err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal;
-- Checkers for Paths/turns from/to Local port
-- FIFO
L2N_fault <= L_FIFO_checkers_ORed or
-- LBDR
L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_N1 or L_err_dst_addr_cur_addr_not_N1 or
L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_N_in or
L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
L_err_packet_drop_order or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
L_err_Requests_state_in_state_not_equal or L_err_IDLE_Req_N or L_err_IDLE_grant_N or L_err_North_Req_N or L_err_North_grant_N or
L_err_Local_Req_N or L_err_Local_grant_N or L_err_South_Req_N or L_err_South_grant_N or L_err_West_Req_N or L_err_West_grant_N or
L_err_East_Req_N or L_err_East_grant_N or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or
L_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_Local_req_X_L or
N_err_Local_credit_not_zero_req_X_L_grant_L or N_err_Local_credit_zero_or_not_req_X_L_not_grant_L or N_err_South_req_X_L or
N_err_West_req_X_L or N_err_East_req_X_L or N_err_IDLE_req_X_L or N_err_North_req_X_L or N_arbiter_out_err_state_in_onehot or
N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or
err_grant_N_L_sig_not_empty_L_grant_N_L or err_not_grant_N_L_sig_or_empty_L_not_grant_N_L or err_grant_signals_not_empty_grant_N or
err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal;
-- FIFO
L2E_fault <= L_FIFO_checkers_ORed or
-- LBDR
L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_E1 or L_err_dst_addr_cur_addr_not_E1 or
L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_E_in or L_err_header_empty_packet_drop_in_packet_drop_equal or
L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
L_err_Requests_state_in_state_not_equal or L_err_East_Req_E or L_err_East_grant_E or L_err_IDLE_Req_E or L_err_IDLE_grant_E or
L_err_North_Req_E or L_err_North_grant_E or L_err_Local_Req_E or L_err_Local_grant_E or L_err_South_Req_E or L_err_South_grant_E or
L_err_West_Req_E or L_err_West_grant_E or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or
L_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_Local_req_X_L or
E_err_Local_credit_not_zero_req_X_L_grant_L or E_err_Local_credit_zero_or_not_req_X_L_not_grant_L or E_err_South_req_X_L or
E_err_West_req_X_L or E_err_East_req_X_L or E_err_IDLE_req_X_L or E_err_North_req_X_L or E_arbiter_out_err_state_in_onehot or
E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or
err_grant_E_L_sig_not_empty_L_grant_E_L or err_not_grant_E_L_sig_or_empty_L_not_grant_E_L or err_grant_signals_not_empty_grant_E or
err_not_grant_signals_empty_not_grant_E or err_grants_valid_not_match or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal;
-- FIFO
L2W_fault <= L_FIFO_checkers_ORed or
-- LBDR
L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_W1 or L_err_dst_addr_cur_addr_not_W1 or
L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_W_in or L_err_header_empty_packet_drop_in_packet_drop_equal or
L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
L_err_Requests_state_in_state_not_equal or L_err_West_Req_W or L_err_West_grant_W or L_err_East_Req_W or L_err_East_grant_W or
L_err_IDLE_Req_W or L_err_IDLE_grant_W or L_err_North_Req_W or L_err_North_grant_W or L_err_Local_Req_W or L_err_Local_grant_W or
L_err_South_Req_W or L_err_South_grant_W or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or
L_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_Local_req_X_L or
W_err_Local_credit_not_zero_req_X_L_grant_L or W_err_Local_credit_zero_or_not_req_X_L_not_grant_L or W_err_South_req_X_L or
W_err_West_req_X_L or W_err_East_req_X_L or W_err_IDLE_req_X_L or W_err_North_req_X_L or W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or
err_grant_W_L_sig_not_empty_L_grant_W_L or err_not_grant_W_L_sig_or_empty_L_not_grant_W_L or err_grant_signals_not_empty_grant_W or
err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal;
-- FIFO
L2S_fault <= L_FIFO_checkers_ORed or
-- LBDR
L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_S1 or L_err_dst_addr_cur_addr_not_S1 or
L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_S_in or
L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
L_err_packet_drop_order or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
L_err_Requests_state_in_state_not_equal or L_err_South_Req_S or L_err_South_grant_S or L_err_West_Req_S or L_err_West_grant_S or
L_err_East_Req_S or L_err_East_grant_S or L_err_IDLE_Req_S or L_err_IDLE_grant_S or L_err_North_Req_S or L_err_North_grant_S or
L_err_Local_Req_S or L_err_Local_grant_S or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or
L_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_Local_req_X_L or
S_err_Local_credit_not_zero_req_X_L_grant_L or S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or S_err_South_req_X_L or
S_err_West_req_X_L or S_err_East_req_X_L or S_err_IDLE_req_X_L or S_err_North_req_X_L or S_arbiter_out_err_state_in_onehot or
S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or
err_grant_S_L_sig_not_empty_L_grant_S_L or err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or err_grant_signals_not_empty_grant_S or
err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal;
-- FIFO
N2L_fault <= N_FIFO_checkers_ORed or
-- LBDR
N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_tail_empty_Requests_FF_Requests_in or
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
N_err_grants_onehot or
N_err_grants_mismatch or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_Req_L_in or
N_err_dst_addr_cur_addr_not_Req_L_in or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
--N_err_header_not_empty_Req_L_in or
N_err_header_empty_packet_drop_in_packet_drop_equal or
N_err_tail_not_empty_packet_drop_not_packet_drop_in or
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
N_err_packet_drop_order or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
N_err_Requests_state_in_state_not_equal or N_err_Local_Req_L or N_err_Local_grant_L or N_err_South_Req_L or N_err_South_grant_L or
N_err_West_Req_L or N_err_West_grant_L or N_err_East_Req_L or N_err_East_grant_L or N_err_IDLE_Req_L or N_err_IDLE_grant_L or
N_err_North_Req_L or N_err_North_grant_L or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or
N_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_IDLE_req_X_N or L_err_North_req_X_N or
L_err_North_credit_not_zero_req_X_N_grant_N or L_err_North_credit_zero_or_not_req_X_N_not_grant_N or L_err_Local_req_X_N or
L_err_South_req_X_N or L_err_West_req_X_N or L_err_East_req_X_N or L_arbiter_out_err_state_in_onehot or
L_arbiter_out_err_no_request_grants or
L_err_request_IDLE_state or
L_err_request_IDLE_not_Grants or
L_err_Grants_onehot_or_all_zero or
err_grant_L_N_sig_not_empty_N_grant_L_N or
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N or
err_grant_signals_not_empty_grant_L or
err_not_grant_signals_empty_not_grant_L or
err_grants_valid_not_match or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or
err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or
err_grant_L_credit_counter_L_out_decrement or
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal;
-- FIFO
E2L_fault <= E_FIFO_checkers_ORed or
-- LBDR
E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
E_err_grants_onehot or
E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_Req_L_in or
E_err_dst_addr_cur_addr_not_Req_L_in or
E_err_header_not_empty_faulty_drop_packet_in or
E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
E_err_header_not_empty_faulty_Req_in_all_zero or
--E_err_header_not_empty_Req_L_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or
E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
E_err_Requests_state_in_state_not_equal or E_err_Local_Req_L or E_err_Local_grant_L or E_err_South_Req_L or E_err_South_grant_L or
E_err_West_Req_L or E_err_West_grant_L or E_err_East_Req_L or E_err_East_grant_L or E_err_IDLE_Req_L or E_err_IDLE_grant_L or
E_err_North_Req_L or E_err_North_grant_L or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or
E_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_East_req_X_E or
L_err_East_credit_not_zero_req_X_E_grant_E or L_err_East_credit_zero_or_not_req_X_E_not_grant_E or L_err_IDLE_req_X_E or
L_err_North_req_X_E or L_err_Local_req_X_E or L_err_South_req_X_E or L_err_West_req_X_E or L_arbiter_out_err_state_in_onehot or
L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or
err_grant_L_E_sig_not_empty_E_grant_L_E or err_not_grant_L_E_sig_or_empty_E_not_grant_L_E or err_grant_signals_not_empty_grant_L or
err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal;
-- FIFO
W2L_fault <= W_FIFO_checkers_ORed or
-- LBDR
W_err_header_empty_Requests_FF_Requests_in or
W_err_tail_Requests_in_all_zero or
W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
W_err_grants_onehot or
W_err_grants_mismatch or
W_err_header_tail_Requests_FF_Requests_in or
W_err_dst_addr_cur_addr_Req_L_in or
W_err_dst_addr_cur_addr_not_Req_L_in or
W_err_header_not_empty_faulty_drop_packet_in or
W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
W_err_header_not_empty_faulty_Req_in_all_zero or
--W_err_header_not_empty_Req_L_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or
W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
W_err_packet_drop_order or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
W_err_Requests_state_in_state_not_equal or W_err_Local_Req_L or W_err_Local_grant_L or W_err_South_Req_L or
W_err_South_grant_L or W_err_West_Req_L or W_err_West_grant_L or W_err_East_Req_L or W_err_East_grant_L or
W_err_IDLE_Req_L or W_err_IDLE_grant_L or W_err_North_Req_L or W_err_North_grant_L or W_err_state_in_onehot or
W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_L_grant_L or
L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_West_req_X_W or L_err_West_credit_not_zero_req_X_W_grant_W or
L_err_West_credit_zero_or_not_req_X_W_not_grant_W or L_err_East_req_X_W or L_err_IDLE_req_X_W or L_err_North_req_X_W or
L_err_Local_req_X_W or L_err_South_req_X_W or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or
L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or
err_grant_L_W_sig_not_empty_W_grant_L_W or err_not_grant_L_W_sig_or_empty_W_not_grant_L_W or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal;
-- FIFO
S2L_fault <= S_FIFO_checkers_ORed or
-- LBDR
S_err_header_empty_Requests_FF_Requests_in or
S_err_tail_Requests_in_all_zero or
S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
S_err_grants_onehot or
S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or
S_err_dst_addr_cur_addr_Req_L_in or
S_err_dst_addr_cur_addr_not_Req_L_in or
S_err_header_not_empty_faulty_drop_packet_in or
S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
S_err_header_not_empty_faulty_Req_in_all_zero or
--S_err_header_not_empty_Req_L_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or
S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
S_err_Requests_state_in_state_not_equal or S_err_Local_Req_L or S_err_Local_grant_L or S_err_South_Req_L or
S_err_South_grant_L or S_err_West_Req_L or S_err_West_grant_L or S_err_East_Req_L or S_err_East_grant_L or
S_err_IDLE_Req_L or S_err_IDLE_grant_L or S_err_North_Req_L or S_err_North_grant_L or S_err_state_in_onehot or
S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_L_grant_L or
L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_South_req_X_S or L_err_South_credit_not_zero_req_X_S_grant_S or
L_err_South_credit_zero_or_not_req_X_S_not_grant_S or L_err_West_req_X_S or L_err_East_req_X_S or L_err_IDLE_req_X_S or
L_err_North_req_X_S or L_err_Local_req_X_S or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or
L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or
err_grant_L_S_sig_not_empty_S_grant_L_S or err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or err_grant_signals_not_empty_grant_L or
err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or
err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal;
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- Link faults and turn faults
-- The order of the turns/paths from left to right (MSB to LSB) -> 20 bits
-- N2E, N2W, E2N, E2S,
-- W2N, W2S, S2E, S2W,
-- N2S, S2N, E2W, W2E,
-- L2N, L2E, L2W, L2S,
-- N2L, E2L, W2L, S2L
------------------------------------------------------------------------------------------------------------------------------
-- Taking classified fault information to output
------------------------------------------------------------------------------------------------------------------------------
turn_faults <= faulty_N2E_turn_fault & faulty_N2W_turn_fault & faulty_E2N_turn_fault & faulty_E2S_turn_fault &
faulty_W2N_turn_fault & faulty_W2S_turn_fault & faulty_S2E_turn_fault & faulty_S2W_turn_fault &
faulty_N2S_path_fault & faulty_S2N_path_fault & faulty_E2W_path_fault & faulty_W2E_path_fault &
faulty_L2N_fault & faulty_L2E_fault & faulty_L2W_fault & faulty_L2S_fault &
faulty_N2L_fault & faulty_E2L_fault & faulty_W2L_fault & faulty_S2L_fault; -- 20 bits because of turn/path faults
link_faults <= sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L;
------------------------------------------------------------------------------------------------------------------------------
-- Taking non-classified fault information to output
------------------------------------------------------------------------------------------------------------------------------
--turn_faults_async <= N2E_turn_fault & N2W_turn_fault & E2N_turn_fault & E2S_turn_fault &
-- W2N_turn_fault & W2S_turn_fault & S2E_turn_fault & S2W_turn_fault &
-- N2S_path_fault & S2N_path_fault & E2W_path_fault & W2E_path_fault &
-- L2N_fault & L2E_fault & L2W_fault & L2S_fault &
-- N2L_fault & E2L_fault & W2L_fault & S2L_fault; -- 20 bits because of turn/path faults
--link_faults_async <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L;
------------------------------------------------------------------------------------------------------------------------------
Faulty_N_out <= sig_Faulty_N_out;
Faulty_E_out <= sig_Faulty_E_out;
Faulty_W_out <= sig_Faulty_W_out;
Faulty_S_out <= sig_Faulty_S_out;
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the counter_threshold modules
CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N,
Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out);
CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E,
Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out);
CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W,
Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out);
CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S,
Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out);
CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L,
Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Checker Counter Threshold modules
-- Turn faults
CHK_CT_N2E_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => N2E_turn_fault, Healthy_packet => not_N2E_turn_fault,
Intermittent => intermittent_N2E_turn_fault, Faulty => faulty_N2E_turn_fault);
CHK_CT_N2W_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => N2W_turn_fault, Healthy_packet => not_N2W_turn_fault,
Intermittent => intermittent_N2W_turn_fault, Faulty => faulty_N2W_turn_fault);
CHK_CT_E2N_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => E2N_turn_fault, Healthy_packet => not_E2N_turn_fault,
Intermittent => intermittent_E2N_turn_fault, Faulty => faulty_E2N_turn_fault);
CHK_CT_E2S_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => E2S_turn_fault, Healthy_packet => not_E2S_turn_fault,
Intermittent => intermittent_E2S_turn_fault, Faulty => faulty_E2S_turn_fault);
CHK_CT_W2N_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => W2N_turn_fault, Healthy_packet => not_W2N_turn_fault,
Intermittent => intermittent_W2N_turn_fault, Faulty => faulty_W2N_turn_fault);
CHK_CT_W2S_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => W2S_turn_fault, Healthy_packet => not_W2S_turn_fault,
Intermittent => intermittent_W2S_turn_fault, Faulty => faulty_W2S_turn_fault);
CHK_CT_S2E_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => S2E_turn_fault, Healthy_packet => not_S2E_turn_fault,
Intermittent => intermittent_S2E_turn_fault, Faulty => faulty_S2E_turn_fault);
CHK_CT_S2W_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => S2W_turn_fault, Healthy_packet => not_S2W_turn_fault,
Intermittent => intermittent_S2W_turn_fault, Faulty => faulty_S2W_turn_fault);
--Path faults
CHK_CT_N2S_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => N2S_path_fault, Healthy_packet => not_N2S_path_fault,
Intermittent => intermittent_N2S_path_fault, Faulty => faulty_N2S_path_fault);
CHK_CT_S2N_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => S2N_path_fault, Healthy_packet => not_S2N_path_fault,
Intermittent => intermittent_S2N_path_fault, Faulty => faulty_S2N_path_fault);
CHK_CT_E2W_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => E2W_path_fault, Healthy_packet => not_E2W_path_fault,
Intermittent => intermittent_E2W_path_fault, Faulty => faulty_E2W_path_fault);
CHK_CT_W2E_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => W2E_path_fault, Healthy_packet => not_W2E_path_fault,
Intermittent => intermittent_W2E_path_fault, Faulty => faulty_W2E_path_fault);
-- Local port related faults (to/from local port)
CHK_CT_L2N_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => L2N_fault, Healthy_packet => not_L2N_fault,
Intermittent => intermittent_L2N_fault, Faulty => faulty_L2N_fault);
CHK_CT_L2E_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => L2E_fault, Healthy_packet => not_L2E_fault,
Intermittent => intermittent_L2E_fault, Faulty => faulty_L2E_fault);
CHK_CT_L2W_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => L2W_fault, Healthy_packet => not_L2W_fault,
Intermittent => intermittent_L2W_fault, Faulty => faulty_L2W_fault);
CHK_CT_L2S_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => L2S_fault, Healthy_packet => not_L2S_fault,
Intermittent => intermittent_L2S_fault, Faulty => faulty_L2S_fault);
CHK_CT_N2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => N2L_fault, Healthy_packet => not_N2L_fault,
Intermittent => intermittent_N2L_fault, Faulty => faulty_N2L_fault);
CHK_CT_E2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => E2L_fault, Healthy_packet => not_E2L_fault,
Intermittent => intermittent_E2L_fault, Faulty => faulty_E2L_fault);
CHK_CT_W2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => W2L_fault, Healthy_packet => not_W2L_fault,
Intermittent => intermittent_W2L_fault, Faulty => faulty_W2L_fault);
CHK_CT_S2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => S2L_fault, Healthy_packet => not_S2L_fault,
Intermittent => intermittent_S2L_fault, Faulty => faulty_S2L_fault);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- All the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_FIFO_to_N_FIFO, SO=> fault_DO_serial_N_FIFO_to_E_FIFO,
-- Checker outputs
-- Functional checkers
err_empty_full => N_err_empty_full, err_empty_read_en => N_err_empty_read_en, err_full_write_en => N_err_full_write_en,
err_state_in_onehot => N_err_state_in_onehot, err_read_pointer_in_onehot => N_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => N_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => N_err_write_en_write_pointer,
err_not_write_en_write_pointer => N_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => N_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => N_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => N_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => N_err_read_pointer_write_pointer_full,
err_read_pointer_increment => N_err_read_pointer_increment,
err_read_pointer_not_increment => N_err_read_pointer_not_increment,
err_write_en => N_err_write_en,
err_not_write_en => N_err_not_write_en,
err_not_write_en1 => N_err_not_write_en1,
err_not_write_en2 => N_err_not_write_en2,
err_read_en_mismatch => N_err_read_en_mismatch,
err_read_en_mismatch1 => N_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => N_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => N_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => N_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => N_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => N_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => N_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => N_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => N_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => N_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => N_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => N_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => N_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => N_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => N_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => N_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => N_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => N_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => N_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => N_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => N_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => N_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_N_FIFO_to_E_FIFO, SO=> fault_DO_serial_E_FIFO_to_W_FIFO,
-- Checker outputs
-- Functional checkers
err_empty_full => E_err_empty_full, err_empty_read_en => E_err_empty_read_en, err_full_write_en => E_err_full_write_en,
err_state_in_onehot => E_err_state_in_onehot, err_read_pointer_in_onehot => E_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => E_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => E_err_write_en_write_pointer,
err_not_write_en_write_pointer => E_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => E_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => E_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => E_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => E_err_read_pointer_write_pointer_full,
err_read_pointer_increment => E_err_read_pointer_increment,
err_read_pointer_not_increment => E_err_read_pointer_not_increment,
err_write_en => E_err_write_en,
err_not_write_en => E_err_not_write_en,
err_not_write_en1 => E_err_not_write_en1,
err_not_write_en2 => E_err_not_write_en2,
err_read_en_mismatch => E_err_read_en_mismatch,
err_read_en_mismatch1 => E_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => E_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => E_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => E_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => E_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => E_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => E_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => E_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => E_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => E_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => E_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => E_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => E_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => E_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => E_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => E_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => E_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => E_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => E_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => E_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => E_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => E_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_FIFO_to_W_FIFO, SO=> fault_DO_serial_W_FIFO_to_S_FIFO,
-- Checker outputs
-- Functional checkers
err_empty_full => W_err_empty_full, err_empty_read_en => W_err_empty_read_en, err_full_write_en => W_err_full_write_en,
err_state_in_onehot => W_err_state_in_onehot, err_read_pointer_in_onehot => W_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => W_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => W_err_write_en_write_pointer,
err_not_write_en_write_pointer => W_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => W_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => W_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => W_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => W_err_read_pointer_write_pointer_full,
err_read_pointer_increment => W_err_read_pointer_increment,
err_read_pointer_not_increment => W_err_read_pointer_not_increment,
err_write_en => W_err_write_en,
err_not_write_en => W_err_not_write_en,
err_not_write_en1 => W_err_not_write_en1,
err_not_write_en2 => W_err_not_write_en2,
err_read_en_mismatch => W_err_read_en_mismatch,
err_read_en_mismatch1 => W_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => W_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => W_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => W_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => W_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => W_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => W_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => W_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => W_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => W_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => W_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => W_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => W_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => W_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => W_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => W_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => W_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => W_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => W_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => W_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => W_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => W_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_FIFO_to_S_FIFO, SO=> fault_DO_serial_S_FIFO_to_L_LBDR,
-- Checker outputs
-- Functional checkers
err_empty_full => S_err_empty_full,
err_empty_read_en => S_err_empty_read_en,
err_full_write_en => S_err_full_write_en,
err_state_in_onehot => S_err_state_in_onehot,
err_read_pointer_in_onehot => S_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => S_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => S_err_write_en_write_pointer,
err_not_write_en_write_pointer => S_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => S_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => S_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => S_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => S_err_read_pointer_write_pointer_full,
err_read_pointer_increment => S_err_read_pointer_increment,
err_read_pointer_not_increment => S_err_read_pointer_not_increment,
err_write_en => S_err_write_en,
err_not_write_en => S_err_not_write_en,
err_not_write_en1 => S_err_not_write_en1,
err_not_write_en2 => S_err_not_write_en2,
err_read_en_mismatch => S_err_read_en_mismatch,
err_read_en_mismatch1 => S_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => S_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => S_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => S_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => S_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => S_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => S_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => S_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => S_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => S_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => S_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => S_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => S_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => S_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => S_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => S_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => S_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => S_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => S_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => S_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => S_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> SI, SO=> fault_DO_serial_L_FIFO_to_N_FIFO,
-- Checker outputs
-- Functional checkers
err_empty_full => L_err_empty_full, err_empty_read_en => L_err_empty_read_en, err_full_write_en => L_err_full_write_en,
err_state_in_onehot => L_err_state_in_onehot, err_read_pointer_in_onehot => L_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => L_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => L_err_write_en_write_pointer,
err_not_write_en_write_pointer => L_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => L_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => L_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => L_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => L_err_read_pointer_write_pointer_full,
err_read_pointer_increment => L_err_read_pointer_increment,
err_read_pointer_not_increment => L_err_read_pointer_not_increment,
err_write_en => L_err_write_en,
err_not_write_en => L_err_not_write_en,
err_not_write_en1 => L_err_not_write_en1,
err_not_write_en2 => L_err_not_write_en2,
err_read_en_mismatch => L_err_read_en_mismatch,
err_read_en_mismatch1 => L_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => L_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => L_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => L_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => L_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => L_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => L_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => L_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => L_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => L_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => L_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => L_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => L_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => L_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => L_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => L_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => L_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => L_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => L_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => L_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => L_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
parity_LBDR_N: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_N, empty_N, LBDR_Fault_N);
parity_LBDR_E: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_E, empty_E, LBDR_Fault_E);
parity_LBDR_W: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_W, empty_W, LBDR_Fault_W);
parity_LBDR_S: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_S, empty_S, LBDR_Fault_S);
parity_LBDR_L: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_L, empty_L, LBDR_Fault_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
--- all the LBDRs
LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_N, packet_drop_order => packet_drop_order_N,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_LBDR_to_N_LBDR, SO=> fault_DO_serial_N_LBDR_to_E_LBDR,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => N_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => N_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => N_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => N_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => N_err_grants_onehot,
err_grants_mismatch => N_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => N_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => N_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => N_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => N_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => N_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => N_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => N_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => N_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => N_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => N_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => N_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => N_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => N_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => N_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => N_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => N_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => N_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => N_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => N_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => N_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => N_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_E, packet_drop_order => packet_drop_order_E,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_N_LBDR_to_E_LBDR, SO=> fault_DO_serial_E_LBDR_to_W_LBDR,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => E_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => E_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => E_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => E_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => E_err_grants_onehot,
err_grants_mismatch => E_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => E_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => E_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => E_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => E_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => E_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => E_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => E_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => E_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => E_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => E_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => E_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => E_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => E_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => E_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => E_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => E_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => E_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => E_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => E_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => E_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => E_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_W, packet_drop_order => packet_drop_order_W,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_LBDR_to_W_LBDR, SO=> fault_DO_serial_W_LBDR_to_S_LBDR,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => W_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => W_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => W_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => W_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => W_err_grants_onehot,
err_grants_mismatch => W_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => W_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => W_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => W_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => W_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => W_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => W_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => W_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => W_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => W_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => W_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => W_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => W_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => W_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => W_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => W_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => W_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => W_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => W_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => W_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => W_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => W_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_S, packet_drop_order => packet_drop_order_S,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_LBDR_to_S_LBDR, SO=> fault_DO_serial_S_LBDR_to_Allocator,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => S_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => S_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => S_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => S_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => S_err_grants_onehot,
err_grants_mismatch => S_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => S_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => S_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => S_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => S_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => S_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => S_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => S_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => S_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => S_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => S_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => S_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => S_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => S_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => S_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => S_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => S_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => S_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => S_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => S_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_L, packet_drop_order => packet_drop_order_L,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_FIFO_to_L_LBDR, SO=> fault_DO_serial_L_LBDR_to_N_LBDR,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => L_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => L_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => L_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => L_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => L_err_grants_onehot,
err_grants_mismatch => L_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => L_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => L_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => L_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => L_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => L_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => L_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => L_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => L_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => L_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => L_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => L_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => L_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => L_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => L_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => L_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => L_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => L_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => L_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => L_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_LBDR_to_Allocator, SO=> SO,
-- Checker outputs
-- Allocator logic checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N => err_grant_N_N_sig_not_empty_N_grant_N_N ,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N => err_not_grant_N_N_sig_or_empty_N_not_grant_N_N ,
err_grant_N_E_sig_not_empty_E_grant_N_E => err_grant_N_E_sig_not_empty_E_grant_N_E ,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E => err_not_grant_N_E_sig_or_empty_E_not_grant_N_E ,
err_grant_N_W_sig_not_empty_W_grant_N_W => err_grant_N_W_sig_not_empty_W_grant_N_W ,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W => err_not_grant_N_W_sig_or_empty_W_not_grant_N_W ,
err_grant_N_S_sig_not_empty_S_grant_N_S => err_grant_N_S_sig_not_empty_S_grant_N_S ,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S => err_not_grant_N_S_sig_or_empty_S_not_grant_N_S ,
err_grant_N_L_sig_not_empty_L_grant_N_L => err_grant_N_L_sig_not_empty_L_grant_N_L ,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L => err_not_grant_N_L_sig_or_empty_L_not_grant_N_L ,
err_grant_E_N_sig_not_empty_N_grant_E_N => err_grant_E_N_sig_not_empty_N_grant_E_N ,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N => err_not_grant_E_N_sig_or_empty_N_not_grant_E_N ,
err_grant_E_E_sig_not_empty_E_grant_E_E => err_grant_E_E_sig_not_empty_E_grant_E_E ,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E => err_not_grant_E_E_sig_or_empty_E_not_grant_E_E ,
err_grant_E_W_sig_not_empty_W_grant_E_W => err_grant_E_W_sig_not_empty_W_grant_E_W ,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W => err_not_grant_E_W_sig_or_empty_W_not_grant_E_W ,
err_grant_E_S_sig_not_empty_S_grant_E_S => err_grant_E_S_sig_not_empty_S_grant_E_S ,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S => err_not_grant_E_S_sig_or_empty_S_not_grant_E_S ,
err_grant_E_L_sig_not_empty_L_grant_E_L => err_grant_E_L_sig_not_empty_L_grant_E_L ,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L => err_not_grant_E_L_sig_or_empty_L_not_grant_E_L ,
err_grant_W_N_sig_not_empty_N_grant_W_N => err_grant_W_N_sig_not_empty_N_grant_W_N ,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N => err_not_grant_W_N_sig_or_empty_N_not_grant_W_N ,
err_grant_W_E_sig_not_empty_E_grant_W_E => err_grant_W_E_sig_not_empty_E_grant_W_E ,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E => err_not_grant_W_E_sig_or_empty_E_not_grant_W_E ,
err_grant_W_W_sig_not_empty_W_grant_W_W => err_grant_W_W_sig_not_empty_W_grant_W_W ,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W => err_not_grant_W_W_sig_or_empty_W_not_grant_W_W ,
err_grant_W_S_sig_not_empty_S_grant_W_S => err_grant_W_S_sig_not_empty_S_grant_W_S ,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S => err_not_grant_W_S_sig_or_empty_S_not_grant_W_S ,
err_grant_W_L_sig_not_empty_L_grant_W_L => err_grant_W_L_sig_not_empty_L_grant_W_L ,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L => err_not_grant_W_L_sig_or_empty_L_not_grant_W_L ,
err_grant_S_N_sig_not_empty_N_grant_S_N => err_grant_S_N_sig_not_empty_N_grant_S_N ,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N => err_not_grant_S_N_sig_or_empty_N_not_grant_S_N ,
err_grant_S_E_sig_not_empty_E_grant_S_E => err_grant_S_E_sig_not_empty_E_grant_S_E ,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E => err_not_grant_S_E_sig_or_empty_E_not_grant_S_E ,
err_grant_S_W_sig_not_empty_W_grant_S_W => err_grant_S_W_sig_not_empty_W_grant_S_W ,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W => err_not_grant_S_W_sig_or_empty_W_not_grant_S_W ,
err_grant_S_S_sig_not_empty_S_grant_S_S => err_grant_S_S_sig_not_empty_S_grant_S_S ,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S => err_not_grant_S_S_sig_or_empty_S_not_grant_S_S ,
err_grant_S_L_sig_not_empty_L_grant_S_L => err_grant_S_L_sig_not_empty_L_grant_S_L ,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L => err_not_grant_S_L_sig_or_empty_L_not_grant_S_L ,
err_grant_L_N_sig_not_empty_N_grant_L_N => err_grant_L_N_sig_not_empty_N_grant_L_N ,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N => err_not_grant_L_N_sig_or_empty_N_not_grant_L_N ,
err_grant_L_E_sig_not_empty_E_grant_L_E => err_grant_L_E_sig_not_empty_E_grant_L_E ,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E => err_not_grant_L_E_sig_or_empty_E_not_grant_L_E ,
err_grant_L_W_sig_not_empty_W_grant_L_W => err_grant_L_W_sig_not_empty_W_grant_L_W ,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W => err_not_grant_L_W_sig_or_empty_W_not_grant_L_W ,
err_grant_L_S_sig_not_empty_S_grant_L_S => err_grant_L_S_sig_not_empty_S_grant_L_S ,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S => err_not_grant_L_S_sig_or_empty_S_not_grant_L_S ,
err_grant_L_L_sig_not_empty_L_grant_L_L => err_grant_L_L_sig_not_empty_L_grant_L_L ,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L => err_not_grant_L_L_sig_or_empty_L_not_grant_L_L ,
err_grant_signals_not_empty_grant_N => err_grant_signals_not_empty_grant_N ,
err_not_grant_signals_empty_not_grant_N => err_not_grant_signals_empty_not_grant_N ,
err_grant_signals_not_empty_grant_E => err_grant_signals_not_empty_grant_E ,
err_not_grant_signals_empty_not_grant_E => err_not_grant_signals_empty_not_grant_E ,
err_grant_signals_not_empty_grant_W => err_grant_signals_not_empty_grant_W ,
err_not_grant_signals_empty_not_grant_W => err_not_grant_signals_empty_not_grant_W ,
err_grant_signals_not_empty_grant_S => err_grant_signals_not_empty_grant_S ,
err_not_grant_signals_empty_not_grant_S => err_not_grant_signals_empty_not_grant_S ,
err_grant_signals_not_empty_grant_L => err_grant_signals_not_empty_grant_L ,
err_not_grant_signals_empty_not_grant_L => err_not_grant_signals_empty_not_grant_L ,
err_grants_valid_not_match => err_grants_valid_not_match ,
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal ,
err_credit_in_N_credit_counter_N_out_increment => err_credit_in_N_credit_counter_N_out_increment ,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change => err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change ,
err_grant_N_credit_counter_N_out_decrement => err_grant_N_credit_counter_N_out_decrement ,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change => err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change ,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal ,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal ,
err_credit_in_E_credit_counter_E_out_increment => err_credit_in_E_credit_counter_E_out_increment ,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change => err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change ,
err_grant_E_credit_counter_E_out_decrement => err_grant_E_credit_counter_E_out_decrement ,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change => err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change ,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal ,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal ,
err_credit_in_W_credit_counter_W_out_increment => err_credit_in_W_credit_counter_W_out_increment ,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change => err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change ,
err_grant_W_credit_counter_W_out_decrement => err_grant_W_credit_counter_W_out_decrement ,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change => err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change ,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal ,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal ,
err_credit_in_S_credit_counter_S_out_increment => err_credit_in_S_credit_counter_S_out_increment ,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change => err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change ,
err_grant_S_credit_counter_S_out_decrement => err_grant_S_credit_counter_S_out_decrement ,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change => err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change ,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal ,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal ,
err_credit_in_L_credit_counter_L_out_increment => err_credit_in_L_credit_counter_L_out_increment ,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change => err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change ,
err_grant_L_credit_counter_L_out_decrement => err_grant_L_credit_counter_L_out_decrement ,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change => err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change ,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal ,
-- North Arbiter_in Checker outputs
N_err_Requests_state_in_state_not_equal => N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N => N_err_IDLE_Req_N, N_err_IDLE_grant_N => N_err_IDLE_grant_N, N_err_North_Req_N => N_err_North_Req_N,
N_err_North_grant_N => N_err_North_grant_N, N_err_East_Req_E => N_err_East_Req_E, N_err_East_grant_E => N_err_East_grant_E,
N_err_West_Req_W => N_err_West_Req_W, N_err_West_grant_W => N_err_West_grant_W, N_err_South_Req_S => N_err_South_Req_S,
N_err_South_grant_S => N_err_South_grant_S, N_err_Local_Req_L => N_err_Local_Req_L, N_err_Local_grant_L => N_err_Local_grant_L,
N_err_IDLE_Req_E => N_err_IDLE_Req_E, N_err_IDLE_grant_E => N_err_IDLE_grant_E, N_err_North_Req_E => N_err_North_Req_E,
N_err_North_grant_E => N_err_North_grant_E, N_err_East_Req_W => N_err_East_Req_W, N_err_East_grant_W => N_err_East_grant_W,
N_err_West_Req_S => N_err_West_Req_S, N_err_West_grant_S => N_err_West_grant_S, N_err_South_Req_L => N_err_South_Req_L,
N_err_South_grant_L => N_err_South_grant_L, N_err_Local_Req_N => N_err_Local_Req_N, N_err_Local_grant_N => N_err_Local_grant_N,
N_err_IDLE_Req_W => N_err_IDLE_Req_W, N_err_IDLE_grant_W => N_err_IDLE_grant_W, N_err_North_Req_W => N_err_North_Req_W,
N_err_North_grant_W => N_err_North_grant_W, N_err_East_Req_S => N_err_East_Req_S, N_err_East_grant_S => N_err_East_grant_S,
N_err_West_Req_L => N_err_West_Req_L, N_err_West_grant_L => N_err_West_grant_L, N_err_South_Req_N => N_err_South_Req_N,
N_err_South_grant_N => N_err_South_grant_N, N_err_Local_Req_E => N_err_Local_Req_E, N_err_Local_grant_E => N_err_Local_grant_E,
N_err_IDLE_Req_S => N_err_IDLE_Req_S, N_err_IDLE_grant_S => N_err_IDLE_grant_S, N_err_North_Req_S => N_err_North_Req_S,
N_err_North_grant_S => N_err_North_grant_S, N_err_East_Req_L => N_err_East_Req_L, N_err_East_grant_L => N_err_East_grant_L,
N_err_West_Req_N => N_err_West_Req_N, N_err_West_grant_N => N_err_West_grant_N, N_err_South_Req_E => N_err_South_Req_E,
N_err_South_grant_E => N_err_South_grant_E, N_err_Local_Req_W => N_err_Local_Req_W, N_err_Local_grant_W => N_err_Local_grant_W,
N_err_IDLE_Req_L => N_err_IDLE_Req_L, N_err_IDLE_grant_L => N_err_IDLE_grant_L, N_err_North_Req_L => N_err_North_Req_L,
N_err_North_grant_L => N_err_North_grant_L, N_err_East_Req_N => N_err_East_Req_N, N_err_East_grant_N => N_err_East_grant_N,
N_err_West_Req_E => N_err_West_Req_E, N_err_West_grant_E => N_err_West_grant_E, N_err_South_Req_W => N_err_South_Req_W,
N_err_South_grant_W => N_err_South_grant_W, N_err_Local_Req_S => N_err_Local_Req_S, N_err_Local_grant_S => N_err_Local_grant_S,
N_err_state_in_onehot => N_err_arbiter_state_in_onehot, N_err_no_request_grants => N_err_no_request_grants,
N_err_request_no_grants => N_err_request_no_grants,
N_err_no_Req_N_grant_N => N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E => N_err_no_Req_E_grant_E,
N_err_no_Req_W_grant_W => N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S => N_err_no_Req_S_grant_S,
N_err_no_Req_L_grant_L => N_err_no_Req_L_grant_L,
-- East Arbiter_in Checker outputs
E_err_Requests_state_in_state_not_equal => E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N => E_err_IDLE_Req_N, E_err_IDLE_grant_N => E_err_IDLE_grant_N, E_err_North_Req_N => E_err_North_Req_N,
E_err_North_grant_N => E_err_North_grant_N, E_err_East_Req_E => E_err_East_Req_E, E_err_East_grant_E => E_err_East_grant_E,
E_err_West_Req_W => E_err_West_Req_W, E_err_West_grant_W => E_err_West_grant_W, E_err_South_Req_S => E_err_South_Req_S,
E_err_South_grant_S => E_err_South_grant_S, E_err_Local_Req_L => E_err_Local_Req_L, E_err_Local_grant_L => E_err_Local_grant_L,
E_err_IDLE_Req_E => E_err_IDLE_Req_E, E_err_IDLE_grant_E => E_err_IDLE_grant_E, E_err_North_Req_E => E_err_North_Req_E,
E_err_North_grant_E => E_err_North_grant_E, E_err_East_Req_W => E_err_East_Req_W, E_err_East_grant_W => E_err_East_grant_W,
E_err_West_Req_S => E_err_West_Req_S, E_err_West_grant_S => E_err_West_grant_S, E_err_South_Req_L => E_err_South_Req_L,
E_err_South_grant_L => E_err_South_grant_L, E_err_Local_Req_N => E_err_Local_Req_N, E_err_Local_grant_N => E_err_Local_grant_N,
E_err_IDLE_Req_W => E_err_IDLE_Req_W, E_err_IDLE_grant_W => E_err_IDLE_grant_W, E_err_North_Req_W => E_err_North_Req_W,
E_err_North_grant_W => E_err_North_grant_W, E_err_East_Req_S => E_err_East_Req_S, E_err_East_grant_S => E_err_East_grant_S,
E_err_West_Req_L => E_err_West_Req_L, E_err_West_grant_L => E_err_West_grant_L, E_err_South_Req_N => E_err_South_Req_N,
E_err_South_grant_N => E_err_South_grant_N, E_err_Local_Req_E => E_err_Local_Req_E, E_err_Local_grant_E => E_err_Local_grant_E,
E_err_IDLE_Req_S => E_err_IDLE_Req_S, E_err_IDLE_grant_S => E_err_IDLE_grant_S, E_err_North_Req_S => E_err_North_Req_S,
E_err_North_grant_S => E_err_North_grant_S, E_err_East_Req_L => E_err_East_Req_L, E_err_East_grant_L => E_err_East_grant_L,
E_err_West_Req_N => E_err_West_Req_N, E_err_West_grant_N => E_err_West_grant_N, E_err_South_Req_E => E_err_South_Req_E,
E_err_South_grant_E => E_err_South_grant_E, E_err_Local_Req_W => E_err_Local_Req_W, E_err_Local_grant_W => E_err_Local_grant_W,
E_err_IDLE_Req_L => E_err_IDLE_Req_L, E_err_IDLE_grant_L => E_err_IDLE_grant_L, E_err_North_Req_L => E_err_North_Req_L,
E_err_North_grant_L => E_err_North_grant_L, E_err_East_Req_N => E_err_East_Req_N, E_err_East_grant_N => E_err_East_grant_N,
E_err_West_Req_E => E_err_West_Req_E, E_err_West_grant_E => E_err_West_grant_E, E_err_South_Req_W => E_err_South_Req_W,
E_err_South_grant_W => E_err_South_grant_W, E_err_Local_Req_S => E_err_Local_Req_S, E_err_Local_grant_S => E_err_Local_grant_S,
E_err_state_in_onehot => E_err_arbiter_state_in_onehot,
E_err_no_request_grants => E_err_no_request_grants,
E_err_request_no_grants => E_err_request_no_grants,
E_err_no_Req_N_grant_N => E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E => E_err_no_Req_E_grant_E,
E_err_no_Req_W_grant_W => E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S => E_err_no_Req_S_grant_S,
E_err_no_Req_L_grant_L => E_err_no_Req_L_grant_L,
-- West Arbiter_in Checker outputs
W_err_Requests_state_in_state_not_equal => W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N => W_err_IDLE_Req_N, W_err_IDLE_grant_N => W_err_IDLE_grant_N, W_err_North_Req_N => W_err_North_Req_N,
W_err_North_grant_N => W_err_North_grant_N, W_err_East_Req_E => W_err_East_Req_E, W_err_East_grant_E => W_err_East_grant_E,
W_err_West_Req_W => W_err_West_Req_W, W_err_West_grant_W => W_err_West_grant_W, W_err_South_Req_S => W_err_South_Req_S,
W_err_South_grant_S => W_err_South_grant_S, W_err_Local_Req_L => W_err_Local_Req_L, W_err_Local_grant_L => W_err_Local_grant_L,
W_err_IDLE_Req_E => W_err_IDLE_Req_E, W_err_IDLE_grant_E => W_err_IDLE_grant_E, W_err_North_Req_E => W_err_North_Req_E,
W_err_North_grant_E => W_err_North_grant_E, W_err_East_Req_W => W_err_East_Req_W, W_err_East_grant_W => W_err_East_grant_W,
W_err_West_Req_S => W_err_West_Req_S, W_err_West_grant_S => W_err_West_grant_S, W_err_South_Req_L => W_err_South_Req_L,
W_err_South_grant_L => W_err_South_grant_L, W_err_Local_Req_N => W_err_Local_Req_N, W_err_Local_grant_N => W_err_Local_grant_N,
W_err_IDLE_Req_W => W_err_IDLE_Req_W, W_err_IDLE_grant_W => W_err_IDLE_grant_W, W_err_North_Req_W => W_err_North_Req_W,
W_err_North_grant_W => W_err_North_grant_W, W_err_East_Req_S => W_err_East_Req_S, W_err_East_grant_S => W_err_East_grant_S,
W_err_West_Req_L => W_err_West_Req_L, W_err_West_grant_L => W_err_West_grant_L, W_err_South_Req_N => W_err_South_Req_N,
W_err_South_grant_N => W_err_South_grant_N, W_err_Local_Req_E => W_err_Local_Req_E, W_err_Local_grant_E => W_err_Local_grant_E,
W_err_IDLE_Req_S => W_err_IDLE_Req_S, W_err_IDLE_grant_S => W_err_IDLE_grant_S, W_err_North_Req_S => W_err_North_Req_S,
W_err_North_grant_S => W_err_North_grant_S, W_err_East_Req_L => W_err_East_Req_L, W_err_East_grant_L => W_err_East_grant_L,
W_err_West_Req_N => W_err_West_Req_N, W_err_West_grant_N => W_err_West_grant_N, W_err_South_Req_E => W_err_South_Req_E,
W_err_South_grant_E => W_err_South_grant_E, W_err_Local_Req_W => W_err_Local_Req_W, W_err_Local_grant_W => W_err_Local_grant_W,
W_err_IDLE_Req_L => W_err_IDLE_Req_L, W_err_IDLE_grant_L => W_err_IDLE_grant_L, W_err_North_Req_L => W_err_North_Req_L,
W_err_North_grant_L => W_err_North_grant_L, W_err_East_Req_N => W_err_East_Req_N, W_err_East_grant_N => W_err_East_grant_N,
W_err_West_Req_E => W_err_West_Req_E, W_err_West_grant_E => W_err_West_grant_E, W_err_South_Req_W => W_err_South_Req_W,
W_err_South_grant_W => W_err_South_grant_W, W_err_Local_Req_S => W_err_Local_Req_S, W_err_Local_grant_S => W_err_Local_grant_S,
W_err_state_in_onehot => W_err_arbiter_state_in_onehot,
W_err_no_request_grants => W_err_no_request_grants,
W_err_request_no_grants => W_err_request_no_grants,
W_err_no_Req_N_grant_N => W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E => W_err_no_Req_E_grant_E,
W_err_no_Req_W_grant_W => W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S => W_err_no_Req_S_grant_S,
W_err_no_Req_L_grant_L => W_err_no_Req_L_grant_L,
-- South Arbiter_in Checker outputs
S_err_Requests_state_in_state_not_equal => S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N => S_err_IDLE_Req_N, S_err_IDLE_grant_N => S_err_IDLE_grant_N, S_err_North_Req_N => S_err_North_Req_N,
S_err_North_grant_N => S_err_North_grant_N, S_err_East_Req_E => S_err_East_Req_E, S_err_East_grant_E => S_err_East_grant_E,
S_err_West_Req_W => S_err_West_Req_W, S_err_West_grant_W => S_err_West_grant_W, S_err_South_Req_S => S_err_South_Req_S,
S_err_South_grant_S => S_err_South_grant_S, S_err_Local_Req_L => S_err_Local_Req_L, S_err_Local_grant_L => S_err_Local_grant_L,
S_err_IDLE_Req_E => S_err_IDLE_Req_E, S_err_IDLE_grant_E => S_err_IDLE_grant_E, S_err_North_Req_E => S_err_North_Req_E,
S_err_North_grant_E => S_err_North_grant_E, S_err_East_Req_W => S_err_East_Req_W, S_err_East_grant_W => S_err_East_grant_W,
S_err_West_Req_S => S_err_West_Req_S, S_err_West_grant_S => S_err_West_grant_S, S_err_South_Req_L => S_err_South_Req_L,
S_err_South_grant_L => S_err_South_grant_L, S_err_Local_Req_N => S_err_Local_Req_N, S_err_Local_grant_N => S_err_Local_grant_N,
S_err_IDLE_Req_W => S_err_IDLE_Req_W, S_err_IDLE_grant_W => S_err_IDLE_grant_W, S_err_North_Req_W => S_err_North_Req_W,
S_err_North_grant_W => S_err_North_grant_W, S_err_East_Req_S => S_err_East_Req_S, S_err_East_grant_S => S_err_East_grant_S,
S_err_West_Req_L => S_err_West_Req_L, S_err_West_grant_L => S_err_West_grant_L, S_err_South_Req_N => S_err_South_Req_N,
S_err_South_grant_N => S_err_South_grant_N, S_err_Local_Req_E => S_err_Local_Req_E, S_err_Local_grant_E => S_err_Local_grant_E,
S_err_IDLE_Req_S => S_err_IDLE_Req_S, S_err_IDLE_grant_S => S_err_IDLE_grant_S, S_err_North_Req_S => S_err_North_Req_S,
S_err_North_grant_S => S_err_North_grant_S, S_err_East_Req_L => S_err_East_Req_L, S_err_East_grant_L => S_err_East_grant_L,
S_err_West_Req_N => S_err_West_Req_N, S_err_West_grant_N => S_err_West_grant_N, S_err_South_Req_E => S_err_South_Req_E,
S_err_South_grant_E => S_err_South_grant_E, S_err_Local_Req_W => S_err_Local_Req_W, S_err_Local_grant_W => S_err_Local_grant_W,
S_err_IDLE_Req_L => S_err_IDLE_Req_L, S_err_IDLE_grant_L => S_err_IDLE_grant_L, S_err_North_Req_L => S_err_North_Req_L,
S_err_North_grant_L => S_err_North_grant_L, S_err_East_Req_N => S_err_East_Req_N, S_err_East_grant_N => S_err_East_grant_N,
S_err_West_Req_E => S_err_West_Req_E, S_err_West_grant_E => S_err_West_grant_E, S_err_South_Req_W => S_err_South_Req_W,
S_err_South_grant_W => S_err_South_grant_W, S_err_Local_Req_S => S_err_Local_Req_S, S_err_Local_grant_S => S_err_Local_grant_S,
S_err_state_in_onehot => S_err_arbiter_state_in_onehot,
S_err_no_request_grants => S_err_no_request_grants,
S_err_request_no_grants => S_err_request_no_grants,
S_err_no_Req_N_grant_N => S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E => S_err_no_Req_E_grant_E,
S_err_no_Req_W_grant_W => S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S => S_err_no_Req_S_grant_S,
S_err_no_Req_L_grant_L => S_err_no_Req_L_grant_L,
-- Local Arbiter_in Checker outputs
L_err_Requests_state_in_state_not_equal => L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N => L_err_IDLE_Req_N, L_err_IDLE_grant_N => L_err_IDLE_grant_N, L_err_North_Req_N => L_err_North_Req_N,
L_err_North_grant_N => L_err_North_grant_N, L_err_East_Req_E => L_err_East_Req_E, L_err_East_grant_E => L_err_East_grant_E,
L_err_West_Req_W => L_err_West_Req_W, L_err_West_grant_W => L_err_West_grant_W, L_err_South_Req_S => L_err_South_Req_S,
L_err_South_grant_S => L_err_South_grant_S, L_err_Local_Req_L => L_err_Local_Req_L, L_err_Local_grant_L => L_err_Local_grant_L,
L_err_IDLE_Req_E => L_err_IDLE_Req_E, L_err_IDLE_grant_E => L_err_IDLE_grant_E, L_err_North_Req_E => L_err_North_Req_E,
L_err_North_grant_E => L_err_North_grant_E, L_err_East_Req_W => L_err_East_Req_W, L_err_East_grant_W => L_err_East_grant_W,
L_err_West_Req_S => L_err_West_Req_S, L_err_West_grant_S => L_err_West_grant_S, L_err_South_Req_L => L_err_South_Req_L,
L_err_South_grant_L => L_err_South_grant_L, L_err_Local_Req_N => L_err_Local_Req_N, L_err_Local_grant_N => L_err_Local_grant_N,
L_err_IDLE_Req_W => L_err_IDLE_Req_W, L_err_IDLE_grant_W => L_err_IDLE_grant_W, L_err_North_Req_W => L_err_North_Req_W,
L_err_North_grant_W => L_err_North_grant_W, L_err_East_Req_S => L_err_East_Req_S, L_err_East_grant_S => L_err_East_grant_S,
L_err_West_Req_L => L_err_West_Req_L, L_err_West_grant_L => L_err_West_grant_L, L_err_South_Req_N => L_err_South_Req_N,
L_err_South_grant_N => L_err_South_grant_N, L_err_Local_Req_E => L_err_Local_Req_E, L_err_Local_grant_E => L_err_Local_grant_E,
L_err_IDLE_Req_S => L_err_IDLE_Req_S, L_err_IDLE_grant_S => L_err_IDLE_grant_S, L_err_North_Req_S => L_err_North_Req_S,
L_err_North_grant_S => L_err_North_grant_S, L_err_East_Req_L => L_err_East_Req_L, L_err_East_grant_L => L_err_East_grant_L,
L_err_West_Req_N => L_err_West_Req_N, L_err_West_grant_N => L_err_West_grant_N, L_err_South_Req_E => L_err_South_Req_E,
L_err_South_grant_E => L_err_South_grant_E, L_err_Local_Req_W => L_err_Local_Req_W, L_err_Local_grant_W => L_err_Local_grant_W,
L_err_IDLE_Req_L => L_err_IDLE_Req_L, L_err_IDLE_grant_L => L_err_IDLE_grant_L, L_err_North_Req_L => L_err_North_Req_L,
L_err_North_grant_L => L_err_North_grant_L, L_err_East_Req_N => L_err_East_Req_N, L_err_East_grant_N => L_err_East_grant_N,
L_err_West_Req_E => L_err_West_Req_E, L_err_West_grant_E => L_err_West_grant_E, L_err_South_Req_W => L_err_South_Req_W,
L_err_South_grant_W => L_err_South_grant_W, L_err_Local_Req_S => L_err_Local_Req_S, L_err_Local_grant_S => L_err_Local_grant_S,
L_err_state_in_onehot => L_err_arbiter_state_in_onehot,
L_err_no_request_grants => L_err_no_request_grants,
L_err_request_no_grants => L_err_request_no_grants,
L_err_no_Req_N_grant_N => L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E => L_err_no_Req_E_grant_E,
L_err_no_Req_W_grant_W => L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S => L_err_no_Req_S_grant_S,
L_err_no_Req_L_grant_L => L_err_no_Req_L_grant_L,
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal => N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N => N_err_IDLE_req_X_N,
N_err_North_req_X_N => N_err_North_req_X_N,
N_err_North_credit_not_zero_req_X_N_grant_N => N_err_North_credit_not_zero_req_X_N_grant_N,
N_err_North_credit_zero_or_not_req_X_N_not_grant_N => N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E => N_err_East_req_X_E,
N_err_East_credit_not_zero_req_X_E_grant_E => N_err_East_credit_not_zero_req_X_E_grant_E,
N_err_East_credit_zero_or_not_req_X_E_not_grant_E => N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
N_err_West_req_X_W => N_err_West_req_X_W,
N_err_West_credit_not_zero_req_X_W_grant_W => N_err_West_credit_not_zero_req_X_W_grant_W,
N_err_West_credit_zero_or_not_req_X_W_not_grant_W => N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
N_err_South_req_X_S => N_err_South_req_X_S,
N_err_South_credit_not_zero_req_X_S_grant_S => N_err_South_credit_not_zero_req_X_S_grant_S,
N_err_South_credit_zero_or_not_req_X_S_not_grant_S => N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
N_err_Local_req_X_L => N_err_Local_req_X_L,
N_err_Local_credit_not_zero_req_X_L_grant_L => N_err_Local_credit_not_zero_req_X_L_grant_L,
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L => N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E => N_err_IDLE_req_X_E, N_err_North_req_X_E => N_err_North_req_X_E, N_err_East_req_X_W => N_err_East_req_X_W,
N_err_West_req_X_S => N_err_West_req_X_S, N_err_South_req_X_L => N_err_South_req_X_L, N_err_Local_req_X_N => N_err_Local_req_X_N,
N_err_IDLE_req_X_W => N_err_IDLE_req_X_W, N_err_North_req_X_W => N_err_North_req_X_W, N_err_East_req_X_S => N_err_East_req_X_S,
N_err_West_req_X_L => N_err_West_req_X_L, N_err_South_req_X_N => N_err_South_req_X_N, N_err_Local_req_X_E => N_err_Local_req_X_E,
N_err_IDLE_req_X_S => N_err_IDLE_req_X_S, N_err_North_req_X_S => N_err_North_req_X_S, N_err_East_req_X_L => N_err_East_req_X_L,
N_err_West_req_X_N => N_err_West_req_X_N, N_err_South_req_X_E => N_err_South_req_X_E, N_err_Local_req_X_W => N_err_Local_req_X_W,
N_err_IDLE_req_X_L => N_err_IDLE_req_X_L, N_err_North_req_X_L => N_err_North_req_X_L, N_err_East_req_X_N => N_err_East_req_X_N,
N_err_West_req_X_E => N_err_West_req_X_E, N_err_South_req_X_W => N_err_South_req_X_W, N_err_Local_req_X_S => N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot => N_arbiter_out_err_state_in_onehot,
N_arbiter_out_err_no_request_grants => N_arbiter_out_err_no_request_grants,
N_err_request_IDLE_state => N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants => N_err_request_IDLE_not_Grants,
N_err_state_North_Invalid_Grant => N_err_state_North_Invalid_Grant,
N_err_state_East_Invalid_Grant => N_err_state_East_Invalid_Grant,
N_err_state_West_Invalid_Grant => N_err_state_West_Invalid_Grant,
N_err_state_South_Invalid_Grant => N_err_state_South_Invalid_Grant,
N_err_state_Local_Invalid_Grant => N_err_state_Local_Invalid_Grant,
N_err_Grants_onehot_or_all_zero => N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal => E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N => E_err_IDLE_req_X_N,
E_err_North_req_X_N => E_err_North_req_X_N,
E_err_North_credit_not_zero_req_X_N_grant_N => E_err_North_credit_not_zero_req_X_N_grant_N,
E_err_North_credit_zero_or_not_req_X_N_not_grant_N => E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E => E_err_East_req_X_E,
E_err_East_credit_not_zero_req_X_E_grant_E => E_err_East_credit_not_zero_req_X_E_grant_E,
E_err_East_credit_zero_or_not_req_X_E_not_grant_E => E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
E_err_West_req_X_W => E_err_West_req_X_W,
E_err_West_credit_not_zero_req_X_W_grant_W => E_err_West_credit_not_zero_req_X_W_grant_W,
E_err_West_credit_zero_or_not_req_X_W_not_grant_W => E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
E_err_South_req_X_S => E_err_South_req_X_S,
E_err_South_credit_not_zero_req_X_S_grant_S => E_err_South_credit_not_zero_req_X_S_grant_S,
E_err_South_credit_zero_or_not_req_X_S_not_grant_S => E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
E_err_Local_req_X_L => E_err_Local_req_X_L,
E_err_Local_credit_not_zero_req_X_L_grant_L => E_err_Local_credit_not_zero_req_X_L_grant_L,
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L => E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E => E_err_IDLE_req_X_E, E_err_North_req_X_E => E_err_North_req_X_E, E_err_East_req_X_W => E_err_East_req_X_W,
E_err_West_req_X_S => E_err_West_req_X_S, E_err_South_req_X_L => E_err_South_req_X_L, E_err_Local_req_X_N => E_err_Local_req_X_N,
E_err_IDLE_req_X_W => E_err_IDLE_req_X_W, E_err_North_req_X_W => E_err_North_req_X_W, E_err_East_req_X_S => E_err_East_req_X_S,
E_err_West_req_X_L => E_err_West_req_X_L, E_err_South_req_X_N => E_err_South_req_X_N, E_err_Local_req_X_E => E_err_Local_req_X_E,
E_err_IDLE_req_X_S => E_err_IDLE_req_X_S, E_err_North_req_X_S => E_err_North_req_X_S, E_err_East_req_X_L => E_err_East_req_X_L,
E_err_West_req_X_N => E_err_West_req_X_N, E_err_South_req_X_E => E_err_South_req_X_E, E_err_Local_req_X_W => E_err_Local_req_X_W,
E_err_IDLE_req_X_L => E_err_IDLE_req_X_L, E_err_North_req_X_L => E_err_North_req_X_L, E_err_East_req_X_N => E_err_East_req_X_N,
E_err_West_req_X_E => E_err_West_req_X_E, E_err_South_req_X_W => E_err_South_req_X_W, E_err_Local_req_X_S => E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot => E_arbiter_out_err_state_in_onehot,
E_arbiter_out_err_no_request_grants => E_arbiter_out_err_no_request_grants,
E_err_request_IDLE_state => E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants => E_err_request_IDLE_not_Grants,
E_err_state_North_Invalid_Grant => E_err_state_North_Invalid_Grant,
E_err_state_East_Invalid_Grant => E_err_state_East_Invalid_Grant,
E_err_state_West_Invalid_Grant => E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant => E_err_state_South_Invalid_Grant,
E_err_state_Local_Invalid_Grant => E_err_state_Local_Invalid_Grant,
E_err_Grants_onehot_or_all_zero => E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal => W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N => W_err_IDLE_req_X_N,
W_err_North_req_X_N => W_err_North_req_X_N,
W_err_North_credit_not_zero_req_X_N_grant_N => W_err_North_credit_not_zero_req_X_N_grant_N,
W_err_North_credit_zero_or_not_req_X_N_not_grant_N => W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E => W_err_East_req_X_E,
W_err_East_credit_not_zero_req_X_E_grant_E => W_err_East_credit_not_zero_req_X_E_grant_E,
W_err_East_credit_zero_or_not_req_X_E_not_grant_E => W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W => W_err_West_req_X_W,
W_err_West_credit_not_zero_req_X_W_grant_W => W_err_West_credit_not_zero_req_X_W_grant_W,
W_err_West_credit_zero_or_not_req_X_W_not_grant_W => W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S => W_err_South_req_X_S,
W_err_South_credit_not_zero_req_X_S_grant_S => W_err_South_credit_not_zero_req_X_S_grant_S,
W_err_South_credit_zero_or_not_req_X_S_not_grant_S => W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L => W_err_Local_req_X_L,
W_err_Local_credit_not_zero_req_X_L_grant_L => W_err_Local_credit_not_zero_req_X_L_grant_L,
W_err_Local_credit_zero_or_not_req_X_L_not_grant_L => W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E => W_err_IDLE_req_X_E, W_err_North_req_X_E => W_err_North_req_X_E, W_err_East_req_X_W => W_err_East_req_X_W,
W_err_West_req_X_S => W_err_West_req_X_S, W_err_South_req_X_L => W_err_South_req_X_L, W_err_Local_req_X_N => W_err_Local_req_X_N,
W_err_IDLE_req_X_W => W_err_IDLE_req_X_W, W_err_North_req_X_W => W_err_North_req_X_W, W_err_East_req_X_S => W_err_East_req_X_S,
W_err_West_req_X_L => W_err_West_req_X_L, W_err_South_req_X_N => W_err_South_req_X_N, W_err_Local_req_X_E => W_err_Local_req_X_E,
W_err_IDLE_req_X_S => W_err_IDLE_req_X_S, W_err_North_req_X_S => W_err_North_req_X_S, W_err_East_req_X_L => W_err_East_req_X_L,
W_err_West_req_X_N => W_err_West_req_X_N, W_err_South_req_X_E => W_err_South_req_X_E, W_err_Local_req_X_W => W_err_Local_req_X_W,
W_err_IDLE_req_X_L => W_err_IDLE_req_X_L, W_err_North_req_X_L => W_err_North_req_X_L, W_err_East_req_X_N => W_err_East_req_X_N,
W_err_West_req_X_E => W_err_West_req_X_E, W_err_South_req_X_W => W_err_South_req_X_W, W_err_Local_req_X_S => W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot => W_arbiter_out_err_state_in_onehot,
W_arbiter_out_err_no_request_grants => W_arbiter_out_err_no_request_grants,
W_err_request_IDLE_state => W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants => W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant => W_err_state_North_Invalid_Grant,
W_err_state_East_Invalid_Grant => W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant => W_err_state_West_Invalid_Grant,
W_err_state_South_Invalid_Grant => W_err_state_South_Invalid_Grant, W_err_state_Local_Invalid_Grant => W_err_state_Local_Invalid_Grant,
W_err_Grants_onehot_or_all_zero => W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal => S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N => S_err_IDLE_req_X_N,
S_err_North_req_X_N => S_err_North_req_X_N,
S_err_North_credit_not_zero_req_X_N_grant_N => S_err_North_credit_not_zero_req_X_N_grant_N,
S_err_North_credit_zero_or_not_req_X_N_not_grant_N => S_err_North_credit_zero_or_not_req_X_N_not_grant_N,
S_err_East_req_X_E => S_err_East_req_X_E,
S_err_East_credit_not_zero_req_X_E_grant_E => S_err_East_credit_not_zero_req_X_E_grant_E,
S_err_East_credit_zero_or_not_req_X_E_not_grant_E => S_err_East_credit_zero_or_not_req_X_E_not_grant_E,
S_err_West_req_X_W => S_err_West_req_X_W,
S_err_West_credit_not_zero_req_X_W_grant_W => S_err_West_credit_not_zero_req_X_W_grant_W,
S_err_West_credit_zero_or_not_req_X_W_not_grant_W => S_err_West_credit_zero_or_not_req_X_W_not_grant_W,
S_err_South_req_X_S => S_err_South_req_X_S,
S_err_South_credit_not_zero_req_X_S_grant_S => S_err_South_credit_not_zero_req_X_S_grant_S,
S_err_South_credit_zero_or_not_req_X_S_not_grant_S => S_err_South_credit_zero_or_not_req_X_S_not_grant_S,
S_err_Local_req_X_L => S_err_Local_req_X_L,
S_err_Local_credit_not_zero_req_X_L_grant_L => S_err_Local_credit_not_zero_req_X_L_grant_L,
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L => S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E => S_err_IDLE_req_X_E, S_err_North_req_X_E => S_err_North_req_X_E, S_err_East_req_X_W => S_err_East_req_X_W,
S_err_West_req_X_S => S_err_West_req_X_S, S_err_South_req_X_L => S_err_South_req_X_L, S_err_Local_req_X_N => S_err_Local_req_X_N,
S_err_IDLE_req_X_W => S_err_IDLE_req_X_W, S_err_North_req_X_W => S_err_North_req_X_W, S_err_East_req_X_S => S_err_East_req_X_S,
S_err_West_req_X_L => S_err_West_req_X_L, S_err_South_req_X_N => S_err_South_req_X_N, S_err_Local_req_X_E => S_err_Local_req_X_E,
S_err_IDLE_req_X_S => S_err_IDLE_req_X_S, S_err_North_req_X_S => S_err_North_req_X_S, S_err_East_req_X_L => S_err_East_req_X_L,
S_err_West_req_X_N => S_err_West_req_X_N, S_err_South_req_X_E => S_err_South_req_X_E, S_err_Local_req_X_W => S_err_Local_req_X_W,
S_err_IDLE_req_X_L => S_err_IDLE_req_X_L, S_err_North_req_X_L => S_err_North_req_X_L, S_err_East_req_X_N => S_err_East_req_X_N,
S_err_West_req_X_E => S_err_West_req_X_E, S_err_South_req_X_W => S_err_South_req_X_W, S_err_Local_req_X_S => S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot => S_arbiter_out_err_state_in_onehot,
S_arbiter_out_err_no_request_grants => S_arbiter_out_err_no_request_grants,
S_err_request_IDLE_state => S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants => S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant => S_err_state_North_Invalid_Grant,
S_err_state_East_Invalid_Grant => S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant => S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant => S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant => S_err_state_Local_Invalid_Grant,
S_err_Grants_onehot_or_all_zero => S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal => L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N => L_err_IDLE_req_X_N,
L_err_North_req_X_N => L_err_North_req_X_N,
L_err_North_credit_not_zero_req_X_N_grant_N => L_err_North_credit_not_zero_req_X_N_grant_N,
L_err_North_credit_zero_or_not_req_X_N_not_grant_N => L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E => L_err_East_req_X_E,
L_err_East_credit_not_zero_req_X_E_grant_E => L_err_East_credit_not_zero_req_X_E_grant_E,
L_err_East_credit_zero_or_not_req_X_E_not_grant_E => L_err_East_credit_zero_or_not_req_X_E_not_grant_E,
L_err_West_req_X_W => L_err_West_req_X_W,
L_err_West_credit_not_zero_req_X_W_grant_W => L_err_West_credit_not_zero_req_X_W_grant_W,
L_err_West_credit_zero_or_not_req_X_W_not_grant_W => L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S => L_err_South_req_X_S,
L_err_South_credit_not_zero_req_X_S_grant_S => L_err_South_credit_not_zero_req_X_S_grant_S,
L_err_South_credit_zero_or_not_req_X_S_not_grant_S => L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L => L_err_Local_req_X_L,
L_err_Local_credit_not_zero_req_X_L_grant_L => L_err_Local_credit_not_zero_req_X_L_grant_L,
L_err_Local_credit_zero_or_not_req_X_L_not_grant_L => L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E => L_err_IDLE_req_X_E, L_err_North_req_X_E => L_err_North_req_X_E, L_err_East_req_X_W => L_err_East_req_X_W,
L_err_West_req_X_S => L_err_West_req_X_S, L_err_South_req_X_L => L_err_South_req_X_L, L_err_Local_req_X_N => L_err_Local_req_X_N,
L_err_IDLE_req_X_W => L_err_IDLE_req_X_W, L_err_North_req_X_W => L_err_North_req_X_W, L_err_East_req_X_S => L_err_East_req_X_S,
L_err_West_req_X_L => L_err_West_req_X_L, L_err_South_req_X_N => L_err_South_req_X_N, L_err_Local_req_X_E => L_err_Local_req_X_E,
L_err_IDLE_req_X_S => L_err_IDLE_req_X_S, L_err_North_req_X_S => L_err_North_req_X_S, L_err_East_req_X_L => L_err_East_req_X_L,
L_err_West_req_X_N => L_err_West_req_X_N, L_err_South_req_X_E => L_err_South_req_X_E, L_err_Local_req_X_W => L_err_Local_req_X_W,
L_err_IDLE_req_X_L => L_err_IDLE_req_X_L, L_err_North_req_X_L => L_err_North_req_X_L, L_err_East_req_X_N => L_err_East_req_X_N,
L_err_West_req_X_E => L_err_West_req_X_E, L_err_South_req_X_W => L_err_South_req_X_W, L_err_Local_req_X_S => L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot => L_arbiter_out_err_state_in_onehot,
L_arbiter_out_err_no_request_grants => L_arbiter_out_err_no_request_grants,
L_err_request_IDLE_state => L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants => L_err_request_IDLE_not_Grants,
L_err_state_North_Invalid_Grant => L_err_state_North_Invalid_Grant,
L_err_state_East_Invalid_Grant => L_err_state_East_Invalid_Grant,
L_err_state_West_Invalid_Grant => L_err_state_West_Invalid_Grant,
L_err_state_South_Invalid_Grant => L_err_state_South_Invalid_Grant,
L_err_state_Local_Invalid_Grant => L_err_state_Local_Invalid_Grant,
L_err_Grants_onehot_or_all_zero => L_err_Grants_onehot_or_all_zero
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
end; | gpl-3.0 | 953f020cd880221ebf59b3bd6bc52565 | 0.602116 | 2.965441 | false | true | false | false |
elainemielas/CVUT_BI-PNO | project1/kitt.vhd | 1 | 2,408 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity KITT is
port (
CLK : in std_logic;
INPUT : in std_logic_vector (7 downto 0);
BTN0 : in std_logic;
BTN1 : in std_logic;
BTN2 : in std_logic;
BTN3 : in std_logic;
SEG : out STD_LOGIC_VECTOR (6 downto 0); -- 7 segmentu displeje
DP_K : out STD_LOGIC; -- desetinna tecka
DIG : out STD_LOGIC_VECTOR (3 downto 0) -- 4 cifry displeje
);
end KITT;
architecture KITT_BODY of KITT is
signal DATAOUT, SHOW1OUT, SHOW2OUT, OUTPUT : std_logic_vector (15 downto 0);
signal POSUN, SCIT, ZERO : std_logic;
component AUTOMAT is
port(
CLK, BTN0, BTN1, ZERO : in std_logic;
POSUN, SCIT : out std_logic
);
end component;
component DATAPATH is
port(
INPUT : in std_logic_vector (7 downto 0);
CLK, RESET, POSUN, SCIT : in std_logic;
OUTPUT : out std_logic_vector (15 downto 0);
SHOW1OUT : out std_logic_vector (15 downto 0);
SHOW2OUT : out std_logic_vector (15 downto 0);
ZERO : out std_logic
);
end component;
component HEX2SEG is
port (
DATA : in STD_LOGIC_VECTOR (15 downto 0); -- vstupni data k zobrazeni (4 sestnactkove cislice)
CLK : in STD_LOGIC;
SEGMENT : out STD_LOGIC_VECTOR (6 downto 0); -- 7 segmentu displeje
DP : out STD_LOGIC; -- desetinna tecka
DIGIT : out STD_LOGIC_VECTOR (3 downto 0) -- 4 cifry displeje
);
end component;
component MUX is
port (
SHOWA1A0 : in std_logic;
SHOWA3A2 : in std_logic;
OUTPUT : in std_logic_vector (15 downto 0);
SHOW1OUT : in std_logic_vector (15 downto 0);
SHOW2OUT : in std_logic_vector (15 downto 0);
DATAOUT : out std_logic_vector (15 downto 0)
);
end component;
begin
RADIC : AUTOMAT port map (CLK => CLK, POSUN => POSUN, SCIT => SCIT, BTN0 => BTN0, BTN1 => BTN1, ZERO => ZERO);
SCITANI : DATAPATH port map (CLK => CLK, RESET => BTN0, POSUN => POSUN, SCIT => SCIT, INPUT => INPUT, OUTPUT => OUTPUT, SHOW1OUT => SHOW1OUT, SHOW2OUT => SHOW2OUT, ZERO => ZERO);
MULTIPLEXER : MUX port map (SHOWA1A0 => BTN3, SHOWA3A2 => BTN2, OUTPUT => OUTPUT, SHOW1OUT => SHOW1OUT, SHOW2OUT => SHOW2OUT, DATAOUT => DATAOUT);
DEKODER : HEX2SEG port map (DATA => DATAOUT, CLK => CLK, SEGMENT => SEG, DP => DP_K, DIGIT => DIG);
end architecture;
| mit | 6ed4b9a1f2a8d50e5ceb818cf4a5ee7b | 0.609635 | 3.040404 | false | false | false | false |
Wynjones1/gbvhdl | scripts/out.vhd | 1 | 4,142 | elsif mem_dout = "00000000" then -- NOP
elsif mem_dout = "00000111" then -- RLCA
elsif mem_dout = "00001111" then -- RRCA
elsif mem_dout = "00010000" then -- STOP
elsif mem_dout = "00010111" then -- RLA
elsif mem_dout = "00011000" then -- JR r8
elsif mem_dout = "00011111" then -- RRA
elsif mem_dout = "00100111" then -- DDA
elsif mem_dout = "00101111" then -- CPL
elsif mem_dout = "00110100" then -- INC (HL)
elsif mem_dout = "00110101" then -- DEC (HL)
elsif mem_dout = "00110111" then -- SCF
elsif mem_dout = "00111111" then -- CCF
elsif mem_dout = "01110110" then -- HALT
elsif mem_dout = "11000011" then -- JP d16
elsif mem_dout = "11001001" then -- RET
elsif mem_dout = "11001011" then -- CB
elsif mem_dout = "11001101" then -- CALL d16
elsif mem_dout = "11011001" then -- RETI
elsif mem_dout = "11101000" then -- ADD SP r8
elsif mem_dout = "11101001" then -- JP PC (HL)
elsif mem_dout = "11110011" then -- DI
elsif mem_dout = "11111011" then -- EI
elsif mem_dout = "00000010" then -- LD (BC) A
elsif mem_dout = "00001000" then -- LD (d16) SP
elsif mem_dout = "00001010" then -- LD A (BC)
elsif mem_dout = "00010010" then -- LD (DE) A
elsif mem_dout = "00011010" then -- LD A (DE)
elsif mem_dout = "00100010" then -- LD (HL++) A
elsif mem_dout = "00101010" then -- LD A (HL++)
elsif mem_dout = "00110010" then -- LD (HL--) A
elsif mem_dout = "00110110" then -- LD (HL) d8
elsif mem_dout = "00111010" then -- LD A (HL--)
elsif mem_dout = "11100010" then -- LD (C) A
elsif mem_dout = "11101010" then -- LD (d16) A
elsif mem_dout = "11110010" then -- LD A (C)
elsif mem_dout = "11111000" then -- LD HL SP + r8
elsif mem_dout = "11111001" then -- LD SP HL
elsif mem_dout = "11111010" then -- LD A (d16)
elsif mem_dout = "11100000" then -- LDH (d8) A
elsif mem_dout = "11110000" then -- LDH A (d8)
elsif mem_dout = "11010011" then -- INVALID
elsif mem_dout = "11011011" then -- INVALID
elsif mem_dout = "11011101" then -- INVALID
elsif mem_dout = "11100011" then -- INVALID
elsif mem_dout = "11100100" then -- INVALID
elsif mem_dout = "11101011" then -- INVALID
elsif mem_dout = "11101100" then -- INVALID
elsif mem_dout = "11101101" then -- INVALID
elsif mem_dout = "11110100" then -- INVALID
elsif mem_dout = "11111100" then -- INVALID
elsif mem_dout = "11111101" then -- INVALID
elsif mem_dout(7 downto 3) = "01110" then -- LD (HL) r'
elsif mem_dout(7 downto 5) = "001" and mem_dout(2 downto 0) = "000" then -- JR cc r8
elsif mem_dout(7 downto 5) = "110" and mem_dout(2 downto 0) = "000" then -- RET cc
elsif mem_dout(7 downto 5) = "110" and mem_dout(2 downto 0) = "010" then -- JP cc d16
elsif mem_dout(7 downto 5) = "110" and mem_dout(2 downto 0) = "100" then -- CALL cc d16
elsif mem_dout(7 downto 6) = "00" and mem_dout(2 downto 0) = "100" then -- INC r
elsif mem_dout(7 downto 6) = "00" and mem_dout(2 downto 0) = "101" then -- DEC r
elsif mem_dout(7 downto 6) = "00" and mem_dout(2 downto 0) = "110" then -- LD r n
elsif mem_dout(7 downto 6) = "01" and mem_dout(2 downto 0) = "110" then -- LD r (HL)
elsif mem_dout(7 downto 6) = "10" and mem_dout(2 downto 0) = "110" then -- f A (HL)
elsif mem_dout(7 downto 6) = "11" and mem_dout(2 downto 0) = "110" then -- f A n
elsif mem_dout(7 downto 6) = "11" and mem_dout(2 downto 0) = "111" then -- RST t
elsif mem_dout(7 downto 6) = "00" and mem_dout(3 downto 0) = "0001" then -- LD dd d16
elsif mem_dout(7 downto 6) = "00" and mem_dout(3 downto 0) = "0011" then -- INC ss
elsif mem_dout(7 downto 6) = "00" and mem_dout(3 downto 0) = "1001" then -- ADD HL ss
elsif mem_dout(7 downto 6) = "00" and mem_dout(3 downto 0) = "1011" then -- DEC ss
elsif mem_dout(7 downto 6) = "11" and mem_dout(3 downto 0) = "0001" then -- POP qq
elsif mem_dout(7 downto 6) = "11" and mem_dout(3 downto 0) = "0101" then -- PUSH qq
elsif mem_dout(7 downto 6) = "01" then -- LD r r'
elsif mem_dout(7 downto 6) = "10" then -- f A r'
| mit | b708a4ed5b0e02488df7abb22802fa24 | 0.60478 | 2.880389 | false | false | false | false |
camacazio/de0_nano_DAC | DE0_12bitDAC_controller/logic_mem.vhd | 1 | 8,529 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: logic_mem.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY logic_mem IS
PORT
(
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END logic_mem;
ARCHITECTURE SYN OF logic_mem IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
q <= sub_wire0(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
ram_block_type => "M9K",
read_during_write_mode_mixed_ports => "OLD_DATA",
widthad_a => 10,
widthad_b => 10,
width_a => 16,
width_b => 16,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
address_b => rdaddress,
clock0 => clock,
data_a => data,
wren_a => wren,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
-- Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL logic_mem.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL logic_mem.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL logic_mem.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL logic_mem.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL logic_mem_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 9a1141b1431827237e3f91ff7c9d2e85 | 0.685895 | 3.580605 | false | false | false | false |
simoesusp/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE70/KB_ASCII.vhd | 3 | 15,996 | -- ASCII DECODER FOR ABNT2 KEYBOARDS
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY KB_ASCII IS
PORT( CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
SCANCODE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SCANEXTENDED : IN STD_LOGIC;
SCANPRESSING : IN STD_LOGIC;
ASCII : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
HALT_REQ : OUT STD_LOGIC;
RESET_REQ : OUT STD_LOGIC
);
END KB_ASCII;
ARCHITECTURE main OF KB_ASCII IS
SIGNAL CTRLpressed : STD_LOGIC;
SIGNAL SHIFTpressed : STD_LOGIC;
SIGNAL ALTpressed : STD_LOGIC;
SIGNAL CTRLcombos : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL SHIFTcombos : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL NORMALpress : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(CLK, RST)
VARIABLE PRESSTATE : STD_LOGIC;
BEGIN
IF(RST = '1') THEN
NORMALpress <= x"FF";
SHIFTpressed <= '0';
CTRLpressed <= '0';
PRESSTATE := '0';
ELSIF(CLK'EVENT AND CLK = '1') THEN
CASE PRESSTATE IS
WHEN '0' =>
-- Tratar todas as teclas iniciais (ou unicas)
CASE SCANCODE IS
-- [CTRL START] CTRL + (N/A)
WHEN x"14" =>
CTRLpressed <= '1';
PRESSTATE := '1';
-- [LEFT SHIFT START] SHIFT + (N/A)
WHEN x"12" =>
SHIFTpressed <= '1';
PRESSTATE := '1';
-- [RIGHT SHIFT START] SHIFT + (N/A)
WHEN x"59" =>
SHIFTpressed <= '1';
PRESSTATE := '1';
-- [LINE FEED] ENTER (0x0A)
WHEN x"5A" =>
NORMALpress <= x"0A";
PRESSTATE := '1';
-- [BACKSPACE] BACKSPACE (0x08)
WHEN x"66" =>
NORMALpress <= x"08";
PRESSTATE := '1';
-- [HORIZONTAL TAB] TAB (0x09)
WHEN x"0D" =>
NORMALpress <= x"09";
PRESSTATE := '1';
-- [ESCAPE] ESC (0x1B)
WHEN x"76" =>
NORMALpress <= x"1B";
PRESSTATE := '1';
-- [SPACE] SPACE (0x20)
WHEN x"29" =>
NORMALpress <= x"20";
PRESSTATE := '1';
-- ['] ' (0x27)
WHEN x"0E" =>
NORMALpress <= x"27";
PRESSTATE := '1';
-- [,] , (0x2C)
WHEN x"41" =>
NORMALpress <= x"2C";
PRESSTATE := '1';
-- [-] - (0x2D)
WHEN x"4E" =>
NORMALpress <= x"2D";
PRESSTATE := '1';
-- [.] . (0x2E)
WHEN x"49" =>
NORMALpress <= x"2E";
PRESSTATE := '1';
-- [/] / (0x2F)
WHEN x"51" =>
NORMALpress <= x"2F";
PRESSTATE := '1';
-- [0] 0 (0x30)
WHEN x"45" =>
NORMALpress <= x"30";
PRESSTATE := '1';
-- [1] 1 (0x31)
WHEN x"16" =>
NORMALpress <= x"31";
PRESSTATE := '1';
-- [2] 2 (0x32)
WHEN x"1E" =>
NORMALpress <= x"32";
PRESSTATE := '1';
-- [3] 3 (0x33)
WHEN x"26" =>
NORMALpress <= x"33";
PRESSTATE := '1';
-- [4] 4 (0x34)
WHEN x"25" =>
NORMALpress <= x"34";
PRESSTATE := '1';
-- [5] 5 (0x35)
WHEN x"2E" =>
NORMALpress <= x"35";
PRESSTATE := '1';
-- [6] 6 (0x36)
WHEN x"36" =>
NORMALpress <= x"36";
PRESSTATE := '1';
-- [7] 7 (0x37)
WHEN x"3D" =>
NORMALpress <= x"37";
PRESSTATE := '1';
-- [8] 8 (0x38)
WHEN x"3E" =>
NORMALpress <= x"38";
PRESSTATE := '1';
-- [9] 9 (0x39)
WHEN x"46" =>
NORMALpress <= x"39";
PRESSTATE := '1';
-- [;] ; (0x3B)
WHEN x"4A" =>
NORMALpress <= x"3B";
PRESSTATE := '1';
-- [=] = (0x3D)
WHEN x"55" =>
NORMALpress <= x"3D";
PRESSTATE := '1';
-- [[] [ (0x5B)
WHEN x"5B" =>
NORMALpress <= x"5B";
PRESSTATE := '1';
-- [\] \ (0x5C)
WHEN x"61" =>
NORMALpress <= x"5C";
PRESSTATE := '1';
-- []] ] (0x5D)
WHEN x"5D" =>
NORMALpress <= x"5D";
PRESSTATE := '1';
-- [a] a (0x61)
WHEN x"1C" =>
NORMALpress <= x"61";
PRESSTATE := '1';
-- [b] b (0x62)
WHEN x"32" =>
NORMALpress <= x"62";
PRESSTATE := '1';
-- [c] c (0x63)
WHEN x"21" =>
NORMALpress <= x"63";
PRESSTATE := '1';
-- [d] d (0x64)
WHEN x"23" =>
NORMALpress <= x"64";
PRESSTATE := '1';
-- [e] e (0x65)
WHEN x"24" =>
NORMALpress <= x"65";
PRESSTATE := '1';
-- [f] f (0x66)
WHEN x"2B" =>
NORMALpress <= x"66";
PRESSTATE := '1';
-- [g] g (0x67)
WHEN x"34" =>
NORMALpress <= x"67";
PRESSTATE := '1';
-- [h] h (0x68)
WHEN x"33" =>
NORMALpress <= x"68";
PRESSTATE := '1';
-- [i] i (0x69)
WHEN x"43" =>
NORMALpress <= x"69";
PRESSTATE := '1';
-- [j] j (0x6A)
WHEN x"3B" =>
NORMALpress <= x"6A";
PRESSTATE := '1';
-- [k] k (0x6B)
WHEN x"42" =>
NORMALpress <= x"6B";
PRESSTATE := '1';
-- [l] l (0x6C)
WHEN x"4B" =>
NORMALpress <= x"6C";
PRESSTATE := '1';
-- [m] m (0x6D)
WHEN x"3A" =>
NORMALpress <= x"6D";
PRESSTATE := '1';
-- [n] n (0x6E)
WHEN x"31" =>
NORMALpress <= x"6E";
PRESSTATE := '1';
-- [o] o (0x6F)
WHEN x"44" =>
NORMALpress <= x"6F";
PRESSTATE := '1';
-- [p] p (0x70)
WHEN x"4D" =>
NORMALpress <= x"70";
PRESSTATE := '1';
-- [q] q (0x71)
WHEN x"15" =>
NORMALpress <= x"71";
PRESSTATE := '1';
-- [r] r (0x72)
WHEN x"2D" =>
NORMALpress <= x"72";
PRESSTATE := '1';
-- [s] s (0x73)
WHEN x"1B" =>
NORMALpress <= x"73";
PRESSTATE := '1';
-- [t] t (0x74)
WHEN x"2C" =>
NORMALpress <= x"74";
PRESSTATE := '1';
-- [u] u (0x75)
WHEN x"3C" =>
NORMALpress <= x"75";
PRESSTATE := '1';
-- [v] v (0x76)
WHEN x"2A" =>
NORMALpress <= x"76";
PRESSTATE := '1';
-- [w] w (0x77)
WHEN x"1D" =>
NORMALpress <= x"77";
PRESSTATE := '1';
-- [x] x (0x78)
WHEN x"22" =>
NORMALpress <= x"78";
PRESSTATE := '1';
-- [y] y (0x79)
WHEN x"35" =>
NORMALpress <= x"79";
PRESSTATE := '1';
-- [z] z (0x7A)
WHEN x"1A" =>
NORMALpress <= x"7A";
PRESSTATE := '1';
-- [~] ~ (0x7E)
WHEN x"52" =>
NORMALpress <= x"7E";
PRESSTATE := '1';
-- [ ] DEL (0x7F)
WHEN x"71" =>
NORMALpress <= x"7F";
PRESSTATE := '1';
WHEN OTHERS =>
NORMALpress <= x"00";
SHIFTpressed <= '0';
CTRLpressed <= '0';
END CASE;
WHEN '1' =>
IF(SCANPRESSING = '0') THEN
SHIFTpressed <= '0';
CTRLpressed <= '0';
PRESSTATE := '0';
END IF;
END CASE;
END IF;
END PROCESS;
PROCESS(CLK, RST)
VARIABLE PRESSTATE : STD_LOGIC;
BEGIN
IF(RST = '1') THEN
ALTpressed <= '0';
CTRLcombos <= "00000";
SHIFTcombos <= "0000000";
PRESSTATE := '0';
ELSIF(CLK'EVENT AND CLK = '1' AND CTRLpressed = '1') THEN
CASE PRESSTATE IS
WHEN '0' =>
CASE SCANCODE IS
-- [ALT START] CTRL + ALT + (N/A)
WHEN x"11" =>
ALTpressed <= '1';
PRESSTATE := '1';
-- [START OF HEADER] CTRL + A (0x01)
WHEN x"1C" =>
CTRLcombos <= "00001";
PRESSTATE := '1';
-- [START OF TRANSMISSION] CTRL + B (0x02)
WHEN x"32" =>
CTRLcombos <= "00010";
PRESSTATE := '1';
-- [END OF TRANSMISSION] CTRL + C (0x03)
WHEN x"21" =>
CTRLcombos <= "00011";
PRESSTATE := '1';
-- [END OF TEXT] CTRL + D (0x04)
WHEN x"23" =>
CTRLcombos <= "00100";
PRESSTATE := '1';
-- [ENQUIRY] CTRL + E (0x05)
WHEN x"24" =>
CTRLcombos <= "00101";
PRESSTATE := '1';
-- [ACKNOWLEDGE] CTRL + F (0x06)
WHEN x"2B" =>
CTRLcombos <= "00110";
PRESSTATE := '1';
-- [BELL] CTRL + G (0x07)
WHEN x"34" =>
CTRLcombos <= "00111";
PRESSTATE := '1';
-- [BACKSPACE] CTRL + H (0x08)
WHEN x"33" =>
CTRLcombos <= "01000";
PRESSTATE := '1';
-- [HORIZONTAL TAB] CTRL + I (0x09)
WHEN x"43" =>
CTRLcombos <= "01001";
PRESSTATE := '1';
-- [LINE FEED] CTRL + J (0x0A)
WHEN x"3B" =>
CTRLcombos <= "01010";
PRESSTATE := '1';
-- [VERTICAL TAB] CTRL + K (0x0B)
WHEN x"42" =>
CTRLcombos <= "01011";
PRESSTATE := '1';
-- [FORM FEED] CTRL + L (0x0C)
WHEN x"4B" =>
CTRLcombos <= "01100";
PRESSTATE := '1';
-- [CARRIAGE RETURN] CTRL + M (0x0D)
WHEN x"3A" =>
CTRLcombos <= "01101";
PRESSTATE := '1';
-- FROM 0x0E to 0x1A and 0x1C to 0x1F WAS NOT MAPPED
-- [ESCAPE] CTRL + [ (0x1B)
WHEN x"5B" =>
CTRLcombos <= "11011";
PRESSTATE := '1';
WHEN OTHERS =>
ALTpressed <= '0';
CTRLcombos <= "00000";
END CASE;
WHEN '1' =>
IF(SCANPRESSING = '0') THEN
ALTpressed <= '0';
CTRLcombos <= "00000";
PRESSTATE := '0';
END IF;
END CASE;
ELSIF(CLK'EVENT AND CLK = '1' AND SHIFTpressed = '1') THEN
CASE PRESSTATE IS
WHEN '0' =>
CASE SCANCODE IS
-- [!] SHIFT + 1 (0x21)
WHEN x"16" =>
SHIFTcombos <= "0100001";
PRESSTATE := '1';
-- ["] SHIFT + ' (0x22)
WHEN x"0E" =>
SHIFTcombos <= "0100010";
PRESSTATE := '1';
-- [#] SHIFT + 3 (0x23)
WHEN x"26" =>
SHIFTcombos <= "0100011";
PRESSTATE := '1';
-- [$] SHIFT + 4 (0x24)
WHEN x"25" =>
SHIFTcombos <= "0100100";
PRESSTATE := '1';
-- [%] SHIFT + 5 (0x25)
WHEN x"2E" =>
SHIFTcombos <= "0100101";
PRESSTATE := '1';
-- [&] SHIFT + 7 (0x26)
WHEN x"3D" =>
SHIFTcombos <= "0100110";
PRESSTATE := '1';
-- [(] SHIFT + 9 (0x28)
WHEN x"46" =>
SHIFTcombos <= "0101000";
PRESSTATE := '1';
-- [)] SHIFT + 0 (0x29)
WHEN x"45" =>
SHIFTcombos <= "0101001";
PRESSTATE := '1';
-- [*] SHIFT + 8 (0x2A)
WHEN x"3E" =>
SHIFTcombos <= "0101010";
PRESSTATE := '1';
-- [+] SHIFT + = (0x2B)
WHEN x"55" =>
SHIFTcombos <= "0101011";
PRESSTATE := '1';
-- [:] SHIFT + ; (0x3A)
WHEN x"4A" =>
SHIFTcombos <= "0111010";
PRESSTATE := '1';
-- [<] SHIFT + , (0x3C)
WHEN x"41" =>
SHIFTcombos <= "0111100";
PRESSTATE := '1';
-- [>] SHIFT + . (0x3E)
WHEN x"49" =>
SHIFTcombos <= "0111110";
PRESSTATE := '1';
-- [?] SHIFT + / (0x3F)
WHEN x"51" =>
SHIFTcombos <= "0111111";
PRESSTATE := '1';
-- [@] SHIFT + 2 (0x40)
WHEN x"1E" =>
SHIFTcombos <= "1000000";
PRESSTATE := '1';
-- [A] SHIFT + a (0x41)
WHEN x"1C" =>
SHIFTcombos <= "1000001";
PRESSTATE := '1';
-- [B] SHIFT + b (0x42)
WHEN x"32" =>
SHIFTcombos <= "1000010";
PRESSTATE := '1';
-- [C] SHIFT + c (0x43)
WHEN x"21" =>
SHIFTcombos <= "1000011";
PRESSTATE := '1';
-- [D] SHIFT + d (0x44)
WHEN x"23" =>
SHIFTcombos <= "1000100";
PRESSTATE := '1';
-- [E] SHIFT + e (0x45)
WHEN x"24" =>
SHIFTcombos <= "1000101";
PRESSTATE := '1';
-- [F] SHIFT + f (0x46)
WHEN x"2B" =>
SHIFTcombos <= "1000110";
PRESSTATE := '1';
-- [G] SHIFT + g (0x47)
WHEN x"34" =>
SHIFTcombos <= "1000111";
PRESSTATE := '1';
-- [H] SHIFT + h (0x48)
WHEN x"33" =>
SHIFTcombos <= "1001000";
PRESSTATE := '1';
-- [I] SHIFT + i (0x49)
WHEN x"43" =>
SHIFTcombos <= "1001001";
PRESSTATE := '1';
-- [J] SHIFT + j (0x4A)
WHEN x"3B" =>
SHIFTcombos <= "1001010";
PRESSTATE := '1';
-- [K] SHIFT + k (0x4B)
WHEN x"42" =>
SHIFTcombos <= "1001011";
PRESSTATE := '1';
-- [L] SHIFT + l (0x4C)
WHEN x"4B" =>
SHIFTcombos <= "1001100";
PRESSTATE := '1';
-- [M] SHIFT + m (0x4D)
WHEN x"3A" =>
SHIFTcombos <= "1001101";
PRESSTATE := '1';
-- [N] SHIFT + n (0x4E)
WHEN x"31" =>
SHIFTcombos <= "1001110";
PRESSTATE := '1';
-- [O] SHIFT + o (0x4F)
WHEN x"44" =>
SHIFTcombos <= "1001111";
PRESSTATE := '1';
-- [P] SHIFT + p (0x50)
WHEN x"4D" =>
SHIFTcombos <= "1010000";
PRESSTATE := '1';
-- [Q] SHIFT + q (0x51)
WHEN x"15" =>
SHIFTcombos <= "1010001";
PRESSTATE := '1';
-- [R] SHIFT + r (0x52)
WHEN x"2D" =>
SHIFTcombos <= "1010010";
PRESSTATE := '1';
-- [S] SHIFT + s (0x53)
WHEN x"1B" =>
SHIFTcombos <= "1010011";
PRESSTATE := '1';
-- [T] SHIFT + t (0x54)
WHEN x"2C" =>
SHIFTcombos <= "1010100";
PRESSTATE := '1';
-- [U] SHIFT + u (0x55)
WHEN x"3C" =>
SHIFTcombos <= "1010101";
PRESSTATE := '1';
-- [V] SHIFT + v (0x56)
WHEN x"2A" =>
SHIFTcombos <= "1010110";
PRESSTATE := '1';
-- [W] SHIFT + w (0x57)
WHEN x"1D" =>
SHIFTcombos <= "1010111";
PRESSTATE := '1';
-- [X] SHIFT + x (0x58)
WHEN x"22" =>
SHIFTcombos <= "1011000";
PRESSTATE := '1';
-- [Y] SHIFT + y (0x59)
WHEN x"35" =>
SHIFTcombos <= "1011001";
PRESSTATE := '1';
-- [Z] SHIFT + z (0x5A)
WHEN x"1A" =>
SHIFTcombos <= "1011010";
PRESSTATE := '1';
-- [^] SHIFT + ~ (0x5E)
WHEN x"52" =>
SHIFTcombos <= "1011110";
PRESSTATE := '1';
-- [_] SHIFT + - (0x5F)
WHEN x"4E" =>
SHIFTcombos <= "1011111";
PRESSTATE := '1';
-- [`] SHIFT + ' (0x60)
WHEN x"54" =>
SHIFTcombos <= "1100000";
PRESSTATE := '1';
-- [{] SHIFT + [ (0x7B)
WHEN x"5B" =>
SHIFTcombos <= "1111011";
PRESSTATE := '1';
-- [|] SHIFT + \ (0x7C)
WHEN x"61" =>
SHIFTcombos <= "1111100";
PRESSTATE := '1';
-- [}] SHIFT + ] (0x7D)
WHEN x"5D" =>
SHIFTcombos <= "1111101";
PRESSTATE := '1';
WHEN OTHERS =>
SHIFTcombos <= "0000000";
END CASE;
WHEN '1' =>
IF(SCANPRESSING = '0') THEN
SHIFTcombos <= "0000000";
PRESSTATE := '0';
END IF;
END CASE;
END IF;
END PROCESS;
PROCESS(CLK, RST)
VARIABLE PRESSTATE : STD_LOGIC;
VARIABLE COUNTDOWN : INTEGER RANGE 0 TO 10000000;
BEGIN
IF(RST = '1') THEN
COUNTDOWN := 0;
HALT_REQ <= '0';
RESET_REQ <= '0';
PRESSTATE := '0';
ELSIF(CLK'EVENT AND CLK = '1' AND ALTpressed = '1') THEN
CASE PRESSTATE IS
WHEN '0' =>
CASE SCANCODE IS
-- [RESET] CTRL + ALT + DEL (Emit RESET_REQ)
WHEN x"71" =>
IF(COUNTDOWN = 10000000) THEN
RESET_REQ <= '1';
PRESSTATE := '1';
ELSE
COUNTDOWN := COUNTDOWN + 1;
END IF;
-- [HALT] CTRL + ALT + H (Emit HALT_REQ)
WHEN x"33" =>
HALT_REQ <= '1';
PRESSTATE := '1';
WHEN OTHERS =>
COUNTDOWN := 0;
RESET_REQ <= '0';
HALT_REQ <= '0';
END CASE;
WHEN '1' =>
IF(SCANPRESSING = '0') THEN
COUNTDOWN := 0;
RESET_REQ <= '0';
HALT_REQ <= '0';
PRESSTATE := '0';
END IF;
END CASE;
END IF;
END PROCESS;
PROCESS(CLK, RST)
BEGIN
IF(RST = '1') THEN
ASCII <= x"00";
ELSIF(CLK'EVENT AND CLK = '1') THEN
IF(NOT (CTRLcombos = "00000")) THEN
ASCII <= "000" & CTRLcombos;
ELSIF(NOT (NORMALpress = x"00")) THEN
ASCII <= NORMALpress;
ELSIF(NOT (SHIFTcombos = "0000000")) THEN
ASCII <= '0' & SHIFTcombos;
ELSE
ASCII <= x"00";
END IF;
END IF;
END PROCESS;
END main; | gpl-3.0 | 8ff193ab801ea1614644dd974db8d7a6 | 0.446737 | 2.868209 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/RTL/Router_32_bit_credit_based_packet_drop_classifier.vhd | 3 | 19,736 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic
);
end router_credit_based_PD_C;
architecture behavior of router_credit_based_PD_C is
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic
);
end COMPONENT;
COMPONENT counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, intermittent, Faulty:out std_logic
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR_packet_drop is
generic (
cur_addr_rst: integer := 0;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic;
signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic;
signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic;
signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic;
begin
Faulty_N_out <= sig_Faulty_N_out;
Faulty_E_out <= sig_Faulty_E_out;
Faulty_W_out <= sig_Faulty_W_out;
Faulty_S_out <= sig_Faulty_S_out;
-- all the counter_threshold modules
CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N,
Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out);
CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E,
Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out);
CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W,
Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out);
CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S,
Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out);
CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L,
Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
--- all the LBDRs
LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_N,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_E,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_W,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_S,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_L,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
| gpl-3.0 | 52964c4c9aeb39c7e5900ccd08608153 | 0.562171 | 3.04709 | false | false | false | false |
SKravitsky/ECEC412 | PCMulticycle.vhd | 1 | 510 | library ieee;
use ieee.std_logic_1164.all;
entity PCMulticycle is
port(
clk, d: in std_logic;
AddressIn: in std_logic_vector(31 downto 0);
AddressOut: out std_logic_vector(31 downto 0)
);
end PCMulticycle;
architecture Structural of PCMulticycle is
signal temp: std_logic_vector(31 downto 0) := X"00000000";
begin
AddressOut <= temp;
process(clk)
begin
AddressOut <= temp;
if rising_edge(clk) and d='1' then
temp <= AddressIn;
end if;
end process;
end Structural;
| apache-2.0 | 0713f6764eada6000f954a0b57a54a45 | 0.684314 | 3.469388 | false | false | false | false |
AndyMcC0/UVVM_All | bitvis_vip_gpio/src/vvc_cmd_pkg.vhd | 3 | 6,886 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
--========================================================================================================================
--========================================================================================================================
package vvc_cmd_pkg is
--========================================================================================================================
-- t_operation
-- - VVC and BFM operations
--========================================================================================================================
type t_operation is (
-- UVVM common
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
SET, GET, CHECK, EXPECT
);
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 32;
--========================================================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--========================================================================================================================
type t_vvc_cmd_record is record
-- Common UVVM fields (Used by td_vvc_framework_common_methods_pkg procedures, and thus mandatory)
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued; -- QUEUED/IMMEDIATE
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
-- VVC dedicated fields
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
data_exp : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
-- Common VVC fields
operation => NO_OPERATION, -- Default unless overwritten by a common operation
alert_level => failure,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_command_type,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
delay => 0 ns,
quietness => NON_QUIET,
-- VVC dedicated fields
data => (others => '0'),
data_exp => (others => '0')
);
--========================================================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--========================================================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - These are used for storing the result of the read/receive BFM commands issued by the VVC,
-- - so that the result can be transported from the VVC to the sequencer via a
-- a fetch_result() call as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result matches the return value of read/receive procedure in the BFM.
--===============================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>, natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1));
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
| mit | 5464670c9c8a441114ba44af51835aed | 0.44772 | 5.16967 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/immortal_volt_monitor_instrument.vhd | 3 | 4,892 | --Copyright (C) 2017 Konstantin Shibin
------------------------------------------------------------
-- File name: immortal_volt_monitor_instrument.vhd
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
entity immortal_volt_monitor_instrument is
port (
-- IJTAG connection
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- Monitor connections
control : out std_logic_vector(2 downto 0);
data : in std_logic_vector(31 downto 0)
);
end immortal_volt_monitor_instrument;
architecture rtl of immortal_volt_monitor_instrument is
component SReg is
Generic ( Size : positive := 32);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
DI : in STD_LOGIC_VECTOR (Size-1 downto 0); --DataInPort
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)); --DataOutPort
end component;
signal update_strobe : std_logic;
signal shiftreg_update : std_logic_vector (31 downto 0);
signal threshold_H : std_logic_vector (4 downto 0);
signal threshold_L : std_logic_vector (4 downto 0);
signal monitor_controls : std_logic_vector (2 downto 0);
signal threshold_compare : std_logic;
signal threshold_H_active : std_logic;
signal threshold_L_active : std_logic;
signal f_output_enable : std_logic;
signal data_sync, data_sync_first : std_logic_vector (31 downto 0);
signal UE_prev : std_logic;
begin
-- Shift register for capturing data from monitor and updating control and compare threshold
shiftreg : SReg
Generic map ( Size => 32)
Port map ( -- Scan Interface scan_client ----------
SI => SI, -- Input Port SI = SI
SO => SO,
SEL => SEL,
SE => SE,
CE => CE,
UE => UE,
RST => RST,
TCK => TCK,
DI => data_sync,
DO => shiftreg_update);
-- shiftreg_update description:
-- [4:0] threshold bit position H
-- [9:5] threshold bit position L
-- [10] threshold bit value to compare to
-- [11] F flag output enabled
-- [12] threshold value update enable
-- [30:28] control signals
-- [31] control signals update enable
synchronizer_data : process(TCK,RST)
begin
if RST = '1' then
data_sync_first <= (others => '0');
data_sync <= (others => '0');
elsif TCK'event and TCK = '1' then
data_sync_first <= data;
data_sync <= data_sync_first;
end if ;
end process ; -- synchronizer
update_strobes: process(TCK)
begin
if TCK'event and TCK = '0' then
UE_prev <= UE;
update_strobe <= not UE_prev and UE and SEL;
end if;
end process;
threshold_controls_set: process(TCK, RST)
begin
if RST = '1' then
threshold_H <= (others => '0');
threshold_L <= (others => '0');
threshold_compare <= '0';
f_output_enable <= '0';
monitor_controls <= (others => '0');
elsif TCK'event and TCK = '0' then
if update_strobe = '1' then
if shiftreg_update(12) = '1' then -- update thresholds only when bit 12 allows it
threshold_H <= shiftreg_update(4 downto 0);
threshold_L <= shiftreg_update(9 downto 5);
threshold_compare <= shiftreg_update(10);
f_output_enable <= shiftreg_update(11);
end if;
if shiftreg_update(31) = '1' then -- update controls only when bit 31 allows it
monitor_controls <= shiftreg_update(30 downto 28);
end if;
end if;
end if;
end process;
control <= monitor_controls;
threshold_H_active <= threshold_compare xnor data_sync(to_integer(unsigned(threshold_H)));
threshold_L_active <= threshold_compare xnor data_sync(to_integer(unsigned(threshold_L)));
toF <= (threshold_H_active or threshold_L_active) and f_output_enable;
toC <= not (threshold_H_active and f_output_enable);
end; | gpl-3.0 | 0fa73a93d6936f79a9b011b2b20a2038 | 0.544154 | 3.870253 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/Allocator_with_checkers_with_FI/arbiter_out_one_hot_with_checkers_with_FI.vhd | 3 | 13,022 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use work.component_pack.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- fault injector shift register with serial input signals
TCK: in std_logic;
SE: in std_logic; -- shift enable
UE: in std_logic; -- update enable
SI: in std_logic; -- serial Input
SO: out std_logic; -- serial output
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N, err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E, err_North_req_X_E, err_East_req_X_W, err_West_req_X_S, err_South_req_X_L, err_Local_req_X_N,
err_IDLE_req_X_W, err_North_req_X_W, err_East_req_X_S, err_West_req_X_L, err_South_req_X_N, err_Local_req_X_E,
err_IDLE_req_X_S, err_North_req_X_S, err_East_req_X_L, err_West_req_X_N, err_South_req_X_E, err_Local_req_X_W,
err_IDLE_req_X_L, err_North_req_X_L, err_East_req_X_N, err_West_req_X_E, err_South_req_X_W, err_Local_req_X_S,
err_state_in_onehot, err_no_request_grants, err_request_IDLE_state,
err_request_IDLE_not_Grants, err_state_North_Invalid_Grant, err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant, err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic
);
end;
architecture behavior of arbiter_out is
----------------------------------------
-- Signals related to fault injection --
----------------------------------------
-- Total: 7 bits
signal FI_add_sta: std_logic_vector (6 downto 0); -- 5 bits for fault injection location address (ceil of log2(17) = 5)
-- 2 bits for type of fault (SA0 or SA1)
signal non_faulty_signals: std_logic_vector (16 downto 0); -- 17 bits for internal- and output-related signals (non-faulty)
signal faulty_signals: std_logic_vector(16 downto 0); -- 17 bits for internal- and output-related signals (with single stuck-at fault injected in one of them)
----------------------------------------
--TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : std_logic_vector (5 downto 0) := IDLE; -- : STATE_TYPE := IDLE;
SIGNAL grant_Y_N_sig, grant_Y_E_sig, grant_Y_W_sig, grant_Y_S_sig, grant_Y_L_sig : std_logic; -- needed for connecting output ports
-- of Arbiter_out to checker inputs
-- Signal(s) used for creating the chain of injected fault locations
-- Total: 17 bits ??!!
-- Arbiter_out internal-related signals
signal state_faulty, state_in_faulty: std_logic_vector(5 downto 0);
-- Arbiter_out output-related signals
signal grant_Y_N_sig_faulty, grant_Y_E_sig_faulty, grant_Y_W_sig_faulty, grant_Y_S_sig_faulty, grant_Y_L_sig_faulty: std_logic;
begin
-------------------------------------
---- Related to fault injection -----
-------------------------------------
-- Total: 17 bits
-- for grant_Y_N, ... , grant_Y_L output signals, not sure whether to include them or the signals with _sig suffix in their names ??!!
non_faulty_signals <= state & state_in & grant_Y_N_sig & grant_Y_E_sig & grant_Y_W_sig & grant_Y_S_sig & grant_Y_L_sig;
-- Fault injector module instantiation
FI: fault_injector generic map(DATA_WIDTH => 17, ADDRESS_WIDTH => 5)
port map (data_in=> non_faulty_signals , address => FI_add_sta(6 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals
);
-- Extracting faulty values for internal- and output-related signals
-- Total: 17 bits
state_faulty <= faulty_signals (16 downto 11);
state_in_faulty <= faulty_signals (10 downto 5);
grant_Y_N_sig_faulty <= faulty_signals (4);
grant_Y_E_sig_faulty <= faulty_signals (3);
grant_Y_W_sig_faulty <= faulty_signals (2);
grant_Y_S_sig_faulty <= faulty_signals (1);
grant_Y_L_sig_faulty <= faulty_signals (0);
-- Total: 7 bits
SR: shift_register_serial_in generic map(REG_WIDTH => 7)
port map ( TCK=> TCK, reset=>reset, SE=> SE, UE=> UE, SI=> SI, SO=> SO, data_out_parallel=> FI_add_sta
);
-------------------------------------
-------------------------------------
-- We did this because of the checker outputs!
grant_Y_N <= grant_Y_N_sig;
grant_Y_E <= grant_Y_E_sig;
grant_Y_W <= grant_Y_W_sig;
grant_Y_S <= grant_Y_S_sig;
grant_Y_L <= grant_Y_L_sig;
-- Sequential part
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1' then
state <= state_in;
end if;
end process;
-- Arbiter_out checkers module instantiation
ARBITER_OUT_ONE_HOT_CHECKERS:
Arbiter_out_one_hot_pseudo_checkers
port map (
credit => credit,
req_X_N => X_N_Y, req_X_E => X_E_Y, req_X_W => X_W_Y, req_X_S => X_S_Y, req_X_L => X_L_Y,
state => state_faulty,
grant_Y_N => grant_Y_N_sig_faulty,
grant_Y_E => grant_Y_E_sig_faulty,
grant_Y_W => grant_Y_W_sig_faulty,
grant_Y_S => grant_Y_S_sig_faulty,
grant_Y_L => grant_Y_L_sig_faulty,
state_in => state_in_faulty,
-- Checker outputs
err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => err_IDLE_req_X_N, err_North_req_X_N => err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => err_IDLE_req_X_E, err_North_req_X_E => err_North_req_X_E, err_East_req_X_W => err_East_req_X_W,
err_West_req_X_S => err_West_req_X_S, err_South_req_X_L => err_South_req_X_L, err_Local_req_X_N => err_Local_req_X_N,
err_IDLE_req_X_W => err_IDLE_req_X_W, err_North_req_X_W => err_North_req_X_W, err_East_req_X_S => err_East_req_X_S,
err_West_req_X_L => err_West_req_X_L, err_South_req_X_N => err_South_req_X_N, err_Local_req_X_E => err_Local_req_X_E,
err_IDLE_req_X_S => err_IDLE_req_X_S, err_North_req_X_S => err_North_req_X_S, err_East_req_X_L => err_East_req_X_L,
err_West_req_X_N => err_West_req_X_N, err_South_req_X_E => err_South_req_X_E, err_Local_req_X_W => err_Local_req_X_W,
err_IDLE_req_X_L => err_IDLE_req_X_L, err_North_req_X_L => err_North_req_X_L, err_East_req_X_N => err_East_req_X_N,
err_West_req_X_E => err_West_req_X_E, err_South_req_X_W => err_South_req_X_W, err_Local_req_X_S => err_Local_req_X_S,
err_state_in_onehot => err_state_in_onehot,
err_no_request_grants => err_no_request_grants,
err_request_IDLE_state => err_request_IDLE_state,
err_request_IDLE_not_Grants => err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant => err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant => err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant => err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => err_Grants_onehot_or_all_zero
);
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit)
begin
grant_Y_N_sig <= '0';
grant_Y_E_sig <= '0';
grant_Y_W_sig <= '0';
grant_Y_S_sig <= '0';
grant_Y_L_sig <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1' then
grant_Y_N_sig <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1' then
grant_Y_E_sig <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1' then
grant_Y_W_sig <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S_sig <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L_sig <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
| gpl-3.0 | 5e6c3cf37aa4b990e2d89d4d22466244 | 0.526417 | 3.01505 | false | false | false | false |
ashtonchase/logic_analyzer | target_hardware/Zybo/zybo_top_capture_ctrl_test.vhd | 1 | 10,719 | -------------------------------------------------------------------------------
-- Title : Zybo Board Top Level
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : zybo_top_capture_cotnrol_test.vhd
-- Created : 2016-02-22
-- Last update: 2016-03-11
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: Xilinx Zynq 7000 on a Digilent Zybo Board Top Level Module,
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-22 1.0 ashton Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY zybo_top IS
PORT (
DDR_addr : INOUT STD_LOGIC_VECTOR (14 DOWNTO 0);
DDR_ba : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0);
DDR_cas_n : INOUT STD_LOGIC;
DDR_ck_n : INOUT STD_LOGIC;
DDR_ck_p : INOUT STD_LOGIC;
DDR_cke : INOUT STD_LOGIC;
DDR_cs_n : INOUT STD_LOGIC;
DDR_dm : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
DDR_dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DDR_dqs_n : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
DDR_dqs_p : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
DDR_odt : INOUT STD_LOGIC;
DDR_ras_n : INOUT STD_LOGIC;
DDR_reset_n : INOUT STD_LOGIC;
DDR_we_n : INOUT STD_LOGIC;
FIXED_IO_ddr_vrn : INOUT STD_LOGIC;
FIXED_IO_ddr_vrp : INOUT STD_LOGIC;
FIXED_IO_mio : INOUT STD_LOGIC_VECTOR (53 DOWNTO 0);
FIXED_IO_ps_clk : INOUT STD_LOGIC;
FIXED_IO_ps_porb : INOUT STD_LOGIC;
FIXED_IO_ps_srstb : INOUT STD_LOGIC;
clk : IN STD_LOGIC; -- 125 MHz clock
je : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- PMOD JE inputs
led : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --LED outputs
-- sw : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Switches
btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0) --Buttons
);
END ENTITY zybo_top;
ARCHITECTURE top OF zybo_top IS
-----------------------------------------------------------------------------
-- Components
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
SIGNAL reset, reset_clk_gen : STD_LOGIC := '1'; -- reset (async high, sync low)
SIGNAL run_clk : STD_LOGIC := '0'; -- clock output of the clocking wizard
SIGNAL clk_locked : STD_LOGIC := '0'; -- indicator if the clocking wizard has locked
-----------------------------------------------------------------------------
-- Aliases
-----------------------------------------------------------------------------
ALIAS reset_btn : STD_LOGIC IS btn(0);
CONSTANT DATA_WIDTH : POSITIVE := 8;
SIGNAL din : STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
SIGNAL armed : STD_LOGIC;
SIGNAL triggered : STD_LOGIC;
SIGNAL rst_cmd : STD_LOGIC := '0';
SIGNAL arm_cmd : STD_LOGIC;
SIGNAL sample_enable : STD_LOGIC := '1';
SIGNAL sample_cnt_rst : STD_LOGIC;
SIGNAL delay_cnt_4x : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL read_cnt_4x : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(1000, 16));
SIGNAL par_trig_msk : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := X"00_00_00_03";
SIGNAL par_trig_val : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL capture_rdy : STD_LOGIC;
SIGNAL in_fifo_tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL in_fifo_tvalid : STD_LOGIC;
SIGNAL in_fifo_tlast : STD_LOGIC;
SIGNAL in_fifo_tready : STD_LOGIC;
SIGNAL in_fifo_tfull : STD_LOGIC;
SIGNAL in_fifo_tempty : STD_LOGIC;
SIGNAL in_fifo_tflush : STD_LOGIC;
--
SIGNAL out_fifo_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL out_fifo_tvalid : STD_LOGIC;
SIGNAL out_fifo_tlast : STD_LOGIC;
SIGNAL out_fifo_tready : STD_LOGIC;
COMPONENT design_1_wrapper IS
PORT (
DDR_addr : INOUT STD_LOGIC_VECTOR (14 DOWNTO 0);
DDR_ba : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0);
DDR_cas_n : INOUT STD_LOGIC;
DDR_ck_n : INOUT STD_LOGIC;
DDR_ck_p : INOUT STD_LOGIC;
DDR_cke : INOUT STD_LOGIC;
DDR_cs_n : INOUT STD_LOGIC;
DDR_dm : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
DDR_dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DDR_dqs_n : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
DDR_dqs_p : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
DDR_odt : INOUT STD_LOGIC;
DDR_ras_n : INOUT STD_LOGIC;
DDR_reset_n : INOUT STD_LOGIC;
DDR_we_n : INOUT STD_LOGIC;
FIXED_IO_ddr_vrn : INOUT STD_LOGIC;
FIXED_IO_ddr_vrp : INOUT STD_LOGIC;
FIXED_IO_mio : INOUT STD_LOGIC_VECTOR (53 DOWNTO 0);
FIXED_IO_ps_clk : INOUT STD_LOGIC;
FIXED_IO_ps_porb : INOUT STD_LOGIC;
FIXED_IO_ps_srstb : INOUT STD_LOGIC;
UART_rxd : IN STD_LOGIC;
UART_txd : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL uart_txd, uart_rxd : STD_LOGIC := '0';
BEGIN -- ARCHITECTURE top
je <= out_fifo_tdata(7 DOWNTO 0);
led(1) <= clk_locked;
capture_ctrl_1 : ENTITY work.capture_ctrl
GENERIC MAP (
DATA_WIDTH => DATA_WIDTH)
PORT MAP (
clk => run_clk,
rst => reset,
din => "000000"&btn(2)&btn(1),
armed => led(3),
triggered => led(2),
rst_cmd => reset_btn,
arm_cmd => btn(3),
-- sample_enable => sample_enable,
sample_cnt_rst => sample_cnt_rst,
-- delay_cnt_4x => delay_cnt_4x,
read_cnt_4x => read_cnt_4x,
par_trig_msk => par_trig_msk,
par_trig_val => par_trig_val,
capture_rdy => led(0),
fifo_tdata => in_fifo_tdata,
fifo_tvalid => in_fifo_tvalid,
fifo_tlast => in_fifo_tlast,
fifo_tready => in_fifo_tready,
fifo_tfull => in_fifo_tfull,
fifo_tempty => in_fifo_tempty,
fifo_aresetn => in_fifo_tflush);
sample_storage_block : ENTITY work.storage
GENERIC MAP (
FIFO_SIZE => 2**4)
PORT MAP (
clk => run_clk,
reset => reset,
--
in_fifo_tdata => in_fifo_tdata,
in_fifo_tvalid => in_fifo_tvalid,
in_fifo_tlast => in_fifo_tlast,
in_fifo_tready => in_fifo_tready,
in_fifo_tfull => in_fifo_tfull,
in_fifo_tempty => in_fifo_tempty,
in_fifo_tflush => in_fifo_tflush,
--
out_fifo_tdata => out_fifo_tdata,
out_fifo_tvalid => out_fifo_tvalid,
out_fifo_tlast => out_fifo_tlast,
out_fifo_tready => '1');
-----------------------------------------------------------------------------
-- Component Instatiations
-----------------------------------------------------------------------------
-- purpose: this component will generate the desired system clock based on
-- the 125 MHz input clock. Not the output is already downstream of a global
-- clock buffer
-- inputs : clk, reset
-- outputs: clk_locked
run_clk_component : ENTITY work.clock_gen
PORT MAP (
-- Clock in ports
clk_in1 => clk,
-- Clock out ports
clk_out1 => run_clk,
-- Status and control signals
reset => reset_clk_gen,
locked => clk_locked
);
-- purpose: this process will reset the system when btn0 is pressed
-- type : combinational
-- inputs : reset_btn, clk, clk_locked
-- outputs: reset
run_clk_reset_proc : PROCESS (reset_btn, run_clk) IS
VARIABLE reset_dly_v : STD_LOGIC;
BEGIN -- PROCESS reset_proc
IF reset_btn = '1' THEN
reset <= '1';
reset_dly_v := '1';
ELSIF rising_edge(run_clk) THEN
IF clk_locked = '1' THEN
reset <= reset_dly_v;
reset_dly_v := '0';
ELSE
reset <= '1';
reset_dly_v := '1';
END IF;
END IF;
END PROCESS run_clk_reset_proc;
reset_proc : PROCESS (reset_btn, clk) IS
VARIABLE reset_dly_v : STD_LOGIC;
BEGIN -- PROCESS reset_proc
IF reset_btn = '1' THEN
reset_clk_gen <= '1';
ELSIF rising_edge(clk) THEN
reset_clk_gen <= reset_dly_v;
reset_dly_v := '0';
END IF;
END PROCESS reset_proc;
zynq : ENTITY work.design_1_wrapper
PORT MAP (
DDR_addr => DDR_addr,
DDR_ba => DDR_ba,
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm => DDR_dm,
DDR_dq => DDR_dq,
DDR_dqs_n => DDR_dqs_n,
DDR_dqs_p => DDR_dqs_p,
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio => FIXED_IO_mio,
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
UART_rxd => UART_rxd,
UART_txd => UART_txd);
END ARCHITECTURE top;
| gpl-2.0 | 95fc8cbfa35aeb59ee7eb42dd1c6ee76 | 0.501353 | 3.723168 | false | false | false | false |
elainemielas/CVUT_BI-PNO | cvika/scit4/tb_scit4.vhd | 1 | 1,079 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TB_SCIT4 is
end entity TB_SCIT4;
architecture TB_SCIT4_BODY of TB_SCIT4 is
signal T_A, T_B : std_logic_vector ( 3 downto 0 );
signal T_S : std_logic_vector ( 4 downto 0 );
signal T_Cin : std_logic;
component SCIT4
port (
A, B : in std_logic_vector ( 3 downto 0 );
Cin : in std_logic;
S : out std_logic_vector ( 4 downto 0 )
);
end component;
begin
UUT : SCIT4 port map ( A => T_A, B => T_B, S => T_S, Cin => T_Cin );
TESTA : process
begin
for I in 0 to 15 loop
T_A <= conv_std_logic_vector ( I, 4 );
for J in 0 to 15 loop
T_B <= conv_std_logic_vector ( J, 4 );
T_Cin <= '0';
wait for 30 ns;
assert T_S = conv_std_logic_vector (I + J + 0, 5)
report "chyba!"
severity ERROR;
T_Cin <= '1';
wait for 30 ns;
assert T_S = conv_std_logic_vector (I + J + 1, 5)
report "chyba!"
severity ERROR;
end loop;
end loop;
assert FALSE report "konec" severity FAILURE;
end process;
end architecture TB_SCIT4_BODY; | mit | ac0de9e91741f2cafc7901d9011d371f | 0.60241 | 2.651106 | false | false | false | false |
camacazio/de0_nano_DAC | DE0_12bitDAC_controller/comm_pll.vhd | 1 | 16,301 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: comm_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY comm_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END comm_pll;
ARCHITECTURE SYN OF comm_pll IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire2_bv(0 DOWNTO 0) <= "0";
sub_wire2 <= To_stdlogicvector(sub_wire2_bv);
sub_wire0 <= inclk0;
sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0;
sub_wire5 <= sub_wire3(1);
sub_wire4 <= sub_wire3(0);
c0 <= sub_wire4;
c1 <= sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 10,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 5,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=comm_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire1,
clk => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "10"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "5"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "5.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "10.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "5.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "10.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "comm_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: GEN_FILE: TYPE_NORMAL comm_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL comm_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL comm_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL comm_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL comm_pll.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL comm_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-3.0 | ce013d156158146f4a2210b022edaeb1 | 0.700571 | 3.332856 | false | false | false | false |
camacazio/de0_nano_DAC | DE0_12bitDAC_controller/onchip_memory.vhd | 1 | 8,574 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: onchip_memory.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY onchip_memory IS
PORT
(
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END onchip_memory;
ARCHITECTURE SYN OF onchip_memory IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
q <= sub_wire0(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 16384,
numwords_b => 16384,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
ram_block_type => "M9K",
read_during_write_mode_mixed_ports => "OLD_DATA",
widthad_a => 14,
widthad_b => 14,
width_a => 16,
width_b => 16,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
address_b => rdaddress,
clock0 => clock,
data_a => data,
wren_a => wren,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "262144"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 14 0 INPUT NODEFVAL "rdaddress[13..0]"
-- Retrieval info: USED_PORT: wraddress 0 0 14 0 INPUT NODEFVAL "wraddress[13..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 14 0 wraddress 0 0 14 0
-- Retrieval info: CONNECT: @address_b 0 0 14 0 rdaddress 0 0 14 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL onchip_memory.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL onchip_memory.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL onchip_memory.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL onchip_memory.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL onchip_memory_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 087583f438d18937014b67f8f3f29de4 | 0.687544 | 3.597986 | false | false | false | false |
ashtonchase/logic_analyzer | test/sump_comms_tb.vhd | 1 | 5,341 | -------------------------------------------------------------------------------
-- Title : UART testbench
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : UART_tb.vhd
-- Created : 2016-02-22
-- Last update: 2016-04-06
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: This is the UART testbench
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-03-16 1.0 ian Created
-------------------------------------------------------------------------------
use WORK.all;
library ieee;
use IEEE.std_logic_1164.all;
entity UART_tb is
end entity;
library ieee;
use IEEE.std_logic_1164.all;
architecture test of sump_commsT_tb is
signal clk : std_logic; -- clock
signal rst : std_logic; -- reset
signal rx : std_logic; -- data line from top level
signal tx : std_logic;
signal tx_command : std_logic_vector(31 downto 0); -- data from storage
signal command_ready : std_logic; -- flags for data message collect
signal data_ready : std_logic; -- flag for transmit message
signal data_sent : std_logic; -- flag for transmit message
--
signal command : std_logic_vector(7 downto 0); -- commands for message handler
constant baud_rate : integer := 9600;
constant clock_freq : integer := 10_000_000;
signal recieve_data : std_logic_vector(7 downto 0);
begin
u1 : entity work.uart_comms
generic map (clock_freq => clock_freq,
baud_rate => baud_rate)
port map (clk => clk,
rst => rst,
tx => tx,
rx => rx,
tx_command => tx_command,
command_ready => command_ready,
data_ready => data_ready,
data_sent => data_sent,
command => command);
process (clk)
begin
clk <= not clk after 50 ns; -- 10 MHz clock
end process;
baud_clocking : process (clk)
begin
if(clk = '1' and clk'event) then
if (baud_counter < baud_total-1) then
baud_counter <= baud_counter + 1;
else
baud_counter <= 0;
baud_clock <= not baud_clock;
end if;
end if;
end process baud_clocking;
process
begin
rx <= '1';
rst <= '0';
wait for 10 ns;
receive_data <= "10011100";
wait until rising_edge(baud_clock);
wait until rising_edge(baud_clock);
rx <= '1'; -- nothing
wait until rising_edge(baud_clock);
rx <= '0'; -- stb
wait until rising_edge(baud_clock);
rx <= receive_data(0);
wait until rising_edge(baud_clock);
rx <= receive_data(1);
wait until rising_edge(baud_clock);
rx <= receive_data(2);
wait until rising_edge(baud_clock);
rx <= receive_data(3);
wait until rising_edge(baud_clock);
rx <= receive_data(4);
wait until rising_edge(baud_clock);
rx <= receive_data(5);
wait until rising_edge(baud_clock);
rx <= receive_data(6);
wait until rising_edge(baud_clock);
rx <= receive_data(7);
wait until rising_edge(baud_clock);
rx <= '1'; -- end
assert data_out = receive_data report "data out does not match UART data in" severity failure;
wait for 100 us;
wait until rising_edge(baud_clock);
rx_get_more_data <= '1';
end process;
process
begin
data_ready <= '0';
wait until rising_edge(baud_clock);
wait until rising_edge(baud_clock);
wait until rising_edge(baud_clock);
wait until rising_edge(baud_clock);
tx_command <= "10100111"&"00001111"&"10101010"&"01010101";
data_ready <= '1';
wait for 100 ms;
end process;
end test;
| gpl-2.0 | c617b96b2e9d435ba6c8b66fb6fd505d | 0.495787 | 4.421358 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/memory_xilinx.vhd | 3 | 2,609 | library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-- Library UNISIM;
-- use UNISIM.vcomponents.all;
Library UNIMACRO;
use UNIMACRO.vcomponents.all;
entity memory is
generic(address_width : natural := 16);
port(clk : in std_logic;
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
pause : in std_logic;
byte_we : in std_logic_vector(3 downto 0);
data_read : out std_logic_vector(31 downto 0)
);
end; --entity memory
architecture rtl of memory is
signal data_out : std_logic_vector(31 downto 0);
signal index : integer := 0;
begin
index <= conv_integer(address(16 - 1 downto 2));
BRAM_SINGLE_MACRO_inst : BRAM_SINGLE_MACRO
generic map(
BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "7SERIES", "VIRTEX6, "SPARTAN6"
DO_REG => 0, -- Optional output register (0 or 1)
INIT => X"000000000000000000", -- Initial values on output port
INIT_FILE => "NONE",
WRITE_WIDTH => 32, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
READ_WIDTH => 32, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
SRVAL => X"000000000000000000", -- Set/Reset value for port output
WRITE_MODE => "READ_FIRST" -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
)
port map(
DO => data_out, -- Output data, width defined by READ_WIDTH parameter
ADDR => STD_logic_vector(to_unsigned(index, 10)), -- Input address, width defined by read/write port depth
CLK => CLK, -- 1-bit input clock
DI => data_write, -- Input data port, width defined by WRITE_WIDTH parameter
EN => '1', -- 1-bit input RAM enable
REGCE => '0', -- 1-bit input output register enable
RST => '0', -- 1-bit input reset
WE => byte_we -- Input write enable, width defined by write port depth
);
dram_proc : process(clk, address, byte_we, pause)
begin
if rising_edge(clk) then
if pause = '0' then
data_read <= data_out;
end if;
end if;
end process;
end; --architecture logic
| gpl-3.0 | 0b2edca148c156e359a25d419e3b4432 | 0.541204 | 3.89403 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/NoC_Node.vhd | 3 | 5,391 | ---------------------------------------------------------------------
-- TITLE: NoC_Node
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- ORIGNAL FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity provides a simple NoC node with plasma as its processor
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
entity NoC_Node is
generic( current_address : integer := 0;
stim_file: string :="code.txt";
log_file : string := "output.txt");
port( reset : in std_logic;
clk : in std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0);
Reconfig_command : out std_logic
);
end; --entity NoC_Node
architecture messed_up of NoC_Node is
constant memory_type : string :=
"TRI_PORT_X";
-- "DUAL_PORT_";
-- "ALTERA_LPM";
-- "XILINX_16X";
signal interrupt : std_logic := '0';
signal mem_write : std_logic;
signal address : std_logic_vector(31 downto 2);
signal data_write : std_logic_vector(31 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal pause1 : std_logic := '0';
signal pause2 : std_logic := '0';
signal pause : std_logic;
signal no_ddr_start: std_logic;
signal no_ddr_stop : std_logic;
signal byte_we : std_logic_vector(3 downto 0);
signal uart_write : std_logic;
signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0');
--signal credit_in, valid_in: std_logic := '0';
--signal credit_out, valid_out: std_logic := '0';
--signal RX: std_logic_vector(31 downto 0) := (others => '0');
--signal TX: std_logic_vector(31 downto 0) := (others => '0');
-- signal credit_counter_out_0: std_logic_vector (1 downto 0);
begin --architecture
--pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns;
pause1 <= '0';
--pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns;
pause2 <= '0';
pause <= pause1 or pause2;
--gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK
--gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV
--gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD
--gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK
u1_plasma: plasma
generic map (memory_type => memory_type,
ethernet => '0',
use_cache => '0',
log_file => log_file,
current_address => current_address,
stim_file => stim_file)
PORT MAP (
clk => clk,
reset => reset,
uart_read => uart_write,
uart_write => uart_write,
address => address,
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
mem_pause_in => pause,
no_ddr_start => no_ddr_start,
no_ddr_stop => no_ddr_stop,
gpio0_out => open,
gpioA_in => gpioA_in,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX,
link_faults => link_faults,
turn_faults => turn_faults,
Rxy_reconf_PE => Rxy_reconf_PE,
Cx_reconf_PE => Cx_reconf_PE,
Reconfig_command => Reconfig_command
);
dram_proc: process(clk, address, byte_we, data_write, pause)
constant ADDRESS_WIDTH : natural := 16;
type storage_array is
array(natural range 0 to (2 ** ADDRESS_WIDTH) / 4 - 1) of
std_logic_vector(31 downto 0);
variable storage : storage_array;
variable data : std_logic_vector(31 downto 0);
variable index : natural := 0;
begin
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if byte_we(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if byte_we(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if byte_we(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if byte_we(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
if rising_edge(clk) then
if address(30 downto 28) = "001" and byte_we /= "0000" then
storage(index) := data;
end if;
end if;
if pause = '0' then
data_read <= data;
end if;
end process;
end; --architecture logic
| gpl-3.0 | dd0c2567e2650c16cc8396866b00bd94 | 0.530328 | 3.535082 | false | false | false | false |
Wynjones1/gbvhdl | src/cpu.vhd | 1 | 31,616 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.types.all;
use work.common.all;
use work.interfaces.all;
entity cpu is
port(clk : in std_logic;
reset : in std_logic);
end entity;
architecture rtl of cpu is
component alu is
port( input : in alu_in_if; output : out alu_out_if);
end component;
component memory is
port( clk : in std_logic;
reset : in std_logic;
input : in memory_in_if;
output : out memory_out_if);
end component;
component registers is
port( clk : in std_logic;
reset : in std_logic;
input : in registers_in_if;
output : out registers_out_if);
end component;
component load_logic is
port( clk : in std_logic;
reset : in std_logic;
input : in load_logic_in_if;
output : out load_logic_out_if);
end component;
component alu_logic is
port( clk : in std_logic;
reset : in std_logic;
input : in alu_logic_in_if;
output : out alu_logic_out_if);
end component;
type state_t is (state_load_instr, state_decode_instr,
state_execute_instr, state_wait_for_load,
state_rel_jump, state_call_0, state_call_1,
state_dec_double_0, state_dec_double_1,
state_inc_double_0, state_inc_double_1,
state_ret_0, state_ret_1, state_ret_2,
state_push_0, state_push_1, state_push_2,
state_pop_0, state_pop_1, state_pop_2, state_pop_3,
state_call_2, state_call_3, state_call_4,
state_wait_for_alu, state_increment_pc);
signal state : state_t;
-- alu i/o signals
signal alu_in :alu_logic_in_if;
signal alu_out :alu_logic_out_if;
-- memory i/o signals
signal mem_in : memory_in_if;
signal mem_in_mux : memory_in_if;
signal mem_out : memory_out_if;
-- register i/o signals
signal reg_in : registers_in_if;
signal reg_in_mux : registers_in_if;
signal reg_out : registers_out_if;
-- load store i/o signals
signal load_in : load_logic_in_if;
signal load_out : load_logic_out_if;
-- local signals
signal pc : word_t := (others => '0');
signal instr_string : string(1 to 15);
signal immediate : word_t;
-- instruction decode signals
signal r0,r1 : register_t;
signal f : alu_op_t;
signal t : std_logic_vector(2 downto 0);
signal cc, dd, qq, ss : register_t;
-- load_process signals
signal load_init : std_logic := '0';
signal load_cmd : std_logic_vector(3 downto 0) := (others => '0');
signal load_arg0 : word_t := (others => '0');
signal load_arg1 : word_t := (others => '0');
signal load_reg_out : register_t;
signal load_en : std_logic := '0';
signal alu_en : std_logic := '0';
signal instr_size : integer range 1 to 3;
signal qq_temp : register_t; -- TODO: Clean up this.
signal reg_temp : word_t;
begin
memory0 : memory port map(clk, reset, mem_in_mux, mem_out);
reg0 : registers port map(clk, reset, reg_in_mux, reg_out);
alu0 : alu_logic port map(clk, reset, alu_in, alu_out);
load0 : load_logic port map(clk, reset, load_in, load_out);
load_in.reg <= reg_out;
load_in.mem <= mem_out;
alu_in.reg <= reg_out;
alu_in.mem <= mem_out;
mem_in_mux <= load_out.mem when load_en = '1' else
alu_out.mem when alu_en = '1' else
mem_in;
reg_in_mux <= load_out.reg when load_en = '1' else
alu_out.reg when alu_en = '1' else
reg_in;
r0 <= r_table(mem_out.data(5 downto 3));
f <= f_table(mem_out.data(5 downto 3));
-- t <= t_table(mem_out.data(5 downto 3));
dd <= d_table(mem_out.data(5 downto 4));
qq <= q_table(mem_out.data(5 downto 4));
ss <= s_table(mem_out.data(5 downto 4));
-- cc <= c_table(mem_out.data(4 downto 3));
r1 <= r_table(mem_out.data(2 downto 0));
control_proc:
process(clk, reset)
variable next_instr : word_t;
variable temp_addr : word_t;
begin
if reset = '1' then
state <= state_load_instr;
alu_in.en <= '0';
mem_in.we <= '0'; -- <= (we => '0', others => (others => '0'));
reg_in.we <= '0'; -- <= (we => '0', others => (others => '0'));
elsif rising_edge(clk) then
reg_in.we <= '0';
mem_in.we <= '0';
case state is
when state_load_instr =>
mem_in.address <= reg_out.pc;
state <= state_decode_instr;
when state_decode_instr =>
--report instr_string severity note;
instr_string <= instruction_to_string(mem_out.data);
state <= state_execute_instr;
instr_size <= 1;
reg_in.wsel <= register_pc;
if std_match(mem_out.data, "00000000") then -- NOP
reg_in.we <= '1';
reg_in.data <= std_logic_vector(unsigned(reg_out.pc) + 1);
state <= state_increment_pc;
elsif std_match(mem_out.data, "00000111") then -- RLCA
state <= state_wait_for_alu;
alu_in.en <= '1';
alu_en <= '1';
alu_in.mode <= "00";
alu_in.op <= alu_op_rlc;
alu_in.rsel <= register_a;
elsif std_match(mem_out.data, "00001111") then -- RRCA
state <= state_wait_for_alu;
alu_in.en <= '1';
alu_en <= '1';
alu_in.mode <= "00";
alu_in.op <= alu_op_rrc;
alu_in.rsel <= register_a;
elsif std_match(mem_out.data, "00010000") then -- STOP
elsif std_match(mem_out.data, "00010111") then -- RLA
state <= state_wait_for_alu;
alu_in.en <= '1';
alu_en <= '1';
alu_in.mode <= "00";
alu_in.op <= alu_op_rl;
alu_in.rsel <= register_a;
elsif std_match(mem_out.data, "00011000") then -- JR r8
instr_size <= 2;
state <= state_rel_jump;
mem_in.address <= std_logic_vector(unsigned(reg_out.pc) + 1);
elsif std_match(mem_out.data, "00011111") then -- RRA
elsif std_match(mem_out.data, "00100111") then -- DDA
elsif std_match(mem_out.data, "00101111") then -- CPL
elsif std_match(mem_out.data, "00110100") then -- INC (HL)
state <= state_wait_for_alu;
alu_in.en <= '1';
alu_en <= '1';
alu_in.mode <= "10";
alu_in.rsel <= register_hl;
elsif std_match(mem_out.data, "00110101") then -- DEC (HL)
elsif std_match(mem_out.data, "00110111") then -- SCF
elsif std_match(mem_out.data, "00111111") then -- CCF
elsif std_match(mem_out.data, "11000011") then -- JP d16
elsif std_match(mem_out.data, "11001001") then -- RET
state <= state_ret_0;
mem_in.address <= reg_out.sp;
elsif std_match(mem_out.data, "11001011") then -- CB
state <= state_wait_for_alu;
alu_in.en <= '1';
alu_en <= '1';
alu_in.mode <= "11";
alu_in.op <= alu_op_cb;
instr_size <= 2;
elsif std_match(mem_out.data, "11001101") then -- CALL d16
state <= state_call_0;
-- TODO: We could start the loads here.
elsif std_match(mem_out.data, "11011001") then -- RETI
elsif std_match(mem_out.data, "11101000") then -- ADD SP r8
elsif std_match(mem_out.data, "11101001") then -- JP PC (HL)
elsif std_match(mem_out.data, "11110011") then -- DI
elsif std_match(mem_out.data, "11111011") then -- EI
elsif std_match(mem_out.data, "00000010") then -- LD (BC) A
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_bc;
load_in.r1 <= register_a;
load_in.indirect <= "01";
load_in.inc_dec <= "00";
elsif std_match(mem_out.data, "00001000") then -- LD (d16) SP
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_d16;
load_in.r1 <= register_sp;
load_in.indirect <= "01";
load_in.inc_dec <= "00";
instr_size <= 3;
elsif std_match(mem_out.data, "00001010") then -- LD A (BC)
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_a;
load_in.r1 <= register_bc;
load_in.indirect <= "10";
load_in.inc_dec <= "00";
elsif std_match(mem_out.data, "00010010") then -- LD (DE) A
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_de;
load_in.r1 <= register_a;
load_in.indirect <= "01";
load_in.inc_dec <= "00";
elsif std_match(mem_out.data, "00011010") then -- LD A (DE)
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_a;
load_in.r1 <= register_de;
load_in.indirect <= "10";
load_in.inc_dec <= "00";
elsif std_match(mem_out.data, "00100010") then -- LD (HL++) A
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_hl;
load_in.r1 <= register_a;
load_in.indirect <= "01";
load_in.inc_dec <= "01";
elsif std_match(mem_out.data, "00101010") then -- LD A (HL++)
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_a;
load_in.r1 <= register_hl;
load_in.indirect <= "10";
load_in.inc_dec <= "01";
elsif std_match(mem_out.data, "00110010") then -- LD (HL--) A
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_hl;
load_in.r1 <= register_a;
load_in.indirect <= "01";
load_in.inc_dec <= "10";
elsif std_match(mem_out.data, "00110110") then -- LD (HL) d8
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_hl;
load_in.r1 <= register_d8;
load_in.indirect <= "10";
load_in.inc_dec <= "00";
instr_size <= 2;
elsif std_match(mem_out.data, "00111010") then -- LD A (HL--)
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_sp;
load_in.r1 <= register_hl;
load_in.indirect <= "00";
load_in.inc_dec <= "01";
elsif std_match(mem_out.data, "11100010") then -- LD (C) A
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_c;
load_in.r1 <= register_a;
load_in.indirect <= "01";
load_in.inc_dec <= "00";
elsif std_match(mem_out.data, "11101010") then -- LD (d16) A
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_d16;
load_in.r1 <= register_a;
load_in.indirect <= "01";
load_in.inc_dec <= "00";
instr_size <= 3;
elsif std_match(mem_out.data, "11110010") then -- LD A (C)
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_a;
load_in.r1 <= register_c;
load_in.indirect <= "10";
load_in.inc_dec <= "00";
elsif std_match(mem_out.data, "11111000") then -- LD HL SP + r8
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_hl;
load_in.r1 <= register_sp;
load_in.indirect <= "00";
load_in.inc_dec <= "11";
instr_size <= 2;
elsif std_match(mem_out.data, "11111001") then -- LD SP HL
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_sp;
load_in.r1 <= register_hl;
load_in.indirect <= "00";
load_in.inc_dec <= "00";
elsif std_match(mem_out.data, "11111010") then -- LD A (d16)
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_a;
load_in.r1 <= register_d16;
load_in.indirect <= "10";
load_in.inc_dec <= "00";
instr_size <= 3;
elsif std_match(mem_out.data, "11100000") then -- LDH (d8) A
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_d8;
load_in.r1 <= register_a;
load_in.indirect <= "01";
load_in.inc_dec <= "00";
instr_size <= 2;
elsif std_match(mem_out.data, "11110000") then -- LDH A (d8)
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_a;
load_in.r1 <= register_d8;
load_in.indirect <= "10";
load_in.inc_dec <= "00";
instr_size <= 2;
elsif std_match(mem_out.data, "11010011") then -- INVALID
elsif std_match(mem_out.data, "11011011") then -- INVALID
elsif std_match(mem_out.data, "11011101") then -- INVALID
elsif std_match(mem_out.data, "11100011") then -- INVALID
elsif std_match(mem_out.data, "11100100") then -- INVALID
elsif std_match(mem_out.data, "11101011") then -- INVALID
elsif std_match(mem_out.data, "11101100") then -- INVALID
elsif std_match(mem_out.data, "11101101") then -- INVALID
elsif std_match(mem_out.data, "11110100") then -- INVALID
elsif std_match(mem_out.data, "11111100") then -- INVALID
elsif std_match(mem_out.data, "11111101") then -- INVALID
elsif std_match(mem_out.data, "01110110") then -- HALT
elsif std_match(mem_out.data, "01110---") then -- LD (HL) r'
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= register_hl;
load_in.r1 <= r1;
load_in.indirect <= "01";
load_in.inc_dec <= "00";
elsif std_match(mem_out.data, "001--000") then -- JR cc r8
instr_size <= 2;
if need_to_jump(mem_out.data(4 downto 3), reg_out.f(7 downto 4)) then
state <= state_rel_jump;
mem_in.address <= std_logic_vector(unsigned(reg_out.pc) + 1);
else
reg_in.we <= '1';
reg_in.wsel <= register_pc;
reg_in.data <= std_logic_vector(unsigned(reg_out.pc) + 2);
state <= state_increment_pc;
end if;
elsif std_match(mem_out.data, "110--000") then -- RET cc
elsif std_match(mem_out.data, "110--010") then -- JP cc d16
elsif std_match(mem_out.data, "110--100") then -- CALL cc d16
elsif std_match(mem_out.data, "00--0001") then -- LD dd d16
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= dd;
load_in.r1 <= register_d16;
load_in.indirect <= "00";
load_in.inc_dec <= "00";
instr_size <= 3;
elsif std_match(mem_out.data, "00--0011") then -- INC ss
state <= state_inc_double_0;
reg_in.rsel0 <= ss;
elsif std_match(mem_out.data, "00--1001") then -- ADD HL ss
elsif std_match(mem_out.data, "00--1011") then -- DEC ss
state <= state_dec_double_0;
reg_in.rsel0 <= ss;
elsif std_match(mem_out.data, "11--0001") then -- POP qq
state <= state_pop_0;
mem_in.address <= reg_out.sp;
qq_temp <= qq;
elsif std_match(mem_out.data, "11--0101") then -- PUSH qq
state <= state_push_0;
reg_in.rsel0 <= qq;
elsif std_match(mem_out.data, "00---100") then -- INC r
state <= state_wait_for_alu;
alu_in.en <= '1';
alu_en <= '1';
alu_in.mode <= alu_mode_register;
alu_in.rsel <= r0;
alu_in.op <= alu_op_inc;
elsif std_match(mem_out.data, "00---101") then -- DEC r
state <= state_wait_for_alu;
alu_in.en <= '1';
alu_en <= '1';
alu_in.mode <= alu_mode_register;
alu_in.rsel <= r0;
alu_in.op <= alu_op_dec;
elsif std_match(mem_out.data, "00---110") then -- LD r n
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= r0;
load_in.r1 <= register_d8;
load_in.indirect <= "00";
load_in.inc_dec <= "00";
instr_size <= 2;
elsif std_match(mem_out.data, "01---110") then -- LD r (HL)
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= r0;
load_in.r1 <= register_hl;
load_in.indirect <= "10";
load_in.inc_dec <= "00";
elsif std_match(mem_out.data, "10---110") then -- f A (HL)
alu_in.op <= f;
alu_in.en <= '1';
alu_en <= '1';
alu_in.mode <= "10";
state <= state_wait_for_alu;
elsif std_match(mem_out.data, "11---110") then -- f A n
alu_in.op <= f;
alu_in.en <= '1';
alu_en <= '1';
alu_in.mode <= "01";
state <= state_wait_for_alu;
instr_size <= 2;
elsif std_match(mem_out.data, "11---111") then -- RST t
elsif std_match(mem_out.data, "01------") then -- LD r r'
load_in.en <= '1';
load_en <= '1';
state <= state_wait_for_load;
load_in.r0 <= r0;
load_in.r1 <= r1;
load_in.indirect <= "00";
load_in.inc_dec <= "00";
elsif std_match(mem_out.data, "10------") then -- f A r'
state <= state_wait_for_alu;
alu_in.op <= f;
alu_in.rsel <= r1;
alu_in.en <= '1';
alu_in.mode <= "00";
alu_en <= '1';
end if;
when state_execute_instr =>
state <= state_load_instr;
when state_wait_for_load =>
load_in.en <= '0';
if load_out.done = '1' then
state <= state_increment_pc;
alu_en <= '0';
load_en <= '0';
reg_in.we <= '1';
reg_in.data <= std_logic_vector(unsigned(reg_out.pc) + instr_size);
else
state <= state_wait_for_load;
end if;
when state_wait_for_alu =>
alu_in.en <= '0';
if alu_out.done = '1' then
state <= state_increment_pc;
alu_en <= '0';
load_en <= '0';
reg_in.we <= '1';
reg_in.data <= std_logic_vector(unsigned(reg_out.pc) + instr_size);
else
state <= state_wait_for_alu;
end if;
when state_rel_jump =>
state <= state_increment_pc;
reg_in.we <= '1';
reg_in.wsel <= register_pc;
reg_in.data <= std_logic_vector( unsigned(reg_out.pc) + unsigned(resize(signed(mem_out.data), 16)) + 2);
when state_call_0 =>
-- Calculate return instruction
next_instr := std_logic_vector(unsigned(reg_out.pc) + 3);
state <= state_call_1;
-- Write top byte of return address.
mem_in.we <= '1';
mem_in.address <= std_logic_vector(unsigned(reg_out.sp) - 1);
mem_in.data <= next_instr(HI_BYTE);
when state_call_1 =>
temp_addr := std_logic_vector(unsigned(reg_out.sp) - 2);
state <= state_call_2;
-- Write bottom byte of return address.
mem_in.we <= '1';
mem_in.address <= temp_addr;
mem_in.data <= next_instr(LO_BYTE);
-- Adjust the stack pointer
reg_in.we <= '1';
reg_in.wsel <= register_sp;
reg_in.data <= temp_addr;
when state_call_2 =>
-- Set up read of first immediate byte.
state <= state_call_3;
mem_in.address <= std_logic_vector(unsigned(reg_out.pc) + 1);
when state_call_3 =>
state <= state_call_4;
temp_addr(LO_BYTE) := mem_out.data;
-- Set up read of second immediate byte.
mem_in.address <= std_logic_vector(unsigned(reg_out.pc) + 2);
when state_call_4 =>
state <= state_increment_pc;
temp_addr(HI_BYTE) := mem_out.data;
reg_in.we <= '1';
reg_in.wsel <= register_pc;
reg_in.data <= temp_addr;
when state_push_0 =>
state <= state_push_1;
mem_in.we <= '1';
mem_in.address <= std_logic_vector(unsigned(reg_out.sp) - 1);
mem_in.data <= reg_out.d0(HI_BYTE);
when state_push_1 =>
state <= state_push_2;
temp_addr := std_logic_vector(unsigned(reg_out.sp) - 2);
mem_in.we <= '1';
mem_in.address <= temp_addr;
mem_in.data <= reg_out.d0(LO_BYTE);
reg_in.we <= '1';
reg_in.wsel <= register_sp;
reg_in.data <= temp_addr;
when state_push_2 =>
state <= state_increment_pc;
reg_in.we <= '1';
reg_in.wsel <= register_pc;
reg_in.data <= std_logic_vector(unsigned(reg_out.pc) + 1);
when state_pop_0 =>
state <= state_pop_1;
mem_in.address <= std_logic_vector(unsigned(reg_out.sp) + 1);
reg_temp(LO_BYTE) <= mem_out.data;
when state_pop_1 =>
state <= state_pop_2;
reg_in.we <= '1';
reg_in.wsel <= qq_temp;
reg_in.data <= mem_out.data & reg_temp(LO_BYTE);
when state_pop_2 =>
state <= state_pop_3;
reg_in.we <= '1';
reg_in.wsel <= register_sp;
reg_in.data <= std_logic_vector(unsigned(reg_out.sp) + 2);
when state_pop_3 =>
state <= state_increment_pc;
reg_in.we <= '1';
reg_in.wsel <= register_pc;
reg_in.data <= std_logic_vector(unsigned(reg_out.pc) + 1);
when state_inc_double_0 =>
state <= state_inc_double_1;
reg_in.we <= '1';
reg_in.wsel <= ss;
reg_in.data <= std_logic_vector(unsigned(reg_out.d0) + 1);
when state_inc_double_1 =>
state <= state_increment_pc;
reg_in.we <= '1';
reg_in.wsel <= register_pc;
reg_in.data <= std_logic_vector(unsigned(reg_out.pc) + 1);
when state_dec_double_0 =>
state <= state_dec_double_1;
reg_in.we <= '1';
reg_in.wsel <= ss;
reg_in.data <= std_logic_vector(unsigned(reg_out.d0) - 1);
when state_dec_double_1 =>
state <= state_increment_pc;
reg_in.we <= '1';
reg_in.wsel <= register_pc;
reg_in.data <= std_logic_vector(unsigned(reg_out.pc) + 1);
when state_ret_0 =>
state <= state_ret_1;
reg_temp(LO_BYTE) <= mem_out.data;
mem_in.address <= std_logic_vector(unsigned(reg_out.sp) + 1);
when state_ret_1 =>
state <= state_ret_2;
reg_in.we <= '1';
reg_in.wsel <= register_pc;
reg_in.data <= mem_out.data & reg_temp(LO_BYTE);
when state_ret_2 =>
state <= state_increment_pc;
reg_in.we <= '1';
reg_in.wsel <= register_sp;
reg_in.data <= std_logic_vector(unsigned(reg_out.sp) + 2);
when state_increment_pc =>
state <= state_load_instr;
end case;
end if;
end process;
end architecture;
| mit | 2e0a2b46cdf2be19cceda5d7d280203a | 0.380092 | 4.055933 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/Arbiter_out_one_hot_pseudo_checkers.vhd | 12 | 21,948 | --Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_out_one_hot_pseudo_checkers is
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : in std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N,
err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E,
err_North_req_X_E,
err_East_req_X_W,
err_West_req_X_S,
err_South_req_X_L,
err_Local_req_X_N,
err_IDLE_req_X_W,
err_North_req_X_W,
err_East_req_X_S,
err_West_req_X_L,
err_South_req_X_N,
err_Local_req_X_E,
err_IDLE_req_X_S,
err_North_req_X_S,
err_East_req_X_L,
err_West_req_X_N,
err_South_req_X_E,
err_Local_req_X_W,
err_IDLE_req_X_L,
err_North_req_X_L,
err_East_req_X_N,
err_West_req_X_E,
err_South_req_X_W,
err_Local_req_X_S,
err_state_in_onehot,
err_no_request_grants,
err_request_IDLE_state,
err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic
);
end Arbiter_out_one_hot_pseudo_checkers;
architecture behavior of Arbiter_out_one_hot_pseudo_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= grant_Y_N & grant_Y_E & grant_Y_W & grant_Y_S & grant_Y_L;
-- Checkers
--checked
process (Requests, state_in)
begin
if (Requests = "00000" and state_in /= IDLE ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_req_X_N <= '1';
else
err_IDLE_req_X_N <= '0';
end if;
end process;
--checked
process (state, req_X_N, state_in)
begin
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_req_X_N <= '1';
else
err_North_req_X_N <= '0';
end if;
end process;
--checked
process (state, credit, req_X_N, grant_Y_N)
begin
if ( state = North and credit /= "00" and req_X_N = '1' and grant_Y_N /= '1' ) then
err_North_credit_not_zero_req_X_N_grant_N <= '1';
else
err_North_credit_not_zero_req_X_N_grant_N <= '0';
end if;
end process;
--checked
process (state, credit, req_X_N, grant_Y_N)
begin
if ( state = North and (credit = "00" or req_X_N = '0') and grant_Y_N /= '0' ) then
err_North_credit_zero_or_not_req_X_N_not_grant_N <= '1';
else
err_North_credit_zero_or_not_req_X_N_not_grant_N <= '0';
end if;
end process;
--checked
process (state, req_X_E, state_in)
begin
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_req_X_E <= '1';
else
err_East_req_X_E <= '0';
end if;
end process;
--checked
process (state, credit, req_X_E, grant_Y_E)
begin
if ( state = East and credit /= "00" and req_X_E = '1' and grant_Y_E = '0' ) then
err_East_credit_not_zero_req_X_E_grant_E <= '1';
else
err_East_credit_not_zero_req_X_E_grant_E <= '0';
end if;
end process;
--checked
process (state, credit, req_X_E, grant_Y_E)
begin
if ( state = East and (credit = "00" or req_X_E = '0') and grant_Y_E /= '0' ) then
err_East_credit_zero_or_not_req_X_E_not_grant_E <= '1';
else
err_East_credit_zero_or_not_req_X_E_not_grant_E <= '0';
end if;
end process;
--checked
process (state, req_X_W, state_in)
begin
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_req_X_W <= '1';
else
err_West_req_X_W <= '0';
end if;
end process;
--checked
process (state, credit, req_X_W, grant_Y_W)
begin
if ( state = West and credit /= "00" and req_X_W = '1' and grant_Y_W = '0') then
err_West_credit_not_zero_req_X_W_grant_W <= '1';
else
err_West_credit_not_zero_req_X_W_grant_W <= '0';
end if;
end process;
--checked
process (state, credit, req_X_W, grant_Y_W)
begin
if ( state = West and (credit = "00" or req_X_W = '0') and grant_Y_W /= '0' ) then
err_West_credit_zero_or_not_req_X_W_not_grant_W <= '1';
else
err_West_credit_zero_or_not_req_X_W_not_grant_W <= '0';
end if;
end process;
--checked
process (state, req_X_S, state_in)
begin
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_req_X_S <= '1';
else
err_South_req_X_S <= '0';
end if;
end process;
--checked
process (state, credit, req_X_S, grant_Y_S)
begin
if ( state = South and credit /= "00" and req_X_S = '1' and grant_Y_S = '0' ) then
err_South_credit_not_zero_req_X_S_grant_S <= '1';
else
err_South_credit_not_zero_req_X_S_grant_S <= '0';
end if;
end process;
--checked
process (state, credit, req_X_S, grant_Y_S)
begin
if ( state = South and (credit = "00" or req_X_S = '0') and grant_Y_S /= '0' ) then
err_South_credit_zero_or_not_req_X_S_not_grant_S <= '1';
else
err_South_credit_zero_or_not_req_X_S_not_grant_S <= '0';
end if;
end process;
--checked
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_req_X_L <= '1';
else
err_Local_req_X_L <= '0';
end if;
end process;
--checked
process (state, credit, req_X_L, grant_Y_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
credit /= "00" and req_X_L = '1' and grant_Y_L = '0' ) then
err_Local_credit_not_zero_req_X_L_grant_L <= '1';
else
err_Local_credit_not_zero_req_X_L_grant_L <= '0';
end if;
end process;
--checked
process (state, credit, req_X_L, grant_Y_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
( credit = "00" or req_X_L = '0') and grant_Y_L /= '0' ) then
err_Local_credit_zero_or_not_req_X_L_not_grant_L <= '1';
else
err_Local_credit_zero_or_not_req_X_L_not_grant_L <= '0';
end if;
end process;
-- Checked
-- Double checked!
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 2
--checked
-- IDLE
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_req_X_E <= '1';
else
err_IDLE_req_X_E <= '0';
end if;
end process;
-- North
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_req_X_E <= '1';
else
err_North_req_X_E <= '0';
end if;
end process;
-- East
process (state, req_X_E, req_X_W, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_req_X_W <= '1';
else
err_East_req_X_W <= '0';
end if;
end process;
-- West
process (state, req_X_W, req_X_S, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_req_X_S <= '1';
else
err_West_req_X_S <= '0';
end if;
end process;
-- South
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_req_X_L <= '1';
else
err_South_req_X_L <= '0';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_req_X_N <= '1';
else
err_Local_req_X_N <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_req_X_W <= '1';
else
err_IDLE_req_X_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_req_X_W <= '1';
else
err_North_req_X_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_req_X_S <= '1';
else
err_East_req_X_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_req_X_L <= '1';
else
err_West_req_X_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_req_X_N <= '1';
else
err_South_req_X_N <= '0';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_req_X_E <= '1';
else
err_Local_req_X_E <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_req_X_S <= '1';
else
err_IDLE_req_X_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_req_X_S <= '1';
else
err_North_req_X_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_req_X_L <= '1';
else
err_East_req_X_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_req_X_N <= '1';
else
err_West_req_X_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_req_X_E <= '1';
else
err_South_req_X_E <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_req_X_W <= '1';
else
err_Local_req_X_W <= '0';
end if;
end process;
-- Checked
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_req_X_L <= '1';
else
err_IDLE_req_X_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_req_X_L <= '1';
else
err_North_req_X_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_req_X_N <= '1';
else
err_East_req_X_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_req_X_E <= '1';
else
err_West_req_X_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_req_X_W <= '1';
else
err_South_req_X_W <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_req_X_S <= '1';
else
err_Local_req_X_S <= '0';
end if;
end process;
-- Checked
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
-- Checked
process (Requests, Grants)
begin
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
else
err_no_request_grants <= '0';
end if;
end process;
-- Checked
process (Requests, state_in)
begin
if (Requests /= "00000" and state_in = IDLE) then
err_request_IDLE_state <= '1';
else
err_request_IDLE_state <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
process (state, Grants)
begin
if (state = IDLE and Grants /= "00000") then
err_request_IDLE_not_Grants <= '1';
else
err_request_IDLE_not_Grants <= '0';
end if;
end process;
process (state, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L)
begin
if (state = North and (grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then
err_state_North_Invalid_Grant <= '1';
else
err_state_North_Invalid_Grant <= '0';
end if;
end process;
process (state, grant_Y_N, grant_Y_W, grant_Y_S, grant_Y_L)
begin
if (state = East and (grant_Y_N = '1' or grant_Y_W = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then
err_state_East_Invalid_Grant <= '1';
else
err_state_East_Invalid_Grant <= '0';
end if;
end process;
process (state, grant_Y_N, grant_Y_E, grant_Y_S, grant_Y_L)
begin
if (state = West and (grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then
err_state_West_Invalid_Grant <= '1';
else
err_state_West_Invalid_Grant <= '0';
end if;
end process;
process (state, grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_L)
begin
if (state = South and (grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_L = '1') ) then
err_state_South_Invalid_Grant <= '1';
else
err_state_South_Invalid_Grant <= '0';
end if;
end process;
-- Local or invalid state(s) (a bit different logic!)
process (state, grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S)
begin
if (state /= IDLE and state /= North and state /= East and state /= West and state /= South and
(grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_S = '1') ) then
err_state_Local_Invalid_Grant <= '1';
else
err_state_Local_Invalid_Grant <= '0';
end if;
end process;
-- Because we do not have multi-casting, Grants must always be one-hot or all zeros, no other possible combination for them !
process (Grants)
begin
if (Grants /= "00000" and Grants /= "00001" and Grants /= "00010" and Grants /= "00100" and Grants /= "01000" and Grants /= "10000") then
err_Grants_onehot_or_all_zero <= '1';
else
err_Grants_onehot_or_all_zero <= '0';
end if;
end process;
end behavior; | gpl-3.0 | 390062b3fd06e4d506592a4c6fcf0da8 | 0.488928 | 2.915128 | false | false | false | false |
simoesusp/Processador-ICMC | Software_Assembly/IR_Controller/Processor_IR_PWM_DE2_70/clk_div.vhd | 2 | 3,921 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY clk_div IS
PORT
(
clock_25Mhz : IN STD_LOGIC;
clock_12Mhz : OUT STD_LOGIC;
clock_6Mhz : OUT STD_LOGIC;
clock_3Mhz : OUT STD_LOGIC;
clock_1MHz : OUT STD_LOGIC;
clock_100KHz : OUT STD_LOGIC;
clock_10KHz : OUT STD_LOGIC;
clock_1KHz : OUT STD_LOGIC;
clock_100Hz : OUT STD_LOGIC;
clock_10Hz : OUT STD_LOGIC;
clock_1Hz : OUT STD_LOGIC
);
END clk_div;
ARCHITECTURE a OF clk_div IS
SIGNAL count_1Mhz: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL count_100Khz, count_10Khz, count_1Khz : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL count_100hz, count_10hz, count_1hz : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC;
SIGNAL clock_100hz_int, clock_10Hz_int, clock_1Hz_int, clock_12Mhz_int, clock_6Mhz_int, clock_3Mhz_int : STD_LOGIC;
BEGIN
PROCESS -- 25 divide by 2
BEGIN
WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';
clock_12Mhz_int <= not clock_12Mhz_int;
END PROCESS;
PROCESS -- 12 divide by 2
BEGIN
WAIT UNTIL clock_12Mhz_int'EVENT and clock_12Mhz_int = '1';
clock_6Mhz_int <= not clock_6Mhz_int;
END PROCESS;
PROCESS -- 6 divide by 2
BEGIN
WAIT UNTIL clock_6Mhz_int'EVENT and clock_6Mhz_int = '1';
clock_3Mhz_int <= not clock_3Mhz_int;
END PROCESS;
PROCESS
BEGIN
-- Divide by 25
WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';
IF count_1Mhz < 24 THEN
count_1Mhz <= count_1Mhz + 1;
ELSE
count_1Mhz <= "00000";
END IF;
IF count_1Mhz < 12 THEN
clock_1Mhz_int <= '0';
ELSE
clock_1Mhz_int <= '1';
END IF;
-- Ripple clocks are used in this code to save prescalar hardware
-- Sync all clock prescalar outputs back to master clock signal
clock_12Mhz <= clock_12Mhz_int;
clock_3Mhz <= clock_3Mhz_int;
clock_1Mhz <= clock_1Mhz_int;
clock_100Khz <= clock_100Khz_int;
clock_10Khz <= clock_10Khz_int;
clock_1Khz <= clock_1Khz_int;
clock_100hz <= clock_100hz_int;
clock_10hz <= clock_10hz_int;
clock_6Mhz <= clock_6Mhz_int;
clock_1hz <= clock_1hz_int;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_1Mhz_int'EVENT and clock_1Mhz_int = '1';
IF count_100Khz /= 4 THEN
count_100Khz <= count_100Khz + 1;
ELSE
count_100khz <= "000";
clock_100Khz_int <= NOT clock_100Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_100Khz_int'EVENT and clock_100Khz_int = '1';
IF count_10Khz /= 4 THEN
count_10Khz <= count_10Khz + 1;
ELSE
count_10khz <= "000";
clock_10Khz_int <= NOT clock_10Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_10Khz_int'EVENT and clock_10Khz_int = '1';
IF count_1Khz /= 4 THEN
count_1Khz <= count_1Khz + 1;
ELSE
count_1khz <= "000";
clock_1Khz_int <= NOT clock_1Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_1Khz_int'EVENT and clock_1Khz_int = '1';
IF count_100hz /= 4 THEN
count_100hz <= count_100hz + 1;
ELSE
count_100hz <= "000";
clock_100hz_int <= NOT clock_100hz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_100hz_int'EVENT and clock_100hz_int = '1';
IF count_10hz /= 4 THEN
count_10hz <= count_10hz + 1;
ELSE
count_10hz <= "000";
clock_10hz_int <= NOT clock_10hz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_10hz_int'EVENT and clock_10hz_int = '1';
IF count_1hz /= 4 THEN
count_1hz <= count_1hz + 1;
ELSE
count_1hz <= "000";
clock_1hz_int <= NOT clock_1hz_int;
END IF;
END PROCESS;
END a;
| gpl-3.0 | 7375c7c7b669aa2294505f95712685f0 | 0.6228 | 2.691146 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/ram_xilinx_2.vhd | 3 | 181,455 | ---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram_2 is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 8);
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram_2 is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"afafafafafafafafafafafafafafafaf2308000c241400ac273c243c243c273c",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f230c008c8c3caf00af00af2340afaf",
INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f",
INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac",
INIT_04 => X"8c343c00af03af270003278f0300ac008f34af0000000014008f8fafaf03af27",
INIT_05 => X"008f000c2400142480008f0010af03afaf270003278f0300ac008f3c00103000",
INIT_06 => X"008f8f0010af24af03afaf270003278f8f030000140080008f000c000080af24",
INIT_07 => X"03000004008faf24008f000c0024008f0010000c0024008f00102c008faf3000",
INIT_08 => X"0c000080af24008f0010af27000c8f008f002727afafaf03afaf270003278f8f",
INIT_09 => X"3c03af270003278f8f030000140080008fa0248faf24008f0014248024008f00",
INIT_0A => X"0000000003278f8f030000008c3c0010000c0003afaf270003278f0330008c34",
INIT_0B => X"243c000c343c243c24000c343c243c24000c243c000c243c000c243c03afaf27",
INIT_0C => X"24243c243c243caf243caf24000c24243c243c243caf243caf24000c243c000c",
INIT_0D => X"000c343c243c243c243caf243caf24000c343c243c243c243caf243caf24000c",
INIT_0E => X"243c000c000c243c000c243c000c000c243c000c243c000c000c243c000c243c",
INIT_0F => X"3c000c243c0010000c243c0014008c3c000c243c000c243c000c000c243c000c",
INIT_10 => X"af240010af24afaf03afaf270003278f8f0300000c24000c0024008c3c000c24",
INIT_11 => X"0c8f24000010008f001400008f8faf24008f0010af001400000014008f8f0010",
INIT_12 => X"24008faf240010008f8c002400008f3c000c0024008c002400008f3c000c2400",
INIT_13 => X"0c243c0010ac3c24008c3c000c243c0014248f001428008faf24008f000c24af",
INIT_14 => X"0087000c24000c8faf00008f870010a7afafafaf03afaf270003278f8f030000",
INIT_15 => X"0087a730240097af240010008f8c00008f000087000c24000c00008c00008f00",
INIT_16 => X"000c243c0010ac3c24008c3c000c243c0014248f000c8f2400000c243c001428",
INIT_17 => X"87000c24000c8faf0000008f870010a7afafafafaf03afaf270003278f8f0300",
INIT_18 => X"87a730240097af240010008f8c00008f000087000c24000c00008c00008f0000",
INIT_19 => X"008c00008f000087000c24000c8faf0000008f2400870010a7000c2400142800",
INIT_1A => X"000c240014280087a730240097af240010008f8c00008f000087000c24000c00",
INIT_1B => X"000c00008c00008f0000343c87000c24000c8faf0000000014008f870010a724",
INIT_1C => X"24000c240014280087a730240097af240010008f8c00008f0000343c87000c24",
INIT_1D => X"0c24000c00008c00008f0000343c87000c24000c8faf00000014008f870010a7",
INIT_1E => X"2400000c243c0014280087a730240097af240010008f8c00008f0000343c8700",
INIT_1F => X"af270003278f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c8f",
INIT_20 => X"0c24000c00008c002400008f3c000c24000c8faf00008f8f0010afafaf2403af",
INIT_21 => X"008f8f0010af000c24001428008faf24008faf240010008f8c002400008f3c00",
INIT_22 => X"10008f8c002400008f3c000c24000c00008c002400008f3c000c24000c8faf00",
INIT_23 => X"0010ac3c24008c3c000c243c0014248f000c243c001428008faf24008faf2400",
INIT_24 => X"8f0000008fa000278f0000008f0010afaf03afaf270003278f8f0300000c243c",
INIT_25 => X"00af008000278f0010af001428008faf24008fac008f002700008fa400270000",
INIT_26 => X"10008f8c002400008f3c000c24000c0024008c002400008f3c000c24000c8f24",
INIT_27 => X"24000c0024008c002400008f3c000c24000c8f2400af0084002700008faf2400",
INIT_28 => X"3c000c24000c8f2400af008c002700008faf240010008f8c002400008f3c000c",
INIT_29 => X"8faf24008faf240010008f8c002400008f3c000c24000c0024008c002400008f",
INIT_2A => X"8f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c243c00142800",
INIT_2B => X"000c24000c00008c3c000c24000c8faf00008f8fafaf24af2403afaf27000327",
INIT_2C => X"8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f8c3c",
INIT_2D => X"008f8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f",
INIT_2E => X"240010008f8c243c000c24000c00008c243c000c24000c8faf00008faf240010",
INIT_2F => X"008faf240010008f8c243c000c24000c00008c243c000c24000c8faf24008faf",
INIT_30 => X"0014248f000c243caf240010008f8c243c000c00008c243c000c24000c8faf24",
INIT_31 => X"28008c3caf03af27000003278f8f0300000c243c0010ac3c24008c3c000c243c",
INIT_32 => X"a324af03af270003278f0324001000ac3c24008c3cac008f0024003c8c3c0010",
INIT_33 => X"14003c8c340010240010248c3c00100083a4248fa3001000102400100094008f",
INIT_34 => X"af270003278f0324a4008fa30010ac3cac243cac3cac008c3c240018008c3c00",
INIT_35 => X"0010240010248c3c00100083a4248fa3001000102400100094008fa324afaf03",
INIT_36 => X"3cac0024003c8c248c3c001028008c3c0004008f0010008faf008c34af008c34",
INIT_37 => X"af008fafaf03af270003278f0324a4008fa30010ac243cac3cac3cac3c24008c",
INIT_38 => X"10afafafafaf03afaf270003278f038f00140080a00080af24008faf24008f00",
INIT_39 => X"8f8faf240010af240010248f0004008fa3001428008faf24008fa02400278f00",
INIT_3A => X"008f001028008faf0000000014008f8faf00000014008f8f0010af24af000000",
INIT_3B => X"1000008c008f00008f240014008fa000278f0000302430008f00100000302430",
INIT_3C => X"8f0010008c008fa02400278faf24008f0014248f0000100004008faf24008f00",
INIT_3D => X"2700248c008f0010ac008f00008f24000c8f0000008f2700100000008f248c00",
INIT_3E => X"af03af270003278f0300ac343c343cafaf03af270003278f8f0300000c8f0000",
INIT_3F => X"008fafaf03af270003278f038f0014008faf00008f24008faf302c008f0010af"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"b8afaeadacabaaa9a8a7a6a5a4a3a2a1bd000000a560a4a0bd1d8404a5059c1c",
INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9",
INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf",
INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594",
INIT_04 => X"42420200c4a0bebd00e0bdbec0004300c302c2000007624000c2c3c5c4a0bebd",
INIT_05 => X"00c20000040062024300c20000c4a0bebfbd00e0bdbec0004300c30200404200",
INIT_06 => X"00c2c30000c202c4a0bebfbd00e0bdbebfc0000040004200c20000400042c343",
INIT_07 => X"c000004100c2c24200c20000404200c200000000404200c200404200c2c24243",
INIT_08 => X"00400042c34300c20000c2c20000c440c660c2c3c6c5c4a0bebfbd00e0bdbebf",
INIT_09 => X"02a0bebd00e0bdbebfc0000040004200c24303c2c24200c2006202434200c200",
INIT_0A => X"00000000e0bdbebfc002020042020040000000a0bebfbd00e0bdbec042004242",
INIT_0B => X"44020000440245020600004402450206000044020000440200004402a0bebfbd",
INIT_0C => X"04450246024702a24202a202000004450246024702a24202a202000044020000",
INIT_0D => X"00004402450246024702a24202a20200004402450246024702a24202a2020000",
INIT_0E => X"4402000000004402000044020000000044020000440200000000440200004402",
INIT_0F => X"0200004402000000004402004000420200004402000044020000000044020000",
INIT_10 => X"c2020000c202c0c0a0bebfbd00e0bdbebfc00000000400004005004202000044",
INIT_11 => X"00c40500004000c200406200c2c3c24200c20000c000400007624000c2c30000",
INIT_12 => X"4200c2c202006200c24362420300c30200004005004262420300c30200000400",
INIT_13 => X"004402000043024300420200004402006202c300404200c2c24200c2000004c2",
INIT_14 => X"00c20000040000c4c24300c3c20000c0c0c6c5c4a0bebfbd00e0bdbebfc00000",
INIT_15 => X"00c2c2424200c2c202006200c2436200c30200c200000400004000426200c302",
INIT_16 => X"00004402000043024300420200004402006202c30000c4050000004402004042",
INIT_17 => X"c20000040000c4c2006200c2c30000c0c0c7c6c5c4a0bebfbd00e0bdbebfc000",
INIT_18 => X"c2c2424200c2c202006200c2436200c30200c200000400004000426200c30200",
INIT_19 => X"00426200c30200c20000040000c4c2006200c24300c20000c000000400404200",
INIT_1A => X"00000400404200c2c2424200c2c202006200c2436200c30200c2000004000040",
INIT_1B => X"00004000426200c302624202c30000040000c4c2000007624000c3c20000c202",
INIT_1C => X"0200000400404200c2c2424200c2c202006200c2436200c302624202c3000004",
INIT_1D => X"000400004000426200c302624202c30000040000c4c20007624000c3c20000c2",
INIT_1E => X"05000000440200404200c2c2424200c2c202006200c2436200c302624202c300",
INIT_1F => X"bfbd00e0bdbebfc00000004402000043024300420200004402006202c30000c4",
INIT_20 => X"0004000040004262420300c3020000040000c4c26200c2c30000c0c0c202a0be",
INIT_21 => X"00c2c30000c000000400404200c2c24200c2c202006200c24362420300c30200",
INIT_22 => X"6200c24362420300c302000004000040004262420300c3020000040000c4c262",
INIT_23 => X"000043024300420200004402006202c30000440200404200c2c24200c2c20200",
INIT_24 => X"c2030200c24382c4c2030200c20000c0c0a0bebfbd00e0bdbebfc00000004402",
INIT_25 => X"00c2004262c3c20000c000404200c2c24200c24300c362c30200c24382c40200",
INIT_26 => X"6200c24362420300c30200000400004005004262420300c3020000040000c405",
INIT_27 => X"0400004005004262420300c3020000040000c40500c2004262c30200c2c20200",
INIT_28 => X"020000040000c40500c2004262c30200c2c202006200c24362420300c3020000",
INIT_29 => X"c2c24200c2c202006200c24362420300c30200000400004005004262420300c3",
INIT_2A => X"bebfc00000004402000043024300420200004402006202c30000440200404200",
INIT_2B => X"0000040000400042020000040000c4c26200c2c3c0c202c202a0bebfbd00e0bd",
INIT_2C => X"434202000004000040004242020000040000c4c26200c2c3c202006200c24302",
INIT_2D => X"00c2434202000004000040004242020000040000c4c26200c2c3c202006200c2",
INIT_2E => X"02006200c2434202000004000040004242020000040000c4c20200c2c2020062",
INIT_2F => X"00c2c202006200c2434202000004000040004242020000040000c4c24200c2c2",
INIT_30 => X"006202c300004402c202006200c2434202000040004242020000040000c4c242",
INIT_31 => X"42004202c4a0bebd0000e0bdbebfc00000004402000043024300420200004402",
INIT_32 => X"c202c4a0bebd00e0bdbec0020000004302430042024300c36242030243020040",
INIT_33 => X"40620243020000020062024302004000c24303c2c000000043030040004200c2",
INIT_34 => X"bebd00e0bdbec0024000c2c00000400243030240024300630302004000420200",
INIT_35 => X"0000020062024302004000c24303c2c000000043030040004200c2c202c0c4a0",
INIT_36 => X"02438242040243024402004042004202004000c2004000c2c2004202c2004202",
INIT_37 => X"c200c2c5c4a0bebd00e0bdbec0024000c2c00000430302400240024302430042",
INIT_38 => X"00c0c7c6c5c4a0bebfbd00e0bdbec0c200400042430063c46400c3c34300c200",
INIT_39 => X"c2c3c2020000c202006202c3004100c2c000404200c2c24200c2430362c3c200",
INIT_3A => X"00c200404200c2c2000007624000c3c2c20007624000c3c20000c202c2006200",
INIT_3B => X"4062004200c26200c203004000c26283c4c3020242424200c200000202424242",
INIT_3C => X"c20040004200c2430362c3c2c24200c2006202c3000000004100c2c24200c200",
INIT_3D => X"c362034200c200004300c26200c2030000c4406200c2c30040628200c2044300",
INIT_3E => X"c4a0bebd00e0bdbec0004363034202c5c4a0bebd00e0bdbebfc0000000c44062",
INIT_3F => X"00c2c5c4a0bebd00e0bdbec0c2004000c2c26200c34200c2c2424200c20000c0"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000000000000000ff00000800ff1800350035003300b200",
INIT_01 => X"000000000000000000000000000000000000072000002000d800d800ff700000",
INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000",
INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000200000f000ff00000000e800000000800010100000000000000000f000ff",
INIT_05 => X"0000000000000000000000000000f00000ff00000000e8000000002000ff0000",
INIT_06 => X"0000000000000000f00000ff0000000000e80000ff0000000000002000000000",
INIT_07 => X"e80000ff000000ff000000002000000000000000200000000000000000000010",
INIT_08 => X"0020000000000000000000000007002800380000000000f00000ff0000000000",
INIT_09 => X"20f000ff0000000000e80000ff0000000000000000ff000000000000ff000000",
INIT_0A => X"0000000000000000e8161600002000ff000100f00000ff00000000e800000000",
INIT_0B => X"2a00000256922700000002561227000000002a0000002a0000002a00f00000ff",
INIT_0C => X"032800280028000028000000000200280028002800002800000000002a000000",
INIT_0D => X"0002230029002900290000290000000002430028002900290000290000000002",
INIT_0E => X"2a00000400002a0000002a00000500002a0000002a00000300002a0000002a00",
INIT_0F => X"0000002b00000000002b00000000330000002b0000002b00000200002a000000",
INIT_10 => X"0000000000000000f00000ff0000000000e8000000000001200030330000002b",
INIT_11 => X"010000300000000000ff10000000000000000000000000100000000000000000",
INIT_12 => X"0000000000000000000010241800000000012000300010241800000000000000",
INIT_13 => X"002b00000033000000330000002b000000000000ff0300000000000000000000",
INIT_14 => X"0000000000000000001000000000000000000000f00000ff0000000000e80000",
INIT_15 => X"000000ff00000000000000000000100000100000000000000020000010000010",
INIT_16 => X"00002b00000033000000330000002b0000000000000100003000002b0000ff00",
INIT_17 => X"000000000000000010000000000000000000000000f00000ff0000000000e800",
INIT_18 => X"0000ff0000000000000000000010000010000000000000002000001000001000",
INIT_19 => X"0000100000100000000000000000001000000001000000000000000000ff0000",
INIT_1A => X"00000000ff00000000ff00000000000000000000100000100000000000000020",
INIT_1B => X"00002000001000001010ff3f0000000000000000101000000000000000000000",
INIT_1C => X"0000000000ff00000000ff000000000000000000001000001010ff3f00000000",
INIT_1D => X"000000002000001000001010ff3f000000000000000010000000000000000000",
INIT_1E => X"003000002b0000ff00000000ff000000000000000000001000001010ff3f0000",
INIT_1F => X"00ff0000000000e80000002b00000033000000330000002b0000000000000100",
INIT_20 => X"000000002000001029180000000000000000000010000000000000000012f000",
INIT_21 => X"00000000000000000000ff000000000000000000000000000010291800000000",
INIT_22 => X"00000000102a180000000000000000200000102a180000000000000000000010",
INIT_23 => X"000033000000330000002b000000000000002c0000ff00000000000000000000",
INIT_24 => X"001c1c0000001000001e1e000000000000f00000ff0000000000e80000002b00",
INIT_25 => X"3000000010000000000000ff0000000000000000000010001000000010001000",
INIT_26 => X"00000000102c18000000000000000120003000102c1800000000000000010000",
INIT_27 => X"00000120003000102c1800000000000000010000300000001000100000000000",
INIT_28 => X"000000000001000030000000100010000000000000000000102c180000000000",
INIT_29 => X"000000000000000000000000102c18000000000000000120003000102c180000",
INIT_2A => X"0000e80000002b00000033000000330000002b000000000000002c0000ff0000",
INIT_2B => X"000000000020002c0000000000000000100000000000430012f00000ff000000",
INIT_2C => X"002c0000000000002000002c0000000000000000100000000000000000002c00",
INIT_2D => X"0000002c0000000000002000002c000000000000000010000000000000000000",
INIT_2E => X"0000000000002c0000000000002000002c000000000000000010000000000000",
INIT_2F => X"0000000000000000002c0000000000002000002c000000000000000000000000",
INIT_30 => X"0000000000002c00000000000000002c0000002000002c0000000000000000ff",
INIT_31 => X"0000330000f000ff000000000000e80000002b00000033000000330000002b00",
INIT_32 => X"000000f000ff00000000e8ff0000103300000033000000001035180033000000",
INIT_33 => X"0010400080000000000000320000000000000000000000000000000000000000",
INIT_34 => X"00ff00000000e8000000000000ff33003300003200000035007f000000330000",
INIT_35 => X"00000000000033000000000000000000000000000000000000000000000000f0",
INIT_36 => X"000010352000007f330000000000330000000000000000000000008000000080",
INIT_37 => X"0000000000f000ff00000000e8000000000000ff330000330032003300000033",
INIT_38 => X"000000000000f00000ff00000000e80000ff0000000000000000000000000000",
INIT_39 => X"000000ff0000000000000000000000000000ff00000000000000000010000000",
INIT_3A => X"0000000000000000101000000000000000100000000000000000000000100000",
INIT_3B => X"0010000000001800000000000000001800001616000000000000001616000000",
INIT_3C => X"00000000000000000010000000ff00000000ff0000000000ff000000ff000000",
INIT_3D => X"0010000000000000000000180000000006002810000000000010100000000000",
INIT_3E => X"00f000ff00000000e80000fc0000200000f000ff0000000000e8000006002810",
INIT_3F => X"00000000f000ff00000000e80000ff000000100000ff00000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"4c4844403c3834302c2824201c181410980e00ac04fd2a001800b0000000f001",
INIT_01 => X"504c4844403c3834302c2824201c18141000cc2410200060125c1058fc005450",
INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854",
INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410",
INIT_04 => X"00200000082504f80008100c2500000000100012100d1b020014101410250cf0",
INIT_05 => X"001800980d00040a000018001318251014e80008080425000000080000fa0200",
INIT_06 => X"001020001e101c2025181ce00008181014250000e90000001800982500001801",
INIT_07 => X"250000e0001010fc0010009825570014000700982530001400090a0014140f06",
INIT_08 => X"9825000010010010001810140016a025a42514a8a8a4a025989c60000820181c",
INIT_09 => X"002504f80008a0989c250000e400000010000d1010ff001000080a00ff001000",
INIT_0A => X"000000000818101425030000000000fd003c00251014e8000808042501000020",
INIT_0B => X"8000008878348c0002008878340c000100ae680000ae540000ae3c0025181ce0",
INIT_0C => X"2184009c00b40010d800140200e7070c0024003c00106000140100ae680000ae",
INIT_0D => X"00e7450174008c00a40010c800140400e72105fc0014002c00105000140300e7",
INIT_0E => X"f800008b00ae680000aee000006300ae680000aec80000fe00ae680000aea800",
INIT_0F => X"0000ae5000001300ae4800000700100000ae380000ae2800001400ae680000ae",
INIT_10 => X"1403004b10031c18252024d8000820181c250000980a0005250a25100000ae5c",
INIT_11 => X"05100a250026001400eb2a00101414020014000b140004100d1a020014100011",
INIT_12 => X"0100181c0100030010002170800018000005250a250021708000180000983a00",
INIT_13 => X"ae9c00000510000100100000ae7400000d011c00b2e800101002001000982018",
INIT_14 => X"001000983a00d4181807002810002c1014302c28252024d80008282024250000",
INIT_15 => X"001010ff0100101401000300180021002c80001000982000d425000021002c80",
INIT_16 => X"00aee400000510000100100000aed800000d01140005300a2500aec40000d120",
INIT_17 => X"1000983a00d418181218002810002d101434302c28252024d800082820242500",
INIT_18 => X"1010ff0100101401000300180021002c80001000982000d425000021002c8000",
INIT_19 => X"000021003080001000983a00d4181812180028230010002f1000980a00d00600",
INIT_1A => X"00980a00ce06001010ff0100101401000300180021003080001000982000d425",
INIT_1B => X"00d42500002100348021ffff1000983a00d4181812100d1a0200281000341001",
INIT_1C => X"0100980a00c90a001010ff010010140100030018002100348021ffff10009820",
INIT_1D => X"982000d42500002100388021ffff1000983a00d41818100d1a02002810003310",
INIT_1E => X"0a2500aef00000ca0a001010ff010010140100030018002100388021ffff1000",
INIT_1F => X"24d80008282024250000aee400000510000100100000aed800000d011400053c",
INIT_20 => X"982000d425000021ec8000100000983a00d41c1c21001018002b101418342520",
INIT_21 => X"001018002b1000980a00d20a00101001001014010003001c0021ec8000100000",
INIT_22 => X"03001c0021148000100000982000d425000021148000100000983a00d41c1c23",
INIT_23 => X"000510000100100000aed800000d011400ae140000d20a001010010010140100",
INIT_24 => X"10030000100c21101003000010001f1014259094680008282024250000aee400",
INIT_25 => X"2518000c21101000871000de0a0010100100103c001021108000101c21104000",
INIT_26 => X"030018002158800010000098200005250a250021588000100000983a0005180a",
INIT_27 => X"200005250a250021588000100000983a0005180a2518001c2110400010140100",
INIT_28 => X"0000983a0005180a2518003c2110800010140100030018002158800010000098",
INIT_29 => X"10100100101401000300180021588000100000980a0005250a25002158800010",
INIT_2A => X"9094250000aee400000510000100100000aed800000d011400ae300000760a00",
INIT_2B => X"00982000d42500800000983a00d41c1c240018141018211434252024d8000898",
INIT_2C => X"04800000982000d4250004800000983a00d41c1c2500181410010003001c8000",
INIT_2D => X"001c08800000982000d4250008800000983a00d41c1c2600181410010003001c",
INIT_2E => X"010003001c0c800000982000d425000c800000983a00d41c1c27001410010003",
INIT_2F => X"001410010003001c10800000982000d4250010800000983a00d41c1c12001410",
INIT_30 => X"000d011000ae400010010003001c14800000d4250014800000983a00d41c1cee",
INIT_31 => X"0f002400082504f8000008282024250000aee400000510000100100000aed800",
INIT_32 => X"000110250cf00008080425ff0002252400010024000000082130800024000013",
INIT_33 => X"0b24000000001f01000401f0000006000000321000002a000732000600000010",
INIT_34 => X"14e80008100c25030000100000d82c00280100f00000003000fc000600240000",
INIT_35 => X"003401000401280000060000005d1800003f00075d0006000000180001041825",
INIT_36 => X"00002170800000fc200000100f00200000160008001a00040800000004000004",
INIT_37 => X"0000101410250cf00008181425030000180000c32c01002800f0002000010020",
INIT_38 => X"0a104c48444025383cc00008100c250000f20000000000140100141001001000",
INIT_39 => X"184018ff0003180100050a48000500402f00f30f001010010010102021101000",
INIT_3A => X"0010000a0a00101c12100d1b02001c4810100d1b02001c48003e140e1c121800",
INIT_3B => X"0b2a0000004c2300140f000c001c102110140300ff57ff001000080300ff30ff",
INIT_3C => X"4c000b0000004c102d21101414ff0014000aff1800000200c0001414ff001400",
INIT_3D => X"20230f00004c000c00004c2300140f00f844252100142000122a2300140f0000",
INIT_3E => X"10250cf000080804250000180360000c082504f8000840383c250000f8442521",
INIT_3F => X"00080c082504f80008100c250000f1001010240010ff001000ff010000000d00"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"00008f8faf000c8faf0000008f00008fafaf03afaf270003278f030000008f00",
INIT_01 => X"8f0000003c8fac008fac008fac008f30008fafafafafaf03af270003278f8f03",
INIT_02 => X"0010248f001428008faf24008faf00008f0030003000008f8c008f0010afac00",
INIT_03 => X"10240014008f8f001024001000008f8c008f001024001000008f8c008f001024",
INIT_04 => X"03af270003278f0300008faf03af270003278f0300001024001028008c008f00",
INIT_05 => X"343c000c243c000c343c34af24afaf03afafaf27000003278f030000343c8faf",
INIT_06 => X"240004008c340010ac24ac343c24ae000c242424000c243cac008f343caf008c",
INIT_07 => X"008fae000c242424000c24000c0024008f000c243c0014248faf000c8faf008c",
INIT_08 => X"00000000000003278f8f8f0300000c00142c008fac008f24af000c8f0010af24",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000102040912000000",
INIT_0F => X"fffffffffffffffffffffffffffffffffffffffffffffefcf9f2e4c992000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000606060606050000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000010101010101000000",
INIT_14 => X"3d3d3d3d3d3d676620740a0a747320650a000000000000000000000000000000",
INIT_15 => X"694c7363726d69546e616f6269546f6175206467730a00696920746c6c67730a",
INIT_16 => X"4e490a007420696c54004546455000454d500a6469540030617261736d657061",
INIT_17 => X"544c4c0a0a53200a4c2000454e490a0044414f4c41454e490a0044414f4c4145",
INIT_18 => X"0000000000000000000054204945540a54204d0a542043422f440a2054494920",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000102040912000000000000000000000000000000",
INIT_1F => X"fffffffffffffffffffffefcf9f2e4c992000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000606060606050000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000010101010101000000000000000000000000000000",
INIT_24 => X"7566542055000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000072756570695300736e61756369670a0a727475526e2068616e",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"6200c2c3c20000c4c2430300c30200c2c5c4a0bebfbd00e0bdbec0620200c202",
INIT_01 => X"c240026202c34000c24000c24300c24300c2c0c7c6c5c4a0bebd00e0bdbebfc0",
INIT_02 => X"006202c300404200c2c24200c2c24300c2404202424300c24300c20000c04300",
INIT_03 => X"0002006200c2c300000200404300c24300c200000200404300c24300c2000002",
INIT_04 => X"a0bebd00e0bdbec00200c2c4a0bebd00e0bdbec000000002004042004200c200",
INIT_05 => X"4202000044020000440205c202c5c4a0b0bebfbd0000e0bdbec002624202c3c4",
INIT_06 => X"0200400042020000400243630302020000040510000044024300c34202c20042",
INIT_07 => X"00c20200000405100000040000400500c200004402006202c3c20000c4c20042",
INIT_08 => X"000000000000e0bdb0bebfc000000000404200c24300c302c20000c40000c242",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"00000000000000000000000000000000010204091224489123468d1a34000000",
INIT_0F => X"fffffffffffffffffffffffffffffefcf9f2e4c99224489123468d1a34000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000003030303030300000000000000",
INIT_12 => X"02010000000000000000000000000000010101020515100b0500fb1a150f0a05",
INIT_13 => X"0000000000000000000000000000000000000000000001504f4e4d4c4b050403",
INIT_14 => X"0a3d3d3d3d3d0a747369540a656d707247000000000000000000000000000000",
INIT_15 => X"6e69736379656e65737470696e656e63622f6920740a006f762f69697420740a",
INIT_16 => X"554d0a0073746c206f00444144410053414c0a6f6e6500306e206c206220726c",
INIT_17 => X"4949540a0a45500a4546005347460a0021534e414c52554d0a0021494e414c52",
INIT_18 => X"0000000000000000000020544f52200a20544f0a2054545420450a00454f562f",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"00000000010204091224489123468d1a34000000000000000000000000000000",
INIT_1F => X"fffffefcf9f2e4c99224489123468d1a34000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000003030303030300000000000000000000000000000000000000",
INIT_22 => X"00000000010101020515100b0500fb1a150f0a05000000000000000000000000",
INIT_23 => X"0000000000000000000001504f4e4d4c4b050403020100000000000000000000",
INIT_24 => X"20203a5441000000000000000000000000000000000000000000000000000000",
INIT_25 => X"00000000000000206d74616e65007420746e6f6e690a006b2074542074696420",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"100000000000070000101f00001000000000f00000ff00000000e8101400001f",
INIT_01 => X"001814100f000000000000000000000000000000000000f000ff0000000000e8",
INIT_02 => X"0000000000ff0000000000000000100000180010001000000000000000000000",
INIT_03 => X"0000000000000000000000001000000000000000000000100000000000000000",
INIT_04 => X"f000ff00000000e817000000f000ff00000000e8100000000000000000000000",
INIT_05 => X"00200000320000007801e100000000f0000000ff0000000000e81010ff1f0000",
INIT_06 => X"7f00000000800000007f00ff0f7f00000700007f000032000000000020000000",
INIT_07 => X"000000000700007f000000000120003000000032000000000000000800000000",
INIT_08 => X"0000000000000000000000e810000100ff0000000000007f0000080000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0101010101010101010101010101010000000000000000000000000000000000",
INIT_0B => X"0202020201010101010101010101010101010101010101010101010101010101",
INIT_0C => X"0202020202020202020202020202020202020202020202020202020202020202",
INIT_0D => X"0303030303030303030303030303030303030303030303030303030303030202",
INIT_0E => X"0000000000000000010204091224489123468d1a3468d1a2458a152b56030303",
INIT_0F => X"fffffffffffffefcf9f2e4c99224489123468d1a3468d1a2458a152b56000000",
INIT_10 => X"0000000000000000000000000000000000080808080707000000000000ffffff",
INIT_11 => X"000000000000000000000000000000000101039e9b9794918e0f0c0906030000",
INIT_12 => X"46230000000000000000000095a8c0e00d50c1a1439e5b17d4914e4f0cc98643",
INIT_13 => X"1212121212000000000000000000202429303a48619123c7a4815d3a17b08d69",
INIT_14 => X"003d3d3d3d3d0069686e650073616c6165121212121212121212121212121212",
INIT_15 => X"67730a65206d67730a69657467730a7474206e616954006e69206f63696d6954",
INIT_16 => X"4d4550003a65656674002149215300542041006e6773003020746c73656e696c",
INIT_17 => X"4f43494d0044410044410054205453000a53205443204d4550000a4c20544320",
INIT_18 => X"0000000000000000000000454e414f420045524d00454f5253524100534e4920",
INIT_19 => X"00000000000000000000000000000000000000000000000000001212ed515302",
INIT_1A => X"0101010000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0101010101010101010101010101010101010101010101010101010101010101",
INIT_1C => X"0202020202020202020202020202020202020202020202020101010101010101",
INIT_1D => X"0303030303030303030303030303030303030202020202020202020202020202",
INIT_1E => X"1224489123468d1a3468d1a2458a152b56030303030303030303030303030303",
INIT_1F => X"9224489123468d1a3468d1a2458a152b56000000000000000000000001020409",
INIT_20 => X"0000000000080808080707000000000000fffffffffffffffffffefcf9f2e4c9",
INIT_21 => X"000000000101039e9b9794918e0f0c0906030000000000000000000000000000",
INIT_22 => X"95a8c0e00d50c1a1439e5b17d4914e4f0cc98643000000000000000000000000",
INIT_23 => X"0000202429303a48619123c7a4815d3a17b08d69462300000000000000000000",
INIT_24 => X"6379204552121212121212121212121212121212121212121200000000000000",
INIT_25 => X"0000000000000000622063676e000a7469696d676e4200737770205568732072",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"250014101400dc101025400020400024242025181ce000080804252500000c00",
INIT_01 => X"20250224ff1000001c000018000014ff0010041c181410250cf0000820181c25",
INIT_02 => X"0004010400ea080000000100000421000425ff2b010700000000140013000000",
INIT_03 => X"0c04000400181c00140300042a002400001c001f0200042a0024000018002a01",
INIT_04 => X"2504f80008080425420008082504f80008100c25250002050004020000002000",
INIT_05 => X"500000ae6c000080407d0010013c38252c3034c80000080804254224feff0808",
INIT_06 => X"fc002e000000003300fc00fffffc0000f90303fc00aea8000000143000140000",
INIT_07 => X"00100000f90303fc00980a0005250a251000aecc00001a011c1c009118180000",
INIT_08 => X"0b070503000008382c30342525006000ca650010000020fc20009d1800091001",
INIT_09 => X"9d97958b89837f716d6b67656159534f4947433d3b352f2b29251f1d1713110d",
INIT_0A => X"5b514b3d393733251b19150f0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a3",
INIT_0B => X"231d0b09fdf7f3ebe7dfd3cfcdc9c1bbb7b1afa5a399918d857f7b756f67615d",
INIT_0C => X"efe7e3ddd7cfc5bdb3aba5a195938d878381776b69655f5957514b413b39332d",
INIT_0D => X"d1cbc7b9b3ada9a1978f8b7773716d5f5b5955473d3b37352b291d130501f9f5",
INIT_0E => X"010204091224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78e5dfd7",
INIT_0F => X"f9f2e4c99224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78000000",
INIT_10 => X"070001020301010000000101010102030718110a03fcf5231c150e0700fffefc",
INIT_11 => X"0000010303010100010059647285a0c80b90212807e6c5a483a5846342210007",
INIT_12 => X"8a4500030103030001000100ae6472856dc80b90212807e6c5a483a584634221",
INIT_13 => X"38373635340005010300010001005d689c8b41d117a245c8833ef9b46f5914cf",
INIT_14 => X"003d3d3d3d3d006e696773007420616c6e2b2c2d2e2f30313233343d3c3b3a39",
INIT_15 => X"20740073616f2074006f722020740069727367646e65000a73646e6170756e65",
INIT_16 => X"422052002073646161000a4c00530020545300652074000a3168656d72756d20",
INIT_17 => X"4e4150550021530021490020544948000a4550495543422052000a4546495543",
INIT_18 => X"0908070605040302010000535354504900535945005352415520440054205344",
INIT_19 => X"6159534f4947433d3b352f2b29251f1d1713110d0b07050300002246cb153520",
INIT_1A => X"0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a39d97958b89837f716d6b6765",
INIT_1B => X"cdc9c1bbb7b1afa5a399918d857f7b756f67615d5b514b3d393733251b19150f",
INIT_1C => X"95938d878381776b69655f5957514b413b39332d231d0b09fdf7f3ebe7dfd3cf",
INIT_1D => X"73716d5f5b5955473d3b37352b291d130501f9f5efe7e3ddd7cfc5bdb3aba5a1",
INIT_1E => X"3468d1a2458a152b56ac59b367cf9e3c78e5dfd7d1cbc7b9b3ada9a1978f8b77",
INIT_1F => X"3468d1a2458a152b56ac59b367cf9e3c78000000010204091224489123468d1a",
INIT_20 => X"010102030718110a03fcf5231c150e0700fffefcf9f2e4c99224489123468d1a",
INIT_21 => X"7285a0c80b90212807e6c5a483a5846342210007070001020301010000000101",
INIT_22 => X"ae6472856dc80b90212807e6c5a483a584634221000001030301010001005964",
INIT_23 => X"01005d689c8b41d117a245c8833ef9b46f5914cf8a4500030103030001000100",
INIT_24 => X"616f4953542b2c2d2e2f30313233343d3c3b3a39383736353400050103000100",
INIT_25 => X"0000000100000000656e6b2064000a656f636d206e6500216f756f41652c7465",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
| gpl-3.0 | ab8c87f1df2a3ca4ff765ca494a9db8f | 0.843311 | 5.637524 | false | false | false | false |
Wynjones1/gbvhdl | testing/memory_tb.vhd | 1 | 2,971 | library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.types.all;
use work.interfaces.all;
entity memory_tb is
end;
architecture rtl of memory_tb is
component memory is
port( clk : in std_logic;
reset : in std_logic;
input : in memory_in_if;
output : out memory_out_if);
end component;
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal input : memory_in_if;
signal output : memory_out_if;
signal read_data_cmp : byte_t;
signal lineno : integer := 0;
begin
reset_gen : process
begin
reset <= '1';
wait for 40 ns;
reset <= '0';
wait;
end process;
clk_gen : process
begin
if clk = '1' then
clk <= '0';
wait for 10 ns;
else
clk <= '1';
wait for 10 ns;
end if;
end process;
run_test : process(clk, reset)
type state_t is (s0, s1, s2, s3);
variable state : state_t := s0;
file fp : text open read_mode is "/home/stuart/VHDL/gbvhdl/testing/tests/memory.txt";
variable address_s : string(16 downto 1);
variable we_s : string( 1 downto 1);
variable wdata_s : string( 8 downto 1);
variable rdata_s : string( 8 downto 1);
variable dummy : string( 1 downto 1);
variable l : line;
begin
if reset = '1' then
input.address <= (others => '0');
elsif rising_edge(clk) then
case state is
when s0 =>
if endfile(fp) then
state := s3;
else
readline(fp, l);
read(l, address_s);
read(l, dummy);
read(l, we_s);
read(l, dummy);
read(l, wdata_s);
read(l, dummy);
read(l, rdata_s);
if we_s(1) = '1' then
input.we <= '1';
else
input.we <= '0';
end if;
input.address <= to_std_logic_vector(address_s);
input.data <= to_std_logic_vector(wdata_s);
read_data_cmp <= to_std_logic_vector(rdata_s);
state := s1;
end if;
when s1 =>
state := s0;
assert read_data_cmp = output.data;
lineno <= lineno + 1;
when s2 =>
state := s0;
when s3 =>
report "End of simulation" severity failure;
end case;
end if;
end process;
memory_0 : memory
port map (clk, reset, input, output);
end rtl;
| mit | 846efc7fc4373c53ee0b8d272f1dbab4 | 0.452373 | 3.971925 | false | false | false | false |
camacazio/de0_nano_DAC | DE0_12bitDAC_controller/adc_pll.vhd | 1 | 14,721 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: adc_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY adc_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END adc_pll;
ARCHITECTURE SYN OF adc_pll IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire2_bv(0 DOWNTO 0) <= "0";
sub_wire2 <= To_stdlogicvector(sub_wire2_bv);
sub_wire0 <= inclk0;
sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0;
sub_wire4 <= sub_wire3(0);
c0 <= sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 125,
clk0_duty_cycle => 50,
clk0_multiply_by => 8,
clk0_phase_shift => "0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=adc_pll",
lpm_type => "altpll",
operation_mode => "NO_COMPENSATION",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire1,
clk => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "3.200000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "3.20000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "adc_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "125"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-3.0 | f2e822e2057315a8d51fbcfb348ff0c5 | 0.700156 | 3.370192 | false | false | false | false |
SKravitsky/ECEC412 | DataMemoryMulticycle.vhd | 1 | 1,415 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DataMemoryMulticycle is
port(
WriteData: in std_logic_vector(31 downto 0);
Address: in std_logic_vector(31 downto 0);
MemRead, MemWrite: in std_logic;
ReadData: out std_logic_vector(31 downto 0)
);
end DataMemoryMulticycle;
Architecture Structural of DataMemoryMulticycle is
type mem_array is array(0 to 55) of std_logic_vector(31 downto 0);
signal data_mem: mem_array := (
-- Instruction Memory
0 => X"8d100028", -- lw $s0, 40($t0)
1 => X"8d11002c", -- lw $s1, 44($t0)
2 => X"12110002", -- beq $s0, $s1, L
3 => X"02959820", -- add $s3, $s4, $s5
4 => X"08000006", -- j exit
5 => X"02959822", -- L: sub $s3, $s4, $s5
6 => X"ad130030", -- exit: sw $s3, 48($t0)
-- Data Memory
10 => X"00000004",
11 => X"00000004", -- Branch Taken
-- 11 => X"FFFFFFFB", -- Branch Untaken
others => x"00000000"
);
signal temp_data: std_logic_vector(31 downto 0) := X"00000000";
begin
ReadData <= temp_data;
process(WriteData, Address, MemRead, MemWrite)
begin
if MemWrite = '1' then
data_mem(to_integer(unsigned(Address)) / 4) <= WriteData;
end if;
if MemRead = '1' then
temp_data <= data_mem(to_integer(unsigned(Address)) / 4);
end if;
end process;
end Structural;
| apache-2.0 | 88aac332f4a02c9f9f476f4559766321 | 0.587279 | 3.144444 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Processor_NI/uart.vhd | 3 | 9,274 | ---------------------------------------------------------------------
-- TITLE: Simulatable UART. Does not synthesize. Writes UART output to a file.
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the UART.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * added a memory mapped register for counter value
-- * added necessary signals for the above mentioned register to the interface!
-- * COUNT_VALUE is replaced with count_value_sig which comes from the above mentioned register
-- NOTICE: Please add the newline character ('\n') to the end of every
-- line you send over the UART, otherwise it won't save it.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.mlite_pack.all;
entity uart is
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic;
reg_enable : in std_logic;
reg_write_byte_enable : in std_logic_vector(3 downto 0);
reg_address : in std_logic_vector(31 downto 2);
reg_data_write : in std_logic_vector(31 downto 0);
reg_data_read : out std_logic_vector(31 downto 0)
);
end; --entity uart
architecture logic of uart is
signal delay_write_reg : std_logic_vector(9 downto 0);
signal bits_write_reg : std_logic_vector(3 downto 0);
signal data_write_reg : std_logic_vector(8 downto 0);
signal delay_read_reg : std_logic_vector(9 downto 0);
signal bits_read_reg : std_logic_vector(3 downto 0);
signal data_read_reg : std_logic_vector(7 downto 0);
signal data_save_reg : std_logic_vector(17 downto 0);
signal busy_write_sig : std_logic;
signal count_value_reg_in, count_value_reg: std_logic_vector(31 downto 0);
signal old_address : std_logic_vector(31 downto 2);
signal count_value_sig : std_logic_vector(9 downto 0);
begin
-- added by siavoosh payandeh azad
update_count_value: process(count_value_reg, reg_data_write, reg_write_byte_enable, reg_address, reg_enable)begin
count_value_reg_in <= count_value_reg ;
if reg_enable = '1' and reg_address = uart_count_value_address then
if reg_write_byte_enable(0) = '1' then
count_value_reg_in(7 downto 0) <= reg_data_write(7 downto 0);
end if;
if reg_write_byte_enable(1) = '1' then
count_value_reg_in(15 downto 8) <= reg_data_write(15 downto 8);
end if;
if reg_write_byte_enable(2) = '1' then
count_value_reg_in(23 downto 16) <= reg_data_write(23 downto 16);
end if;
if reg_write_byte_enable(3) = '1' then
count_value_reg_in(31 downto 24) <= reg_data_write(31 downto 24);
end if;
end if;
end process;
process(count_value_reg, old_address) begin
if old_address = uart_count_value_address then
reg_data_read <= count_value_reg;
else
reg_data_read <= (others => 'U');
end if;
end process;
process(clk, reset, count_value_reg_in, reg_address)begin
if reset = '1' then
old_address <= (others => '0');
count_value_reg <= (others => '0');
elsif rising_edge(clk) then
old_address <= reg_address;
count_value_reg <= count_value_reg_in;
end if;
end process;
count_value_sig <= count_value_reg(9 downto 0);
-- end of updates by Siavoosh Payandeh Azad
uart_proc: process(clk, reset, enable_read, enable_write, data_in,
data_write_reg, bits_write_reg, delay_write_reg,
data_read_reg, bits_read_reg, delay_read_reg,
data_save_reg,
busy_write_sig, uart_read)
-----------------------------------------------
--- MUST BE EDITED BASED ON THE FREQUENCY! ----
-----------------------------------------------
-- constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
-- "0100011110"; --33MHz/2/57600Hz = 0x11e
-- "1101100100"; --50MHz/57600Hz = 0x364
-- "0110110010"; --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2
-- "0011011001"; --12.5MHz/57600Hz = 0xd9
-- "0000000100"; --for debug (shorten read_value_reg)
begin
if reset = '1' then
data_write_reg <= ZERO(8 downto 1) & '1';
bits_write_reg <= "0000";
delay_write_reg <= ZERO(9 downto 0);
data_read_reg <= ZERO(7 downto 0);
bits_read_reg <= "0000";
delay_read_reg <= ZERO(9 downto 0);
data_save_reg <= ZERO(17 downto 0);
elsif rising_edge(clk) then
--Write UART
if bits_write_reg = "0000" then --nothing left to write?
if enable_write = '1' then
delay_write_reg <= ZERO(9 downto 0); --delay before next bit
bits_write_reg <= "1010"; --number of bits to write
data_write_reg <= data_in & '0'; --remember data & start bit
end if;
else
--if delay_write_reg /= COUNT_VALUE then
if delay_write_reg /= count_value_sig then
delay_write_reg <= delay_write_reg + 1; --delay before next bit
else
delay_write_reg <= ZERO(9 downto 0); --reset delay
bits_write_reg <= bits_write_reg - 1; --bits left to write
data_write_reg <= '1' & data_write_reg(8 downto 1);
end if;
end if;
--Read UART
if delay_read_reg = ZERO(9 downto 0) then --done delay for read?
if bits_read_reg = "0000" then --nothing left to read?
if uart_read = '0' then --wait for start bit
--delay_read_reg <= '0' & COUNT_VALUE(9 downto 1); --half period
delay_read_reg <= '0' & count_value_sig(9 downto 1); --half period
bits_read_reg <= "1001"; --bits left to read
end if;
else
--delay_read_reg <= COUNT_VALUE; --initialize delay
delay_read_reg <= count_value_sig; --initialize delay
bits_read_reg <= bits_read_reg - 1; --bits left to read
data_read_reg <= uart_read & data_read_reg(7 downto 1);
end if;
else
delay_read_reg <= delay_read_reg - 1; --delay
end if;
--Control character buffer
--if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
if bits_read_reg = "0000" and delay_read_reg = count_value_sig then
if data_save_reg(8) = '0' or
(enable_read = '1' and data_save_reg(17) = '0') then
--Empty buffer
data_save_reg(8 downto 0) <= '1' & data_read_reg;
else
--Second character in buffer
data_save_reg(17 downto 9) <= '1' & data_read_reg;
if enable_read = '1' then
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if;
elsif enable_read = '1' then
data_save_reg(17) <= '0'; --data_available
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if; --rising_edge(clk)
uart_write <= data_write_reg(0);
if bits_write_reg /= "0000"
-- Comment out the following line for full UART simulation (much slower)
--and log_file = "UNUSED"
then
busy_write_sig <= '1';
else
busy_write_sig <= '0';
end if;
busy_write <= busy_write_sig;
data_avail <= data_save_reg(8);
data_out <= data_save_reg(7 downto 0);
end process; --uart_proc
-- synthesis_off
uart_logger:
if log_file /= "UNUSED" generate
uart_proc: process(clk, enable_write, data_in)
file store_file : text open write_mode is log_file;
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if rising_edge(clk) and busy_write_sig = '0' then
if enable_write = '1' then
index := conv_integer(data_in(6 downto 0));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
--The following line may have to be commented out for synthesis
writeline(store_file, hex_file_line);
line_length := 0;
end if;
end if; --uart_sel
end if; --rising_edge(clk)
end process; --uart_proc
end generate; --uart_logger
-- synthesis_on
end; --architecture logic
| gpl-3.0 | ad94e4fe60f8fe52ce1f820e92c5fa32 | 0.567069 | 3.551896 | false | false | false | false |
camacazio/de0_nano_DAC | DE0_12bitDAC_controller/output_to_DAC.vhd | 1 | 8,277 | ----------------------------------------------------------------------------------
-- 12 bit output to DAC system.
-- Pulls data out from memory and assumes it comes in with the following flow:
-- 1)Waveform duration
-- 2)Starting Voltage
-- 3)Slope
-- If duration comes in as x"FFFF", read_addr is reset to 0 (it is up to the user to design software to insert this)
-- If duration comes in as x"FFFE", the 'running' state is paused to await for a new trigger ( " )
-- If duration comes in as x"FFFD", then 'running' state continues but loops back to the start of memory.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Physical ports
entity output_to_12bitDAC is
port
(
-- clks for incoming data and outputting to DAC
clk_dac : in std_logic;
-- reset trigger for DAC process
iRST : in std_logic;
-- Data buses
data_in : in std_logic_vector(15 downto 0); -- 16 bit data input for waveform data
dac_out : out std_logic_vector(11 downto 0) := (others => '0'); -- 12 bit DAC output
-- Memory address location for DAC data from memory
read_addr_out : out std_logic_vector(13 downto 0);
-- Logic to output new dac value
wr_n : out std_logic; -- Data is transparent to DAC when '0', initialize so dac is suspended
cs_n : out std_logic; -- chip select DAC line, DAC active when '0'
-- Input to begin running waveforms from computer trigger
run_cmd : in std_logic;
-- External logic input to begin running waveforms
run_trigger : in std_logic
);
end entity;
-- Behavioral
architecture rtl of output_to_12bitDAC is
----------------------------------------------------------------------------------
-- SIGNALS
----------------------------------------------------------------------------------
-- Internal write enable and chip select
signal wr_i : std_logic := '0';
signal cs_i : std_logic := '0';
-- Internal copy of the address for reading from memory
signal read_addr : std_logic_vector((read_addr_out'length - 1) downto 0) := (others => '0');
-- Amount of clock cycles to read in new waveform data while running a waveform
constant READ_TIME : std_logic_vector(15 downto 0) := x"0004";
----------------------------------------------------------------------------------
-- BEGIN
----------------------------------------------------------------------------------
begin
-- Latch DAC on/off signals
wr_n <= not(wr_i);
cs_n <= not(cs_i);
-- Latch internal read address to output
read_addr_out <= read_addr;
-- interpret data for DAC
process (clk_dac, run_cmd, run_trigger, iRST)
-- States for the DAC
type DAC_STATES is (RESET, IDLE, RUNNING);
variable dac_state : DAC_STATES := RESET;
-- States when pulling data out of memory
type DAC_READ_MODES is (READ_T, READ_V, READ_dV_float, READ_dV, DONE, NONE);
variable dac_read_mode : DAC_READ_MODES := READ_T;
-- Data communication for the waveform
variable data_comm : std_logic_vector(15 downto 0);
-- The following are internal values for outputting to the DAC waveform
-- Voltage values go 15 downto 4, we have 3 downto 0 to hold decimal points in lower bits
variable dac_out_i : std_logic_vector(31 downto 0);
variable dac_dV_i : std_logic_vector(31 downto 0);
variable time_dac_i : std_logic_vector(15 downto 0);
-- "Reading" versions for reading memory while the DAC still runs the previous waveform cycle
variable dac_out_read : std_logic_vector(31 downto 0);
variable dac_dV_read : std_logic_vector(31 downto 0);
variable time_dac_read : std_logic_vector(15 downto 0);
-- Whether or not we need to be counting
variable timing : std_logic;
begin
-- check reset flag
if iRST = '0' then
dac_state := RESET;
else
-- DAC operations
if rising_edge(clk_dac) then
case dac_state is
when RESET => -- Return to boot conditions
dac_out <= (others => '0');
read_addr <= (others => '0');
wr_i <= '1';
cs_i <= '1';
dac_state := IDLE;
when IDLE => -- Awaiting a run command
-- Prepare to begin reading data at start of 'running'
dac_read_mode := READ_T;
-- empty out linear coefficient while IDLE
dac_dV_i := (others => '0');
-- No counting down when beginning to read a waveform
timing := '0';
-- Deactivate DAC write but activate chip
wr_i <= '0';
cs_i <= '1';
-- Check if the next value on the memory register signifies the end of memory,
-- should be in the position to which READ_T would point in memory
if data_in = x"FFFF" then
read_addr <= (others => '0');
end if;
-- Check conditions to run the waveform
if (run_cmd = '1' OR run_trigger = '1') then
dac_state := RUNNING;
end if;
when RUNNING => -- RUNNING is interpreting data at the current address
-- the M9K RAM updates much faster than this process, so no worries on timing with read_addr
-- Activate DAC output
wr_i <= '1';
-- Latch external waveform data
data_comm := data_in;
case dac_read_mode is
when READ_T =>
-- Read in the time to run the waveform
-- Handling the case that time_dac_read - read_time < 0 to make sure we have time to load the next waveform
if data_comm < READ_TIME then
time_dac_read := READ_TIME;
else
time_dac_read := data_comm;
end if;
read_addr <= read_addr + '1';
-- Read in the starting voltage
dac_read_mode := READ_V;
when READ_V =>
-- Read the voltage
dac_out_read := data_comm & x"0000";
read_addr <= read_addr + '1';
-- Read in the slope
dac_read_mode := READ_dV_float;
when READ_dV_float =>
-- Read fractional linear part
dac_dV_read(15 downto 0) := data_comm;
read_addr <= read_addr + '1';
-- Read the integer part
dac_read_mode := READ_dV;
when READ_dV =>
-- Read linear part
dac_dV_read(31 downto 16) := data_comm;
read_addr <= read_addr + '1';
-- Finished reading in this portion of waveform
dac_read_mode := DONE;
when DONE =>
-- Latch all the read data into values used for writing to DACs, timing including this cycle
dac_out_i := dac_out_read;
dac_dV_i := dac_dV_read;
-- If the next data requires waiting for a new trigger, need to allow the waveform to finish and then break to IDLE
if data_comm >= x"FFFE" then
time_dac_i := time_dac_read - 1 + READ_TIME;
else
time_dac_i := time_dac_read - 1;
end if;
-- If we are in "continous run" mode, loop back to the start of memory but keep running
if data_comm = x"FFFD" then
read_addr <= (others => '0');
end if;
-- We are going to be timing operation time
timing := '1';
-- Prepared to run the waveform
dac_read_mode := NONE;
when NONE =>
-- Not currently reading anything
-- Case statement at NONE should end with the read address for the next waveform's time
dac_read_mode := NONE;
end case;
-- Generating waveform values
-- Alter dac_val_i from coefficients for next output
dac_out_i := dac_out_i + dac_dV_i;
-- Output the voltage
dac_out <= dac_out_i(31 downto (32 - dac_out'length));
if timing = '1' then
if time_dac_i <= READ_TIME then
--Start getting ready for the next round of data
timing := '0';
-- Read in the next waveform
dac_read_mode := READ_T;
-- Check if the time value flags the need to leave RUNNING
if data_comm >= x"FFFE" then
-- Await next run trigger
dac_state := IDLE;
-- Prepare for next waveform
read_addr <= read_addr + '1';
end if;
else -- Still waiting, so loop
time_dac_i := time_dac_i - 1;
dac_read_mode := NONE;
end if;
end if;
end case;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 80c9c4abcd9da723b24ee487153d7bf0 | 0.577625 | 3.46608 | false | false | false | false |
AndyMcC0/UVVM_All | bitvis_vip_axistream/src/vvc_cmd_pkg.vhd | 1 | 9,153 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.axistream_bfm_pkg.all;
--========================================================================================================================
--========================================================================================================================
package vvc_cmd_pkg is
--===============================================================================================
-- t_operation
-- - Bitvis defined BFM operations
--===============================================================================================
type t_operation is (
-- UVVM common
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
TRANSMIT,
RECEIVE,
EXPECT
);
-- Constants for the maximum sizes to use in this VVC.
-- You can create VVCs with smaller sizes than these constants, but not larger.
-- Create constants for the maximum sizes to use in this VVC.
constant C_VVC_CMD_DATA_MAX_BYTES : natural := 16*1024;
constant C_VVC_CMD_DATA_MAX_WORDS : natural := C_VVC_CMD_DATA_MAX_BYTES;
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--===============================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--===============================================================================================
type t_vvc_cmd_record is record
-- VVC dedicated fields
data_array : t_byte_array(0 to C_VVC_CMD_DATA_MAX_BYTES-1);
data_array_length : integer range -10 to C_VVC_CMD_DATA_MAX_BYTES; -- Some negative numbers have special meaning in axistreamStartTransmits()
-- If you need support for more bits per data byte, replace this with a wider type:
user_array : t_user_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1);
user_array_length : natural range 1 to C_VVC_CMD_DATA_MAX_WORDS; -- One user_array entry per word (clock cycle)
strb_array : t_strb_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1);
strb_array_length : natural range 1 to C_VVC_CMD_DATA_MAX_WORDS; -- One strb_array entry per word (clock cycle)
id_array : t_id_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1);
id_array_length : natural range 1 to C_VVC_CMD_DATA_MAX_WORDS; -- One id_array entry per word (clock cycle)
dest_array : t_dest_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1);
dest_array_length : natural range 1 to C_VVC_CMD_DATA_MAX_WORDS; -- One dest_array entry per word (clock cycle)
-- Common VVC fields
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued;
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
data_array => (others => (others => '0')),
data_array_length => 1,
user_array => (others => (others => '0')),
user_array_length => 1,
strb_array => (others => (others => '0')),
strb_array_length => 1,
id_array => (others => (others => '0')),
id_array_length => 1,
dest_array => (others => (others => '0')),
dest_array_length => 1,
-- Common VVC fields
operation => NO_OPERATION,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_COMMAND_TYPE,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
alert_level => FAILURE,
delay => 0 ns,
quietness => NON_QUIET
);
--===============================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--===============================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--===============================================================================================
type t_vvc_result is record
data_array : t_byte_array(0 to C_VVC_CMD_DATA_MAX_BYTES-1);
data_length : natural;
user_array : t_user_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1);
strb_array : t_strb_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1);
id_array : t_id_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1);
dest_array : t_dest_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1);
end record;
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1));
--===============================================================================================
-- Procedures
--===============================================================================================
function to_string(
result : t_vvc_result
) return string;
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
-- Custom to_string overload needed when result is of a type that haven't got one already
function to_string(
result : t_vvc_result
) return string is
begin
return to_string(result.data_length) & " Bytes";
end;
end package body vvc_cmd_pkg;
| mit | b4398a3a200c5497704ef9030a783215 | 0.482246 | 4.5765 | false | false | false | false |
kiwih/subleq-vhdl | genericregister.vhd | 1 | 684 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity genericregister is
generic (
NUMBITS: integer := 16
);
port(
CLK: in std_logic;
EN: in std_logic;
RESET: in std_logic;
DATA_IN: in std_logic_vector(NUMBITS-1 downto 0);
DATA_OUT: out std_logic_vector(NUMBITS-1 downto 0)
);
end genericregister;
architecture beh of genericregister is
signal reg: std_logic_vector(NUMBITS-1 downto 0) := (others => '0');
begin
reg_proc: process(clk, reset)
begin
if(RESET = '1') then
reg <= (others => '0');
elsif rising_edge(CLK) then
if EN = '1' then
reg <= DATA_IN;
end if;
end if;
end process reg_proc;
DATA_OUT <= reg;
end beh; | mit | 306ed194b1ced963cd0c6bcaff8a8201 | 0.671053 | 2.746988 | false | false | false | false |
simoesusp/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE70/lpm_ram_dq0.vhd | 3 | 6,957 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_ram_dq0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 10.1 Build 153 11/29/2010 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_ram_dq0 IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_ram_dq0;
ARCHITECTURE SYN OF lpm_ram_dq0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(3 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "video_mem1.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 65536,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
widthad_a => 16,
width_a => 4,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "video_mem1.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "65536"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "video_mem1.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL "data[3..0]"
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | eab429e56d50aab70fde2d995e67f4ec | 0.67141 | 3.469825 | false | false | false | false |
AndyMcC0/UVVM_All | bitvis_irqc/src/irqc_core.vhd | 3 | 3,515 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_core
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.irqc_pif_pkg.all;
entity irqc_core is
port(
-- DSP interface and general control signals
clk : in std_logic;
arst : in std_logic;
-- PIF-core interface
p2c : in t_p2c;
c2p : out t_c2p;
-- Interrupt related signals
irq_source : in std_logic_vector(C_NUM_SOURCES-1 downto 0);
irq2cpu : out std_logic;
irq2cpu_ack : in std_logic
);
end irqc_core;
architecture rtl of irqc_core is
signal c2p_i : t_c2p; -- Internal version of output
signal igr : std_logic;
function or_reduce(
constant value : std_logic_vector
) return std_logic is
variable v_tmp : std_logic := '0';
begin
for i in value'range loop
v_tmp := v_tmp or value(i);
end loop;
return v_tmp;
end;
begin
p_irr : process(clk, arst)
begin
if arst = '1' then
c2p_i.aro_irr <= (others => '0');
elsif rising_edge(clk) then
for i in 0 to C_NUM_SOURCES-1 loop
if p2c.awt_itr(i) = '1' then
c2p_i.aro_irr(i) <= '1';
elsif p2c.awt_icr(i) = '1' then
c2p_i.aro_irr(i) <= '0';
elsif irq_source(i) = '1' then
c2p_i.aro_irr(i) <= '1';
else
null; -- Keep value if none above
end if;
end loop;
end if;
end process;
c2p_i.aro_ipr <= c2p_i.aro_irr and p2c.rw_ier;
igr <= or_reduce(c2p_i.aro_ipr);
p_irq2cpu : process(clk, arst)
begin
if arst = '1' then
c2p_i.aro_irq2cpu_allowed <= '0';
elsif rising_edge(clk) then
if p2c.awt_irq2cpu_ena = '1' then
c2p_i.aro_irq2cpu_allowed <= '1';
-- NOTE: No way to disallow irq2cpu without the following two lines (However not included in the specification)
elsif p2c.awt_irq2cpu_disable = '1' then
c2p_i.aro_irq2cpu_allowed <= '0';
elsif irq2cpu_ack = '1' then
c2p_i.aro_irq2cpu_allowed <= '0';
else
null; -- Keep value if none above
end if;
end if;
end process;
irq2cpu <= '1' when (igr = '1' and c2p_i.aro_irq2cpu_allowed = '1') else '0';
c2p <= c2p_i;
end rtl;
| mit | 7e1586e6e8bb94fdf933a9a60f0d614f | 0.530299 | 3.623711 | false | false | false | false |
elainemielas/CVUT_BI-PNO | project2/Allinall.vhd | 1 | 2,025 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ALLINALL is
port (
PS2_DATA : in std_logic; -- serial PS2 input
PS2_CLK : in std_logic; -- serial PS2 clock
CLK : in std_logic; -- standard 50MHz clock
RESET : in std_logic;
JCHYBA : out std_logic; -- detekovano s 1 chybou
SHODA : out std_logic -- detekovana uplna shoda
);
end ALLINALL;
architecture ALLINALL_BODY of ALLINALL is
signal KEY_F, KEY_U, KEY_L, KEY_PRESS : std_logic;
component KEYBOARD is
port (
PS2_DATA : in std_logic; -- serial PS2 input
PS2_CLK : in std_logic; -- serial PS2 clock
KEY_F : out std_logic; -- high for one clock when key 'f' pressed
KEY_U : out std_logic; -- high for one clock when key 'u' pressed
KEY_L : out std_logic; -- high for one clock when key 'l' pressed
KEY_PRESS : out std_logic; -- high for one clock when any key pressed
CLK : in std_logic; -- standard 50MHz clock
RESET : in std_logic
);
end component;
component AUTOMAT is
port (
KEY_F : in std_logic; -- high for one clock when key 'f' pressed
KEY_U : in std_logic; -- high for one clock when key 'u' pressed
KEY_L : in std_logic; -- high for one clock when key 'l' pressed
KEY_PRESS : in std_logic; -- high for one clock when any key pressed
CLK : in std_logic; -- standard 50MHz clock
RESET : in std_logic;
JCHYBA : out std_logic; -- detekovano s 1 chybou
SHODA : out std_logic -- detekovana uplna shoda
);
end component;
begin
AUT : AUTOMAT port map (CLK => CLK, RESET => RESET, KEY_F => KEY_F, KEY_U => KEY_U, KEY_L => KEY_L,
KEY_PRESS => KEY_PRESS, JCHYBA => JCHYBA, SHODA => SHODA);
KB : KEYBOARD port map (CLK => CLK, RESET => RESET, KEY_F => KEY_F, KEY_U => KEY_U, KEY_L => KEY_L,
KEY_PRESS => KEY_PRESS, PS2_DATA => PS2_DATA, PS2_CLK => PS2_CLK);
end architecture;
| mit | 06d3f66747b20f655f8fcd455a811524 | 0.586173 | 3.049699 | false | false | false | false |
Wynjones1/gbvhdl | testing/registers_tb.vhd | 1 | 3,480 | library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.types.all;
entity registers_tb is
end;
architecture rtl of registers_tb is
component registers is
port( clk : in std_logic;
reset : in std_logic;
we : in std_logic;
write_sel : in register_t;
read_sel : in register_t;
write_data : in word_t;
read_data : out word_t);
end component;
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal we : std_logic := '0';
signal write_data : word_t := (others => '0');
signal read_data : word_t := (others => '0');
signal read_data_cmp : word_t := (others => '0');
signal write_sel : register_t := (others => '0');
signal read_sel : register_t := (others => '0');
signal lineno : integer := 0;
begin
reset_gen : process
begin
reset <= '1';
wait for 40 ns;
reset <= '0';
wait for 40 ns;
reset <= '0';
wait;
end process;
clk_gen : process
begin
if clk = '1' then
clk <= '0';
wait for 10 ns;
else
clk <= '1';
wait for 10 ns;
end if;
end process;
run_test : process(clk, reset)
type state_t is (s0, s1, s2, s3);
variable state : state_t := s0;
file input : text open read_mode is "/home/stuart/VHDL/gbvhdl/testing/tests/registers.txt";
variable reg_s : string( 4 downto 1);
variable data_s : string(16 downto 1);
variable we_s : string( 1 downto 1);
variable dummy : string( 1 downto 1);
variable l : line;
begin
if reset = '1' then
we <= '0';
write_sel <= register_a;
read_sel <= register_a;
elsif rising_edge(clk) then
case state is
when s0 =>
if endfile(input) then
state := s3;
else
readline(input, l);
read(l, reg_s);
write_sel <= to_std_logic_vector(reg_s);
read(l, dummy);
read(l, reg_s);
read_sel <= to_std_logic_vector(reg_s);
read(l, dummy);
read(l, we_s);
if we_s(1) = '1' then
we <= '1';
else
we <= '0';
end if;
read(l, dummy);
read(l, data_s);
write_data <= to_std_logic_vector(data_s);
read(l, dummy);
read(l, data_s);
read_data_cmp <= to_std_logic_vector(data_s);
state := s1;
end if;
when s1 =>
state := s0;
assert read_data_cmp = read_data;
lineno <= lineno + 1;
when s2 =>
state := s0;
when s3 =>
report "End of simulation" severity failure;
end case;
end if;
end process;
registers_0 : registers
port map (clk, reset, we, write_sel, read_sel, write_data, read_data);
end rtl;
| mit | abd119902dcdd93b7931927ea73bf5f1 | 0.439368 | 3.866667 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/archived/checkers_counter_threshold.vhd | 3 | 3,871 | --Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity checkers_counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
data_input: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end checkers_counter_threshold_classifier;
architecture behavior of checkers_counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Healthy_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(data_input, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif data_input = '1' then -- Checker has fired! There is a fault.
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(data_input, reset_counters, healthy_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif data_input = '0' then -- Checker has not fired! There is no fault, or fault is masked.
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when others =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END;
| gpl-3.0 | beab7b8d1c43e58f1e2d6e15ad1472dd | 0.621803 | 3.662252 | false | false | false | false |
AndyMcC0/UVVM_All | uvvm_vvc_framework/src_target_dependent/td_vvc_framework_common_methods_pkg.vhd | 1 | 37,518 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
-- Note: This package will be compiled into every single VVC library.
-- As the type t_vvc_target_record is already compiled into every single VVC library,
-- the type definition will be unique for every library, and thus result in a unique
-- procedure signature for every VVC. Hence the shared variable shared_vvc_cmd will
-- refer to only the shared variable defined in the given library.
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.vvc_cmd_pkg.all; -- shared_vvc_response, t_vvc_result
use work.td_target_support_pkg.all;
package td_vvc_framework_common_methods_pkg is
--======================================================================
-- Common Methods
--======================================================================
-------------------------------------------
-- await_completion
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Awaits completion of all commands in the queue for the specified VVC, or
-- until timeout.
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant timeout : in time;
constant msg : in string := ""
);
-------------------------------------------
-- await_completion
-------------------------------------------
-- See description above
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant timeout : in time;
constant msg : in string := ""
);
-------------------------------------------
-- await_completion
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Awaits completion of the specified command 'wanted_idx' in the queue for the specified VVC, or
-- until timeout.
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in natural;
constant timeout : in time;
constant msg : in string := ""
);
-------------------------------------------
-- await_completion
-------------------------------------------
-- See description above
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in natural;
constant timeout : in time;
constant msg : in string := ""
);
-------------------------------------------
-- await_any_completion
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Waits for the first of multiple VVCs to finish :
-- - Awaits completion of all commands in the queue for the specified VVC, or
-- - until global_awaiting_completion /= '1' (any of the other involved VVCs completed).
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0
);
-- Overload without vvc_channel
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0
);
-- Overload with wanted_idx
-- - Awaits completion of the specified command 'wanted_idx' in the queue for the specified VVC, or
-- - until global_awaiting_completion /= '1' (any of the other involved VVCs completed).
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in natural;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0
);
-- Overload without vvc_channel
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in natural;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0
);
-------------------------------------------
-- disable_log_msg
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Disables the specified msg_id for the VVC
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
);
-------------------------------------------
-- disable_log_msg
-------------------------------------------
-- See description above
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
);
-------------------------------------------
-- enable_log_msg
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Enables the specified msg_id for the VVC
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
);
-------------------------------------------
-- enable_log_msg
-------------------------------------------
-- See description above
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
);
-------------------------------------------
-- flush_command_queue
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Flushes the command queue of the specified VVC
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg : in string := ""
);
-------------------------------------------
-- flush_command_queue
-------------------------------------------
-- See description above
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := ""
);
-------------------------------------------
-- fetch_result
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Fetches result from a VVC
-- - Requires that result is available (i.e. already executed in respective VVC)
-- - Logs with ID ID_UVVM_CMD_RESULT
-- The 'result' parameter is of type t_vvc_result to
-- support that the BFM returns something other than a std_logic_vector.
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant caller_name : in string := "base_procedure"
);
-- -- Same as above but without fetch_is_accepted.
-- -- Will trigger alert with alert_level if not OK.
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
);
-- -- - This version does not use vvc_channel.
-- -- - Fetches result from a VVC
-- -- - Requires that result is available (i.e. already executed in respective VVC)
-- -- - Logs with ID ID_UVVM_CMD_RESULT
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
);
-- -- Same as above but without fetch_is_accepted.
-- -- Will trigger alert with alert_level if not OK.
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- VVC executor QUEUED command
-- - Inserts delay for 'delay' clock cycles
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in natural; -- in clock cycles
constant msg : in string := ""
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- See description above
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in natural; -- in clock cycles
constant msg : in string := ""
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- VVC executor QUEUED command
-- - Inserts delay for a given time
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in time;
constant msg : in string := ""
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- See description above
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in time;
constant msg : in string := ""
);
-------------------------------------------
-- terminate_current_command
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Terminates the current command being processed in the VVC executor
procedure terminate_current_command(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
);
-------------------------------------------
-- terminate_all_commands
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Terminates the current command being processed in the VVC executor, and
-- flushes the command queue
procedure terminate_all_commands(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
);
-- Returns the index of the last queued command
impure function get_last_received_cmd_idx(
signal vvc_target : in t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
) return natural;
end package td_vvc_framework_common_methods_pkg;
package body td_vvc_framework_common_methods_pkg is
--=========================================================================================
-- Methods
--=========================================================================================
-- NOTE: ALL VVCs using this td_vvc_framework_common_methods_pkg package MUST have the following declared in their local vvc_cmd_pkg.
-- - The enumerated t_operation (e.g. AWAIT_COMPLETION, ENABLE_LOG_MSG, etc.)
-- Any VVC based on an older version of td_vvc_framework_common_methods_pkg must - if new operators have been introduced in td_vvc_framework_common_methods_pkg either
-- a) include the new operator(s) in its t_operation, or
-- b) change the use-reference to an older common_methods package.
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant timeout : in time;
constant msg : in string := ""
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(timeout, ns) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := -1; -- All commands must be completed (i.e. not just a selected command index)
shared_vvc_cmd.timeout := timeout;
send_command_to_vvc(vvc_target, timeout);
end procedure;
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant timeout : in time;
constant msg : in string := ""
) is
begin
await_completion(vvc_target, vvc_instance_idx, NA, timeout, msg);
end procedure;
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in natural;
constant timeout : in time;
constant msg : in string := ""
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ", " & to_string(timeout, ns) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := wanted_idx;
shared_vvc_cmd.timeout := timeout;
send_command_to_vvc(vvc_target, timeout);
end procedure;
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in natural;
constant timeout : in time;
constant msg : in string := ""
) is
begin
await_completion(vvc_target, vvc_instance_idx, NA, wanted_idx, timeout, msg);
end procedure;
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0 -- Useful when being called by multiple sequencers
) is
constant proc_name : string := "await_any_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(timeout, ns) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_ANY_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := -1; -- All commands must be completed (i.e. not just a selected command index)
shared_vvc_cmd.gen_integer_array(1) := awaiting_completion_idx;
shared_vvc_cmd.timeout := timeout;
if lastness = LAST then
shared_vvc_cmd.gen_boolean := true; -- LAST
else
shared_vvc_cmd.gen_boolean := false; -- NOT_LAST
end if;
send_command_to_vvc(vvc_target, timeout); -- sets vvc_target.trigger, then waits until global_vvc_ack = '1' for timeout
end procedure;
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0
) is
begin
await_any_completion(vvc_target, vvc_instance_idx, NA, lastness, timeout, msg, awaiting_completion_idx);
end procedure;
-- The two below are as the two above, except with wanted_idx as parameter
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in natural;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0 -- Useful when being called by multiple sequencers
) is
constant proc_name : string := "await_any_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ", " & to_string(timeout, ns) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_ANY_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := wanted_idx;
shared_vvc_cmd.gen_integer_array(1) := awaiting_completion_idx;
shared_vvc_cmd.timeout := timeout;
if lastness = LAST then
-- LAST
shared_vvc_cmd.gen_boolean := true;
else
-- NOT_LAST : Timeout must be handled in interpreter_await_any_completion
-- becuase the command is always acknowledged immediately by the VVC to allow the sequencer to continue
shared_vvc_cmd.gen_boolean := false;
end if;
send_command_to_vvc(vvc_target, timeout);
end procedure;
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in natural;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0 -- Useful when being called by multiple sequencers
) is
begin
await_any_completion(vvc_target, vvc_instance_idx, NA, wanted_idx, lastness, timeout, msg, awaiting_completion_idx);
end procedure;
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
) is
constant proc_name : string := "disable_log_msg";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_upper(to_string(msg_id)) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, DISABLE_LOG_MSG);
shared_vvc_cmd.msg_id := msg_id;
shared_vvc_cmd.quietness := quietness;
send_command_to_vvc(vvc_target);
end procedure;
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
) is
begin
disable_log_msg(vvc_target, vvc_instance_idx, NA, msg_id, msg, quietness);
end procedure;
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
) is
constant proc_name : string := "enable_log_msg";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_upper(to_string(msg_id)) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, ENABLE_LOG_MSG);
shared_vvc_cmd.msg_id := msg_id;
shared_vvc_cmd.quietness := quietness;
send_command_to_vvc(vvc_target);
end procedure;
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
) is
begin
enable_log_msg(vvc_target, vvc_instance_idx, NA, msg_id, msg, quietness);
end procedure;
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg : in string := ""
) is
constant proc_name : string := "flush_command_queue";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, FLUSH_COMMAND_QUEUE);
send_command_to_vvc(vvc_target);
end procedure;
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := ""
) is
begin
flush_command_queue(vvc_target, vvc_instance_idx, NA, msg);
end procedure;
-- Requires that result is available (i.e. already executed in respective VVC)
-- The four next procedures are overloads for when 'result' is of type work.vvc_cmd_pkg.t_vvc_result
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant caller_name : in string := "base_procedure"
) is
constant proc_name : string := "fetch_result";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ")";
begin
await_semaphore_in_delta_cycles(protected_response_semaphore);
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, FETCH_RESULT);
shared_vvc_cmd.gen_integer_array(0) := wanted_idx;
send_command_to_vvc(vvc_target);
-- Post process
result := shared_vvc_response.result;
fetch_is_accepted := shared_vvc_response.fetch_is_accepted;
if caller_name = "base_procedure" then
log(ID_UVVM_CMD_RESULT, proc_call & ": Legal=>" & to_string(shared_vvc_response.fetch_is_accepted) & ", Result=>" & to_string(result) & format_command_idx(shared_cmd_idx), C_SCOPE); -- Get and ack the new command
end if;
release_semaphore(protected_response_semaphore);
end procedure;
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
) is
variable v_fetch_is_accepted : boolean;
constant proc_name : string := "fetch_result";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ")";
begin
fetch_result(vvc_target, vvc_instance_idx, vvc_channel, wanted_idx, result, v_fetch_is_accepted, msg, alert_level, proc_name & "_with_check_of_ok");
if v_fetch_is_accepted then
log(ID_UVVM_CMD_RESULT, proc_call & ": Legal=>" & to_string(v_fetch_is_accepted) & ", Result=>" & format_command_idx(shared_cmd_idx), C_SCOPE); -- Get and ack the new command
else
alert(alert_level, "fetch_result(" & to_string(wanted_idx) & "): " & add_msg_delimiter(msg) & "." &
" Failed. Trying to fetch result from not yet executed command or from command with no result stored. " & format_command_idx(shared_cmd_idx), C_SCOPE);
end if;
end procedure;
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
) is
begin
fetch_result(vvc_target, vvc_instance_idx, NA, wanted_idx, result, fetch_is_accepted, msg, alert_level);
end procedure;
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
) is
begin
fetch_result(vvc_target, vvc_instance_idx, NA, wanted_idx, result, msg, alert_level);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in natural; -- in clock cycles
constant msg : in string := ""
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(delay) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, QUEUED, INSERT_DELAY);
shared_vvc_cmd.gen_integer_array(0) := delay;
send_command_to_vvc(vvc_target);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in natural; -- in clock cycles
constant msg : in string := ""
) is
begin
insert_delay(vvc_target, vvc_instance_idx, NA, delay, msg);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in time;
constant msg : in string := ""
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(delay) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, QUEUED, INSERT_DELAY);
shared_vvc_cmd.delay := delay;
send_command_to_vvc(vvc_target);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in time;
constant msg : in string := ""
) is
begin
insert_delay(vvc_target, vvc_instance_idx, NA, delay, msg);
end procedure;
procedure terminate_current_command(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
) is
constant proc_name : string := "terminate_current_command";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, TERMINATE_CURRENT_COMMAND);
send_command_to_vvc(vvc_target);
end procedure;
procedure terminate_all_commands(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
) is
begin
flush_command_queue(vvc_target, vvc_instance_idx, vvc_channel,msg);
terminate_current_command(vvc_target, vvc_instance_idx, vvc_channel, msg);
end procedure;
-- Returns the index of the last queued command
impure function get_last_received_cmd_idx(
signal vvc_target : in t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
) return natural is
variable v_cmd_idx : integer := -1;
begin
v_cmd_idx := shared_vvc_last_received_cmd_idx(vvc_channel, vvc_instance_idx);
check_value(v_cmd_idx /= -1, tb_error, "Channel " & to_string(vvc_channel) & " not supported on VVC " & vvc_target.vvc_name, C_SCOPE, ID_NEVER);
if v_cmd_idx /= -1 then
return v_cmd_idx;
else
-- return 0 in case of failure
return 0;
end if;
end function;
end package body td_vvc_framework_common_methods_pkg;
| mit | 4152c66442c79bba34388e65a4c4e2e7 | 0.59113 | 4.171448 | false | false | false | false |
ashtonchase/logic_analyzer | target_hardware/ZedBoard/zed_top_capture_ctrl_test.vhd | 1 | 11,863 | -------------------------------------------------------------------------------
-- Title : Zybo Board Top Level
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : zybo_top_capture_cotnrol_test.vhd
-- Created : 2016-02-22
-- Last update: 2016-03-22
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: Xilinx Zynq 7000 on a Digilent Zybo Board Top Level Module,
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-22 1.0 ashton Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY zybo_top IS
PORT (
--Clock Source
GCLK : IN STD_LOGIC; -- 100 MHz clock
--LED Outputs
LD0, LD1, LD2, LD3, LD4, LD5, LD6, LD7 : OUT STD_LOGIC;
--Buttons
BTNC, BTND, BTNL, BTNR, BTNU : IN STD_LOGIC;
--Temporary Data Ouput (JA10-JA7, JA4-JA1)
JA10, JA9, JA8, JA7, JA4, JA3, JA2, JA1 : OUT STD_LOGIC;
--UART SIGNALS
JB4 : IN STD_LOGIC := 'H'; --RX
JB1 : OUT STD_LOGIC --TX
--Fixed Zync Signals
--DDR_addr : INOUT STD_LOGIC_VECTOR (14 DOWNTO 0);
--DDR_ba : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0);
--DDR_cas_n : INOUT STD_LOGIC;
--DDR_ck_n : INOUT STD_LOGIC;
--DDR_ck_p : INOUT STD_LOGIC;
--DDR_cke : INOUT STD_LOGIC;
--DDR_cs_n : INOUT STD_LOGIC;
--DDR_dm : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
--DDR_dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
--DDR_dqs_n : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
--DDR_dqs_p : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
--DDR_odt : INOUT STD_LOGIC;
--DDR_ras_n : INOUT STD_LOGIC;
--DDR_reset_n : INOUT STD_LOGIC;
--DDR_we_n : INOUT STD_LOGIC;
--FIXED_IO_ddr_vrn : INOUT STD_LOGIC;
--FIXED_IO_ddr_vrp : INOUT STD_LOGIC;
--FIXED_IO_mio : INOUT STD_LOGIC_VECTOR (53 DOWNTO 0);
--FIXED_IO_ps_clk : INOUT STD_LOGIC;
--FIXED_IO_ps_porb : INOUT STD_LOGIC;
--FIXED_IO_ps_srstb : INOUT STD_LOGIC;
);
END ENTITY zybo_top;
ARCHITECTURE top OF zybo_top IS
-----------------------------------------------------------------------------
-- Components
-----------------------------------------------------------------------------
COMPONENT Zynq_BD_wrapper IS
PORT (
DDR_addr : INOUT STD_LOGIC_VECTOR (14 DOWNTO 0);
DDR_ba : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0);
DDR_cas_n : INOUT STD_LOGIC;
DDR_ck_n : INOUT STD_LOGIC;
DDR_ck_p : INOUT STD_LOGIC;
DDR_cke : INOUT STD_LOGIC;
DDR_cs_n : INOUT STD_LOGIC;
DDR_dm : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
DDR_dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DDR_dqs_n : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
DDR_dqs_p : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
DDR_odt : INOUT STD_LOGIC;
DDR_ras_n : INOUT STD_LOGIC;
DDR_reset_n : INOUT STD_LOGIC;
DDR_we_n : INOUT STD_LOGIC;
FIXED_IO_ddr_vrn : INOUT STD_LOGIC;
FIXED_IO_ddr_vrp : INOUT STD_LOGIC;
FIXED_IO_mio : INOUT STD_LOGIC_VECTOR (53 DOWNTO 0);
FIXED_IO_ps_clk : INOUT STD_LOGIC;
FIXED_IO_ps_porb : INOUT STD_LOGIC;
FIXED_IO_ps_srstb : INOUT STD_LOGIC;
UART_rxd : IN STD_LOGIC;
UART_txd : OUT STD_LOGIC
);
END COMPONENT;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
CONSTANT DATA_WIDTH : POSITIVE := 32;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
SIGNAL reset, reset_clk_gen : STD_LOGIC := '1'; -- reset (async high, sync low)
SIGNAL run_clk : STD_LOGIC := '0'; -- clock output of the clocking wizard
SIGNAL clk_locked : STD_LOGIC := '0'; -- indicator if the clocking wizard has locked
SIGNAL din : STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
SIGNAL armed : STD_LOGIC;
SIGNAL triggered : STD_LOGIC;
SIGNAL rst_cmd : STD_LOGIC := '0';
SIGNAL arm_cmd : STD_LOGIC;
SIGNAL sample_enable : STD_LOGIC := '1';
SIGNAL sample_cnt_rst : STD_LOGIC;
SIGNAL delay_cnt_4x : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL read_cnt_4x : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(1000, 16));
SIGNAL par_trig_msk : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := X"00_00_00_03";
SIGNAL par_trig_val : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL capture_rdy : STD_LOGIC;
SIGNAL in_fifo_tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL in_fifo_tvalid : STD_LOGIC;
SIGNAL in_fifo_tlast : STD_LOGIC;
SIGNAL in_fifo_tready : STD_LOGIC;
SIGNAL in_fifo_tfull : STD_LOGIC;
SIGNAL in_fifo_tempty : STD_LOGIC;
SIGNAL in_fifo_tflush : STD_LOGIC;
--
SIGNAL out_fifo_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL out_fifo_tvalid : STD_LOGIC;
SIGNAL out_fifo_tlast : STD_LOGIC;
SIGNAL out_fifo_tready : STD_LOGIC;
-----------------------------------------------------------------------------
-- Aliases
-----------------------------------------------------------------------------
ALIAS reset_btn : STD_LOGIC IS BTND;
ALIAS CLK : STD_LOGIC IS GCLK;
ALIAS UART_RX : STD_LOGIC IS JB4;
ALIAS UART_TX : STD_LOGIC IS JB1;
BEGIN -- ARCHITECTURE top
JA10 <= out_fifo_tdata(7);
JA9 <= out_fifo_tdata(6);
JA8 <= out_fifo_tdata(5);
JA7 <= out_fifo_tdata(4);
JA4 <= out_fifo_tdata(3);
JA3 <= out_fifo_tdata(2);
JA2 <= out_fifo_tdata(1);
JA1 <= out_fifo_tdata(0);
--LED to indicate that the clock is locked
LD1 <= clk_locked;
capture_control_block : ENTITY work.capture_ctrl
GENERIC MAP (
DATA_WIDTH => DATA_WIDTH)
PORT MAP (
clk => run_clk,
rst => reset,
din => X"00_00_00" & "00000" & btnl & btnc & btnr,
armed => ld3,
triggered => ld2,
rst_cmd => btnd,
arm_cmd => btnu,
-- sample_enable => sample_enable,
sample_cnt_rst => sample_cnt_rst,
-- delay_cnt_4x => delay_cnt_4x,
read_cnt_4x => read_cnt_4x,
par_trig_msk => par_trig_msk,
par_trig_val => par_trig_val,
capture_rdy => ld0,
fifo_tdata => in_fifo_tdata,
fifo_tvalid => in_fifo_tvalid,
fifo_tlast => in_fifo_tlast,
fifo_tready => in_fifo_tready,
fifo_tfull => in_fifo_tfull,
fifo_tempty => in_fifo_tempty,
fifo_aresetn => in_fifo_tflush);
sample_storage_block : ENTITY work.storage
GENERIC MAP (
FIFO_SIZE => 2**18)
PORT MAP (
clk => run_clk,
reset => reset,
--
in_fifo_tdata => in_fifo_tdata,
in_fifo_tvalid => in_fifo_tvalid,
in_fifo_tlast => in_fifo_tlast,
in_fifo_tready => in_fifo_tready,
in_fifo_tfull => in_fifo_tfull,
in_fifo_tempty => in_fifo_tempty,
in_fifo_tflush => in_fifo_tflush,
--
out_fifo_tdata => out_fifo_tdata,
out_fifo_tvalid => out_fifo_tvalid,
out_fifo_tlast => out_fifo_tlast,
out_fifo_tready => '1');
-----------------------------------------------------------------------------
-- Component Instatiations
-----------------------------------------------------------------------------
-- purpose: this component will generate the desired system clock based on
-- the 125 MHz input clock. Not the output is already downstream of a global
-- clock buffer
-- inputs : clk, reset
-- outputs: clk_locked
run_clk_component : ENTITY work.clock_gen
PORT MAP (
-- Clock in ports
clk_in1 => clk,
-- Clock out ports
clk_out1 => run_clk,
-- Status and control signals
reset => reset_clk_gen,
locked => clk_locked
);
-- purpose: this process will reset the system when btn0 is pressed
-- type : combinational
-- inputs : reset_btn, clk, clk_locked
-- outputs: reset
run_clk_reset_proc : PROCESS (reset_btn, run_clk) IS
VARIABLE reset_dly_v : STD_LOGIC;
BEGIN -- PROCESS reset_proc
IF reset_btn = '1' THEN
reset <= '1';
reset_dly_v := '1';
ELSIF rising_edge(run_clk) THEN
IF clk_locked = '1' THEN
reset <= reset_dly_v;
reset_dly_v := '0';
ELSE
reset <= '1';
reset_dly_v := '1';
END IF;
END IF;
END PROCESS run_clk_reset_proc;
reset_proc : PROCESS (reset_btn, clk) IS
VARIABLE reset_dly_v : STD_LOGIC;
BEGIN -- PROCESS reset_proc
IF reset_btn = '1' THEN
reset_clk_gen <= '1';
ELSIF rising_edge(clk) THEN
reset_clk_gen <= reset_dly_v;
reset_dly_v := '0';
END IF;
END PROCESS reset_proc;
--zynq : ENTITY work.Zynq_BD_wrapper
-- PORT MAP (
-- DDR_addr => DDR_addr,
-- DDR_ba => DDR_ba,
-- DDR_cas_n => DDR_cas_n,
-- DDR_ck_n => DDR_ck_n,
-- DDR_ck_p => DDR_ck_p,
-- DDR_cke => DDR_cke,
-- DDR_cs_n => DDR_cs_n,
-- DDR_dm => DDR_dm,
-- DDR_dq => DDR_dq,
-- DDR_dqs_n => DDR_dqs_n,
-- DDR_dqs_p => DDR_dqs_p,
-- DDR_odt => DDR_odt,
-- DDR_ras_n => DDR_ras_n,
-- DDR_reset_n => DDR_reset_n,
-- DDR_we_n => DDR_we_n,
-- FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
-- FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
-- FIXED_IO_mio => FIXED_IO_mio,
-- FIXED_IO_ps_clk => FIXED_IO_ps_clk,
-- FIXED_IO_ps_porb => FIXED_IO_ps_porb,
-- FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
-- UART_rxd => UART_rxd,
-- UART_txd => UART_txd);
END ARCHITECTURE top;
| gpl-2.0 | da01c51f684d6c6ccb271009af6ff989 | 0.476102 | 3.734026 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.