repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
HackLinux/ION | src/rtl/cpu/ion_shifter.vhdl | 1 | 4,197 | --------------------------------------------------------------------------------
-- ion_shifter.vhdl -- combinational barrel shifter
--
--------------------------------------------------------------------------------
-- Copyright (C) 2011 Jose A. Ruiz
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received A_I copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity ION_SHIFTER is
port(
-- data input
D_I : in std_logic_vector(31 downto 0);
-- shift amount
A_I : in std_logic_vector(4 downto 0);
-- shift function: {0=sll,1=sla(unused),2=srl,3=sra}
FN_I : in std_logic_vector(1 downto 0);
-- shift result
R_O : out std_logic_vector(31 downto 0)
);
end;
architecture small of ION_SHIFTER is
signal i_rev, o_rev : std_logic_vector(31 downto 0);
signal ext : std_logic_vector(31 downto 0);
type t_s is array(0 to 5) of std_logic_vector(31 downto 0);
signal s : t_s;
begin
-- The barrel shifter needs to shift left and right. This would usually
-- require two parallel barrel shifters (left and right) and an output mux
-- stage. Instead, we're gonna use A_I single left shifter, with two
-- conditional bit-reversal stages at input and output.
-- This will increase the LUT depth (and thus the delay) by 1 LUT row but
-- we'll cut the area by 4/11 more or less (depends on how many dedicated
-- muxes vs. LUTs the synth will use).
-- The barrel shifter can account for as much as 1/4 of the CPU area
-- (excluding mult/div unit) so it makes sense to be cheap here if what we
-- want is A_I small core.
-- NOTE: this logic may or may not be in the critical delay path of the
-- core, depending on the cache implementation. See your synthesis report.
-- Reverse input when shifting right
input_reversed:
for i in 0 to 31 generate
begin
i_rev(i) <= D_I(31-i);
end generate input_reversed;
s(5) <= i_rev when FN_I(1)='1' else D_I;
-- Sign extension / zero extension
ext <= (others => D_I(31)) when FN_I(0)='1' else (others => '0');
-- Build left barrel shifter in 5 binary stages as usual
shifter_stages:
for i in 0 to 4 generate
begin
with A_I(i) select s(i) <=
s(i+1)(31-2**i downto 0) & ext(2**i-1 downto 0) when '1',
s(i+1) when others;
end generate shifter_stages;
-- Reverse output when shifting right
output_reversal:
for i in 0 to 31 generate
begin
o_rev(i) <= s(0)(31-i);
end generate output_reversal;
R_O <= o_rev when FN_I(1)='1' else s(0);
end architecture small;
| lgpl-3.0 | b2167b647931fd4131406d96b2e6c86e | 0.544198 | 4.317901 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/configuration/fpga_config_block.vhd | 1 | 24,485 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 30.01.2017
-- Design Name: FPGA Configuration Block
-- Module Name: fpga_config_block - RTL
-- Project Name: MMFE8 - NTUA
-- Target Devices: Artix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description: Module that samples the data coming from the UDP/Ethernet
-- to produce various control signals for the FPGA user logic. It controls
-- the configuration of the XADC/AXI4SPI_FLASH modules and more general
-- FPGA commands.
-- Dependencies: MMFE8 NTUA Project
--
-- Changelog:
-- 07.03.2017 Changed FPGA_conf_proc to accomodate CKBC/CKTP configuration
-- and future register address configuration scheme. (Christos Bakalis)
-- 14.03.2017 Register address configuration scheme deployed. (Christos Bakalis)
-- 17.03.2017 Added synchronizers for daq and trigger signals. (Christos Bakalis)
-- 31.03.2017 Added 2 ckbc mode register (Paris)
-- 05.08.2017 Added fpga_config_router and fpga_config_buffer to optimize the
-- FPGA configuration scheme. (Christos Bakalis)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity fpga_config_block is
port(
------------------------------------
------- General Interface ----------
clk_125 : in std_logic;
rst : in std_logic;
rst_fifo_init : in std_logic;
cnt_bytes : in unsigned(7 downto 0);
user_din_udp : in std_logic_vector(7 downto 0);
------------------------------------
-------- UDP Interface -------------
udp_rx : in udp_rx_type;
------------------------------------
---------- XADC Interface ----------
xadc_conf : in std_logic;
xadcPacket_rdy : out std_logic;
vmm_id_xadc : out std_logic_vector(15 downto 0);
xadc_sample_size : out std_logic_vector(10 downto 0);
xadc_delay : out std_logic_vector(17 downto 0);
------------------------------------
---------- AXI4SPI Interface -------
flash_conf : in std_logic;
flashPacket_rdy : out std_logic;
myIP_set : out std_logic_vector(31 downto 0);
myMAC_set : out std_logic_vector(47 downto 0);
destIP_set : out std_logic_vector(31 downto 0);
------------------------------------
-------- CKTP/CKBC Interface -------
ckbc_freq : out std_logic_vector(7 downto 0);
cktk_max_num : out std_logic_vector(7 downto 0);
cktp_max_num : out std_logic_vector(15 downto 0);
cktp_skew : out std_logic_vector(7 downto 0);
cktp_period : out std_logic_vector(15 downto 0);
cktp_width : out std_logic_vector(7 downto 0);
ckbc_max_num : out std_logic_vector(7 downto 0);
------------------------------------
-------- FPGA Config Interface -----
fpga_conf : in std_logic;
fpga_rst : out std_logic;
fpgaPacket_rdy : out std_logic;
latency : out std_logic_vector(15 downto 0);
tr_delay_limit : out std_logic_vector(15 downto 0);
daq_on : out std_logic;
ext_trigger : out std_logic;
ckbcMode : out std_logic
);
end fpga_config_block;
architecture RTL of fpga_config_block is
component fpga_reg_buffer
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic;
wr_rst_busy : out std_logic;
rd_rst_busy : out std_logic
);
end component;
component fpga_config_router
port(
------------------------------------
------ General Interface -----------
clk_125 : in std_logic;
reg_addr : in std_logic_vector(7 downto 0);
reg_rst : in std_logic;
reg_value_bit : in std_logic;
sreg_ena : in std_logic;
------------------------------------
---------- XADC Interface ----------
vmm_id_xadc : out std_logic_vector(15 downto 0);
xadc_sample_size : out std_logic_vector(10 downto 0);
xadc_delay : out std_logic_vector(17 downto 0);
------------------------------------
---------- AXI4SPI Interface -------
myIP_set : out std_logic_vector(31 downto 0);
myMAC_set : out std_logic_vector(47 downto 0);
destIP_set : out std_logic_vector(31 downto 0);
------------------------------------
-------- CKTP/CKBC Interface -------
ckbc_freq : out std_logic_vector(7 downto 0);
cktk_max_num : out std_logic_vector(7 downto 0);
cktp_max_num : out std_logic_vector(15 downto 0);
cktp_skew : out std_logic_vector(7 downto 0);
cktp_period : out std_logic_vector(15 downto 0);
cktp_width : out std_logic_vector(7 downto 0);
------------------------------------
-------- FPGA Config Interface -----
latency : out std_logic_vector(15 downto 0);
tr_delay_limit : out std_logic_vector(15 downto 0);
ckbc_max_num : out std_logic_vector(7 downto 0);
daq_state : out std_logic_vector(7 downto 0);
trig_state : out std_logic_vector(7 downto 0);
ro_state : out std_logic_vector(7 downto 0);
fpga_rst_state : out std_logic_vector(7 downto 0)
);
end component;
-- register the address/value and valid signal from UDP packet
signal reg_address : std_logic_vector(7 downto 0) := (others => '0');
signal reg_value : std_logic_vector(31 downto 0) := (others => '0');
signal din_valid : std_logic := '0';
signal din_last : std_logic := '0';
-- FPGA reset signals
signal reg_rst : std_logic := '0';
signal rst_cnt : integer range 0 to 63 := 0;
-- other
signal fpgaPacket_rdy_i : std_logic := '0';
-- FSM, demux signals
signal wait_cnt : unsigned(4 downto 0) := (others => '0');
signal reg_index : integer range 0 to 31 := 31;
signal reg_value_bit : std_logic := '0';
signal sreg_en : std_logic := '0';
signal read_buffers : std_logic := '0';
type stateType is (ST_IDLE, ST_CHK, ST_WAIT, ST_WRH_SREG, ST_WRL_SREG, ST_DONE);
signal state : stateType := ST_IDLE;
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of state : signal is "ONE_HOT";
-- signals for the FIFOs
signal wr_en : std_logic := '0';
signal rd_en : std_logic := '0';
signal rst_fifo : std_logic := '0';
signal din_regAddr : std_logic_vector(31 downto 0) := (others => '0');
signal dout_regAaddr : std_logic_vector(31 downto 0) := (others => '0');
signal dout_regValue : std_logic_vector(31 downto 0) := (others => '0');
signal addr_buffer_full : std_logic := '0';
signal addr_buffer_empty: std_logic := '0';
signal val_buffer_full : std_logic := '0';
signal val_buffer_empty : std_logic := '0';
signal addr_rdRst_busy : std_logic := '0';
signal addr_wrRst_busy : std_logic := '0';
signal val_rdRst_busy : std_logic := '0';
signal val_wrRst_busy : std_logic := '0';
-- internal registers and synchronizer signals
signal daq_state_reg : std_logic_vector(7 downto 0) := (others => '0');
signal trig_state_reg : std_logic_vector(7 downto 0) := (others => '0');
signal ro_state_reg : std_logic_vector(7 downto 0) := (others => '0');
signal fpga_rst_reg : std_logic_vector(7 downto 0) := (others => '0');
signal daq_on_i : std_logic := '0';
signal daq_on_sync : std_logic := '0';
signal ext_trg_i : std_logic := '0';
signal ext_trg_sync : std_logic := '0';
signal fpga_rst_i : std_logic := '0';
signal ckbcMode_i : std_logic := '0';
signal ckbcMode_sync : std_logic := '0';
-- async_regs
attribute ASYNC_REG : string;
attribute ASYNC_REG of daq_on : signal is "true";
attribute ASYNC_REG of daq_on_sync : signal is "true";
attribute ASYNC_REG of ext_trigger : signal is "true";
attribute ASYNC_REG of ext_trg_sync : signal is "true";
attribute ASYNC_REG of ckbcMode : signal is "true";
attribute ASYNC_REG of ckbcMode_sync : signal is "true";
begin
-- register the valid signal
reg_valid_proc: process(clk_125)
begin
if(rising_edge(clk_125))then
din_valid <= udp_rx.data.data_in_valid;
din_last <= udp_rx.data.data_in_last;
end if;
end process;
-- sub-process that samples register addresses and values for FPGA/xADC/Flash-IP configuration
FPGA_conf_proc: process(clk_125)
begin
if(rising_edge(clk_125))then
if(rst = '1')then
reg_address <= (others => '0');
reg_value <= (others => '0');
else
if((fpga_conf = '1' or flash_conf = '1' or xadc_conf = '1') and din_valid = '1')then
case cnt_bytes is
----------------------------
--- register addresses -----
when "00001100" => -- 12
reg_address <= user_din_udp;
when "00010100" => -- 20
reg_address <= user_din_udp;
when "00011100" => -- 28
reg_address <= user_din_udp;
when "00100100" => -- 36
reg_address <= user_din_udp;
when "00101100" => -- 44
reg_address <= user_din_udp;
when "00110100" => -- 52
reg_address <= user_din_udp;
when "00111100" => -- 60
reg_address <= user_din_udp;
----------------------------
--- register values --------
when "00001101" => -- 13
reg_value(31 downto 24) <= user_din_udp;
when "00001110" => -- 14
reg_value(23 downto 16) <= user_din_udp;
when "00001111" => -- 15
reg_value(15 downto 8) <= user_din_udp;
when "00010000" => -- 16
reg_value(7 downto 0) <= user_din_udp;
----------------------------
when "00010101" => -- 21
reg_value(31 downto 24) <= user_din_udp;
when "00010110" => -- 22
reg_value(23 downto 16) <= user_din_udp;
when "00010111" => -- 23
reg_value(15 downto 8) <= user_din_udp;
when "00011000" => -- 24
reg_value(7 downto 0) <= user_din_udp;
----------------------------
when "00011101" => -- 29
reg_value(31 downto 24) <= user_din_udp;
when "00011110" => -- 30
reg_value(23 downto 16) <= user_din_udp;
when "00011111" => -- 31
reg_value(15 downto 8) <= user_din_udp;
when "00100000" => -- 32
reg_value(7 downto 0) <= user_din_udp;
----------------------------
when "00100101" => -- 37
reg_value(31 downto 24) <= user_din_udp;
when "00100110" => -- 38
reg_value(23 downto 16) <= user_din_udp;
when "00100111" => -- 39
reg_value(15 downto 8) <= user_din_udp;
when "00101000" => -- 40
reg_value(7 downto 0) <= user_din_udp;
----------------------------
when "00101101" => -- 45
reg_value(31 downto 24) <= user_din_udp;
when "00101110" => -- 46
reg_value(23 downto 16) <= user_din_udp;
when "00101111" => -- 47
reg_value(15 downto 8) <= user_din_udp;
when "00110000" => -- 48
reg_value(7 downto 0) <= user_din_udp;
----------------------------
when "00110101" => -- 53
reg_value(31 downto 24) <= user_din_udp;
when "00110110" => -- 54
reg_value(23 downto 16) <= user_din_udp;
when "00110111" => -- 55
reg_value(15 downto 8) <= user_din_udp;
when "00111000" => -- 56
reg_value(7 downto 0) <= user_din_udp;
----------------------------
when "00111101" => -- 61
reg_value(31 downto 24) <= user_din_udp;
when "00111110" => -- 62
reg_value(23 downto 16) <= user_din_udp;
when "00111111" => -- 63
reg_value(15 downto 8) <= user_din_udp;
when "01000000" => -- 64
reg_value(7 downto 0) <= user_din_udp;
----------------------------
when "01000100" => -- 68
read_buffers <= '1';
when others => null;
end case;
elsif((fpga_conf = '1' or flash_conf = '1' or xadc_conf = '1') and din_valid = '0')then
read_buffers <= '1';
else
read_buffers <= '0';
end if;
end if;
end if;
end process;
-- process that controls the write-enable signal
wr_ena_proc: process(clk_125)
begin
if(rising_edge(clk_125))then
if((fpga_conf = '1' or flash_conf = '1' or xadc_conf = '1') and din_valid = '1' and din_last = '0')then
case cnt_bytes is
-- 18 26 34 42 50 58 66
when "00010010" | "00011010" | "00100010" | "00101010" | "00110010" | "00111010" | "01000010" =>
wr_en <= '1';
-- 19 27 35 43 51 59 67
when "00010011" | "00011011" | "00100011" | "00101011" | "00110011" | "00111011" | "01000011" =>
wr_en <= '0';
when others =>
wr_en <= '0';
end case;
elsif((fpga_conf = '1' or flash_conf = '1' or xadc_conf = '1') and din_valid = '1' and din_last = '1')then
wr_en <= '1';
else
wr_en <= '0';
end if;
end if;
end process;
-- FSM that reads the two FIFOs and fills the shift registers
FSM_FPGA_conf: process(clk_125)
begin
if(rising_edge(clk_125))then
--reg_value_bit <= dout_regValue(reg_index); -- userclk2 clock domain
if(fpga_conf = '0' and flash_conf = '0' and xadc_conf = '0')then
rd_en <= '0';
sreg_en <= '0';
reg_index <= 31;
fpgaPacket_rdy_i <= '0';
flashPacket_rdy <= '0';
xadcPacket_rdy <= '0';
wait_cnt <= (others => '0');
state <= ST_IDLE;
else
case state is
-- wait to be activated by registering process
when ST_IDLE =>
if(read_buffers = '1' and wait_cnt = "11111")then
wait_cnt <= (others => '0');
state <= ST_CHK;
elsif(read_buffers = '1' and wait_cnt /= "11111")then
wait_cnt <= wait_cnt + 1;
state <= ST_IDLE;
else
wait_cnt <= (others => '0');
state <= ST_IDLE;
end if;
-- check if the FIFOs are empty
when ST_CHK =>
if(addr_buffer_empty = '0' and val_buffer_empty = '0')then
rd_en <= '1';
state <= ST_WAIT;
else
rd_en <= '0';
state <= ST_DONE;
end if;
-- wait here for MUX and shift register
when ST_WAIT =>
rd_en <= '0';
wait_cnt <= wait_cnt + 1;
if(wait_cnt = "00111")then
state <= ST_WRH_SREG;
else
state <= ST_WAIT;
end if;
-- write the shift register
when ST_WRH_SREG =>
sreg_en <= '1';
state <= ST_WRL_SREG;
-- check the index
when ST_WRL_SREG =>
sreg_en <= '0';
if(reg_index = 0)then -- sent the entire register value
reg_index <= 31;
state <= ST_CHK;
else
reg_index <= reg_index - 1;
state <= ST_WAIT;
end if;
-- wait here until reset by master_handling_FSM
when ST_DONE =>
if(fpga_conf = '1')then
fpgaPacket_rdy_i <= '1';
elsif(flash_conf = '1')then
flashPacket_rdy <= '1';
elsif(xadc_conf = '1')then
xadcPacket_rdy <= '1';
else
fpgaPacket_rdy_i <= '1';
end if;
state <= ST_DONE;
when others =>
rd_en <= '0';
sreg_en <= '0';
reg_index <= 31;
fpgaPacket_rdy_i <= '0';
flashPacket_rdy <= '0';
xadcPacket_rdy <= '0';
wait_cnt <= (others => '0');
state <= ST_IDLE;
end case;
end if;
end if;
end process;
fpga_conf_router_inst: fpga_config_router
port map(
------------------------------------
------ General Interface -----------
clk_125 => clk_125,
reg_addr => dout_regAaddr(7 downto 0),
reg_rst => reg_rst,
reg_value_bit => reg_value_bit,
sreg_ena => sreg_en,
------------------------------------
---------- XADC Interface ----------
vmm_id_xadc => vmm_id_xadc,
xadc_sample_size => xadc_sample_size,
xadc_delay => xadc_delay,
------------------------------------
---------- AXI4SPI Interface -------
myIP_set => myIP_set,
myMAC_set => myMAC_set,
destIP_set => destIP_set,
------------------------------------
-------- CKTP/CKBC Interface -------
ckbc_freq => ckbc_freq,
cktk_max_num => cktk_max_num,
cktp_max_num => cktp_max_num,
cktp_skew => cktp_skew,
cktp_period => cktp_period,
cktp_width => cktp_width,
------------------------------------
-------- FPGA Config Interface -----
latency => latency,
tr_delay_limit => tr_delay_limit,
ckbc_max_num => ckbc_max_num,
daq_state => daq_state_reg,
trig_state => trig_state_reg,
ro_state => ro_state_reg,
fpga_rst_state => fpga_rst_reg
);
reg_addr_buffer: fpga_reg_buffer
PORT MAP (
rst => rst_fifo,
wr_clk => clk_125,
rd_clk => clk_125,
din => din_regAddr,
wr_en => wr_en,
rd_en => rd_en,
dout => dout_regAaddr,
full => addr_buffer_full,
empty => addr_buffer_empty,
wr_rst_busy => addr_rdRst_busy,
rd_rst_busy => addr_wrRst_busy
);
reg_value_buffer: fpga_reg_buffer
PORT MAP (
rst => rst_fifo,
wr_clk => clk_125,
rd_clk => clk_125,
din => reg_value,
wr_en => wr_en,
rd_en => rd_en,
dout => dout_regValue,
full => val_buffer_full,
empty => val_buffer_empty,
wr_rst_busy => val_rdRst_busy,
rd_rst_busy => val_wrRst_busy
);
-- FPGA reset asserter
rst_asserter_proc: process(clk_125)
begin
if(rising_edge(clk_125))then
if(fpga_rst_i = '1')then
case rst_cnt is
when 0 to 62 =>
fpga_rst <= '1';
rst_cnt <= rst_cnt + 1;
when 63 =>
fpga_rst <= '0';
reg_rst <= '1';
when others =>
rst_cnt <= 0;
fpga_rst <= '0';
reg_rst <= '0';
end case;
else
rst_cnt <= 0;
fpga_rst <= '0';
reg_rst <= '0';
end if;
end if;
end process;
din_regAddr <= x"000000" & reg_address;
fpgaPacket_rdy <= fpgaPacket_rdy_i;
-- process to handle daq state
daqOnOff_proc: process(daq_state_reg, daq_on_i, fpgaPacket_rdy_i)
begin
if(fpgaPacket_rdy_i = '1')then
case daq_state_reg is
when x"01" => daq_on_i <= '1';
when x"00" => daq_on_i <= '0';
when others => daq_on_i <= daq_on_i;
end case;
else
daq_on_i <= daq_on_i;
end if;
end process;
-- process to handle trigger state
triggerState_proc: process(trig_state_reg, ext_trg_i, fpgaPacket_rdy_i)
begin
if(fpgaPacket_rdy_i = '1')then
case trig_state_reg is
when x"04" => ext_trg_i <= '1';
when x"07" => ext_trg_i <= '0';
when others => ext_trg_i <= ext_trg_i;
end case;
else
ext_trg_i <= ext_trg_i;
end if;
end process;
-- process to handle readout state
readoutState_proc: process(ro_state_reg, ckbcMode_i, fpgaPacket_rdy_i)
begin
if(fpgaPacket_rdy_i = '1')then
case ro_state_reg is
when x"01" => ckbcMode_i <= '1';
when x"00" => ckbcMode_i <= '0';
when others => ckbcMode_i <= ckbcMode_i;
end case;
else
ckbcMode_i <= ckbcMode_i;
end if;
end process;
-- process to handle FPGA reset state
FPGArst_proc: process(fpga_rst_reg, fpga_rst_i, fpgaPacket_rdy_i)
begin
if(fpgaPacket_rdy_i = '1')then
case fpga_rst_reg is
when x"aa" => fpga_rst_i <= '1';
when x"00" => fpga_rst_i <= '0';
when others => fpga_rst_i <= fpga_rst_i;
end case;
else
fpga_rst_i <= fpga_rst_i;
end if;
end process;
-- synchronizing circuit
syncProc: process(clk_125)
begin
if(rising_edge(clk_125))then
daq_on_sync <= daq_on_i;
daq_on <= daq_on_sync;
ext_trg_sync <= ext_trg_i;
ext_trigger <= ext_trg_sync;
ckbcMode_sync <= ckbcMode_i;
ckbcMode <= ckbcMode_sync;
end if;
end process;
reg_value_bit <= dout_regValue(reg_index); -- userclk2 clock domain
rst_fifo <= rst or fpgaPacket_rdy_i or rst_fifo_init; -- reset the FIFOs after each configuration
end RTL;
| gpl-3.0 | 68bdedfaceecfeede6a296497eb9ba3f | 0.467225 | 3.910093 | false | false | false | false |
HackLinux/ION | src/rtl/cpu/ion_core.vhdl | 1 | 17,129 | --------------------------------------------------------------------------------
-- ion_core.vhdl -- MIPS32r2(tm) compatible CPU core
--------------------------------------------------------------------------------
-- This is the main project module. It contains the CPU plus the TCMs and caches
-- if it is configured to have any.
-- The user does not need to tinker with any modules at or below this level.
--------------------------------------------------------------------------------
-- FIXME when caches are missing they should be replaced with a WB bridge.
-- TODO add brief usage instructions.
-- TODO add reference to datasheet.
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ion_core is
generic(
-- Size of code TCM block in 32-bit words.
-- Set to a power of 2 or to zero to disable code TCM.
TCM_CODE_SIZE : integer := 2048;
-- Contents of code TCM. Defaults to zero.
TCM_CODE_INIT : t_obj_code := zero_objcode(16);
-- Size of data TCM block in 32-bit words.
-- Set to a power of 2 or to zero to disable data TCM.
TCM_DATA_SIZE : integer := 2048;
-- Contents of data TCM.
TCM_DATA_INIT : t_obj_code := zero_objcode(16);
-- Size of data cache in lines.
-- Set to a power of 2 or 0 to disable the data cache.
DATA_CACHE_LINES : integer := 128;
-- Size of code cache in lines.
-- Set to a power of 2 or 0 to disable the code cache.
CODE_CACHE_LINES : integer := 128;
-- Type of memory to be used for register bank in xilinx HW
XILINX_REGBANK : string := "distributed" -- {distributed|block}
);
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
-- Code cache refill port.
CODE_WB_MOSI_O : out t_wishbone_mosi;
CODE_WB_MISO_I : in t_wishbone_miso;
-- Data cache refill port.
DATA_WB_MOSI_O : out t_wishbone_mosi;
DATA_WB_MISO_I : in t_wishbone_miso;
-- Uncached data WB bridge port.
DATA_UC_WB_MOSI_O : out t_wishbone_mosi;
DATA_UC_WB_MISO_I : in t_wishbone_miso;
-- COP2 interface.
COP2_MOSI_O : out t_cop2_mosi;
COP2_MISO_I : in t_cop2_miso;
IRQ_I : in std_logic_vector(5 downto 0)
);
end; --entity ion_cpu
architecture rtl of ion_core is
--------------------------------------------------------------------------------
-- CPU interface signals
signal data_mosi : t_cpumem_mosi;
signal data_miso : t_cpumem_miso;
signal code_mosi : t_cpumem_mosi;
signal code_miso : t_cpumem_miso;
signal cache_ctrl_mosi : t_cache_mosi;
signal icache_ctrl_miso : t_cache_miso;
signal dcache_ctrl_miso : t_cache_miso;
--------------------------------------------------------------------------------
-- Code space signals
-- Address decoding signals.
signal code_mux_ctrl : std_logic_vector(1 downto 0);
signal code_mux_ctrl_reg : std_logic_vector(1 downto 0);
signal code_ce : std_logic_vector(1 downto 0);
-- Instruction Cache MISO bus & enable signal.
signal icache_miso : t_cpumem_miso;
-- Code TCM MISO bus & enable signal.
signal ctcm_c_miso : t_cpumem_miso;
-- Bus from CTCM arbiter to CTCM.
signal ctcm_mosi : t_cpumem_mosi;
signal ctcm_miso : t_cpumem_miso;
--------------------------------------------------------------------------------
-- Data space signals
-- Address decoding signals.
signal data_mux_ctrl : std_logic_vector(2 downto 0);
signal data_mux_ctrl_reg : std_logic_vector(2 downto 0);
signal data_ce : std_logic_vector(3 downto 0);
-- Data Cache MISO bus & enable signal.
signal dcache_miso : t_cpumem_miso;
signal dcache_ce : std_logic;
-- Data TCM MISO bus & enable signal.
signal dtcm_miso : t_cpumem_miso;
signal dtcm_ce : std_logic;
-- Code TCM MISO bus & enable signal (CTCM seen from data bus).
signal ctcm_d_miso : t_cpumem_miso;
-- Uncached Data, external WB bridge MISO bus & enable signal.
signal ucd_wb_mosi : t_cpumem_mosi;
signal ucd_wb_miso : t_cpumem_miso;
signal void_miso : t_cpumem_miso;
--------------------------------------------------------------------------------
-- Address decoding constant & constant functions.
-- Data TCM mapped to the start of KSEG1 uncached area.
constant DTCM_BASE : t_word := X"A0000000";
constant DTCM_ASIZE : integer := log2(TCM_DATA_SIZE+2);
-- Code TCM mapped to reset vector within KSEG1 uncached area.
constant CTCM_BASE : t_word := X"BFC00000";
constant CTCM_ASIZE : integer := log2(TCM_CODE_SIZE+2);
-- Code TCM accessible on data bus on the same address as on the code bus.
constant DCTCM_BASE : t_word := X"BFC00000";
-- Wishbone port is mapped to high 1GB area, meant for I/O mostly.
constant DWB_BASE : t_word := X"c0000000";
constant DWB_ASIZE : integer := 30;
-- NOTE: all the functions defined in this entity are "constant functions" that
-- can be used in synthesizable rtl as long as their parameters are constants.
-- Return '1' if high 's' of address 'a' match those of address 'b'.
function adecode(a : t_word; b : t_word; s : integer) return std_logic is
begin
if a(31 downto s+1) = b(31 downto s+1) then
return '1';
else
return '0';
end if;
end function adecode;
-- Decode address to see if it is within the cached area.
-- (Cached addresses are all addresses from 0x00000000 to 0x9fffffff.)
-- Return '1' if address 'a' is cached, '0' otherwise.
function cached(a : t_word) return std_logic is
begin
if a(31 downto 29) = "101" or a(31 downto 30) = "11" then
return '0';
else
return '1';
end if;
end function cached;
begin
--------------------------------------------------------------------------------
-- CPU
cpu: entity work.ION_CPU
generic map (
XILINX_REGBANK => XILINX_REGBANK
)
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
DATA_MOSI_O => data_mosi,
DATA_MISO_I => data_miso,
CODE_MOSI_O => code_mosi,
CODE_MISO_I => code_miso,
CACHE_CTRL_MOSI_O => cache_ctrl_mosi,
ICACHE_CTRL_MISO_I => icache_ctrl_miso,
DCACHE_CTRL_MISO_I => dcache_ctrl_miso,
COP2_MOSI_O => COP2_MOSI_O,
COP2_MISO_I => COP2_MISO_I,
IRQ_I => IRQ_I
);
--------------------------------------------------------------------------------
-- Code Bus interconnect.
-- Address decoding --------------------------------------------------------
-- Decode the index of the slave being addressed.
code_mux_ctrl <=
"01" when adecode(code_mosi.addr, CTCM_BASE, CTCM_ASIZE) = '1' else
"10" when cached(code_mosi.addr) = '1' else
"00";
-- Convert slave index to one-hot enable signal vector.
with code_mux_ctrl select code_ce <=
"01" when "01",
"10" when "10",
"00" when others;
-- Code MISO multiplexor -----------------------------------------------
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
code_mux_ctrl_reg <= (others => '0');
elsif code_mosi.rd_en='1' then
code_mux_ctrl_reg <= code_mux_ctrl;
end if;
end if;
end process;
with code_mux_ctrl_reg select code_miso <=
ctcm_c_miso when "01",
icache_miso when "10",
void_miso when others;
-- MISO to be fed to the CPU by the code and data MISO multiplexors when
-- no valid area is addressed.
void_miso.mwait <= '0';
void_miso.rd_data <= (others => '0');
-- Code cache ----------------------------------------------------------
code_cache_present:
if CODE_CACHE_LINES > 0 generate
code_cache: entity work.ION_CACHE
generic map (
NUM_LINES => CODE_CACHE_LINES
)
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
-- FIXME there should be a MISO for each cache in the control port
CACHE_CTRL_MOSI_I => cache_ctrl_mosi,
CACHE_CTRL_MISO_O => OPEN,
CE_I => code_ce(1),
CPU_MOSI_I => code_mosi,
CPU_MISO_O => icache_miso,
MEM_MOSI_O => CODE_WB_MOSI_O,
MEM_MISO_I => CODE_WB_MISO_I
);
end generate code_cache_present;
code_cache_missing:
if CODE_CACHE_LINES = 0 generate
icache_miso.mwait <= '0';
icache_miso.rd_data <= (others => '0');
-- FIXME a missing code cache should be replaced by a WB bridge.
CODE_WB_MOSI_O.cyc <= '0';
CODE_WB_MOSI_O.stb <= '0';
icache_ctrl_miso.present <= '0';
end generate code_cache_missing;
-- Code TCM ------------------------------------------------------------
tcm_code_present:
if TCM_CODE_SIZE > 0 generate
-- Arbiter: share Code TCM between Code and Data space accesses.
-- note that Data accesses have priority necessarily.
code_arbiter: entity work.ION_CTCM_ARBITER
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
MASTER_D_CE_I => data_ce(2),
MASTER_D_MOSI_I => data_mosi,
MASTER_D_MISO_O => ctcm_d_miso,
MASTER_C_CE_I => code_ce(0),
MASTER_C_MOSI_I => code_mosi,
MASTER_C_MISO_O => ctcm_c_miso,
SLAVE_MOSI_O => ctcm_mosi,
SLAVE_MISO_I => ctcm_miso
);
-- Code TCM block.
code_tcm: entity work.ION_TCM_CODE
generic map (
SIZE => TCM_CODE_SIZE,
INIT_DATA => TCM_CODE_INIT
)
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
EN_I => code_ce(0),
MEM_MOSI_I => ctcm_mosi,
MEM_MISO_O => ctcm_miso
);
end generate tcm_code_present;
tcm_code_missing:
if TCM_CODE_SIZE = 0 generate
ctcm_miso.mwait <= '0';
ctcm_miso.rd_data <= (others => '0');
end generate tcm_code_missing;
--------------------------------------------------------------------------------
-- Data Bus interconnect.
-- Address decoding --------------------------------------------------------
-- Decode the index of the slave being addressed.
data_mux_ctrl <=
"001" when adecode(data_mosi.addr, DTCM_BASE, DTCM_ASIZE) = '1' else
"011" when adecode(data_mosi.addr, DCTCM_BASE, CTCM_ASIZE) = '1' else
"010" when cached(data_mosi.addr) = '1' else
"100" when adecode(data_mosi.addr, DWB_BASE, DWB_ASIZE) = '1' else
"100";
-- Convert slave index to one-hot enable signal vector.
with data_mux_ctrl select data_ce <=
"0001" when "001",
"0010" when "010",
"0100" when "011",
"1000" when "100",
"0000" when others;
-- Data MISO multiplexor -----------------------------------------------
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
data_mux_ctrl_reg <= (others => '0');
elsif data_mosi.rd_en='1' or data_mosi.wr_be/="0000" then
data_mux_ctrl_reg <= data_mux_ctrl;
end if;
end if;
end process;
with data_mux_ctrl_reg select data_miso <=
dtcm_miso when "001",
dcache_miso when "010",
ctcm_d_miso when "011",
ucd_wb_miso when "100",
void_miso when others;
-- Data cache ----------------------------------------------------------
data_cache_present:
if DATA_CACHE_LINES > 0 generate
data_cache: entity work.ION_CACHE
generic map (
NUM_LINES => DATA_CACHE_LINES
)
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
-- FIXME there should be a MISO for each cache in the control port
CACHE_CTRL_MOSI_I => cache_ctrl_mosi,
CACHE_CTRL_MISO_O => dcache_ctrl_miso,
CE_I => data_ce(1),
CPU_MOSI_I => data_mosi,
CPU_MISO_O => dcache_miso,
MEM_MOSI_O => DATA_WB_MOSI_O,
MEM_MISO_I => DATA_WB_MISO_I
);
end generate data_cache_present;
data_cache_missing:
if DATA_CACHE_LINES = 0 generate
dcache_miso.mwait <= '0';
dcache_miso.rd_data <= (others => '0');
-- FIXME a missing data cache should be replaced by a WB bridge.
DATA_WB_MOSI_O.cyc <= '0';
DATA_WB_MOSI_O.stb <= '0';
dcache_ctrl_miso.present <= '0';
end generate data_cache_missing;
-- Data TCM ------------------------------------------------------------
tcm_data_present:
if TCM_DATA_SIZE > 0 generate
data_tcm: entity work.ION_TCM_DATA
generic map (
SIZE => TCM_DATA_SIZE,
INIT_DATA => TCM_DATA_INIT
)
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
EN_I => data_ce(0),
MEM_MOSI_I => data_mosi,
MEM_MISO_O => dtcm_miso
);
end generate tcm_data_present;
tcm_data_missing:
if TCM_DATA_SIZE = 0 generate
dtcm_miso.mwait <= '0';
dtcm_miso.rd_data <= (others => '0');
end generate tcm_data_missing;
-- Wishbone Bridge ---------------------------------------------------------
-- The CPU side of the WB bridge will only be enabled if addressed.
with data_ce(3) select ucd_wb_mosi.rd_en <=
data_mosi.rd_en when '1',
'0' when others;
with data_ce(3) select ucd_wb_mosi.wr_be <=
data_mosi.wr_be when '1',
"0000" when others;
ucd_wb_mosi.addr <= data_mosi.addr;
ucd_wb_mosi.wr_data <= data_mosi.wr_data;
-- WB bridge instance.
data_wb_bridge: entity work.ION_WISHBONE_BRIDGE
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
ION_MOSI_I => ucd_wb_mosi,
ION_MISO_O => ucd_wb_miso,
WISHBONE_MOSI_O => DATA_UC_WB_MOSI_O,
WISHBONE_MISO_I => DATA_UC_WB_MISO_I
);
end architecture rtl;
| lgpl-3.0 | f1487330b583fc96c1a6ec96f307bb57 | 0.47802 | 4.160554 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/configuration/trint_gen.vhd | 1 | 6,059 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 12.04.2017 20:51:01
-- Design Name:
-- Module Name: trint_gen - RTL
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: State machine that detects a CKTP pulse and issues an internal
-- trigger signal that starts the readout process.
--
-- Dependencies:
--
-- Changelog:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity trint_gen is
Generic(vmmReadoutMode : std_logic);
Port(
clk_160 : in std_logic;
clk_125 : in std_logic;
cktp_start : in std_logic;
cktp_pulse : in std_logic;
ckbc_mode : in std_logic;
cktp_width : in std_logic_vector(11 downto 0);
trint : out std_logic
);
end trint_gen;
architecture RTL of trint_gen is
signal trint_cnt : unsigned(11 downto 0) := (others => '0');
signal cktp_start_i : std_logic := '0';
signal cktp_start_s_0 : std_logic := '0';
signal cktp_start_s : std_logic := '0';
signal cktp_start_final : std_logic := '0';
signal cnt_delay : unsigned(3 downto 0) := (others => '0');
signal trint_i : std_logic := '0'; -- synced @ 160
-- signal trint_s_0 : std_logic := '0';
-- signal trint_s : std_logic := '0'; -- synced @ 125
type trint_state_type is (ST_INIT, ST_IDLE, ST_WAIT, ST_TRINT);
signal state : trint_state_type := ST_INIT;
attribute ASYNC_REG : string;
attribute ASYNC_REG of cktp_start_s_0 : signal is "TRUE";
attribute ASYNC_REG of cktp_start_s : signal is "TRUE";
-- attribute ASYNC_REG of trint_s_0 : signal is "TRUE";
-- attribute ASYNC_REG of trint_s : signal is "TRUE";
begin
-- check if the width is zero, and inhibit the fsm if so
width_check_proc: process(cktp_width, cktp_start)
begin
case cktp_width is
when x"000" =>
cktp_start_i <= '0';
when others =>
if(cktp_start = '1')then
cktp_start_i <= '1';
else
cktp_start_i <= '0';
end if;
end case;
end process;
-- sync the start signal
sync_start_proc: process(clk_160)
begin
if(rising_edge(clk_160))then
cktp_start_s_0 <= cktp_start_i;
cktp_start_s <= cktp_start_s_0;
end if;
end process;
-- delay assertion of cktp start
cktp_enable_delayer_trint: process(clk_160)
begin
if(rising_edge(clk_160))then
if(cktp_start_s = '1')then
if(cnt_delay < "1110")then
cnt_delay <= cnt_delay + 1;
cktp_start_final <= '0';
else
cktp_start_final <= '1';
end if;
else
cnt_delay <= (others => '0');
cktp_start_final <= '0';
end if;
end if;
end process;
-- internal trigger FSM
trint_fsm: process(clk_160)
begin
if(rising_edge(clk_160))then
if(cktp_start_final = '1')then
case state is
-- only proceed if cktp is low
when ST_INIT =>
if(cktp_pulse = '0')then
state <= ST_IDLE;
else
state <= ST_INIT;
end if;
-- wait for CKTP pulse
when ST_IDLE =>
trint_i <= '0';
trint_cnt <= (others => '0');
if(cktp_pulse = '1' and vmmReadoutMode = '0')then
state <= ST_TRINT;
elsif(cktp_pulse = '1' and vmmReadoutMode = '1')then
state <= ST_TRINT;
else
state <= ST_IDLE;
end if;
-- wait before asserting the internal trigger
when ST_WAIT =>
if(cktp_pulse = '1')then
trint_cnt <= trint_cnt + 1;
if(trint_cnt < unsigned(cktp_width) - "1000110")then
state <= ST_WAIT;
else
state <= ST_TRINT;
end if;
else
state <= ST_IDLE;
end if;
-- assert the internal trigger pulse (expected width ~ 400ns if continuous mode)
when ST_TRINT =>
trint_i <= '1';
if(cktp_pulse = '1')then
state <= ST_TRINT;
else
state <= ST_IDLE;
end if;
when others => state <= ST_INIT;
end case;
else
trint_i <= '0';
trint_cnt <= (others => '0');
state <= ST_INIT;
end if;
end if;
end process;
-- sync the trint signal (Obsolete as the signal is synced one level-up)
--sync_trint_proc: process(clk_125)
--begin
-- if(rising_edge(clk_125))then
-- trint_s_0 <= trint_i;
-- trint_s <= trint_s_0;
-- end if;
--end process;
trint <= trint_i; -- synced to 160 Mhz
end RTL; | gpl-3.0 | 6841b4fd5b27fff30df18f711b263388 | 0.517907 | 3.805905 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/BLOCK_WORD_COUNTER.vhd | 1 | 4,970 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: BLOCK_WORD_COUNTER
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.centralRouter_package.all;
use work.all;
--! counts block words, inserts block header
entity BLOCK_WORD_COUNTER is
generic (
GBTid : integer := 0;
egroupID : integer := 0;
epathID : integer := 0
);
port (
CLK : in std_logic;
RESET : in std_logic;
RESTART : in std_logic;
BW_RDY : in std_logic; -- Block Word Ready Enable
-------------
EOB_MARK : out std_logic; -- End Of Block flag to send the trailer
BLOCK_HEADER_OUT : out std_logic_vector(15 downto 0); --> sending block header
BLOCK_HEADER_OUT_RDY : out std_logic; --> sending block header
-------------
BLOCK_COUNT_RDY : out std_logic
);
end BLOCK_WORD_COUNTER;
architecture Behavioral of BLOCK_WORD_COUNTER is
signal count_sig : std_logic_vector (9 downto 0) := (others => '0');
signal seq_num : std_logic_vector (4 downto 0) := (others => '0');
signal SOB_MARK, SOB_MARK0, seqCNTcase, seqCNTtrig, EOB_MARK_sig : std_logic;
signal SOB_MARK1, blockCountRdy : std_logic := '0';
signal BLOCK_HEADER : std_logic_vector(31 downto 0);
-- two first words are always sent in the beginning of a block transmittion
constant count_offset : std_logic_vector (9 downto 0) := "0000000001"; --(others => '0');
begin
ce: process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' or RESTART = '1' then
blockCountRdy <= '0';
elsif SOB_MARK1 = '1' then
blockCountRdy <= '1';
end if;
end if;
end process;
--
BLOCK_COUNT_RDY <= blockCountRdy;
--------------------------------------------------------------
-- counting block words, data partition
--------------------------------------------------------------
counter: process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
count_sig <= (others => '0');
else
if EOB_MARK_sig = '1' or RESTART = '1' then
count_sig <= count_offset;
elsif BW_RDY = '1' then
count_sig <= count_sig + 1;
end if;
end if;
end if;
end process;
--------------------------------------------------------------
-- End Of Block trigger out for the
-- sub-chunk data manager to insert a trailer
--------------------------------------------------------------
EOB_MARK_sig <= '1' when (count_sig = BLOCK_WORDn) else '0'; -- there is one more space left, for the trailer
EOB_MARK <= EOB_MARK_sig; -- to output
--------------------------------------------------------------
-- Block Sequence counter, 5 bit
--------------------------------------------------------------
seqCNTcase <= EOB_MARK_sig or RESTART;
seqCNTtrig_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>2,pw=>1) port map(CLK, seqCNTcase, seqCNTtrig);
--
scounter: process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
seq_num <= (others => '0');
else
if seqCNTtrig = '1' then
seq_num <= seq_num + 1;
end if;
end if;
end if;
end process;
--------------------------------------------------------------
-- Start Of Block Mark to insert block header
--------------------------------------------------------------
SOB_MARK <= '1' when (count_sig = count_offset) else '0';
--------------------------------------------------------------
-- Start Of Block produces 2 triggers
-- to send 2 words, as header is 32bit
--------------------------------------------------------------
SOB_MARK0_PULSE: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(CLK, SOB_MARK, SOB_MARK0); -- FIFO WE to send word0
SOB_MARK1_PULSE: process(CLK)
begin
if rising_edge(CLK) then
SOB_MARK1 <= SOB_MARK0; -- FIFO WE to send word1
end if;
end process;
--
-- [0xABCD_16] [[block_counter_5] [GBTid_5 egroupID_3 epathID_3]]
BLOCK_HEADER <= "1010101111001101" & seq_num & (std_logic_vector(to_unsigned(GBTid, 5))) & (std_logic_vector(to_unsigned(egroupID, 3))) & (std_logic_vector(to_unsigned(epathID, 3)));
--
out_sel: process(CLK)
begin
if rising_edge(CLK) then
if SOB_MARK0 = '1' then
BLOCK_HEADER_OUT <= BLOCK_HEADER(31 downto 16);
else
BLOCK_HEADER_OUT <= BLOCK_HEADER(15 downto 0);
end if;
end if;
end process;
--
BLOCK_HEADER_OUT_RDY <= SOB_MARK0 or SOB_MARK1;
--
end Behavioral; | gpl-3.0 | 3455090ad9249cba62d7a5626754783e | 0.495372 | 3.805513 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/IP_complete_nomac.vhd | 2 | 15,067 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:43:16 06/04/2011
-- Design Name:
-- Module Name: IP_complete_nomac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Implements complete IP stack with ARP (but no MAC)
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Revision 0.03 - Added mac_tx_tfirst
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
use work.arp;
use work.arpv2;
entity IP_complete_nomac is
generic (
use_arpv2 : boolean := true; -- use ARP with multipule entries. for signel entry, set
-- to false
no_default_gateway : boolean := false; -- set to false if communicating with devices accessed
-- through a "default gateway or router"
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
ip_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end IP_complete_nomac;
architecture structural of IP_complete_nomac is
component IPv4
port(
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system control signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- system status signals
rx_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer RX signals
mac_data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in std_logic; -- indicates data_in valid on clock
mac_data_in_last : in std_logic; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
end component;
component arp
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 1; -- (added for compatibility with arpv2. this value not used in this impl)
MAX_ARP_ENTRIES : integer := 1 -- (added for compatibility with arpv2. this value not used in this impl)
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
control : in arp_control_type;
req_count : out std_logic_vector(7 downto 0) -- count of arp pkts received
);
end component;
component tx_arbitrator
port(
clk : in std_logic;
reset : in std_logic;
req_1 : in std_logic;
grant_1 : out std_logic;
data_1 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_1 : in std_logic; -- tdata is valid
first_1 : in std_logic; -- indicates first byte of frame
last_1 : in std_logic; -- indicates last byte of frame
req_2 : in std_logic;
grant_2 : out std_logic;
data_2 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_2 : in std_logic; -- tdata is valid
first_2 : in std_logic; -- indicates first byte of frame
last_2 : in std_logic; -- indicates last byte of frame
data : out std_logic_vector(7 downto 0); -- data byte to tx
valid : out std_logic; -- tdata is valid
first : out std_logic; -- indicates first byte of frame
last : out std_logic -- indicates last byte of frame
);
end component;
-------------------
-- Configuration
--
-- Enable one of the following to specify which
-- implementation of the ARP layer to use
-------------------
-- for arp_layer : arp use entity work.arp; -- single slot arbitrator
-- for arp_layer : arp use entity work.arpv2; -- multislot arbitrator
---------------------------
-- Signals
---------------------------
-- ARP REQUEST
signal arp_req_req_int : arp_req_req_type;
signal arp_req_rslt_int : arp_req_rslt_type;
-- MAC arbitration busses
signal ip_mac_req : std_logic;
signal ip_mac_grant : std_logic;
signal ip_mac_data_out : std_logic_vector (7 downto 0);
signal ip_mac_valid : std_logic;
signal ip_mac_first : std_logic;
signal ip_mac_last : std_logic;
signal arp_mac_req : std_logic;
signal arp_mac_grant : std_logic;
signal arp_mac_data_out : std_logic_vector (7 downto 0);
signal arp_mac_valid : std_logic;
signal arp_mac_first : std_logic;
signal arp_mac_last : std_logic;
-- MAC RX bus
signal mac_rx_tready_int : std_logic;
-- MAC TX bus
signal mac_tx_tdata_int : std_logic_vector (7 downto 0);
signal mac_tx_tvalid_int : std_logic;
signal mac_tx_tfirst_int : std_logic;
signal mac_tx_tlast_int : std_logic;
-- control signals
signal mac_tx_granted_int : std_logic;
begin
mac_rx_tready_int <= '1'; -- enable the mac receiver
-- set followers
mac_tx_tdata <= mac_tx_tdata_int;
mac_tx_tvalid <= mac_tx_tvalid_int;
mac_tx_tfirst <= mac_tx_tfirst_int;
mac_tx_tlast <= mac_tx_tlast_int;
mac_rx_tready <= mac_rx_tready_int;
------------------------------------------------------------------------------
-- Instantiate the IP layer
------------------------------------------------------------------------------
IP_layer : IPv4 port map
(
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready => ip_tx_data_out_ready,
ip_rx_start => ip_rx_start,
ip_rx => ip_rx,
rx_clk => rx_clk,
tx_clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
rx_pkt_count => ip_pkt_count,
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
mac_tx_req => ip_mac_req,
mac_tx_granted => ip_mac_grant,
mac_data_out_ready => mac_tx_tready,
mac_data_out_valid => ip_mac_valid,
mac_data_out_first => ip_mac_first,
mac_data_out_last => ip_mac_last,
mac_data_out => ip_mac_data_out,
mac_data_in => mac_rx_tdata,
mac_data_in_valid => mac_rx_tvalid,
mac_data_in_last => mac_rx_tlast
);
------------------------------------------------------------------------------
-- Instantiate the ARP layer
------------------------------------------------------------------------------
signle_entry_arp: if (not use_arpv2) generate
arp_layer : entity work.arp
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
port map(
-- request signals
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
-- rx signals
data_in_clk => rx_clk,
reset => reset,
data_in => mac_rx_tdata,
data_in_valid => mac_rx_tvalid,
data_in_last => mac_rx_tlast,
-- tx signals
mac_tx_req => arp_mac_req,
mac_tx_granted => arp_mac_grant,
data_out_clk => tx_clk,
data_out_ready => mac_tx_tready,
data_out_valid => arp_mac_valid,
data_out_first => arp_mac_first,
data_out_last => arp_mac_last,
data_out => arp_mac_data_out,
-- system signals
our_mac_address => our_mac_address,
our_ip_address => our_ip_address,
control => control.arp_controls,
req_count => arp_pkt_count
);
end generate signle_entry_arp;
multi_entry_arp: if (use_arpv2) generate
arp_layer : entity work.arpv2
generic map (
no_default_gateway => no_default_gateway,
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
port map(
-- request signals
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
-- rx signals
data_in_clk => rx_clk,
reset => reset,
data_in => mac_rx_tdata,
data_in_valid => mac_rx_tvalid,
data_in_last => mac_rx_tlast,
-- tx signals
mac_tx_req => arp_mac_req,
mac_tx_granted => arp_mac_grant,
data_out_clk => tx_clk,
data_out_ready => mac_tx_tready,
data_out_valid => arp_mac_valid,
data_out_first => arp_mac_first,
data_out_last => arp_mac_last,
data_out => arp_mac_data_out,
-- system signals
our_mac_address => our_mac_address,
our_ip_address => our_ip_address,
control => control.arp_controls,
req_count => arp_pkt_count
);
end generate multi_entry_arp;
------------------------------------------------------------------------------
-- Instantiate the TX Arbitrator
------------------------------------------------------------------------------
mac_tx_arb : tx_arbitrator
port map(
clk => tx_clk,
reset => reset,
req_1 => ip_mac_req,
grant_1 => ip_mac_grant,
data_1 => ip_mac_data_out,
valid_1 => ip_mac_valid,
first_1 => ip_mac_first,
last_1 => ip_mac_last,
req_2 => arp_mac_req,
grant_2 => arp_mac_grant,
data_2 => arp_mac_data_out,
valid_2 => arp_mac_valid,
first_2 => arp_mac_first,
last_2 => arp_mac_last,
data => mac_tx_tdata_int,
valid => mac_tx_tvalid_int,
first => mac_tx_tfirst_int,
last => mac_tx_tlast_int
);
end structural;
| gpl-3.0 | 8978938d46045f5d598210bae7beb8b2 | 0.532953 | 3.657039 | false | false | false | false |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/fetch2decode_reg.vhd | 1 | 581 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fetch2decode_reg is
port(
clk, rst : in std_logic;
noop : in std_logic;
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0));
end fetch2decode_reg;
architecture mixed of fetch2decode_reg is
begin
process(clk, rst)
begin
if (rst = '1') then
data_out <= X"0000";
elsif rising_edge(clk) then
if (noop = '1') then
data_out <= X"0000";
else
data_out <= data_in;
end if;
end if;
end process;
end mixed;
| unlicense | 203221b36ef60550df14be833254441c | 0.674699 | 2.7277 | false | false | false | false |
EltonBroering/Estacionamento-Inteligente-com-portas-logicas | multiplex.vhd | 1 | 5,076 | -- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 32-bit"
-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
-- CREATED "Thu May 22 09:35:54 2014"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY multiplex IS
PORT
(
P2 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
P0 : IN STD_LOGIC;
P3 : IN STD_LOGIC;
display_dezena : OUT STD_LOGIC;
display_unidade_0 : OUT STD_LOGIC;
display_unidade_1 : OUT STD_LOGIC;
display_unidade_2 : OUT STD_LOGIC;
display_unidade_3 : OUT STD_LOGIC
);
END multiplex;
ARCHITECTURE bdf_type OF multiplex IS
ATTRIBUTE black_box : BOOLEAN;
ATTRIBUTE noopt : BOOLEAN;
COMPONENT \74158_0\
PORT(GN : IN STD_LOGIC;
SEL : IN STD_LOGIC;
m1A : IN STD_LOGIC;
m1B : IN STD_LOGIC;
m2A : IN STD_LOGIC;
m2B : IN STD_LOGIC;
m3A : IN STD_LOGIC;
m3B : IN STD_LOGIC;
m4A : IN STD_LOGIC;
m4B : IN STD_LOGIC;
m1YN : OUT STD_LOGIC;
m2YN : OUT STD_LOGIC;
m3YN : OUT STD_LOGIC;
m4YN : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74158_0\: COMPONENT IS true;
ATTRIBUTE noopt OF \74158_0\: COMPONENT IS true;
COMPONENT \74283_1\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_1\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_1\: COMPONENT IS true;
COMPONENT \74684_2\
PORT(P2 : IN STD_LOGIC;
Q2 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
Q1 : IN STD_LOGIC;
P0 : IN STD_LOGIC;
Q0 : IN STD_LOGIC;
P7 : IN STD_LOGIC;
Q7 : IN STD_LOGIC;
Q6 : IN STD_LOGIC;
P6 : IN STD_LOGIC;
Q5 : IN STD_LOGIC;
P5 : IN STD_LOGIC;
P4 : IN STD_LOGIC;
Q4 : IN STD_LOGIC;
Q3 : IN STD_LOGIC;
P3 : IN STD_LOGIC;
P_GR_QN : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74684_2\: COMPONENT IS true;
ATTRIBUTE noopt OF \74684_2\: COMPONENT IS true;
SIGNAL SYNTHESIZED_WIRE_28 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_10 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_29 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_30 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_31 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_32 : STD_LOGIC;
BEGIN
SYNTHESIZED_WIRE_2 <= '0';
SYNTHESIZED_WIRE_29 <= '0';
SYNTHESIZED_WIRE_30 <= '1';
SYNTHESIZED_WIRE_31 <= '0';
SYNTHESIZED_WIRE_32 <= '0';
display_dezena <= NOT(SYNTHESIZED_WIRE_28);
display_unidade_3 <= NOT(SYNTHESIZED_WIRE_1);
b2v_inst1 : 74158_0
PORT MAP(GN => SYNTHESIZED_WIRE_2,
SEL => SYNTHESIZED_WIRE_28,
m1A => SYNTHESIZED_WIRE_4,
m1B => P0,
m2A => SYNTHESIZED_WIRE_5,
m2B => P1,
m3A => SYNTHESIZED_WIRE_6,
m3B => P2,
m4A => SYNTHESIZED_WIRE_7,
m4B => P3,
m1YN => SYNTHESIZED_WIRE_8,
m2YN => SYNTHESIZED_WIRE_9,
m3YN => SYNTHESIZED_WIRE_10,
m4YN => SYNTHESIZED_WIRE_1);
display_unidade_0 <= NOT(SYNTHESIZED_WIRE_8);
display_unidade_1 <= NOT(SYNTHESIZED_WIRE_9);
display_unidade_2 <= NOT(SYNTHESIZED_WIRE_10);
b2v_inst26 : 74283_1
PORT MAP(CIN => SYNTHESIZED_WIRE_29,
A1 => P0,
A2 => P1,
B2 => SYNTHESIZED_WIRE_30,
A3 => P2,
A4 => P3,
B4 => SYNTHESIZED_WIRE_29,
B1 => SYNTHESIZED_WIRE_29,
B3 => SYNTHESIZED_WIRE_30,
SUM4 => SYNTHESIZED_WIRE_7,
SUM1 => SYNTHESIZED_WIRE_4,
SUM2 => SYNTHESIZED_WIRE_5,
SUM3 => SYNTHESIZED_WIRE_6);
b2v_inst45 : 74684_2
PORT MAP(P2 => P2,
Q2 => SYNTHESIZED_WIRE_31,
P1 => P1,
Q1 => SYNTHESIZED_WIRE_31,
P0 => P0,
Q0 => SYNTHESIZED_WIRE_30,
P7 => SYNTHESIZED_WIRE_32,
Q7 => SYNTHESIZED_WIRE_32,
Q6 => SYNTHESIZED_WIRE_32,
P6 => SYNTHESIZED_WIRE_32,
Q5 => SYNTHESIZED_WIRE_32,
P5 => SYNTHESIZED_WIRE_32,
P4 => SYNTHESIZED_WIRE_32,
Q4 => SYNTHESIZED_WIRE_32,
Q3 => SYNTHESIZED_WIRE_30,
P3 => P3,
P_GR_QN => SYNTHESIZED_WIRE_28);
END bdf_type; | gpl-2.0 | f554b9c2edd97fd86a54c56c4779ea35 | 0.666273 | 2.915566 | false | false | false | false |
quicky2000/top_test_fsm_implem | fsm_implem.vhd | 1 | 6,930 | --
-- This file is part of top_test_fsm_implem
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fsm_implem is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
output : out STD_LOGIC);
end fsm_implem;
-- Fmax : 217.58Mhz
-- Number of Slice Flip Flops : 6
-- Number of 4 input LUTs : 9
-- Number of occupied Slices : 5
-- Number of BUFGMUXs : 1
-- Average Fanout of Non-Clock Nets : 3.6
architecture Simple of fsm_implem is
constant low_duration : positive := 7;
constant max_value : positive := 18;
type output_type is (low,high);
signal next_value : output_type := low;
signal value : output_type := low;
signal counter : std_logic_vector ( 4 downto 0 ) := (others => '0');
begin
-- process managing state register
process (clk,rst)
begin
if rising_edge(clk) then
if rst = '1' or unsigned(counter) = max_value then
counter <= (others => '0');
else
counter <= std_logic_vector(unsigned(counter) + 1);
end if;
end if;
end process;
-- process managing state register
process (clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
value <= low;
else
value <= next_value;
end if;
end if;
end process;
-- process computing next state
process (value,counter)
begin
case value is
when low => if unsigned(counter) = low_duration then
next_value <= high;
else
next_value <= low;
end if;
when high => if unsigned(counter) = max_value then
next_value <= low;
else
next_value <= high;
end if;
when others => next_value <= low;
end case;
end process;
-- output function
output <= '1' when value = high else '0';
end Simple;
-- Fmax : 223.065 Mhz
-- Total Number Slice Registers : 7
-- Number used as Flip Flops : 6
-- Number used as Latches : 1
-- Number of 4 input LUTs : 9
-- Number of occupied Slices : 7
-- Number of BUFGMUXs : 1
-- Average Fanout of Non-Clock Nets : 3.9
architecture Trial of fsm_implem is
constant low_duration : positive := 7;
constant max_value : positive := 18;
type output_type is (low,high);
signal next_value : output_type := low;
signal prepared_value : output_type := low;
signal value : output_type := low;
signal counter : std_logic_vector ( 4 downto 0 ) := (others => '0');
begin
-- process managing state register
process (clk,rst)
begin
if rising_edge(clk) then
if rst = '1' or unsigned(counter) = max_value then
counter <= (others => '0');
else
counter <= std_logic_vector(unsigned(counter) + 1);
end if;
end if;
end process;
-- process managing state register
process (clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
value <= low;
else
value <= next_value;
end if;
end if;
end process;
-- process computing prepared_value
process (value)
begin
case value is
when low => prepared_value <= high;
when high => prepared_value <= low;
when others => prepared_value <= low;
end case;
end process;
-- process computing next_value_value
process (counter,prepared_value,next_value)
begin
if unsigned(counter) = low_duration or unsigned(counter) = max_value then
next_value <= prepared_value;
else
next_value <= next_value;
end if;
end process;
-- output function
output <= '1' when value = high else '0';
end Trial;
-- Fmax : 229.727 Mhz
-- Number of Slice Flip Flops : 6
-- Number of 4 input LUTs : 8
-- Number of occupied Slices : 6
-- Total Number of 4 input LUTs : 8
-- Number of BUFGMUXs : 1
-- Average Fanout of Non-Clock Nets : 3.20
architecture Naive of fsm_implem is
constant low_duration : positive := 7;
constant max_value : positive := 18;
signal counter : std_logic_vector ( 4 downto 0 ) := (others => '0');
begin
-- process managing state register
process (clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
counter <= (others => '0');
output <= '0';
else
if unsigned(counter) = max_value - 1 then
counter <= (others => '0');
else
counter <= std_logic_vector(unsigned(counter) + 1);
end if;
if unsigned(counter) < low_duration then
output <= '0';
else
output <= '1';
end if;
end if;
end if;
end process;
end Naive;
-- Fmax : 315.159 MHz
-- Number of Slice Flip Flops : 7
-- Number of 4 input LUTs : 6
-- Number of occupied Slices : 6
-- Total Number of 4 input LUTs : 6
-- Number of BUFGMUXs : 1
-- Average Fanout of Non-Clock Nets : 3.00
architecture Test of fsm_implem is
constant low_duration : positive := 7;
constant max_value : positive := 18;
constant counter_low : positive := 16-low_duration+1;
constant counter_high : positive := 16 - (max_value - low_duration )+ 1;
signal valueN : std_logic := '0';
signal valueP : std_logic := '0';
signal counterP : std_logic_vector ( 4 downto 0 ) := std_logic_vector(to_unsigned(counter_low,5));
signal counterN : std_logic_vector ( 4 downto 0 ) := (others => '0');
begin
-- main_process
main_process : process(clk,rst)
begin
if rst = '1' then
counterP <= std_logic_vector(to_unsigned(counter_low,5));
valueP <= '0';
elsif rising_edge(clk) then
output <= valueP;
if counterP(4) = '1' then
valueP <= valueN;
counterP <= counterN;
else
counterP <= std_logic_vector(unsigned(counterP)+1);
end if;
end if;
end process;
-- process computing next_value
prepare_next_value : process (valueP)
begin
case valueP is
when '0' => valueN <= '1';
when '1' => valueN <= '0';
when others => valueN <= '0';
end case;
end process;
-- process computing next counter
prepare_next_counter : process (valueP)
begin
case valueP is
when '0' => counterN <= std_logic_vector(to_unsigned(counter_high,5));
when '1' => counterN <= std_logic_vector(to_unsigned(counter_low,5));
when others => counterN <= std_logic_vector(to_unsigned(counter_high,5));
end case;
end process;
end Test;
| gpl-3.0 | 29af85c661958cda5ffc5f36fa5b5291 | 0.65873 | 3.271955 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Multirate/multirate_fir_filter.vhd | 1 | 3,680 | --------------------------------------------------------------------------------------------------
-- Multirate FIR Filter
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package multirate_fir_filter_pkg is
--FIR filter component declaration
component multirate_fir_filter is
generic( h : coefficient_array);
port( clk_low : in std_logic;
clk_high : in std_logic;
rst : in std_logic;
x : in sig;
y : out sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
use work.decimator_pkg.all;
use work.interpolator_pkg.all;
use work.fir_filter_pkg.all;
--synthesis translate_off
use work.tb_write_csv_pkg.all;
--synthesis translate_on
entity multirate_fir_filter is
generic( h : coefficient_array);
port( clk_low : in std_logic;
clk_high : in std_logic;
rst : in std_logic;
x : in sig;
y : out sig);
end multirate_fir_filter;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of multirate_fir_filter is
signal decimated : sig := (others => '0');
signal filtered : fir_sig := (others => '0');
constant DECIMATED_FILE : string
:= "X:\Education\Masters Thesis\matlab\multirate\decimated_sig.csv";
constant DECIMATED_FILTERED_FILE : string
:= "X:\Education\Masters Thesis\matlab\multirate\decimated_filtered_sig.csv";
begin
--Decimate the signal by 2
downsampling : decimator
generic map(h => PR_ANALYSIS_LOW)
port map( clk_high => clk_high,
clk_low => clk_low,
rst => rst,
sig_high => x,
sig_low => decimated);
--Filter the decimated signal
filter : fir_filter
generic map(h => h)
port map( clk => clk_low,
rst => rst,
x => decimated,
y => filtered);
--Interpolate the filtered signal up by 2
upsample : interpolator
generic map(h => PR_SYNTHESIS_LOW)
port map( clk_high => clk_high,
clk_low => clk_low,
rst => rst,
sig_low => filtered(29 downto 14),
sig_high => y);
--synthesis translate_off
--Output to files for review
writer1 : tb_write_csv
generic map(FILENAME => DECIMATED_FILE)
port map( clk => clk_low,
data => std_logic_vector(decimated));
writer2 : tb_write_csv
generic map(FILENAME => DECIMATED_FILTERED_FILE)
port map( clk => clk_low,
data => std_logic_vector(filtered(29 downto 14)));
--synthesis translate_on
end behave;
| mit | 714130cffdde892e8ab3652e7ef30d20 | 0.42663 | 4.854881 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/Decoder8b10b.vhd | 1 | 3,174 | -------------------------------------------------------------------------------
-- Title :
-------------------------------------------------------------------------------
-- File : Decoder8b10b.vhd
-- Author : Benjamin Reese <[email protected]>
-- Company : SLAC National Accelerator Laboratory
-- Created : 2012-11-15
-- Last update: 2013-08-02
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.StdRtlPkg.all;
use work.Code8b10bPkg.all;
entity Decoder8b10b is
generic (
TPD_G : time := 1 ns;
NUM_BYTES_G : positive := 2;
RST_POLARITY_G : sl := '1';
RST_ASYNC_G : boolean := false);
port (
clk : in sl;
clkEn : in sl := '1';
rst : in sl;
dataIn : in slv(NUM_BYTES_G*10-1 downto 0);
dataOut : out slv(NUM_BYTES_G*8-1 downto 0);
dataKOut : out slv(NUM_BYTES_G-1 downto 0);
codeErr : out slv(NUM_BYTES_G-1 downto 0);
dispErr : out slv(NUM_BYTES_G-1 downto 0));
end entity Decoder8b10b;
architecture rtl of Decoder8b10b is
type RegType is record
runDisp : sl;
dataOut : slv(NUM_BYTES_G*8-1 downto 0);
dataKOut : slv(NUM_BYTES_G-1 downto 0);
codeErr : slv(NUM_BYTES_G-1 downto 0);
dispErr : slv(NUM_BYTES_G-1 downto 0);
end record RegType;
constant REG_INIT_C : RegType := (
runDisp => '0',
dataOut => (others => '0'),
dataKOut => (others => '0'),
codeErr => (others => '0'),
dispErr => (others => '0'));
signal r : RegType := REG_INIT_C;
signal rin : RegType;
begin
comb : process (r, dataIn, rst) is
variable v : RegType;
variable dispChainVar : sl;
begin
v := r;
dispChainVar := r.runDisp;
for i in 0 to NUM_BYTES_G-1 loop
decode8b10b(dataIn => dataIn(i*10+9 downto i*10),
dispIn => dispChainVar,
dataOut => v.dataOut(i*8+7 downto i*8),
dataKOut => v.dataKOut(i),
dispOut => dispChainVar,
codeErr => v.codeErr(i),
dispErr => v.dispErr(i));
end loop;
v.runDisp := dispChainVar;
if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then
v := REG_INIT_C;
end if;
rin <= v;
dataOut <= r.dataOut;
dataKOut <= r.dataKOut;
codeErr <= r.codeErr;
dispErr <= r.dispErr;
end process comb;
seq : process (clk, rst) is
begin
if (RST_ASYNC_G and rst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
elsif (rising_edge(clk)) then
if (clkEn = '1') then
r <= rin after TPD_G;
end if;
end if;
end process seq;
end architecture rtl;
| gpl-3.0 | 3dba0ee77243e0e76a09cf53a0038872 | 0.467549 | 3.742925 | false | false | false | false |
rkrajnc/minimig-mist | rtl/tg68k/TG68K_ALU.vhd | 1 | 36,854 | ------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2011 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
use IEEE.numeric_std.ALL;
use work.TG68K_Pack.ALL;
entity TG68K_ALU is
generic (
MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode : integer := 0 --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
);
port (
clk : in std_logic;
Reset : in std_logic;
clkena_lw : in std_logic := '1';
execOPC : in bit;
exe_condition : in std_logic;
exec_tas : in std_logic;
long_start : in bit;
non_aligned : in std_logic;
movem_presub : in bit;
set_stop : in bit;
Z_error : in bit;
rot_bits : in std_logic_vector(1 downto 0);
exec : in bit_vector(lastOpcBit downto 0);
OP1out : in std_logic_vector(31 downto 0);
OP2out : in std_logic_vector(31 downto 0);
reg_QA : in std_logic_vector(31 downto 0);
reg_QB : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(15 downto 0);
datatype : in std_logic_vector(1 downto 0);
exe_opcode : in std_logic_vector(15 downto 0);
exe_datatype : in std_logic_vector(1 downto 0);
sndOPC : in std_logic_vector(15 downto 0);
last_data_read : in std_logic_vector(15 downto 0);
data_read : in std_logic_vector(15 downto 0);
FlagsSR : in std_logic_vector(7 downto 0);
micro_state : in micro_states;
bf_ext_in : in std_logic_vector(7 downto 0);
bf_ext_out : out std_logic_vector(7 downto 0);
bf_width : in std_logic_vector(4 downto 0);
bf_loffset : in std_logic_vector(4 downto 0);
bf_offset : in std_logic_vector(31 downto 0);
set_V_Flag_out : out bit;
Flags_out : out std_logic_vector(7 downto 0);
c_out_out : out std_logic_vector(2 downto 0);
addsub_q_out : out std_logic_vector(31 downto 0);
ALUout : out std_logic_vector(31 downto 0)
);
end TG68K_ALU;
architecture logic of TG68K_ALU IS
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- ALU and more
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
signal OP1in : std_logic_vector(31 downto 0);
signal addsub_a : std_logic_vector(31 downto 0);
signal addsub_b : std_logic_vector(31 downto 0);
signal notaddsub_b : std_logic_vector(33 downto 0);
signal add_result : std_logic_vector(33 downto 0);
signal addsub_ofl : std_logic_vector(2 downto 0);
signal opaddsub : BIT;
signal c_in : std_logic_vector(3 downto 0);
signal flag_z : std_logic_vector(2 downto 0);
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal CCRin : std_logic_vector(7 downto 0);
signal niba_l : std_logic_vector(5 downto 0);
signal niba_h : std_logic_vector(5 downto 0);
signal niba_lc : std_logic;
signal niba_hc : std_logic;
signal bcda_lc : std_logic;
signal bcda_hc : std_logic;
signal nibs_l : std_logic_vector(5 downto 0);
signal nibs_h : std_logic_vector(5 downto 0);
signal nibs_lc : std_logic;
signal nibs_hc : std_logic;
signal bcd_a : std_logic_vector(8 downto 0);
signal bcd_s : std_logic_vector(8 downto 0);
signal pack_out : std_logic_vector(15 downto 0);
signal pack_a : std_logic_vector(15 downto 0);
signal result_mulu : std_logic_vector(63 downto 0);
signal result_div : std_logic_vector(63 downto 0);
signal set_mV_Flag : std_logic;
signal V_Flag : BIT;
signal rot_rot : std_logic;
signal rot_lsb : std_logic;
signal rot_msb : std_logic;
signal rot_X : std_logic;
signal rot_C : std_logic;
signal rot_out : std_logic_vector(31 downto 0);
signal asl_VFlag : std_logic;
signal bit_bits : std_logic_vector(1 downto 0);
signal bit_number : std_logic_vector(4 downto 0);
signal bits_out : std_logic_vector(31 downto 0);
signal one_bit_in : std_logic;
signal bchg : std_logic;
signal bset : std_logic;
signal mulu_sign : std_logic;
signal mulu_signext : std_logic_vector(16 downto 0);
signal muls_msb : std_logic;
signal mulu_reg : std_logic_vector(63 downto 0);
signal FAsign : std_logic;
signal faktorA : std_logic_vector(31 downto 0);
signal faktorB : std_logic_vector(31 downto 0);
signal div_reg : std_logic_vector(63 downto 0);
signal div_quot : std_logic_vector(63 downto 0);
signal div_ovl : std_logic;
signal div_neg : std_logic;
signal div_bit : std_logic;
signal div_sub : std_logic_vector(32 downto 0);
signal div_over : std_logic_vector(32 downto 0);
signal nozero : std_logic;
signal div_qsign : std_logic;
signal divisor : std_logic_vector(63 downto 0);
signal divs : std_logic;
signal signedOP : std_logic;
signal OP1_sign : std_logic;
signal OP2_sign : std_logic;
signal OP2outext : std_logic_vector(15 downto 0);
signal in_offset : std_logic_vector(5 downto 0);
signal datareg : std_logic_vector(31 downto 0);
signal insert : std_logic_vector(31 downto 0);
signal bf_datareg : std_logic_vector(31 downto 0);
signal result : std_logic_vector(39 downto 0);
signal result_tmp : std_logic_vector(39 downto 0);
signal sign : std_logic_vector(31 downto 0);
signal bf_loff_dir : std_logic_vector(4 downto 0);
signal bf_set2 : std_logic_vector(39 downto 0);
signal copy : std_logic_vector(39 downto 0);
signal bf_firstbit : std_logic_vector(5 downto 0);
signal bf_bset : std_logic;
signal bf_NFlag : std_logic;
signal bf_bchg : std_logic;
signal bf_ins : std_logic;
signal bf_exts : std_logic;
signal bf_extu : std_logic;
signal bf_fffo : std_logic;
signal bf_d32 : std_logic;
signal index : std_logic_vector(4 downto 0);
signal bf_flag_z : std_logic;
signal bf_flag_n : std_logic;
signal set_V_Flag : BIT;
signal Flags : std_logic_vector(7 downto 0);
signal c_out : std_logic_vector(2 downto 0);
signal addsub_q : std_logic_vector(31 downto 0);
begin
-----------------------------------------------------------------------------
-- set OP1in
-----------------------------------------------------------------------------
process (OP2out, reg_QB, opcode, OP1out, OP1in, exe_datatype, addsub_q, execOPC, exec,
pack_out, bcd_a, bcd_s, result_mulu, result_div, exe_condition, bf_offset, bf_width,
Flags, FlagsSR, bits_out, exec_tas, rot_out, exe_opcode, result, bf_fffo, bf_firstbit, bf_datareg)
begin
ALUout <= OP1in;
ALUout(7) <= OP1in(7) OR exec_tas;
if exec(opcBFwb) = '1' then
ALUout <= result(31 downto 0);
if bf_fffo = '1' then
ALUout <= bf_offset + bf_width + 1 - bf_firstbit;
end if;
end if;
OP1in <= addsub_q;
if exec(opcABCD) = '1' then
OP1in(7 downto 0) <= bcd_a(7 downto 0);
elsif exec(opcSBCD) = '1' then
OP1in(7 downto 0) <= bcd_s(7 downto 0);
elsif exec(opcMULU) = '1' and MUL_Mode /= 3 then
if exec(write_lowlong) = '1' and (MUL_Mode = 1 OR MUL_Mode = 2) then
OP1in <= result_mulu(31 downto 0);
else
OP1in <= result_mulu(63 downto 32);
end if;
elsif exec(opcDIVU) = '1' and DIV_Mode /= 3 then
if exe_opcode(15) = '1' OR DIV_Mode = 0 then
-- if exe_opcode(15)='1' then
OP1in <= result_div(47 downto 32) & result_div(15 downto 0);
else --64bit
if exec(write_reminder) = '1' then
OP1in <= result_div(63 downto 32);
else
OP1in <= result_div(31 downto 0);
end if;
end if;
elsif exec(opcOR) = '1' then
OP1in <= OP2out OR OP1out;
elsif exec(opcand) = '1' then
OP1in <= OP2out and OP1out;
elsif exec(opcScc) = '1' then
OP1in(7 downto 0) <= (others => exe_condition);
elsif exec(opcEOR) = '1' then
OP1in <= OP2out xor OP1out;
elsif exec(opcMOVE) = '1' OR exec(exg) = '1' then
-- OP1in <= OP2out(31 downto 8)&(OP2out(7)OR exec_tas)&OP2out(6 downto 0);
OP1in <= OP2out;
elsif exec(opcROT) = '1' then
OP1in <= rot_out;
elsif exec(opcSWAP) = '1' then
OP1in <= OP1out(15 downto 0) & OP1out(31 downto 16);
elsif exec(opcBITS) = '1' then
OP1in <= bits_out;
elsif exec(opcBF) = '1' then
OP1in <= bf_datareg;
elsif exec(opcMOVECCR) = '1' then
OP1in(15 downto 8) <= "00000000";
OP1in( 7 downto 0) <= Flags;
elsif exec(opcMOVESR) = '1' then
OP1in(15 downto 8) <= FlagsSR;
OP1in( 7 downto 0) <= Flags;
elsif exec(opcPACK) = '1' then
OP1in(15 downto 0) <= pack_out;
end if;
end process;
-----------------------------------------------------------------------------
-- addsub
-----------------------------------------------------------------------------
process (OP1out, OP2out, execOPC, datatype, Flags, long_start, non_aligned, movem_presub, exe_datatype, exec, addsub_a, addsub_b, opaddsub,
notaddsub_b, add_result, c_in, sndOPC)
begin
addsub_a <= OP1out;
if exec(get_bfoffset) = '1' then
if sndOPC(11) = '1' then
addsub_a <= OP1out(31) & OP1out(31) & OP1out(31) & OP1out(31 downto 3);
else
addsub_a <= "000000000000000000000000000000" & sndOPC(10 downto 9);
end if;
end if;
if exec(subidx) = '1' then
opaddsub <= '1';
else
opaddsub <= '0';
end if;
c_in(0) <= '0';
addsub_b <= OP2out;
if execOPC = '0' and exec(OP2out_one) = '0' and exec(get_bfoffset) = '0' then
if long_start = '0' and datatype = "00" and exec(use_SP) = '0' then
addsub_b <= "00000000000000000000000000000001";
elsif long_start = '0' and exe_datatype = "10" and (exec(presub) OR exec(postadd) OR movem_presub) = '1' then
if exec(movem_action) = '1' then -- used for initial offset / aligned case
addsub_b <= "00000000000000000000000000000110";
else
addsub_b <= "00000000000000000000000000000100";
end if;
else
addsub_b <= "00000000000000000000000000000010";
end if;
else
if (exec(use_XZFlag) = '1' and Flags(4) = '1') OR exec(opcCHK) = '1' then
c_in(0) <= '1';
end if;
opaddsub <= exec(addsub);
end if;
-- patch for un-aligned movem
if (exec(movem_action) = '1') then
if (movem_presub = '0') then -- up
if (non_aligned = '1') and (long_start = '0') then -- hold
addsub_b <= (others => '0');
end if;
else
if (non_aligned = '1') and (long_start = '0') then
if (exe_datatype = "10") then
addsub_b <= "00000000000000000000000000001000";
else
addsub_b <= "00000000000000000000000000000100";
end if;
end if;
end if;
end if;
if opaddsub = '0' OR long_start = '1' then --ADD
notaddsub_b <= '0' & addsub_b & c_in(0);
else --SUB
notaddsub_b <= not ('0' & addsub_b & c_in(0));
end if;
add_result <= (('0' & addsub_a & notaddsub_b(0)) + notaddsub_b);
c_in(1) <= add_result(9) xor addsub_a(8) xor addsub_b(8);
c_in(2) <= add_result(17) xor addsub_a(16) xor addsub_b(16);
c_in(3) <= add_result(33);
addsub_q <= add_result(32 downto 1);
addsub_ofl(0) <= (c_in(1) xor add_result(8) xor addsub_a(7) xor addsub_b(7)); --V Byte
addsub_ofl(1) <= (c_in(2) xor add_result(16) xor addsub_a(15) xor addsub_b(15)); --V Word
addsub_ofl(2) <= (c_in(3) xor add_result(32) xor addsub_a(31) xor addsub_b(31)); --V Long
c_out <= c_in(3 downto 1);
end process;
------------------------------------------------------------------------------
--ALU
------------------------------------------------------------------------------
process (OP1out, OP2out, pack_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, Flags)
begin
if exe_opcode(7 downto 6) = "01" then
-- PACK
pack_a <= std_logic_vector(unsigned(OP1out(15 downto 0)) + unsigned(OP2out(15 downto 0)));
pack_out <= "00000000" & pack_a(11 downto 8) & pack_a(3 downto 0);
else
-- UNPK
pack_a <= "0000" & OP2out(7 downto 4) & "0000" & OP2out(3 downto 0);
pack_out <= std_logic_vector(unsigned(OP1out(15 downto 0)) + unsigned(pack_a));
end if;
--BCD_ARITH-------------------------------------------------------------------
--ADC
bcd_a <= niba_hc & (niba_h(4 downto 1) + ('0', niba_hc, niba_hc, '0')) & (niba_l(4 downto 1) + ('0', niba_lc, niba_lc, '0'));
niba_l <= ('0' & OP1out(3 downto 0) & '1') + ('0' & OP2out(3 downto 0) & Flags(4));
niba_lc <= niba_l(5) OR (niba_l(4) and niba_l(3)) OR (niba_l(4) and niba_l(2));
niba_h <= ('0' & OP1out(7 downto 4) & '1') + ('0' & OP2out(7 downto 4) & niba_lc);
niba_hc <= niba_h(5) OR (niba_h(4) and niba_h(3)) OR (niba_h(4) and niba_h(2));
--SBC
bcd_s <= nibs_hc & (nibs_h(4 downto 1) - ('0', nibs_hc, nibs_hc, '0')) & (nibs_l(4 downto 1) - ('0', nibs_lc, nibs_lc, '0'));
nibs_l <= ('0' & OP1out(3 downto 0) & '0') - ('0' & OP2out(3 downto 0) & Flags(4));
nibs_lc <= nibs_l(5);
nibs_h <= ('0' & OP1out(7 downto 4) & '0') - ('0' & OP2out(7 downto 4) & nibs_lc);
nibs_hc <= nibs_h(5);
end process;
-----------------------------------------------------------------------------
-- Bits
-----------------------------------------------------------------------------
process (clk, exe_opcode, OP1out, OP2out, one_bit_in, bchg, bset, bit_Number, sndOPC, reg_QB)
begin
if rising_edge(clk) then
if clkena_lw = '1' then
bchg <= '0';
bset <= '0';
case opcode(7 downto 6) IS
when "01" => --bchg
bchg <= '1';
when "11" => --bset
bset <= '1';
when others => NULL;
end case;
end if;
end if;
if exe_opcode(8) = '0' then
if exe_opcode(5 downto 4) = "00" then
bit_number <= sndOPC(4 downto 0);
else
bit_number <= "00" & sndOPC(2 downto 0);
end if;
else
if exe_opcode(5 downto 4) = "00" then
bit_number <= reg_QB(4 downto 0);
else
bit_number <= "00" & reg_QB(2 downto 0);
end if;
end if;
one_bit_in <= OP1out(to_integer(unsigned(bit_Number)));
bits_out <= OP1out;
bits_out(to_integer(unsigned(bit_Number))) <= (bchg and not one_bit_in) OR bset;
end process;
-----------------------------------------------------------------------------
-- Bit Field
-----------------------------------------------------------------------------
-- Bitfields can have up to four (register) operands, e.g. bfins d0,d1{d2,d3}
-- the width an offset operands are evaluated while the second opcode word is
-- evaluated. These values are latched, so the two other registers can be read
-- in the next cycle while the ALU is working since the tg68k can only read
-- from two registers at once.
--
-- All bitfield operations can operate on registers or memory. There are
-- two fundamental differences which make the shifters quite complex:
-- 1. Memory content is delivered byte aligned to the ALU. Thus all shifting
-- is 7 bits far at most. Registers are 32 bit in size and may require
-- shifting of up to 31 bit positions
-- 2. Memory operations can affect 5 bytes. Thus all shifting is 40 bit in that
-- case. Registers are 32 bit in size and bitfield operations wrap. Shifts
-- are actually rotations for that reason
--
-- The destination operand is transfered via op1out and bf_ext into the ALU.
--
-- bftst, bfset, bfclr and bfchg
--------------------------------
-- bftst, bfset, bfclr and bfchg work very similar. A "sign" vector is generated
-- having "width" right aligned 0-bits and the rest ones.
-- A "copy" vector is generated from this by shifting through copymux so
-- this contains a 1 for all bits in bf_ext_in & op1out that will not be
-- affected by the operation.
-- The result vector is either all 1's (bfset), all 0's(bfclr) or the inverse
-- of bf_ext_in & op1out. Those bits in result that have a 1 in the copy
-- vector are overwritten with the original value from bf_ext_in & op1out
-- The result is returned through bf_ext_out and ALUout
--
-- These instructions only calculate the Z and N flags. Both are derived
-- directly from bf_ext_in & op1out with the help of the copy vector and
-- the offset/width fields. Thus Z and N are set from the previous contents
-- of the bitfield.
--
-- bfins
--------
-- bfins reuses most of the functionality of bfset, bfclr and bfchg. But it
-- has another 32 bit parameter that's being used for the source. This is passed
-- to the ALU via op2out. This is moved to the shift register and shifted
-- bf_shift bits to the right.
-- The input valus is also store in datareg and the lowest "width" bits
-- are masked. This is then forwarded to op1in which in turn uses the normal
-- mechanisms to generate the flags. A special bf_NFlag is also generated
-- from this. Z and N are set from these and not from the previous bitfield
-- contents as with bfset, bfclr or bfchg
--
-- bfextu/bfexts
----------------
-- bfexts and bfextu use the same shifter that is used by bfins to shift the
-- data to be inserted. It's using that same shifter to shift data in the
-- opposite direction. Flags are set from the extraced data
--
-- bfffo
--------
-- bfffo uses the same data path as bfext. But instead of directly returning
-- the extracted data it determines the highest bit setin the result
process (clk, bf_ins, bf_bchg, bf_bset, bf_exts, bf_extu, bf_set2, OP1out, OP2out, result_tmp, bf_ext_in,
datareg, bf_NFlag, result, reg_QB, sign, bf_d32, copy, bf_loffset, bf_width)
begin
if rising_edge(clk) then
if clkena_lw = '1' then
bf_bset <= '0';
bf_bchg <= '0';
bf_ins <= '0';
bf_exts <= '0';
bf_extu <= '0';
bf_fffo <= '0';
bf_d32 <= '0';
case opcode(10 downto 8) IS
when "010" => bf_bchg <= '1'; --BFCHG
when "011" => bf_exts <= '1'; --BFEXTS
when "001" => bf_extu <= '1'; --BFEXTU
-- when "100" => insert <= (others =>'0'); --BFCLR
when "101" => bf_fffo <= '1'; --BFFFO
when "110" => bf_bset <= '1'; --BFSET
when "111" => bf_ins <= '1'; --BFinS
when others => NULL;
end case;
-- ea is a register
if opcode(4 downto 3) = "00" then
bf_d32 <= '1';
end if;
bf_ext_out <= result(39 downto 32);
end if;
end if;
------------- BF_SET2 --------------
if bf_ins = '1' then
bf_loff_dir <= 32 - bf_loffset;
else
bf_loff_dir <= bf_loffset;
end if;
if bf_d32 = '1' then
-- 32bit: rotate 0..31 bits left or right, don't care for upper 8 bits
bf_set2 <= "--------" & std_logic_vector(unsigned(OP2out) ror to_integer(unsigned(bf_loff_dir)));
else
if bf_ins = '1' then
-- 40 bit: shift 0..7 bits left
bf_set2 <= std_logic_vector(unsigned(bf_ext_in & OP2out) sll to_integer(unsigned(bf_loffset(2 downto 0))));
else
-- 40 bit: shift 0..7 bits right
bf_set2 <= std_logic_vector(unsigned(bf_ext_in & OP2out) srl to_integer(unsigned(bf_loffset(2 downto 0))));
end if;
end if;
------------- COPY --------------
if bf_d32 = '1' then
-- 32bit: rotate 32 bits 0..31 bits left, don't care for upper 8 bits
copy <= "--------" & std_logic_vector(unsigned(sign) rol to_integer(unsigned(bf_loffset)));
else
-- 40 bit: shift 40 bits 0..7 bits left, fill with '1's (hence the two not's)
copy <= not std_logic_vector(unsigned(x"00" & (not sign)) sll to_integer(unsigned(bf_loffset(2 downto 0))));
end if;
if bf_ins = '1' then
datareg <= reg_QB;
else
datareg <= bf_set2(31 downto 0);
end if;
-- do the bitfield operation itself
if bf_ins = '1' then
result <= bf_set2;
elsif bf_bchg = '1' then
result <= not (bf_ext_in & OP1out);
elsif bf_bset = '1' then
result <= (others => '1');
else
result <= (others => '0');
end if;
sign <= (others => '0');
bf_NFlag <= datareg(to_integer(unsigned(bf_width)));
for i in 0 TO 31 loop
if i > bf_width then
datareg(i) <= '0';
sign(i) <= '1';
end if;
end loop;
-- Set bits 32..39 to 0 if operating on register to make sure
-- zero flag calculation over all 40 bits works correctly
result_tmp(31 downto 0) <= OP1out;
if bf_d32 = '1' then
result_tmp(39 downto 32) <= "00000000";
else
result_tmp(39 downto 32) <= bf_ext_in;
end if;
bf_flag_z <= '1';
if bf_d32 = '0' then
-- The test for this overflow shouldn't be needed. But GHDL complains
-- otherwise.
if(to_integer(unsigned('0' & bf_loffset)+unsigned(bf_width)) > 39) then
bf_flag_n <= result_tmp(39);
else
bf_flag_n <= result_tmp(to_integer(unsigned('0' & bf_loffset)+unsigned(bf_width)));
end if;
else
--TH: TODO: check if this really does what it's supposed to
bf_flag_n <= result_tmp(to_integer(unsigned(bf_loffset)+unsigned(bf_width)));
end if;
for i in 0 TO 39 loop
if copy(i) = '1' then
result(i) <= result_tmp(i);
elsif result_tmp(i) = '1' then
bf_flag_z <= '0';
end if;
end loop;
if bf_exts = '1' and bf_NFlag = '1' then
bf_datareg <= datareg OR sign;
else
bf_datareg <= datareg;
end if;
--BFFFO
if datareg(31) = '1' then bf_firstbit <= "100000";
elsif datareg(30) = '1' then bf_firstbit <= "011111";
elsif datareg(29) = '1' then bf_firstbit <= "011110";
elsif datareg(28) = '1' then bf_firstbit <= "011101";
elsif datareg(27) = '1' then bf_firstbit <= "011100";
elsif datareg(26) = '1' then bf_firstbit <= "011011";
elsif datareg(25) = '1' then bf_firstbit <= "011010";
elsif datareg(24) = '1' then bf_firstbit <= "011001";
elsif datareg(23) = '1' then bf_firstbit <= "011000";
elsif datareg(22) = '1' then bf_firstbit <= "010111";
elsif datareg(21) = '1' then bf_firstbit <= "010110";
elsif datareg(20) = '1' then bf_firstbit <= "010101";
elsif datareg(19) = '1' then bf_firstbit <= "010100";
elsif datareg(18) = '1' then bf_firstbit <= "010011";
elsif datareg(17) = '1' then bf_firstbit <= "010010";
elsif datareg(16) = '1' then bf_firstbit <= "010001";
elsif datareg(15) = '1' then bf_firstbit <= "010000";
elsif datareg(14) = '1' then bf_firstbit <= "001111";
elsif datareg(13) = '1' then bf_firstbit <= "001110";
elsif datareg(12) = '1' then bf_firstbit <= "001101";
elsif datareg(11) = '1' then bf_firstbit <= "001100";
elsif datareg(10) = '1' then bf_firstbit <= "001011";
elsif datareg(9) = '1' then bf_firstbit <= "001010";
elsif datareg(8) = '1' then bf_firstbit <= "001001";
elsif datareg(7) = '1' then bf_firstbit <= "001000";
elsif datareg(6) = '1' then bf_firstbit <= "000111";
elsif datareg(5) = '1' then bf_firstbit <= "000110";
elsif datareg(4) = '1' then bf_firstbit <= "000101";
elsif datareg(3) = '1' then bf_firstbit <= "000100";
elsif datareg(2) = '1' then bf_firstbit <= "000011";
elsif datareg(1) = '1' then bf_firstbit <= "000010";
elsif datareg(0) = '1' then bf_firstbit <= "000001";
else bf_firstbit <= "000000";
end if;
end process;
-----------------------------------------------------------------------------
-- Rotation
-----------------------------------------------------------------------------
process (exe_opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, exec)
begin
case exe_opcode(7 downto 6) IS
when "00" => --Byte
rot_rot <= OP1out(7);
when "01" | "11" => --Word
rot_rot <= OP1out(15);
when "10" => --Long
rot_rot <= OP1out(31);
when others => NULL;
end case;
case rot_bits IS
when "00" => --ASL, ASR
rot_lsb <= '0';
rot_msb <= rot_rot;
when "01" => --LSL, LSR
rot_lsb <= '0';
rot_msb <= '0';
when "10" => --ROXL, ROXR
rot_lsb <= Flags(4);
rot_msb <= Flags(4);
when "11" => --ROL, ROR
rot_lsb <= rot_rot;
rot_msb <= OP1out(0);
when others => NULL;
end case;
if exec(rot_nop) = '1' then
rot_out <= OP1out;
rot_X <= Flags(4);
if rot_bits = "10" then --ROXL, ROXR
rot_C <= Flags(4);
else
rot_C <= '0';
end if;
else
if exe_opcode(8) = '1' then --left
rot_out <= OP1out(30 downto 0) & rot_lsb;
rot_X <= rot_rot;
rot_C <= rot_rot;
else --right
rot_X <= OP1out(0);
rot_C <= OP1out(0);
rot_out <= rot_msb & OP1out(31 downto 1);
case exe_opcode(7 downto 6) IS
when "00" => --Byte
rot_out(7) <= rot_msb;
when "01" | "11" => --Word
rot_out(15) <= rot_msb;
when others => NULL;
end case;
end if;
end if;
end process;
------------------------------------------------------------------------------
--CCR op
------------------------------------------------------------------------------
process (clk, Reset, exe_opcode, exe_datatype, Flags, last_data_read, OP2out, flag_z, OP1in, c_out, addsub_ofl,
bcd_s, bcd_a, exec)
begin
if exec(andiSR) = '1' then
CCRin <= Flags and last_data_read(7 downto 0);
elsif exec(eoriSR) = '1' then
CCRin <= Flags xor last_data_read(7 downto 0);
elsif exec(oriSR) = '1' then
CCRin <= Flags OR last_data_read(7 downto 0);
else
CCRin <= OP2out(7 downto 0);
end if;
------------------------------------------------------------------------------
--Flags
------------------------------------------------------------------------------
flag_z <= "000";
if exec(use_XZFlag) = '1' and flags(2) = '0' then
flag_z <= "000";
elsif OP1in(7 downto 0) = "00000000" then
flag_z(0) <= '1';
if OP1in(15 downto 8) = "00000000" then
flag_z(1) <= '1';
if OP1in(31 downto 16) = "0000000000000000" then
flag_z(2) <= '1';
end if;
end if;
end if;
-- --Flags NZVC
if exe_datatype = "00" then --Byte
set_flags <= OP1in(7) & flag_z(0) & addsub_ofl(0) & c_out(0);
if exec(opcABCD) = '1' then
set_flags(0) <= bcd_a(8);
elsif exec(opcSBCD) = '1' then
set_flags(0) <= bcd_s(8);
end if;
elsif exe_datatype = "10" OR exec(opcCPMAW) = '1' then --Long
set_flags <= OP1in(31) & flag_z(2) & addsub_ofl(2) & c_out(2);
else --Word
set_flags <= OP1in(15) & flag_z(1) & addsub_ofl(1) & c_out(1);
end if;
if rising_edge(clk) then
if clkena_lw = '1' then
if exec(directSR) = '1' OR set_stop = '1' then
Flags(7 downto 0) <= data_read(7 downto 0);
end if;
if exec(directCCR) = '1' then
Flags(7 downto 0) <= data_read(7 downto 0);
end if;
if exec(opcROT) = '1' then
asl_VFlag <= ((set_flags(3) xor rot_rot) OR asl_VFlag);
else
asl_VFlag <= '0';
end if;
if exec(to_CCR) = '1' then
Flags(7 downto 0) <= CCRin(7 downto 0); --CCR
elsif Z_error = '1' then
if exe_opcode(8) = '0' then
Flags(3 downto 0) <= reg_QA(31) & "000";
else
Flags(3 downto 0) <= "0100";
end if;
elsif exec(no_Flags) = '0' then
if exec(opcADD) = '1' then
Flags(4) <= set_flags(0);
elsif exec(opcROT) = '1' and rot_bits /= "11" and exec(rot_nop) = '0' then
Flags(4) <= rot_X;
end if;
if (exec(opcADD) OR exec(opcCMP)) = '1' then
Flags(3 downto 0) <= set_flags;
elsif exec(opcDIVU) = '1' and DIV_Mode /= 3 then
if V_Flag = '1' then
Flags(3 downto 0) <= "1010";
else
Flags(3 downto 0) <= OP1in(15) & flag_z(1) & "00";
end if;
elsif exec(write_reminder) = '1' and MUL_Mode /= 3 then -- z-flag MULU.l
Flags(3) <= set_flags(3);
Flags(2) <= set_flags(2) and Flags(2);
Flags(1) <= '0';
Flags(0) <= '0';
elsif exec(write_lowlong) = '1' and (MUL_Mode = 1 OR MUL_Mode = 2) then -- flag MULU.l
Flags(3) <= set_flags(3);
Flags(2) <= set_flags(2);
Flags(1) <= set_mV_Flag; --V
Flags(0) <= '0';
elsif exec(opcOR) = '1' OR exec(opcand) = '1' OR exec(opcEOR) = '1' OR exec(opcMOVE) = '1' OR exec(opcMOVEQ) = '1' OR exec(opcSWAP) = '1' OR exec(opcBF) = '1' OR (exec(opcMULU) = '1' and MUL_Mode /= 3) then
Flags(1 downto 0) <= "00";
Flags(3 downto 2) <= set_flags(3 downto 2);
if exec(opcBF) = '1' then
-- flags(2) has correctly been set from set_flags
Flags(3) <= bf_NFlag;
--TH TODO: check flag handling of fffo
-- "normal" flags are taken from op2in
if bf_fffo = '0' and bf_extu='0' and bf_exts='0' and bf_ins='0' then
Flags(2) <= bf_flag_z;
Flags(3) <= bf_flag_n;
end if;
end if;
elsif exec(opcROT) = '1' then
Flags(3 downto 2) <= set_flags(3 downto 2);
Flags(0) <= rot_C;
if rot_bits = "00" and ((set_flags(3) xor rot_rot) OR asl_VFlag) = '1' then --ASL/ASR
Flags(1) <= '1';
else
Flags(1) <= '0';
end if;
elsif exec(opcBITS) = '1' then
Flags(2) <= not one_bit_in;
elsif exec(opcCHK) = '1' then
if exe_datatype = "01" then --Word
Flags(3) <= OP1out(15);
else
Flags(3) <= OP1out(31);
end if;
if OP1out(15 downto 0) = X"0000" and (exe_datatype = "01" OR OP1out(31 downto 16) = X"0000") then
Flags(2) <= '1';
else
Flags(2) <= '0';
end if;
Flags(1 downto 0) <= "00";
end if;
end if;
end if;
Flags(7 downto 5) <= "000";
end if;
end process;
-------------------------------------------------------------------------------
---- MULU/MULS
-------------------------------------------------------------------------------
process (exe_opcode, OP2out, muls_msb, mulu_reg, FAsign, mulu_sign, reg_QA, faktorB, result_mulu, signedOP)
begin
if (signedOP = '1' and faktorB(31) = '1') OR FAsign = '1' then
muls_msb <= mulu_reg(63);
else
muls_msb <= '0';
end if;
if signedOP = '1' and faktorB(31) = '1' then
mulu_sign <= '1';
else
mulu_sign <= '0';
end if;
if MUL_Mode = 0 then -- 16 Bit
result_mulu(63 downto 32) <= muls_msb & mulu_reg(63 downto 33);
result_mulu(15 downto 0) <= 'X' & mulu_reg(15 downto 1);
if mulu_reg(0) = '1' then
if FAsign = '1' then
result_mulu(63 downto 47) <= (muls_msb & mulu_reg(63 downto 48) - (mulu_sign & faktorB(31 downto 16)));
else
result_mulu(63 downto 47) <= (muls_msb & mulu_reg(63 downto 48) + (mulu_sign & faktorB(31 downto 16)));
end if;
end if;
else -- 32 Bit
result_mulu <= muls_msb & mulu_reg(63 downto 1);
if mulu_reg(0) = '1' then
if FAsign = '1' then
result_mulu(63 downto 31) <= (muls_msb & mulu_reg(63 downto 32) - (mulu_sign & faktorB));
else
result_mulu(63 downto 31) <= (muls_msb & mulu_reg(63 downto 32) + (mulu_sign & faktorB));
end if;
end if;
end if;
if exe_opcode(15) = '1' OR MUL_Mode = 0 then
faktorB(31 downto 16) <= OP2out(15 downto 0);
faktorB(15 downto 0) <= (others => '0');
else
faktorB <= OP2out;
end if;
if (result_mulu(63 downto 32) = X"00000000" and (signedOP = '0' OR result_mulu(31) = '0')) OR
(result_mulu(63 downto 32) = X"FFFFFFFF" and signedOP = '1' and result_mulu(31) = '1') then
set_mV_Flag <= '0';
else
set_mV_Flag <= '1';
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if clkena_lw = '1' then
if micro_state = mul1 then
mulu_reg(63 downto 32) <= (others => '0');
if divs = '1' and ((exe_opcode(15) = '1' and reg_QA(15) = '1') OR (exe_opcode(15) = '0' and reg_QA(31) = '1')) then --MULS Neg faktor
FAsign <= '1';
mulu_reg(31 downto 0) <= 0 - reg_QA;
else
FAsign <= '0';
mulu_reg(31 downto 0) <= reg_QA;
end if;
elsif exec(opcMULU) = '0' then
mulu_reg <= result_mulu;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------
---- DIVU/DIVS
-------------------------------------------------------------------------------
process (execOPC, OP1out, OP2out, div_reg, div_neg, div_bit, div_sub, div_quot, OP1_sign, div_over, result_div, reg_QA, opcode, sndOPC, divs, exe_opcode, reg_QB,
signedOP, nozero, div_qsign, OP2outext)
begin
divs <= (opcode(15) and opcode(8)) OR (not opcode(15) and sndOPC(11));
divisor(15 downto 0) <= (others => '0');
divisor(63 downto 32) <= (others => divs and reg_QA(31));
if exe_opcode(15) = '1' OR DIV_Mode = 0 then
divisor(47 downto 16) <= reg_QA;
else
divisor(31 downto 0) <= reg_QA;
if exe_opcode(14) = '1' and sndOPC(10) = '1' then
divisor(63 downto 32) <= reg_QB;
end if;
end if;
if signedOP = '1' OR opcode(15) = '0' then
OP2outext <= OP2out(31 downto 16);
else
OP2outext <= (others => '0');
end if;
if signedOP = '1' and OP2out(31) = '1' then
div_sub <= (div_reg(63 downto 31)) + ('1' & OP2out(31 downto 0));
else
div_sub <= (div_reg(63 downto 31)) - ('0' & OP2outext(15 downto 0) & OP2out(15 downto 0));
end if;
if DIV_Mode = 0 then
div_bit <= div_sub(16);
else
div_bit <= div_sub(32);
end if;
if div_bit = '1' then
div_quot(63 downto 32) <= div_reg(62 downto 31);
else
div_quot(63 downto 32) <= div_sub(31 downto 0);
end if;
div_quot(31 downto 0) <= div_reg(30 downto 0) & not div_bit;
if ((nozero = '1' and signedOP = '1' and (OP2out(31) xor OP1_sign xor div_neg xor div_qsign) = '1' ) --Overflow DIVS
OR (signedOP = '0' and div_over(32) = '0')) and DIV_Mode /= 3 then --Overflow DIVU
set_V_Flag <= '1';
else
set_V_Flag <= '0';
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if clkena_lw = '1' then
V_Flag <= set_V_Flag;
signedOP <= divs;
if micro_state = div1 then
nozero <= '0';
if divs = '1' and divisor(63) = '1' then -- Neg divisor
OP1_sign <= '1';
div_reg <= 0 - divisor;
else
OP1_sign <= '0';
div_reg <= divisor;
end if;
else
div_reg <= div_quot;
nozero <= not div_bit OR nozero;
end if;
if micro_state = div2 then
div_qsign <= not div_bit;
div_neg <= signedOP and (OP2out(31) xor OP1_sign);
if DIV_Mode = 0 then
div_over(32 downto 16) <= ('0' & div_reg(47 downto 32)) - ('0' & OP2out(15 downto 0));
else
div_over <= ('0' & div_reg(63 downto 32)) - ('0' & OP2out);
end if;
end if;
if exec(write_reminder) = '0' then
-- if exec_DIVU='0' then
if div_neg = '1' then
result_div(31 downto 0) <= 0 - div_quot(31 downto 0);
else
result_div(31 downto 0) <= div_quot(31 downto 0);
end if;
if OP1_sign = '1' then
result_div(63 downto 32) <= 0 - div_quot(63 downto 32);
else
result_div(63 downto 32) <= div_quot(63 downto 32);
end if;
end if;
end if;
end if;
end process;
set_V_Flag_out <= set_V_Flag;
Flags_out <= Flags;
c_out_out <= c_out;
addsub_q_out <= addsub_q;
end;
| gpl-3.0 | ceef9e2a36ab90af7e11825692cc2ef9 | 0.539751 | 3.144003 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4088/FIFO2Elink.vhd | 1 | 6,301 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 17/08/2015
--! Module Name: FIFO2Elink
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
--! consists of 1 E-path
entity FIFO2Elink is
generic (
OutputDataRate : integer := 80 -- 80 or 160 MHz
);
port (
clk40 : in std_logic;
clk80 : in std_logic;
clk160 : in std_logic;
RSTclk40 : in std_logic;
------
efifoDin : in std_logic_vector (17 downto 0); -- [data_code,2bit][data,16bit]
efifoWe : in std_logic;
efifoPfull : out std_logic;
efifoWclk : in std_logic;
------
DATA1bitOUT : out std_logic
------
);
end FIFO2Elink;
architecture Behavioral of FIFO2Elink is
----------------------------------
----------------------------------
component upstreamEpathFifoWrap
port (
rst : in std_logic;
fifoRstState : out std_logic;
---
wr_clk : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(17 downto 0);
---
rd_clk : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(9 downto 0);
doutRdy : out std_logic;
---
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
prog_full : out std_logic
);
end component upstreamEpathFifoWrap;
----------------------------------
----------------------------------
component EPROC_OUT2
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
getDataTrig : out std_logic; -- @ bitCLKx4
ENCODING : in std_logic_vector (3 downto 0);
EDATA_OUT : out std_logic_vector (1 downto 0);
TTCin : in std_logic_vector (1 downto 0);
DATA_IN : in std_logic_vector (9 downto 0);
DATA_RDY : in std_logic
);
end component;
----------------------------------
----------------------------------
component EPROC_OUT4
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
getDataTrig : out std_logic; -- @ bitCLKx4
ENCODING : in std_logic_vector (3 downto 0);
EDATA_OUT : out std_logic_vector (3 downto 0);
TTCin : in std_logic_vector (4 downto 0);
DATA_IN : in std_logic_vector (9 downto 0);
DATA_RDY : in std_logic
);
end component;
----------------------------------
----------------------------------
----
signal efifoRE, doutRdy : std_logic;
signal efifoDout : std_logic_vector(9 downto 0);
signal dout2bit, dout2bit_r : std_logic_vector(1 downto 0);
signal bitCount1 : std_logic := '0';
signal dout4bit, dout4bit_r : std_logic_vector(3 downto 0);
signal bitCount2 : std_logic_vector(1 downto 0) := "00";
----
begin
------------------------------------------------------------
-- EPATH_FIFO
------------------------------------------------------------
UEF: upstreamEpathFifoWrap
port map(
rst => RSTclk40,
fifoRstState => open,
---
wr_clk => efifoWclk,
wr_en => efifoWe,
din => efifoDin,
---
rd_clk => clk160,
rd_en => efifoRE,
dout => efifoDout,
doutRdy => doutRdy,
---
full => open,
almost_full => efifoPfull,
empty => open,
prog_full => open
);
--
------------------------------------------------------------
-- E-PATH case 80 MHz
------------------------------------------------------------
OutputDataRate80: if OutputDataRate = 80 generate
EPROC_OUT2bit: EPROC_OUT2
port map(
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => RSTclk40,
ENA => '1',
getDataTrig => efifoRE,
ENCODING => "10", -- 8b10b
EDATA_OUT => dout2bit, -- @ 40MHz
TTCin => "00", -- not in use
DATA_IN => efifoDout,
DATA_RDY => doutRdy
);
---
process(clk80)
begin
if clk80'event and clk80 = '1' then
bitCount1 <= not bitCount1;
end if;
end process;
--
process(clk80)
begin
if clk80'event and clk80 = '1' then
if bitCount1 = '0' then
dout2bit_r <= dout2bit(1);
end if;
end if;
end process;
---
process(clk80)
begin
if clk80'event and clk80 = '1' then
if bitCount1 = '0' then
DATA1bitOUT <= dout2bit(0);
else
DATA1bitOUT <= dout2bit_r(1);
end if;
end if;
end process;
---
end generate OutputDataRate80;
------------------------------------------------------------
-- E-PATH case 160 MHz
------------------------------------------------------------
OutputDataRate160: if OutputDataRate = 160 generate
EPROC_OUT4bit: EPROC_OUT4
PORT MAP(
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => RSTclk40,
ENA => '1',
getDataTrig => efifoRE,
ENCODING => "10", -- 8b10b
EDATA_OUT => dout4bit, -- @ 40MHz
TTCin => "00000", -- not in use
DATA_IN => efifoDout,
DATA_RDY => doutRdy
);
---
process(clk160)
begin
if clk160'event and clk160 = '1' then
bitCount2 <= bitCount2 + 1;
end if;
end process;
--
process(clk160)
begin
if clk160'event and clk160 = '1' then
if bitCount2 = "00" then
dout4bit_r <= dout4bit;
end if;
end if;
end process;
---
process(clk80)
begin
if clk160'event and clk160 = '1' then
case bitCount2 is
when "00" => DATA1bitOUT <= dout4bit(0);
when "01" => DATA1bitOUT <= dout4bit_r(1);
when "10" => DATA1bitOUT <= dout4bit_r(2);
when "11" => DATA1bitOUT <= dout4bit_r(3);
when others =>
end case;
end if;
end process;
---
end generate OutputDataRate160;
end Behavioral;
| gpl-3.0 | 22fd2a8dcb72a286210bd6734d7e7ade | 0.475321 | 3.578081 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Pulse_Extender/pulse_extender.vhd | 1 | 3,995 | ----------------------------------------------------------------------------------------------------
-- Pulse Extender
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
----------------------------------------------------------------------------------------------------
-- PACKAGE
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package pulse_extender_pkg is
component pulse_extender is
generic( EXTEND_COUNT : natural := 0;
ACTIVE_LEVEL : std_logic := '1';
RESET_LEVEL : std_logic := '0');
port( clk : in std_logic;
rst : in std_logic;
pulse : in std_logic;
extended_pulse : out std_logic);
end component;
end package;
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.reduce_pkg.all;
--This entity takes an input pulse and extends its active state for the specified durations.
entity pulse_extender is
generic( --The number of clock cycles to keep the pulse in the active state
EXTEND_COUNT : natural := 0;
--The active level of the pulse, use '1' for active high and '0' for active low
ACTIVE_LEVEL : std_logic := '1';
--The active level of the pulse during the modules reset. Useful for initialization
--reset sequences
RESET_LEVEL : std_logic := '0');
port( --The clock driving the module
clk : in std_logic;
--Active High. Resets the module
rst : in std_logic;
--The input pulse. When the pulse leaves the active state, the module will hold the
--active state for the amount specified in EXTEND_COUNT.
pulse : in std_logic;
--The output extended pulse.
extended_pulse : out std_logic);
end pulse_extender;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture behave of pulse_extender is
--This register will contain the past history of the input pulse
signal shift_reg : std_logic_vector(0 to EXTEND_COUNT) := (others => RESET_LEVEL);
alias data_in : std_logic is shift_reg(0);
alias history : std_logic_vector(0 to EXTEND_COUNT-1) is shift_reg(1 to EXTEND_COUNT);
begin
--Shifting the input through the pulse history
shifter: process(clk, rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
data_in <= RESET_LEVEL;
shift_reg <= (others => '0');
else
--copying the pulse into the shift register
data_in <= pulse;
--right shifting the shift register
history <= shift_reg(history'range);
end if;
end if;
end process;
--Determine if the history has any pulse in it. If it does, then we are still holding the
--extended pulse
active_high : if(ACTIVE_LEVEL = '1') generate
extend_check_high : reduce_or
port map( data => shift_reg,
result => extended_pulse);
end generate;
active_low : if(ACTIVE_LEVEL = '0') generate
extend_check_low : reduce_and
port map( data => shift_reg,
result => extended_pulse);
end generate;
end behave;
| mit | 2505d7f5fa5bfecd9e4328ff89d3a441 | 0.445307 | 5.195059 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/IPv4.vhd | 2 | 6,599 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP RX and TX
-- doesnt handle seg & reass
-- dest MAC addr resolution through ARP layer
-- Handle IPv4 protocol
-- Respond to ARP requests and replies
-- Ignore pkts that are not IP
-- Ignore pkts that are not addressed to us--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Revision 0.03 - Added mac_data_out_first
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity IPv4 is
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system control signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- system status signals
rx_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer RX signals
mac_data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in std_logic; -- indicates data_in valid on clock
mac_data_in_last : in std_logic; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
end IPv4;
architecture structural of IPv4 is
COMPONENT IPv4_TX
PORT(
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
-- system signals
clk : in std_logic; -- same clock used to clock mac data and ip data
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
END COMPONENT;
COMPONENT IPv4_RX
PORT(
-- IP Layer signals
ip_rx : out ipv4_rx_type;
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
-- system signals
clk : in std_logic;
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
rx_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- MAC layer RX signals
mac_data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in std_logic; -- indicates data_in valid on clock
mac_data_in_last : in std_logic -- indicates last data in frame
);
END COMPONENT;
begin
TX : IPv4_TX
PORT MAP (
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready=> ip_tx_data_out_ready,
clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
arp_req_req => arp_req_req,
arp_req_rslt => arp_req_rslt,
mac_tx_req => mac_tx_req,
mac_tx_granted => mac_tx_granted,
mac_data_out_ready => mac_data_out_ready,
mac_data_out_valid => mac_data_out_valid,
mac_data_out_first => mac_data_out_first,
mac_data_out_last => mac_data_out_last,
mac_data_out => mac_data_out
);
RX : IPv4_RX
PORT MAP (
ip_rx => ip_rx,
ip_rx_start => ip_rx_start,
clk => rx_clk,
reset => reset,
our_ip_address => our_ip_address,
rx_pkt_count => rx_pkt_count,
mac_data_in => mac_data_in,
mac_data_in_valid => mac_data_in_valid,
mac_data_in_last => mac_data_in_last
);
end structural;
| gpl-3.0 | 525ccee7a844f6c37a0987ebfbe3941d | 0.567359 | 3.201844 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/IPv4_TX.vhd | 1 | 23,283 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4_TX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP TX
-- doesnt handle segmentation
-- dest MAC addr resolution through ARP layer
-- Handle IPv4 protocol
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - fixed up setting of tx_result control defaults
-- Revision 0.03 - Added data_out_first
-- Revision 0.04 - Added handling of broadcast address
-- Revision 0.05 - Fix cks calc when add of high bits causes another ovf
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity IPv4_TX is
port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
-- system signals
clk : in std_logic; -- same clock used to clock mac data and ip data
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
end IPv4_TX;
architecture Behavioral of IPv4_TX is
type tx_state_type is (
IDLE,
WAIT_MAC, -- waiting for response from ARP for mac lookup
WAIT_CHN, -- waiting for tx access to MAC channel
SEND_ETH_HDR, -- sending the ethernet header
SEND_IP_HDR, -- sending the IP header
SEND_USER_DATA -- sending the users data
);
type crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END);
type count_mode_type is (RST, INCR, HOLD);
type settable_cnt_type is (RST, SET, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- Configuration
constant IP_TTL : std_logic_vector (7 downto 0) := x"80";
-- TX state variables
signal tx_state : tx_state_type;
signal tx_count : unsigned (11 downto 0);
signal tx_result_reg : std_logic_vector (1 downto 0);
signal tx_mac : std_logic_vector (47 downto 0);
signal tx_mac_chn_reqd : std_logic;
signal tx_hdr_cks : std_logic_vector (23 downto 0);
signal mac_lookup_req : std_logic;
signal crc_state : crc_state_type;
signal arp_req_ip_reg : std_logic_vector (31 downto 0);
signal mac_data_out_ready_reg : std_logic;
-- tx control signals
signal next_tx_state : tx_state_type;
signal set_tx_state : std_logic;
signal next_tx_result : std_logic_vector (1 downto 0);
signal set_tx_result : std_logic;
signal tx_mac_value : std_logic_vector (47 downto 0);
signal set_tx_mac : std_logic;
signal tx_count_val : unsigned (11 downto 0);
signal tx_count_mode : settable_cnt_type;
signal tx_data : std_logic_vector (7 downto 0);
signal set_last : std_logic;
signal set_chn_reqd : set_clr_type;
signal set_mac_lku_req : set_clr_type;
signal tx_data_valid : std_logic; -- indicates whether data is valid to tx or not
-- tx temp signals
signal total_length : std_logic_vector (15 downto 0); -- computed combinatorially from header size
function inv_if_one(s1 : std_logic_vector; en : std_logic) return std_logic_vector is
--this function inverts all the bits of a vector if
--'en' is '1'.
variable Z : std_logic_vector(s1'high downto s1'low);
begin
for i in (s1'low) to s1'high loop
Z(i) := en xor s1(i);
end loop;
return Z;
end inv_if_one; -- end function
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | Version | *Header | Service Type | Total Length including header |
-- | (4) | Length | (ignored) | (in bytes) |
-- --------------------------------------------------------------------------------------------
-- | Identification | Flags | Fragment Offset |
-- | | | (in 32 bit words) |
-- --------------------------------------------------------------------------------------------
-- | Time To Live | Protocol | Header Checksum |
-- | (ignored) | | |
-- --------------------------------------------------------------------------------------------
-- | Source IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Destination IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Options (if any - ignored) | Padding |
-- | | (if needed) |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
--
-- * - in 32 bit words
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
tx_combinatorial : process(
-- input signals
ip_tx_start, ip_tx, our_ip_address, our_mac_address, arp_req_rslt, --clk,
mac_tx_granted, mac_data_out_ready,
-- state variables
tx_state, tx_count, tx_result_reg, tx_mac, tx_mac_chn_reqd,
mac_lookup_req, tx_hdr_cks, arp_req_ip_reg, mac_data_out_ready_reg,
-- control signals
next_tx_state, set_tx_state, next_tx_result, set_tx_result, tx_mac_value, set_tx_mac, tx_count_mode,
tx_data, set_last, set_chn_reqd, set_mac_lku_req, total_length,
tx_data_valid, tx_count_val
)
begin
-- set output followers
ip_tx_result <= tx_result_reg;
mac_tx_req <= tx_mac_chn_reqd;
arp_req_req.lookup_req <= mac_lookup_req;
arp_req_req.ip <= arp_req_ip_reg;
-- set initial values for combinatorial outputs
mac_data_out_first <= '0';
case tx_state is
when SEND_ETH_HDR | SEND_IP_HDR =>
mac_data_out <= tx_data;
tx_data_valid <= mac_data_out_ready; -- generated internally
mac_data_out_last <= set_last;
when SEND_USER_DATA =>
mac_data_out <= ip_tx.data.data_out;
tx_data_valid <= ip_tx.data.data_out_valid;
mac_data_out_last <= ip_tx.data.data_out_last;
when others =>
mac_data_out <= (others => '0');
tx_data_valid <= '0'; -- not transmitting during this phase
mac_data_out_last <= '0';
end case;
mac_data_out_valid <= tx_data_valid and mac_data_out_ready;
-- set signal defaults
next_tx_state <= IDLE;
set_tx_state <= '0';
tx_count_mode <= HOLD;
tx_data <= x"00";
set_last <= '0';
set_tx_mac <= '0';
set_chn_reqd <= HOLD;
set_mac_lku_req <= HOLD;
next_tx_result <= IPTX_RESULT_NONE;
set_tx_result <= '0';
tx_count_val <= (others => '0');
tx_mac_value <= (others => '0');
-- set temp signals
total_length <= std_logic_vector(unsigned(ip_tx.hdr.data_length) + 20); -- total length = user data length + header length (bytes)
-- TX FSM
case tx_state is
when IDLE =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
tx_count_mode <= RST;
set_chn_reqd <= CLR;
if ip_tx_start = '1' then
-- check header count for error if too high
if unsigned(ip_tx.hdr.data_length) > 8980 then
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
else
next_tx_result <= IPTX_RESULT_SENDING;
set_tx_result <= '1';
-- TODO - check if we already have the mac addr for this ip, if so, bypass the WAIT_MAC state
if ip_tx.hdr.dst_ip_addr = IP_BC_ADDR then
-- for IP broadcast, dont need to look up the MAC addr
tx_mac_value <= MAC_BC_ADDR;
set_tx_mac <= '1';
next_tx_state <= WAIT_CHN;
set_tx_state <= '1';
else
-- need to req the mac address for this ip
set_mac_lku_req <= SET;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
end if;
end if;
else
set_mac_lku_req <= CLR;
end if;
when WAIT_MAC =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
set_mac_lku_req <= CLR; -- clear the request - will have been latched in the ARP layer
-- if arp_req_rslt.got_mac = '1' then
-- save the MAC we got back from the ARP lookup
tx_mac_value <= arp_req_rslt.mac;
set_tx_mac <= '1';
set_chn_reqd <= SET;
-- check for optimise when already have the channel
-- if mac_tx_granted = '1' then
-- ready to send data
next_tx_state <= SEND_ETH_HDR;
set_tx_state <= '1';
-- else
-- next_tx_state <= WAIT_CHN;
-- set_tx_state <= '1';
-- end if;
-- elsif arp_req_rslt.got_err = '1' then
-- set_mac_lku_req <= CLR;
-- next_tx_result <= IPTX_RESULT_ERR;
-- set_tx_result <= '1';
-- next_tx_state <= IDLE;
-- set_tx_state <= '1';
-- end if;
when WAIT_CHN =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_tx_granted = '1' then
-- ready to send data
next_tx_state <= SEND_ETH_HDR;
set_tx_state <= '1';
end if;
-- probably should handle a timeout here
when SEND_ETH_HDR =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_data_out_ready = '1' then
if tx_count = x"00d" then
tx_count_mode <= RST;
next_tx_state <= SEND_IP_HDR;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"000" =>
mac_data_out_first <= mac_data_out_ready;
tx_data <= tx_mac (47 downto 40); -- trg = mac from ARP lookup
when x"001" => tx_data <= tx_mac (39 downto 32);
when x"002" => tx_data <= tx_mac (31 downto 24);
when x"003" => tx_data <= tx_mac (23 downto 16);
when x"004" => tx_data <= tx_mac (15 downto 8);
when x"005" => tx_data <= tx_mac (7 downto 0);
when x"006" => tx_data <= our_mac_address (47 downto 40); -- src = our mac
when x"007" => tx_data <= our_mac_address (39 downto 32);
when x"008" => tx_data <= our_mac_address (31 downto 24);
when x"009" => tx_data <= our_mac_address (23 downto 16);
when x"00a" => tx_data <= our_mac_address (15 downto 8);
when x"00b" => tx_data <= our_mac_address (7 downto 0);
when x"00c" => tx_data <= x"08"; -- pkt type = 0800 : IP
when x"00d" => tx_data <= x"00";
when others =>
-- shouldnt get here - handle as error
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end if;
when SEND_IP_HDR =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_data_out_ready = '1' then
if tx_count = x"013" then
tx_count_val <= x"001";
tx_count_mode <= SET;
next_tx_state <= SEND_USER_DATA;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"000" => tx_data <= x"45"; -- v4, 5 words in hdr
when x"001" => tx_data <= x"00"; -- service type
when x"002" => tx_data <= total_length (15 downto 8); -- total length
when x"003" => tx_data <= total_length (7 downto 0);
when x"004" => tx_data <= x"00"; -- identification
when x"005" => tx_data <= x"00";
when x"006" => tx_data <= x"00"; -- flags and fragment offset
when x"007" => tx_data <= x"00";
when x"008" => tx_data <= IP_TTL; -- TTL
when x"009" => tx_data <= ip_tx.hdr.protocol; -- protocol
when x"00a" => tx_data <= tx_hdr_cks (15 downto 8); -- HDR checksum
when x"00b" => tx_data <= tx_hdr_cks (7 downto 0); -- HDR checksum
when x"00c" => tx_data <= our_ip_address (31 downto 24); -- src ip
when x"00d" => tx_data <= our_ip_address (23 downto 16);
when x"00e" => tx_data <= our_ip_address (15 downto 8);
when x"00f" => tx_data <= our_ip_address (7 downto 0);
when x"010" => tx_data <= ip_tx.hdr.dst_ip_addr (31 downto 24); -- dst ip
when x"011" => tx_data <= ip_tx.hdr.dst_ip_addr (23 downto 16);
when x"012" => tx_data <= ip_tx.hdr.dst_ip_addr (15 downto 8);
when x"013" => tx_data <= ip_tx.hdr.dst_ip_addr (7 downto 0);
when others =>
-- shouldnt get here - handle as error
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end if;
when SEND_USER_DATA =>
ip_tx_data_out_ready <= mac_data_out_ready;-- and mac_data_out_ready_reg; -- in this state, we are always ready to accept user data for tx
if mac_data_out_ready = '1' then
if ip_tx.data.data_out_valid = '1' or tx_count = x"000" then
-- only increment if ready and valid has been subsequently established, otherwise data count moves on too fast
if unsigned(tx_count) = unsigned(ip_tx.hdr.data_length) then
-- TX terminated due to count - end normally
set_last <= '1';
set_chn_reqd <= CLR;
tx_data <= ip_tx.data.data_out;
next_tx_result <= IPTX_RESULT_SENT;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
if ip_tx.data.data_out_last = '0' then
next_tx_result <= IPTX_RESULT_ERR;
end if;
elsif ip_tx.data.data_out_last = '1' then
-- TX terminated due to receiving last indication from upstream - end with error
set_last <= '1';
set_chn_reqd <= CLR;
tx_data <= ip_tx.data.data_out;
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
else
-- TX continues
tx_count_mode <= INCR;
tx_data <= ip_tx.data.data_out;
end if;
end if;
end if;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
tx_sequential : process (clk)--, reset, mac_data_out_ready_reg)
begin
-- if rising_edge(clk) then
-- mac_data_out_ready_reg <= mac_data_out_ready;
-- else
-- mac_data_out_ready_reg <= mac_data_out_ready_reg;
-- end if;
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
tx_state <= IDLE;
tx_count <= x"000";
tx_result_reg <= IPTX_RESULT_NONE;
tx_mac <= (others => '0');
tx_mac_chn_reqd <= '0';
mac_lookup_req <= '0';
else
-- Next tx_state processing
if set_tx_state = '1' then
tx_state <= next_tx_state;
else
tx_state <= tx_state;
end if;
-- tx result processing
if set_tx_result = '1' then
tx_result_reg <= next_tx_result;
else
tx_result_reg <= tx_result_reg;
end if;
-- control arp lookup request
case set_mac_lku_req is
when SET =>
arp_req_ip_reg <= ip_tx.hdr.dst_ip_addr;
mac_lookup_req <= '1';
when CLR =>
mac_lookup_req <= '0';
arp_req_ip_reg <= arp_req_ip_reg;
when HOLD =>
mac_lookup_req <= mac_lookup_req;
arp_req_ip_reg <= arp_req_ip_reg;
end case;
-- save MAC
if set_tx_mac = '1' then
tx_mac <= tx_mac_value;
else
tx_mac <= tx_mac;
end if;
-- control access request to mac tx chn
case set_chn_reqd is
when SET => tx_mac_chn_reqd <= '1';
when CLR => tx_mac_chn_reqd <= '0';
when HOLD => tx_mac_chn_reqd <= tx_mac_chn_reqd;
end case;
-- tx_count processing
case tx_count_mode is
when RST => tx_count <= x"000";
when SET => tx_count <= tx_count_val;
when INCR => tx_count <= tx_count + 1;
when HOLD => tx_count <= tx_count;
end case;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Process to calculate CRC in parallel with pkt out processing
-- this process must yield a valid CRC before it is required to be used in the hdr
-----------------------------------------------------------------------------
crc : process (clk)--, reset)
begin
if rising_edge(clk) then
case crc_state is
when IDLE =>
if ip_tx_start = '1' then
tx_hdr_cks <= x"004500"; -- vers & hdr len & service
crc_state <= TOT_LEN;
end if;
when TOT_LEN =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(total_length));
crc_state <= ID;
when ID =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= FLAGS;
when FLAGS =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= TTL;
when TTL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(IP_TTL & ip_tx.hdr.protocol));
crc_state <= CKS;
when CKS =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= SAH;
when SAH =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(our_ip_address(31 downto 16)));
crc_state <= SAL;
when SAL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(our_ip_address(15 downto 0)));
crc_state <= DAH;
when DAH =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(ip_tx.hdr.dst_ip_addr(31 downto 16)));
crc_state <= DAL;
when DAL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(ip_tx.hdr.dst_ip_addr(15 downto 0)));
crc_state <= ADDOVF;
when ADDOVF =>
tx_hdr_cks <= std_logic_vector ((unsigned(tx_hdr_cks) and x"00ffff")+ unsigned(tx_hdr_cks(23 downto 16)));
crc_state <= FINAL;
when FINAL =>
tx_hdr_cks <= inv_if_one(std_logic_vector (unsigned(tx_hdr_cks) + unsigned(tx_hdr_cks(23 downto 16))), '1');
crc_state <= WAIT_END;
when WAIT_END =>
tx_hdr_cks <= tx_hdr_cks;
if ip_tx_start = '0' then
crc_state <= IDLE;
else
crc_state <= WAIT_END;
end if;
end case;
end if;
end process;
end Behavioral;
| gpl-3.0 | 5bf5ae912eb80b29489c5b4a1148a2a4 | 0.454838 | 3.925645 | false | false | false | false |
HackLinux/ION | src/rtl/buses/ion_wishbone_bridge.vhdl | 1 | 5,944 | --------------------------------------------------------------------------------
-- ion_wishbone_bridge.vhdl -- Connects an ION bus master to a Wishbone bus.
--------------------------------------------------------------------------------
-- ION_WISHBONE_BRIDGE
-- This bridge converts ION-bus signals to Wishbone signals ans vice-versa.
-- For the Wb-slaves, the bridge appears as the Wb-bus master.
--
-- REFERENCES
--
--------------------------------------------------------------------------------
--
--
--------------------------------------------------------------------------------
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ION_WISHBONE_BRIDGE is
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
ION_MOSI_I : in t_cpumem_mosi;
ION_MISO_O : out t_cpumem_miso;
WISHBONE_MOSI_O : out t_wishbone_mosi;
WISHBONE_MISO_I : in t_wishbone_miso
);
end;
architecture ION_WISHBONE_BRIDGE_arc of ION_WISHBONE_BRIDGE is
-- Signal to register the value of Wb-signal STALL_I
signal stall_i_reg : std_logic;
begin
--WISHBONE_MOSI_O <= ION_MOSI_I;
--ION_MISO_O <= WISHBONE_MISO_I;
--process (CLK_I, RESET_I, ION_MOSI_I.rd_en, ION_MOSI_I.wr_be,
-- WISHBONE_MISO_I.ack)
process (CLK_I, RESET_I, ION_MOSI_I, WISHBONE_MISO_I)
-- variable cyc_var : boolean := false;
begin
-----------------------------------------------------------------
-- Generate ION-bus o/p signals
-----------------------------------------------------------------
ION_MISO_O.rd_data <= WISHBONE_MISO_I.dat;
ION_MISO_O.mwait <= WISHBONE_MISO_I.stall;
-----------------------------------------------------------------
-- Generate Wishbone o/p signals
-----------------------------------------------------------------
WISHBONE_MOSI_O.adr <= ION_MOSI_I.addr;
WISHBONE_MOSI_O.dat <= ION_MOSI_I.wr_data;
WISHBONE_MOSI_O.tga <= ION_MOSI_I.wr_be;
WISHBONE_MOSI_O.we <= not(ION_MOSI_I.rd_en);
-----------------------------------------------------------------
-- Generate the Wb STROBE signal from valid read or write cycles
-----------------------------------------------------------------
if ((ION_MOSI_I.rd_en = '1' and ION_MOSI_I.wr_be /= "1111") or
(ION_MOSI_I.rd_en = '0' and ION_MOSI_I.wr_be = "1111")) then
WISHBONE_MOSI_O.stb <= '1';
else
WISHBONE_MOSI_O.stb <= '0';
end if;
-- Register the value of Wb signal STALL_I
if (RESET_I = '0') then
stall_i_reg <= '0';
else
if (CLK_I='1' and CLK_I'event) then
stall_i_reg <= WISHBONE_MISO_I.stall;
end if;
end if;
-----------------------------------------------------------------
-- Generate the Wb CYCLIC signal from valid read/write cycles
-----------------------------------------------------------------
if ((ION_MOSI_I.rd_en = '1' and ION_MOSI_I.wr_be /= "1111") or
(ION_MOSI_I.rd_en = '0' and ION_MOSI_I.wr_be = "1111")) then
WISHBONE_MOSI_O.cyc <= '1';
-- Check the STALL & ACK inputs in case of invalid read/write
else
-- If STALL was LOW in the previous clk cycle
if (stall_i_reg = '0') then
-- CYC is de-asserted only if ACK is de-asserted
if (WISHBONE_MISO_I.ack = '0') then
WISHBONE_MOSI_O.cyc <= '0';
-- CYC remains asserted
else
WISHBONE_MOSI_O.cyc <= '1';
end if;
-- If STALL was HIGH in previous clk cycle
else
WISHBONE_MOSI_O.cyc <= '1';
end if;
end if;
end process;
end architecture ION_WISHBONE_BRIDGE_arc;
| lgpl-3.0 | 668a43a5e4dbdf4427ace9836b3e8875 | 0.415377 | 4.93278 | false | false | false | false |
TeamSPoon/logicmoo_workspace | packs_web/swish/web/node_modules/ace/build/demo/kitchen-sink/docs/vhdl.vhd | 8 | 838 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count : unsigned (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= std_logic_vector(count);
end architecture;
| mit | a9e4c352ddf48de4a55dbb4f09609bc6 | 0.480907 | 4.067961 | false | false | false | false |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/decoder_ldstr.vhd | 1 | 10,225 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decode is
port(
din: in std_logic_vector(15 downto 0);
reg_rd_en : out std_logic;
Raddr1:out std_logic_vector(3 downto 0);
Raddr2:out std_logic_vector(3 downto 0);
memaddr: out std_logic_vector(7 downto 0);
operation:out std_logic_vector(4 downto 0);
dest_reg_en: out std_logic;
dest_reg: out std_logic_vector(3 downto 0);
src_reg1_en: out std_logic;
src_reg1: out std_logic_vector(3 downto 0);
src_reg2_en: out std_logic;
src_reg2: out std_logic_vector(3 downto 0);
return_from_interrupt : out std_logic
);
end decode;
architecture behav of decode is
begin
process(din)
variable check : std_logic_vector(3 downto 0);
begin
dest_reg_en <= '0';
dest_reg <= "0000";
src_reg1_en <= '0';
src_reg1 <= "0000";
src_reg2_en <= '0';
src_reg2 <= "0000";
return_from_interrupt <= '0';
reg_rd_en <= '1';
check := din(15 downto 12);
case check is
-------------------------------- No Operation ------------------------------------------
when "0000" => -- no op
Raddr1 <= "0000";
Raddr2 <= "0000";
memaddr<= "00000000";
operation <= "00000";
dest_reg_en <= '0';
src_reg1_en <= '0';
src_reg2_en <= '0';
reg_rd_en <= '0';
---------------------------------- Add/Subtract Operations ------------------------------
when "0001" => -- add immediate
Raddr1<= din(11 downto 8);
Raddr2<= "0000";
memaddr<= din(7 downto 0);
operation<= "00001";
dest_reg_en <= '1';
dest_reg <= din(11 downto 8);
src_reg1_en <= '1';
src_reg1 <= din(11 downto 8);
src_reg2_en <= '0';
when "0010" => -- add/sub
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
if (din(11 downto 8) = "0000") then
operation<= "00010"; --add
else
operation<= "00011"; --sub
end if;
dest_reg_en <= '1';
dest_reg <= din(7 downto 4);
src_reg1_en <= '1';
src_reg1 <= din(7 downto 4);
src_reg2_en <= '1';
src_reg2 <= din(3 downto 0);
--------------------------------------- Increment/Decrement ---------------------------------
when "0011" => -- increment/decrement
Raddr1<= din(11 downto 8);
Raddr2<= "0000";
memaddr<= "00000000";
if (din(11 downto 8) = "0000") then
operation<= "00100"; --inc
else
operation<= "00101"; --dec
end if;
dest_reg_en <= '1';
dest_reg <= din(11 downto 8);
src_reg1_en <= '1';
src_reg1 <= din(11 downto 8);
src_reg2_en <= '0';
------------------------------------------ Shift Operations -----------------------------------
when "0100" => -- shift left/right
Raddr1<= din(11 downto 8);
Raddr2<= "0000";
memaddr<= "00000000";
if (din(11 downto 8) = "0000") then
operation<= "00110"; --shift left
else
operation<= "00111"; --shift right
end if;
dest_reg_en <= '1';
dest_reg <= din(11 downto 8);
src_reg1_en <= '1';
src_reg1 <= din(11 downto 8);
src_reg2_en <= '0';
-------------------------------------------- Logical Operations ---------------------------------
when "0101" => --- logical operator
dest_reg_en <= '1';
dest_reg <= din(7 downto 4);
src_reg1_en <= '1';
src_reg1 <= din(7 downto 4);
src_reg2_en <= '1';
src_reg2 <= din(3 downto 0);
if(din(11 downto 8) = "0000") then -- not
operation<= "01000";
Raddr1<= din(11 downto 8);
Raddr2<= "0000";
memaddr<= "00000000";
dest_reg <= din(11 downto 8);
src_reg1 <= din(11 downto 8);
src_reg2_en <= '0';
end if;
if(din(11 downto 8) = "0001") then -- nor
operation<= "01001";
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
end if;
if(din(11 downto 8) = "0010") then -- nand
operation<= "01010";
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
end if;
if(din(11 downto 8) = "0011") then -- xor
operation<= "01011";
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
end if;
if(din(11 downto 8) = "0100") then -- and
operation<= "01100";
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
end if;
if(din(11 downto 8) = "0101") then -- nor
operation<= "01101";
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
end if;
------------------------------------- Set/Clear Operations -------------------------
if(din(11 downto 8) = "0110") then -- clear
operation<= "01110";
Raddr1<= din(7 downto 4);
Raddr2<= "0000";
memaddr<= "00000000";
dest_reg <= din(7 downto 4);
src_reg1 <= din(7 downto 4);
src_reg2_en <= '0';
end if;
if(din(11 downto 8) = "0111" ) then -- set
operation<= "01111";
Raddr1<= din(7 downto 4);
Raddr2<= "0000";
memaddr<= "00000000";
dest_reg <= din(7 downto 4);
src_reg1 <= din(7 downto 4);
src_reg2_en <= '0';
end if;
if(din(11 downto 8) = "1111") then -- set if less than
operation<= "10000";
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
dest_reg <= din(7 downto 4);
src_reg1 <= din(7 downto 4);
src_reg2 <= din(3 downto 0);
end if;
-------------------------------------- Move Operations -------------------------------------
if(din(11 downto 8) = "1000") then -- move
operation<= "10001";
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
dest_reg <= din(7 downto 4);
src_reg1 <= din(3 downto 0);
src_reg2_en <= '0';
end if;
------------------------------------- Enable Interrupt -------------------------------------
when "0111" => --enable interrupts
operation<= "10010";
Raddr1<= "0000";
Raddr2<= "0000";
memaddr<= "00000000";
dest_reg_en <= '0';
src_reg1_en <= '0';
src_reg2_en <= '0';
reg_rd_en <= '0';
----------------------------------- Load/Store Operations ----------------------------------
when "1000" => --load indirect
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
operation<= "10011";
dest_reg_en <= '1';
dest_reg <= din(7 downto 4);
src_reg1_en <= '0';
src_reg2_en <= '1';
src_reg2 <= din(3 downto 0);
when "1001" => --store indirect
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
operation <= "10100";
dest_reg_en <= '0';
src_reg1_en <= '1';
src_reg1 <= din(7 downto 4);
src_reg2_en <= '1';
src_reg2 <= din(3 downto 0);
--reg_rd_en <= '1';
when "1010"=> -- load register
Raddr1 <= din(11 downto 8);
Raddr2 <= "0000";
memaddr <= din(7 downto 0);
operation <= "10101";
dest_reg_en <= '1';
dest_reg <= din(11 downto 8);
src_reg1_en <= '0';
src_reg2_en <= '0';
reg_rd_en <= '0';
when "1011"=> -- store register
Raddr1 <= din(11 downto 8);
Raddr2 <= "0000";
memaddr <= din(7 downto 0);
operation <= "10110";
dest_reg_en <= '0';
src_reg1_en <= '1';
src_reg1 <= din(11 downto 8);
src_reg2_en <= '0';
--reg_rd_en <= '1';
------------------------------------------- Branch Intructions -----------------------------------
when "1100" => -- Jump
Raddr1 <= X"0";
Raddr2 <= X"0";
memaddr <= din(7 downto 0);
operation <= "10111";
dest_reg_en <= '0';
src_reg1_en <= '0';
src_reg2_en <= '0';
reg_rd_en <= '0';
when "1101" => -- Branch if Zero
Raddr1 <= din(11 downto 8);
Raddr2 <= X"0";
memaddr <= din(7 downto 0);
operation <= "11000";
dest_reg_en <= '0';
src_reg1_en <= '1';
src_reg1 <= din(11 downto 8);
src_reg2_en <= '0';
--reg_rd_en <= '0';
when "1110" => -- Branch if not Zero
Raddr1 <= din(11 downto 8);
Raddr2 <= X"0";
memaddr <= din(7 downto 0);
operation <= "11001";
dest_reg_en <= '0';
src_reg1_en <= '1';
src_reg1 <= din(11 downto 8);
src_reg2_en <= '0';
--reg_rd_en <= '0';
------------------------------------------ Return from Interrupt -----------------------------------
when "1111" => -- Return from Interrupt
Raddr1 <= "0000";
Raddr2 <= "0000";
memaddr<= "00000000";
operation <= "00000";
dest_reg_en <= '0';
src_reg1_en <= '0';
src_reg2_en <= '0';
reg_rd_en <= '0';
return_from_interrupt <= '1';
---------------------------------------------- Default/Nop ------------------------------------------
when others =>
Raddr1 <= "0000";
Raddr2 <= "0000";
memaddr<= "00000000";
operation <= "00000";
dest_reg_en <= '0';
src_reg1_en <= '0';
src_reg2_en <= '0';
reg_rd_en <= '0';
end case;
end process;
end architecture;
| unlicense | 1b15385bc99480ab652ed98e64f929c0 | 0.419169 | 3.556522 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN2_DEC8b10b.vhd | 1 | 5,728 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use work.all;
use work.centralRouter_package.all;
--! 8b10b decoder for EPROC_IN2 module
entity EPROC_IN2_DEC8b10b is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (1 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
busyOut : out std_logic
);
end EPROC_IN2_DEC8b10b;
architecture Behavioral of EPROC_IN2_DEC8b10b is
signal EDATAbitstreamSREG : std_logic_vector (11 downto 0) := (others=>'0'); -- 12 bit (2 x 5 = 10, plus 2 more)
signal word10b_align_array, word10b_align_array_r : word10b_2array_type;
signal word10b : std_logic_vector (9 downto 0) := (others=>'0');
signal comma_valid_bits_or, word10b_align_rdy_r : std_logic;
signal align_select, word10b_rdy : std_logic := '0';
signal comma_valid_bits : std_logic_vector (1 downto 0);
signal alignment_sreg : std_logic_vector (4 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- input shift register
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
EDATAbitstreamSREG <= (others => '0');
elsif rising_edge(bitCLK) then
EDATAbitstreamSREG <= edataIN & EDATAbitstreamSREG(11 downto 2);
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock0
-- input shift register mapping into 10 bit registers
-------------------------------------------------------------------------------------------
input_map: for I in 0 to 1 generate -- 1 10bit-word per alignment, 2 possible alignments
--word10b_align_array(I) <= EDATAbitstreamSREG((I+9) downto (I+0)); -- 10 bit word, alligned to bit I
word10b_align_array(I) <= EDATAbitstreamSREG(I+0)&EDATAbitstreamSREG(I+1)&EDATAbitstreamSREG(I+2)&EDATAbitstreamSREG(I+3)&EDATAbitstreamSREG(I+4)&
EDATAbitstreamSREG(I+5)&EDATAbitstreamSREG(I+6)&EDATAbitstreamSREG(I+7)&EDATAbitstreamSREG(I+8)&EDATAbitstreamSREG(I+9); -- 10 bit word, alligned to bit I
end generate input_map;
--
-------------------------------------------------------------------------------------------
--clock0
-- K28.5 comma test
-------------------------------------------------------------------------------------------
comma_test: for I in 0 to 1 generate -- 1 10bit-word per alignment, comma is valid if two first words have comma...
comma_valid_bits(I) <= '1' when (word10b_align_array(I) = COMMAp or word10b_align_array(I) = COMMAn) else '0';
end generate comma_test;
--
comma_valid_bits_or <= comma_valid_bits(1) or comma_valid_bits(0);
--
-------------------------------------------------------------------------------------------
--clock1
-- alignment selector state
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
alignment_sreg <= "00000";
elsif rising_edge(bitCLK) then
if comma_valid_bits_or = '1' then
alignment_sreg <= "10000";
else
alignment_sreg <= alignment_sreg(0) & alignment_sreg(4 downto 1);
end if;
end if;
end process;
--
input_reg1: process(bitCLK)
begin
if rising_edge(bitCLK) then
word10b_align_array_r <= word10b_align_array;
end if;
end process;
--
word10b_align_rdy_r <= alignment_sreg(4);
--
process(bitCLK, rst)
begin
if rst = '1' then
align_select <= '0';
elsif rising_edge(bitCLK) then
if comma_valid_bits_or = '1' then
align_select <= (not comma_valid_bits(0)) and comma_valid_bits(1);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock2
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg2: process(bitCLK)
begin
if rising_edge(bitCLK) then
word10b_rdy <= word10b_align_rdy_r;
end if;
end process;
--
process(bitCLK)
begin
if rising_edge(bitCLK) then
case (align_select) is
when '0' => -- bit0 word got comma => align to bit0
word10b <= word10b_align_array_r(0);
when '1' => -- bit1 word got comma => align to bit1
word10b <= word10b_align_array_r(1);
when others =>
end case;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- at this stage: word10b and word10b_rdy are aligned @ bitCLK
-------------------------------------------------------------------------------------------
EPROC_IN2_ALIGN_BLOCK_inst: entity work.EPROC_IN2_ALIGN_BLOCK
port map(
bitCLK => bitCLK,
bitCLKx4 => bitCLKx4,
rst => rst,
bytes => word10b,
bytes_rdy => word10b_rdy,
dataOUT => dataOUT,
dataOUTrdy => dataOUTrdy,
busyOut => busyOut
);
end Behavioral;
| gpl-3.0 | f22447049bc308b8a936c8a5812d5782 | 0.477654 | 4.005594 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/CD_COUNTER.vhd | 4 | 1,687 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: CD_COUNTER
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--! chunk data counter
entity CD_COUNTER is
port (
CLK : in std_logic;
RESET : in std_logic;
xoff : in std_logic;
COUNT_ENA : in std_logic; -- high only when data is sent (not counting header and trailers)
MAX_COUNT : in std_logic_vector (2 downto 0); -- (15 downto 0);
-----
count_out : out std_logic_vector (11 downto 0);
truncate_data : out std_logic
);
end CD_COUNTER;
architecture Behavioral of CD_COUNTER is
signal count_sig : std_logic_vector (11 downto 0) := (others => '0');
signal max_mark, max_ena : std_logic;
begin
--
max_ena <= '0' when (MAX_COUNT = "000") else '1'; -- when max count is 0x0, no chunk length limit is set
max_mark <= '1' when ((count_sig(11 downto 9) = MAX_COUNT) and (max_ena = '1')) else '0'; -- stays high until reset
--
counter: process(RESET, CLK)
begin
if RESET = '1' then
count_sig <= (others => '0');
elsif CLK'event and CLK = '1' then
if (COUNT_ENA = '1' and max_mark = '0') then
count_sig <= count_sig + 1; -- keeps the final value until reset
end if;
end if;
end process;
--
truncate_data <= max_mark or xoff;
count_out <= count_sig;
--
end Behavioral;
| gpl-3.0 | 499a4add85300f1d3337d926fdc9a84d | 0.5246 | 3.380762 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4088/pulse_pdxx_pwxx.vhd | 1 | 2,986 | ----------------------------------------------------------------------------------
--! Company: Weizmann Institute of Science
--! Engineer: juna
--!
--! Create Date: 18/12/2014
--! Module Name: pulse_pdxx_pwxx
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! generates a one clk-pulse pd clkss after trigger rising edge
entity pulse_pdxx_pwxx is
generic (
pd : integer := 0; -- pulse delay in clks
pw : integer := 1 -- pulse width in clks
);
Port (
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end pulse_pdxx_pwxx;
architecture Behavioral of pulse_pdxx_pwxx is
------
constant shreg_pd_zeros: std_logic_vector(pd downto 0) := (others => '0');
constant shreg_pw_zeros: std_logic_vector(pw downto 0) := (others => '0');
--
signal shreg_pd: std_logic_vector(pd downto 0) := (others => '0');
signal shreg_pw: std_logic_vector(pw downto 0) := (others => '0');
--
signal on_s : std_logic := '0';
signal pulseout_s_pw_gt1_case_s : std_logic := '0';
signal trigger_1clk_delayed, t0, off_s : std_logic := '0';
------
begin
process (clk)
begin
if clk'event and clk = '1' then
trigger_1clk_delayed <= trigger;
end if;
end process;
t0 <= trigger and (not trigger_1clk_delayed); -- the first clk of a trigger, one clk pulse
--
----------------------------------------
-- shift register for pulse delay
----------------------------------------
pd0_case: if (pd = 0) generate
on_s <= t0;
end generate pd0_case;
--
--
pd_gt0_case: if (pd > 0) generate
--
process (clk)
begin
if clk'event and clk = '1' then
if t0 = '1' then
shreg_pd <= shreg_pd_zeros(pd-1 downto 0) & '1';
else
shreg_pd <= shreg_pd(pd-1 downto 0) & '0';
end if;
end if;
end process;
--
on_s <= shreg_pd(pd-1);
end generate pd_gt0_case;
----------------------------------------
-- shift register for pulse width
----------------------------------------
pw1_case: if (pw = 1) generate
pulseout <= on_s;
end generate pw1_case;
pw_gt1_case: if (pw > 1) generate
--
process (clk)
begin
if clk'event and clk = '1' then
if on_s = '1' then
shreg_pw <= shreg_pw_zeros(pw-1 downto 0) & '1';
else
shreg_pw <= shreg_pw(pw-1 downto 0) & '0';
end if;
end if;
end process;
--
off_s <= shreg_pw(pw-1);
--
process (clk)
begin
if clk'event and clk = '1' then
if off_s = '1' then
pulseout_s_pw_gt1_case_s <= '0';
elsif on_s = '1' then
pulseout_s_pw_gt1_case_s <= '1';
end if;
end if;
end process;
--
pulseout <= (pulseout_s_pw_gt1_case_s or on_s) and (not off_s);
end generate pw_gt1_case;
end Behavioral;
| gpl-3.0 | be4feacc8001c5df1c4cf520d9d90437 | 0.494642 | 3.245652 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/LCD.vhdl | 1 | 5,914 |
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use work.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------------
--FPGA to DMC16207 LCD interface. Takes care of inititation and after that sits
--ready to take commands from the top module to print, clear or row-change.
-------------------------------------------------------------------------------
entity LCD is
Generic ( Frequency : integer); --Needs to know the frequency the curcuit is running at
Port (INPUT : in STD_LOGIC_VECTOR (7 downto 0); --ASCII IN
CLK : in STD_LOGIC; --FPGA Clock (100MHz)
RESET : in STD_LOGIC; --RESET
DATA_BUS : out STD_LOGIC_VECTOR (7 downto 0);--DB 7 downto DB 0
RW : out STD_LOGIC := '0'; --RW signal (unused as of now)
RS : out STD_LOGIC; --RS signal
E : out STD_LOGIC; --E (200Hz)
MODE_SELECT : in STD_LOGIC_VECTOR (1 downto 0); --Select cmd to be done
RDY_CMD : out STD_LOGIC := '0'; --Ready for cmd from top module
DO_CMD : in STD_LOGIC); --Cmd to be done from top module
end LCD;
architecture Behaviour of LCD is
Signal INPUT_2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
Signal clock_div_1, clock_div_2: unsigned (7 downto 0) := (others => '0');
Signal clock_div_3, init_state : unsigned (3 downto 0) := (others => '0');
Signal E_toggle, e_step : STD_LOGIC := '0';
constant Clock_cutoff : integer := Frequency/800;
Signal Clock_div : integer range 0 to Frequency/800 := 0;
begin
-------------------------------------CLOCK DIVIDER----------------------------
--Divides a clock from FREQ to 400Hz
------------------------------------------------------------------------------
clock_divider: process (clk)
begin
if rising_edge(clk) then
if RESET = '1' then
Clock_div <= 0;
E_toggle <= '0';
else
if Clock_div < Clock_cutoff then --Inc the counter
Clock_div <= Clock_div + 1;
else --Happens at a frequency of 800Hz
Clock_div <= 0;
E_toggle <= NOT E_toggle; --As this is the inverse of the previous signal, the E_toggle is at 400Hz
end if;
end if;
end if;
end process;
---------------------------------State and Data changes------------------------
--Happens on high flank as on E low flank the action will be executed. Switches
--between having the E 1 and 0 each high flank of E_toggle, and is as such half
--the frequency of E_toggle (200Hz).
-------------------------------------------------------------------------------
E_process: process (E_toggle)
begin
if rising_edge(E_toggle) then
if e_step = '0' then
---------------------------------------------------Initilazion takes 8 E-cycles
if init_state < 8 then
init_state <= init_state + 1;
e_step <= '1';
case init_state is
when x"4" => --Display OFF
RS <= '0';
RW <= '0';
DATA_BUS <= "00001000";
when x"5" => --Clear Display
RS <= '0';
RW <= '0';
DATA_BUS <= "00000001";
when x"6" => --Entry Mode Set
RS <= '0';
RW <= '0';
DATA_BUS <= "00000110";
when x"7" => --Display ON (Blink and Cursor ON)
RS <= '0';
RW <= '0';
DATA_BUS <= "00001111";
RDY_CMD <= '1';
when others => --Function set command (step 0,1,2,3)
RS <= '0';
RW <= '0';
DATA_BUS <= "00111100";
end case;
-----------------------------------------------------Normal operation selection
elsif DO_CMD = '1' then
e_step <= '1';
RDY_CMD <= '0';
case MODE_SELECT is
when "00" => --CLEAR DISPAY
RS <= '0';
RW <= '0';
DATA_BUS <= "00000001";
when "01" => --Print INPUT on DISPLAY
RS <= '1';
RW <= '0';
DATA_BUS <= INPUT;
if INPUT = "00000000" then --if char is '\0', don't print it
e_step <= '0';
end if;
when "10" => --CHANGE ROW
RS <= '0';
RW <= '0';
DATA_BUS <= "11000000";
when others => --CLEAR DISPLAY
RS <= '0';
RW <= '0';
DATA_BUS <= "00000001";
end case;
else --Because we don't print '\0' we have to reset RDY_CMD here
RDY_CMD <= '1';
end if;
else
e_step <= '0';
RDY_CMD <= '1';
end if;
E <= e_step;
end if;
end process E_process;
end architecture; | bsd-3-clause | 3a37d97f9c6a8ec175f06e1e5b8f8291 | 0.573554 | 3.757306 | false | false | false | false |
HackLinux/ION | src/rtl/common/ion_internal_pkg.vhdl | 1 | 12,570 | --------------------------------------------------------------------------------
-- ION_INTERNAL_PKG.vhdl -- Configuration constants, utility types & functions.
--------------------------------------------------------------------------------
-- For use within the core component modules only.
-- Modules instantiating an ion_core entity do not need this package.
--------------------------------------------------------------------------------
-- FIXME Plenty of remnants from the old ION version, refactor!
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
package ION_INTERNAL_PKG is
---- Basic types ---------------------------------------------------------------
subtype t_halfword is std_logic_vector(15 downto 0);
subtype t_byte is std_logic_vector(7 downto 0);
subtype t_pc is std_logic_vector(31 downto 2);
subtype t_regindex is std_logic_vector(4 downto 0);
---- Interface types -----------------------------------------------------------
type t_cpumem_mosi is record
addr : t_word;
rd_en : std_logic;
wr_be : std_logic_vector(3 downto 0);
wr_data : t_word;
end record t_cpumem_mosi;
type t_cpumem_miso is record
rd_data : t_word;
mwait : std_logic;
end record t_cpumem_miso;
type t_cache_mosi is record
function_code : std_logic_vector(2 downto 0);
function_en : std_logic; -- 1 to perform function_code operation.
data_cache : std_logic; -- 1 to operate on D-cache, 0 for I-Cache.
end record t_cache_mosi;
type t_cache_miso is record
present : std_logic; -- Hardwired to 1 when cache is present.
end record t_cache_miso;
type t_cop0_mosi is record
index : t_regindex;
we : std_logic;
data : t_word;
pc_restart : t_pc;
in_delay_slot : std_logic;
pipeline_stalled : std_logic;
exception : std_logic;
hw_irq : std_logic;
hw_irq_reg : std_logic_vector(7 downto 2);
eret : std_logic;
rfe : std_logic;
unknown_opcode : std_logic;
missing_cop : std_logic;
syscall : std_logic;
stall : std_logic;
end record t_cop0_mosi;
type t_cop0_miso is record
data : t_word;
pc_load_en : std_logic;
pc_load_value : t_pc;
hw_irq_enable_mask: std_logic_vector(5 downto 0);
global_irq_enable : std_logic;
kernel : std_logic;
end record t_cop0_miso;
---- System configuration constants --------------------------------------------
-- True to use standard-ish MIPS-1 memory map, false to use Plasma's
-- (see implementation of function decode_addr_old below).
constant USE_MIPS1_ADDR_MAP : boolean := true;
-- Reset vector address.
constant RESET_VECTOR : t_word := X"bfc00000";
-- General exception vector address.
constant GENERAL_EXCEPTION_VECTOR : t_word := X"bfc00180";
-- Object code in bytes, i.e. as read from a binary or HEX file.
-- This type is used to define BRAM init constants from external scripts.
type t_obj_code is array(integer range <>) of std_logic_vector(7 downto 0);
-- Types used to define memories for synthesis or simulation.
type t_word_table is array(integer range <>) of t_word;
type t_hword_table is array(integer range <>) of t_halfword;
type t_byte_table is array(integer range <>) of t_byte;
---- Object code management -- initialization helper functions -----------------
-- Dummy t_obj_code constant, to be used essentially as a syntactic placeholder.
constant default_object_code : t_obj_code(0 to 3) := (
X"00", X"00", X"00", X"00"
);
-- Build t_obj_code if given size (in bytes) filled with zeros.
function zero_objcode(size : integer) return t_obj_code;
-- Builds BRAM initialization constant from a constant CONSTRAINED byte array
-- containing the application object code.
-- The constant is a 32-bit, big endian word table.
-- The object code is placed at the beginning of the BRAM and the rest is
-- filled with zeros.
-- The object code is truncated if it doesn't fit the given table size.
-- CAN BE USED IN SYNTHESIZABLE CODE to compute a BRAM initialization constant
-- from a constant argument.
function objcode_to_wtable(oC : t_obj_code; size : integer) return t_word_table;
-- Builds BRAM initialization constant from a constant CONSTRAINED byte array
-- containing the application object code.
-- The constant is a 16-bit, big endian word table.
-- The object code is placed at the beginning of the BRAM and the rest is
-- filled with zeros.
-- The object code is truncated if it doesn't fit the given table size.
-- CAN BE USED IN SYNTHESIZABLE CODE to compute a BRAM initialization constant
-- from a constant argument.
function objcode_to_htable(oC : t_obj_code; size : integer) return t_hword_table;
-- Builds BRAM initialization constant from a constant CONSTRAINED byte array
-- containing the application object code.
-- It will put the whole object code into a byte table if slice=-1, otherwise
-- it will extract the selected slice (0 to 3) and put only that in the table.
-- If slice = -1, the size is that fo the whole data block.
-- If slice >= 0, the size is that of the slice, i.e. 1/4 of the block size.
-- The constant is an 8-bit byte table in BIG ENDIAN format.
-- Slice 0 is the lowest byte, slice 3 is the highest byte.
-- The object code is placed at the beginning of the BRAM and the rest is
-- filled with zeros.
-- The object code is truncated if it doesn't fit the given table size.
-- CAN BE USED IN SYNTHESIZABLE CODE to compute a BRAM initialization constant
-- from a constant argument.
function objcode_to_btable(oC : t_obj_code; size : integer;
slice : integer := -1) return t_byte_table;
---- More basic types and constants --------------------------------------------
subtype t_addr is std_logic_vector(31 downto 0);
subtype t_dword is std_logic_vector(63 downto 0);
subtype t_regnum is std_logic_vector(4 downto 0);
type t_rbank is array(0 to 31) of t_word;
-- This is used as a textual shortcut only
constant ZERO : t_word := (others => '0');
-- control word for ALU
type t_alu_control is record
logic_sel : std_logic_vector(1 downto 0);
shift_sel : std_logic_vector(1 downto 0);
shift_amount : std_logic_vector(4 downto 0);
neg_sel : std_logic_vector(1 downto 0);
use_arith : std_logic;
use_logic : std_logic_vector(1 downto 0);
cy_in : std_logic;
use_slt : std_logic;
arith_unsigned : std_logic;
end record t_alu_control;
-- Flags coming from the ALU
type t_alu_flags is record
inp1_lt_zero : std_logic;
inp1_eq_zero : std_logic;
inp1_lt_inp2 : std_logic;
inp1_eq_inp2 : std_logic;
end record t_alu_flags;
-- Debug info output by sinthesizable MPU core; meant to debug the core itself,
-- not to debug software!
type t_debug_info is record
cache_enabled : std_logic;
unmapped_access : std_logic;
end record t_debug_info;
-- 32-cycle mul/div module control. Bits 4-3 & 1-0 of IR.
subtype t_mult_function is std_logic_vector(3 downto 0);
constant MULT_NOTHING : t_mult_function := "0000";
constant MULT_MADDU : t_mult_function := "0101"; -- 5
constant MULT_MADD : t_mult_function := "0100"; -- 4
constant MULT_READ_LO : t_mult_function := "1010"; -- 18
constant MULT_READ_HI : t_mult_function := "1000"; -- 16
constant MULT_WRITE_LO : t_mult_function := "1011"; -- 19
constant MULT_WRITE_HI : t_mult_function := "1001"; -- 17
constant MULT_MULT : t_mult_function := "1101"; -- 25
constant MULT_SIGNED_MULT : t_mult_function := "1100"; -- 24
constant MULT_DIVIDE : t_mult_function := "1111"; -- 26
constant MULT_SIGNED_DIVIDE : t_mult_function := "1110"; -- 27
-- Computes ceil(log2(A)), e.g. address width of memory block
-- CAN BE USED IN SYNTHESIZABLE CODE as long as called with constant arguments
function log2(A : natural) return natural;
end package;
package body ION_INTERNAL_PKG is
function log2(A : natural) return natural is
begin
for I in 1 to 30 loop -- Works for up to 32 bit integers
if(2**I >= A) then
return(I);
end if;
end loop;
return(30);
end function log2;
function zero_objcode(size : integer) return t_obj_code is
variable oc : t_obj_code(0 to size-1) := (others => X"00");
begin
return oc;
end function zero_objcode;
function objcode_to_wtable(oC : t_obj_code;
size : integer)
return t_word_table is
variable br : t_word_table(integer range 0 to size/4-1):=(others => X"00000000");
variable i, address, index : integer;
begin
-- Copy object code to start of BRAM...
i := 0;
for i in 0 to oC'length-1 loop
case i mod 4 is
when 0 => index := 24;
when 1 => index := 16;
when 2 => index := 8;
when others => index := 0;
end case;
address := i / 4;
if address >= size or address >= br'high then
exit;
end if;
br(address)(index+7 downto index) := oC(i);
end loop;
return br;
end function objcode_to_wtable;
function objcode_to_htable(oC : t_obj_code;
size : integer)
return t_hword_table is
variable br : t_hword_table(integer range 0 to size-1):=(others => X"0000");
variable i, address, index : integer;
begin
-- Copy object code to start of BRAM...
i := 0;
for i in 0 to oC'length-1 loop
case i mod 2 is
when 1 => index := 8;
when others => index := 0;
end case;
address := i / 2;
if address >= size then
exit;
end if;
br(address)(index+7 downto index) := oC(i);
end loop;
return br;
end function objcode_to_htable;
function objcode_to_btable(oC : t_obj_code;
size : integer;
slice : integer := -1)
return t_byte_table is
variable br : t_byte_table(integer range 0 to size-1):=(others => X"00");
variable i, address, index : integer;
begin
if slice < 0 then
-- Copy object code to start of table, leave the rest filled with zeros.
for i in 0 to oC'length-1 loop
if i >= size then
exit;
end if;
br(i) := oC(i);
end loop;
else
-- Remember, oC is big endian and slice 0 is the low byte.
i := 0; -- TODO check bounds!
while ((i*4)+(3-slice)) < (oC'length) loop
if i >= size then
exit;
end if;
br(i) := oC((3-slice) + (i*4));
i := i + 1;
end loop;
end if;
return br;
end function objcode_to_btable;
end package body;
| lgpl-3.0 | 69877be25f68b92c91496519c9b67f64 | 0.584487 | 3.918329 | false | false | false | false |
tdotu/ra | memoryBank.vhd | 1 | 1,390 | LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY memoryBank IS
GENERIC
(
adressWidth : integer;
memorySize : integer;
wordLength : integer
);
PORT
(
adress : IN std_logic_vector(adressWidth-1 downto 0);
writeBit : IN std_logic; -- if 1 then write input to adressed dword
input : IN std_logic_vector(wordLength-1 downto 0);
output : OUT std_logic_vector(wordLength-1 downto 0) -- value of the selected dword
);
END memoryBank;
ARCHITECTURE behaviour OF memoryBank IS
COMPONENT reg IS
GENERIC
(
width : integer
);
PORT
(
clock : IN std_logic;
change : IN std_logic_vector(width-1 downto 0);
state : OUT std_logic_vector(width-1 downto 0)
);
END COMPONENT;
SUBTYPE cellLane IS std_logic_vector(wordLength-1 downto 0);
TYPE memoryLane IS ARRAY(integer RANGE 0 TO memorySize-1) OF cellLane;
SIGNAL outputLane : memoryLane;
SIGNAL cellWrite : std_logic_vector(memorySize-1 downto 0);
BEGIN
gen0 : FOR X IN 0 TO memorySize-1 GENERATE
regx : reg GENERIC MAP (wordLength) PORT MAP (cellWrite(X),input,outputLane(X)); -- create cells
output <= outputLane(X) WHEN (adress = std_logic_vector(to_unsigned(X, adressWidth))) ELSE (OTHERS => 'Z');
cellWrite(X) <= writeBit WHEN adress = std_logic_vector(to_unsigned(X, adressWidth)) ELSE '0';
END GENERATE;
END behaviour;
| gpl-3.0 | cd609da242e2e0f6464bb87c5a2529d7 | 0.692806 | 3.210162 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/configuration/vmm_oddr_wrapper.vhd | 1 | 13,975 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 21.06.2017 14:18:44
-- Design Name: VMM ODDR Wrapper
-- Module Name: vmm_oddr_wrapper - RTL
-- Project Name: NTUA-BNL VMM3 Readout Firmware
-- Target Devices: Xilinx xc7a200t-2fbg484 and xc7a100t
-- Tool Versions: Vivado 2017.2
-- Description: Wrapper that contains the ODDR instantiations necessary for VMM
-- clock forwarding.
--
-- Dependencies:
--
-- Changelog:
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VComponents.all;
entity vmm_oddr_wrapper is
Port(
-------------------------------------------------------
ckdt_bufg : in std_logic;
ckdt_enable_vec : in std_logic_vector(8 downto 1);
ckdt_toBuf_vec : out std_logic_vector(8 downto 1);
-------------------------------------------------------
ckbc_bufg : in std_logic;
ckbc_enable : in std_logic;
ckbc_toBuf_vec : out std_logic_vector(8 downto 1);
-------------------------------------------------------
cktp_bufg : in std_logic;
cktp_toBuf_vec : out std_logic_vector(8 downto 1);
-------------------------------------------------------
ckart_bufg : in std_logic;
ckart_toBuf_vec : out std_logic_vector(9 downto 1)
-------------------------------------------------------
);
end vmm_oddr_wrapper;
architecture RTL of vmm_oddr_wrapper is
signal ckdt_inhibit : std_logic_vector(8 downto 1) := (others => '0');
signal ckbc_inhibit : std_logic := '0';
begin
----------------------------
--------- CKDT/ODDR --------
----------------------------
ODDR_CKDT_1: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckdt_toBuf_vec(1),
C => ckdt_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKDT_2: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckdt_toBuf_vec(2),
C => ckdt_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKDT_3: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckdt_toBuf_vec(3),
C => ckdt_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKDT_4: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckdt_toBuf_vec(4),
C => ckdt_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKDT_5: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckdt_toBuf_vec(5),
C => ckdt_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKDT_6: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckdt_toBuf_vec(6),
C => ckdt_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKDT_7: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckdt_toBuf_vec(7),
C => ckdt_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKDT_8: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckdt_toBuf_vec(8),
C => ckdt_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
----------------------------
--------- CKBC/ODDR --------
----------------------------
ODDR_CKBC_1: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckbc_toBuf_vec(1),
C => ckbc_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKBC_2: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckbc_toBuf_vec(2),
C => ckbc_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKBC_3: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckbc_toBuf_vec(3),
C => ckbc_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKBC_4: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckbc_toBuf_vec(4),
C => ckbc_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKBC_5: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckbc_toBuf_vec(5),
C => ckbc_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKBC_6: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckbc_toBuf_vec(6),
C => ckbc_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKBC_7: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckbc_toBuf_vec(7),
C => ckbc_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKBC_8: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckbc_toBuf_vec(8),
C => ckbc_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
----------------------------
--------- CKTP/ODDR --------
----------------------------
ODDR_CKTP_1: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => cktp_toBuf_vec(1),
C => cktp_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKTP_2: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => cktp_toBuf_vec(2),
C => cktp_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKTP_3: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => cktp_toBuf_vec(3),
C => cktp_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKTP_4: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => cktp_toBuf_vec(4),
C => cktp_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKTP_5: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => cktp_toBuf_vec(5),
C => cktp_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKTP_6: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => cktp_toBuf_vec(6),
C => cktp_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKTP_7: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => cktp_toBuf_vec(7),
C => cktp_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKTP_8: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => cktp_toBuf_vec(8),
C => cktp_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
----------------------------
--------- CKART/ODDR -------
----------------------------
ODDR_CKART_1: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(1),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKART_2: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(2),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKART_3: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(3),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKART_4: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(4),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKART_5: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(5),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKART_6: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(6),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKART_7: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(7),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKART_8: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(8),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ODDR_CKART_9: ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => ckart_toBuf_vec(9),
C => ckart_bufg,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
ckdt_inhibit(1) <= not ckdt_enable_vec(1);
ckdt_inhibit(2) <= not ckdt_enable_vec(2);
ckdt_inhibit(3) <= not ckdt_enable_vec(3);
ckdt_inhibit(4) <= not ckdt_enable_vec(4);
ckdt_inhibit(5) <= not ckdt_enable_vec(5);
ckdt_inhibit(6) <= not ckdt_enable_vec(6);
ckdt_inhibit(7) <= not ckdt_enable_vec(7);
ckdt_inhibit(8) <= not ckdt_enable_vec(8);
ckbc_inhibit <= not ckbc_enable;
end RTL; | gpl-3.0 | 74a2d1a4853b1dee046dbfb58e97b138 | 0.369803 | 3.340904 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Count_Gen/count_gen.vhd | 1 | 2,100 | --------------------------------------------------------------------------------------------------
-- Count Generator
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package count_gen_pkg is
component count_gen is
generic( INIT_VAL : integer := 0;
STEP_VAL : integer := 1);
port( clk : in std_logic;
rst : in std_logic;
en : in std_logic;
count : out integer);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity count_gen is
generic( INIT_VAL : integer := 0;
STEP_VAL : integer := 1);
port( clk : in std_logic;
rst : in std_logic;
en : in std_logic;
count : out integer);
end count_gen;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture rtl of count_gen is
signal count_reg : integer := INIT_VAL;
begin
-- increment the count value when enabled.
counter : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
count_reg <= INIT_VAL;
elsif(en = '1') then
count_reg <= count_reg + STEP_VAL;
end if;
end if;
end process;
count <= count_reg;
end rtl;
| mit | 88f115cdfa63f5b4f37e92adb27c8bda | 0.316667 | 5.630027 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/UDP_TX.vhd | 2 | 11,282 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 5 June 2011
-- Design Name:
-- Module Name: UDP_TX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple UDP TX
-- doesnt generate the checksum(supposedly optional)
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Added abort of tx when receive last from upstream
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
entity UDP_TX is
Port (
-- UDP Layer signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
-- IP layer TX signals
ip_tx_start : out std_logic;
ip_tx : out ipv4_tx_type; -- IP tx cxns
ip_tx_result : in std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : in std_logic -- indicates IP TX is ready to take data
);
end UDP_TX;
architecture Behavioral of UDP_TX is
type tx_state_type is (IDLE, PAUSE, SEND_UDP_HDR, SEND_USER_DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_cnt_type is (RST, SET, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- TX state variables
signal udp_tx_state : tx_state_type;
signal tx_count : unsigned (15 downto 0);
signal tx_result_reg : std_logic_vector (1 downto 0);
signal ip_tx_start_reg : std_logic;
signal data_out_ready_reg : std_logic;
-- tx control signals
signal next_tx_state : tx_state_type;
signal set_tx_state : std_logic;
signal next_tx_result : std_logic_vector (1 downto 0);
signal set_tx_result : std_logic;
signal tx_count_val : unsigned (15 downto 0);
signal tx_count_mode : settable_cnt_type;
signal tx_data : std_logic_vector (7 downto 0);
signal set_last : std_logic;
signal set_ip_tx_start : set_clr_type;
signal tx_data_valid : std_logic; -- indicates whether data is valid to tx or not
-- tx temp signals
signal total_length : std_logic_vector (15 downto 0); -- computed combinatorially from header size
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | source port number | dest port number |
-- | | |
-- --------------------------------------------------------------------------------------------
-- | length (bytes) | checksum |
-- | (header and data combined) | |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
tx_combinatorial : process(
-- input signals
udp_tx_start, udp_txi, clk, ip_tx_result, ip_tx_data_out_ready,
-- state variables
udp_tx_state, tx_count, tx_result_reg, ip_tx_start_reg, data_out_ready_reg,
-- control signals
next_tx_state, set_tx_state, next_tx_result, set_tx_result, tx_count_mode, tx_count_val,
tx_data, set_last, total_length, set_ip_tx_start, tx_data_valid
)
begin
-- set output followers
ip_tx_start <= ip_tx_start_reg;
ip_tx.hdr.protocol <= x"11"; -- UDP protocol
ip_tx.hdr.data_length <= total_length;
ip_tx.hdr.dst_ip_addr <= udp_txi.hdr.dst_ip_addr;
if udp_tx_start = '1' and ip_tx_start_reg = '0' then
udp_tx_result <= UDPTX_RESULT_NONE; -- kill the result until have started the IP layer
else
udp_tx_result <= tx_result_reg;
end if;
case udp_tx_state is
when SEND_USER_DATA =>
ip_tx.data.data_out <= udp_txi.data.data_out;
tx_data_valid <= udp_txi.data.data_out_valid;
ip_tx.data.data_out_last <= udp_txi.data.data_out_last;
when SEND_UDP_HDR =>
ip_tx.data.data_out <= tx_data;
tx_data_valid <= ip_tx_data_out_ready;
ip_tx.data.data_out_last <= set_last;
when others =>
ip_tx.data.data_out <= (others => '0');
tx_data_valid <= '0';
ip_tx.data.data_out_last <= set_last;
end case;
ip_tx.data.data_out_valid <= tx_data_valid and ip_tx_data_out_ready;
-- set signal defaults
next_tx_state <= IDLE;
set_tx_state <= '0';
tx_count_mode <= HOLD;
tx_data <= x"00";
set_last <= '0';
next_tx_result <= UDPTX_RESULT_NONE;
set_tx_result <= '0';
set_ip_tx_start <= HOLD;
tx_count_val <= (others => '0');
udp_tx_data_out_ready <= '0';
-- set temp signals
total_length <= std_logic_vector(unsigned(udp_txi.hdr.data_length) + 8); -- total length = user data length + header length (bytes)
-- TX FSM
case udp_tx_state is
when IDLE =>
udp_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
tx_count_mode <= RST;
if udp_tx_start = '1' then
-- check header count for error if too high
if unsigned(udp_txi.hdr.data_length) > 8966 then
next_tx_result <= UDPTX_RESULT_ERR; -- 10
set_tx_result <= '1';
else
-- start to send UDP header
tx_count_mode <= RST;
next_tx_result <= UDPTX_RESULT_SENDING; -- 01
set_ip_tx_start <= SET;
set_tx_result <= '1';
next_tx_state <= PAUSE;
set_tx_state <= '1';
end if;
end if;
when PAUSE =>
-- delay one clock for IP layer to respond to ip_tx_start and remove any tx error result
next_tx_state <= SEND_UDP_HDR;
set_tx_state <= '1';
when SEND_UDP_HDR =>
udp_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if ip_tx_result = IPTX_RESULT_ERR then -- 10
set_ip_tx_start <= CLR;
next_tx_result <= UDPTX_RESULT_ERR; -- 10
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
elsif ip_tx_data_out_ready = '1' then
if tx_count = x"0007" then
tx_count_val <= x"0001";
tx_count_mode <= SET;
next_tx_state <= SEND_USER_DATA;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"0000" => tx_data <= udp_txi.hdr.src_port (15 downto 8); -- src port
when x"0001" => tx_data <= udp_txi.hdr.src_port (7 downto 0);
when x"0002" => tx_data <= udp_txi.hdr.dst_port (15 downto 8); -- dst port
when x"0003" => tx_data <= udp_txi.hdr.dst_port (7 downto 0);
when x"0004" => tx_data <= total_length (15 downto 8); -- length
when x"0005" => tx_data <= total_length (7 downto 0);
when x"0006" => tx_data <= udp_txi.hdr.checksum (15 downto 8); -- checksum (set by upstream)
when x"0007" => tx_data <= udp_txi.hdr.checksum (7 downto 0);
when others =>
-- shouldnt get here - handle as error
next_tx_result <= UDPTX_RESULT_ERR;
set_tx_result <= '1';
end case;
end if;
when SEND_USER_DATA =>
udp_tx_data_out_ready <= ip_tx_data_out_ready; -- in this state, we can accept user data if IP TX rdy
if ip_tx_data_out_ready = '1' then
if udp_txi.data.data_out_valid = '1' or tx_count = x"000" then
-- only increment if ready and valid has been subsequently established, otherwise data count moves on too fast
if unsigned(tx_count) = unsigned(udp_txi.hdr.data_length) then
-- TX terminated due to count - end normally
set_last <= '1';
tx_data <= udp_txi.data.data_out;
next_tx_result <= UDPTX_RESULT_SENT; --11
set_ip_tx_start <= CLR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
elsif udp_txi.data.data_out_last = '1' then
-- terminate tx with error as got last from upstream before exhausting count
set_last <= '1';
tx_data <= udp_txi.data.data_out;
next_tx_result <= UDPTX_RESULT_ERR; --10
set_ip_tx_start <= CLR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
else
-- TX continues
tx_count_mode <= INCR;
tx_data <= udp_txi.data.data_out;
end if;
end if;
end if;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
tx_sequential : process (clk,reset,data_out_ready_reg)
begin
if rising_edge(clk) then
data_out_ready_reg <= ip_tx_data_out_ready;
else
data_out_ready_reg <= data_out_ready_reg;
end if;
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
udp_tx_state <= IDLE;
tx_count <= x"0000";
tx_result_reg <= IPTX_RESULT_NONE;
ip_tx_start_reg <= '0';
else
-- Next udp_tx_state processing
if set_tx_state = '1' then
udp_tx_state <= next_tx_state;
else
udp_tx_state <= udp_tx_state;
end if;
-- ip_tx_start_reg processing
case set_ip_tx_start is
when SET => ip_tx_start_reg <= '1';
when CLR => ip_tx_start_reg <= '0';
when HOLD => ip_tx_start_reg <= ip_tx_start_reg;
end case;
-- tx result processing
if set_tx_result = '1' then
tx_result_reg <= next_tx_result;
else
tx_result_reg <= tx_result_reg;
end if;
-- tx_count processing
case tx_count_mode is
when RST => tx_count <= x"0000";
when SET => tx_count <= tx_count_val;
when INCR => tx_count <= tx_count + 1;
when HOLD => tx_count <= tx_count;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 171f0e78aa42f11310f1883027aa83df | 0.507889 | 3.31726 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/arp_TX.vhd | 2 | 12,210 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_tx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle transmission of an ARP packet.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created - refactored this arp_tx module from the complete arp v0.02 module
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
entity arp_tx is
port (
-- control signals
send_I_have : in std_logic; -- pulse will be latched
arp_entry : in arp_entry_t; -- arp target for I_have req (will be latched)
send_who_has : in std_logic; -- pulse will be latched
ip_entry : in std_logic_vector (31 downto 0); -- IP target for who_has req (will be latched)
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
tx_clk : in std_logic;
reset : in std_logic
);
end arp_tx;
architecture Behavioral of arp_tx is
type count_mode_t is (RST, INCR, HOLD);
type set_clr_t is (SET, CLR, HOLD);
type tx_state_t is (IDLE, WAIT_MAC, SEND);
type tx_mode_t is (REPLY, REQUEST);
-- state variables
signal tx_mac_chn_reqd : std_logic;
signal tx_state : tx_state_t;
signal tx_count : unsigned (7 downto 0);
signal send_I_have_reg : std_logic;
signal send_who_has_reg : std_logic;
signal I_have_target : arp_entry_t; -- latched target for "I have" request
signal who_has_target : std_logic_vector (31 downto 0); -- latched IP for "who has" request
signal tx_mode : tx_mode_t; -- what sort of tx to make
signal target : arp_entry_t; -- target to send to
-- busses
signal next_tx_state : tx_state_t;
signal tx_mode_val : tx_mode_t;
signal target_val : arp_entry_t;
-- tx control signals
signal set_tx_state : std_logic;
signal tx_count_mode : count_mode_t;
signal set_chn_reqd : set_clr_t;
signal kill_data_out_valid : std_logic;
signal set_send_I_have : set_clr_t;
signal set_send_who_has : set_clr_t;
signal set_tx_mode : std_logic;
signal set_target : std_logic;
begin
tx_combinatorial : process (
-- input signals
send_I_have, send_who_has, arp_entry, ip_entry, data_out_ready, mac_tx_granted,
our_mac_address, our_ip_address, reset,
-- state variables
tx_state, tx_count, tx_mac_chn_reqd, I_have_target, who_has_target,
send_I_have_reg, send_who_has_reg, tx_mode, target,
-- busses
next_tx_state, tx_mode_val, target_val,
-- control signals
tx_count_mode, kill_data_out_valid, set_send_I_have, set_send_who_has,
set_chn_reqd, set_tx_mode, set_target
)
begin
-- set output followers
mac_tx_req <= tx_mac_chn_reqd;
-- set combinatorial output defaults
data_out_first <= '0';
case tx_state is
when SEND =>
if data_out_ready = '1' and kill_data_out_valid = '0' then
data_out_valid <= '1';
else
data_out_valid <= '0';
end if;
when others => data_out_valid <= '0';
end case;
-- set bus defaults
next_tx_state <= IDLE;
tx_mode_val <= REPLY;
target_val.ip <= (others => '0');
target_val.mac <= (others => '1');
-- set signal defaults
set_tx_state <= '0';
tx_count_mode <= HOLD;
data_out <= x"00";
data_out_last <= '0';
set_chn_reqd <= HOLD;
kill_data_out_valid <= '0';
set_send_I_have <= HOLD;
set_send_who_has <= HOLD;
set_tx_mode <= '0';
set_target <= '0';
-- process requests in regardless of FSM state
if send_I_have = '1' then
set_send_I_have <= SET;
end if;
if send_who_has = '1' then
set_send_who_has <= SET;
end if;
-- TX FSM
case tx_state is
when IDLE =>
tx_count_mode <= RST;
if send_I_have_reg = '1' then
set_chn_reqd <= SET;
tx_mode_val <= REPLY;
set_tx_mode <= '1';
target_val <= I_have_target;
set_target <= '1';
set_send_I_have <= CLR;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
elsif send_who_has_reg = '1' then
set_chn_reqd <= SET;
tx_mode_val <= REQUEST;
set_tx_mode <= '1';
target_val.ip <= who_has_target;
target_val.mac <= (others => '1');
set_target <= '1';
set_send_who_has <= CLR;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
else
set_chn_reqd <= CLR;
end if;
when WAIT_MAC =>
tx_count_mode <= RST;
if mac_tx_granted = '1' then
next_tx_state <= SEND;
set_tx_state <= '1';
end if;
-- TODO - should handle timeout here
when SEND =>
if data_out_ready = '1' then
tx_count_mode <= INCR;
end if;
case tx_count is
when x"00" => data_out_first <= data_out_ready;
data_out <= target.mac (47 downto 40); -- target mac--data_out <= x"ff"; -- dst = broadcast
when x"01" => data_out <= target.mac (39 downto 32); --data_out <= x"ff";
when x"02" => data_out <= target.mac (31 downto 24); --data_out <= x"ff";
when x"03" => data_out <= target.mac (23 downto 16); --data_out <= x"ff";
when x"04" => data_out <= target.mac (15 downto 8); --data_out <= x"ff";
when x"05" => data_out <= target.mac (7 downto 0); --data_out <= x"ff";
when x"06" => data_out <= our_mac_address (47 downto 40); -- src = our mac
when x"07" => data_out <= our_mac_address (39 downto 32);
when x"08" => data_out <= our_mac_address (31 downto 24);
when x"09" => data_out <= our_mac_address (23 downto 16);
when x"0a" => data_out <= our_mac_address (15 downto 8);
when x"0b" => data_out <= our_mac_address (7 downto 0);
when x"0c" => data_out <= x"08"; -- pkt type = 0806 : ARP
when x"0d" => data_out <= x"06";
when x"0e" => data_out <= x"00"; -- HW type = 0001 : eth
when x"0f" => data_out <= x"01";
when x"10" => data_out <= x"08"; -- protocol = 0800 : ip
when x"11" => data_out <= x"00";
when x"12" => data_out <= x"06"; -- HW size = 06
when x"13" => data_out <= x"04"; -- prot size = 04
when x"14" => data_out <= x"00"; -- opcode =
when x"15" =>
if tx_mode = REPLY then
data_out <= x"02"; -- 02 : REPLY
else
data_out <= x"01"; -- 01 : REQ
end if;
when x"16" => data_out <= our_mac_address (47 downto 40); -- sender mac
when x"17" => data_out <= our_mac_address (39 downto 32);
when x"18" => data_out <= our_mac_address (31 downto 24);
when x"19" => data_out <= our_mac_address (23 downto 16);
when x"1a" => data_out <= our_mac_address (15 downto 8);
when x"1b" => data_out <= our_mac_address (7 downto 0);
when x"1c" => data_out <= our_ip_address (31 downto 24); -- sender ip
when x"1d" => data_out <= our_ip_address (23 downto 16);
when x"1e" => data_out <= our_ip_address (15 downto 8);
when x"1f" => data_out <= our_ip_address (7 downto 0);
when x"20" => data_out <= target.mac (47 downto 40); -- target mac
when x"21" => data_out <= target.mac (39 downto 32);
when x"22" => data_out <= target.mac (31 downto 24);
when x"23" => data_out <= target.mac (23 downto 16);
when x"24" => data_out <= target.mac (15 downto 8);
when x"25" => data_out <= target.mac (7 downto 0);
when x"26" => data_out <= target.ip (31 downto 24); -- target ip
when x"27" => data_out <= target.ip (23 downto 16);
when x"28" => data_out <= target.ip (15 downto 8);
when x"29" =>
data_out <= target.ip(7 downto 0);
data_out_last <= '1';
when x"2a" =>
kill_data_out_valid <= '1'; -- data is no longer valid
next_tx_state <= IDLE;
set_tx_state <= '1';
when others =>
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end case;
end process;
tx_sequential : process (tx_clk)
begin
if rising_edge(tx_clk) then
if reset = '1' then
-- reset state variables
tx_state <= IDLE;
tx_count <= (others => '0');
tx_mac_chn_reqd <= '0';
send_I_have_reg <= '0';
send_who_has_reg <= '0';
who_has_target <= (others => '0');
I_have_target.ip <= (others => '0');
I_have_target.mac <= (others => '0');
target.ip <= (others => '0');
target.mac <= (others => '1');
else
-- normal (non reset) processing
-- Next tx_state processing
if set_tx_state = '1' then
tx_state <= next_tx_state;
else
tx_state <= tx_state;
end if;
-- input request latching
case set_send_I_have is
when SET =>
send_I_have_reg <= '1';
I_have_target <= arp_entry;
when CLR =>
send_I_have_reg <= '0';
I_have_target <= I_have_target;
when HOLD =>
send_I_have_reg <= send_I_have_reg;
I_have_target <= I_have_target;
end case;
case set_send_who_has is
when SET =>
send_who_has_reg <= '1';
who_has_target <= ip_entry;
when CLR =>
send_who_has_reg <= '0';
who_has_target <= who_has_target;
when HOLD =>
send_who_has_reg <= send_who_has_reg;
who_has_target <= who_has_target;
end case;
-- tx mode
if set_tx_mode = '1' then
tx_mode <= tx_mode_val;
else
tx_mode <= tx_mode;
end if;
-- target latching
if set_target = '1' then
target <= target_val;
else
target <= target;
end if;
-- tx_count processing
case tx_count_mode is
when RST =>
tx_count <= x"00";
when INCR =>
tx_count <= tx_count + 1;
when HOLD =>
tx_count <= tx_count;
end case;
-- control access request to mac tx chn
case set_chn_reqd is
when SET => tx_mac_chn_reqd <= '1';
when CLR => tx_mac_chn_reqd <= '0';
when HOLD => tx_mac_chn_reqd <= tx_mac_chn_reqd;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | fba7fbcc46ac44c5d8667945d0483073 | 0.499181 | 3.4375 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/MUX4.vhd | 4 | 1,344 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 10/07/2014
--! Module Name: MUX4
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--! MUX 4x1
entity MUX4 is
Port (
data0 : in std_logic;
data1 : in std_logic;
data2 : in std_logic;
data3 : in std_logic;
sel : in std_logic_vector(1 downto 0);
data_out : out std_logic
);
end MUX4;
--architecture low_level_MUX4 of MUX4 is
--begin
--lut_inst: LUT6
--generic map (INIT => X"FF00F0F0CCCCAAAA")
--port map(
-- I0 => data0,
-- I1 => data1,
-- I2 => data2,
-- I3 => data3,
-- I4 => sel(0),
-- I5 => sel(1),
-- O => data_out
-- );
--end low_level_MUX4;
architecture behavioral of MUX4 is
begin
process(data0,data1,data2,data3,sel)
begin
case sel is
when "00" => data_out <= data0;
when "01" => data_out <= data1;
when "10" => data_out <= data2;
when "11" => data_out <= data3;
when others =>
end case;
end process;
end behavioral;
| gpl-3.0 | 5aeda551a12e38ef4db37c4aed0a1064 | 0.491815 | 3.03386 | false | false | false | false |
adelapie/noekeon | tb_theta.vhd | 5 | 3,723 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_theta IS
END tb_theta;
ARCHITECTURE behavior OF tb_theta IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT theta
PORT(a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: theta PORT MAP (
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
a_0_in <= X"200d6ff9";
a_1_in <= X"02667af7";
a_2_in <= X"3a345347";
a_3_in <= X"2cd90d69";
k_0_in <= X"fd178c4d";
k_1_in <= X"fc0df5d7";
k_2_in <= X"7a728549";
k_3_in <= X"eaa289dd";
wait for clk_period;
assert a_0_out = X"61396C13"
report "THETA ERROR (a_0)" severity FAILURE;
assert a_1_out = X"637434B8"
report "THETA ERROR (a_1)" severity FAILURE;
assert a_2_out = X"FC6559A9"
report "THETA ERROR (a_2)" severity FAILURE;
assert a_3_out = X"5B643F2C"
report "THETA ERROR (a_3)" severity FAILURE;
wait;
end process;
END;
| gpl-3.0 | a82d452154477d9bb8c7d1e77b1950c4 | 0.591727 | 2.954762 | false | false | false | false |
adelapie/noekeon | rc_gen.vhd | 5 | 1,656 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rc_gen is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- 0 (enc), 1 (dec)
rc_out : out std_logic_vector(7 downto 0));
end rc_gen;
architecture Behavioral of rc_gen is
signal rc_s : std_logic_vector(7 downto 0);
begin
pr_gen: process(clk, rst, enc)
begin
if rising_edge(clk) then
if rst = '1' then
if enc = '0' then
rc_s <= X"80";
else
rc_s <= X"D4";
end if;
else
if enc = '0' then
if ((rc_s and X"80") = X"00") then
rc_s <= rc_s(6 downto 0) & '0';
else
rc_s <= (rc_s(6 downto 0) & '0') xor X"1B";
end if;
else
if ((rc_s and X"01") = X"00") then
rc_s <= '0' & rc_s(7 downto 1);
else
rc_s <= ('0' & rc_s(7 downto 1)) xor X"8D";
end if;
end if;
end if;
end if;
end process;
rc_out <= rc_s;
end Behavioral;
| gpl-3.0 | 89e99a79b163d600812cfbf64383d0d9 | 0.600845 | 3.055351 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/UDP_RX.vhd | 2 | 12,625 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 5 June 2011
-- Design Name:
-- Module Name: UDP_RX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple UDP RX
-- doesnt check the checsum
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Improved error handling
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
entity UDP_RX is
port (
-- UDP Layer signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- system signals
clk : in std_logic;
reset : in std_logic;
-- IP layer RX signals
ip_rx_start : in std_logic; -- indicates receipt of ip header
ip_rx : in ipv4_rx_type
);
end UDP_RX;
architecture Behavioral of UDP_RX is
type rx_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END, ERR);
type rx_event_type is (NO_EVENT, DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_count_mode_type is (RST, INCR, SET_VAL, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- state variables
signal rx_state : rx_state_type;
signal rx_count : unsigned (15 downto 0);
signal src_port : std_logic_vector (15 downto 0); -- src port captured from input
signal dst_port : std_logic_vector (15 downto 0); -- dst port captured from input
signal data_len : std_logic_vector (15 downto 0); -- user data length captured from input
signal udp_rx_start_reg : std_logic; -- indicates start of user data
signal hdr_valid_reg : std_logic; -- indicates that hdr data is valid
signal src_ip_addr : std_logic_vector (31 downto 0); -- captured from IP hdr
-- rx control signals
signal next_rx_state : rx_state_type;
signal set_rx_state : std_logic;
signal rx_event : rx_event_type;
signal rx_count_mode : settable_count_mode_type;
signal rx_count_val : unsigned (15 downto 0);
signal set_sph : std_logic;
signal set_spl : std_logic;
signal set_dph : std_logic;
signal set_dpl : std_logic;
signal set_len_H : std_logic;
signal set_len_L : std_logic;
signal set_udp_rx_start : set_clr_type;
signal set_hdr_valid : set_clr_type;
signal dataval : std_logic_vector (7 downto 0);
signal set_pkt_cnt : count_mode_type;
signal set_src_ip : std_logic;
signal set_data_last : std_logic;
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | source port number | dest port number |
-- | | |
-- --------------------------------------------------------------------------------------------
-- | length (bytes) | checksum |
-- | (header and data combined) | |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
rx_combinatorial : process (
-- input signals
ip_rx, ip_rx_start,
-- state variables
rx_state, rx_count, src_port, dst_port, data_len, udp_rx_start_reg, hdr_valid_reg, src_ip_addr,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode, rx_count_val,
set_sph, set_spl, set_dph, set_dpl, set_len_H, set_len_L, set_data_last,
set_udp_rx_start, set_hdr_valid, dataval, set_pkt_cnt, set_src_ip
)
begin
-- set output followers
udp_rx_start <= udp_rx_start_reg;
udp_rxo.hdr.is_valid <= hdr_valid_reg;
udp_rxo.hdr.data_length <= data_len;
udp_rxo.hdr.src_port <= src_port;
udp_rxo.hdr.dst_port <= dst_port;
udp_rxo.hdr.src_ip_addr <= src_ip_addr;
-- transfer data upstream if in user data phase
if rx_state = USER_DATA then
udp_rxo.data.data_in <= ip_rx.data.data_in;
udp_rxo.data.data_in_valid <= ip_rx.data.data_in_valid;
udp_rxo.data.data_in_last <= set_data_last;
else
udp_rxo.data.data_in <= (others => '0');
udp_rxo.data.data_in_valid <= '0';
udp_rxo.data.data_in_last <= '0';
end if;
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_sph <= '0';
set_spl <= '0';
set_dph <= '0';
set_dpl <= '0';
set_len_H <= '0';
set_len_L <= '0';
set_udp_rx_start <= HOLD;
set_hdr_valid <= HOLD;
dataval <= (others => '0');
set_src_ip <= '0';
rx_count_val <= (others => '0');
set_data_last <= '0';
-- determine event (if any)
if ip_rx.data.data_in_valid = '1' then
rx_event <= DATA;
dataval <= ip_rx.data.data_in;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if ip_rx.hdr.protocol = x"11" then
-- UDP protocol
rx_count_mode <= INCR;
set_hdr_valid <= CLR;
set_src_ip <= '1';
set_sph <= '1';
next_rx_state <= UDP_HDR;
set_rx_state <= '1';
else
-- non-UDP protocol - ignore this pkt
set_hdr_valid <= CLR;
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
end case;
when UDP_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if rx_count = x"0007" then
rx_count_mode <= SET_VAL;
rx_count_val <= x"0001";
next_rx_state <= USER_DATA;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if ip_rx.data.data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
else
case rx_count is
when x"0000" => set_sph <= '1';
when x"0001" => set_spl <= '1';
when x"0002" => set_dph <= '1';
when x"0003" => set_dpl <= '1';
when x"0004" => set_len_H <= '1';
when x"0005" => set_len_L <= '1'; set_hdr_valid <= SET; -- header values are now valid, although the pkt may not be for us
when x"0006" => -- ignore checksum values
when x"0007" => set_udp_rx_start <= SET; -- indicate frame received
when others => -- ignore other bytes in udp header
end case;
end if;
end case;
when USER_DATA =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
-- note: data gets transfered upstream as part of "output followers" processing
if rx_count = unsigned(data_len) then
set_udp_rx_start <= CLR;
rx_count_mode <= RST;
set_data_last <= '1';
if ip_rx.data.data_in_last = '1' then
next_rx_state <= IDLE;
set_udp_rx_start <= CLR;
else
next_rx_state <= WAIT_END;
end if;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
-- check for early frame termination
-- TODO need to mark frame as errored
if ip_rx.data.data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
set_data_last <= '1';
end if;
end if;
end case;
when ERR =>
if ip_rx.data.data_in_last = '0' then
next_rx_state <= WAIT_END;
set_rx_state <= '1';
else
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if ip_rx.data.data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
end case;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
rx_sequential : process (clk, reset)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"0000";
src_port <= (others => '0');
dst_port <= (others => '0');
data_len <= (others => '0');
udp_rx_start_reg <= '0';
hdr_valid_reg <= '0';
src_ip_addr <= (others => '0');
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST => rx_count <= x"0000";
when INCR => rx_count <= rx_count + 1;
when SET_VAL => rx_count <= rx_count_val;
when HOLD => rx_count <= rx_count;
end case;
-- port number capture
if (set_sph = '1') then src_port(15 downto 8) <= dataval; end if;
if (set_spl = '1') then src_port(7 downto 0) <= dataval; end if;
if (set_dph = '1') then dst_port(15 downto 8) <= dataval; end if;
if (set_dpl = '1') then dst_port(7 downto 0) <= dataval; end if;
if (set_len_H = '1') then
data_len (15 downto 8) <= dataval;
data_len (7 downto 0) <= x"00";
elsif (set_len_L = '1') then
-- compute data length, taking into account that we need to subtract the header length
data_len <= std_logic_vector(unsigned(data_len(15 downto 8) & dataval) - 8);
else
data_len <= data_len;
end if;
case set_udp_rx_start is
when SET => udp_rx_start_reg <= '1';
when CLR => udp_rx_start_reg <= '0';
when HOLD => udp_rx_start_reg <= udp_rx_start_reg;
end case;
-- capture src IP address
if set_src_ip = '1' then
src_ip_addr <= ip_rx.hdr.src_ip_addr;
else
src_ip_addr <= src_ip_addr;
end if;
case set_hdr_valid is
when SET => hdr_valid_reg <= '1';
when CLR => hdr_valid_reg <= '0';
when HOLD => hdr_valid_reg <= hdr_valid_reg;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | d1bef13bdbff1c4a91c2f673f422855a | 0.431525 | 4.020701 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/MUX4_Nbit.vhd | 4 | 1,276 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 10/07/2014
--! Module Name: MUX4_Nbit
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE,work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
library unisim;
use unisim.vcomponents.all;
--! MUX 4x1, 16 bit data
entity MUX4_Nbit is
generic (
N : integer := 16);
Port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
data2 : in std_logic_vector((N-1) downto 0);
data3 : in std_logic_vector((N-1) downto 0);
sel : in std_logic_vector(1 downto 0);
data_out : out std_logic_vector((N-1) downto 0)
);
end MUX4_Nbit;
architecture MUX4_Nbit_arc of MUX4_Nbit is
begin
process(data0,data1,data2,data3,sel)
begin
case sel is
when "00" => data_out <= data0;
when "01" => data_out <= data1;
when "10" => data_out <= data2;
when "11" => data_out <= data3;
when others =>
end case;
end process;
end MUX4_Nbit_arc;
| gpl-3.0 | 1ca0102456eae07806927bc5be3999a3 | 0.505486 | 3.197995 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Pulse_Extender/tb_pulse_extender.vhd | 1 | 6,157 | ----------------------------------------------------------------------------------------------------
-- Pulse Extender Test-bench
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tb_clockgen_pkg.all;
use work.pulse_extender_pkg.all;
--This module is a test-bench for simulating the pulse_extender module
entity tb_pulse_extender is
end tb_pulse_extender;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture sim of tb_pulse_extender is
signal rst : std_logic;
signal clk : std_logic;
signal stimulus : std_logic;
signal result_e0a0r0 : std_logic;
signal result_e0a0r1 : std_logic;
signal result_e0a1r0 : std_logic;
signal result_e0a1r1 : std_logic;
signal result_e1a0r0 : std_logic;
signal result_e1a0r1 : std_logic;
signal result_e1a1r0 : std_logic;
signal result_e1a1r1 : std_logic;
signal result_e4a0r0 : std_logic;
signal result_e4a0r1 : std_logic;
signal result_e4a1r0 : std_logic;
signal result_e4a1r1 : std_logic;
begin
--Instantiate clock generator
clk1 : tb_clockgen
generic map(PERIOD => 10ns,
DUTY_CYCLE => 0.50)
port map( clk => clk);
--UUT
e0a0r0 : pulse_extender
generic map(EXTEND_COUNT => 0,
ACTIVE_LEVEL => '0',
RESET_LEVEL => '0')
port map( clk => clk,
rst => rst,
pulse => stimulus,
extended_pulse => result_e0a0r0);
e0a0r1 : pulse_extender
generic map(EXTEND_COUNT => 0,
ACTIVE_LEVEL => '0',
RESET_LEVEL => '1')
port map( clk => clk,
rst => rst,
pulse => stimulus,
extended_pulse => result_e0a0r1);
e0a1r0 : pulse_extender
generic map(EXTEND_COUNT => 0,
ACTIVE_LEVEL => '1',
RESET_LEVEL => '0')
port map( clk => clk,
rst => rst,
pulse => stimulus,
extended_pulse => result_e0a1r0);
e0a1r1 : pulse_extender
generic map(EXTEND_COUNT => 0,
ACTIVE_LEVEL => '1',
RESET_LEVEL => '1')
port map( clk => clk,
rst => rst,
pulse => stimulus,
extended_pulse => result_e0a1r1);
e1a0r0 : pulse_extender
generic map(EXTEND_COUNT => 1,
ACTIVE_LEVEL => '0',
RESET_LEVEL => '0')
port map( clk => clk,
rst => rst,
pulse => stimulus,
extended_pulse => result_e1a0r0);
e1a0r1 : pulse_extender
generic map(EXTEND_COUNT => 1,
ACTIVE_LEVEL => '0',
RESET_LEVEL => '1')
port map( clk => clk,
rst => rst,
pulse => stimulus,
extended_pulse => result_e1a0r1);
e1a1r0 : pulse_extender
generic map(EXTEND_COUNT => 1,
ACTIVE_LEVEL => '1',
RESET_LEVEL => '0')
port map( clk => clk,
rst => rst,
pulse => stimulus,
extended_pulse => result_e1a1r0);
e1a1r1 : pulse_extender
generic map(EXTEND_COUNT => 1,
ACTIVE_LEVEL => '1',
RESET_LEVEL => '1')
port map( clk => clk,
rst => rst,
pulse => stimulus,
extended_pulse => result_e1a1r1);
e4a0r0 : pulse_extender
generic map(EXTEND_COUNT => 4,
ACTIVE_LEVEL => '0',
RESET_LEVEL => '0')
port map( clk => clk,
rst => rst,
pulse => stimulus,
extended_pulse => result_e4a0r0);
e4a0r1 : pulse_extender
generic map(EXTEND_COUNT => 4,
ACTIVE_LEVEL => '0',
RESET_LEVEL => '1')
port map( clk => clk,
rst => rst,
pulse => stimulus,
extended_pulse => result_e4a0r1);
e4a1r0 : pulse_extender
generic map(EXTEND_COUNT => 4,
ACTIVE_LEVEL => '1',
RESET_LEVEL => '0')
port map( clk => clk,
rst => rst,
pulse => stimulus,
extended_pulse => result_e4a1r0);
e4a1r1 : pulse_extender
generic map(EXTEND_COUNT => 4,
ACTIVE_LEVEL => '1',
RESET_LEVEL => '1')
port map( clk => clk,
rst => rst,
pulse => stimulus,
extended_pulse => result_e4a1r1);
--Main Process
main: process
begin
--Initializing
stimulus <= '0';
rst <= '1';
wait for 55ns;
rst <= '0';
--Wait for max (5) clock cycles
wait for 50ns;
--pulse for 1 clock cycle then wait for 5
stimulus <= '1';
wait for 10ns;
stimulus <= '0';
wait for 50ns;
--pulse for 2 clock cycles then wait for 5
stimulus <= '1';
wait for 20ns;
stimulus <= '0';
wait for 50ns;
--pulse for 4 clock cycles then wait for 5
stimulus <= '1';
wait for 40ns;
stimulus <= '0';
wait for 50ns;
wait;
end process;
end sim; | mit | 99e9453a18c4a2d5650e9d95e86129a9 | 0.413026 | 4.199864 | false | false | false | false |
HackLinux/ION | src/application/interfaces/ion_sram_interface.vhdl | 1 | 8,683 | --------------------------------------------------------------------------------
-- ion_sram16_interface.vhdl -- WB-to-16-bit-SRAM interface.
--------------------------------------------------------------------------------
--
-- The interface targets a specific SRAM chip, the 256Kx16 61LV25616 from ISSI.
-- This chip is representative of the class of SRAMs this module is meant for.
-- (And happens to be used in the DE-1 board we're targetting...)
--
-- REFERENCES
-- [1] http://www.issi.com/WW/pdf/61C256AL.pdf -- Target SRAM datasheet.
-- [2] ion_design_notes.pdf -- ION project design notes.
--------------------------------------------------------------------------------
--
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ION_SRAM16_INTERFACE is
generic(
-- Size of RAM in 16-bit words.
SRAM_SIZE : integer := 256 * 1024;
-- Wait states introduced in each read or write 16-bit cycle.
WAIT_CYCLES : integer := 3
);
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
-- Core WB interface (this module is a WB slave).
WB_MOSI_I : in t_wishbone_mosi;
WB_MISO_O : out t_wishbone_miso;
-- External SRAM interface.
SRAM_ADDR_O : out std_logic_vector(log2(SRAM_SIZE) downto 1);
SRAM_DATA_O : out std_logic_vector(15 downto 0);
SRAM_DATA_I : in std_logic_vector(15 downto 0);
SRAM_WEn_O : out std_logic;
SRAM_OEn_O : out std_logic;
SRAM_UBn_O : out std_logic;
SRAM_LBn_O : out std_logic;
SRAM_CEn_O : out std_logic;
SRAM_DRIVE_EN_O : out std_logic
);
end;
architecture rtl of ION_SRAM16_INTERFACE is
constant SRAM_ADDR_SIZE : integer := log2(SRAM_SIZE);
type t_sram_state is (
IDLE,
READ_0,
READ_0_HOLD,
READ_1,
READ_1_HOLD,
WRITE_0,
WRITE_0_HOLD,
WRITE_1,
WRITE_1_HOLD
);
signal ps, ns : t_sram_state;
signal wait_ctr : integer range 0 to WAIT_CYCLES;
signal wait_done : std_logic;
signal low_hword_reg : std_logic_vector(15 downto 0);
begin
-- Control state machine ---------------------------------------------------
control_state_machine_reg:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
ps <= IDLE;
else
ps <= ns;
end if;
end if;
end process control_state_machine_reg;
control_state_machine_transitions:
process(ps, wait_done, WB_MOSI_I)
begin
case ps is
when IDLE =>
if WB_MOSI_I.cyc = '1' and WB_MOSI_I.we = '0' then
ns <= READ_0;
elsif WB_MOSI_I.cyc = '1' and WB_MOSI_I.we = '1' then
ns <= WRITE_0;
else
ns <= ps;
end if;
when READ_0 =>
if wait_done='1' then
ns <= READ_0_HOLD;
else
ns <= ps;
end if;
when READ_0_HOLD =>
ns <= READ_1;
when READ_1 =>
if wait_done='1' then
ns <= READ_1_HOLD;
else
ns <= ps;
end if;
when READ_1_HOLD =>
ns <= IDLE;
when WRITE_0 =>
if wait_done='1' then
ns <= WRITE_0_HOLD;
else
ns <= ps;
end if;
when WRITE_0_HOLD =>
ns <= WRITE_1;
when WRITE_1 =>
if wait_done='1' then
ns <= WRITE_1_HOLD;
else
ns <= ps;
end if;
when WRITE_1_HOLD =>
ns <= IDLE;
when others =>
-- NOTE: We´re not detecting here a real derailed HW state machine,
-- only a buggy rtl.
ns <= IDLE;
end case;
end process control_state_machine_transitions;
-- Wait state counter ------------------------------------------------------
wait_cycle_counter_reg:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
wait_ctr <= WAIT_CYCLES;
else
if wait_ctr /= 0 then
wait_ctr <= wait_ctr - 1;
end if;
end if;
end if;
end process wait_cycle_counter_reg;
wait_done <= '1' when wait_ctr = 0 else '0';
-- External interface ------------------------------------------------------
with ps select SRAM_DRIVE_EN_O <=
'1' when WRITE_0,
'1' when WRITE_0_HOLD,
'1' when WRITE_1,
'1' when WRITE_1_HOLD,
'0' when others;
with ps select SRAM_CEn_O <=
'1' when IDLE,
'0' when others;
with ps select SRAM_UBn_O <=
'0' when READ_0 | READ_0_HOLD | READ_1 | READ_1_HOLD,
not WB_MOSI_I.sel(1) when WRITE_0 | WRITE_0_HOLD,
not WB_MOSI_I.sel(3) when WRITE_1 | WRITE_1_HOLD,
'1' when others;
with ps select SRAM_LBn_O <=
'0' when READ_0 | READ_0_HOLD | READ_1 | READ_1_HOLD,
not WB_MOSI_I.sel(0) when WRITE_0 | WRITE_0_HOLD,
not WB_MOSI_I.sel(2) when WRITE_1 | WRITE_1_HOLD,
'1' when others;
with ps select SRAM_OEn_O <=
'0' when READ_0 | READ_0_HOLD | READ_1 | READ_1_HOLD,
'1' when others;
with ps select SRAM_WEn_O <=
'0' when WRITE_0 | WRITE_1,
'1' when others;
with ps select SRAM_DATA_O <=
WB_MOSI_I.dat(31 downto 16) when WRITE_1 | WRITE_1_HOLD,
WB_MOSI_I.dat(15 downto 0) when others;
with ps select SRAM_ADDR_O(1) <=
'0' when READ_0 | READ_0_HOLD | WRITE_0 | WRITE_0_HOLD,
'1' when READ_1 | READ_1_HOLD | WRITE_1 | WRITE_1_HOLD,
'1' when others;
SRAM_ADDR_O(SRAM_ADDR_O'high downto 2) <= WB_MOSI_I.adr(SRAM_ADDR_O'high downto 2);
low_halfword_register:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if ps = READ_0 and wait_ctr=0 then
low_hword_reg <= SRAM_DATA_I;
end if;
end if;
end process low_halfword_register;
-- Wishbone interface ------------------------------------------------------
WB_MISO_O.stall <=
'1' when ps=IDLE and WB_MOSI_I.cyc='1' else
'1' when ps=READ_0 else
'1' when ps=READ_0_HOLD else
'1' when ps=READ_1 and wait_ctr/=0 else
'1' when ps=READ_1_HOLD and WB_MOSI_I.cyc='1' else
'1' when ps=WRITE_0 else
'1' when ps=WRITE_0_HOLD else
'1' when ps=WRITE_1 and wait_ctr/=0 else
'1' when ps=WRITE_1_HOLD and WB_MOSI_I.cyc='1' else
'0';
WB_MISO_O.ack <=
'1' when ps=READ_1 and wait_ctr=0 else
'1' when ps=WRITE_1 and wait_ctr=0 else
'0';
WB_MISO_O.dat <= SRAM_DATA_I & low_hword_reg;
end architecture rtl;
| lgpl-3.0 | 193fa22bb782d089d44b644051fcf534 | 0.479788 | 3.864263 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/readout/trigger.vhd | 1 | 8,167 | ----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Paris Moschovakos
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: trigger.vhd - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 1.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
use UNISIM.VComponents.all;
entity trigger is
Port (
clk_200 : in STD_LOGIC;
tren : in STD_LOGIC;
tr_hold : in STD_LOGIC;
trmode : in STD_LOGIC;
trext : in STD_LOGIC;
trint : in STD_LOGIC;
reset : in STD_LOGIC;
event_counter : out STD_LOGIC_VECTOR(31 DOWNTO 0);
tr_out : out STD_LOGIC
);
end trigger;
architecture Behavioral of trigger is
-- Signals
signal event_counter_i : std_logic_vector(31 downto 0) := ( others => '0' );
signal tr_out_i : std_logic := '0';
signal mode : std_logic;
signal trint_pre : std_logic := '0';
signal trext_pre : std_logic := '0';
signal tren_buff : std_logic := '0'; -- buffered enable signal
---------------------------------------------------------------------------------------------- Uncomment for hold window Start
-- signal hold_state : std_logic_vector(3 downto 0);
-- signal hold_cnt : std_logic_vector(31 downto 0);
-- signal start : std_logic;
-- signal hold : std_logic;
-- signal state : std_logic_vector(2 downto 0) := ( others => '0' );
---------------------------------------------------------------------------------------------- Uncomment for hold window End
-- Attributes
---------------------------------------------------------------------------------------------- Uncomment for hold window Start
-- constant delay : std_logic_vector(31 downto 0) := x"00000002"; -- Number of 200 MHz clock cycles to hold trigger in hex
---------------------------------------------------------------------------------------------- Uncomment for hold window End
begin
-- Processes
---------------------------------------------------------------------------------------------- Uncomment for hold window Start
--holdDelay: process (clk_200, reset, start, tr_out_i, trext, trint) -- state machine to manage delay
--begin
-- if (reset = '1') then
-- hold <= '0';
-- state <= ( others => '0' );
-- elsif rising_edge(clk_200) then
-- case state is
-- when "000" => -- Idle
-- if (start = '1') then -- wait for start signal
-- state <= "001";
-- else
-- state <= "000";
-- end if;
-- when "001" => -- st1
-- if (tr_out_i = '0') then -- trigger returned to zero, start the count
-- hold <= '1';
-- hold_cnt <= ( others => '0' ); -- reset the counter
-- state <= "010";
-- else
-- state <= "001";
-- end if;
-- when "010" => -- st2
-- if (hold_cnt = delay) then -- reached end of deadtime
-- if ((trext = '0' and mode = '1') or (trint = '0' and mode = '0')) then -- No current trigger
-- hold <= '0';
-- state <= "000";
-- else
-- state <= "011";
-- end if;
-- hold_cnt <= ( others => '0');
-- else
-- hold_cnt <= hold_cnt + '1';
-- end if;
-- when "011" => -- st3
-- if ((trext = '0' and mode = '1') or (trint = '0' and mode = '0')) then -- wait until missed trigger ends
-- state <= "000";
-- hold <= '0';
-- else
-- state <= "011";
-- end if;
-- when others =>
-- state <= "000";
-- end case ;
-- end if;
--end process;
--triggerLatch: process (tr_out_i, hold)
--begin
-- if (tr_out_i = '1' and hold = '0') then -- start of trigger
-- start <= '1';
-- else -- Release the start command
-- start <= '0';
-- end if;
--end process;
---------------------------------------------------------------------------------------------- Uncomment for hold window End
trenAnd: process(tren, tr_hold)
begin
if (tren = '1' and tr_hold = '0') then -- No hold command, trigger enabled
tren_buff <= '1';
else
tren_buff <= '0';
end if;
end process;
changeModeCommandProc: process (clk_200, reset, tren_buff, trmode)
begin
if rising_edge(clk_200) and reset = '0' then
if tren_buff = '1' then
if trmode = '0' then -- Internal trigger
mode <= '0';
else -- External trigger
mode <= '1';
end if;
end if;
end if;
end process;
triggerDistrSignalProc: process (reset, mode, trext, trint)
begin
if reset = '1' then
tr_out_i <= '0';
else
if mode = '0' then
if (tren_buff = '1' and trmode = '0' and trint = '1') then
tr_out_i <= '1';
elsif (trmode = '0' and trint = '0') then
tr_out_i <= '0';
else
tr_out_i <= '0';
end if;
else
if (tren_buff = '1' and trmode = '1' and trext = '1') then
tr_out_i <= '1';
elsif (trmode = '1' and trext = '0') then
tr_out_i <= '0';
else
tr_out_i <= '0';
end if;
end if;
end if;
end process;
eventCounterProc: process (clk_200, reset, mode, trext, trint)
begin
if reset = '1' or event_counter_i = x"FFFFFFFF" then
event_counter_i <= x"00000000";
else
if rising_edge(clk_200) then
if mode = '0' then
if (tren_buff = '1' and trmode = '0' and trint = '1' and trint_pre = '0') then
event_counter_i <= event_counter_i + 1;
trint_pre <= '1';
elsif (trmode = '0' and trint = '0') then
event_counter_i <= event_counter_i;
trint_pre <= '0';
else
event_counter_i <= event_counter_i;
end if;
else
if (tren_buff = '1' and trmode = '1' and trext = '1' and trext_pre = '0') then
event_counter_i <= event_counter_i + 1;
trext_pre <= '1';
elsif (trmode = '1' and trext = '0') then
event_counter_i <= event_counter_i;
trext_pre <= '0';
else
event_counter_i <= event_counter_i;
end if;
end if;
end if;
end if;
end process;
-- Signal assignment
event_counter <= event_counter_i;
tr_out <= tr_out_i;
-- Instantiations if any
end Behavioral; | gpl-3.0 | 99eb6dde75d414a3207fa4c1f8f42be6 | 0.388147 | 4.365045 | false | false | false | false |
HackLinux/ION | src/rtl/cpu/ion_muldiv.vhdl | 1 | 11,948 | --------------------------------------------------------------------------------
-- mips_muldiv.vhdl -- multiplier/divider module.
--------------------------------------------------------------------------------
--
-- The module can be synthesized in two versions differing in the implementation
-- of the multiplier:
--
-- 1.- Sequential multiplier, with MULT_TYPE = "FAST".
-- This option will infer a pipelined multiplier (2 stages) using whatever
-- DSP resources the underlying FPGA provides (e.g. DSP48 blocks).
-- 2.- Sequential Booth multiplier, with MULT_TYPE = "SEQUENTIAL".
-- This option will implement a Booth algorithm which takes 33 cycles to
-- compute a product, with no optimizations for leading signs, etc.
-- Some of the logic is shared with the division logic.
-- FIXME Sequential multiplier not implemented; only "FAST" is.
--
-- As for the division, it is implemented with a sequential algorithm.
-- which takes 33 clock cycles to perform either a signed or unsigned division.
--
-- A true, efficient signed division algorithm is somewhat complicated, so we
-- go the lazy route here: Compute ABS(A)/ABS(B) and then adjust the sign of the
-- quotient Q and remainder R according to these rules:
--
-- # The remainder has the same sign as the dividend.
-- # The quotient is positive if divisor and dividend have the same sign,
-- otherwise it's negative.
--
-- These rules match the C99 specs.
--------------------------------------------------------------------------------
-- FIXME sequential multiplier option not implemented.
-- The description of the multiplier above is that of Plasma's, which this
-- project has been using until recently. It will be offered as an option
-- in subsequent versions of this module.
--------------------------------------------------------------------------------
-- Copyright (C) 2014 Jose A. Ruiz and Debayan Paul.
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ION_MULDIV is
generic(
MULT_TYPE : string := "FAST"
);
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
A_I : in std_logic_vector(31 downto 0);
B_I : in std_logic_vector(31 downto 0);
MULT_FN_I : in t_mult_function;
C_MULT_O : out std_logic_vector(31 downto 0);
PAUSE_O : out std_logic);
end; --entity mult
architecture logic of ION_MULDIV is
-- Multiplier block signals.
signal ma, mb : signed(32 downto 0);
signal max, mbx : std_logic;
signal product : signed(65 downto 0);
signal product_p0 : signed(65 downto 0);
-- Divider block signals.
signal sign_reg : std_logic;
signal sign2_reg : std_logic;
signal negate_quot_reg : std_logic;
signal negate_rem_reg : std_logic;
signal aa_reg : std_logic_vector(31 downto 0);
signal bb_reg : std_logic_vector(31 downto 0);
signal upper_reg : std_logic_vector(31 downto 0);
signal lower_reg : std_logic_vector(31 downto 0);
signal sum : signed(32 downto 0);
signal sum_a : std_logic_vector(32 downto 0);
signal sum_b : std_logic_vector(32 downto 0);
signal a_neg : std_logic_vector(31 downto 0);
signal b_neg : std_logic_vector(31 downto 0);
---- State machine, control & interface signals.
type t_mdiv_state is (
S_IDLE, -- Block is idle.
S_MULT, -- Multiplication in progress (signer or unsigned).
S_DIVU, -- Unsigned division in progress.
S_DIVS -- Signed division in progress.
);
signal ps, ns : t_mdiv_state;
signal start_divu : std_logic;
signal start_divs : std_logic;
signal start_mult : std_logic;
signal counter : integer range 0 to 33;
signal hireg, loreg : signed(31 downto 0);
signal output : signed(31 downto 0);
begin
-- Output glue logic -------------------------------------------------------
with MULT_FN_I select output <=
loreg when MULT_READ_LO,
hireg when others;
C_MULT_O <= std_logic_vector(output);
PAUSE_O <= '0' when ps=S_IDLE else '1';
result_register:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if (ps=S_DIVU) and counter=0 then
hireg <= signed(upper_reg(31 downto 0));
loreg <= signed(lower_reg(31 downto 0));
elsif (ps=S_DIVS) and counter=0 then
if negate_rem_reg='1' then
hireg <= signed(not(upper_reg(31 downto 0))) + 1;
else
hireg <= signed(upper_reg(31 downto 0));
end if;
if negate_quot_reg='1' then
loreg <= signed(not(lower_reg(31 downto 0))) + 1;
else
loreg <= signed(lower_reg(31 downto 0));
end if;
elsif ps=S_MULT and counter=0 then
hireg <= product(63 downto 32);
loreg <= product(31 downto 0);
end if;
end if;
end process result_register;
-- Control state machine ---------------------------------------------------
state_register:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
ps <= S_IDLE;
else
ps <= ns;
end if;
end if;
end process state_register;
state_machine_transitions:
process(ns, MULT_FN_I, counter, start_divs, start_divu, start_mult)
begin
case ps is
when S_IDLE =>
if start_divs='1' then
ns <= S_DIVS;
elsif start_divu='1' then
ns <= S_DIVU;
elsif start_mult='1' then
ns <= S_MULT;
else
ns <= ps;
end if;
when S_MULT | S_DIVS | S_DIVU =>
if counter=0 then
ns <= S_IDLE;
else
ns <= ps;
end if;
when others =>
ns <= S_IDLE;
end case;
end process state_machine_transitions;
with MULT_FN_I select start_divs <=
'1' when MULT_SIGNED_DIVIDE,
'0' when others;
with MULT_FN_I select start_divu <=
'1' when MULT_DIVIDE,
'0' when others;
with MULT_FN_I select start_mult <=
'1' when MULT_MULT | MULT_SIGNED_MULT,
'0' when others;
cycle_counter:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
counter <= 0;
else
if ps=S_IDLE and start_mult='1' then
counter <= 1;
elsif ps=S_IDLE and (start_divs='1' or start_divu='1') then
counter <= 32;
elsif ps=S_DIVS or ps=S_DIVU or ps=S_MULT then
if counter > 0 then
counter <= counter - 1;
end if;
end if;
end if;
end if;
end process cycle_counter;
-- Multiplier --------------------------------------------------------------
max <= A_I(31) when MULT_FN_I = MULT_SIGNED_MULT or
MULT_FN_I = MULT_SIGNED_DIVIDE else '0';
mbx <= B_I(31) when MULT_FN_I = MULT_SIGNED_MULT or
MULT_FN_I = MULT_SIGNED_DIVIDE else '0';
ma <= signed(max & A_I);
mb <= signed(mbx & B_I);
pipelined_dedicated_multiplier:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
product_p0 <= ma * mb;
product <= product_p0;
end if;
end process pipelined_dedicated_multiplier;
-- Divider -----------------------------------------------------------------
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
aa_reg <= ZERO;
bb_reg <= ZERO;
upper_reg <= ZERO;
lower_reg <= ZERO;
else
if start_divu='1' then
-- Start unsigned division.
aa_reg <= B_I(0) & ZERO(30 downto 0);
bb_reg <= B_I;
upper_reg <= A_I;
negate_quot_reg <= '0';
negate_rem_reg <= '0';
elsif start_divs='1' then
-- Start signed division.
if B_I(31) = '0' then
aa_reg(31) <= B_I(0);
bb_reg <= B_I;
else
aa_reg(31) <= b_neg(0);
bb_reg <= b_neg;
end if;
if A_I(31) = '0' then
upper_reg <= A_I;
else
upper_reg <= a_neg;
end if;
aa_reg(30 downto 0) <= ZERO(30 downto 0);
negate_quot_reg <= A_I(31) xor B_I(31);
negate_rem_reg <= A_I(31);
else
-- Continue signed or unsigned division in course
if ps=S_DIVU or ps=S_DIVS then
if sum(32) = '0' and aa_reg /= ZERO and
bb_reg(31 downto 1) = ZERO(31 downto 1) then
upper_reg <= std_logic_vector(sum(31 downto 0));
lower_reg(0) <= '1';
else
lower_reg(0) <= '0';
end if;
aa_reg <= bb_reg(1) & aa_reg(31 downto 1);
lower_reg(31 downto 1) <= lower_reg(30 downto 0);
bb_reg <= '0' & bb_reg(31 downto 1);
end if;
end if;
end if;
end if;
end process;
-- Partial subtractor: subtract shifted divisor from dividend.
sum_a <= ('0' & upper_reg); -- No sign extension: MSB of sum is special
sum_b <= ('0' & aa_reg);
sum <= signed(sum_a) - signed(sum_b);
-- We'll use these negated input values for ABS(A_I) and ABS(B_I).
a_neg <= std_logic_vector(-signed(A_I));
b_neg <= std_logic_vector(-signed(B_I));
end; --architecture logic
| lgpl-3.0 | 97f7e63354ff97c3b121c3ab6c4b1f03 | 0.485353 | 4.290126 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN2.vhd | 1 | 4,930 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! 80 Mbps E-link processor, 2bit input @ clk40
entity EPROC_IN2 is
generic (
do_generate : boolean := true;
includeNoEncodingCase : boolean := true
);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
swap_inputbits : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (1 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN2;
architecture Behavioral of EPROC_IN2 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
signal edata_in_s : std_logic_vector (1 downto 0);
signal DATA_OUT_direct,DATA_OUT_8b10b_case,DATA_OUT_HDLC_case,DATA_OUT_s : std_logic_vector (9 downto 0);
signal DATA_RDY_direct,DATA_RDY_8b10b_case,DATA_RDY_HDLC_case,DATA_RDY_sig : std_logic;
signal RESTART_sig, rst_case00, rst_case01, rst_case10 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
--
in_sel: process(swap_inputbits,EDATA_IN)
begin
if swap_inputbits = '1' then
edata_in_s <= EDATA_IN(0) & EDATA_IN(1);
else
edata_in_s <= EDATA_IN;
end if;
end process;
--
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
--
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
direct_data_enabled: if includeNoEncodingCase = true generate
rst_case00 <= '0' when ((RESTART_sig = '0') and (ENCODING = "00")) else '1';
direct_data_case: entity work.EPROC_IN2_direct
port map(
bitCLK => bitCLK,
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => edata_in_s,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
end generate direct_data_enabled;
--
direct_data_disabled: if includeNoEncodingCase = false generate
DATA_RDY_direct <= '0';
DATA_OUT_direct <= (others=>'0');
end generate direct_data_disabled;
--
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= '0' when ((RESTART_sig = '0') and (ENCODING = "01")) else '1';
--
dec8b10b_case: entity work.EPROC_IN2_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => edata_in_s,
dataOUT => DATA_OUT_8b10b_case,
dataOUTrdy => DATA_RDY_8b10b_case,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
rst_case10 <= '0' when ((RESTART_sig = '0') and (ENCODING = "10")) else '1';
--
decHDLC_case: entity work.EPROC_IN2_HDLC
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case10,
edataIN => edata_in_s,
dataOUT => DATA_OUT_HDLC_case,
dataOUTrdy => DATA_RDY_HDLC_case
);
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_case,
data2 => DATA_OUT_HDLC_case,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_case,
data2 => DATA_RDY_HDLC_case,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 | 3d6b254ec04a6adc2520b0d1a1238be2 | 0.481136 | 3.665428 | false | false | false | false |
rkrajnc/minimig-mist | rtl/tg68/TG68_fast.vhd | 3 | 104,993 | ------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the 68000 software compatible Kernal of TG68 --
-- --
-- Copyright (c) 2007-2010 Tobias Gubener <[email protected]> --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- Revision 1.08 2010/06/14
-- Bugfix Movem with regmask==xFFFF
-- Add missing Illegal $4AFC
--
-- Revision 1.07 2009/10/02
-- Bugfix Movem with regmask==x0000
--
-- Revision 1.06 2009/02/10
-- Bugfix shift and rotations opcodes when the bitcount and the data are in the same register:
-- Example lsr.l D2,D2
-- Thanks to Peter Graf for report
--
-- Revision 1.05 2009/01/26
-- Implement missing RTR
-- Thanks to Peter Graf for report
--
-- Revision 1.04 2007/12/29
-- size improvement
-- change signal "microaddr" to one hot state machine
--
-- Revision 1.03 2007/12/21
-- Thanks to Andreas Ehliar
-- Split regfile to use blockram for registers
-- insert "WHEN OTHERS => null;" on END CASE;
--
-- Revision 1.02 2007/12/17
-- Bugfix jsr nn.w
--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
--
-- Revision 1.0 2007/11/05
-- Clean up code and first release
--
-- known bugs/todo:
-- Add CHK INSTRUCTION
-- full decode ILLEGAL INSTRUCTIONS
-- Add FC Output
-- add odd Address test
-- add TRACE
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TG68_fast is
port(clk : in std_logic;
reset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
test_IPL : in std_logic:='0'; --only for debugging
address : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
state_out : out std_logic_vector(1 downto 0);
LDS, UDS : out std_logic;
decodeOPC : buffer std_logic;
wr : out std_logic;
enaRDreg : in std_logic:='1';
enaWRreg : in std_logic:='1'
);
end TG68_fast;
architecture logic of TG68_fast is
signal state : std_logic_vector(1 downto 0);
signal clkena : std_logic;
signal clkenareg : std_logic;
signal TG68_PC : std_logic_vector(31 downto 0);
signal TG68_PC_add : std_logic_vector(31 downto 0);
signal memaddr : std_logic_vector(31 downto 0);
signal memaddr_in : std_logic_vector(31 downto 0);
signal ea_data : std_logic_vector(31 downto 0);
signal ea_data_OP1 : std_logic;
signal setaddrlong : std_logic;
signal OP1out, OP2out : std_logic_vector(31 downto 0);
signal OP1outbrief : std_logic_vector(15 downto 0);
signal OP1in : std_logic_vector(31 downto 0);
signal data_write_tmp : std_logic_vector(31 downto 0);
signal Xtmp : std_logic_vector(31 downto 0);
signal PC_dataa, PC_datab, PC_result : std_logic_vector(31 downto 0);
signal setregstore : std_logic;
signal datatype : std_logic_vector(1 downto 0);
signal longread : std_logic;
signal longreaddirect : std_logic;
signal long_done : std_logic;
signal nextpass : std_logic;
signal setnextpass : std_logic;
signal setdispbyte : std_logic;
signal setdisp : std_logic;
signal setdispbrief : std_logic;
signal regdirectsource : std_logic;
signal endOPC : std_logic;
signal postadd : std_logic;
signal presub : std_logic;
signal addsub_a : std_logic_vector(31 downto 0);
signal addsub_b : std_logic_vector(31 downto 0);
signal addsub_q : std_logic_vector(31 downto 0);
signal briefext : std_logic_vector(31 downto 0);
signal setbriefext : std_logic;
signal addsub : std_logic;
signal c_in : std_logic_vector(3 downto 0);
signal c_out : std_logic_vector(2 downto 0);
signal add_result : std_logic_vector(33 downto 0);
signal addsub_ofl : std_logic_vector(2 downto 0);
signal flag_z : std_logic_vector(2 downto 0);
signal last_data_read : std_logic_vector(15 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal registerin : std_logic_vector(31 downto 0);
signal reg_QA : std_logic_vector(31 downto 0);
signal reg_QB : std_logic_vector(31 downto 0);
signal Hwrena,Lwrena : std_logic;
signal Regwrena : std_logic;
signal rf_dest_addr : std_logic_vector(6 downto 0);
signal rf_source_addr : std_logic_vector(6 downto 0);
signal rf_dest_addr_tmp : std_logic_vector(6 downto 0);
signal rf_source_addr_tmp : std_logic_vector(6 downto 0);
signal opcode : std_logic_vector(15 downto 0);
signal laststate : std_logic_vector(1 downto 0);
signal setstate : std_logic_vector(1 downto 0);
signal mem_address : std_logic_vector(31 downto 0);
signal memaddr_a : std_logic_vector(31 downto 0);
signal mem_data_read : std_logic_vector(31 downto 0);
signal mem_data_write : std_logic_vector(31 downto 0);
signal set_mem_rega : std_logic;
signal data_read_ram : std_logic_vector(31 downto 0);
signal data_read_uart : std_logic_vector(7 downto 0);
signal counter_reg : std_logic_vector(31 downto 0);
signal TG68_PC_br8 : std_logic;
signal TG68_PC_brw : std_logic;
signal TG68_PC_nop : std_logic;
signal setgetbrief : std_logic;
signal getbrief : std_logic;
signal brief : std_logic_vector(15 downto 0);
signal dest_areg : std_logic;
signal source_areg : std_logic;
signal data_is_source : std_logic;
signal set_store_in_tmp : std_logic;
signal store_in_tmp : std_logic;
signal write_back : std_logic;
signal setaddsub : std_logic;
signal setstackaddr : std_logic;
signal writePC : std_logic;
signal writePC_add : std_logic;
signal set_TG68_PC_dec: std_logic;
signal TG68_PC_dec : std_logic_vector(1 downto 0);
signal directPC : std_logic;
signal set_directPC : std_logic;
signal execOPC : std_logic;
signal fetchOPC : std_logic;
signal Flags : std_logic_vector(15 downto 0); --T.S..III ...XNZVC
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal exec_ADD : std_logic;
signal exec_OR : std_logic;
signal exec_AND : std_logic;
signal exec_EOR : std_logic;
signal exec_MOVE : std_logic;
signal exec_MOVEQ : std_logic;
signal exec_MOVESR : std_logic;
signal exec_DIRECT : std_logic;
signal exec_ADDQ : std_logic;
signal exec_CMP : std_logic;
signal exec_ROT : std_logic;
signal exec_exg : std_logic;
signal exec_swap : std_logic;
signal exec_write_back: std_logic;
signal exec_tas : std_logic;
signal exec_EXT : std_logic;
signal exec_ABCD : std_logic;
signal exec_SBCD : std_logic;
signal exec_MULU : std_logic;
signal exec_DIVU : std_logic;
signal exec_Scc : std_logic;
signal exec_CPMAW : std_logic;
signal set_exec_ADD : std_logic;
signal set_exec_OR : std_logic;
signal set_exec_AND : std_logic;
signal set_exec_EOR : std_logic;
signal set_exec_MOVE : std_logic;
signal set_exec_MOVEQ : std_logic;
signal set_exec_MOVESR: std_logic;
signal set_exec_ADDQ : std_logic;
signal set_exec_CMP : std_logic;
signal set_exec_ROT : std_logic;
signal set_exec_tas : std_logic;
signal set_exec_EXT : std_logic;
signal set_exec_ABCD : std_logic;
signal set_exec_SBCD : std_logic;
signal set_exec_MULU : std_logic;
signal set_exec_DIVU : std_logic;
signal set_exec_Scc : std_logic;
signal set_exec_CPMAW : std_logic;
signal condition : std_logic;
signal OP2out_one : std_logic;
signal OP1out_zero : std_logic;
signal ea_to_pc : std_logic;
signal ea_build : std_logic;
signal ea_only : std_logic;
signal get_ea_now : std_logic;
signal source_lowbits : std_logic;
signal dest_hbits : std_logic;
signal rot_rot : std_logic;
signal rot_lsb : std_logic;
signal rot_msb : std_logic;
signal rot_XC : std_logic;
signal set_rot_nop : std_logic;
signal rot_nop : std_logic;
signal rot_out : std_logic_vector(31 downto 0);
signal rot_bits : std_logic_vector(1 downto 0);
signal rot_cnt : std_logic_vector(5 downto 0);
signal set_rot_cnt : std_logic_vector(5 downto 0);
signal movem_busy : std_logic;
signal set_movem_busy : std_logic;
signal movem_addr : std_logic;
signal movem_regaddr : std_logic_vector(3 downto 0);
signal movem_mask : std_logic_vector(15 downto 0);
signal set_get_movem_mask : std_logic;
signal get_movem_mask : std_logic;
signal maskzero : std_logic;
signal test_maskzero : std_logic;
signal movem_muxa : std_logic_vector(7 downto 0);
signal movem_muxb : std_logic_vector(3 downto 0);
signal movem_muxc : std_logic_vector(1 downto 0);
signal movem_presub : std_logic;
signal save_memaddr : std_logic;
signal movem_bits : std_logic_vector(4 downto 0);
signal ea_calc_b : std_logic_vector(31 downto 0);
signal set_mem_addsub : std_logic;
signal bit_bits : std_logic_vector(1 downto 0);
signal bit_number_reg : std_logic_vector(4 downto 0);
signal bit_number : std_logic_vector(4 downto 0);
signal exec_Bits : std_logic;
signal bits_out : std_logic_vector(31 downto 0);
signal one_bit_in : std_logic;
signal one_bit_out : std_logic;
signal set_get_bitnumber : std_logic;
signal get_bitnumber : std_logic;
signal mem_byte : std_logic;
signal wait_mem_byte : std_logic;
signal movepl : std_logic;
signal movepw : std_logic;
signal set_movepl : std_logic;
signal set_movepw : std_logic;
signal set_direct_data: std_logic;
signal use_direct_data: std_logic;
signal direct_data : std_logic;
signal set_get_extendedOPC : std_logic;
signal get_extendedOPC: std_logic;
signal setstate_delay : std_logic_vector(1 downto 0);
signal setstate_mux : std_logic_vector(1 downto 0);
signal use_XZFlag : std_logic;
signal use_XFlag : std_logic;
signal dummy_a : std_logic_vector(8 downto 0);
signal niba_l : std_logic_vector(5 downto 0);
signal niba_h : std_logic_vector(5 downto 0);
signal niba_lc : std_logic;
signal niba_hc : std_logic;
signal bcda_lc : std_logic;
signal bcda_hc : std_logic;
signal dummy_s : std_logic_vector(8 downto 0);
signal nibs_l : std_logic_vector(5 downto 0);
signal nibs_h : std_logic_vector(5 downto 0);
signal nibs_lc : std_logic;
signal nibs_hc : std_logic;
signal dummy_mulu : std_logic_vector(31 downto 0);
signal dummy_div : std_logic_vector(31 downto 0);
signal dummy_div_sub : std_logic_vector(16 downto 0);
signal dummy_div_over : std_logic_vector(16 downto 0);
signal set_V_Flag : std_logic;
signal OP1sign : std_logic;
signal set_sign : std_logic;
signal sign : std_logic;
signal sign2 : std_logic;
signal muls_msb : std_logic;
signal mulu_reg : std_logic_vector(31 downto 0);
signal div_reg : std_logic_vector(31 downto 0);
signal div_sign : std_logic;
signal div_quot : std_logic_vector(31 downto 0);
signal div_ovl : std_logic;
signal pre_V_Flag : std_logic;
signal set_vectoraddr : std_logic;
signal writeSR : std_logic;
signal trap_illegal : std_logic;
signal trap_priv : std_logic;
signal trap_1010 : std_logic;
signal trap_1111 : std_logic;
signal trap_trap : std_logic;
signal trap_trapv : std_logic;
signal trap_interrupt : std_logic;
signal trapmake : std_logic;
signal trapd : std_logic;
-- signal trap_PC : std_logic_vector(31 downto 0);
signal trap_SR : std_logic_vector(15 downto 0);
signal set_directSR : std_logic;
signal directSR : std_logic;
signal set_directCCR : std_logic;
signal directCCR : std_logic;
signal set_stop : std_logic;
signal stop : std_logic;
signal trap_vector : std_logic_vector(31 downto 0);
signal to_USP : std_logic;
signal from_USP : std_logic;
signal to_SR : std_logic;
signal from_SR : std_logic;
signal illegal_write_mode : std_logic;
signal illegal_read_mode : std_logic;
signal illegal_byteaddr : std_logic;
signal use_SP : std_logic;
signal no_Flags : std_logic;
signal IPL_nr : std_logic_vector(2 downto 0);
signal rIPL_nr : std_logic_vector(2 downto 0);
signal interrupt : std_logic;
signal SVmode : std_logic;
signal trap_chk : std_logic;
signal test_delay : std_logic_vector(2 downto 0);
signal set_PCmarker : std_logic;
signal PCmarker : std_logic;
signal set_Z_error : std_logic;
signal Z_error : std_logic;
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_dAn2, ld_AnXn1, ld_AnXn2, ld_AnXn3, st_dAn1, st_dAn2,
st_AnXn1, st_AnXn2, st_AnXn3, bra1, bra2, bsr1, bsr2, dbcc1, dbcc2,
movem, andi, op_AxAy, cmpm, link, int1, int2, int3, int4, rte, trap1, trap2, trap3,
movep1, movep2, movep3, movep4, movep5, init1, init2,
mul1, mul2, mul3, mul4, mul5, mul6, mul7, mul8, mul9, mul10, mul11, mul12, mul13, mul14, mul15,
div1, div2, div3, div4, div5, div6, div7, div8, div9, div10, div11, div12, div13, div14, div15 );
signal micro_state : micro_states;
signal next_micro_state : micro_states;
type regfile_t is array(0 to 16) of std_logic_vector(15 downto 0);
signal regfile_low : regfile_t;
signal regfile_high : regfile_t;
signal RWindex_A : integer range 0 to 16;
signal RWindex_B : integer range 0 to 16;
BEGIN
-----------------------------------------------------------------------------
-- Registerfile
-----------------------------------------------------------------------------
RWindex_A <= conv_integer(rf_dest_addr(4)&(rf_dest_addr(3 downto 0) XOR "1111"));
RWindex_B <= conv_integer(rf_source_addr(4)&(rf_source_addr(3 downto 0) XOR "1111"));
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF clkenareg='1' THEN
-- IF falling_edge(clk) THEN
-- IF clkena='1' THEN
reg_QA <= regfile_high(RWindex_A) & regfile_low(RWindex_A);
reg_QB <= regfile_high(RWindex_B) & regfile_low(RWindex_B);
END IF;
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF Lwrena='1' THEN
regfile_low(RWindex_A) <= registerin(15 downto 0);
END IF;
IF Hwrena='1' THEN
regfile_high(RWindex_A) <= registerin(31 downto 16);
END IF;
END IF;
END IF;
END PROCESS;
address <= TG68_PC when state="00" else X"ffffffff" when state="01" else memaddr;
LDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='1') AND state/="01" ELSE '1';
UDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='0') AND state/="01" ELSE '1';
state_out <= state;
wr <= '0' WHEN state="11" ELSE '1';
IPL_nr <= NOT IPL;
-----------------------------------------------------------------------------
-- "ALU"
-----------------------------------------------------------------------------
PROCESS (addsub_a, addsub_b, addsub, add_result, c_in)
BEGIN
IF addsub='1' THEN --ADD
add_result <= (('0'&addsub_a&c_in(0))+('0'&addsub_b&c_in(0)));
ELSE --SUB
add_result <= (('0'&addsub_a&'0')-('0'&addsub_b&c_in(0)));
END IF;
addsub_q <= add_result(32 downto 1);
c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
c_in(3) <= add_result(33);
addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte
addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word
addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long
c_out <= c_in(3 downto 1);
END PROCESS;
-----------------------------------------------------------------------------
-- MEM_IO
-----------------------------------------------------------------------------
PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, memaddr, memaddr_a, set_mem_addsub, movem_presub,
movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
data_write_tmp, addsub_q, set_vectoraddr, trap_vector, interrupt, enaWRreg, enaRDreg)
BEGIN
clkena <= clkena_in AND NOT longread AND NOT get_extendedOPC AND enaWRreg;
clkenareg <= clkena_in AND NOT longread AND NOT get_extendedOPC AND enaRDreg;
IF rising_edge(clk) THEN
IF clkena='1' THEN
trap_vector(31 downto 8) <= (others => '0');
-- IF trap_addr_fault='1' THEN
-- trap_vector(7 downto 0) <= X"08";
-- END IF;
-- IF trap_addr_error='1' THEN
-- trap_vector(7 downto 0) <= X"0C";
-- END IF;
IF trap_illegal='1' THEN
trap_vector(7 downto 0) <= X"10";
END IF;
IF z_error='1' THEN
trap_vector(7 downto 0) <= X"14";
END IF;
-- IF trap_chk='1' THEN
-- trap_vector(7 downto 0) <= X"18";
-- END IF;
IF trap_trapv='1' THEN
trap_vector(7 downto 0) <= X"1C";
END IF;
IF trap_priv='1' THEN
trap_vector(7 downto 0) <= X"20";
END IF;
-- IF trap_trace='1' THEN
-- trap_vector(7 downto 0) <= X"24";
-- END IF;
IF trap_1010='1' THEN
trap_vector(7 downto 0) <= X"28";
END IF;
IF trap_1111='1' THEN
trap_vector(7 downto 0) <= X"2C";
END IF;
IF trap_trap='1' THEN
trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
END IF;
IF interrupt='1' THEN
trap_vector(7 downto 2) <= "011"&rIPL_nr;
END IF;
END IF;
END IF;
memaddr_a(3 downto 0) <= "0000";
memaddr_a(7 downto 4) <= (OTHERS=>memaddr_a(3));
memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
memaddr_a(31 downto 16) <= (OTHERS=>memaddr_a(15));
IF movem_presub='1' THEN
IF movem_busy='1' OR longread='1' THEN
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF state(1)='1' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr_a(1) <= '1';
ELSIF execOPC='1' THEN
IF datatype="10" THEN
memaddr_a(3 downto 0) <= "1100";
ELSE
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF setdisp='1' THEN
IF setdispbrief='1' THEN
memaddr_a <= briefext;
ELSIF setdispbyte='1' THEN
memaddr_a(7 downto 0) <= brief(7 downto 0);
ELSE
memaddr_a(15 downto 0) <= brief;
END IF;
END IF;
memaddr_in <= memaddr+memaddr_a;
IF longread='0' THEN
IF set_mem_addsub='1' THEN
memaddr_in <= addsub_q;
ELSIF set_vectoraddr='1' THEN
memaddr_in <= trap_vector;
ELSIF interrupt='1' THEN
memaddr_in <= "1111111111111111111111111111"&rIPL_nr&'0';
ELSIF set_mem_rega='1' THEN
memaddr_in <= reg_QA;
ELSIF setaddrlong='1' AND longread='0' THEN
memaddr_in <= data_read;
ELSIF decodeOPC='1' THEN
memaddr_in <= TG68_PC;
END IF;
END IF;
data_read(15 downto 0) <= data_in;
data_read(31 downto 16) <= (OTHERS=>data_in(15));
IF long_done='1' THEN
data_read(31 downto 16) <= last_data_read;
END IF;
IF mem_byte='1' AND memaddr(0)='0' THEN
data_read(7 downto 0) <= data_in(15 downto 8);
END IF;
IF longread='1' THEN
data_write <= data_write_tmp(31 downto 16);
ELSE
data_write(7 downto 0) <= data_write_tmp(7 downto 0);
IF mem_byte='1' THEN
data_write(15 downto 8) <= data_write_tmp(7 downto 0);
ELSE
data_write(15 downto 8) <= data_write_tmp(15 downto 8);
IF datatype="00" THEN
data_write(7 downto 0) <= data_write_tmp(15 downto 8);
END IF;
END IF;
END IF;
IF reset='0' THEN
longread <= '0';
long_done <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND enaWRreg='1' THEN
last_data_read <= data_in;
long_done <= longread;
IF get_extendedOPC='0' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr <= memaddr_in;
END IF;
IF get_extendedOPC='0' THEN
IF ((setstate_mux(1)='1' AND datatype="10") OR longreaddirect='1') AND longread='0' AND interrupt='0' THEN
longread <= '1';
ELSE
longread <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- brief
-----------------------------------------------------------------------------
process (clk, brief, OP1out)
begin
IF brief(11)='1' THEN
OP1outbrief <= OP1out(31 downto 16);
ELSE
OP1outbrief <= (OTHERS=>OP1out(15));
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
briefext <= OP1outbrief&OP1out(15 downto 0);
-- CASE brief(10 downto 9) IS
-- WHEN "00" => briefext <= OP1outbrief&OP1out(15 downto 0);
-- WHEN "01" => briefext <= OP1outbrief(14 downto 0)&OP1out(15 downto 0)&'0';
-- WHEN "10" => briefext <= OP1outbrief(13 downto 0)&OP1out(15 downto 0)&"00";
-- WHEN "11" => briefext <= OP1outbrief(12 downto 0)&OP1out(15 downto 0)&"000";
-- END CASE;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- PC Calc + fetch opcode
-----------------------------------------------------------------------------
process (clk, reset, opcode, TG68_PC, TG68_PC_dec, TG68_PC_br8, TG68_PC_brw, PC_dataa, PC_datab, execOPC, last_data_read, get_extendedOPC,
setstate_delay, setstate)
begin
PC_dataa <= TG68_PC;
PC_datab(2 downto 0) <= "010";
PC_datab(7 downto 3) <= (others => PC_datab(2));
PC_datab(15 downto 8) <= (others => PC_datab(7));
PC_datab(31 downto 16) <= (others => PC_datab(15));
IF execOPC='0' THEN
IF TG68_PC_br8='1' THEN
PC_datab(7 downto 0) <= opcode(7 downto 0);
END IF;
IF TG68_PC_dec(1)='1' THEN
PC_datab(2) <= '1';
END IF;
IF TG68_PC_brw = '1' THEN
PC_datab(15 downto 0) <= last_data_read(15 downto 0);
END IF;
END IF;
TG68_PC_add <= PC_dataa+PC_datab;
IF get_extendedOPC='1' THEN
setstate_mux <= setstate_delay;
ELSE
setstate_mux <= setstate;
END IF;
IF reset = '0' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
TG68_PC <= (others =>'0');
state <= "01";
decodeOPC <= '0';
fetchOPC <= '0';
endOPC <= '0';
interrupt <= '0';
trap_interrupt <= '1';
execOPC <= '0';
getbrief <= '0';
TG68_PC_dec <= "00";
directPC <= '0';
directSR <= '0';
directCCR <= '0';
stop <= '0';
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_EXT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
exec_MULU <= '0';
exec_DIVU <= '0';
exec_Scc <= '0';
exec_CPMAW <= '0';
mem_byte <= '0';
rot_cnt <="000001";
rot_nop <= '0';
get_extendedOPC <= '0';
get_bitnumber <= '0';
get_movem_mask <= '0';
test_maskzero <= '0';
movepl <= '0';
movepw <= '0';
test_delay <= "000";
PCmarker <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND enaWRreg='1' THEN
get_extendedOPC <= set_get_extendedOPC;
get_bitnumber <= set_get_bitnumber;
get_movem_mask <= set_get_movem_mask;
test_maskzero <= get_movem_mask;
setstate_delay <= setstate;
TG68_PC_dec <= TG68_PC_dec(0)&set_TG68_PC_dec;
IF directPC='1' AND clkena='1' THEN
TG68_PC <= data_read;
ELSIF ea_to_pc='1' AND longread='0' THEN
TG68_PC <= memaddr_in;
ELSIF (state ="00" AND TG68_PC_nop='0') OR TG68_PC_br8='1' OR TG68_PC_brw='1' OR TG68_PC_dec(1)='1' THEN
TG68_PC <= TG68_PC_add;
END IF;
IF get_bitnumber='1' THEN
bit_number_reg <= data_read(4 downto 0);
END IF;
IF clkena='1' OR get_extendedOPC='1' THEN
IF set_get_extendedOPC='1' THEN
state <= "00";
ELSIF get_extendedOPC='1' THEN
state <= setstate_mux;
ELSIF fetchOPC='1' OR (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR stop='1' THEN
state <= "01"; --decode cycle, execute cycle
ELSE
state <= setstate_mux;
END IF;
IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' AND wait_mem_byte='0' THEN
mem_byte <= '1';
ELSE
mem_byte <= '0';
END IF;
END IF;
END IF;
IF clkena='1' THEN
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
fetchOPC <= '0';
exec_CPMAW <= '0';
endOPC <= '0';
interrupt <= '0';
execOPC <= '0';
exec_EXT <= '0';
exec_Scc <= '0';
rot_nop <= '0';
decodeOPC <= fetchOPC;
directPC <= set_directPC;
directSR <= set_directSR;
directCCR <= set_directCCR;
exec_MULU <= set_exec_MULU;
exec_DIVU <= set_exec_DIVU;
movepl <= '0';
movepw <= '0';
stop <= set_stop OR (stop AND NOT interrupt);
IF set_PCmarker='1' THEN
PCmarker <= '1';
ELSIF (state="10" AND longread='0') OR (ea_only='1' AND get_ea_now='1') THEN
PCmarker <= '0';
END IF;
IF (decodeOPC OR execOPC)='1' THEN
rot_cnt <= set_rot_cnt;
END IF;
IF next_micro_state=idle AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
nextpass <= '0';
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
endOPC <= '1';
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
interrupt <= '1';
rIPL_nr <= IPL_nr;
ELSE
IF stop='0' THEN
fetchOPC <= '1';
END IF;
END IF;
END IF;
IF exec_write_back='0' OR state/="11" THEN
IF stop='0' THEN
execOPC <= '1';
END IF;
exec_ADD <= set_exec_ADD;
exec_OR <= set_exec_OR;
exec_AND <= set_exec_AND;
exec_EOR <= set_exec_EOR;
exec_MOVE <= set_exec_MOVE;
exec_MOVEQ <= set_exec_MOVEQ;
exec_MOVESR <= set_exec_MOVESR;
exec_ADDQ <= set_exec_ADDQ;
exec_CMP <= set_exec_CMP;
exec_ROT <= set_exec_ROT;
exec_tas <= set_exec_tas;
exec_EXT <= set_exec_EXT;
exec_ABCD <= set_exec_ABCD;
exec_SBCD <= set_exec_SBCD;
exec_Scc <= set_exec_Scc;
exec_CPMAW <= set_exec_CPMAW;
rot_nop <= set_rot_nop;
END IF;
ELSE
IF endOPC='0' AND (setnextpass='1' OR (regdirectsource='1' AND decodeOPC='1')) THEN
nextpass <= '1';
END IF;
END IF;
IF interrupt='1' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
-- trap_PC <= TG68_PC;
trap_interrupt <= '1';
END IF;
IF fetchOPC='1' THEN
trap_interrupt <= '0';
IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' THEN
-- IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' OR opcode(15 downto 6)="0100111011" THEN --nur für Validator
opcode <= X"60FE";
IF to_SR='0' THEN
test_delay <= "001";
END IF;
ELSE
opcode <= data_read(15 downto 0);
END IF;
getbrief <= '0';
-- trap_PC <= TG68_PC;
ELSE
test_delay <= test_delay(1 downto 0)&'0';
getbrief <= setgetbrief;
movepl <= set_movepl;
movepw <= set_movepw;
END IF;
IF decodeOPC='1' OR interrupt='1' THEN
trap_SR <= Flags;
END IF;
IF getbrief='1' THEN
brief <= data_read(15 downto 0);
END IF;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- handle EA_data, data_write_tmp
-----------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset = '0' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
direct_data <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
direct_data <= '0';
IF endOPC='1' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSE
IF set_Z_error='1' THEN
Z_error <= '1';
END IF;
exec_DIRECT <= set_exec_MOVE;
IF setstate_mux="10" AND write_back='1' THEN
exec_write_back <= '1';
END IF;
END IF;
IF set_direct_data='1' THEN
direct_data <= '1';
use_direct_data <= '1';
END IF;
IF set_exec_MOVE='1' AND state="11" THEN
use_direct_data <= '1';
END IF;
IF (exec_DIRECT='1' AND state="00" AND getbrief='0' AND endOPC='0') OR state="10" THEN
set_store_in_tmp <= '1';
ea_data <= data_read;
END IF;
IF writePC_add='1' THEN
data_write_tmp <= TG68_PC_add;
ELSIF writePC='1' OR fetchOPC='1' OR interrupt='1' OR (trap_trap='1' AND decodeOPC='1') THEN --fetchOPC für Trap
data_write_tmp <= TG68_PC;
ELSIF execOPC='1' OR (get_ea_now='1' AND ea_only='1') THEN --get_ea_now='1' AND ea_only='1' ist für pea
data_write_tmp <= registerin(31 downto 8)&(registerin(7)OR exec_tas)®isterin(6 downto 0);
ELSIF (exec_DIRECT='1' AND state="10") OR direct_data='1' THEN
data_write_tmp <= data_read;
IF movepl='1' THEN
data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0);
END IF;
ELSIF (movem_busy='1' AND datatype="10" AND movem_presub='1') OR movepl='1' THEN
data_write_tmp <= OP2out(15 downto 0)&OP2out(31 downto 16);
ELSIF (NOT trapmake AND decodeOPC)='1' OR movem_busy='1' OR movepw='1' THEN
data_write_tmp <= OP2out;
ELSIF writeSR='1'THEN
data_write_tmp(15 downto 0) <= trap_SR(15 downto 8)& Flags(7 downto 0);
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set dest regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, rf_dest_addr_tmp, to_USP, Flags, trapmake, movem_addr, movem_presub, movem_regaddr, setbriefext, brief, setstackaddr, dest_hbits, dest_areg, data_is_source)
BEGIN
rf_dest_addr <= rf_dest_addr_tmp;
IF rf_dest_addr_tmp(3 downto 0)="1111" AND to_USP='0' THEN
rf_dest_addr(4) <= Flags(13) OR trapmake;
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_dest_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_dest_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF setbriefext='1' THEN
rf_dest_addr_tmp <= ("000"&brief(15 downto 12));
ELSIF setstackaddr='1' THEN
rf_dest_addr_tmp <= "0001111";
ELSIF dest_hbits='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(11 downto 9);
ELSE
IF opcode(5 downto 3)="000" OR data_is_source='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(2 downto 0);
ELSE
rf_dest_addr_tmp <= "0001"&opcode(2 downto 0);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP1
-----------------------------------------------------------------------------
PROCESS (reg_QA, OP1out_zero, from_SR, Flags, ea_data_OP1, set_store_in_tmp, ea_data)
BEGIN
OP1out <= reg_QA;
IF OP1out_zero='1' THEN
OP1out <= (OTHERS => '0');
ELSIF from_SR='1' THEN
OP1out(15 downto 0) <= Flags;
ELSIF ea_data_OP1='1' AND set_store_in_tmp='1' THEN
OP1out <= ea_data;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set source regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, Flags, movem_addr, movem_presub, movem_regaddr, source_lowbits, source_areg, from_USP, rf_source_addr_tmp)
BEGIN
rf_source_addr <= rf_source_addr_tmp;
IF rf_source_addr_tmp(3 downto 0)="1111" AND from_USP='0' THEN
rf_source_addr(4) <= Flags(13);
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_source_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_source_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF from_USP='1' THEN
rf_source_addr_tmp <= "0001111";
ELSIF source_lowbits='1' THEN
rf_source_addr_tmp <= "000"&source_areg&opcode(2 downto 0);
ELSE
rf_source_addr_tmp <= "000"&source_areg&opcode(11 downto 9);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP2
-----------------------------------------------------------------------------
PROCESS (OP2out, reg_QB, opcode, datatype, OP2out_one, exec_EXT, exec_MOVEQ, EXEC_ADDQ, use_direct_data, data_write_tmp,
ea_data_OP1, set_store_in_tmp, ea_data, movepl)
BEGIN
OP2out(15 downto 0) <= reg_QB(15 downto 0);
OP2out(31 downto 16) <= (OTHERS => OP2out(15));
IF OP2out_one='1' THEN
OP2out(15 downto 0) <= "1111111111111111";
ELSIF exec_EXT='1' THEN
IF opcode(6)='0' THEN --ext.w
OP2out(15 downto 8) <= (OTHERS => OP2out(7));
END IF;
ELSIF use_direct_data='1' THEN
OP2out <= data_write_tmp;
ELSIF ea_data_OP1='0' AND set_store_in_tmp='1' THEN
OP2out <= ea_data;
ELSIF exec_MOVEQ='1' THEN
OP2out(7 downto 0) <= opcode(7 downto 0);
OP2out(15 downto 8) <= (OTHERS => opcode(7));
ELSIF exec_ADDQ='1' THEN
OP2out(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
OP2out(3) <='1';
ELSE
OP2out(3) <='0';
END IF;
OP2out(15 downto 4) <= (OTHERS => '0');
ELSIF datatype="10" OR movepl='1' THEN
OP2out(31 downto 16) <= reg_QB(31 downto 16);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- addsub
-----------------------------------------------------------------------------
PROCESS (OP1out, OP2out, presub, postadd, execOPC, OP2out_one, datatype, use_SP, use_XZFlag, use_XFlag, Flags, setaddsub)
BEGIN
addsub_a <= OP1out;
addsub_b <= OP2out;
addsub <= NOT presub;
c_in(0) <='0';
IF execOPC='0' AND OP2out_one='0' THEN
IF datatype="00" AND use_SP='0' THEN
addsub_b <= "00000000000000000000000000000001";
ELSIF datatype="10" AND (presub OR postadd)='1' THEN
addsub_b <= "00000000000000000000000000000100";
ELSE
addsub_b <= "00000000000000000000000000000010";
END IF;
ELSE
IF (use_XZFlag='1' OR use_XFlag='1') AND Flags(4)='1' THEN
c_in(0) <= '1';
END IF;
addsub <= setaddsub;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Write Reg
-----------------------------------------------------------------------------
PROCESS (clkena, OP1in, datatype, presub, postadd, endOPC, regwrena, state, execOPC, last_data_read, movem_addr, rf_dest_addr, reg_QA, maskzero)
BEGIN
Lwrena <= '0';
Hwrena <= '0';
registerin <= OP1in;
IF (presub='1' OR postadd='1') AND endOPC='0' THEN -- -(An)+
Hwrena <= '1';
Lwrena <= '1';
ELSIF Regwrena='1' AND maskzero='0' THEN --read (mem)
Lwrena <= '1';
CASE datatype IS
WHEN "00" => --BYTE
registerin(15 downto 8) <= reg_QA(15 downto 8);
WHEN "01" => --WORD
IF rf_dest_addr(3)='1' OR movem_addr='1' THEN
Hwrena <='1';
END IF;
WHEN OTHERS => --LONG
Hwrena <= '1';
END CASE;
END IF;
END PROCESS;
------------------------------------------------------------------------------
--ALU
------------------------------------------------------------------------------
PROCESS (opcode, OP1in, OP1out, OP2out, datatype, c_out, exec_ABCD, exec_SBCD, exec_CPMAW, exec_MOVESR, bits_out, Flags, flag_z, use_XZFlag, addsub_ofl,
dummy_s, dummy_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, addsub_q, movem_addr, data_read, exec_MULU, exec_DIVU, exec_OR,
exec_AND, exec_Scc, exec_EOR, exec_MOVE, exec_exg, exec_ROT, execOPC, exec_swap, exec_Bits, rot_out, dummy_mulu, dummy_div, save_memaddr, memaddr,
memaddr_in, ea_only, get_ea_now)
BEGIN
--BCD_ARITH-------------------------------------------------------------------
--ADC
dummy_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0'));
niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4));
niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc);
niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
--SBC
dummy_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0'));
nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4));
nibs_lc <= nibs_l(5);
nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc);
nibs_hc <= nibs_h(5);
------------------------------------------------------------------------------
flag_z <= "000";
OP1in <= addsub_q;
IF movem_addr='1' THEN
OP1in <= data_read;
ELSIF exec_ABCD='1' THEN
OP1in(7 downto 0) <= dummy_a(7 downto 0);
ELSIF exec_SBCD='1' THEN
OP1in(7 downto 0) <= dummy_s(7 downto 0);
ELSIF exec_MULU='1' THEN
OP1in <= dummy_mulu;
ELSIF exec_DIVU='1' AND execOPC='1' THEN
OP1in <= dummy_div;
ELSIF exec_OR='1' THEN
OP1in <= OP2out OR OP1out;
ELSIF exec_AND='1' OR exec_Scc='1' THEN
OP1in <= OP2out AND OP1out;
ELSIF exec_EOR='1' THEN
OP1in <= OP2out XOR OP1out;
ELSIF exec_MOVE='1' OR exec_exg='1' THEN
OP1in <= OP2out;
ELSIF exec_ROT='1' THEN
OP1in <= rot_out;
ELSIF save_memaddr='1' THEN
OP1in <= memaddr;
ELSIF get_ea_now='1' AND ea_only='1' THEN
OP1in <= memaddr_in;
ELSIF exec_swap='1' THEN
OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
ELSIF exec_bits='1' THEN
OP1in <= bits_out;
ELSIF exec_MOVESR='1' THEN
OP1in(15 downto 0) <= Flags;
END IF;
IF use_XZFlag='1' AND flags(2)='0' THEN
flag_z <= "000";
ELSIF OP1in(7 downto 0)="00000000" THEN
flag_z(0) <= '1';
IF OP1in(15 downto 8)="00000000" THEN
flag_z(1) <= '1';
IF OP1in(31 downto 16)="0000000000000000" THEN
flag_z(2) <= '1';
END IF;
END IF;
END IF;
-- --Flags NZVC
IF datatype="00" THEN --Byte
set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
IF exec_ABCD='1' THEN
set_flags(0) <= dummy_a(8);
ELSIF exec_SBCD='1' THEN
set_flags(0) <= dummy_s(8);
END IF;
ELSIF datatype="10" OR exec_CPMAW='1' THEN --Long
set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
ELSE --Word
set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
END IF;
END PROCESS;
------------------------------------------------------------------------------
--Flags
------------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset='0' THEN
Flags(13) <= '1';
SVmode <= '1';
Flags(10 downto 8) <= "111";
ELSIF rising_edge(clk) THEN
IF clkena = '1' THEN
IF directSR='1' THEN
Flags <= data_read(15 downto 0);
END IF;
IF directCCR='1' THEN
Flags(7 downto 0) <= data_read(7 downto 0);
END IF;
IF interrupt='1' THEN
Flags(10 downto 8) <=rIPL_nr;
SVmode <= '1';
END IF;
IF writeSR='1' OR interrupt='1' THEN
Flags(13) <='1';
END IF;
IF endOPC='1' AND to_SR='0' THEN
SVmode <= Flags(13);
END IF;
IF execOPC='1' AND to_SR='1' THEN
Flags(7 downto 0) <= OP1in(7 downto 0); --CCR
IF datatype="01" AND (opcode(14)='0' OR opcode(9)='1') THEN --move to CCR wird als word gespeichert
Flags(15 downto 8) <= OP1in(15 downto 8); --SR
SVmode <= OP1in(13);
END IF;
ELSIF Z_error='1' THEN
IF opcode(8)='0' THEN
Flags(3 downto 0) <= "1000";
ELSE
Flags(3 downto 0) <= "0100";
END IF;
ELSIF no_Flags='0' AND trapmake='0' THEN
IF exec_ADD='1' THEN
Flags(4) <= set_flags(0);
ELSIF exec_ROT='1' AND rot_bits/="11" AND rot_nop='0' THEN
Flags(4) <= rot_XC;
END IF;
IF (exec_ADD OR exec_CMP)='1' THEN
Flags(3 downto 0) <= set_flags;
ELSIF decodeOPC='1' and set_exec_ROT='1' THEN
Flags(1) <= '0';
ELSIF exec_DIVU='1' THEN
IF set_V_Flag='1' THEN
Flags(3 downto 0) <= "1010";
ELSE
Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
END IF;
ELSIF exec_OR='1' OR exec_AND='1' OR exec_EOR='1' OR exec_MOVE='1' OR exec_swap='1' OR exec_MULU='1' THEN
Flags(3 downto 0) <= set_flags(3 downto 2)&"00";
ELSIF exec_ROT='1' THEN
Flags(3 downto 2) <= set_flags(3 downto 2);
Flags(0) <= rot_XC;
IF rot_bits="00" THEN --ASL/ASR
Flags(1) <= ((set_flags(3) XOR rot_rot) OR Flags(1));
END IF;
ELSIF exec_bits='1' THEN
Flags(2) <= NOT one_bit_in;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- execute opcode
-----------------------------------------------------------------------------
PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt, rot_nop,
Z_error, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec, c_out, OP1out, micro_state)
BEGIN
TG68_PC_br8 <= '0';
TG68_PC_brw <= '0';
TG68_PC_nop <= '0';
setstate <= "00";
Regwrena <= '0';
postadd <= '0';
presub <= '0';
movem_presub <= '0';
setaddsub <= '1';
setaddrlong <= '0';
setnextpass <= '0';
regdirectsource <= '0';
setdisp <= '0';
setdispbyte <= '0';
setdispbrief <= '0';
setbriefext <= '0';
setgetbrief <= '0';
longreaddirect <= '0';
dest_areg <= '0';
source_areg <= '0';
data_is_source <= '0';
write_back <= '0';
setstackaddr <= '0';
writePC <= '0';
writePC_add <= '0';
set_TG68_PC_dec <= '0';
set_directPC <= '0';
set_exec_ADD <= '0';
set_exec_OR <= '0';
set_exec_AND <= '0';
set_exec_EOR <= '0';
set_exec_MOVE <= '0';
set_exec_MOVEQ <= '0';
set_exec_MOVESR <= '0';
set_exec_ADDQ <= '0';
set_exec_CMP <= '0';
set_exec_ROT <= '0';
set_exec_EXT <= '0';
set_exec_CPMAW <= '0';
OP2out_one <= '0';
ea_to_pc <= '0';
ea_build <= '0';
get_ea_now <= '0';
rot_bits <= "XX";
set_rot_nop <= '0';
set_rot_cnt <= "000001";
set_movem_busy <= '0';
set_get_movem_mask <= '0';
save_memaddr <= '0';
set_mem_addsub <= '0';
exec_exg <= '0';
exec_swap <= '0';
exec_Bits <= '0';
set_get_bitnumber <= '0';
dest_hbits <= '0';
source_lowbits <= '0';
set_mem_rega <= '0';
ea_data_OP1 <= '0';
ea_only <= '0';
set_direct_data <= '0';
set_get_extendedOPC <= '0';
set_exec_tas <= '0';
OP1out_zero <= '0';
use_XZFlag <= '0';
use_XFlag <= '0';
set_exec_ABCD <= '0';
set_exec_SBCD <= '0';
set_exec_MULU <= '0';
set_exec_DIVU <= '0';
set_exec_Scc <= '0';
trap_illegal <='0';
trap_priv <='0';
trap_1010 <='0';
trap_1111 <='0';
trap_trap <='0';
trap_trapv <= '0';
trapmake <='0';
set_vectoraddr <='0';
writeSR <= '0';
set_directSR <= '0';
set_directCCR <= '0';
set_stop <= '0';
from_SR <= '0';
to_SR <= '0';
from_USP <= '0';
to_USP <= '0';
illegal_write_mode <= '0';
illegal_read_mode <= '0';
illegal_byteaddr <= '0';
no_Flags <= '0';
set_PCmarker <= '0';
use_SP <= '0';
set_Z_error <= '0';
wait_mem_byte <= '0';
set_movepl <= '0';
set_movepw <= '0';
trap_chk <= '0';
next_micro_state <= idle;
------------------------------------------------------------------------------
--Sourcepass
------------------------------------------------------------------------------
IF ea_only='0' AND get_ea_now='1' THEN
setstate <= "10";
END IF;
IF ea_build='1' THEN
CASE opcode(5 downto 3) IS --source
WHEN "010"|"011"|"100" => -- -(An)+
get_ea_now <='1';
setnextpass <= '1';
IF opcode(4)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(3)='1' THEN --(An)+
postadd <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(5)='1' THEN -- -(An)
presub <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(4 downto 3)/="10" THEN
regwrena <= '1';
END IF;
WHEN "101" => --(d16,An)
next_micro_state <= ld_dAn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "111" =>
CASE opcode(2 downto 0) IS
WHEN "000" => --(xxxx).w
next_micro_state <= ld_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= ld_nn;
WHEN "010" => --(d16,PC)
next_micro_state <= ld_dAn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "011" => --(d8,PC,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "100" => --#data
setnextpass <= '1';
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
------------------------------------------------------------------------------
--prepere opcode
------------------------------------------------------------------------------
CASE opcode(7 downto 6) IS
WHEN "00" => datatype <= "00"; --Byte
WHEN "01" => datatype <= "01"; --Word
WHEN OTHERS => datatype <= "10"; --Long
END CASE;
IF execOPC='1' AND endOPC='0' AND exec_write_back='1' THEN
setstate <="11";
END IF;
------------------------------------------------------------------------------
--test illegal mode
------------------------------------------------------------------------------
IF (opcode(5 downto 3)="111" AND opcode(2 downto 1)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_write_mode <= '1';
END IF;
IF (opcode(5 downto 2)="1111" AND opcode(1 downto 0)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_read_mode <= '1';
END IF;
IF opcode(5 downto 3)="001" AND datatype="00" THEN
illegal_byteaddr <= '1';
END IF;
CASE opcode(15 downto 12) IS
-- 0000 ----------------------------------------------------------------------------
WHEN "0000" =>
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
datatype <= "00"; --Byte
use_SP <= '1';
no_Flags <='1';
IF opcode(7)='0' THEN
set_exec_move <= '1';
set_movepl <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7)='0' THEN
set_direct_data <= '1';
END IF;
next_micro_state <= movep1;
setgetbrief <='1';
set_mem_regA <= '1';
END IF;
IF opcode(7)='0' AND endOPC='1' THEN
IF opcode(6)='1' THEN
datatype <= "10"; --Long
ELSE
datatype <= "01"; --Word
END IF;
dest_hbits <='1';
regwrena <= '1';
END IF;
ELSE
IF opcode(8)='1' OR opcode(11 downto 8)="1000" THEN --Bits
IF execOPC='1' AND get_extendedOPC='0' THEN
IF opcode(7 downto 6)/="00" AND endOPC='1' THEN
regwrena <= '1';
END IF;
exec_Bits <= '1';
ea_data_OP1 <= '1';
END IF;
-- IF get_extendedOPC='1' THEN
-- datatype <= "01"; --Word
-- ELS
IF opcode(5 downto 4)="00" THEN
datatype <= "10"; --Long
ELSE
datatype <= "00"; --Byte
IF opcode(7 downto 6)/="00" THEN
write_back <= '1';
END IF;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
IF opcode(8)='0' THEN
IF opcode(5 downto 4)/="00" THEN --Dn, An
set_get_extendedOPC <= '1';
END IF;
set_get_bitnumber <= '1';
END IF;
END IF;
ELSE --andi, ...xxxi
IF opcode(11 downto 8)="0000" THEN --ORI
set_exec_OR <= '1';
END IF;
IF opcode(11 downto 8)="0010" THEN --ANDI
set_exec_AND <= '1';
END IF;
IF opcode(11 downto 8)="0100" OR opcode(11 downto 8)="0110" THEN --SUBI, ADDI
set_exec_ADD <= '1';
END IF;
IF opcode(11 downto 8)="1010" THEN --EORI
set_exec_EOR <= '1';
END IF;
IF opcode(11 downto 8)="1100" THEN --CMPI
set_exec_CMP <= '1';
ELSIF trapmake='0' THEN
write_back <= '1';
END IF;
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec_AND OR set_exec_OR OR set_exec_EOR)='1' THEN --SR
-- IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="1010") THEN --SR
IF SVmode='0' AND opcode(6)='1' THEN --SR
trap_priv <= '1';
trapmake <= '1';
ELSE
from_SR <= '1';
to_SR <= '1';
IF decodeOPC='1' THEN
setnextpass <= '1';
set_direct_data <= '1';
END IF;
END IF;
ELSE
IF decodeOPC='1' THEN
IF opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="0100" --ANDI, ORI, SUBI
OR opcode(11 downto 8)="0110" OR opcode(11 downto 8)="1010" OR opcode(11 downto 8)="1100" THEN --ADDI, EORI, CMPI
-- IF (set_exec_AND OR set_exec_OR OR set_exec_ADD --ANDI, ORI, SUBI
-- OR set_exec_EOR OR set_exec_CMP)='1' THEN --ADDI, EORI, CMPI
next_micro_state <= andi;
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF opcode(11 downto 8)/="1100" THEN --CMPI
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
IF opcode(11 downto 8)="1100" OR opcode(11 downto 8)="0100" THEN --CMPI, SUBI
setaddsub <= '0';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 0001, 0010, 0011 -----------------------------------------------------------------
WHEN "0001"|"0010"|"0011" => --move.b, move.l, move.w
set_exec_MOVE <= '1';
IF opcode(8 downto 6)="001" THEN
no_Flags <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
CASE opcode(13 downto 12) IS
WHEN "01" => datatype <= "00"; --Byte
WHEN "10" => datatype <= "10"; --Long
WHEN OTHERS => datatype <= "01"; --Word
END CASE;
source_lowbits <= '1'; -- Dn=> An=>
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF getbrief='1' AND nextpass='1' THEN -- =>(d16,An) =>(d8,An,Xn)
set_mem_rega <= '1';
END IF;
IF execOPC='1' AND opcode(8 downto 7)="00" THEN
Regwrena <= '1';
END IF;
IF nextpass='1' OR execOPC='1' OR opcode(5 downto 4)="00" THEN
dest_hbits <= '1';
IF opcode(8 downto 6)/="000" THEN
dest_areg <= '1';
END IF;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
CASE opcode(8 downto 6) IS --destination
-- WHEN "000" => --Dn
-- WHEN "001" => --An
WHEN "010"|"011"|"100" => --destination -(an)+
IF opcode(7)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(6)='1' THEN --(An)+
postadd <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(8)='1' THEN -- -(An)
presub <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(7 downto 6)/="10" THEN
regwrena <= '1';
END IF;
setstate <= "11";
next_micro_state <= nop;
WHEN "101" => --(d16,An)
next_micro_state <= st_dAn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= st_AnXn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "111" =>
CASE opcode(11 downto 9) IS
WHEN "000" => --(xxxx).w
next_micro_state <= st_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= st_nn;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
-- 0100 ----------------------------------------------------------------------------
WHEN "0100" => --rts_group
IF opcode(8)='1' THEN --lea
IF opcode(6)='1' THEN --lea
IF opcode(7)='1' THEN
ea_only <= '1';
IF opcode(5 downto 3)="010" THEN --lea (Am),An
set_exec_move <='1';
no_Flags <='1';
dest_areg <= '1';
dest_hbits <= '1';
source_lowbits <= '1';
source_areg <= '1';
IF execOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
dest_areg <= '1';
dest_hbits <= '1';
regwrena <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --chk
IF opcode(7)='1' THEN
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
datatype <= "01"; --Word
IF execOPC='1' THEN
setaddsub <= '0';
--first alternative
ea_data_OP1 <= '1';
IF c_out(1)='1' OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- trap_chk <= '1'; --first I must change the Trap System
-- trapmake <= '1';
END IF;
--second alternative
-- IF (c_out(1)='0' AND flag_z(1)='0') OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- -- trap_chk <= '1'; --first I must change the Trap System
-- -- trapmake <= '1';
-- END IF;
-- dest_hbits <= '1';
-- source_lowbits <='1';
END IF;
ELSE
trap_illegal <= '1'; -- chk long for 68020
trapmake <= '1';
END IF;
END IF;
ELSE
CASE opcode(11 downto 9) IS
WHEN "000"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move from SR
set_exec_MOVESR <= '1';
datatype <= "01";
write_back <='1'; -- im 68000 wird auch erst gelesen
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --negx
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "001"=>
IF opcode(7 downto 6)="11" THEN --move from CCR 68010
trap_illegal <= '1';
trapmake <= '1';
ELSE --clr
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_AND <= '1';
IF execOPC='1' THEN
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "010"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move to CCR
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE --neg
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "011"=> --not, move toSR
IF opcode(7 downto 6)="11" THEN --move to SR
IF SVmode='1' THEN
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
ELSE --not
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_EOR <= '1';
IF execOPC='1' THEN
OP2out_one <= '1';
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "100"|"110"=>
IF opcode(7)='1' THEN --movem, ext
IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
source_lowbits <= '1';
IF decodeOPC='1' THEN
set_exec_EXT <= '1';
set_exec_move <= '1';
END IF;
IF opcode(6)='0' THEN
datatype <= "01"; --WORD
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE --movem
-- IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN --MOVEM
ea_only <= '1';
IF decodeOPC='1' THEN
datatype <= "01"; --Word
set_get_movem_mask <='1';
set_get_extendedOPC <='1';
IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
set_mem_rega <= '1';
setstate <= "01";
IF opcode(10)='0' THEN
set_movem_busy <='1';
ELSE
next_micro_state <= movem;
END IF;
ELSE
ea_build <= '1';
END IF;
ELSE
IF opcode(6)='0' THEN
datatype <= "01"; --Word
END IF;
END IF;
IF execOPC='1' THEN
IF opcode(5 downto 3)="100" OR opcode(5 downto 3)="011" THEN
regwrena <= '1';
save_memaddr <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
set_movem_busy <= '1';
IF opcode(10)='0' THEN
setstate <="01";
ELSE
setstate <="10";
END IF;
END IF;
IF opcode(5 downto 3)="100" THEN
movem_presub <= '1';
END IF;
IF movem_addr='1' THEN
IF opcode(10)='1' THEN
regwrena <= '1';
END IF;
END IF;
IF movem_busy='1' THEN
IF opcode(10)='0' THEN
setstate <="11";
ELSE
setstate <="10";
END IF;
END IF;
END IF;
ELSE
IF opcode(10)='1' THEN --MUL, DIV 68020
trap_illegal <= '1';
trapmake <= '1';
ELSE --pea, swap
IF opcode(6)='1' THEN
datatype <= "10";
IF opcode(5 downto 3)="000" THEN --swap
IF execOPC='1' THEN
exec_swap <= '1';
regwrena <= '1';
END IF;
ELSIF opcode(5 downto 3)="001" THEN --bkpt
ELSE --pea
ea_only <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF get_ea_now='1' THEN
setstate <="01";
END IF;
END IF;
ELSE --nbcd
IF decodeOPC='1' THEN --nbcd
ea_build <= '1';
END IF;
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
WHEN "101"=> --tst, tas
IF opcode(7 downto 2)="111111" THEN --4AFC illegal
trap_illegal <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
dest_hbits <= '1'; --for Flags
source_lowbits <= '1';
-- IF opcode(3)='1' THEN --MC68020...
-- source_areg <= '1';
-- END IF;
END IF;
set_exec_MOVE <= '1';
IF opcode(7 downto 6)="11" THEN --tas
set_exec_tas <= '1';
write_back <= '1';
datatype <= "00"; --Byte
IF execOPC='1' AND endOPC='1' THEN
regwrena <= '1';
END IF;
END IF;
END IF;
-- WHEN "110"=>
WHEN "111"=> --4EXX
IF opcode(7)='1' THEN --jsr, jmp
datatype <= "10";
ea_only <= '1';
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF get_ea_now='1' THEN --jsr
IF opcode(6)='0' THEN
setstate <="01";
END IF;
ea_to_pc <= '1';
IF opcode(5 downto 1)="11100" THEN
writePC_add <= '1';
ELSE
writePC <= '1';
END IF;
END IF;
ELSE --
CASE opcode(6 downto 0) IS
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
trap_trap <='1';
trapmake <= '1';
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link
datatype <= "10";
IF decodeOPC='1' THEN
next_micro_state <= link;
set_exec_MOVE <= '1'; --für displacement
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
source_lowbits <= '1';
source_areg <= '1';
END IF;
IF execOPC='1' THEN
setstackaddr <='1';
regwrena <= '1';
END IF;
WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" => --unlink
datatype <= "10";
IF decodeOPC='1' THEN
setstate <= "10";
set_mem_rega <= '1';
ELSIF execOPC='1' THEN
regwrena <= '1';
exec_exg <= '1';
ELSE
setstackaddr <='1';
regwrena <= '1';
get_ea_now <= '1';
ea_only <= '1';
END IF;
WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" => --move An,USP
IF SVmode='1' THEN
no_Flags <= '1';
to_USP <= '1';
setstackaddr <= '1';
source_lowbits <= '1';
source_areg <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
IF SVmode='1' THEN
no_Flags <= '1';
from_USP <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110000" => --reset
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110001" => --nop
WHEN "1110010" => --stop
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
setnextpass <= '1';
set_directSR <= '1';
set_stop <= '1';
END IF;
END IF;
WHEN "1110011" => --rte
IF SVmode='1' THEN
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directSR <= '1';
next_micro_state <= rte;
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110101" => --rts
IF decodeOPC='1' THEN
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
END IF;
WHEN "1110110" => --trapv
IF Flags(1)='1' THEN
trap_trapv <= '1';
trapmake <= '1';
END IF;
WHEN "1110111" => --rtr
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directCCR <= '1';
next_micro_state <= rte;
END IF;
WHEN OTHERS =>
trap_illegal <= '1';
trapmake <= '1';
END CASE;
END IF;
WHEN OTHERS => null;
END CASE;
END IF;
-- 0101 ----------------------------------------------------------------------------
WHEN "0101" => --subq, addq
IF opcode(7 downto 6)="11" THEN --dbcc
IF opcode(5 downto 3)="001" THEN --dbcc
datatype <= "01"; --Word
IF decodeOPC='1' THEN
next_micro_state <= nop;
OP2out_one <= '1';
IF condition='0' THEN
Regwrena <= '1';
IF c_in(2)='1' THEN
next_micro_state <= dbcc1;
END IF;
END IF;
data_is_source <= '1';
END IF;
ELSE --Scc
datatype <= "00"; --Byte
write_back <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF condition='0' THEN
set_exec_Scc <= '1';
END IF;
IF execOPC='1' THEN
IF condition='1' THEN
OP2out_one <= '1';
exec_EXG <= '1';
ELSE
OP1out_zero <= '1';
END IF;
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
ELSE --addq, subq
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(5 downto 3)="001" THEN
no_Flags <= '1';
END IF;
write_back <= '1';
set_exec_ADDQ <= '1';
set_exec_ADD <= '1';
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 0110 ----------------------------------------------------------------------------
WHEN "0110" => --bra,bsr,bcc
datatype <= "10";
IF micro_state=idle THEN
IF opcode(11 downto 8)="0001" THEN --bsr
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bsr1;
ELSE
next_micro_state <= bsr2;
setstate <= "01";
END IF;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
ELSE --bra
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bra1;
END IF;
IF condition='1' THEN
TG68_PC_br8 <= '1';
END IF;
END IF;
END IF;
-- 0111 ----------------------------------------------------------------------------
WHEN "0111" => --moveq
IF opcode(8)='0' THEN
IF trap_interrupt='0' THEN
datatype <= "10"; --Long
Regwrena <= '1';
set_exec_MOVEQ <= '1';
set_exec_MOVE <= '1';
dest_hbits <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
-- 1000 ----------------------------------------------------------------------------
WHEN "1000" => --or
IF opcode(7 downto 6)="11" THEN --divu, divs
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' AND z_error='0' AND set_V_Flag='0' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --sbcd, pack , unpack
IF opcode(7 downto 6)="00" THEN --sbcd
use_XZFlag <= '1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --pack, unpack
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --or
set_exec_OR <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1001, 1101 -----------------------------------------------------------------------
WHEN "1001"|"1101" => --sub, add
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --adda.w, suba.w
datatype <= "01"; --Word
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(14)='0' THEN
setaddsub <= '0';
END IF;
END IF;
IF opcode(8)='1' AND opcode(5 downto 4)="00" AND opcode(7 downto 6)/="11" THEN --addx, subx
use_XZFlag <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN
write_back <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(7 downto 6)="11" THEN --adda, suba
no_Flags <= '1';
dest_areg <='1';
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
ELSE
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 1010 ----------------------------------------------------------------------------
WHEN "1010" => --Trap 1010
trap_1010 <= '1';
trapmake <= '1';
-- 1011 ----------------------------------------------------------------------------
WHEN "1011" => --eor, cmp
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --cmpa.w
datatype <= "01"; --Word
set_exec_CPMAW <= '1';
END IF;
IF opcode(8)='1' AND opcode(5 downto 3)="001" AND opcode(7 downto 6)/="11" THEN --cmpm
set_exec_CMP <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_rega <= '1';
postadd <= '1';
next_micro_state <= cmpm;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
setaddsub <= '0';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
set_exec_EOR <= '1';
write_back <= '1';
ELSE --cmp
set_exec_CMP <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE --cmp
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --cmpa
dest_areg <='1';
END IF;
dest_hbits <= '1';
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 1100 ----------------------------------------------------------------------------
WHEN "1100" => --and, exg
IF opcode(7 downto 6)="11" THEN --mulu, muls
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --exg, abcd
IF opcode(7 downto 6)="00" THEN --abcd
use_XZFlag <= '1';
-- datatype <= "00"; --ist schon default
set_exec_ADD <= '1';
set_exec_ABCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --exg
datatype <= "10";
regwrena <= '1';
IF opcode(6)='1' AND opcode(3)='1' THEN
dest_areg <= '1';
source_areg <= '1';
END IF;
IF decodeOPC='1' THEN
set_mem_rega <= '1';
exec_exg <= '1';
ELSE
save_memaddr <= '1';
dest_hbits <= '1';
END IF;
END IF;
ELSE --and
set_exec_AND <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1110 ----------------------------------------------------------------------------
WHEN "1110" => --rotation
set_exec_ROT <= '1';
IF opcode(7 downto 6)="11" THEN
datatype <= "01";
rot_bits <= opcode(10 downto 9);
ea_data_OP1 <= '1';
write_back <= '1';
ELSE
rot_bits <= opcode(4 downto 3);
data_is_source <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7 downto 6)="11" THEN
ea_build <= '1';
ELSE
IF opcode(5)='1' THEN
IF OP2out(5 downto 0)/="000000" THEN
set_rot_cnt <= OP2out(5 downto 0);
ELSE
set_rot_nop <= '1';
END IF;
ELSE
set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
set_rot_cnt(3) <='1';
ELSE
set_rot_cnt(3) <='0';
END IF;
END IF;
END IF;
END IF;
IF opcode(7 downto 6)/="11" THEN
IF execOPC='1' AND rot_nop='0' THEN
Regwrena <= '1';
set_rot_cnt <= rot_cnt-1;
END IF;
END IF;
-- ----------------------------------------------------------------------------
WHEN OTHERS =>
trap_1111 <= '1';
trapmake <= '1';
END CASE;
-- END PROCESS;
-----------------------------------------------------------------------------
-- execute microcode
-----------------------------------------------------------------------------
--PROCESS (micro_state)
-- BEGIN
IF Z_error='1' THEN -- divu by zero
trapmake <= '1'; --wichtig für USP
IF trapd='0' THEN
writePC <= '1';
END IF;
END IF;
IF trapmake='1' AND trapd='0' THEN
next_micro_state <= trap1;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
END IF;
IF interrupt='1' THEN
next_micro_state <= int1;
setstate <= "10";
-- datatype <= "01"; --wirkt sich auf Flags aus
END IF;
IF reset='0' THEN
micro_state <= init1;
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
trapd <= trapmake;
IF fetchOPC='1' THEN
micro_state <= idle;
ELSE
micro_state <= next_micro_state;
END IF;
END IF;
END IF;
CASE micro_state IS
WHEN ld_nn => -- (nnnn).w/l=>
get_ea_now <='1';
setnextpass <= '1';
setaddrlong <= '1';
WHEN st_nn => -- =>(nnnn).w/l
setstate <= "11";
setaddrlong <= '1';
next_micro_state <= nop;
WHEN ld_dAn1 => -- d(An)=>, --d(PC)=>
setstate <= "01";
next_micro_state <= ld_dAn2;
WHEN ld_dAn2 => -- d(An)=>, --d(PC)=>
get_ea_now <='1';
setdisp <= '1'; --word
setnextpass <= '1';
WHEN ld_AnXn1 => -- d(An,Xn)=>, --d(PC,Xn)=>
setstate <= "01";
next_micro_state <= ld_AnXn2;
WHEN ld_AnXn2 => -- d(An,Xn)=>, --d(PC,Xn)=>
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= ld_AnXn3;
WHEN ld_AnXn3 =>
get_ea_now <='1';
setdisp <= '1'; --brief
setdispbrief <= '1';
setnextpass <= '1';
WHEN st_dAn1 => -- =>d(An)
setstate <= "01";
next_micro_state <= st_dAn2;
WHEN st_dAn2 => -- =>d(An)
setstate <= "11";
setdisp <= '1'; --word
next_micro_state <= nop;
WHEN st_AnXn1 => -- =>d(An,Xn)
setstate <= "01";
next_micro_state <= st_AnXn2;
WHEN st_AnXn2 => -- =>d(An,Xn)
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= st_AnXn3;
WHEN st_AnXn3 =>
setstate <= "11";
setdisp <= '1'; --brief
setdispbrief <= '1';
next_micro_state <= nop;
WHEN bra1 => --bra
IF condition='1' THEN
TG68_PC_br8 <= '1'; --pc+0000
setstate <= "01";
next_micro_state <= bra2;
END IF;
WHEN bra2 => --bra
TG68_PC_brw <= '1';
WHEN bsr1 => --bsr
set_TG68_PC_dec <= '1'; --in 2 Takten -2
setstate <= "01";
next_micro_state <= bsr2;
WHEN bsr2 => --bsr
IF TG68_PC_dec(0)='1' THEN
TG68_PC_brw <= '1';
ELSE
TG68_PC_br8 <= '1';
END IF;
writePC <= '1';
setstate <= "11";
next_micro_state <= nop;
WHEN dbcc1 => --dbcc
TG68_PC_nop <= '1';
setstate <= "01";
next_micro_state <= dbcc2;
WHEN dbcc2 => --dbcc
TG68_PC_brw <= '1';
WHEN movem => --movem
set_movem_busy <='1';
setstate <= "10";
WHEN andi => --andi
IF opcode(5 downto 4)/="00" THEN
ea_build <= '1';
setnextpass <= '1';
END IF;
WHEN op_AxAy => -- op -(Ax),-(Ay)
presub <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_addsub <= '1';
setstate <= "10";
WHEN cmpm => -- cmpm (Ay)+,(Ax)+
postadd <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_rega <= '1';
setstate <= "10";
WHEN link => -- link
setstate <="11";
save_memaddr <= '1';
regwrena <= '1';
WHEN int1 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
next_micro_state <= int2;
WHEN int2 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= int3;
WHEN int3 => -- interrupt
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
setstate <= "10";
next_micro_state <= int4;
WHEN int4 => -- interrupt
datatype <= "10";
WHEN rte => -- RTE
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
WHEN trap1 => -- TRAP
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= trap2;
WHEN trap2 => -- TRAP
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
-- longreaddirect <= '1';
setstate <= "10";
next_micro_state <= trap3;
WHEN trap3 => -- TRAP
datatype <= "10";
WHEN movep1 => -- MOVEP d(An)
setstate <= "01";
IF opcode(6)='1' THEN
set_movepl <= '1';
END IF;
next_micro_state <= movep2;
WHEN movep2 =>
setdisp <= '1';
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
wait_mem_byte <= '1';
END IF;
next_micro_state <= movep3;
WHEN movep3 =>
IF opcode(6)='1' THEN
set_movepw <= '1';
next_micro_state <= movep4;
END IF;
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN movep4 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
wait_mem_byte <= '1';
setstate <= "11";
END IF;
next_micro_state <= movep5;
WHEN movep5 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN init1 => -- init SP
longreaddirect <= '1';
next_micro_state <= init2;
WHEN init2 => -- init PC
get_ea_now <='1'; --\
ea_only <= '1'; --- OP1in <= memaddr_in
setaddrlong <= '1'; -- memaddr_in <= data_read
regwrena <= '1';
setstackaddr <='1'; -- dest_addr <= SP
set_directPC <= '1';
longreaddirect <= '1';
next_micro_state <= nop;
WHEN mul1 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul2;
WHEN mul2 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul3;
WHEN mul3 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul4;
WHEN mul4 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul5;
WHEN mul5 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul6;
WHEN mul6 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul7;
WHEN mul7 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul8;
WHEN mul8 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul9;
WHEN mul9 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul10;
WHEN mul10 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul11;
WHEN mul11 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul12;
WHEN mul12 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul13;
WHEN mul13 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul14;
WHEN mul14 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul15;
WHEN mul15 => -- mulu
set_exec_MULU <= '1';
WHEN div1 => -- divu
IF OP2out(15 downto 0)=x"0000" THEN --div zero
set_Z_error <= '1';
ELSE
set_exec_DIVU <= '1';
next_micro_state <= div2;
END IF;
setstate <="01";
WHEN div2 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div3;
WHEN div3 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div4;
WHEN div4 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div5;
WHEN div5 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div6;
WHEN div6 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div7;
WHEN div7 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div8;
WHEN div8 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div9;
WHEN div9 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div10;
WHEN div10 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div11;
WHEN div11 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div12;
WHEN div12 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div13;
WHEN div13 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div14;
WHEN div14 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div15;
WHEN div15 => -- divu
set_exec_DIVU <= '1';
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Conditions
-----------------------------------------------------------------------------
PROCESS (opcode, Flags)
BEGIN
CASE opcode(11 downto 8) IS
WHEN X"0" => condition <= '1';
WHEN X"1" => condition <= '0';
WHEN X"2" => condition <= NOT Flags(0) AND NOT Flags(2);
WHEN X"3" => condition <= Flags(0) OR Flags(2);
WHEN X"4" => condition <= NOT Flags(0);
WHEN X"5" => condition <= Flags(0);
WHEN X"6" => condition <= NOT Flags(2);
WHEN X"7" => condition <= Flags(2);
WHEN X"8" => condition <= NOT Flags(1);
WHEN X"9" => condition <= Flags(1);
WHEN X"a" => condition <= NOT Flags(3);
WHEN X"b" => condition <= Flags(3);
WHEN X"c" => condition <= (Flags(3) AND Flags(1)) OR (NOT Flags(3) AND NOT Flags(1));
WHEN X"d" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1));
WHEN X"e" => condition <= (Flags(3) AND Flags(1) AND NOT Flags(2)) OR (NOT Flags(3) AND NOT Flags(1) AND NOT Flags(2));
WHEN X"f" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR Flags(2);
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Bits
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, OP2out, one_bit_in, one_bit_out, bit_Number, bit_number_reg)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --btst
one_bit_out <= one_bit_in;
WHEN "01" => --bchg
one_bit_out <= NOT one_bit_in;
WHEN "10" => --bclr
one_bit_out <= '0';
WHEN "11" => --bset
one_bit_out <= '1';
WHEN OTHERS => null;
END CASE;
IF opcode(8)='0' THEN
IF opcode(5 downto 4)="00" THEN
bit_number <= bit_number_reg(4 downto 0);
ELSE
bit_number <= "00"&bit_number_reg(2 downto 0);
END IF;
ELSE
IF opcode(5 downto 4)="00" THEN
bit_number <= OP2out(4 downto 0);
ELSE
bit_number <= "00"&OP2out(2 downto 0);
END IF;
END IF;
bits_out <= OP1out;
CASE bit_Number IS
WHEN "00000" => one_bit_in <= OP1out(0);
bits_out(0) <= one_bit_out;
WHEN "00001" => one_bit_in <= OP1out(1);
bits_out(1) <= one_bit_out;
WHEN "00010" => one_bit_in <= OP1out(2);
bits_out(2) <= one_bit_out;
WHEN "00011" => one_bit_in <= OP1out(3);
bits_out(3) <= one_bit_out;
WHEN "00100" => one_bit_in <= OP1out(4);
bits_out(4) <= one_bit_out;
WHEN "00101" => one_bit_in <= OP1out(5);
bits_out(5) <= one_bit_out;
WHEN "00110" => one_bit_in <= OP1out(6);
bits_out(6) <= one_bit_out;
WHEN "00111" => one_bit_in <= OP1out(7);
bits_out(7) <= one_bit_out;
WHEN "01000" => one_bit_in <= OP1out(8);
bits_out(8) <= one_bit_out;
WHEN "01001" => one_bit_in <= OP1out(9);
bits_out(9) <= one_bit_out;
WHEN "01010" => one_bit_in <= OP1out(10);
bits_out(10) <= one_bit_out;
WHEN "01011" => one_bit_in <= OP1out(11);
bits_out(11) <= one_bit_out;
WHEN "01100" => one_bit_in <= OP1out(12);
bits_out(12) <= one_bit_out;
WHEN "01101" => one_bit_in <= OP1out(13);
bits_out(13) <= one_bit_out;
WHEN "01110" => one_bit_in <= OP1out(14);
bits_out(14) <= one_bit_out;
WHEN "01111" => one_bit_in <= OP1out(15);
bits_out(15) <= one_bit_out;
WHEN "10000" => one_bit_in <= OP1out(16);
bits_out(16) <= one_bit_out;
WHEN "10001" => one_bit_in <= OP1out(17);
bits_out(17) <= one_bit_out;
WHEN "10010" => one_bit_in <= OP1out(18);
bits_out(18) <= one_bit_out;
WHEN "10011" => one_bit_in <= OP1out(19);
bits_out(19) <= one_bit_out;
WHEN "10100" => one_bit_in <= OP1out(20);
bits_out(20) <= one_bit_out;
WHEN "10101" => one_bit_in <= OP1out(21);
bits_out(21) <= one_bit_out;
WHEN "10110" => one_bit_in <= OP1out(22);
bits_out(22) <= one_bit_out;
WHEN "10111" => one_bit_in <= OP1out(23);
bits_out(23) <= one_bit_out;
WHEN "11000" => one_bit_in <= OP1out(24);
bits_out(24) <= one_bit_out;
WHEN "11001" => one_bit_in <= OP1out(25);
bits_out(25) <= one_bit_out;
WHEN "11010" => one_bit_in <= OP1out(26);
bits_out(26) <= one_bit_out;
WHEN "11011" => one_bit_in <= OP1out(27);
bits_out(27) <= one_bit_out;
WHEN "11100" => one_bit_in <= OP1out(28);
bits_out(28) <= one_bit_out;
WHEN "11101" => one_bit_in <= OP1out(29);
bits_out(29) <= one_bit_out;
WHEN "11110" => one_bit_in <= OP1out(30);
bits_out(30) <= one_bit_out;
WHEN "11111" => one_bit_in <= OP1out(31);
bits_out(31) <= one_bit_out;
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Rotation
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, rot_nop)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_rot <= OP1out(7);
WHEN "01"|"11" => --Word
rot_rot <= OP1out(15);
WHEN "10" => --Long
rot_rot <= OP1out(31);
WHEN OTHERS => null;
END CASE;
CASE rot_bits IS
WHEN "00" => --ASL, ASR
rot_lsb <= '0';
rot_msb <= rot_rot;
WHEN "01" => --LSL, LSR
rot_lsb <= '0';
rot_msb <= '0';
WHEN "10" => --ROXL, ROXR
rot_lsb <= Flags(4);
rot_msb <= Flags(4);
WHEN "11" => --ROL, ROR
rot_lsb <= rot_rot;
rot_msb <= OP1out(0);
WHEN OTHERS => null;
END CASE;
IF rot_nop='1' THEN
rot_out <= OP1out;
rot_XC <= Flags(0);
ELSE
IF opcode(8)='1' THEN --left
rot_out <= OP1out(30 downto 0)&rot_lsb;
rot_XC <= rot_rot;
ELSE --right
rot_XC <= OP1out(0);
rot_out <= rot_msb&OP1out(31 downto 1);
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_out(7) <= rot_msb;
WHEN "01"|"11" => --Word
rot_out(15) <= rot_msb;
WHEN OTHERS =>
END CASE;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- MULU/MULS
-----------------------------------------------------------------------------
PROCESS (clk, opcode, OP2out, muls_msb, mulu_reg, OP1sign, sign2)
BEGIN
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(15)='1' THEN --MULS Neg faktor
OP1sign <= '1';
mulu_reg <= "0000000000000000"&(0-reg_QB(15 downto 0));
ELSE
OP1sign <= '0';
mulu_reg <= "0000000000000000"®_QB(15 downto 0);
END IF;
ELSIF exec_MULU='1' THEN
mulu_reg <= dummy_mulu;
END IF;
END IF;
END IF;
IF (opcode(8)='1' AND OP2out(15)='1') OR OP1sign='1' THEN
muls_msb <= mulu_reg(31);
ELSE
muls_msb <= '0';
END IF;
IF opcode(8)='1' AND OP2out(15)='1' THEN
sign2 <= '1';
ELSE
sign2 <= '0';
END IF;
IF mulu_reg(0)='1' THEN
IF OP1sign='1' THEN
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))-(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
ELSE
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))+(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
END IF;
ELSE
dummy_mulu <= muls_msb&mulu_reg(31 downto 1);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- DIVU
-----------------------------------------------------------------------------
PROCESS (clk, execOPC, opcode, OP1out, OP2out, div_reg, dummy_div_sub, div_quot, div_sign, dummy_div_over, dummy_div)
BEGIN
set_V_Flag <= '0';
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(31)='1' THEN -- Neg divisor
div_sign <= '1';
div_reg <= 0-reg_QB;
ELSE
div_sign <= '0';
div_reg <= reg_QB;
END IF;
ELSIF exec_DIVU='1' THEN
div_reg <= div_quot;
END IF;
END IF;
END IF;
dummy_div_over <= ('0'&OP1out(31 downto 16))-('0'&OP2out(15 downto 0));
IF opcode(8)='1' AND OP2out(15) ='1' THEN
dummy_div_sub <= (div_reg(31 downto 15))+('1'&OP2out(15 downto 0));
ELSE
dummy_div_sub <= (div_reg(31 downto 15))-('0'&OP2out(15 downto 0));
END IF;
IF (dummy_div_sub(16))='1' THEN
div_quot(31 downto 16) <= div_reg(30 downto 15);
ELSE
div_quot(31 downto 16) <= dummy_div_sub(15 downto 0);
END IF;
div_quot(15 downto 0) <= div_reg(14 downto 0)&NOT dummy_div_sub(16);
IF execOPC='1' AND opcode(8)='1' AND (OP2out(15) XOR div_sign)='1' THEN
dummy_div(15 downto 0) <= 0-div_quot(15 downto 0);
ELSE
dummy_div(15 downto 0) <= div_quot(15 downto 0);
END IF;
IF div_sign='1' THEN
dummy_div(31 downto 16) <= 0-div_quot(31 downto 16);
ELSE
dummy_div(31 downto 16) <= div_quot(31 downto 16);
END IF;
IF (opcode(8)='1' AND (OP2out(15) XOR div_sign XOR dummy_div(15))='1' AND dummy_div(15 downto 0)/=X"0000") --Overflow DIVS
OR (opcode(8)='0' AND dummy_div_over(16)='0') THEN --Overflow DIVU
set_V_Flag <= '1';
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Movem
-----------------------------------------------------------------------------
PROCESS (reset, clk, movem_mask, movem_muxa ,movem_muxb, movem_muxc)
BEGIN
IF movem_mask(7 downto 0)="00000000" THEN
movem_muxa <= movem_mask(15 downto 8);
movem_regaddr(3) <= '1';
ELSE
movem_muxa <= movem_mask(7 downto 0);
movem_regaddr(3) <= '0';
END IF;
IF movem_muxa(3 downto 0)="0000" THEN
movem_muxb <= movem_muxa(7 downto 4);
movem_regaddr(2) <= '1';
ELSE
movem_muxb <= movem_muxa(3 downto 0);
movem_regaddr(2) <= '0';
END IF;
IF movem_muxb(1 downto 0)="00" THEN
movem_muxc <= movem_muxb(3 downto 2);
movem_regaddr(1) <= '1';
ELSE
movem_muxc <= movem_muxb(1 downto 0);
movem_regaddr(1) <= '0';
END IF;
IF movem_muxc(0)='0' THEN
movem_regaddr(0) <= '1';
ELSE
movem_regaddr(0) <= '0';
END IF;
movem_bits <= ("0000"&movem_mask(0))+("0000"&movem_mask(1))+("0000"&movem_mask(2))+("0000"&movem_mask(3))+
("0000"&movem_mask(4))+("0000"&movem_mask(5))+("0000"&movem_mask(6))+("0000"&movem_mask(7))+
("0000"&movem_mask(8))+("0000"&movem_mask(9))+("0000"&movem_mask(10))+("0000"&movem_mask(11))+
("0000"&movem_mask(12))+("0000"&movem_mask(13))+("0000"&movem_mask(14))+("0000"&movem_mask(15));
IF reset = '0' THEN
movem_busy <= '0';
movem_addr <= '0';
maskzero <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND get_movem_mask='1' AND enaWRreg='1' THEN
movem_mask <= data_read(15 downto 0);
END IF;
IF clkena_in='1' AND test_maskzero='1' AND enaWRreg='1' THEN
IF movem_mask=X"0000" THEN
maskzero <= '1';
END IF;
END IF;
IF clkena_in='1' AND endOPC='1' AND enaWRreg='1' THEN
maskzero <= '0';
END IF;
IF clkena='1' THEN
IF set_movem_busy='1' THEN
IF movem_bits(4 downto 1) /= "0000" OR opcode(10)='0' THEN
movem_busy <= '1';
END IF;
movem_addr <= '1';
END IF;
IF movem_addr='1' THEN
CASE movem_regaddr IS
WHEN "0000" => movem_mask(0) <= '0';
WHEN "0001" => movem_mask(1) <= '0';
WHEN "0010" => movem_mask(2) <= '0';
WHEN "0011" => movem_mask(3) <= '0';
WHEN "0100" => movem_mask(4) <= '0';
WHEN "0101" => movem_mask(5) <= '0';
WHEN "0110" => movem_mask(6) <= '0';
WHEN "0111" => movem_mask(7) <= '0';
WHEN "1000" => movem_mask(8) <= '0';
WHEN "1001" => movem_mask(9) <= '0';
WHEN "1010" => movem_mask(10) <= '0';
WHEN "1011" => movem_mask(11) <= '0';
WHEN "1100" => movem_mask(12) <= '0';
WHEN "1101" => movem_mask(13) <= '0';
WHEN "1110" => movem_mask(14) <= '0';
WHEN "1111" => movem_mask(15) <= '0';
WHEN OTHERS => null;
END CASE;
IF opcode(10)='1' THEN
IF movem_bits="00010" OR movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
END IF;
END IF;
IF movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
movem_addr <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END;
| gpl-3.0 | e85e28ad8133ed0288e096ad0ad2837c | 0.481165 | 3.130848 | false | false | false | false |
HackLinux/ION | src/application/interfaces/ion_gpio_interface.vhdl | 1 | 5,021 | --------------------------------------------------------------------------------
-- ion_gpio_interface.vhdl -- Simple GPIO block with WB interface.
--------------------------------------------------------------------------------
--
-- This module provides a number N (currently hardwired to N=1) of input/output
-- port pairs of configurable width PORT_WIDTH.
-- Each port has an output port and an input port, each PORT_WIDTH bits wide.
--
-- Output ports are write only since they share the same address with the read
-- register of the pair.
--
-- Read ports are registered (a single register per input) but you may want to
-- supply extra registers for protection against metastability.
--
-- Only the lower bits of the data are significan when writing, and when
-- reading all bits above PORT_WIDTH will read as zero.
--
-- REFERENCES
-- [1] ion_design_notes.pdf -- ION project design notes.
--------------------------------------------------------------------------------
-- REGISTER MAP:
--
-- When EN_I is asserted, bits 3 to 2 of the address will be decoded as this:
--
-- 00 write : Writes to GPIO_0_OUT
-- 00 read : Reads from GPIO_0_IN
-- 1x, x1 : Undefined
--------------------------------------------------------------------------------
-- THINGS TO BE DONE:
--
-- Eventually, a set/reset register will be added for each output port. This
-- is why the width is limited to 16 bits.
-- Also eventually the number of ports will be configurable.
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ION_GPIO_INTERFACE is
generic(
-- Width of all GPIO ports in bits (1 to 16)
PORT_WIDTH : natural := 16
);
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
-- Core WB interface (this module is a WB slave).
WB_MOSI_I : in t_wishbone_mosi;
WB_MISO_O : out t_wishbone_miso;
-- Enable: WB ignored unless this input is asserted.
EN_I : in std_logic;
-- I/O ports (always in pairs).
GPIO_0_O : out std_logic_vector(PORT_WIDTH-1 downto 0);
GPIO_0_I : in std_logic_vector(PORT_WIDTH-1 downto 0)
);
end;
architecture rtl of ION_GPIO_INTERFACE is
subtype t_port is std_logic_vector(PORT_WIDTH-1 downto 0);
signal port0_inp_reg : t_port;
begin
-- Make sure the generic value is within bounds.
assert (PORT_WIDTH >= 1) and (PORT_WIDTH <= 16)
report "Invalid port width value for ION_GPIO_INTERFACE module."
severity failure;
-- Eventually this will be parameterizable and we'll have a generate loop
-- here with several registers. for the time being we have only the one.
port_0_output_reg:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
GPIO_0_O <= (others => '0');
elsif WB_MOSI_I.stb = '1' and WB_MOSI_I.we = '1' and EN_I='1' then
GPIO_0_O <= WB_MOSI_I.dat(PORT_WIDTH-1 downto 0);
end if;
end if;
end process port_0_output_reg;
port_0_input_reg:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
port0_inp_reg <= (others => '0');
else
port0_inp_reg <= GPIO_0_I;
end if;
end if;
end process port_0_input_reg;
-- WB interface ------------------------------------------------------------
-- No need to multiplex output data for the time being.
WB_MISO_O.dat(31 downto PORT_WIDTH) <= (others => '0');
WB_MISO_O.dat(PORT_WIDTH-1 downto 0) <= port0_inp_reg;
-- No wait states.
WB_MISO_O.stall <= '0';
WB_MISO_O.ack <= '1';
end architecture rtl;
| lgpl-3.0 | 2cbfdaaee63449470ee9a82b201a8014 | 0.573193 | 4.062298 | false | false | false | false |
HackLinux/ION | boards/terasic_de1/src/de1_demo.vhdl | 1 | 16,165 | --##############################################################################
-- de1_demo.vhdl -- ION CPU demo on Terasic DE-1 Cyclone-II starter board.
--##############################################################################
-- This module is little more than a wrapper around the application entity.
--------------------------------------------------------------------------------
-- Switch 9 (leftmost) is used as reset.
--------------------------------------------------------------------------------
-- NOTE: See note at bottom of file about optional use of PLL.
--##############################################################################
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Hardware parameters & memory contents from SW build (generated package).
use work.OBJ_CODE_PKG.all;
-- Top entity is a generic wrapper with all the I/O of Terasic DE-1 board.
-- (Many of the board's i/o devices will go unused in this demo)
entity de1_demo is
port (
-- ***** Clocks
clk_50MHz : in std_logic;
clk_27MHz : in std_logic;
-- ***** Flash 4MB
flash_addr : out std_logic_vector(21 downto 0);
flash_data : in std_logic_vector(7 downto 0);
flash_oe_n : out std_logic;
flash_we_n : out std_logic;
flash_reset_n : out std_logic;
-- ***** SRAM 256K x 16
sram_addr : out std_logic_vector(17 downto 0);
sram_data : inout std_logic_vector(15 downto 0);
sram_oe_n : out std_logic;
sram_ub_n : out std_logic;
sram_lb_n : out std_logic;
sram_ce_n : out std_logic;
sram_we_n : out std_logic;
-- ***** RS-232
rxd : in std_logic;
txd : out std_logic;
-- ***** Switches and buttons
switches : in std_logic_vector(9 downto 0);
buttons : in std_logic_vector(3 downto 0);
-- ***** Quad 7-seg displays
hex0 : out std_logic_vector(0 to 6);
hex1 : out std_logic_vector(0 to 6);
hex2 : out std_logic_vector(0 to 6);
hex3 : out std_logic_vector(0 to 6);
-- ***** Leds
red_leds : out std_logic_vector(9 downto 0);
green_leds : out std_logic_vector(7 downto 0);
-- ***** SD Card
sd_data : in std_logic;
sd_cs : out std_logic;
sd_cmd : out std_logic;
sd_clk : out std_logic
);
end de1_demo;
architecture minimal of de1_demo is
--##############################################################################
-- Parameters of the demo board (MPU parameters are set in a gnerated package).
-- Clock rate selection (affects UART configuration)
-- Acceptable values: {27000000, 50000000, 45000000(pll config)}
constant CLOCK_FREQ : integer := 50000000;
--##############################################################################
-- I/O registers.
signal p0_out : std_logic_vector(31 downto 0);
signal p1_in : std_logic_vector(31 downto 0);
--##############################################################################
-- DE-1 board interface signals
-- Synchronization FF chain for asynchronous reset input
signal reset_sync : std_logic_vector(3 downto 0);
-- Reset pushbutton debouncing logic
subtype t_debouncer is natural range 0 to CLOCK_FREQ*4;
constant DEBOUNCING_DELAY : t_debouncer := 1500;
signal debouncing_counter : t_debouncer := (CLOCK_FREQ/1000) * DEBOUNCING_DELAY;
-- Quad 7-segment display (non multiplexed) & LEDS
signal display_data : std_logic_vector(15 downto 0);
signal reg_gleds : std_logic_vector(7 downto 0);
-- Clock & reset signals
signal clk_1hz : std_logic;
signal clk_master : std_logic;
signal counter_1hz : std_logic_vector(25 downto 0);
signal reset : std_logic;
-- Master clock signal
signal clk : std_logic;
-- Clock from PLL, if a PLL is used
signal clk_pll : std_logic;
-- '1' when PLL is locked or when no PLL is used
signal pll_locked : std_logic;
-- Altera PLL component declaration (in case it's used)
-- Note that the MegaWizard component needs to be called 'pll' or the component
-- name should be changed in this file.
--component pll
-- port (
-- areset : in std_logic := '0';
-- inclk0 : in std_logic := '0';
-- c0 : out std_logic ;
-- locked : out std_logic
-- );
--end component;
-- MPU interface signals
constant SRAM_SIZE : integer := 256 * 1024;
constant SRAM_ADDR_SIZE : integer := 18;
signal mpu_sram_addr : std_logic_vector(SRAM_ADDR_SIZE downto 1);
signal mpu_sram_data_in : std_logic_vector(15 downto 0);
signal mpu_sram_data_out : std_logic_vector(15 downto 0);
signal sram_output : std_logic_vector(15 downto 0);
signal sram_wen : std_logic;
signal sram_ben : std_logic_vector(1 downto 0);
signal sram_oen : std_logic;
signal sram_cen : std_logic;
signal sram_drive_en : std_logic;
signal irq : std_logic_vector(5 downto 0);
signal port0_out : std_logic_vector(15 downto 0);
signal port0_in : std_logic_vector(15 downto 0);
-- Converts hex nibble to 7-segment
-- Segments ordered as "GFEDCBA"; '0' is ON, '1' is OFF
function nibble_to_7seg(nibble : std_logic_vector(3 downto 0))
return std_logic_vector is
begin
case nibble is
when X"0" => return "0000001";
when X"1" => return "1001111";
when X"2" => return "0010010";
when X"3" => return "0000110";
when X"4" => return "1001100";
when X"5" => return "0100100";
when X"6" => return "0100000";
when X"7" => return "0001111";
when X"8" => return "0000000";
when X"9" => return "0000100";
when X"a" => return "0001000";
when X"b" => return "1100000";
when X"c" => return "0110001";
when X"d" => return "1000010";
when X"e" => return "0110000";
when X"f" => return "0111000";
when others => return "0111111"; -- can't happen
end case;
end function nibble_to_7seg;
begin
--##############################################################################
-- CPU application core instance
--##############################################################################
mpu: entity work.ION_APPLICATION
generic map (
TCM_CODE_SIZE => CODE_MEM_SIZE,
TCM_CODE_INIT => OBJ_CODE,
TCM_DATA_SIZE => DATA_MEM_SIZE,
SRAM_SIZE => SRAM_SIZE,
DATA_CACHE_LINES => 128,
CODE_CACHE_LINES => 0
)
port map (
CLK_I => clk_27MHz, -- clk_50MHz,
RESET_I => reset,
SRAM_ADDR_O => mpu_sram_addr,
SRAM_DATA_O => mpu_sram_data_out,
SRAM_DATA_I => mpu_sram_data_in,
SRAM_WEn_O => sram_wen,
SRAM_OEn_O => sram_oen,
SRAM_UBn_O => sram_ben(1),
SRAM_LBn_O => sram_ben(0),
SRAM_CEn_O => sram_cen,
SRAM_DRIVE_EN_O => sram_drive_en,
IRQ_I => irq,
GPIO_0_OUT_O => port0_out,
GPIO_0_INP_I => port0_in
);
-- FIXME HW interrupts not connected.
irq <= (others => '0');
-- FIXME GPIO ports looped back as in the simulation TBs.
port0_in <= port0_out;
-- Make sure we don't attempt to infer more RAM than the DE-1 chip has.
-- We'll define arbitrary bounds for the code and data TCMs; remember that
-- TCM sizes are in 32-bit words.
assert CODE_MEM_SIZE <= 4096
report "Code TCM size too large for target chip."
severity failure;
assert DATA_MEM_SIZE <= 2048
report "Data TCM size too large for target chip."
severity failure;
--##############################################################################
-- GPIO and LEDs
--##############################################################################
---- LEDS -- We'll use the LEDs to display debug info --------------------------
-- Show the SD interface signals on the green leds for debug
reg_gleds <= p1_in(0) & "0000" & p0_out(2 downto 0);
-- Red leds (light with '1') -- some CPU control signals
red_leds(0) <= '0';
red_leds(1) <= '0';
red_leds(2) <= '0';
red_leds(3) <= '0';
red_leds(4) <= '0';
red_leds(5) <= '0';
red_leds(6) <= '0';
red_leds(7) <= '0';
red_leds(8) <= reset;
red_leds(9) <= clk_1hz;
--##############################################################################
-- terasIC Cyclone II STARTER KIT BOARD -- interface to on-board devices
--##############################################################################
--##############################################################################
-- FLASH
--##############################################################################
-- The FLASH memory is not used in this demo.
flash_we_n <= '1';
flash_reset_n <= '1';
flash_addr <= (others => '0');
flash_oe_n <= '1';
--##############################################################################
-- SRAM
--##############################################################################
-- The SRAM pins are wired straight into the SRAM interface of the MPU core.
sram_addr <= mpu_sram_addr(SRAM_ADDR_SIZE downto 1);
sram_oe_n <= sram_oen;
sram_data <=
mpu_sram_data_out when sram_drive_en='1' else
(others => 'Z');
mpu_sram_data_in <= sram_data;
sram_ub_n <= sram_ben(1);
sram_lb_n <= sram_ben(0);
sram_ce_n <= sram_cen;
sram_we_n <= sram_wen;
--##############################################################################
-- RESET, CLOCK
--##############################################################################
-- This FF chain only prevents metastability trouble, it does not help with
-- switching bounces.
-- (NOTE: the anti-metastability logic is probably not needed when we include
-- the debouncing logic)
reset_synchronization:
process(clk)
begin
if clk'event and clk='1' then
reset_sync(3) <= not switches(9);
reset_sync(2) <= reset_sync(3);
reset_sync(1) <= reset_sync(2);
reset_sync(0) <= reset_sync(1);
end if;
end process reset_synchronization;
reset_debouncing:
process(clk)
begin
if clk'event and clk='1' then
if reset_sync(0)='1' and reset_sync(1)='0' then
debouncing_counter <= (CLOCK_FREQ/1000) * DEBOUNCING_DELAY;
else
if debouncing_counter /= 0 then
debouncing_counter <= debouncing_counter - 1;
end if;
end if;
end if;
end process reset_debouncing;
-- Reset will be active and glitch free for some serious time (1.5 s).
reset <= '1' when debouncing_counter /= 0 or pll_locked='0' else '0';
-- Generate a 1-Hz 'clock' to flash a LED for visual reference.
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
clk_1hz <= '0';
counter_1hz <= (others => '0');
else
if conv_integer(counter_1hz) = CLOCK_FREQ-1 then
counter_1hz <= (others => '0');
clk_1hz <= not clk_1hz;
else
counter_1hz <= counter_1hz + 1;
end if;
end if;
end if;
end process;
-- Master clock is external 50MHz or 27MHz oscillator
slow_clock:
if CLOCK_FREQ = 27000000 generate
clk <= clk_27MHz;
pll_locked <= '1';
end generate;
fast_clock:
if CLOCK_FREQ = 50000000 generate
clk <= clk_50MHz;
pll_locked <= '1';
end generate;
--pll_clock:
--if CLOCK_FREQ /= 27000000 and CLOCK_FREQ/=50000000 generate
---- Assume PLL black box is properly configured for whatever the clock rate is...
--input_clock_pll: component pll
-- port map(
-- areset => '0',
-- inclk0 => clk_50MHz,
-- c0 => clk_pll,
-- locked => pll_locked
-- );
--
--clk <= clk_pll;
--end generate;
--##############################################################################
-- LEDS, SWITCHES
--##############################################################################
-- Display the contents of a debug register at the green leds bar
green_leds <= reg_gleds;
--##############################################################################
-- QUAD 7-SEGMENT DISPLAYS
--##############################################################################
-- Show contents of debug register in hex display
display_data <= port0_out;
-- 7-segment encoders; the dev board displays are not multiplexed or encoded
hex3 <= nibble_to_7seg(display_data(15 downto 12));
hex2 <= nibble_to_7seg(display_data(11 downto 8));
hex1 <= nibble_to_7seg(display_data( 7 downto 4));
hex0 <= nibble_to_7seg(display_data( 3 downto 0));
--##############################################################################
-- SD card interface
--##############################################################################
-- Connect to FFs for use in bit-banged interface (still unused)
sd_cs <= p0_out(0); -- SPI CS
sd_cmd <= p0_out(2); -- SPI DI
sd_clk <= p0_out(1); -- SPI SCLK
p1_in(0) <= sd_data; -- SPI DO
--##############################################################################
-- SERIAL
--##############################################################################
-- Embedded in the MPU entity
end minimal;
--------------------------------------------------------------------------------
-- NOTE: Optional use of a PLL
--
-- In order to try the core with any clock other the 50 and 27MHz oscillators
-- readily available onboard we need to use a PLL.
-- Unfortunately, Quartus-II won't let you just instantiate a PLL like ISE does.
-- Instead, you have to build a PLL module using the MegaWizard tool.
-- A nasty consequence of this is that the PLL can't be reconfigured without
-- rebuilding it with the MW tool, and a bunch of ugly binary files have to be
-- committed to SVN if the project is to be complete.
-- When I figure up what files need to be committed to SVN I will. Meanwhile you
-- have to build the module yourself if you want to use a PLL -- Sorry!
-- At least it is very straightforward -- create an ALTPLL variation (from the
-- IO module library) named 'pll' with a 45MHz clock at output c0, that's it.
--
-- Please note that the system will run at >50MHz when using 'balanced'
-- synthesis. Only the 'area optimized' synthesis may give you trouble.
--------------------------------------------------------------------------------
| lgpl-3.0 | ada7d5d01f48320e1fe55e2c6bf9eecd | 0.49935 | 4.127937 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN16_DEC8b10b.vhd | 2 | 17,946 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/24/2014
--! Module Name: EPROC_IN16_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use work.all;
use work.centralRouter_package.all;
--! 8b10b decoder for EPROC_IN16 module
entity EPROC_IN16_DEC8b10b is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (15 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
busyOut : out std_logic
);
end EPROC_IN16_DEC8b10b;
architecture Behavioral of EPROC_IN16_DEC8b10b is
----------------------------------
----------------------------------
component KcharTest is
port (
clk : in std_logic;
encoded10in : in std_logic_vector (9 downto 0);
KcharCode : out std_logic_vector (1 downto 0)
);
end component KcharTest;
----------------------------------
----------------------------------
signal EDATAbitstreamSREG : std_logic_vector (95 downto 0) := (others=>'0'); -- 96 bit (16 x 5 = 80, plus 16 more)
signal word10bx8_align_array, word10bx8_align_array_r, word10bx8_align_array_s1, word10bx8_align_array_s2 : word10b_8array_16array_type;
signal word10b_array, word10b_array_s : word10b_8array_type;
signal isk_array : isk_8array_type;
signal comma_valid_bits_or, word10bx8_align_rdy_s1, word10bx8_align_rdy_s2, word10bx8_align_rdy_r,
word10b_array_rdy, word10b_array_rdy_s, word10b_array_rdy_s1, realignment_ena : std_logic;
signal align_select, align_select_work, align_select_current, align_select_work_s, align_select_work_s1 : std_logic_vector (3 downto 0) := (others=>'0');
signal comma_valid_bits : std_logic_vector (15 downto 0);
signal alignment_sreg : std_logic_vector (4 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- 96 bit input shift register
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
EDATAbitstreamSREG <= (others => '0');
elsif bitCLK'event and bitCLK = '1' then
EDATAbitstreamSREG <= edataIN & EDATAbitstreamSREG(95 downto 16);
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock0
-- input shift register mapping into 10 bit registers
-------------------------------------------------------------------------------------------
input_map: for I in 0 to 15 generate -- 8 10bit-words per alignment, 16 possible alignments
--word10bx8_align_array(I)(0) <= EDATAbitstreamSREG((I+9) downto (I+0)); -- 1st 10 bit word, alligned to bit I
--word10bx8_align_array(I)(1) <= EDATAbitstreamSREG((I+19) downto (I+10)); -- 2nd 10 bit word, alligned to bit I
--word10bx8_align_array(I)(2) <= EDATAbitstreamSREG((I+29) downto (I+20)); -- 3rd 10 bit word, alligned to bit I
--word10bx8_align_array(I)(3) <= EDATAbitstreamSREG((I+39) downto (I+30)); -- 4th 10 bit word, alligned to bit I
--word10bx8_align_array(I)(4) <= EDATAbitstreamSREG((I+49) downto (I+40)); -- 5th 10 bit word, alligned to bit I
--word10bx8_align_array(I)(5) <= EDATAbitstreamSREG((I+59) downto (I+50)); -- 6th 10 bit word, alligned to bit I
--word10bx8_align_array(I)(6) <= EDATAbitstreamSREG((I+69) downto (I+60)); -- 7th 10 bit word, alligned to bit I
--word10bx8_align_array(I)(7) <= EDATAbitstreamSREG((I+79) downto (I+70)); -- 8th 10 bit word, alligned to bit I
word10bx8_align_array(I)(0) <= EDATAbitstreamSREG(I+0)&EDATAbitstreamSREG(I+1)&EDATAbitstreamSREG(I+2)&EDATAbitstreamSREG(I+3)&EDATAbitstreamSREG(I+4)&
EDATAbitstreamSREG(I+5)&EDATAbitstreamSREG(I+6)&EDATAbitstreamSREG(I+7)&EDATAbitstreamSREG(I+8)&EDATAbitstreamSREG(I+9); -- 1st 10 bit word, alligned to bit I
word10bx8_align_array(I)(1) <= EDATAbitstreamSREG(I+10)&EDATAbitstreamSREG(I+11)&EDATAbitstreamSREG(I+12)&EDATAbitstreamSREG(I+13)&EDATAbitstreamSREG(I+14)&
EDATAbitstreamSREG(I+15)&EDATAbitstreamSREG(I+16)&EDATAbitstreamSREG(I+17)&EDATAbitstreamSREG(I+18)&EDATAbitstreamSREG(I+19); -- 2nd 10 bit word, alligned to bit I
word10bx8_align_array(I)(2) <= EDATAbitstreamSREG(I+20)&EDATAbitstreamSREG(I+21)&EDATAbitstreamSREG(I+22)&EDATAbitstreamSREG(I+23)&EDATAbitstreamSREG(I+24)&
EDATAbitstreamSREG(I+25)&EDATAbitstreamSREG(I+26)&EDATAbitstreamSREG(I+27)&EDATAbitstreamSREG(I+28)&EDATAbitstreamSREG(I+29); -- 3rd 10 bit word, alligned to bit I
word10bx8_align_array(I)(3) <= EDATAbitstreamSREG(I+30)&EDATAbitstreamSREG(I+31)&EDATAbitstreamSREG(I+32)&EDATAbitstreamSREG(I+33)&EDATAbitstreamSREG(I+34)&
EDATAbitstreamSREG(I+35)&EDATAbitstreamSREG(I+36)&EDATAbitstreamSREG(I+37)&EDATAbitstreamSREG(I+38)&EDATAbitstreamSREG(I+39); -- 4th 10 bit word, alligned to bit I
word10bx8_align_array(I)(4) <= EDATAbitstreamSREG(I+40)&EDATAbitstreamSREG(I+41)&EDATAbitstreamSREG(I+42)&EDATAbitstreamSREG(I+43)&EDATAbitstreamSREG(I+44)&
EDATAbitstreamSREG(I+45)&EDATAbitstreamSREG(I+46)&EDATAbitstreamSREG(I+47)&EDATAbitstreamSREG(I+48)&EDATAbitstreamSREG(I+49); -- 5th 10 bit word, alligned to bit I
word10bx8_align_array(I)(5) <= EDATAbitstreamSREG(I+50)&EDATAbitstreamSREG(I+51)&EDATAbitstreamSREG(I+52)&EDATAbitstreamSREG(I+53)&EDATAbitstreamSREG(I+54)&
EDATAbitstreamSREG(I+55)&EDATAbitstreamSREG(I+56)&EDATAbitstreamSREG(I+57)&EDATAbitstreamSREG(I+58)&EDATAbitstreamSREG(I+59); -- 6th 10 bit word, alligned to bit I
word10bx8_align_array(I)(6) <= EDATAbitstreamSREG(I+60)&EDATAbitstreamSREG(I+61)&EDATAbitstreamSREG(I+62)&EDATAbitstreamSREG(I+63)&EDATAbitstreamSREG(I+64)&
EDATAbitstreamSREG(I+65)&EDATAbitstreamSREG(I+66)&EDATAbitstreamSREG(I+67)&EDATAbitstreamSREG(I+68)&EDATAbitstreamSREG(I+69); -- 7th 10 bit word, alligned to bit I
word10bx8_align_array(I)(7) <= EDATAbitstreamSREG(I+70)&EDATAbitstreamSREG(I+71)&EDATAbitstreamSREG(I+72)&EDATAbitstreamSREG(I+73)&EDATAbitstreamSREG(I+74)&
EDATAbitstreamSREG(I+75)&EDATAbitstreamSREG(I+76)&EDATAbitstreamSREG(I+77)&EDATAbitstreamSREG(I+78)&EDATAbitstreamSREG(I+79); -- 8th 10 bit word, alligned to bit I
end generate input_map;
-------------------------------------------------------------------------------------------
--clock0
-- K28.5 comma test
-------------------------------------------------------------------------------------------
comma_test: for I in 0 to 15 generate -- 8 10bit-words per alignment, comma is valid if two first words have comma
comma_valid_bits(I) <= '1' when ((word10bx8_align_array(I)(0) = COMMAp or word10bx8_align_array(I)(0) = COMMAn) and
(word10bx8_align_array(I)(1) = COMMAp or word10bx8_align_array(I)(1) = COMMAn)) else '0';
end generate comma_test;
--
comma_valid_bits_or <= comma_valid_bits(15) or comma_valid_bits(14) or comma_valid_bits(13) or comma_valid_bits(12) or
comma_valid_bits(11) or comma_valid_bits(10) or comma_valid_bits(9) or comma_valid_bits(8) or
comma_valid_bits(7) or comma_valid_bits(6) or comma_valid_bits(5) or comma_valid_bits(4) or
comma_valid_bits(3) or comma_valid_bits(2) or comma_valid_bits(1) or comma_valid_bits(0);
--
-------------------------------------------------------------------------------------------
--clock1
-- alignment selector state
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
alignment_sreg <= "00000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
alignment_sreg <= "10000";
else
alignment_sreg <= alignment_sreg(0) & alignment_sreg(4 downto 1);
end if;
end if;
end process;
--
input_reg1: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10bx8_align_array_s1 <= word10bx8_align_array;
end if;
end process;
--
word10bx8_align_rdy_s1 <= alignment_sreg(4);
--
process(bitCLK, rst)
begin
if rst = '1' then
align_select <= "0000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
align_select(0) <= (not comma_valid_bits(0)) and (
comma_valid_bits(1) or ( (not comma_valid_bits(1)) and (not comma_valid_bits(2)) and (
comma_valid_bits(3) or ( (not comma_valid_bits(3)) and (not comma_valid_bits(4)) and (
comma_valid_bits(5) or ( (not comma_valid_bits(5)) and (not comma_valid_bits(6)) and (
comma_valid_bits(7) or ( (not comma_valid_bits(7)) and (not comma_valid_bits(8)) and (
comma_valid_bits(9) or ( (not comma_valid_bits(9)) and (not comma_valid_bits(10)) and (
comma_valid_bits(11) or ( (not comma_valid_bits(11)) and (not comma_valid_bits(12)) and (
comma_valid_bits(13) or ( (not comma_valid_bits(13)) and (not comma_valid_bits(14)) and (
comma_valid_bits(15)
)))))))))))))));
align_select(1) <= ((not comma_valid_bits(0)) and (not comma_valid_bits(1))) and (
(comma_valid_bits(2) or comma_valid_bits(3)) or (
((not comma_valid_bits(2)) and (not comma_valid_bits(3)) and (not comma_valid_bits(4)) and (not comma_valid_bits(5))) and (
(comma_valid_bits(6) or comma_valid_bits(7)) or (
((not comma_valid_bits(6)) and (not comma_valid_bits(7)) and (not comma_valid_bits(8)) and (not comma_valid_bits(9))) and (
(comma_valid_bits(10) or comma_valid_bits(11)) or (
((not comma_valid_bits(10)) and (not comma_valid_bits(11)) and (not comma_valid_bits(12)) and (not comma_valid_bits(13))) and (
(comma_valid_bits(14) or comma_valid_bits(15))
)))))));
align_select(2) <= ((not comma_valid_bits(0)) and (not comma_valid_bits(1)) and (not comma_valid_bits(2)) and (not comma_valid_bits(3))) and (
(comma_valid_bits(4) or comma_valid_bits(5) or comma_valid_bits(6) or comma_valid_bits(7)) or (
((not comma_valid_bits(4)) and (not comma_valid_bits(5)) and (not comma_valid_bits(6)) and (not comma_valid_bits(7)) and (not comma_valid_bits(8)) and (not comma_valid_bits(9)) and (not comma_valid_bits(10)) and (not comma_valid_bits(11))) and (
(comma_valid_bits(12) or comma_valid_bits(13) or comma_valid_bits(14) or comma_valid_bits(15))
)));
align_select(3) <= ((not comma_valid_bits(0)) and (not comma_valid_bits(1)) and (not comma_valid_bits(2)) and (not comma_valid_bits(3)) and (not comma_valid_bits(4)) and (not comma_valid_bits(5)) and (not comma_valid_bits(6)) and (not comma_valid_bits(7))) and (
comma_valid_bits(8) or comma_valid_bits(9) or comma_valid_bits(10) or comma_valid_bits(11) or comma_valid_bits(12) or comma_valid_bits(13) or comma_valid_bits(14) or comma_valid_bits(15)
);
end if;
end if;
end process;
--
align_select_work_s <= "0000" when (align_select_current = "0000" and align_select = "1010") else
"0001" when (align_select_current = "0001" and align_select = "1011") else
"0010" when (align_select_current = "0010" and align_select = "1100") else
"0011" when (align_select_current = "0011" and align_select = "1101") else
"0100" when (align_select_current = "0100" and align_select = "1110") else
"0101" when (align_select_current = "0101" and align_select = "1111") else
align_select;
-------------------------------------------------------------------------------------------
--clock2
--
-------------------------------------------------------------------------------------------
input_reg2: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10bx8_align_array_s2 <= word10bx8_align_array_s1;
word10bx8_align_rdy_s2 <= word10bx8_align_rdy_s1;
end if;
end process;
--
alg_reg2: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
align_select_current <= align_select;
align_select_work_s1 <= align_select_work_s;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock3
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg3: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10bx8_align_array_r <= word10bx8_align_array_s2;
word10bx8_align_rdy_r <= word10bx8_align_rdy_s2;
align_select_work <= align_select_work_s1;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock4
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg4: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_rdy <= word10bx8_align_rdy_r;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case (align_select_work) is
when "0000" => -- bit0 word got comma => align to bit0
word10b_array <= word10bx8_align_array_r(0);
when "0001" => -- bit1 word got comma => align to bit1
word10b_array <= word10bx8_align_array_r(1);
when "0010" => -- bit2 word got comma => align to bit2
word10b_array <= word10bx8_align_array_r(2);
when "0011" => -- bit3 word got comma => align to bit3
word10b_array <= word10bx8_align_array_r(3);
when "0100" => -- bit4 word got comma => align to bit4
word10b_array <= word10bx8_align_array_r(4);
when "0101" => -- bit5 word got comma => align to bit5
word10b_array <= word10bx8_align_array_r(5);
when "0110" => -- bit6 word got comma => align to bit6
word10b_array <= word10bx8_align_array_r(6);
when "0111" => -- bit7 word got comma => align to bit7
word10b_array <= word10bx8_align_array_r(7);
when "1000" => -- bit8 word got comma => align to bit8
word10b_array <= word10bx8_align_array_r(8);
when "1001" => -- bit9 word got comma => align to bit9
word10b_array <= word10bx8_align_array_r(9);
when "1010" => -- bit10 word got comma => align to bit10
word10b_array <= word10bx8_align_array_r(10);
when "1011" => -- bit11 word got comma => align to bit11
word10b_array <= word10bx8_align_array_r(11);
when "1100" => -- bit12 word got comma => align to bit12
word10b_array <= word10bx8_align_array_r(12);
when "1101" => -- bit13 word got comma => align to bit13
word10b_array <= word10bx8_align_array_r(13);
when "1110" => -- bit14 word got comma => align to bit14
word10b_array <= word10bx8_align_array_r(14);
when "1111" => -- bit15 word got comma => align to bit15
word10b_array <= word10bx8_align_array_r(15);
when others =>
end case;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b K-characters codes: COMMA/SOC/EOC/DATA
-------------------------------------------------------------------------------------------
KcharTests: for I in 0 to 7 generate
KcharTestn: KcharTest
port map(
clk => bitCLK,
encoded10in => word10b_array(I),
KcharCode => isk_array(I)
);
end generate KcharTests;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_s <= word10b_array;
word10b_array_rdy_s <= word10b_array_rdy;
end if;
end process;
--
-- if more that 3 commas, will repeat itself next clock
realignment_ena <= '0' when (isk_array(0) = "11" and isk_array(1) = "11" and isk_array(2) = "11" and isk_array(3) = "11") else '1';
word10b_array_rdy_s1 <= word10b_array_rdy_s and realignment_ena;
-------------------------------------------------------------------------------------------
-- 8 words get aligned and ready as 10 bit word (data 8 bit and data code 2 bit)
-------------------------------------------------------------------------------------------
EPROC_IN16_ALIGN_BLOCK_inst: entity work.EPROC_IN16_ALIGN_BLOCK
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst,
bytes => word10b_array_s,
bytes_rdy => word10b_array_rdy_s1,
dataOUT => dataOUT,
dataOUTrdy => dataOUTrdy,
busyOut => busyOut
);
end Behavioral;
| gpl-3.0 | 1b75dd888b25e2988c48c24ff5627330 | 0.542962 | 3.626187 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/readout/event_timing_reset.vhd | 2 | 3,646 | ----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Paris Moschovakos
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library UNISIM;
library ieee;
use ieee.numeric_std.all;
use IEEE.numeric_bit.all;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use UNISIM.vcomponents.all;
entity event_timing_reset is
port(
hp_clk : in std_logic; -- High precision clock 1 GHz
bc_clk : in std_logic; -- 40MHz
trigger : in std_logic;
readout_done : in std_logic;
reset : in std_logic; -- reset
bcid : out std_logic_vector(12 downto 0); -- 13 bits 12 for counting to 0xFFF and the MSB as a signal to auto reset.
prec_cnt : out std_logic_vector(4 downto 0); -- 5 bits are more than enough (32) while 1-25 used
vmm_ena : out std_logic; -- these will be ored with same from other sm. This should evolve to a vector.
vmm_wen : out std_logic -- these will be ored with same from other sm. This should evolve to a vector.
);
end event_timing_reset;
architecture Behavioral of event_timing_reset is
-- Signals
signal bcid_i : std_logic_vector(12 downto 0) := b"0000000000000";
signal prec_cnt_i : std_logic_vector(4 downto 0) := b"00000";
signal state_nxt : std_logic_vector(2 downto 0);
signal vmm_wen_int, vmm_ena_int : std_logic;
signal acq_rst_int, acq_rst_d : std_logic;
-- Components if any
begin
-- Processes
process (bc_clk)
begin
if (bc_clk'event and bc_clk = '1') then
end if;
end process;
process (bc_clk)
-- this process is an edge detect for acq_rst
begin
if rising_edge (bc_clk) then
end if;
end process;
-- process(clk, state_nxt, rst, acq_rst_int, vmm_ena_int, vmm_wen_int)
-- begin
-- if (rising_edge( clk)) then --100MHz
-- if (rst = '1') then
-- state_nxt <= (others=>'0');
-- vmm_ena_int <= '0';
-- vmm_wen_int <= '0';
-- else
-- case state_nxt is
-- when "000" =>
-- vmm_wen_int <= '0';
-- vmm_ena_int <= '0';
-- if (acq_rst_int = '1') then
-- state_nxt <= "001";
-- else
-- state_nxt <= "000" ;
-- end if ;
-- when "001" =>
-- vmm_ena_int <= '0';
-- vmm_wen_int <= '1';
-- state_nxt <= "010";
-- state_nxt <= "001";
-- when "010" =>
-- vmm_ena_int <= '0';
-- vmm_wen_int <= '0';
-- state_nxt <= "000";
-- when others =>
-- vmm_ena_int <= '0';
-- vmm_wen_int <= '0';
-- state_nxt <= (others=>'0');
-- end case;
-- end if;
-- end if;
-- end process;
-- Signal assignment
vmm_wen <= vmm_wen_int;
vmm_ena <= vmm_ena_int;
prec_cnt <= prec_cnt_i;
bcid <= bcid_i;
-- Instantiations if any
end Behavioral; | gpl-3.0 | a5b605121b648ff5808fc8382255d022 | 0.478881 | 3.287647 | false | false | false | false |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/synth/ZynqDesign_axi_gpio_0_0.vhd | 1 | 9,710 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY ZynqDesign_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ZynqDesign_axi_gpio_0_0;
ARCHITECTURE ZynqDesign_axi_gpio_0_0_arch OF ZynqDesign_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ZynqDesign_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ZynqDesign_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ZynqDesign_axi_gpio_0_0_arch : ARCHITECTURE IS "ZynqDesign_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ZynqDesign_axi_gpio_0_0_arch: ARCHITECTURE IS "ZynqDesign_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=8,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=1,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 1,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
gpio_io_o => gpio_io_o,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END ZynqDesign_axi_gpio_0_0_arch;
| mit | 37644c6aa0831550bb68114699cff053 | 0.688157 | 3.196182 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/imports/sgmii_10_100_1000/ipcore_dir/temac_10_100_1000/example_design/temac_10_100_1000_fifo_block.vhd | 1 | 20,064 | --------------------------------------------------------------------------------
-- File : temac_10_100_1000_fifo_block.v
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the FIFO Block level vhdl wrapper for the Tri-Mode
-- Ethernet MAC core. This wrapper enhances the standard MAC core
-- with an example FIFO. The interface to this FIFO is
-- designed to the AXI-S specification.
-- Please refer to core documentation for
-- additional FIFO and AXI-S information.
--
-- _________________________________________________________
-- | |
-- | FIFO BLOCK LEVEL WRAPPER |
-- | |
-- | _____________________ ______________________ |
-- | | _________________ | | | |
-- | | | | | | | |
-- -------->| | TX AXI FIFO | |---->| Tx Tx |--------->
-- | | | | | | AXI-S PHY | |
-- | | |_________________| | | I/F I/F | |
-- | | | | | |
-- AXI | | 10/100/1G | | TRI-MODE ETHERNET | |
-- Stream | | ETHERNET FIFO | | MAC CORE | | PHY I/F
-- | | | | BLOCK WRAPPER | |
-- | | _________________ | | | |
-- | | | | | | | |
-- <--------| | RX AXI FIFO | |<----| Rx Rx |<---------
-- | | | | | | AXI-S PHY | |
-- | | |_________________| | | I/F I/F | |
-- | |_____________________| |______________________| |
-- | |
-- |_________________________________________________________|
--
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- The module declaration for the fifo block level wrapper.
--------------------------------------------------------------------------------
entity temac_10_100_1000_fifo_block is
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_reset : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_axis_fifo_tlast : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_axis_fifo_tlast : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
clk_enable : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- Configuration Vector
-------------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0)
);
end temac_10_100_1000_fifo_block;
architecture wrapper of temac_10_100_1000_fifo_block is
------------------------------------------------------------------------------
-- Component declaration for the block level
------------------------------------------------------------------------------
component temac_10_100_1000_block
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- Transmitter Interface
-------------------------------
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic;
tx_axis_mac_tready : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
clk_enable : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
-- Configuration Vector
-----------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the fifo
------------------------------------------------------------------------------
component temac_10_100_1000_ten_100_1g_eth_fifo
generic (
FULL_DUPLEX_ONLY : boolean := true); -- If fifo is to be used only in full
-- duplex set to true for optimised implementation
port (
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
tx_fifo_overflow : out std_logic;
tx_fifo_status : out std_logic_vector(3 downto 0);
tx_collision : in std_logic;
tx_retransmit : in std_logic;
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tready : out std_logic;
rx_axis_mac_tuser : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
rx_fifo_overflow : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component temac_10_100_1000_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- Internal signals used in this fifo block level wrapper.
------------------------------------------------------------------------------
-- Note: KEEP attributes preserve signal names so they can be displayed in
-- simulator wave windows
signal rx_reset_int : std_logic; -- MAC Rx reset
signal tx_reset_int : std_logic; -- MAC Tx reset
signal tx_mac_resetn : std_logic;
signal rx_mac_resetn : std_logic;
signal tx_mac_reset : std_logic;
signal rx_mac_reset : std_logic;
-- MAC receiver client I/F
signal rx_axis_mac_tdata : std_logic_vector(7 downto 0);
signal rx_axis_mac_tvalid : std_logic;
signal rx_axis_mac_tlast : std_logic;
signal rx_axis_mac_tuser : std_logic;
-- MAC transmitter client I/F
signal tx_axis_mac_tdata : std_logic_vector(7 downto 0);
signal tx_axis_mac_tvalid : std_logic;
signal tx_axis_mac_tready : std_logic;
signal tx_axis_mac_tlast : std_logic;
signal tx_axis_mac_tuser : std_logic;
-- Note: KEEP attributes preserve signal names so they can be displayed in
-- simulator wave windows
attribute keep : string;
attribute keep of rx_axis_mac_tdata : signal is "true";
attribute keep of rx_axis_mac_tvalid : signal is "true";
attribute keep of rx_axis_mac_tlast : signal is "true";
attribute keep of rx_axis_mac_tuser : signal is "true";
attribute keep of tx_axis_mac_tdata : signal is "true";
attribute keep of tx_axis_mac_tvalid : signal is "true";
attribute keep of tx_axis_mac_tready : signal is "true";
attribute keep of tx_axis_mac_tlast : signal is "true";
attribute keep of tx_axis_mac_tuser : signal is "true";
begin
------------------------------------------------------------------------------
-- Connect the output clock signals
------------------------------------------------------------------------------
rx_reset <= rx_reset_int;
tx_reset <= tx_reset_int;
------------------------------------------------------------------------------
-- Instantiate the Tri-Mode EMAC Block wrapper
------------------------------------------------------------------------------
trimac_block : temac_10_100_1000_block
port map(
gtx_clk => gtx_clk,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
-- Client Receiver Interface
rx_statistics_vector => rx_statistics_vector,
rx_statistics_valid => rx_statistics_valid,
rx_reset => rx_reset_int,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
-- Client Transmitter Interface
tx_ifg_delay => tx_ifg_delay,
tx_statistics_vector => tx_statistics_vector,
tx_statistics_valid => tx_statistics_valid,
tx_reset => tx_reset_int,
tx_axis_mac_tdata => tx_axis_mac_tdata ,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser,
tx_axis_mac_tready => tx_axis_mac_tready,
-- Flow Control
pause_req => pause_req,
pause_val => pause_val,
clk_enable => clk_enable,
speedis100 => speedis100,
speedis10100 => speedis10100,
-- GMII Interface
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
-- Configuration Vector
rx_configuration_vector => rx_configuration_vector,
tx_configuration_vector => tx_configuration_vector
);
------------------------------------------------------------------------------
-- Instantiate the user side FIFO
------------------------------------------------------------------------------
-- locally reset sync the mac generated resets - the resets are already fully sync
-- so adding a reset sync shouldn't change that
rx_mac_reset_gen : temac_10_100_1000_reset_sync
port map (
clk => gtx_clk,
enable => '1',
reset_in => rx_reset_int,
reset_out => rx_mac_reset
);
tx_mac_reset_gen : temac_10_100_1000_reset_sync
port map (
clk => gtx_clk,
enable => '1',
reset_in => tx_reset_int,
reset_out => tx_mac_reset
);
-- create inverted mac resets as the FIFO expects AXI compliant resets
tx_mac_resetn <= not tx_mac_reset;
rx_mac_resetn <= not rx_mac_reset;
user_side_FIFO : temac_10_100_1000_ten_100_1g_eth_fifo
generic map(
FULL_DUPLEX_ONLY => true
)
port map(
-- Transmit FIFO MAC TX Interface
tx_fifo_aclk => tx_fifo_clock,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_mac_aclk => gtx_clk,
tx_mac_resetn => tx_mac_resetn,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_axis_mac_tuser => tx_axis_mac_tuser,
tx_fifo_overflow => open,
tx_fifo_status => open,
tx_collision => '0',
tx_retransmit => '0',
rx_fifo_aclk => rx_fifo_clock,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_mac_aclk => gtx_clk,
rx_mac_resetn => rx_mac_resetn,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tready => open, -- not used as MAC cannot throttle
rx_axis_mac_tuser => rx_axis_mac_tuser,
rx_fifo_status => open,
rx_fifo_overflow => open
);
end wrapper;
| gpl-3.0 | 490c4f71ae81fc4463fece36a90d7075 | 0.461423 | 4.234698 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_OUT2_HDLC.vhd | 3 | 8,523 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 24/01/2016
--! Module Name: EPROC_OUT2_HDLC
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE,work;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
use work.all;
--! HDLC data mode EPROC_OUT2 module
entity EPROC_OUT2_HDLC is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(1 downto 0)
);
end EPROC_OUT2_HDLC;
architecture Behavioral of EPROC_OUT2_HDLC is
----------------------------------
----------------------------------
component hdlc_bist_fifo
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(8 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(8 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
----------------------------------
----------------------------------
signal bit_cnt,bit_cnt_r : std_logic_vector (2 downto 0) := (others=>'1');
signal two_bit_out,EdataOUT_s : std_logic_vector (1 downto 0) := (others=>'1');
signal bit_cnt_ena,ce,ce_r,we,re_r,oe : std_logic := '0';
signal fifo_empty_r,isflag_r : std_logic := '1';
signal bitOUTclk,rst_fall,restart,bit_stuffing_case,re,ce_1st_clk,fifo_empty,bit_out,bit_out_r,isflag : std_logic;
signal byte_out : std_logic_vector (8 downto 0);
signal dataByte : std_logic_vector (8 downto 0) := (others=>'1');
signal byte_out_r : std_logic_vector (7 downto 0) := (others=>'1');
signal bit_out_sr : std_logic_vector (4 downto 0) := (others=>'1');
signal bit_out_sr_clk0 : std_logic_vector (4 downto 0);
signal send_out_trig : std_logic := '0';
begin
bitOUTclk <= bitCLKx2; -- 2bit output
-------------------------------------------------------------------------------------------
-- restarting data requests after reset fall
-------------------------------------------------------------------------------------------
rst_fall_pulse: entity work.pulse_fall_pw01 port map(bitOUTclk,rst,rst_fall);
restart_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>10,pw=>1) port map(bitOUTclk,rst_fall,restart);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if restart = '1' then
ce <= '1';
end if;
ce_r <= ce;
end if;
end process;
--
ce_1st_clk_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitOUTclk,ce,ce_1st_clk);
--
-------------------------------------------------------------------------------------------
-- input latching @ bitCLKx4
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if edataINrdy = '1' then
if edataIN(9 downto 8) = "11" then -- comma ('error')
dataByte <= (others=>'1');
we <= '0';
elsif edataIN(9 downto 8) = "01" or edataIN(9 downto 8) = "10" then -- eop/sop
dataByte <= '1' & HDLC_flag;
we <= '1';
else
dataByte <= '0' & edataIN(7 downto 0);
we <= '1';
end if;
else
we <= '0';
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- HDLC bit stuffing FIFO
-------------------------------------------------------------------------------------------
bit_stuffing_FIFO: hdlc_bist_fifo
port map (
rst => rst,
wr_clk => bitCLKx4,
rd_clk => bitOUTclk,
din => dataByte,
wr_en => we,
rd_en => re,
dout => byte_out,
full => open,
empty => fifo_empty
);
-------------------------------------------------------------------------------------------
-- bit counter: counting 8 bit to serialize the out while pausing for zero-bit stuffing
-------------------------------------------------------------------------------------------
bit_stuffing_case <= '1' when (bit_out_sr_clk0 = "11111" and isflag_r = '0') else '0';
bit_cnt_ena <= ce and (not bit_stuffing_case);
re <= '1' when (bit_cnt = "111" and bit_cnt_ena = '1') else '0';
getDataTrig_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitCLKx4,re,getDataTrig);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if ce = '1' then
if bit_cnt_ena = '1' then
bit_cnt <= bit_cnt + 1;
end if;
else
bit_cnt <= (others=>'1');
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- comma selector
-------------------------------------------------------------------------------------------
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
re_r <= re;
fifo_empty_r <= fifo_empty;
end if;
end process;
--
isflag <= byte_out(8); --'1' when (byte_out = HDLC_flag) else '0';
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if re_r = '1' then
if fifo_empty_r = '1' then
byte_out_r <= (others=>'1'); --error flag, not HDLC_flag!
isflag_r <= '1';
else
byte_out_r <= byte_out(7 downto 0);
isflag_r <= isflag; -- no bit stuffing if flag is sent
end if;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- bit selector
-------------------------------------------------------------------------------------------
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
bit_cnt_r <= bit_cnt;
end if;
end process;
--
process(bit_cnt_r,byte_out_r)
begin
case (bit_cnt_r) is
when "000" => bit_out <= byte_out_r(0);
when "001" => bit_out <= byte_out_r(1);
when "010" => bit_out <= byte_out_r(2);
when "011" => bit_out <= byte_out_r(3);
when "100" => bit_out <= byte_out_r(4);
when "101" => bit_out <= byte_out_r(5);
when "110" => bit_out <= byte_out_r(6);
when "111" => bit_out <= byte_out_r(7);
when others =>
end case;
end process;
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
oe <= bit_cnt_ena;
end if;
end process;
--
bit_out_r <= (bit_out and oe) or (not ce_r);
bit_out_sr_clk0 <= bit_out_r & bit_out_sr(4 downto 1);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if rst = '1' then
bit_out_sr <= (others=>'1');
else
bit_out_sr <= bit_out_r & bit_out_sr(4 downto 1);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- sending out 2 bits @ bitCLK
-------------------------------------------------------------------------------------------
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
send_out_trig <= (not send_out_trig) and ce;
end if;
end process;
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if send_out_trig = '1' then
two_bit_out(1) <= bit_out_r;
else
two_bit_out(0) <= bit_out_r;
end if;
end if;
end process;
--
process(bitOUTclk,rst)
begin
if rst = '1' then
EdataOUT_s <= (others=>'1');
elsif bitOUTclk'event and bitOUTclk = '1' then
if send_out_trig = '0' and ce = '1' then
EdataOUT_s <= two_bit_out;
end if;
end if;
end process;
--
EdataOUT <= EdataOUT_s;
--
end Behavioral;
| gpl-3.0 | 87fd167d1d6934447a25f8487709e0f0 | 0.442333 | 3.702433 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/FIR_Filter/lp_fir_tap.vhd | 1 | 4,153 | --------------------------------------------------------------------------------------------------
-- FIR Tap
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package lp_fir_tap_pkg is
--Linear Phase FIR tap component declaration
component lp_fir_tap is
port( clk : in std_logic;
rst : in std_logic;
coef : in coefficient;
sig_in : in sig;
sig_out : out sig;
return_sig_in : in sig;
sum_in : in fir_sig;
sum_out : out fir_sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
--This entity represents a single tap in a even-symmetry linear phase FIR filter. The taps are
--designed to implement a cascade adder allowing for chaining an indefinite (tho definitely
--finite) number of taps.
entity lp_fir_tap is
port( clk : in std_logic;
rst : in std_logic;
coef : in coefficient;
sig_in : in sig;
sig_out : out sig;
return_sig_in : in sig;
sum_in : in fir_sig;
sum_out : out fir_sig);
end lp_fir_tap;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE (behavioral)
--------------------------------------------------------------------------------------------------
architecture behave of lp_fir_tap is
signal sig_delay : sig_array(1 to 2) := (others => (others => '0'));
signal return_sig_delay : sig := (others => '0');
signal pre_add_sum : summed_sig := (others => '0');
signal product : fir_sig := (others => '0');
begin
--delay the input signals
delay_sig : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
sig_delay <= (others => (others => '0'));
return_sig_delay <= (others => '0');
else
sig_delay(1) <= sig_in;
sig_delay(2) <= sig_delay(1);
return_sig_delay <= return_sig_in;
end if;
end if;
end process;
sig_out <= sig_delay(2);
--pre add the signal and returning signal; register the result
pre_add : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
pre_add_sum <= (others => '0');
else
pre_add_sum <= resize(sig_delay(2), NUM_SUMMED_SIG_BITS)
+ resize(return_sig_delay, NUM_SUMMED_SIG_BITS);
end if;
end if;
end process;
--multiply the pre-add sum to the tap coefficient
multiply : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
product <= (others => '0');
else
product <= resize(pre_add_sum * coef, NUM_FIR_BITS);
end if;
end if;
end process;
--update the running sum
update_sum : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
sum_out <= (others => '0');
else
sum_out <= sum_in + product;
end if;
end if;
end process;
end behave;
| mit | 4a8111f49e5d85e4b5d94a62abf8c57a | 0.390079 | 4.661055 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_OUT2.vhd | 2 | 5,358 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT2
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee,work;
use ieee.std_logic_1164.all;
use work.all;
--! E-link processor, 2bit output
entity EPROC_OUT2 is
generic (
do_generate : boolean := true
);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
swap_outbits : in std_logic;
getDataTrig : out std_logic; -- @ bitCLKx4
ENCODING : in std_logic_vector (3 downto 0);
EDATA_OUT : out std_logic_vector (1 downto 0);
TTCin : in std_logic_vector (1 downto 0);
DATA_IN : in std_logic_vector (9 downto 0);
DATA_RDY : in std_logic
);
end EPROC_OUT2;
architecture Behavioral of EPROC_OUT2 is
constant zeros2bit : std_logic_vector (1 downto 0) := (others=>'0');
signal EdataOUT_ENC8b10b_case, EdataOUT_direct_case, EdataOUT_HDLC_case, EdataOUT_TTC0_case : std_logic_vector (1 downto 0);
signal rst_s, rst_case000, rst_case001, rst_case010, rst_case011 : std_logic;
signal getDataTrig_ENC8b10b_case, getDataTrig_direct_case, getDataTrig_HDLC_case, getDataTrig_TTC_case : std_logic;
signal edata_out_s : std_logic_vector (1 downto 0);
begin
gen_enabled: if do_generate = true generate
rst_s <= rst or (not ENA);
-------------------------------------------------------------------------------------------
-- case 0: direct data, no delimeter...
-------------------------------------------------------------------------------------------
rst_case000 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "000")) else '1';
--
direct_case: entity work.EPROC_OUT2_direct
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case000,
getDataTrig => getDataTrig_direct_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_direct_case
);
--
-------------------------------------------------------------------------------------------
-- case 1: DEC8b10b
-------------------------------------------------------------------------------------------
rst_case001 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "001")) else '1';
--
ENC8b10b_case: entity work.EPROC_OUT2_ENC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case001,
getDataTrig => getDataTrig_ENC8b10b_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_ENC8b10b_case
);
--
-------------------------------------------------------------------------------------------
-- case 2: HDLC
-------------------------------------------------------------------------------------------
rst_case010 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "010")) else '1';
--
HDLC_case: entity work.EPROC_OUT2_HDLC
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case010,
getDataTrig => getDataTrig_HDLC_case, -- output, data request
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_HDLC_case
);
--
-------------------------------------------------------------------------------------------
-- case 3: TTC-0
-------------------------------------------------------------------------------------------
rst_case011 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "011")) else '1';
--
getDataTrig_TTC_case <= '0'; --'1' when (ENCODING(2 downto 0) = "011") else '0';
--
ttc_r: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst_case011 = '1' then
EdataOUT_TTC0_case <= zeros2bit;
else
EdataOUT_TTC0_case <= TTCin;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- output data and busy according to the encoding settings
-------------------------------------------------------------------------------------------
dataOUTmux: entity work.MUX4_Nbit
generic map (N=>2)
port map(
data0 => EdataOUT_direct_case,
data1 => EdataOUT_ENC8b10b_case,
data2 => EdataOUT_HDLC_case,
data3 => EdataOUT_TTC0_case,
sel => ENCODING(1 downto 0),
data_out => edata_out_s
);
--
getDataTrig <= ENA and (getDataTrig_TTC_case or getDataTrig_HDLC_case or getDataTrig_ENC8b10b_case or getDataTrig_direct_case);
--
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
edata_out_s <= (others=>'0');
getDataTrig <= '0';
end generate gen_disabled;
--
out_sel: process(swap_outbits,edata_out_s)
begin
if swap_outbits = '1' then
EDATA_OUT <= edata_out_s(0) & edata_out_s(1);
else
EDATA_OUT <= edata_out_s;
end if;
end process;
--
end Behavioral;
| gpl-3.0 | 56286a99e0c054ea56f2aa1aef29caa2 | 0.465099 | 3.832618 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_OUT2_direct.vhd | 4 | 3,959 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_OUT2_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data mode EPROC_OUT2 module
entity EPROC_OUT2_direct is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(1 downto 0)
);
end EPROC_OUT2_direct;
architecture Behavioral of EPROC_OUT2_direct is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
component MUX4_Nbit
generic (N : integer := 16);
Port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
data2 : in std_logic_vector((N-1) downto 0);
data3 : in std_logic_vector((N-1) downto 0);
sel : in std_logic_vector(1 downto 0);
data_out : out std_logic_vector((N-1) downto 0)
);
end component;
----------------------------------
----------------------------------
constant zeros2bit : std_logic_vector (1 downto 0) := (others=>'0');
signal byte_r : std_logic_vector (7 downto 0);
signal request_cycle_cnt, send_count : std_logic_vector (1 downto 0) := (others=>'0');
signal send_out_trig : std_logic := '0';
signal inp_request_trig, inp_request_trig_out : std_logic;
begin
-------------------------------------------------------------------------------------------
-- input handshaking, request cycle 4 CLKs
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
request_cycle_cnt <= (others=>'0');
else
if inp_request_trig = '1' then
request_cycle_cnt <= (others=>'0');
else
request_cycle_cnt <= request_cycle_cnt + 1;
end if;
end if;
end if;
end process;
--
inp_request_trig <= '1' when (request_cycle_cnt = "11") else '0';
--
inp_reques1clk: pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitCLKx4, inp_request_trig, inp_request_trig_out);
getDataTrig <= inp_request_trig_out;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
send_out_trig <= inp_request_trig;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- sending out 2 bits @ bitCLK
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if send_out_trig = '1' then
byte_r <= edataIN(7 downto 0);
end if;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if send_out_trig = '1' then
send_count <= (others=>'0');
else
send_count <= send_count + 1;
end if;
end if;
end process;
--
outmux: MUX4_Nbit
generic map (N=>2)
port map (
data0 => byte_r(1 downto 0),
data1 => byte_r(3 downto 2),
data2 => byte_r(5 downto 4),
data3 => byte_r(7 downto 6),
sel => send_count,
data_out => EdataOUT
);
--
end Behavioral;
| gpl-3.0 | abf5257cb588f70893ac81a43d4eda2c | 0.479667 | 3.53798 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/reg8to16bit.vhd | 4 | 3,301 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 08/12/2014
--! Module Name: reg8to16bit
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library work, IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
--! width matching register 8 bit to 16 bit
entity reg8to16bit is
Port (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
flush : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
din_rdy : IN STD_LOGIC;
-----
flushed : OUT STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dout_rdy : OUT STD_LOGIC
);
end reg8to16bit;
architecture Behavioral of reg8to16bit is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
----
signal dout16bit_s1, dout16bit_s2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal count, ce, count_1CLK_pulse_valid, flush_s, count_rst, flashed_delayed, count_trig : STD_LOGIC := '0';
signal count_1CLK_pulse_s : STD_LOGIC;
----
begin
-----
--
process(clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
ce <= '1';
end if;
end if;
end process;
---
-----
flush_s <= flush and (not count); -- when count is '0', flush the register
--
process(clk)
begin
if clk'event and clk = '1' then
flushed <= flush_s;
end if;
end process;
---
process(flush_s, clk)
begin
if flush_s = '1' then
flashed_delayed <= '1';
elsif clk'event and clk = '1' then
flashed_delayed <= flush_s;
end if;
end process;
---
--
process(clk)
begin
if clk'event and clk = '1' then
if din_rdy = '1' then
dout16bit_s1 <= din;
dout16bit_s2 <= dout16bit_s1;
end if;
end if;
end process;
---
process(flashed_delayed, dout16bit_s1, dout16bit_s2)
begin
if flashed_delayed = '1' then
dout <= "00000000" & dout16bit_s1;
else
dout <= dout16bit_s1 & dout16bit_s2;
end if;
end process;
---
---
count_rst <= rst; -- or flush_s;
---
process(count_rst, clk)
begin
if count_rst = '1' then
count <= '1';
elsif clk'event and clk = '1' then
if flush_s = '1' then
count <= '1';
elsif din_rdy = '1' then
count <= not count;
end if;
end if;
end process;
---
count_trig <= count;-- and (not flashed_delayed) and (not rst) and ce;
count_1CLK_pulse: pulse_pdxx_pwxx PORT MAP(clk, count_trig, count_1CLK_pulse_s);
--count_1CLK_pulse_valid <= count_1CLK_pulse_s and (not flashed_delayed) and (not rst) and ce;
count_1CLK_pulse_valid <= count_1CLK_pulse_s and (not rst) and ce; --and (not flashed_delayed)
---
dout_rdy <= count_1CLK_pulse_valid; -- or flush_s;
---
end Behavioral;
| gpl-3.0 | aa4ffc5803e9822af368531a49a1dc13 | 0.513178 | 3.207969 | false | false | false | false |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/select.vhd | 1 | 3,960 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
entity selectresult is
port(
mem_result : in std_logic_vector(7 downto 0);
alu_result : in std_logic_vector(7 downto 0);
select_op : in std_logic_vector(1 downto 0);
result_out : out std_logic_vector(7 downto 0));
end selectresult;
architecture mixed of selectresult is
begin
process(select_op, mem_result, alu_result)
begin
case select_op is
when "10" =>
result_out <= mem_result;
when others =>
result_out <= alu_result;
end case;
end process;
end mixed;
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
entity datamux is
port(
alu_memdata:in std_logic_vector(7 downto 0);
intrhandler_data:in std_logic_vector(7 downto 0);
sel: in std_logic;
data_out: out std_logic_vector(7 downto 0));
end datamux;
architecture mixed of datamux is
begin
process(alu_memdata, sel, intrhandler_data)
begin
case sel is
when '1' =>
data_out <= intrhandler_data;
when others =>
data_out <= alu_memdata;
end case;
end process;
end mixed;
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
entity writemux is
port(
dec_wr:in std_logic_vector(3 downto 0);
intr_wr:in std_logic_vector(3 downto 0);
sel: in std_logic;
wr_out: out std_logic_vector(3 downto 0));
end writemux;
architecture mixed of writemux is
begin
process(dec_wr, intr_wr, sel)
begin
case sel is
when '1' =>
wr_out <= intr_wr;
when others =>
wr_out <= dec_wr;
end case;
end process;
end mixed;
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
entity readmux is
port(
dec_raddr1:in std_logic_vector(3 downto 0);
dec_raddr2:in std_logic_vector(3 downto 0);
intr_raddr1:in std_logic_vector(3 downto 0);
intr_raddr2:in std_logic_vector(3 downto 0);
sel: in std_logic;
out_raddr1: out std_logic_vector(3 downto 0);
out_raddr2: out std_logic_vector(3 downto 0));
end readmux;
architecture mixed of readmux is
begin
process(dec_raddr1, dec_raddr2, intr_raddr1, intr_raddr2, sel)
begin
case sel is
when '1' =>
out_raddr1 <= intr_raddr1;
out_raddr2 <= intr_raddr2;
when others =>
out_raddr1 <= dec_raddr1;
out_raddr2 <= dec_raddr2;
end case;
end process;
end mixed;
-------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity enable_mux is
port (
processor_en, sel : in std_logic;
en_out : out std_logic
);
end entity;
architecture behav of enable_mux is
begin
process(processor_en, sel)
begin
case sel is
when '1' =>
en_out <= '1';
when others =>
en_out <= processor_en;
end case;
end process;
end architecture;
| unlicense | 6b9fc3505e2d121086ab46dbe8272056 | 0.532323 | 3.826087 | false | false | false | false |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/pipe_top.vhd | 1 | 18,286 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity pipe_top is
port(
clk, rst : in std_logic;
interrupt_reg_data : in std_logic_vector(7 downto 0);
interrupt_reg_we : std_logic
);
end pipe_top;
architecture top of pipe_top is
component fetch_mem is
port(
clk, rst : in std_logic;
read_addr : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(15 downto 0));
end component;
component fetch2decode_reg is
port(
clk, rst : in std_logic;
noop : in std_logic;
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0));
end component;
component decode is
port(
din: in std_logic_vector(15 downto 0);
reg_rd_en : out std_logic;
Raddr1:out std_logic_vector(3 downto 0);
Raddr2:out std_logic_vector(3 downto 0);
memaddr: out std_logic_vector(7 downto 0);
operation:out std_logic_vector(4 downto 0);
dest_reg_en: out std_logic;
dest_reg: out std_logic_vector(3 downto 0);
src_reg1_en: out std_logic;
src_reg1: out std_logic_vector(3 downto 0);
src_reg2_en: out std_logic;
src_reg2: out std_logic_vector(3 downto 0);
return_from_interrupt : out std_logic
);
end component;
component decode2alu_reg is
port(
clk, rst: in std_logic;
noop : in std_logic;
A_in : in std_logic_vector(7 downto 0);
B_in : in std_logic_vector(7 downto 0);
operation_in : in std_logic_vector(4 downto 0);
Raddr1_in : in std_logic_vector(3 downto 0);
Raddr2_in : in std_logic_vector(3 downto 0);
Memaddr_in : in std_logic_vector(7 downto 0);
src_select: in std_logic_vector(1 downto 0);
ALU_result: in std_logic_vector(7 downto 0);
A_out : out std_logic_vector(7 downto 0);
B_out : out std_logic_vector(7 downto 0);
operation_out : out std_logic_vector(4 downto 0);
Raddr1_out : out std_logic_vector(3 downto 0);
Raddr2_out : out std_logic_vector(3 downto 0);
Memaddr_out : out std_logic_vector(7 downto 0));
end component;
component ALU is
port (
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
operation : in std_logic_vector(4 downto 0);
Raddr1 : in std_logic_vector(3 downto 0);
Raddr2 : in std_logic_vector(3 downto 0);
Memaddr_in : in std_logic_vector(7 downto 0);
MemAddr_out : out std_logic_vector(7 downto 0);
Raddr : out std_logic_vector(3 downto 0);
op : out std_logic_vector(1 downto 0);
result : out std_logic_vector(7 downto 0);
branch : out std_logic;
branch_offset : out std_logic_vector(7 downto 0);
mem_rd_en : out std_logic;
reg_wr_en : out std_logic;
mem_wr_en : out std_logic);
end component;
component ram is
port(
data : in std_logic_vector(7 downto 0);
write_addr : in std_logic_vector(7 downto 0);
read_addr : in std_logic_vector(7 downto 0);
w_enable : in std_logic;
r_enable : in std_logic;
clk, rst : in std_logic;
data_out : out std_logic_vector(7 downto 0));
end component;
component alu2register_reg is
port(
clk, rst : in std_logic;
raddr_in : in std_logic_vector(3 downto 0);
op_in : in std_logic_vector(1 downto 0);
result_in : in std_logic_vector(7 downto 0);
reg_wr_en_in : in std_logic;
raddr_out : out std_logic_vector(3 downto 0);
op_out : out std_logic_vector(1 downto 0);
result_out : out std_logic_vector(7 downto 0);
reg_wr_en_out : out std_logic
);
end component;
component register_bank is
port(
clk,rst : in std_logic;
data : in std_logic_vector(7 downto 0);
write_addr : in std_logic_vector(3 downto 0);
read_addr1 : in std_logic_vector(3 downto 0);
read_addr2 : in std_logic_vector(3 downto 0);
w_enable : in std_logic;
r_enable : in std_logic;
data_out1 : out std_logic_vector(7 downto 0);
data_out2 : out std_logic_vector(7 downto 0));
end component;
component hazard_control_block is
port (
dest_reg_en : in std_logic;
dest_reg : in std_logic_vector(3 downto 0);
src_reg1_en : std_logic;
src_reg1 : in std_logic_vector(3 downto 0);
src_reg2_en : in std_logic;
src_reg2 : in std_logic_vector(3 downto 0);
handlerPC : in std_logic_vector(7 downto 0);
nop : inout std_logic;
interrupt_happened : in std_logic;
interrupt_handled : in std_logic;
src_select : out std_logic_vector(1 downto 0);
PC : inout std_logic_vector(7 downto 0);
branch : in std_logic;
branch_addr : in std_logic_vector(7 downto 0);
operation : in std_logic_vector(4 downto 0);
clk, rst : in std_logic;
PC2handler : out std_logic_vector(7 downto 0)
);
end component;
component selectresult is
port(
mem_result : in std_logic_vector(7 downto 0);
alu_result : in std_logic_vector(7 downto 0);
select_op : in std_logic_vector(1 downto 0);
result_out : out std_logic_vector(7 downto 0));
end component;
component interrupt_handler is
port (
data_in1, data_in2 : in std_logic_vector(7 downto 0);
raddr1, raddr2 : inout std_logic_vector(3 downto 0);
raddr_write : out std_logic_vector(3 downto 0);
reg_re, reg_we : out std_logic;
data_out : out std_logic_vector(7 downto 0);
PC_in : in std_logic_vector(7 downto 0);
PC_out : out std_logic_vector(7 downto 0);
interrupt_reg_data : in std_logic_vector(7 downto 0);
interrupt_reg_we : in std_logic;
interrupt_or_return_happened, interrupt_or_return_handled : out std_logic;
return_opcode : in std_logic;
clk, rst : in std_logic
);
end component;
component datamux is
port(
alu_memdata:in std_logic_vector(7 downto 0);
intrhandler_data:in std_logic_vector(7 downto 0);
sel: in std_logic;
data_out: out std_logic_vector(7 downto 0));
end component;
component writemux is
port(
dec_wr:in std_logic_vector(3 downto 0);
intr_wr:in std_logic_vector(3 downto 0);
sel: in std_logic;
wr_out: out std_logic_vector(3 downto 0));
end component;
component readmux is
port(
dec_raddr1:in std_logic_vector(3 downto 0);
dec_raddr2:in std_logic_vector(3 downto 0);
intr_raddr1:in std_logic_vector(3 downto 0);
intr_raddr2:in std_logic_vector(3 downto 0);
sel: in std_logic;
out_raddr1: out std_logic_vector(3 downto 0);
out_raddr2: out std_logic_vector(3 downto 0));
end component;
component enable_mux is
port (
processor_en, sel : in std_logic;
en_out : out std_logic
);
end component;
signal fetch2decodereg_instr : std_logic_vector(15 downto 0);
signal decodereg2decode_instr : std_logic_vector(15 downto 0);
signal decode2regbank_re : std_logic;
signal decode2regbank_raddr1 : std_logic_vector(3 downto 0);
signal decode2regbank_raddr2 : std_logic_vector(3 downto 0);
signal decode2alureg_memaddr : std_logic_vector(7 downto 0);
signal decode2alureg_operation : std_logic_vector(4 downto 0);
signal decode2control_destregen : std_logic;
signal decode2control_destreg : std_logic_vector(3 downto 0);
signal decode2control_srcreg1en : std_logic;
signal decode2control_srcreg1 : std_logic_vector(3 downto 0);
signal decode2control_srcreg2en: std_logic;
signal decode2control_srcreg2: std_logic_vector(3 downto 0);
signal regbank2alureg_ain : std_logic_vector(7 downto 0);
signal regbank2alureg_bin : std_logic_vector(7 downto 0);
signal alureg2alu_aout : std_logic_vector(7 downto 0);
signal alureg2alu_bout : std_logic_vector(7 downto 0);
signal alureg2alu_operationout : std_logic_vector(4 downto 0);
signal alureg2alu_raddr1out : std_logic_vector(3 downto 0);
signal alureg2alu_raddr2out : std_logic_vector(3 downto 0);
signal alureg2alu_memaddrout : std_logic_vector(7 downto 0);
signal alu2mem_memaddrout : std_logic_vector(7 downto 0);
signal alu2mem_memrden : std_logic;
signal alu2mem_memwren : std_logic;
signal alu2mem_result : std_logic_vector(7 downto 0);
signal alu2reg_result : std_logic_vector(7 downto 0);
signal alu2reg_op : std_logic_vector(1 downto 0);
signal alu2reg_regwren : std_logic;
signal alu2reg_raddr : std_logic_vector(3 downto 0);
signal alu2control_branch : std_logic;
signal alu2control_branchoffset : std_logic_vector(7 downto 0);
signal alu2control_operation : std_logic_vector(4 downto 0);
signal control2fetch_pc : std_logic_vector(7 downto 0);
signal control2decodealu_noop : std_logic;
--signal control2alu_noop : std_logic;
signal decode2alureg_raddr1 : std_logic_vector(3 downto 0);
signal decode2alureg_raddr2 : std_logic_vector(3 downto 0);
signal regreg2register_raddr : std_logic_vector(3 downto 0);
signal regreg2register_wre : std_logic;
signal regreg2register_op : std_logic_vector(1 downto 0);
signal regreg2select_aluresult : std_logic_vector(7 downto 0);
signal mem2select_result : std_logic_vector(7 downto 0);
signal select2regbank_data : std_logic_vector(7 downto 0);
signal control2decodealureg_srcselect : std_logic_vector(1 downto 0);
signal interhandler2readaddrmux_raddr1, interhandler2readaddrmux_raddr2 : std_logic_vector(3 downto 0);
signal intrhandler2readaddrmux_re, intrhandler2writeaddrmux_we : std_logic;
signal intrhandler2writedatamux_data : std_logic_vector(7 downto 0);
signal control2intrhandler_PC : std_logic_vector(7 downto 0);
signal intrhandler2control_PC : std_logic_vector(7 downto 0);
signal intrhandler2control_happened, intrhandler2control_handled : std_logic;
signal intrmux2regbank_data : std_logic_vector(7 downto 0);
signal intrmux2regbank_writeaddr : std_logic_vector(3 downto 0);
signal intrmux2regbank_raddr1, intrmux2regbank_raddr2 : std_logic_vector(3 downto 0);
signal intrmux2regbank_we, intrmux2regbank_re : std_logic;
signal intrhandler2readraddrmux_re : std_logic;
signal decode2intrhandler_return : std_logic;
signal intrhandler2regbank_writeaddr : std_logic_vector(3 downto 0);
signal fetch2intrhandler_return : std_logic;
begin
fetch2intrhandler_return <= (fetch2decodereg_instr(15) and fetch2decodereg_instr(14) and fetch2decodereg_instr(13) and fetch2decodereg_instr(12));
fetch : fetch_mem port map(
clk => clk,
rst => rst,
read_addr => control2fetch_pc,
data_out => fetch2decodereg_instr);
decodereg : fetch2decode_reg port map(
clk => clk,
rst => rst,
noop => control2decodealu_noop,
data_in => fetch2decodereg_instr,
data_out => decodereg2decode_instr);
decoder : decode port map(
din => decodereg2decode_instr,
reg_rd_en => decode2regbank_re,
Raddr1 => decode2regbank_raddr1,
Raddr2 => decode2regbank_raddr2,
memaddr => decode2alureg_memaddr,
operation => decode2alureg_operation,
dest_reg_en => decode2control_destregen,
dest_reg => decode2control_destreg,
src_reg1_en => decode2control_srcreg1en,
src_reg1 => decode2control_srcreg1,
src_reg2_en => decode2control_srcreg2en,
src_reg2 => decode2control_srcreg2,
return_from_interrupt => decode2intrhandler_return);
decode2alureg : decode2alu_reg port map(
clk => clk,
rst => rst,
noop => control2decodealu_noop,
A_in => regbank2alureg_ain,
B_in => regbank2alureg_bin,
operation_in => decode2alureg_operation,
Raddr1_in => decode2regbank_raddr1,
Raddr2_in => decode2regbank_raddr2,
Memaddr_in => decode2alureg_memaddr,
src_select => control2decodealureg_srcselect,
ALU_result => select2regbank_data,
A_out => alureg2alu_aout,
B_out => alureg2alu_bout,
operation_out => alureg2alu_operationout,
Raddr1_out => alureg2alu_raddr1out,
Raddr2_out => alureg2alu_raddr2out,
Memaddr_out => alureg2alu_memaddrout);
control : hazard_control_block port map(
dest_reg_en => decode2control_destregen,
dest_reg => decode2control_destreg,
src_reg1_en => decode2control_srcreg1en,
src_reg1 => decode2control_srcreg1,
src_reg2_en => decode2control_srcreg2en,
src_reg2 => decode2control_srcreg2,
handlerPC => intrhandler2control_PC,
nop => control2decodealu_noop,
interrupt_happened => intrhandler2control_happened,
interrupt_handled => intrhandler2control_handled,
src_select => control2decodealureg_srcselect,
PC => control2fetch_pc,
branch => alu2control_branch,
branch_addr => alu2control_branchoffset,
operation => alu2control_operation,
clk => clk,
PC2handler => control2intrhandler_PC,
rst => rst);
alupart : ALU port map(
A => alureg2alu_aout,
B => alureg2alu_bout,
operation => alureg2alu_operationout,
Raddr1 => alureg2alu_raddr1out,
Raddr2 => alureg2alu_raddr2out,
Memaddr_in => alureg2alu_memaddrout,
MemAddr_out => alu2mem_memaddrout,
Raddr => alu2reg_raddr,
op => alu2reg_op,
result => alu2reg_result,
branch => alu2control_branch,
branch_offset => alu2control_branchoffset,
mem_rd_en => alu2mem_memrden,
reg_wr_en => alu2reg_regwren,
mem_wr_en => alu2mem_memwren);
aluregister : alu2register_reg port map(
clk => clk,
rst => rst,
raddr_in => alu2reg_raddr,
op_in => alu2reg_op,
result_in => alu2reg_result,
reg_wr_en_in => alu2reg_regwren,
raddr_out => regreg2register_raddr,
op_out => regreg2register_op,
result_out => regreg2select_aluresult,
reg_wr_en_out => regreg2register_wre);
ram_init : ram port map(
data => alu2reg_result,
write_addr => alu2mem_memaddrout,
read_addr => alu2mem_memaddrout,
w_enable => alu2mem_memwren,
r_enable => alu2mem_memrden,
clk => clk,
rst => rst,
data_out => mem2select_result);
registerbank : register_bank port map(
clk => clk,
rst => rst,
data => intrmux2regbank_data,
write_addr => intrmux2regbank_writeaddr,
read_addr1 => intrmux2regbank_raddr1,
read_addr2 => intrmux2regbank_raddr2,
w_enable => intrmux2regbank_we,
r_enable => intrmux2regbank_re,
data_out1 => regbank2alureg_ain,
data_out2 => regbank2alureg_bin);
interrupt_handler1 : interrupt_handler
port map (
data_in1 => regbank2alureg_ain,
data_in2 => regbank2alureg_bin,
raddr1 => interhandler2readaddrmux_raddr1,
raddr2 => interhandler2readaddrmux_raddr2,
raddr_write => intrhandler2regbank_writeaddr,
reg_re => intrhandler2readraddrmux_re,
reg_we => intrhandler2writeaddrmux_we,
data_out => intrhandler2writedatamux_data,
PC_in => control2intrhandler_PC,
PC_out => intrhandler2control_PC,
interrupt_reg_data => interrupt_reg_data,
interrupt_reg_we => interrupt_reg_we,
interrupt_or_return_happened => intrhandler2control_happened,
interrupt_or_return_handled => intrhandler2control_handled,
return_opcode => fetch2intrhandler_return,
clk => clk,
rst => rst
);
resultselect : selectresult port map(
mem_result => mem2select_result,
alu_result => regreg2select_aluresult,
select_op => regreg2register_op,
result_out => select2regbank_data);
regbank_writedata_mux : datamux
port map (
alu_memdata => select2regbank_data,
intrhandler_data => intrhandler2writedatamux_data,
sel => intrhandler2writeaddrmux_we,
data_out => intrmux2regbank_data);
regbank_writeaddr_mux : writemux
port map (
dec_wr => alu2reg_raddr,
intr_wr => intrhandler2regbank_writeaddr,
sel => intrhandler2writeaddrmux_we,
wr_out => intrmux2regbank_writeaddr);
regbank_readaddr_mux : readmux
port map(
dec_raddr1 => decode2regbank_raddr1,
dec_raddr2 => decode2regbank_raddr2,
intr_raddr1 => interhandler2readaddrmux_raddr1,
intr_raddr2 => interhandler2readaddrmux_raddr2,
sel => intrhandler2readraddrmux_re,
out_raddr1 => intrmux2regbank_raddr1,
out_raddr2 => intrmux2regbank_raddr2);
read_en_mux : enable_mux
port map (
processor_en => decode2regbank_re,
sel => intrhandler2readraddrmux_re,
en_out => intrmux2regbank_re
);
write_en_mux : enable_mux
port map (
processor_en => alu2reg_regwren,
sel => intrhandler2writeaddrmux_we,
en_out => intrmux2regbank_we
);
end top;
| unlicense | 8a16ef0580937d0a343e08d0cb4514fa | 0.608389 | 3.660128 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/sgmii_10_100_1000/ipcore_dir/temac_10_100_1000/example_design/common/temac_10_100_1000_reset_sync.vhd | 2 | 5,019 | --------------------------------------------------------------------------------
-- Title : Reset synchroniser
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : temac_10_100_1000_reset_sync.vhd
-- Author : Xilinx Inc.
--------------------------------------------------------------------------------
-- Description: Both flip-flops have the same asynchronous reset signal.
-- Together the flops create a minimum of a 1 clock period
-- duration pulse which is used for synchronous reset.
--
-- The flops are placed, using RLOCs, into the same slice.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2001-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity temac_10_100_1000_reset_sync is
generic (INITIALISE : bit_vector(1 downto 0) := "11");
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end temac_10_100_1000_reset_sync;
--------------------------------------------------------------------------------
architecture rtl of temac_10_100_1000_reset_sync is
signal reset_sync_reg : std_logic;
signal reset_sync_reg2 : std_logic;
attribute ASYNC_REG : string;
attribute ASYNC_REG of reset_sync_reg : signal is "TRUE";
attribute ASYNC_REG of reset_sync_reg2 : signal is "TRUE";
attribute RLOC : string;
attribute RLOC of reset_sync_reg : signal is "X0Y0";
attribute RLOC of reset_sync_reg2 : signal is "X0Y0";
attribute SHREG_EXTRACT : string;
attribute SHREG_EXTRACT of reset_sync_reg : signal is "NO";
attribute SHREG_EXTRACT of reset_sync_reg2 : signal is "NO";
attribute INIT : string;
attribute INIT of reset_sync_reg : signal is "1";
attribute INIT of reset_sync_reg2 : signal is "1";
begin
reset_sync1 : FDPE
generic map (
INIT => INITIALISE(0)
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => '0',
Q => reset_sync_reg
);
reset_sync2 : FDPE
generic map (
INIT => INITIALISE(1)
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg,
Q => reset_sync_reg2
);
reset_out <= reset_sync_reg2;
end rtl;
| gpl-3.0 | 0cda189f359322a078cd9c41af27bdb4 | 0.596533 | 4.293413 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/sgmii_10_100_1000/ipcore_dir/temac_10_100_1000/example_design/common/temac_10_100_1000_sync_block.vhd | 2 | 4,747 | --------------------------------------------------------------------------------
-- Title : CDC Sync Block
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : temac_10_100_1000_sync_block.vhd
-- Author : Xilinx Inc.
--------------------------------------------------------------------------------
-- Description: Used on signals crossing from one clock domain to
-- another, this is a flip-flop pair, with both flops
-- placed together with RLOCs into the same slice. Thus
-- the routing delay between the two is minimum to safe-
-- guard against metastability issues.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity temac_10_100_1000_sync_block is
generic (
INITIALISE : bit_vector(1 downto 0) := "00"
);
port (
clk : in std_logic; -- clock to be sync'ed to
data_in : in std_logic; -- Data to be 'synced'
data_out : out std_logic -- synced data
);
end temac_10_100_1000_sync_block;
architecture structural of temac_10_100_1000_sync_block is
-- Internal Signals
signal data_sync1 : std_logic;
signal data_sync2 : std_logic;
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
attribute ASYNC_REG : string;
attribute ASYNC_REG of data_sync1 : signal is "TRUE";
attribute ASYNC_REG of data_sync2 : signal is "TRUE";
attribute RLOC : string;
attribute RLOC of data_sync1 : signal is "X0Y0";
attribute RLOC of data_sync2 : signal is "X0Y0";
attribute SHREG_EXTRACT : string;
attribute SHREG_EXTRACT of data_sync1 : signal is "NO";
attribute SHREG_EXTRACT of data_sync2 : signal is "NO";
begin
data_sync : FD
generic map (
INIT => INITIALISE(0)
)
port map (
C => clk,
D => data_in,
Q => data_sync1
);
data_sync_reg : FD
generic map (
INIT => INITIALISE(1)
)
port map (
C => clk,
D => data_sync1,
Q => data_sync2
);
data_out <= data_sync2;
end structural;
| gpl-3.0 | 7b0ee2d27689a6dbc741feb0987cd05f | 0.610491 | 4.327256 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/8b10_dec.vhd | 4 | 8,430 | -------------------------------------------------------------------------------
--
--! Title : 8b/10b Decoder
--! Design : 10-bit to 8-bit Decoder
-- Project : 8000 - 8b10b_encdec
--! Author : Ken Boyette
--! Company : Critia Computer, Inc.
--
-------------------------------------------------------------------------------
--
-- File : 8b10b_dec.vhd
-- Version : 1.0
-- Generated : 09.27.2006
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
-- This module provides 10-bit to 9-bit encoding.
-- It accepts 10-bit encoded parallel data input and generates 8-bit decoded
-- data output in accordance with the 8b/10b standard method. This method was
-- described in the 1983 IBM publication "A DC-Balanced, Partitioned-Block,
-- 8B/10B Transmission Code" by A.X. Widmer and P.A. Franaszek. The method
-- WAS granted a U.S. Patent #4,486,739 in 1984; now expired.
--
-- The parallel 10-bit Binary input represent 1024 possible values, called
-- characters - only 268 of which are valid.
--
-- The input is a 10-bit encoded character whose bits are identified as:
-- AI, BI, CI, DI, EI, II, FI, GI, HI, JI (Least Significant to Most)
--
-- In addition to 256 data output characters, there are 12 special control
-- or K, characters defined for command and synchronization use.
--
-- The eight data output bits are identified as:
-- HI, GI, FI, EI, DI, CI, BI, AI (Most Significant to Least)
--
-- The output, KO, is used to indicate the output value is one of the
-- control characters.
--
-- All inputs and outputs are synchronous with an externally supplied
-- byte rate clock BYTECLK.
-- The encoded output is valid one clock after the input.
-- There is a reset input, RESET, to reset the logic. The next rising
-- BYTECLK after RESET is deasserted latches valid input data.
--
-- Note: This VHDL structure closely follows the discrete logic defined
-- in the original article and the subsequent patent. The Figures
-- referenced are those in the patent.
-------------------------------------------------------------------------------
-- This program is licensed under the GPL
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--! 8b/10b Decoder by Critia Computer, Inc.
entity dec_8b10b is
port(
RESET : in std_logic ; -- Global asynchronous reset (AH) -- syncronous now (13 JUL 2015)
RBYTECLK : in std_logic ; -- Master synchronous receive byte clock
AI, BI, CI, DI, EI, II : in std_logic ;
FI, GI, HI, JI : in std_logic ; -- Encoded input (LS..MS)
KO : out std_logic ; -- Control (K) character indicator (AH)
HO, GO, FO, EO, DO, CO, BO, AO : out std_logic -- Decoded out (MS..LS)
);
end dec_8b10b;
architecture behavioral of dec_8b10b is
-- Signals to tie things together
signal ANEB, CNED, EEI, P13, P22, P31 : std_logic := '0'; -- Figure 10 Signals
signal IKA, IKB, IKC : std_logic := '0'; -- Figure 11 Signals
signal XA, XB, XC, XD, XE : std_logic := '0'; -- Figure 12 Signals
signal OR121, OR122, OR123, OR124, OR125, OR126, OR127 : std_logic := '0';
signal XF, XG, XH : std_logic := '0'; -- Figure 13 Signals
signal OR131, OR132, OR133, OR134, IOR134 : std_logic := '0';
begin
--
-- 6b Input Function (Reference: Figure 10)
--
-- One 1 and three 0's
P13 <= (ANEB and (not CI and not DI))
or (CNED and (not AI and not BI)) ;
-- Three 1's and one 0
P31 <= (ANEB and CI and DI)
or (CNED and AI and BI) ;
-- Two 1's and two 0's
P22 <= (AI and BI and (not CI and not DI))
or (CI and DI and (not AI and not BI))
or (ANEB and CNED) ;
-- Intermediate term for "AI is Not Equal to BI"
ANEB <= AI xor BI ;
-- Intermediate term for "CI is Not Equal to DI"
CNED <= CI xor DI ;
-- Intermediate term for "E is Equal to I"
EEI <= EI xnor II ;
--
-- K Decoder - Figure 11
--
-- Intermediate terms
IKA <= (CI and DI and EI and II)
or (not CI and not DI and not EI and not II) ;
IKB <= P13 and (not EI and II and GI and HI and JI) ;
IKC <= P31 and (EI and not II and not GI and not HI and not JI) ;
-- PROCESS: KFN; Determine K output
-- original:
-- KFN: process (RESET, RBYTECLK, IKA, IKB, IKC)
-- begin
-- if RESET = '1' then
-- KO <= '0';
-- elsif RBYTECLK'event and RBYTECLK = '0' then
-- KO <= IKA or IKB or IKC;
-- end if;
-- end process KFN;
KFN: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '0' then
if RESET = '1' then
KO <= '0';
else
KO <= IKA or IKB or IKC;
end if;
end if;
end process KFN;
--
-- 5b Decoder Figure 12
--
-- Logic to determine complimenting A,B,C,D,E,I inputs
OR121 <= (P22 and (not AI and not CI and EEI))
or (P13 and not EI) ;
OR122 <= (AI and BI and EI and II)
or (not CI and not DI and not EI and not II)
or (P31 and II) ;
OR123 <= (P31 and II)
or (P22 and BI and CI and EEI)
or (P13 and DI and EI and II) ;
OR124 <= (P22 and AI and CI and EEI)
or (P13 and not EI) ;
OR125 <= (P13 and not EI)
or (not CI and not DI and not EI and not II)
or (not AI and not BI and not EI and not II) ;
OR126 <= (P22 and not AI and not CI and EEI)
or (P13 and not II) ;
OR127 <= (P13 and DI and EI and II)
or (P22 and not BI and not CI and EEI) ;
XA <= OR127
or OR121
or OR122 ;
XB <= OR122
or OR123
or OR124 ;
XC <= OR121
or OR123
or OR125 ;
XD <= OR122
or OR124
or OR127 ;
XE <= OR125
or OR126
or OR127 ;
-- PROCESS: DEC5B; Generate and latch LS 5 decoded bits
-- original:
-- DEC5B: process (RESET, RBYTECLK, XA, XB, XC, XD, XE, AI, BI, CI, DI, EI)
-- begin
-- if RESET = '1' then
-- AO <= '0' ;
-- BO <= '0' ;
-- CO <= '0' ;
-- DO <= '0' ;
-- EO <= '0' ;
-- elsif RBYTECLK'event and RBYTECLK = '0' then
-- AO <= XA XOR AI ; -- Least significant bit 0
-- BO <= XB XOR BI ;
-- CO <= XC XOR CI ;
-- DO <= XD XOR DI ;
-- EO <= XE XOR EI ; -- Most significant bit 6
-- end if;
-- end process DEC5B;
DEC5B: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '0' then
if RESET = '1' then
AO <= '0' ;
BO <= '0' ;
CO <= '0' ;
DO <= '0' ;
EO <= '0' ;
else
AO <= XA XOR AI ; -- Least significant bit 0
BO <= XB XOR BI ;
CO <= XC XOR CI ;
DO <= XD XOR DI ;
EO <= XE XOR EI ; -- Most significant bit 6
end if;
end if;
end process DEC5B;
--
-- 3b Decoder - Figure 13
--
-- Logic for complimenting F,G,H outputs
OR131 <= (GI and HI and JI)
or (FI and HI and JI)
or (IOR134);
OR132 <= (FI and GI and JI)
or (not FI and not GI and not HI)
or (not FI and not GI and HI and JI);
OR133 <= (not FI and not HI and not JI)
or (IOR134)
or (not GI and not HI and not JI) ;
OR134 <= (not GI and not HI and not JI)
or (FI and HI and JI)
or (IOR134) ;
IOR134 <= (not (HI and JI))
and (not (not HI and not JI))
and (not CI and not DI and not EI and not II) ;
XF <= OR131
or OR132 ;
XG <= OR132
or OR133 ;
XH <= OR132
or OR134 ;
-- PROCESS: DEC3B; Generate and latch MS 3 decoded bits
-- original:
-- DEC3B: process (RESET, RBYTECLK, XF, XG, XH, FI, GI, HI)
-- begin
-- if RESET = '1' then
-- FO <= '0' ;
-- GO <= '0' ;
-- HO <= '0' ;
-- elsif RBYTECLK'event and RBYTECLK ='0' then
-- FO <= XF XOR FI ; -- Least significant bit 7
-- GO <= XG XOR GI ;
-- HO <= XH XOR HI ; -- Most significant bit 10
-- end if;
-- end process DEC3B ;
DEC3B: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK ='0' then
if RESET = '1' then
FO <= '0' ;
GO <= '0' ;
HO <= '0' ;
else
FO <= XF XOR FI ; -- Least significant bit 7
GO <= XG XOR GI ;
HO <= XH XOR HI ; -- Most significant bit 10
end if;
end if;
end process DEC3B ;
end behavioral;
| gpl-3.0 | 90ae0c24bb7b3096efc3985f6b5d2e7f | 0.538434 | 3.062114 | false | false | false | false |
atti92/heterogenhomework | project1/solution1/syn/vhdl/fir_hw.vhd | 1 | 29,424 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.2
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fir_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
input_V : IN STD_LOGIC_VECTOR (17 downto 0);
res_V : OUT STD_LOGIC_VECTOR (17 downto 0);
res_V_ap_vld : OUT STD_LOGIC );
end;
architecture behav of fir_hw is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"fir_hw,hls_ip_2015_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc6slx9tqg144-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.490000,HLS_SYN_LAT=770,HLS_SYN_TPT=none,HLS_SYN_MEM=2,HLS_SYN_DSP=0,HLS_SYN_FF=100,HLS_SYN_LUT=259}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (8 downto 0) := "000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (8 downto 0) := "000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (8 downto 0) := "000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (8 downto 0) := "000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (8 downto 0) := "001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (8 downto 0) := "010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (8 downto 0) := "100000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv39_0 : STD_LOGIC_VECTOR (38 downto 0) := "000000000000000000000000000000000000000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv7_7F : STD_LOGIC_VECTOR (6 downto 0) := "1111111";
constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_const_lv8_80 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv32_26 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100110";
constant ap_const_lv3_7 : STD_LOGIC_VECTOR (2 downto 0) := "111";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv17_0 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
constant ap_const_lv18_1FFFF : STD_LOGIC_VECTOR (17 downto 0) := "011111111111111111";
constant ap_const_lv18_20001 : STD_LOGIC_VECTOR (17 downto 0) := "100000000000000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_25 : BOOLEAN;
signal smpl_V_address0 : STD_LOGIC_VECTOR (6 downto 0);
signal smpl_V_ce0 : STD_LOGIC;
signal smpl_V_we0 : STD_LOGIC;
signal smpl_V_d0 : STD_LOGIC_VECTOR (17 downto 0);
signal smpl_V_q0 : STD_LOGIC_VECTOR (17 downto 0);
signal coeff_hw_V_address0 : STD_LOGIC_VECTOR (6 downto 0);
signal coeff_hw_V_ce0 : STD_LOGIC;
signal coeff_hw_V_q0 : STD_LOGIC_VECTOR (14 downto 0);
signal i_1_fu_183_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal i_1_reg_525 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_59 : BOOLEAN;
signal exitcond1_fu_177_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_2_fu_205_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal i_2_reg_538 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_74 : BOOLEAN;
signal exitcond_fu_199_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal qb_assign_1_fu_249_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal qb_assign_1_reg_553 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_94 : BOOLEAN;
signal accu_V_fu_273_p2 : STD_LOGIC_VECTOR (38 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_105 : BOOLEAN;
signal p_Val2_2_fu_300_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal p_Val2_2_reg_573 : STD_LOGIC_VECTOR (17 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_114 : BOOLEAN;
signal p_38_i_fu_400_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_38_i_reg_579 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_fu_412_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_reg_584 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_fu_440_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_reg_589 : STD_LOGIC_VECTOR (0 downto 0);
signal i_reg_142 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_133 : BOOLEAN;
signal p_Val2_s_reg_154 : STD_LOGIC_VECTOR (38 downto 0);
signal i1_reg_166 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_2_fu_189_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_fu_194_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_1_fu_211_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_154 : BOOLEAN;
signal tmp_14_fu_225_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_16_fu_235_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal r_fu_229_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal r_i_i_fu_243_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal qbit_fu_217_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_263_p0 : STD_LOGIC_VECTOR (17 downto 0);
signal grp_fu_263_p1 : STD_LOGIC_VECTOR (14 downto 0);
signal grp_fu_263_p2 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_9_cast_fu_269_p1 : STD_LOGIC_VECTOR (38 downto 0);
signal p_Val2_1_fu_279_p4 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_s_fu_297_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal newsignbit_fu_306_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_fu_289_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_fu_314_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_fu_334_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_4_fu_350_p4 : STD_LOGIC_VECTOR (3 downto 0);
signal carry_fu_320_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_ones_fu_360_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_zeros_fu_366_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_fu_326_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal Range2_all_ones_fu_344_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_fu_380_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_41_i_fu_386_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal deleted_zeros_fu_372_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal p_not_i_fu_406_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal deleted_ones_fu_392_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge40_demorgan_i_fu_418_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_fu_430_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_5_fu_434_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge40_i_fu_424_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal signbit_fu_446_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_fu_459_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_454_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp2_fu_470_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_fu_475_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_fu_465_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_2_not_fu_487_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_fu_481_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_fu_493_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_5_mux_fu_499_p3 : STD_LOGIC_VECTOR (17 downto 0);
signal p_Val2_5_fu_506_p3 : STD_LOGIC_VECTOR (17 downto 0);
signal grp_fu_263_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (8 downto 0);
component fir_hw_mul_18s_15s_33_3 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (17 downto 0);
din1 : IN STD_LOGIC_VECTOR (14 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (32 downto 0) );
end component;
component fir_hw_smpl_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (6 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (17 downto 0);
q0 : OUT STD_LOGIC_VECTOR (17 downto 0) );
end component;
component fir_hw_coeff_hw_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (6 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (14 downto 0) );
end component;
begin
smpl_V_U : component fir_hw_smpl_V
generic map (
DataWidth => 18,
AddressRange => 128,
AddressWidth => 7)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => smpl_V_address0,
ce0 => smpl_V_ce0,
we0 => smpl_V_we0,
d0 => smpl_V_d0,
q0 => smpl_V_q0);
coeff_hw_V_U : component fir_hw_coeff_hw_V
generic map (
DataWidth => 15,
AddressRange => 128,
AddressWidth => 7)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => coeff_hw_V_address0,
ce0 => coeff_hw_V_ce0,
q0 => coeff_hw_V_q0);
fir_hw_mul_18s_15s_33_3_U0 : component fir_hw_mul_18s_15s_33_3
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 18,
din1_WIDTH => 15,
dout_WIDTH => 33)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_263_p0,
din1 => grp_fu_263_p1,
ce => grp_fu_263_ce,
dout => grp_fu_263_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- i1_reg_166 assign process. --
i1_reg_166_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
i1_reg_166 <= i_2_reg_538;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond1_fu_177_p2 = ap_const_lv1_0)))) then
i1_reg_166 <= ap_const_lv8_0;
end if;
end if;
end process;
-- i_reg_142 assign process. --
i_reg_142_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
i_reg_142 <= i_1_reg_525;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
i_reg_142 <= ap_const_lv7_0;
end if;
end if;
end process;
-- p_Val2_s_reg_154 assign process. --
p_Val2_s_reg_154_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
p_Val2_s_reg_154 <= accu_V_fu_273_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond1_fu_177_p2 = ap_const_lv1_0)))) then
p_Val2_s_reg_154 <= ap_const_lv39_0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
brmerge_i_reg_584 <= brmerge_i_fu_412_p2;
p_38_i_reg_579 <= p_38_i_fu_400_p2;
p_Val2_2_reg_573 <= p_Val2_2_fu_300_p2;
tmp_10_reg_589 <= tmp_10_fu_440_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
i_1_reg_525 <= i_1_fu_183_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
i_2_reg_538 <= i_2_fu_205_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((ap_const_lv1_0 = exitcond_fu_199_p2)))) then
qb_assign_1_reg_553 <= qb_assign_1_fu_249_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, exitcond1_fu_177_p2, exitcond_fu_199_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((exitcond1_fu_177_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st4_fsm_3 =>
if (not((ap_const_lv1_0 = exitcond_fu_199_p2))) then
ap_NS_fsm <= ap_ST_st8_fsm_7;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXXXX";
end case;
end process;
Range1_all_ones_fu_360_p2 <= "1" when (tmp_4_fu_350_p4 = ap_const_lv4_F) else "0";
Range1_all_zeros_fu_366_p2 <= "1" when (tmp_4_fu_350_p4 = ap_const_lv4_0) else "0";
Range2_all_ones_fu_344_p2 <= "1" when (tmp_9_fu_334_p4 = ap_const_lv3_7) else "0";
accu_V_fu_273_p2 <= std_logic_vector(unsigned(p_Val2_s_reg_154) + unsigned(tmp_9_cast_fu_269_p1));
-- ap_done assign process. --
ap_done_assign_proc : process(ap_sig_cseq_ST_st9_fsm_8)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st9_fsm_8)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_105 assign process. --
ap_sig_bdd_105_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_105 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_114 assign process. --
ap_sig_bdd_114_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_114 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_133 assign process. --
ap_sig_bdd_133_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_133 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_154 assign process. --
ap_sig_bdd_154_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_154 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_25 assign process. --
ap_sig_bdd_25_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_25 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_59 assign process. --
ap_sig_bdd_59_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_59 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_74 assign process. --
ap_sig_bdd_74_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_74 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_94 assign process. --
ap_sig_bdd_94_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_94 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_25)
begin
if (ap_sig_bdd_25) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_59)
begin
if (ap_sig_bdd_59) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_133)
begin
if (ap_sig_bdd_133) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_74)
begin
if (ap_sig_bdd_74) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_94)
begin
if (ap_sig_bdd_94) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_105)
begin
if (ap_sig_bdd_105) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_114)
begin
if (ap_sig_bdd_114) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_154)
begin
if (ap_sig_bdd_154) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
brmerge40_demorgan_i_fu_418_p2 <= (newsignbit_fu_306_p3 and deleted_ones_fu_392_p3);
brmerge40_i_fu_424_p2 <= (brmerge40_demorgan_i_fu_418_p2 xor ap_const_lv1_1);
brmerge_fu_493_p2 <= (overflow_fu_465_p2 or underflow_2_not_fu_487_p2);
brmerge_i_fu_412_p2 <= (newsignbit_fu_306_p3 or p_not_i_fu_406_p2);
brmerge_i_i_fu_481_p2 <= (underflow_fu_475_p2 or overflow_fu_465_p2);
carry_fu_320_p2 <= (tmp_15_fu_289_p3 and tmp_6_fu_314_p2);
coeff_hw_V_address0 <= tmp_1_fu_211_p1(7 - 1 downto 0);
-- coeff_hw_V_ce0 assign process. --
coeff_hw_V_ce0_assign_proc : process(ap_sig_cseq_ST_st4_fsm_3)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
coeff_hw_V_ce0 <= ap_const_logic_1;
else
coeff_hw_V_ce0 <= ap_const_logic_0;
end if;
end process;
deleted_ones_fu_392_p3 <=
p_41_i_fu_386_p2 when (carry_fu_320_p2(0) = '1') else
Range1_all_ones_fu_360_p2;
deleted_zeros_fu_372_p3 <=
Range1_all_ones_fu_360_p2 when (carry_fu_320_p2(0) = '1') else
Range1_all_zeros_fu_366_p2;
exitcond1_fu_177_p2 <= "1" when (i_reg_142 = ap_const_lv7_7F) else "0";
exitcond_fu_199_p2 <= "1" when (i1_reg_166 = ap_const_lv8_80) else "0";
grp_fu_263_ce <= ap_const_logic_1;
grp_fu_263_p0 <= smpl_V_q0;
grp_fu_263_p1 <= coeff_hw_V_q0;
i_1_fu_183_p2 <= std_logic_vector(unsigned(i_reg_142) + unsigned(ap_const_lv7_1));
i_2_fu_205_p2 <= std_logic_vector(unsigned(i1_reg_166) + unsigned(ap_const_lv8_1));
newsignbit_fu_306_p3 <= p_Val2_2_fu_300_p2(17 downto 17);
overflow_fu_465_p2 <= (brmerge_i_reg_584 and tmp_3_fu_459_p2);
p_38_i_fu_400_p2 <= (carry_fu_320_p2 and Range1_all_ones_fu_360_p2);
p_41_i_fu_386_p2 <= (Range2_all_ones_fu_344_p2 and tmp_7_fu_380_p2);
p_Val2_1_fu_279_p4 <= p_Val2_s_reg_154(34 downto 17);
p_Val2_2_fu_300_p2 <= std_logic_vector(unsigned(p_Val2_1_fu_279_p4) + unsigned(tmp_s_fu_297_p1));
p_Val2_5_fu_506_p3 <=
ap_const_lv18_20001 when (underflow_fu_475_p2(0) = '1') else
p_Val2_2_reg_573;
p_Val2_5_mux_fu_499_p3 <=
ap_const_lv18_1FFFF when (brmerge_i_i_fu_481_p2(0) = '1') else
p_Val2_2_reg_573;
p_not_i_fu_406_p2 <= (deleted_zeros_fu_372_p3 xor ap_const_lv1_1);
qb_assign_1_fu_249_p2 <= (r_i_i_fu_243_p2 and qbit_fu_217_p3);
qbit_fu_217_p3 <= p_Val2_s_reg_154(16 downto 16);
r_fu_229_p2 <= "0" when (tmp_14_fu_225_p1 = ap_const_lv16_0) else "1";
r_i_i_fu_243_p2 <= (tmp_16_fu_235_p3 or r_fu_229_p2);
res_V <=
p_Val2_5_mux_fu_499_p3 when (brmerge_fu_493_p2(0) = '1') else
p_Val2_5_fu_506_p3;
-- res_V_ap_vld assign process. --
res_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st9_fsm_8)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
res_V_ap_vld <= ap_const_logic_1;
else
res_V_ap_vld <= ap_const_logic_0;
end if;
end process;
signbit_fu_446_p3 <= p_Val2_s_reg_154(38 downto 38);
-- smpl_V_address0 assign process. --
smpl_V_address0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_177_p2, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st3_fsm_2, tmp_2_fu_189_p1, tmp_fu_194_p1, tmp_1_fu_211_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
smpl_V_address0 <= tmp_fu_194_p1(7 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond1_fu_177_p2 = ap_const_lv1_0)))) then
smpl_V_address0 <= ap_const_lv7_7F;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
smpl_V_address0 <= tmp_1_fu_211_p1(7 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond1_fu_177_p2 = ap_const_lv1_0))) then
smpl_V_address0 <= tmp_2_fu_189_p1(7 - 1 downto 0);
else
smpl_V_address0 <= "XXXXXXX";
end if;
end process;
-- smpl_V_ce0 assign process. --
smpl_V_ce0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_177_p2, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st3_fsm_2)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond1_fu_177_p2 = ap_const_lv1_0)) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond1_fu_177_p2 = ap_const_lv1_0))))) then
smpl_V_ce0 <= ap_const_logic_1;
else
smpl_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- smpl_V_d0 assign process. --
smpl_V_d0_assign_proc : process(input_V, smpl_V_q0, ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_177_p2, ap_sig_cseq_ST_st3_fsm_2)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
smpl_V_d0 <= smpl_V_q0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond1_fu_177_p2 = ap_const_lv1_0)))) then
smpl_V_d0 <= input_V;
else
smpl_V_d0 <= "XXXXXXXXXXXXXXXXXX";
end if;
end process;
-- smpl_V_we0 assign process. --
smpl_V_we0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_177_p2, ap_sig_cseq_ST_st3_fsm_2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond1_fu_177_p2 = ap_const_lv1_0))))) then
smpl_V_we0 <= ap_const_logic_1;
else
smpl_V_we0 <= ap_const_logic_0;
end if;
end process;
tmp2_fu_470_p2 <= (tmp_10_reg_589 and tmp_8_fu_454_p2);
tmp_10_fu_440_p2 <= (tmp_5_fu_434_p2 or brmerge40_i_fu_424_p2);
tmp_14_fu_225_p1 <= p_Val2_s_reg_154(16 - 1 downto 0);
tmp_15_fu_289_p3 <= p_Val2_s_reg_154(34 downto 34);
tmp_16_fu_235_p3 <= p_Val2_s_reg_154(17 downto 17);
tmp_18_fu_326_p3 <= p_Val2_s_reg_154(35 downto 35);
tmp_19_fu_430_p1 <= p_Val2_2_fu_300_p2(17 - 1 downto 0);
tmp_1_fu_211_p1 <= std_logic_vector(resize(unsigned(i1_reg_166),64));
tmp_2_fu_189_p1 <= std_logic_vector(resize(unsigned(i_1_fu_183_p2),64));
tmp_3_fu_459_p2 <= (signbit_fu_446_p3 xor ap_const_lv1_1);
tmp_4_fu_350_p4 <= p_Val2_s_reg_154(38 downto 35);
tmp_5_fu_434_p2 <= "1" when (tmp_19_fu_430_p1 = ap_const_lv17_0) else "0";
tmp_6_fu_314_p2 <= (newsignbit_fu_306_p3 xor ap_const_lv1_1);
tmp_7_fu_380_p2 <= (tmp_18_fu_326_p3 xor ap_const_lv1_1);
tmp_8_fu_454_p2 <= (p_38_i_reg_579 xor ap_const_lv1_1);
tmp_9_cast_fu_269_p1 <= std_logic_vector(resize(signed(grp_fu_263_p2),39));
tmp_9_fu_334_p4 <= p_Val2_s_reg_154(38 downto 36);
tmp_fu_194_p1 <= std_logic_vector(resize(unsigned(i_reg_142),64));
tmp_s_fu_297_p1 <= std_logic_vector(resize(unsigned(qb_assign_1_reg_553),18));
underflow_2_not_fu_487_p2 <= (underflow_fu_475_p2 xor ap_const_lv1_1);
underflow_fu_475_p2 <= (tmp2_fu_470_p2 and signbit_fu_446_p3);
end behav;
| gpl-2.0 | 307bce417a3b9388e9ba2dd6ea2b27dc | 0.584761 | 2.745801 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/readout/level0_wrapper.vhd | 1 | 13,403 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 28.04.2017 14:18:44
-- Design Name: Level-0 Wrapper
-- Module Name: level0_wrapper - RTL
-- Project Name: NTUA-BNL VMM3 Readout Firmware
-- Target Devices: Xilinx xc7a200t-2fbg484
-- Tool Versions: Vivado 2016.4
-- Description: Wrapper that contains all necessary modules for implementing
-- level0 readout of the VMMs
--
-- Dependencies:
--
-- Changelog:
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
use UNISIM.VComponents.all;
entity level0_wrapper is
Generic(is_mmfe8 : std_logic;
vmmReadoutMode : std_logic);
Port(
------------------------------------
------- General Interface ----------
clk_ckdt : in std_logic; -- will be forwarded to the VMM
clk : in std_logic; -- buffer read domain
rst_buff : in std_logic; -- reset buffer
level_0 : in std_logic; -- level-0 signal
wr_accept : in std_logic; -- buffer acceptance window
vmm_conf : in std_logic; -- high during VMM configuration
daq_on_inhib : out std_logic; -- prevent daq_on state before checking link health
------------------------------------
---- Packet Formation Interface ----
rd_ena_buff : in std_logic;
rst_intf_proc : in std_logic;
vmmId : in std_logic_vector(2 downto 0); -- VMM to be readout
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(15 downto 0);
vmmEventDone : out std_logic;
linkHealth_bmsk : out std_logic_vector(8 downto 1);
------------------------------------
---------- VMM3 Interface ----------
vmm_data0_vec : in std_logic_vector(8 downto 1); -- Single-ended data0 from VMM
vmm_data1_vec : in std_logic_vector(8 downto 1); -- Single-ended data1 from VMM
vmm_cktk_vec : out std_logic_vector(8 downto 1) -- Strobe to VMM CKTK
);
end level0_wrapper;
architecture RTL of level0_wrapper is
component l0_deserializer_decoder
Port(
------------------------------------
------- General Interface ----------
clk_ckdt : in std_logic; -- will be forwarded to the VMM
level_0 : in std_logic; -- level-0 signal
------------------------------------
-------- Buffer Interface ----------
inhib_wr : in std_logic;
commas_true : out std_logic;
dout_dec : out std_logic_vector(7 downto 0);
wr_en : out std_logic;
------------------------------------
---------- VMM Interface -----------
vmm_data0 : in std_logic;
vmm_data1 : in std_logic
);
end component;
component l0_buffer_wrapper is
Port(
------------------------------------
------- General Interface ----------
clk_ckdt : in std_logic;
clk : in std_logic;
rst_buff : in std_logic;
wr_accept : in std_logic;
level_0 : in std_logic;
------------------------------------
--- Deserializer Interface ---------
inhib_wr : out std_logic;
commas_true : in std_logic;
dout_dec : in std_logic_vector(7 downto 0);
wr_en : in std_logic;
------------------------------------
---- Packet Formation Interface ----
rd_ena_buff : in std_logic;
rst_intf_proc : in std_logic;
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(15 downto 0);
vmmEventDone : out std_logic
);
end component;
component l0_link_health
Generic(is_mmfe8 : std_logic);
Port(
------------------------------------
------- General Interface ----------
clk : in std_logic;
vmm_conf : in std_logic;
daqOn_inhibit : out std_logic;
------------------------------------
--- Deserializer Interface ---------
commas_true : in std_logic_vector(8 downto 1);
------------------------------------
---- Packet Formation Interface ----
EventDone_dummy : out std_logic_vector(8 downto 1);
linkHealth_bitmask : out std_logic_vector(8 downto 1)
);
end component;
type dout_dec_array is array (8 downto 1) of std_logic_vector(7 downto 0);
type vmmWord_array is array (8 downto 1) of std_logic_vector(15 downto 0);
signal wr_en : std_logic_vector(8 downto 1) := (others => '0');
signal rd_ena_buff_i : std_logic_vector(8 downto 1) := (others => '0');
signal vmmWordReady_i : std_logic_vector(8 downto 1) := (others => '0');
signal EventDone_health_i : std_logic_vector(8 downto 1) := (others => '0');
signal vmmEventDone_i : std_logic_vector(8 downto 1) := (others => '0');
signal inhib_wr_i : std_logic_vector(8 downto 1) := (others => '0');
signal commas_true_i : std_logic_vector(8 downto 1) := (others => '0');
signal commas_true_s0 : std_logic_vector(8 downto 1) := (others => '0');
signal commas_true_s1 : std_logic_vector(8 downto 1) := (others => '0');
signal vmmWord_i : vmmWord_array;
signal dout_dec : dout_dec_array;
attribute ASYNC_REG : string;
attribute ASYNC_REG of commas_true_s0 : signal is "TRUE";
attribute ASYNC_REG of commas_true_s1 : signal is "TRUE";
-- function to convert std_logic to integer for instance generation
function sl2int (x: std_logic) return integer is
begin
if(x='1')then
return 8;
else
return 1;
end if;
end;
begin
---------------------------------------------
------- Add VMM Readout Instances -----------
---------------------------------------------
readout_instances: for I in 1 to sl2int(is_mmfe8) generate
des_dec_inst: l0_deserializer_decoder
Port Map(
------------------------------------
------- General Interface ----------
clk_ckdt => clk_ckdt,
level_0 => level_0,
------------------------------------
-------- Buffer Interface ----------
inhib_wr => inhib_wr_i(I),
commas_true => commas_true_i(I),
dout_dec => dout_dec(I),
wr_en => wr_en(I),
------------------------------------
---------- VMM Interface -----------
vmm_data0 => vmm_data0_vec(I),
vmm_data1 => vmm_data1_vec(I)
);
l0_buf_wr_inst: l0_buffer_wrapper
Port Map(
------------------------------------
------- General Interface ----------
clk_ckdt => clk_ckdt,
clk => clk,
rst_buff => rst_buff,
wr_accept => wr_accept,
level_0 => level_0,
------------------------------------
--- Deserializer Interface ---------
inhib_wr => inhib_wr_i(I),
commas_true => commas_true_i(I),
dout_dec => dout_dec(I),
wr_en => wr_en(I),
------------------------------------
---- Packet Formation Interface ----
rd_ena_buff => rd_ena_buff_i(I),
rst_intf_proc => rst_intf_proc,
vmmWordReady => vmmWordReady_i(I),
vmmWord => vmmWord_i(I),
vmmEventDone => vmmEventDone_i(I)
);
end generate readout_instances;
-- check comma alignment
l0_link_health_inst: l0_link_health
Generic Map(is_mmfe8 => is_mmfe8)
Port Map(
------------------------------------
------- General Interface ----------
clk => clk,
vmm_conf => vmm_conf,
daqOn_inhibit => daq_on_inhib,
------------------------------------
--- Deserializer Interface ---------
commas_true => commas_true_s1,
------------------------------------
---- Packet Formation Interface ----
EventDone_dummy => EventDone_health_i,
linkHealth_bitmask => linkHealth_bmsk
);
sync_linkHealth: process(clk)
begin
if(rising_edge(clk))then
commas_true_s0 <= commas_true_i;
commas_true_s1 <= commas_true_s0;
end if;
end process;
-- multiplexer that drives the packet formation signals corresponding to the vmmID
vmm_ID_MUX: process(vmmId, vmmWordReady_i, vmmWord_i, vmmEventDone_i, EventDone_health_i, rd_ena_buff)
begin
case vmmId is
when "000" =>
vmmWordReady <= vmmWordReady_i(1) and not EventDone_health_i(1);
vmmWord <= vmmWord_i(1);
vmmEventDone <= vmmEventDone_i(1) or EventDone_health_i(1);
rd_ena_buff_i(1) <= rd_ena_buff;
rd_ena_buff_i(8 downto 2) <= (others => '0');
when "001" =>
vmmWordReady <= vmmWordReady_i(2) and not EventDone_health_i(2);
vmmWord <= vmmWord_i(2);
vmmEventDone <= vmmEventDone_i(2) or EventDone_health_i(2);
rd_ena_buff_i(2) <= rd_ena_buff;
rd_ena_buff_i(8 downto 3) <= (others => '0');
rd_ena_buff_i(1 downto 1) <= (others => '0');
when "010" =>
vmmWordReady <= vmmWordReady_i(3) and not EventDone_health_i(3);
vmmWord <= vmmWord_i(3);
vmmEventDone <= vmmEventDone_i(3) or EventDone_health_i(3);
rd_ena_buff_i(3) <= rd_ena_buff;
rd_ena_buff_i(8 downto 4) <= (others => '0');
rd_ena_buff_i(2 downto 1) <= (others => '0');
when "011" =>
vmmWordReady <= vmmWordReady_i(4) and not EventDone_health_i(4);
vmmWord <= vmmWord_i(4);
vmmEventDone <= vmmEventDone_i(4) or EventDone_health_i(4);
rd_ena_buff_i(4) <= rd_ena_buff;
rd_ena_buff_i(8 downto 5) <= (others => '0');
rd_ena_buff_i(3 downto 1) <= (others => '0');
when "100" =>
vmmWordReady <= vmmWordReady_i(5) and not EventDone_health_i(5);
vmmWord <= vmmWord_i(5);
vmmEventDone <= vmmEventDone_i(5) or EventDone_health_i(5);
rd_ena_buff_i(5) <= rd_ena_buff;
rd_ena_buff_i(8 downto 6) <= (others => '0');
rd_ena_buff_i(4 downto 1) <= (others => '0');
when "101" =>
vmmWordReady <= vmmWordReady_i(6) and not EventDone_health_i(6);
vmmWord <= vmmWord_i(6);
vmmEventDone <= vmmEventDone_i(6) or EventDone_health_i(6);
rd_ena_buff_i(6) <= rd_ena_buff;
rd_ena_buff_i(8 downto 7) <= (others => '0');
rd_ena_buff_i(5 downto 1) <= (others => '0');
when "110" =>
vmmWordReady <= vmmWordReady_i(7) and not EventDone_health_i(7);
vmmWord <= vmmWord_i(7);
vmmEventDone <= vmmEventDone_i(7) or EventDone_health_i(7);
rd_ena_buff_i(7) <= rd_ena_buff;
rd_ena_buff_i(6 downto 1) <= (others => '0');
rd_ena_buff_i(8) <= '0';
when "111" =>
vmmWordReady <= vmmWordReady_i(8) and not EventDone_health_i(8);
vmmWord <= vmmWord_i(8);
vmmEventDone <= vmmEventDone_i(8) or EventDone_health_i(8);
rd_ena_buff_i(8) <= rd_ena_buff;
rd_ena_buff_i(7 downto 1) <= (others => '0');
when others =>
vmmWordReady <= '0';
vmmWord <= (others => '0');
rd_ena_buff_i <= (others => '0');
vmmEventDone <= '0';
end case;
end process;
vmm_cktk_vec(1) <= level_0;
vmm_cktk_vec(2) <= level_0;
vmm_cktk_vec(3) <= level_0;
vmm_cktk_vec(4) <= level_0;
vmm_cktk_vec(5) <= level_0;
vmm_cktk_vec(6) <= level_0;
vmm_cktk_vec(7) <= level_0;
vmm_cktk_vec(8) <= level_0;
end RTL; | gpl-3.0 | 40e1cc3dc86aa5d63d0ae4383e1262e3 | 0.480266 | 3.96304 | false | false | false | false |
rkrajnc/minimig-mist | rtl/mist/sdram.vhd | 1 | 29,688 | ------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2011 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sdram is
port
(
sdata : inout std_logic_vector(15 downto 0);
sdaddr : out std_logic_vector(12 downto 0);
dqm : out std_logic_vector(1 downto 0);
sd_cs : out std_logic_vector(3 downto 0);
ba : buffer std_logic_vector(1 downto 0);
sd_we : out std_logic;
sd_ras : out std_logic;
sd_cas : out std_logic;
sysclk : in std_logic;
reset_in : in std_logic;
cache_rst : in std_logic;
hostWR : in std_logic_vector(15 downto 0);
hostAddr : in std_logic_vector(23 downto 0);
hostState : in std_logic_vector(2 downto 0);
hostL : in std_logic;
hostU : in std_logic;
cpuWR : in std_logic_vector(15 downto 0);
cpuAddr : in std_logic_vector(24 downto 1);
cpuU : in std_logic;
cpuL : in std_logic;
cpustate : in std_logic_vector(5 downto 0); -- clkena & slower(1 downto 0) & ramcs & state;
cpu_dma : in std_logic;
chipWR : in std_logic_vector(15 downto 0);
chipAddr : in std_logic_vector(23 downto 1);
chipU : in std_logic;
chipL : in std_logic;
chipRW : in std_logic;
chip_dma : in std_logic;
c_7m : in std_logic;
hostRD : out std_logic_vector(15 downto 0);
hostena : buffer std_logic;
cpuRD : out std_logic_vector(15 downto 0);
cpuena : out std_logic;
chipRD : out std_logic_vector(15 downto 0);
chip48 : out std_logic_vector(47 downto 0);
reset_out : out std_logic;
enaRDreg : out std_logic;
enaWRreg : buffer std_logic;
ena7RDreg : out std_logic;
ena7WRreg : out std_logic
-- c_7m : out std_logic
);
end;
architecture rtl of sdram is
signal initstate :std_logic_vector(3 downto 0);
signal cas_sd_cs :std_logic_vector(3 downto 0);
signal cas_sd_ras :std_logic;
signal cas_sd_cas :std_logic;
signal cas_sd_we :std_logic;
signal cas_dqm :std_logic_vector(1 downto 0);
signal init_done :std_logic;
signal datain :std_logic_vector(15 downto 0);
signal datawr :std_logic_vector(15 downto 0);
signal casaddr :std_logic_vector(24 downto 0);
signal sdwrite :std_logic;
signal sdata_reg :std_logic_vector(15 downto 0);
-- signal hostCycle :std_logic;
signal zmAddr :std_logic_vector(24 downto 0);
signal zena :std_logic;
signal zcache :std_logic_vector(63 downto 0);
signal zcache_addr :std_logic_vector(23 downto 0);
signal zcache_fill :std_logic;
signal zcachehit :std_logic;
signal zvalid :std_logic_vector(3 downto 0);
signal zequal :std_logic;
signal hostStated :std_logic_vector(1 downto 0);
signal hostRDd :std_logic_vector(15 downto 0);
signal cena :std_logic;
signal ccache :std_logic_vector(63 downto 0);
signal ccache_addr :std_logic_vector(24 downto 0);
signal ccache_fill :std_logic;
signal ccachehit :std_logic;
signal cvalid :std_logic_vector(3 downto 0);
signal cequal :std_logic;
signal cpuStated :std_logic_vector(1 downto 0);
signal cpuRDd :std_logic_vector(15 downto 0);
signal dcache :std_logic_vector(63 downto 0);
signal dcache_addr :std_logic_vector(24 downto 0);
signal dcache_fill :std_logic;
signal dcachehit :std_logic;
signal dvalid :std_logic_vector(3 downto 0);
signal dequal :std_logic;
signal hostSlot_cnt :std_logic_vector(7 downto 0);
signal reset_cnt :std_logic_vector(7 downto 0);
signal reset :std_logic;
signal reset_sdstate :std_logic;
signal c_7md :std_logic;
signal c_7mdd :std_logic;
signal c_7mdr :std_logic;
-- signal cpuCycle :std_logic;
-- signal chipCycle :std_logic;
signal refreshcnt : std_logic_vector(8 downto 0);
signal refresh_pending : std_logic;
type sdram_states is (ph0,ph1,ph2,ph3,ph4,ph5,ph6,ph7,ph8,ph9,ph10,ph11,ph12,ph13,ph14,ph15);
signal sdram_state : sdram_states;
type pass_states is (nop,ras,cas);
signal pass : pass_states;
type slot_type is (refresh,chip,cpu_readcache,cpu_writecache,host,idle);
signal slot1_type : slot_type := idle;
signal slot2_type : slot_type := idle;
signal slot1_bank : std_logic_vector(1 downto 0);
signal slot2_bank : std_logic_vector(1 downto 0);
signal cache_req : std_logic;
signal readcache_fill : std_logic;
signal cache_fill_1 : std_logic;
signal cache_fill_2 : std_logic;
signal chip48_1 : std_logic_vector(15 downto 0);
signal chip48_2 : std_logic_vector(15 downto 0);
signal chip48_3 : std_logic_vector(15 downto 0);
COMPONENT TwoWayCache
GENERIC ( WAITING : INTEGER := 0; WAITRD : INTEGER := 1; WAITFILL : INTEGER := 2; FILL2 : INTEGER := 3;
FILL3 : INTEGER := 4; FILL4 : INTEGER := 5; FILL5 : INTEGER := 6; PAUSE1 : INTEGER := 7 );
PORT
(
clk : IN STD_LOGIC;
reset : IN std_logic;
cache_rst : IN std_logic;
ready : out std_logic;
cpu_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cpu_req : IN STD_LOGIC;
cpu_ack : OUT STD_LOGIC;
cpu_wr_ack : OUT STD_LOGIC;
cpu_rw : IN STD_LOGIC;
cpu_rwl : in std_logic;
cpu_rwu : in std_logic;
data_from_cpu : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
data_to_cpu : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
sdram_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
data_from_sdram : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
data_to_sdram : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
sdram_req : OUT STD_LOGIC;
sdram_fill : IN STD_LOGIC;
sdram_rw : OUT STD_LOGIC
);
END COMPONENT;
-- Write buffer signals
signal writebuffer_req : std_logic;
signal writebuffer_ena : std_logic;
-- signal writebufferCycle : std_logic;
signal writebuffer_dqm : std_logic_vector(1 downto 0);
signal writebufferAddr : std_logic_vector(24 downto 1);
signal writebufferWR : std_logic_vector(15 downto 0);
signal writebufferWR_reg : std_logic_vector(15 downto 0);
signal writebuffer_cache_ack : std_logic;
signal writebuffer_hold : std_logic; -- 1 during write access, cleared to indicate that the buffer can accept the next word.
type writebuffer_states is (waiting,write1,write2,write3);
signal writebuffer_state : writebuffer_states;
signal cpuAddr_mangled : std_logic_vector(24 downto 1);
-- Let's try some bank-interleaving.
-- For addresses in the upper 16 meg we shift bits around
-- so that one bank bit comes from addr(3). This should allow
-- bank interleaving to make things more efficient.
begin
-- Turns out this is counter-productive
--cpuAddr_mangled<=cpuAddr(24)&cpuAddr(3)&cpuAddr(22 downto 4)&cpuAddr(23)&cpuAddr(2 downto 1)
-- when cpuAddr(24)='1' else cpuAddr;
cpuAddr_mangled<=cpuAddr;
process (sysclk, reset_in) begin
if reset_in = '0' THEN
reset_cnt <= "00000000";
reset <= '0';
reset_sdstate <= '0';
elsif (sysclk'event and sysclk='1') THEN
IF reset_cnt="00101010"THEN
reset_sdstate <= '1';
END IF;
IF reset_cnt="10101010"THEN
if sdram_state=ph15 then
reset <= '1';
end if;
ELSE
reset_cnt <= reset_cnt+1;
reset <= '0';
END IF;
end if;
end process;
-------------------------------------------------------------------------
-- SPIHOST cache
-------------------------------------------------------------------------
hostena <= '1' when zena='1' or hostState(1 downto 0)="01" OR zcachehit='1' else '0';
-- Map host processor's address space to 0x400000
zmAddr <= "00" & NOT hostAddr(22) & hostAddr(21 downto 0);
process (sysclk, zmAddr, hostAddr, zcache_addr, zcache, zequal, zvalid, hostRDd)
begin
if zmAddr(23 downto 3)=zcache_addr(23 downto 3) THEN
zequal <='1';
else
zequal <='0';
end if;
zcachehit <= '0';
if zequal='1' and zvalid(0)='1' and hostStated(1)='0' THEN
case (hostAddr(2 downto 1)&zcache_addr(2 downto 1)) is
when "0000"|"0101"|"1010"|"1111"=>
zcachehit <= zvalid(0);
hostRD <= zcache(63 downto 48);
when "0100"|"1001"|"1110"|"0011"=>
zcachehit <= zvalid(1);
hostRD <= zcache(47 downto 32);
when "1000"|"1101"|"0010"|"0111"=>
zcachehit <= zvalid(2);
hostRD <= zcache(31 downto 16);
when "1100"|"0001"|"0110"|"1011"=>
zcachehit <= zvalid(3);
hostRD <= zcache(15 downto 0);
when others=> null;
end case;
else
hostRD <= hostRDd;
end if;
end process;
--Datenbernahme
process (sysclk, reset) begin
if reset = '0' THEN
zcache_fill <= '0';
zena <= '0';
zvalid <= "0000";
elsif (sysclk'event and sysclk='1') THEN
if enaWRreg='1' THEN
zena <= '0';
end if;
if sdram_state=ph9 AND slot1_type=host THEN
hostRDd <= sdata_reg;
end if;
if sdram_state=ph11 AND slot1_type=host THEN
-- if zmAddr=casaddr then and cas_sd_cas='0' then
zena <= '1';
-- end if;
end if;
hostStated <= hostState(1 downto 0);
if zequal='1' and hostState(1 downto 0)="11" THEN
zvalid <= "0000";
end if;
case sdram_state is
when ph7 =>
if hostStated(1)='0' AND slot1_type=host THEN --only instruction cache
zcache_addr <= casaddr(23 downto 0);
zcache_fill <= '1';
zvalid <= "0000";
end if;
when ph9 =>
if zcache_fill='1' THEN
zcache(63 downto 48) <= sdata_reg;
end if;
when ph10 =>
if zcache_fill='1' THEN
zcache(47 downto 32) <= sdata_reg;
end if;
when ph11 =>
if zcache_fill='1' THEN
zcache(31 downto 16) <= sdata_reg;
end if;
when ph12 =>
if zcache_fill='1' THEN
zcache(15 downto 0) <= sdata_reg;
zvalid <= "1111";
end if;
zcache_fill <= '0';
when others => null;
end case;
end if;
end process;
-------------------------------------------------------------------------
-- cpu cache
-------------------------------------------------------------------------
mytwc : component TwoWayCache
PORT map
(
clk => sysclk,
reset => reset,
cache_rst => cache_rst,
ready => open,
cpu_addr => "0000000"&cpuAddr_mangled&'0',
cpu_req => not cpustate(2),
cpu_ack => ccachehit,
cpu_wr_ack => writebuffer_cache_ack,
cpu_rw => NOT cpuState(1) OR NOT cpuState(0),
cpu_rwl => cpuL,
cpu_rwu => cpuU,
data_from_cpu => cpuWR,
data_to_cpu => cpuRD,
sdram_addr(31 downto 3) => open,
sdram_addr(2 downto 0) => open,
data_from_sdram => sdata_reg,
data_to_sdram => open,
sdram_req => cache_req,
sdram_fill => readcache_fill,
sdram_rw => open
);
-- Write buffer, enables CPU to continue while a write is in progress.
process(sysclk, reset) begin
if reset='0' then
writebuffer_req<='0';
writebuffer_ena<='0';
writebuffer_state<=waiting;
elsif rising_edge(sysclk) then
case writebuffer_state is
when waiting =>
-- CPU write cycle, no cycle already pending.
if cpuState(2 downto 0)="011" then
writebufferAddr<=cpuAddr_mangled(24 downto 1);
writebufferWR<=cpuWR;
writebuffer_dqm<=cpuU & cpuL;
writebuffer_req<='1';
if writebuffer_cache_ack='1' then
writebuffer_ena<='1';
writebuffer_state<=write2;
end if;
end if;
when write2 =>
if writebuffer_hold='1' then -- The SDRAM controller has picked up the request
writebuffer_req<='0';
writebuffer_state<=write3;
end if;
when write3 =>
if writebuffer_hold='0' then -- Wait for write cycle to finish, so it's safe to update the signals.
writebuffer_state<=waiting;
end if;
when others =>
writebuffer_state<=waiting;
end case;
if cpuState(2)='1' then -- the CPU has unpaused, so clear the ack signal.
writebuffer_ena<='0';
end if;
end if;
end process;
cpuena <= '1' when cena='1' or ccachehit='1' or writebuffer_ena='1' else '0';
readcache_fill<='1' when
(cache_fill_1='1' and slot1_type=cpu_readcache) or
(cache_fill_2='1' and slot2_type=cpu_readcache)
else '0';
-- cpuena <= '1' when cena='1' or ccachehit='1' or dcachehit='1' else '0';
--
-- process (sysclk, cpuAddr, ccache_addr, ccache, cequal, cvalid, cpuRDd)
-- begin
-- if cpuAddr(24 downto 3)=ccache_addr(24 downto 3) THEN
-- cequal <='1';
-- else
-- cequal <='0';
-- end if;
--
-- if cpuAddr(24 downto 3)=dcache_addr(24 downto 3) THEN
-- dequal <='1';
-- else
-- dequal <='0';
-- end if;
--
-- ccachehit <= '0';
-- dcachehit <= '0';
--
-- if cequal='1' and cvalid(0)='1' and cpuStated(1)='0' THEN -- instruction cache
-- case (cpuAddr(2 downto 1)&ccache_addr(2 downto 1)) is
-- when "0000"|"0101"|"1010"|"1111"=>
-- ccachehit <= cvalid(0);
-- cpuRD <= ccache(63 downto 48);
-- when "0100"|"1001"|"1110"|"0011"=>
-- ccachehit <= cvalid(1);
-- cpuRD <= ccache(47 downto 32);
-- when "1000"|"1101"|"0010"|"0111"=>
-- ccachehit <= cvalid(2);
-- cpuRD <= ccache(31 downto 16);
-- when "1100"|"0001"|"0110"|"1011"=>
-- ccachehit <= cvalid(3);
-- cpuRD <= ccache(15 downto 0);
-- when others=> null;
-- end case;
-- elsif dequal='1' and dvalid(0)='1' and cpuStated(1 downto 0)="10" THEN -- Read data
-- case (cpuAddr(2 downto 1)&dcache_addr(2 downto 1)) is
-- when "0000"|"0101"|"1010"|"1111"=>
-- dcachehit <= dvalid(0);
-- cpuRD <= dcache(63 downto 48);
-- when "0100"|"1001"|"1110"|"0011"=>
-- dcachehit <= dvalid(1);
-- cpuRD <= dcache(47 downto 32);
-- when "1000"|"1101"|"0010"|"0111"=>
-- dcachehit <= dvalid(2);
-- cpuRD <= dcache(31 downto 16);
-- when "1100"|"0001"|"0110"|"1011"=>
-- dcachehit <= dvalid(3);
-- cpuRD <= dcache(15 downto 0);
-- when others=> null;
-- end case;
-- else
-- cpuRD <= cpuRDd;
-- end if;
-- end process;
--
--
----Datenbernahme
-- process (sysclk, reset) begin
-- if reset = '0' THEN
-- ccache_fill <= '0';
-- cena <= '0';
-- dcache_fill <= '0';
-- cvalid <= "0000";
-- dvalid <= "0000";
-- elsif (sysclk'event and sysclk='1') THEN
-- if cpuState(5)='1' THEN
-- cena <= '0';
-- end if;
-- if sdram_state=ph9 AND cpuCycle='1' THEN
-- cpuRDd <= sdata_reg;
-- end if;
-- if sdram_state=ph11 AND cpuCycle='1' THEN
-- if cpuAddr=casaddr(24 downto 1) and cas_sd_cas='0' then
-- cena <= '1';
-- end if;
-- end if;
-- cpuStated <= cpuState(1 downto 0);
--
-- -- Invalidate caches on write
-- if cequal='1' and cpuState(1 downto 0)="11" THEN
-- cvalid <= "0000";
-- end if;
-- if dequal='1' and cpuState(1 downto 0)="11" THEN
-- dvalid <= "0000";
-- end if;
--
-- case sdram_state is
-- when ph7 =>
-- if cpuCycle='1' then
-- if cpuStated(1)='0' THEN -- instruction cache
-- ccache_addr <= casaddr;
-- ccache_fill <= '1';
-- cvalid <= "0000";
-- elsif cpuStated(1 downto 0)="10" THEN -- data cache
-- dcache_addr <= casaddr;
-- dcache_fill <= '1';
-- dvalid <= "0000";
-- end if;
-- end if;
-- when ph9 =>
-- if ccache_fill='1' THEN
-- ccache(63 downto 48) <= sdata_reg;
-- end if;
-- if dcache_fill='1' THEN
-- dcache(63 downto 48) <= sdata_reg;
-- end if;
-- when ph10 =>
-- if ccache_fill='1' THEN
-- ccache(47 downto 32) <= sdata_reg;
-- end if;
-- if dcache_fill='1' THEN
-- dcache(47 downto 32) <= sdata_reg;
-- end if;
-- when ph11 =>
-- if ccache_fill='1' THEN
-- ccache(31 downto 16) <= sdata_reg;
-- end if;
-- if dcache_fill='1' THEN
-- dcache(31 downto 16) <= sdata_reg;
-- end if;
-- when ph12 =>
-- if ccache_fill='1' THEN
-- ccache(15 downto 0) <= sdata_reg;
-- cvalid <= "1111";
-- end if;
-- if dcache_fill='1' THEN
-- dcache(15 downto 0) <= sdata_reg;
-- dvalid <= "1111";
-- end if;
-- ccache_fill <= '0';
-- dcache_fill <= '0';
-- when others => null;
-- end case;
-- end if;
-- end process;
-------------------------------------------------------------------------
-- chip cache
-------------------------------------------------------------------------
process (sysclk, sdata_reg)
begin
if (sysclk'event and sysclk='1') then
if slot1_type=chip then
case sdram_state is
when ph9 =>
chipRD <= sdata_reg;
when ph10 =>
chip48_1 <= sdata_reg;
when ph11 =>
chip48_2 <= sdata_reg;
when ph12 =>
chip48_3 <= sdata_reg;
when others =>
null;
end case;
end if;
end if;
end process;
chip48 <= chip48_1 & chip48_2 & chip48_3;
-------------------------------------------------------------------------
-- SDRAM Basic
-------------------------------------------------------------------------
reset_out <= init_done;
process (sysclk, reset, sdwrite, datain) begin
IF sdwrite='1' THEN
sdata <= datawr;
-- sdata <= datain;
ELSE
sdata <= "ZZZZZZZZZZZZZZZZ";
END IF;
if (sysclk'event and sysclk='0') THEN
c_7md <= c_7m;
END IF;
if (sysclk'event and sysclk='1') THEN
if sdram_state=ph2 THEN
case slot1_type is
when chip =>
datawr <= chipWR;
when cpu_writecache =>
datawr <= writebufferWR_reg;
when others =>
datawr <= hostWR;
END case;
END IF;
if sdram_state=ph10 THEN
case slot2_type is
when chip =>
datawr <= chipWR;
when cpu_writecache =>
datawr <= writebufferWR_reg;
when others =>
datawr <= hostWR;
END case;
END IF;
sdata_reg <= sdata;
c_7mdd <= c_7md;
c_7mdr <= c_7md AND NOT c_7mdd;
if reset_sdstate = '0' then
sdwrite <= '0';
enaRDreg <= '0';
enaWRreg <= '0';
ena7RDreg <= '0';
ena7WRreg <= '0';
ELSE
sdwrite <= '0';
enaRDreg <= '0';
enaWRreg <= '0';
ena7RDreg <= '0';
ena7WRreg <= '0';
case sdram_state is --LATENCY=3
when ph2 => enaWRreg <= '1';
when ph3 => sdwrite <= '1';
when ph4 => sdwrite <= '1';
when ph5 => sdwrite <= '1';
when ph6 => enaWRreg <= '1';
ena7RDreg <= '1';
when ph10 => enaWRreg <= '1';
when ph11 => sdwrite<= '1'; -- Access slot 2
when ph12 => sdwrite<= '1';
when ph13 => sdwrite<= '1';
when ph14 => enaWRreg <= '1';
ena7WRreg <= '1';
when others => null;
end case;
END IF;
if reset = '0' then
initstate <= (others => '0');
init_done <= '0';
ELSE
case sdram_state is --LATENCY=3
when ph15 => if initstate /= "1111" THEN
initstate <= initstate+1;
else
init_done <='1';
end if;
when others => null;
end case;
END IF;
IF c_7mdr='1' THEN
sdram_state <= ph2;
ELSE
case sdram_state is --LATENCY=3
when ph0 => sdram_state <= ph1;
when ph1 => sdram_state <= ph2;
when ph2 => sdram_state <= ph3;
when ph3 => sdram_state <= ph4;
when ph4 => sdram_state <= ph5;
when ph5 => sdram_state <= ph6;
when ph6 => sdram_state <= ph7;
when ph7 => sdram_state <= ph8;
when ph8 => sdram_state <= ph9;
when ph9 => sdram_state <= ph10;
when ph10 => sdram_state <= ph11;
when ph11 => sdram_state <= ph12;
when ph12 => sdram_state <= ph13;
when ph13 => sdram_state <= ph14;
when ph14 => sdram_state <= ph15;
when others => sdram_state <= ph0;
end case;
END IF;
END IF;
end process;
-- Address bits will be allocated as follows:
-- 24 downto 23: bank
-- 22 downto 10: row
-- 9 downto 1: column
process (sysclk, initstate, pass, hostAddr, datain, init_done, casaddr, cpuU, cpuL) begin
if (sysclk'event and sysclk='1') THEN
if reset='0' then
refresh_pending<='0';
slot1_type<=idle;
slot2_type<=idle;
end if;
sd_cs <="1111";
sd_ras <= '1';
sd_cas <= '1';
sd_we <= '1';
sdaddr <= "XXXXXXXXXXXXX";
ba <= "00";
dqm <= "00";
cache_fill_1<='0';
cache_fill_2<='0';
if cpuState(5)='1' then
cena<='0';
end if;
if init_done='0' then
if sdram_state =ph1 then
case initstate is
when "0010" => --PRECHARGE
sdaddr(10) <= '1'; --all banks
sd_cs <="0000";
sd_ras <= '0';
sd_cas <= '1';
sd_we <= '0';
when "0011"|"0100"|"0101"|"0110"|"0111"|"1000"|"1001"|"1010"|"1011"|"1100" => --AUTOREFRESH
sd_cs <="0000";
sd_ras <= '0';
sd_cas <= '0';
sd_we <= '1';
when "1101" => --LOAD MODE REGISTER
sd_cs <="0000";
sd_ras <= '0';
sd_cas <= '0';
sd_we <= '0';
sdaddr <= "0001000110010"; --BURST=4 LATENCY=3
when others => null; --NOP
end case;
END IF;
else
-- Time slot control
case sdram_state is
when ph0 =>
cache_fill_2 <='1'; -- slot 2
when ph1 =>
cache_fill_2 <='1'; -- slot 2
-- cpuCycle <= '0';
-- chipCycle <= '0';
-- hostCycle <= '0';
-- writebufferCycle <= '0';
cas_sd_cs <= "1110";
cas_sd_ras <= '1';
cas_sd_cas <= '1';
cas_sd_we <= '1';
IF hostSlot_cnt /= "00000000" THEN
hostSlot_cnt <= hostSlot_cnt-1;
END IF;
if refreshcnt = "000000000" then
refresh_pending<='1';
else
refreshcnt <= refreshcnt-1;
end if;
-- We give the chipset first priority...
-- (This includes anything on the "motherboard" - chip RAM, slow RAM and Kickstart, turbo modes notwithstanding
IF chip_dma='0' OR chipRW='0' THEN
slot1_type<=chip; -- chipCycle <= '1';
sdaddr <= chipAddr(22 downto 10);
ba <= "00"; -- Always bank zero for chipset accesses, so we can interleave Fast RAM access
slot1_bank<="00";
cas_dqm <= chipU& chipL;
sd_cs <= "1110"; --ACTIVE
sd_ras <= '0';
casaddr <= '0'&chipAddr&'0';
-- datain <= chipWR;
cas_sd_cas <= '0';
cas_sd_we <= chipRW;
-- Next in line is refresh...
-- (A refresh cycle blocks both access slots)
elsif refresh_pending='1' and slot2_type=idle then
sd_cs <="0000"; --AUTOREFRESH
sd_ras <= '0';
sd_cas <= '0';
refreshcnt <= "111111111";
slot1_type<=refresh;
refresh_pending<='0';
-- -- The Amiga CPU gets next bite of the cherry, unless the OSD CPU has been cycle-starved...
-- -- ELSIF cpuState(2)='0' AND cpuState(5)='0'
-- -- Request from write buffer.
ELSIF (writebuffer_req='1')
and (hostslot_cnt/="00000000" or (hostState(2)='1' or hostena='1'))
and (slot2_type=idle or slot2_bank/=writebufferAddr(24 downto 23))
then
-- We only yeild to the OSD CPU if it's both cycle-starved and ready to go.
slot1_type<=cpu_writecache;
sdaddr <= writebufferAddr(22 downto 10);
ba <= writebufferAddr(24 downto 23);
slot1_bank<=writebufferAddr(24 downto 23);
cas_dqm <= writebuffer_dqm;
sd_cs <= "1110"; --ACTIVE
sd_ras <= '0';
casaddr <= writebufferAddr(24 downto 1)&'0';
cas_sd_we <= '0';
-- datain <= writebufferWR;
writebufferWR_reg <= writebufferWR;
cas_sd_cas <= '0';
writebuffer_hold<='1'; -- Let the write buffer know we're about to write.
-- Request from read cache
ELSIF (cache_req='1')
and (hostslot_cnt/="00000000" or (hostState(2)='1' or hostena='1'))
and (slot2_type=idle or slot2_bank/=cpuAddr_mangled(24 downto 23))
then
-- We only yeild to the OSD CPU if it's both cycle-starved and ready to go.
slot1_type<=cpu_readcache;
sdaddr <= cpuAddr_mangled(22 downto 10);
ba <= cpuAddr_mangled(24 downto 23);
slot1_bank<=cpuAddr_mangled(24 downto 23);
cas_dqm <= cpuU& cpuL;
sd_cs <= "1110"; --ACTIVE
sd_ras <= '0';
casaddr <= cpuAddr_mangled(24 downto 1)&'0';
-- if (cpuState(1) and cpuState(0))='1' then -- Write cycle
-- casaddr <= cpuAddr(24 downto 1)&'0';
-- cas_sd_we <= '0';
-- else
---- casaddr <= cpuAddr(24 downto 3)&"000";
cas_sd_we <= '1';
-- end if;
-- datain <= cpuWR;
cas_sd_cas <= '0';
ELSIF hostState(2)='0' AND hostena='0' THEN
hostSlot_cnt <= "00001111";
slot1_type<=host;
sdaddr <= zmAddr(22 downto 10);
ba <= "00"; -- Always bank zero for SPI host CPU
slot1_bank<="00";
cas_dqm <= hostU& hostL;
sd_cs <= "1110"; --ACTIVE
sd_ras <= '0';
casaddr <= zmAddr;
-- datain <= hostWR;
cas_sd_cas <= '0';
IF hostState="011" THEN
cas_sd_we <= '0';
END IF;
-- elsif slot2_type=idle then
---- If no-one else wants this cycle we refresh the RAM.
-- sd_cs <="0000"; --AUTOREFRESH
-- sd_ras <= '0';
-- sd_cas <= '0';
-- refreshcnt <= "111111111";
-- slot1_type<=refresh;
else
slot1_type<=idle;
END IF;
when ph2 =>
cache_fill_2 <='1'; -- slot 2
when ph3 =>
cache_fill_2 <='1'; -- slot 2
when ph4 =>
sdaddr <= '0'&'0' & '1' & '0' & casaddr(9 downto 1);--auto precharge
ba <= casaddr(24 downto 23);
sd_cs <= cas_sd_cs;
IF cas_sd_we='0' THEN
dqm <= cas_dqm;
END IF;
sd_ras <= cas_sd_ras;
sd_cas <= cas_sd_cas;
sd_we <= cas_sd_we;
writebuffer_hold<='0'; -- Indicate to WriteBuffer that it's safe to accept the next write.
when ph8 =>
cache_fill_1<='1';
when ph9 =>
cache_fill_1<='1';
-- Access slot 2, RAS
cas_sd_cs <= "1110";
cas_sd_ras <= '1';
cas_sd_cas <= '1';
cas_sd_we <= '1';
slot2_type<=idle;
if refresh_pending='0' and slot1_type/=refresh then
IF writebuffer_req='1' and writebufferAddr(24 downto 23)/="00" -- Reserve bank 0 for slot 1
and (slot1_type=idle or slot1_bank/=writebufferAddr(24 downto 23))
then
-- We only yeild to the OSD CPU if it's both cycle-starved and ready to go.
slot2_type<=cpu_writecache;
sdaddr <= writebufferAddr(22 downto 10);
ba <= writebufferAddr(24 downto 23);
slot2_bank <= writebufferAddr(24 downto 23);
cas_dqm <= writebuffer_dqm;
sd_cs <= "1110"; --ACTIVE
sd_ras <= '0';
casaddr <= writebufferAddr(24 downto 1)&'0';
cas_sd_we <= '0';
-- datain <= writebufferWR;
writebufferWR_reg <= writebufferWR;
cas_sd_cas <= '0';
writebuffer_hold<='1'; -- Let the write buffer know we're about to write.
-- Request from read cache
ELSIF cache_req='1' and cpuAddr(24 downto 23)/="00" -- Reserve bank 0 for slot 1
and (slot1_type=idle or slot1_bank/=cpuAddr_mangled(24 downto 23))
then
slot2_type<=cpu_readcache;
sdaddr <= cpuAddr_mangled(22 downto 10);
ba <= cpuAddr_mangled(24 downto 23);
slot2_bank <= cpuAddr_mangled(24 downto 23);
cas_dqm <= cpuU& cpuL;
sd_cs <= "1110"; --ACTIVE
sd_ras <= '0';
casaddr <= cpuAddr_mangled(24 downto 1)&'0';
cas_sd_we <= '1';
cas_sd_cas <= '0';
end if;
end if;
when ph10 =>
cache_fill_1<='1';
when ph11 =>
cache_fill_1<='1';
-- Slot 2 CAS
when ph12 =>
sdaddr <= '0'&'0' & '1' & '0' & casaddr(9 downto 1);--auto precharge
ba <= casaddr(24 downto 23);
sd_cs <= cas_sd_cs;
IF cas_sd_we='0' THEN
dqm <= cas_dqm;
END IF;
sd_ras <= cas_sd_ras;
sd_cas <= cas_sd_cas;
sd_we <= cas_sd_we;
writebuffer_hold<='0'; -- Indicate to WriteBuffer that it's safe to accept the next write.
when others =>
null;
end case;
end if;
END IF;
END process;
END;
-- Slot 1 Slot 2
-- ph0 (read) (Read 0 in sdata)
-- ph1 Slot alloc, RAS (read) Read0
-- ph2 ... (read) Read1
-- ph3 ... (write) Read2 (read3 in sdata)
-- ph4 CAS, write0 (write) Read3
-- ph5 write1 (write)
-- ph6 write2 (write)
-- ph7 write3 (read)
-- ph8 (read0 in sdata) (rd)
-- ph9 read0 in sdata_reg (rd) Slot alloc, RAS
-- ph10 read1 (read) ...
-- ph11 read2 (rd3 in sdata, wr) ...
-- ph12 read3 (write) CAS, write 0
-- ph13 (write) write1
-- ph14 (write) write2
-- ph15 (read) write3
| gpl-3.0 | e5ce9907a96bd10bf85e85dbc34731bb | 0.552311 | 3.081586 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_IN4_ALIGN_BLOCK.vhd | 1 | 4,079 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4_ALIGN_BLOCK
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
use work.centralRouter_package.all;
--! continuously aligns 4bit bit-stream to two commas
entity EPROC_IN4_ALIGN_BLOCK is
port (
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
bytes : in word10b_2array_type; -- 8b10b encoded
bytes_rdy : in std_logic;
------------
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
------------
busyOut : out std_logic
);
end EPROC_IN4_ALIGN_BLOCK;
architecture Behavioral of EPROC_IN4_ALIGN_BLOCK is
signal bytes_r : word10b_2array_type := ((others=>'0'),(others=>'0'));
signal send_state : std_logic := '0';
signal dataOUT_s : std_logic_vector(9 downto 0) := (others => '0');
signal dataOUTrdy_s, bytes_rdy_r : std_logic := '0';
signal byte_count : std_logic_vector(0 downto 0) := "0";
begin
-------------------------------------------------------------------------------------------
-- clock1
-- input register
-------------------------------------------------------------------------------------------
process(bitCLKx2, rst)
begin
if rst = '1' then
bytes_rdy_r <= '0';
elsif rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
bytes_rdy_r <= not bytes_rdy_r;
else
bytes_rdy_r <= '0';
end if;
end if;
end process;
--
input_latch: process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
bytes_r <= bytes;
end if;
end if;
end process;
--
--
process(bitCLKx2, rst)
begin
if rst = '1' then
send_state <= '0';
elsif rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
send_state <= '1';
else
if byte_count = "1" then
send_state <= '0';
end if;
end if;
end if;
end process;
--
process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if send_state = '1' then
byte_count <= byte_count + 1;
else
byte_count <= "0";
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- clock2
--
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if rising_edge(bitCLKx4) then
if send_state = '1' then
dataOUTrdy_s <= not dataOUTrdy_s;
else
dataOUTrdy_s <= '0';
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------------
out_select_proc: process(byte_count, bytes_r)
begin
case (byte_count) is
when "0" => dataOUT_s <= bytes_r(0);
when "1" => dataOUT_s <= bytes_r(1);
when others =>
end case;
end process;
--
-------------------------------------------------------------------------------------------
-- dataOUT_s (@bitCLKx4) & dataOUTrdy_s (@bitCLKx4, 2nd clock) can be used when
-- decoder is moved up
-------------------------------------------------------------------------------------------
dec_8b10: entity work.dec_8b10_wrap
port map(
RESET => rst,
RBYTECLK => bitCLKx4,
ABCDEIFGHJ_IN => dataOUT_s,
HGFEDCBA => dataOUT(7 downto 0),
ISK => dataOUT(9 downto 8),
BUSY => busyOut
);
--
dataOUTrdy <= dataOUTrdy_s;
--
end Behavioral;
| gpl-3.0 | 94013d9efc0414caea5e80f205167052 | 0.420691 | 4.018719 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Filter_Bank/filter_bank_imp.vhd | 1 | 1,899 | --------------------------------------------------------------------------------------------------
-- Filter Bank Implementation
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
use work.filter_bank_pkg.all;
--This module is a test-bench for simulating the fir filter
entity filter_bank_imp is
port( clk0 : in std_logic;
clk1 : in std_logic;
clk2 : in std_logic;
clk3 : in std_logic;
rst : in std_logic;
x : in sig;
y : out sig);
end filter_bank_imp;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture imp of filter_bank_imp is
begin
--Instantiate unit under test
uut : entity work.filter_bank(behave)
generic map(analysis_low => PR_ANALYSIS_LOW,
analysis_high => PR_ANALYSIS_HIGH,
synthesis_low => PR_SYNTHESIS_LOW,
synthesis_high => PR_SYNTHESIS_HIGH)
port map( clk0 => clk0,
clk1 => clk1,
clk2 => clk2,
clk3 => clk3,
rst => rst,
x => x,
y => y);
end imp;
| mit | 82dfd122621fe688ee7be49fe3c72a34 | 0.318589 | 5.668657 | false | false | false | false |
adelapie/noekeon | tb_gamma.vhd | 5 | 3,100 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_gamma IS
END tb_gamma;
ARCHITECTURE behavior OF tb_gamma IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT gamma
PORT(a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: gamma PORT MAP (
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
a_0_in <= X"C5B032AD";
a_1_in <= X"3E48160D";
a_2_in <= X"8C9A3EF5";
a_3_in <= X"AF2DFC9F";
wait for clk_period;
assert a_0_out = X"AB2DED92"
report "GAMMA ERROR (a_0)" severity FAILURE;
assert a_1_out = X"5C481D1D"
report "GAMMA ERROR (a_1)" severity FAILURE;
assert a_2_out = X"8407F1CF"
report "GAMMA ERROR (a_2)" severity FAILURE;
assert a_3_out = X"C9B824A8"
report "GAMMA ERROR (a_3)" severity FAILURE;
wait;
end process;
END;
| gpl-3.0 | 2a59889e386059b0bbd6c66b9352967c | 0.594516 | 3.144016 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/testbench/tb_read_csv.vhd | 1 | 2,155 | --------------------------------------------------------------------------------------------------
-- file reader for testbenches
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package tb_read_csv_pkg is
component tb_read_csv is
generic( FILENAME : string := "temp.csv");
port( clk : in std_logic;
data : out std_logic_vector);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
-- This entity reads the contents of a csv file to output a signal. Only one signal per file.
entity tb_read_csv is
generic( -- The name of the file to write the data to.
FILENAME : string := "temp.csv");
port( -- the clock synchronous with data
clk : in std_logic;
-- This signal will be written to a file on each rising clock edge
data : out std_logic_vector);
-- TODO: Add a end-of-file flag.
end tb_read_csv;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of tb_read_csv is
file input: text open read_mode is FILENAME;
begin
writer : process
variable L: line;
variable d: std_logic_vector(data'range) := (others => '0');
begin
wait until rising_edge(clk);
readline(input, L);
hread(L, d);
data <= d;
end process;
end behave; | mit | c530fc12b70b1aed65db16a523414969 | 0.384687 | 5.568475 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Filter_Bank/tb_decomposition.vhd | 1 | 3,367 | --------------------------------------------------------------------------------------------------
-- Decimator Testbench
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.tb_read_csv_pkg.all;
use work.tb_write_csv_pkg.all;
use work.dsp_pkg.all;
use work.decomposition_pkg.all;
--This module is a test-bench for simulating the fir filter
entity tb_decomposition is
end tb_decomposition;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture sim of tb_decomposition is
constant INPUT_FILE : string
:= "X:\Education\Masters Thesis\matlab\fir_filters\chirp.csv";
constant OUTPUT_FILE1: string
:= "X:\Education\Masters Thesis\matlab\fir_filters\chirp_decomp_low.csv";
constant OUTPUT_FILE2: string
:= "X:\Education\Masters Thesis\matlab\fir_filters\chirp_decomp_high.csv";
signal rst : std_logic := '0';
signal clk_10ns : std_logic := '0';
signal clk_20ns : std_logic := '0';
signal sig_in : sig := (others => '0');
signal sig_out_low : sig := (others => '0');
signal sig_out_high : sig := (others => '0');
begin
--Instantiate clock generator
clk1 : tb_clockgen
generic map(PERIOD => 10ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_10ns);
clk2 : tb_clockgen
generic map(PERIOD => 20ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_20ns);
--Instantiate file reader
reader : tb_read_csv
generic map(FILENAME => INPUT_FILE)
port map( clk => clk_10ns,
sig(data) => sig_in);
--Instantiate unit under test
uut : entity work.decomposition(behave)
generic map(low_pass => PR_ANALYSIS_LOW,
high_pass => PR_ANALYSIS_HIGH)
port map( clk_low => clk_20ns,
clk_high => clk_10ns,
rst => rst,
x => sig_in,
y_low => sig_out_low,
y_high => sig_out_high);
--Instantiate a file writer
writer1 : tb_write_csv
generic map(FILENAME => OUTPUT_FILE1)
port map( clk => clk_20ns,
data => std_logic_vector(sig_out_low));
--Instantiate a file writer
writer2 : tb_write_csv
generic map(FILENAME => OUTPUT_FILE2)
port map( clk => clk_20ns,
data => std_logic_vector(sig_out_high));
--Main Process
--TODO: Add a check for end of file, once reached terminate simulation.
main: process
begin
rst <= '1';
wait for 16ns;
rst <= '0';
wait;
end process;
end sim;
| mit | a6ea4e95b619957fb34b997b1119e2bb | 0.447282 | 4.407068 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/readout/FIFO2UDP.vhd | 1 | 18,337 | ----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL - Michigan
-- Engineer: Panagiotis Gkountoumis & Reid Pinkham & Paris Moschovakos
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Panagiotis Gkountoumis & Reid Pinkham & Paris Moschovakos
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Changelog:
-- 23.07.2016 Output signal "sending" to hold packet_formation from issuing new
-- packets (Paris)
-- 26.07.2016 Increased the size of the FIFO to 2048 in order to be able to handle
-- jumbo UDP frames. (Paris)
-- 22.08.2016 Re-wrote the main logic into a single state machine to fix the freezing
-- bug. (Reid Pinkham)
-- 26.02.2016 Moved to a global clock domain @125MHz (Paris)
--
----------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity FIFO2UDP is
Port (
clk_125 : in std_logic;
destinationIP : in std_logic_vector(31 downto 0);
daq_data_in : in std_logic_vector(15 downto 0);
fifo_data_out : out std_logic_vector (7 downto 0);
udp_txi : out udp_tx_type;
udp_tx_start : out std_logic;
re_out : out std_logic;
control : out std_logic;
UDPDone : out std_logic;
udp_tx_data_out_ready : in std_logic;
wr_en : in std_logic;
end_packet : in std_logic;
global_reset : in std_logic;
packet_length_in : in std_logic_vector(11 downto 0);
reset_DAQ_FIFO : in std_logic;
confReply_packet : in std_logic;
vmmID : in std_logic_vector(2 downto 0);
trigger_out : out std_logic;
count_o : out std_logic_vector(3 downto 0);
faifouki : out std_logic
);
end FIFO2UDP;
architecture Behavioral of FIFO2UDP is
signal count : unsigned(3 downto 0) := x"0";
signal i : integer := 0;
signal count_length : unsigned(15 downto 0) := x"0000";
signal daq_fifo_re : std_logic := '0';
signal fifo_empty_UDP : std_logic := '0';
signal fifo_full_UDP : std_logic := '0';
signal prog_fifo_empty : std_logic := '0';
signal daq_out : std_logic_vector(255 downto 0);
signal data_out : std_logic_vector(7 downto 0) := x"00";
signal data_out_valid : std_logic := '0';
signal packet_length : unsigned(15 downto 0) := x"0000";
signal data_out_last : std_logic := '0';
signal end_packet_synced : std_logic := '0';
signal udp_tx_start_int : std_logic := '0';
signal wr_en_int : std_logic := '0';
signal fifo_len_wr_en : std_logic := '0';
signal fifo_len_rd_en : std_logic := '0';
signal packet_len_r : std_logic_vector(11 downto 0);
signal fifo_empty_len : std_logic;
signal state : std_logic := '0';
signal is_trailer : integer := 0;
signal temp_buffer : std_logic_vector(63 downto 0) := (others=> '0');
signal daq_data_out : std_logic_vector(7 downto 0) := x"00";
signal vmmID_i : std_logic_vector(2 downto 0);
signal trigger : std_logic;
signal len_cnt : unsigned(7 downto 0) := "00000000";
signal rst_fifo : std_logic := '0';
-- attribute mark_debug : string;
-- attribute mark_debug of prog_fifo_empty : signal is "true";
-- attribute mark_debug of fifo_empty_UDP : signal is "true";
-- attribute mark_debug of daq_fifo_re : signal is "true";
-- attribute mark_debug of data_out_last : signal is "true";
-- attribute mark_debug of data_out : signal is "true";
-- attribute mark_debug of data_out_valid : signal is "true";
-- attribute mark_debug of udp_tx_data_out_ready : signal is "true";
-- attribute mark_debug of daq_data_out : signal is "true";
-- attribute mark_debug of udp_tx_start : signal is "true";
-- attribute mark_debug of end_packet_synced : signal is "true";
-- attribute mark_debug of i : signal is "true";
-- attribute mark_debug of packet_length : signal is "true";
-- attribute mark_debug of count : signal is "true";
-- attribute mark_debug of count_length : signal is "true";
-- attribute mark_debug of wr_en_int : signal is "true";
-- attribute mark_debug of fifo_full_UDP : signal is "true";
-- attribute mark_debug of fifo_empty_len : signal is "true";
-- attribute mark_debug of wr_en : signal is "true";
-- attribute mark_debug of packet_length_in : signal is "true";
-- attribute mark_debug of vmmID_i : signal is "true";
-- attribute mark_debug of trigger : signal is "true";
-- attribute mark_debug of len_cnt : signal is "true";
-- attribute mark_debug of fifo_len_wr_en : signal is "true";
-- attribute mark_debug of fifo_len_rd_en : signal is "true";
-- attribute mark_debug of packet_len_r : signal is "true";
component readout_fifo is
port(
clk : in std_logic;
srst : in std_logic;
din : in std_logic_vector(15 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(7 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
component packet_len_fifo
port (
clk : in std_logic;
srst : in std_logic;
din : in std_logic_vector(11 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(11 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
component ila_0
PORT (
clk : in std_logic;
probe0 : in std_logic_vector(255 DOWNTO 0);
probe1 : in std_logic);
end component;
begin
-- process ot trigger ILAs
trigger_proc: process (clk_125, vmmID_i, data_out_last)
begin
if rising_edge(clk_125) then
if (vmmID_i = "000" and data_out_last = '1') then
trigger <= '1';
else
trigger <= '0';
end if;
end if;
end process;
daq_FIFO_instance: readout_fifo
port map(
clk => clk_125,
srst => rst_fifo,
din => daq_data_in,
wr_en => wr_en,
rd_en => daq_fifo_re,
dout => daq_data_out,
full => fifo_full_UDP,
empty => fifo_empty_UDP
);
packet_len_fifo_instance: packet_len_fifo
port map (
clk => clk_125,
srst => rst_fifo,
din => packet_length_in,
wr_en => fifo_len_wr_en,
rd_en => fifo_len_rd_en,
dout => packet_len_r,
full => open,
empty => fifo_empty_len
);
fill_packet_len: process (clk_125, state) -- small state machine to write packet_len to fifo
begin
if rising_edge(clk_125) then
case state is
when '0' => -- idle
if (end_packet_synced = '1') then -- latch the packet_len into the fifo
fifo_len_wr_en <= '1';
state <= '1';
else
state <= '0';
end if;
when '1' => -- st1
if (end_packet_synced = '0') then-- prevent a double latch
state <= '0';
else
state <= '1';
end if;
fifo_len_wr_en <= '0';
when others =>
state <= '0';
end case;
end if;
end process;
process (clk_125, fifo_len_rd_en)
begin
if rising_edge(clk_125) then
if fifo_len_rd_en = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end process;
UDPDone_proc: process (clk_125)
begin
if rising_edge(clk_125) then
if fifo_empty_UDP = '1' and fifo_empty_len = '1' then -- IF Statement to inidcate when packets have been sent
UDPDone <= '1';
else
UDPDone <= '0';
end if;
end if;
end process;
process (clk_125, count, udp_tx_data_out_ready, fifo_empty_UDP, prog_fifo_empty, data_out_valid)
begin
if rising_edge(clk_125) then
if global_reset = '1' then -- IF statement to read from length fifo and initiate a packet send
data_out_last <= '0';
data_out_valid <= '0';
udp_tx_start_int <= '0';
fifo_len_rd_en <= '0';
daq_fifo_re <= '0';
count <= x"0";
else
case count is
when x"0" =>
if fifo_empty_len = '0' then -- Send packets until FIFO is empty
fifo_len_rd_en <= '1';
count <= x"1";
end if;
when x"1" => -- state to allow fifo time to respond
count <= x"2";
fifo_len_rd_en <= '0';
when x"2" =>
packet_length <= resize(unsigned("0000" & packet_len_r) * 2 + 4, 16);
count_length <= resize(unsigned("0000" & packet_len_r) * 2, 16);
fifo_len_rd_en <= '0';
count <= x"3";
when x"3" =>
data_out_last <= '0';
data_out_valid <= '0';
data_out <= (others => '0');
udp_tx_start_int <= '0';
if(confReply_packet = '1')then
udp_txi.hdr.dst_port <= x"E887";
else
udp_txi.hdr.dst_port <= x"1778";
end if;
count <= x"4";
when x"4" =>
udp_tx_start_int <= '1';
udp_txi.hdr.dst_ip_addr <= destinationIP; -- set a generic ip adrress (192.168.0.255)
udp_txi.hdr.src_port <= x"19CB"; -- set src and dst ports
udp_txi.hdr.data_length <= std_logic_vector(packet_length); -- defined to be 16 bits in UDP
daq_fifo_re <= '0';
udp_txi.hdr.checksum <= x"0000";
count <= x"5";
when x"5" =>
if udp_tx_data_out_ready = '1' then
udp_tx_start_int <= '0';
daq_fifo_re <= '1';
count <= x"6";
end if;
when x"6" =>
if udp_tx_data_out_ready = '1' then
count_length <= count_length - 1;
udp_tx_start_int <= '0';
data_out <= daq_data_out;
count <= x"7";
end if;
when x"7" =>
if udp_tx_data_out_ready = '1' then
if count_length = 1 then
daq_fifo_re <= '0';
elsif count_length = 0 then
count <= x"8";
daq_fifo_re <= '0';
else
daq_fifo_re <= '1';
end if;
count_length <= count_length - 1;
udp_tx_start_int <= '0';
data_out_valid <= '1';
control <= '0';
data_out_last <= '0';
data_out <= daq_data_out;
else
daq_fifo_re <= '0';
end if;
when x"8" =>
if udp_tx_data_out_ready = '1' then
daq_fifo_re <= '0';
udp_tx_start_int <= '0';
data_out_last <= '0';
data_out <= x"ff";
count <= x"9";
end if;
when x"9" =>
if udp_tx_data_out_ready = '1' then
daq_fifo_re <= '0';
udp_tx_start_int <= '0';
data_out_last <= '0';
data_out <= x"ff";
count <= x"a";
end if;
when x"a" =>
if udp_tx_data_out_ready = '1' then
daq_fifo_re <= '0';
udp_tx_start_int <= '0';
data_out_last <= '0';
data_out <= x"ff";
count <= x"b";
end if;
when x"b" =>
if udp_tx_data_out_ready = '1' then
daq_fifo_re <= '0';
udp_tx_start_int <= '0';
data_out_last <= '1';
data_out <= x"ff";
count <= x"c";
end if;
when x"c" =>
data_out_last <= '0';
data_out_valid <= '0';
data_out <= (others => '0');
udp_tx_start_int <= '0';
count <= x"d";
when x"d" =>
count <= x"0";
count_length <= x"0000";
data_out_last <= '0';
data_out_valid <= '0';
udp_tx_start_int <= '0';
when others =>
count <= x"0";
end case;
end if;
end if;
end process;
vmmID_i <= vmmID; -- assign external signal to internal
udp_tx_start <= udp_tx_start_int;
udp_txi.data.data_out_last <= data_out_last;
udp_txi.data.data_out_valid <= data_out_valid ;
udp_txi.data.data_out <= data_out;
wr_en_int <= wr_en;
end_packet_synced <= end_packet;
rst_fifo <= reset_DAQ_FIFO or global_reset;
trigger_out <= trigger;
count_o <= std_logic_vector(count);
faifouki <= fifo_empty_len;
--ila_daq_send : ila_0
-- port map
-- (
-- clk => clk_125,
-- probe0 => daq_out,
-- probe1 => udp_tx_data_out_ready
-- );
daq_out(0) <= end_packet_synced;
daq_out(1) <= fifo_empty_UDP;
daq_out(2) <= daq_fifo_re;
daq_out(3) <= data_out_valid;
daq_out(4) <= data_out_last;
daq_out(12 downto 5) <= data_out;
daq_out(16 downto 13) <= std_logic_vector(count);
daq_out(38 downto 17) <= (others => '0');
daq_out(39) <= udp_tx_start_int;
daq_out(40) <= '0'; --udp_tx_data_out_ready;
daq_out(48 downto 41) <= daq_data_out;
daq_out(112 downto 49) <= (others => '0');
daq_out(113) <= '0';
daq_out(129 downto 114) <= std_logic_vector(packet_length);
daq_out(145 downto 130) <= std_logic_vector(count_length);
daq_out(157 downto 146) <= packet_len_r;
daq_out(221 downto 158) <= (others => '0');
daq_out(222) <= wr_en_int;
daq_out(223) <= wr_en;
daq_out(235 downto 224) <= packet_length_in;
daq_out(236) <= udp_tx_data_out_ready;
daq_out(237) <= fifo_len_wr_en;
daq_out(238) <= fifo_len_rd_en;
daq_out(239) <= fifo_empty_len;
daq_out(240) <= fifo_full_UDP;
daq_out(243 downto 241) <= vmmID_i;
daq_out(244) <= trigger;
daq_out(252 downto 245) <= std_logic_vector(len_cnt);
daq_out(255 downto 253) <= (others => '0');
end Behavioral; | gpl-3.0 | 8fe3aac7967c7d23725de0735f855d07 | 0.441294 | 3.90315 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4088/EPATH_FIFO_WRAP.vhd | 1 | 3,171 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 09/14/2014
--! Module Name: EPATH_FIFO_WRAP
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
--! EPATH FIFO 16 bit wide, 1K deep
entity EPATH_FIFO_WRAP is
port (
rst : in std_logic;
fifoFlush : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(15 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(15 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
rd_data_count : out std_logic_vector(9 downto 0);
prog_full : out std_logic
);
end EPATH_FIFO_WRAP;
architecture Behavioral of EPATH_FIFO_WRAP is
----------------------------------
----------------------------------
component EPATH_FIFO -- IP
port (
wr_clk : in std_logic;
wr_rst : in std_logic;
rd_clk : in std_logic;
rd_rst : in std_logic;
din : in std_logic_vector(15 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(15 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
rd_data_count : out std_logic_vector(9 downto 0);
prog_full : out std_logic;
prog_empty : out std_logic;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0)
);
end component;
----------------------------------
----------------------------------
signal rd_en_s, wr_en_s : std_logic;
signal prog_full_s, full_s, empty_s, prog_empty_s : std_logic;
signal rst_state : std_logic;
begin
--
rd_en_s <= rd_en and (not rst_state);
wr_en_s <= wr_en and (not rst_state);
--
EPATH_FIFO_INST: EPATH_FIFO
PORT MAP (
wr_clk => wr_clk,
wr_rst => fifoFlush,
rd_clk => rd_clk,
rd_rst => fifoFlush,
din => din,
wr_en => wr_en_s,
rd_en => rd_en_s,
dout => dout,
full => full_s,
almost_full => open, --almost_full,
empty => empty_s,
rd_data_count => rd_data_count, -- behavioral simulation only, optimized out
prog_full => prog_full_s,
prog_empty => prog_empty_s,
prog_full_thresh => std_logic_vector(to_unsigned(512, 10)),
prog_empty_thresh => std_logic_vector(to_unsigned(1010, 10))
);
--
rst_state <= rst or (full_s and empty_s);
--
full <= full_s; -- wr_clk domain
empty <= empty_s;-- rd_clk domain
--
process(rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
prog_full <= prog_full_s and (not rst_state);
end if;
end process;
--
process(wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
almost_full <= not prog_empty_s;
end if;
end process;
--
end Behavioral;
| gpl-3.0 | 3156afc645f184928576c52cc0527f5f | 0.512457 | 3.148957 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/UDP_ICMP_Complete_nomac.vhd | 1 | 18,032 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:38:49 06/13/2011
-- Design Name:
-- Module Name: UDP_ICMP_Complete_nomac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Revision 0.03 - Added mac_tx_tfirst
-- Additional Comments: Added ICMP ping functionality (CB)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity UDP_ICMP_Complete_nomac is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- ICMP RX signals
icmp_rx_start : out std_logic;
icmp_rxo : out icmp_rx_type;
-- IP RX signals
ip_rx_hdr : out ipv4_rx_header_type;
-- system signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
fifo_init : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in udp_control_type;
-- status signals
arp_pkt_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
ip_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end UDP_ICMP_Complete_nomac;
architecture structural of UDP_ICMP_Complete_nomac is
------------------------------------------------------------------------------
-- Component Declaration for UDP TX
------------------------------------------------------------------------------
COMPONENT UDP_TX
PORT(
-- UDP Layer signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
-- IP layer TX signals
ip_tx_start : out std_logic;
ip_tx : out ipv4_tx_type; -- IP tx cxns
ip_tx_result : in std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : in std_logic -- indicates IP TX is ready to take data
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for UDP RX
------------------------------------------------------------------------------
COMPONENT UDP_RX
PORT(
-- UDP Layer signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- system signals
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- IP layer RX signals
ip_rx_start : in std_logic; -- indicates receipt of ip header
ip_rx : in ipv4_rx_type
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for ICMP TX
------------------------------------------------------------------------------
COMPONENT ICMP_TX
PORT (
-- ICMP layer signals
icmp_tx_start : in std_logic; -- indicates req to tx ICMP
icmp_txi : in icmp_tx_type; -- icmp tx cxns
icmp_tx_data_out_ready : out std_logic; -- indicates icmp_tx is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
icmp_tx_is_idle : out STD_LOGIC;
-- IP layer TX signals
ip_tx_start : out std_logic;
ip_tx : out ipv4_tx_type; -- IP tx cxns
ip_tx_result : in std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : in std_logic -- indicates IP TX is ready to take data
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for ICMP RX
------------------------------------------------------------------------------
COMPONENT ICMP_RX
PORT (
-- ICMP Layer signals
icmp_rx_start : out std_logic; -- indicates receipt of icmp header
icmp_rxo : out icmp_rx_type;
-- system signals
clk : in std_logic;
reset : in std_logic;
-- IP layer RX signals
ip_rx_start : in std_logic; -- indicates receipt of ip header
ip_rx : in ipv4_rx_type
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for UDP_TX/ICMP_TX Multiplexer
------------------------------------------------------------------------------
COMPONENT icmp_udp_mux
PORT (
-- from ping reply handler
sel_icmp : in std_logic;
-- from ICMP_TX
ip_tx_start_icmp : in std_logic;
ip_tx_icmp : in ipv4_tx_type;
-- from UDP_TX
ip_tx_start_udp : in std_logic;
ip_tx_udp : in ipv4_tx_type;
-- to IP Layer
ip_tx_start_IP : out std_logic;
ip_tx_IP : out ipv4_tx_type
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for the Ping Reply Handling Module
------------------------------------------------------------------------------
COMPONENT ping_reply_processor
PORT (
-- ICMP RX interface
icmp_rx_start : in std_logic;
icmp_rxi : in icmp_rx_type;
-- system signals
tx_clk : in std_logic;
rx_clk : in std_logic;
reset : in std_logic;
fifo_init : in std_logic;
-- ICMP/UDP mux interface
sel_icmp : out std_logic;
-- ICMP TX interface
icmp_tx_start : out std_logic;
icmp_tx_ready : in std_logic;
icmp_txo : out icmp_tx_type;
icmp_tx_is_idle : in std_logic
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for the IP layer
------------------------------------------------------------------------------
component IP_complete_nomac
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end component;
-- IP TX connectivity
signal ip_tx_int : ipv4_tx_type;
signal ip_tx_start_int : std_logic;
signal ip_tx_int_icmp : ipv4_tx_type;
signal ip_tx_start_int_icmp : std_logic;
signal ip_tx_int_udp : ipv4_tx_type;
signal ip_tx_start_int_udp : std_logic;
signal ip_tx_result_int : std_logic_vector (1 downto 0);
signal ip_tx_data_out_ready_int : std_logic;
signal icmp_rx_start_int : std_logic;
signal icmp_rxo_int : icmp_rx_type;
signal icmp_tx_is_idle : std_logic;
-- IP RX connectivity
signal ip_rx_int : ipv4_rx_type;
signal ip_rx_start_int : std_logic := '0';
-- ICMP_TX / Ping Reply Handler connectivity
signal icmp_tx_start : std_logic := '0';
signal icmp_tx_data_out_ready : std_logic := '0';
signal sel_icmp : std_logic := '0';
signal icmp_tx_int : icmp_tx_type;
begin
-- output followers
ip_rx_hdr <= ip_rx_int.hdr;
-- Instantiate the UDP TX block
udp_tx_block: UDP_TX
PORT MAP (
-- UDP Layer signals
udp_tx_start => udp_tx_start,
udp_txi => udp_txi,
udp_tx_result => udp_tx_result,
udp_tx_data_out_ready => udp_tx_data_out_ready,
-- system signals
clk => tx_clk,
reset => reset,
-- IP layer TX signals
ip_tx_start => ip_tx_start_int_udp,
ip_tx => ip_tx_int_udp,
ip_tx_result => ip_tx_result_int,
ip_tx_data_out_ready => ip_tx_data_out_ready_int
);
-- Instantiate the UDP RX block
udp_rx_block: UDP_RX
PORT MAP (
-- UDP Layer signals
udp_rxo => udp_rxo,
udp_rx_start => udp_rx_start,
-- system signals
clk => rx_clk,
reset => reset,
-- IP layer RX signals
ip_rx_start => ip_rx_start_int,
ip_rx => ip_rx_int
);
-- Instantiate the ICMP TX block
icmp_tx_block: ICMP_TX
PORT MAP(
-- ICMP layer signals
icmp_tx_start => icmp_tx_start,
icmp_txi => icmp_tx_int,
icmp_tx_data_out_ready => icmp_tx_data_out_ready,
-- system signals
clk => tx_clk,
reset => reset,
icmp_tx_is_idle => icmp_tx_is_idle,
-- IP layer TX signals
ip_tx_start => ip_tx_start_int_icmp,
ip_tx => ip_tx_int_icmp,
ip_tx_result => ip_tx_result_int,
ip_tx_data_out_ready => ip_tx_data_out_ready_int
);
-- Instantiate the ICMP RX block
icmp_rx_block: ICMP_RX
PORT MAP(
-- ICMP Layer signals
icmp_rx_start => icmp_rx_start_int,
icmp_rxo => icmp_rxo_int,
-- system signals
clk => rx_clk,
reset => reset,
-- IP layer RX signals
ip_rx_start => ip_rx_start_int,
ip_rx => ip_rx_int
);
-- Instantiate the UDP_TX/ICMP_TX multiplexer
mux_block: icmp_udp_mux
PORT MAP(
-- from ping reply handler
sel_icmp => sel_icmp,
-- from ICMP_TX
ip_tx_start_icmp => ip_tx_start_int_icmp,
ip_tx_icmp => ip_tx_int_icmp,
-- from UDP_TX
ip_tx_start_udp => ip_tx_start_int_udp,
ip_tx_udp => ip_tx_int_udp,
-- to IP Layer
ip_tx_start_IP => ip_tx_start_int,
ip_tx_IP => ip_tx_int
);
-- Instantiate the Ping Reply Handler
ping_reply_block: ping_reply_processor
PORT MAP(
-- ICMP RX interface
icmp_rx_start => icmp_rx_start_int,
icmp_rxi => icmp_rxo_int,
-- system signals
tx_clk => tx_clk,
rx_clk => rx_clk,
reset => reset,
fifo_init => fifo_init,
-- ICMP/UDP mux interface
sel_icmp => sel_icmp,
-- ICMP TX interface
icmp_tx_start => icmp_tx_start,
icmp_tx_ready => icmp_tx_data_out_ready,
icmp_txo => icmp_tx_int,
icmp_tx_is_idle => icmp_tx_is_idle
);
------------------------------------------------------------------------------
-- Instantiate the IP layer
------------------------------------------------------------------------------
IP_block : IP_complete_nomac
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES)
PORT MAP (
-- IP interface
ip_tx_start => ip_tx_start_int,
ip_tx => ip_tx_int,
ip_tx_result => ip_tx_result_int,
ip_tx_data_out_ready => ip_tx_data_out_ready_int,
ip_rx_start => ip_rx_start_int,
ip_rx => ip_rx_int,
-- System interface
rx_clk => rx_clk,
tx_clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
control => control.ip_controls,
-- status signals
arp_pkt_count => arp_pkt_count,
ip_pkt_count => ip_pkt_count,
-- MAC Transmitter
mac_tx_tdata => mac_tx_tdata,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tready => mac_tx_tready,
mac_tx_tfirst => mac_tx_tfirst,
mac_tx_tlast => mac_tx_tlast,
-- MAC Receiver
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tlast => mac_rx_tlast
);
icmp_rx_start <= icmp_rx_start_int;
icmp_rxo <= icmp_rxo_int;
end structural;
| gpl-3.0 | e9572cb8f5132dd4500814a857b43340 | 0.446429 | 4.001775 | false | false | false | false |
adelapie/noekeon | noekeon.vhd | 2 | 7,144 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- This is an iterative implementation of the NOEKEON block
-- cipher relying on the direct mode of the cipher. This means that
-- key schedule is not performed.
entity noekeon is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end noekeon;
architecture Behavioral of noekeon is
component round_f is
port(enc : in std_logic;
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_gen is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_out : out std_logic_vector(7 downto 0));
end component;
component output_trans is
port(clk : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
signal rc_s : std_logic_vector(7 downto 0);
signal rc_ext_s : std_logic_vector(31 downto 0);
signal a_0_in_s : std_logic_vector(31 downto 0);
signal a_1_in_s : std_logic_vector(31 downto 0);
signal a_2_in_s : std_logic_vector(31 downto 0);
signal a_3_in_s : std_logic_vector(31 downto 0);
signal out_t_a_0_in_s : std_logic_vector(31 downto 0);
signal out_t_a_1_in_s : std_logic_vector(31 downto 0);
signal out_t_a_2_in_s : std_logic_vector(31 downto 0);
signal out_t_a_3_in_s : std_logic_vector(31 downto 0);
signal a_0_out_s : std_logic_vector(31 downto 0);
signal a_1_out_s : std_logic_vector(31 downto 0);
signal a_2_out_s : std_logic_vector(31 downto 0);
signal a_3_out_s : std_logic_vector(31 downto 0);
signal k_0_d_s : std_logic_vector(31 downto 0);
signal k_1_d_s : std_logic_vector(31 downto 0);
signal k_2_d_s : std_logic_vector(31 downto 0);
signal k_3_d_s : std_logic_vector(31 downto 0);
signal k_0_mux_s : std_logic_vector(31 downto 0);
signal k_1_mux_s : std_logic_vector(31 downto 0);
signal k_2_mux_s : std_logic_vector(31 downto 0);
signal k_3_mux_s : std_logic_vector(31 downto 0);
begin
RC_GEN_0 : rc_gen port map (clk, rst, enc, rc_s);
rc_ext_s <= X"000000" & rc_s;
ROUND_F_0 : round_f port map (enc,
rc_ext_s,
a_0_in_s,
a_1_in_s,
a_2_in_s,
a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out_s,
a_1_out_s,
a_2_out_s,
a_3_out_s);
pr_noe: process(clk, rst, enc)
begin
if rising_edge(clk) then
if rst = '1' then
a_0_in_s <= a_0_in;
a_1_in_s <= a_1_in;
a_2_in_s <= a_2_in;
a_3_in_s <= a_3_in;
else
a_0_in_s <= a_0_out_s;
a_1_in_s <= a_1_out_s;
a_2_in_s <= a_2_out_s;
a_3_in_s <= a_3_out_s;
end if;
end if;
end process;
-- Key decryption as k' = theta(0, k)
-- This is the key required for decryption
-- in NOEKEON
THETA_DECRYPT_0 : theta port map (
k_0_in,
k_1_in,
k_2_in,
k_3_in,
(others => '0'),
(others => '0'),
(others => '0'),
(others => '0'),
k_0_d_s,
k_1_d_s,
k_2_d_s,
k_3_d_s);
-- These multiplexers select the key that is used
-- in each mode i.e. during decryption the key generated
-- as k' = theta(0, k) (THETA_DECRYPT_0) is utilized.
k_0_mux_s <= k_0_in when enc = '0' else k_0_d_s;
k_1_mux_s <= k_1_in when enc = '0' else k_1_d_s;
k_2_mux_s <= k_2_in when enc = '0' else k_2_d_s;
k_3_mux_s <= k_3_in when enc = '0' else k_3_d_s;
out_trans_pr: process(clk, rst, a_0_out_s, a_1_out_s, a_2_out_s, a_3_out_s)
begin
if rising_edge(clk) then
out_t_a_0_in_s <= a_0_out_s;
out_t_a_1_in_s <= a_1_out_s;
out_t_a_2_in_s <= a_2_out_s;
out_t_a_3_in_s <= a_3_out_s;
end if;
end process;
-- This component performs the last operation
-- with theta.
OUT_TRANS_0 : output_trans port map (clk, enc, rc_ext_s,
out_t_a_0_in_s,
out_t_a_1_in_s,
out_t_a_2_in_s,
out_t_a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out,
a_1_out,
a_2_out,
a_3_out);
end Behavioral;
| gpl-3.0 | 88010e59cc9e59265d7cf8d041d40055 | 0.600644 | 2.502277 | false | false | false | false |
adelapie/noekeon | tb_pi_1.vhd | 5 | 2,634 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_pi_1 IS
END tb_pi_1;
ARCHITECTURE behavior OF tb_pi_1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pi_1
PORT(
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pi_1 PORT MAP (
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
a_1_in <= X"a1abab3c";
a_2_in <= X"0232b23f";
a_3_in <= X"f000abbb";
wait for clk_period;
assert a_1_out = X"43575679"
report "PI1 ERROR (a_0)" severity FAILURE;
assert a_2_out = X"465647e0"
report "PI1 ERROR (a_1)" severity FAILURE;
assert a_3_out = X"c002aeef"
report "PI1 ERROR (a_2)" severity FAILURE;
wait;
end process;
END;
| gpl-3.0 | b0fab28e90bc291c700bef86c23c6a08 | 0.610858 | 3.188862 | false | false | false | false |
tdotu/ra | registerBlock.vhd | 1 | 1,674 | LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.numeric_std.all;
ENTITY registerBlock IS
GENERIC
(
regSize : integer
);
PORT
(
regWrite : IN std_logic;
read0 : IN std_logic_vector(4 downto 0);
read1 : IN std_logic_vector(4 downto 0);
write0 : IN std_logic_vector(4 downto 0);
input0 : IN std_logic_vector(regSize-1 downto 0);
output0 : OUT std_logic_vector(regSize-1 downto 0);
output1 : OUT std_logic_vector(regSize-1 downto 0)
);
END registerBlock;
ARCHITECTURE behavior OF registerBlock IS
COMPONENT reg IS
GENERIC
(
width : integer
);
PORT
(
clock : IN std_logic;
change : IN std_logic_vector(width-1 downto 0);
state : OUT std_logic_vector(width-1 downto 0)
);
END COMPONENT;
SUBTYPE outSignal IS std_logic_vector(regSize-1 downto 0);
TYPE outSignalArray IS ARRAY(integer RANGE 0 TO 31) OF outSignal;
SIGNAL outSignals : outSignalArray;
SIGNAL writeBit : std_logic_vector(31 downto 0);
BEGIN
output0 <= "00000000000000000000000000000100" WHEN read0 = std_logic_vector(to_unsigned(0, 5)) ELSE (OTHERS => 'Z');
output1 <= "00000000000000000000000000000100" WHEN read1 = std_logic_vector(to_unsigned(0, 5)) ELSE (OTHERS => 'Z');
gen0 : FOR X IN 1 TO 31 GENERATE
regx : reg GENERIC MAP (regSize) PORT MAP (writeBit(X), input0, outSignals(X));
output0 <= outSignals(X) WHEN read0 = std_logic_vector(to_unsigned(X, 5)) ELSE (OTHERS => 'Z');
output1 <= outSignals(X) WHEN read1 = std_logic_vector(to_unsigned(X, 5)) ELSE (OTHERS => 'Z');
writeBit(X) <= regWrite WHEN write0 = std_logic_vector(to_unsigned(X, 5)) ELSE '0';
END GENERATE gen0;
END behavior;
| gpl-3.0 | 3d8b45e57ee98311a4283a1657b2677b | 0.681601 | 3.088561 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Count_Gen/tb_count_gen.vhd | 1 | 1,826 | --------------------------------------------------------------------------------------------------
-- Count Generator Testbench
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.count_gen_pkg.all;
entity tb_count_gen is
end tb_count_gen;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture rtl of tb_count_gen is
signal clk : std_logic;
signal rst : std_logic;
signal en : std_logic;
signal count : integer;
begin
--Instantiate clock generator
clk_gen : tb_clockgen
generic map(PERIOD => 10ns,
DUTY_CYCLE => 0.50)
port map( clk => clk);
--Unit under test
uut : count_gen
generic map(INIT_VAL => 17,
STEP_VAL => 2)
port map( clk => clk,
rst => rst,
en => en,
count => count);
--main process
main : process
begin
rst <= '1';
en <= '0';
wait until falling_edge(clk);
rst <= '0';
wait for 50ns;
wait until falling_edge(clk);
en <= '1';
wait for 100ns;
wait until falling_edge(clk);
en <= '0';
wait;
end process;
end rtl;
| mit | 3aa9766dde24be6660d211e389702d74 | 0.349945 | 5.129213 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/readout/packet_formation.vhd | 1 | 23,094 | ----------------------------------------------------------------------------------
-- Company: NTU ATHENS - BNL
-- Engineer: Paris Moschovakos
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Paris Moschovakos
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 25.06.2016
-- Design Name:
-- Module Name: packet_formation.vhd - Behavioral
-- Project Name: MMFE8
-- Target Devices: Artix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2017.1
--
-- Changelog:
-- 22.08.2016 Changed readout trigger pulse from 125 to 100 ns long (Reid Pinkham)
-- 09.09.2016 Added two signals for ETR interconnection (Christos Bakalis)
-- 26.02.2016 Moved to a global clock domain @125MHz (Paris)
-- 06.04.2017 Hard setting latency to 300ns as configurable latency was moved to trigger module (Paris)
-- 25.04.2017 Added vmm_driver module. (Christos Bakalis)
-- 06.06.2017 Added ART header a handling (Paris)
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
use UNISIM.VComponents.all;
entity packet_formation is
Generic(is_mmfe8 : std_logic;
vmmReadoutMode : std_logic;
artEnabled : std_logic);
Port(
clk : in std_logic;
newCycle : in std_logic;
trigVmmRo : out std_logic;
vmmId : out std_logic_vector(2 downto 0);
vmmWord : in std_logic_vector(15 downto 0);
vmmWordReady : in std_logic;
vmmEventDone : in std_logic;
UDPDone : in std_logic;
pfBusy : out std_logic; -- Control signal to ETR
glBCID : in std_logic_vector(11 downto 0); -- glBCID counter from ETR
packLen : out std_logic_vector(11 downto 0);
dataout : out std_logic_vector(15 downto 0);
wrenable : out std_logic;
end_packet : out std_logic;
rd_ena_buff : out std_logic;
rst_l0 : out std_logic;
tr_hold : out std_logic;
reset : in std_logic;
rst_vmm : out std_logic;
linkHealth_bmsk : in std_logic_vector(8 downto 1);
rst_FIFO : out std_logic;
latency : in std_logic_vector(15 downto 0);
dbg_st_o : out std_logic_vector(4 downto 0);
trraw_synced125 : in std_logic;
vmmArtData125 : in std_logic_vector(5 downto 0);
vmmArtReady : in std_logic
);
end packet_formation;
architecture Behavioral of packet_formation is
signal artHeader : std_logic_vector(15 downto 0) := ( others => '0' );
signal header : std_logic_vector(63 downto 0) := ( others => '0' );
signal header_l0 : std_logic_vector(47 downto 0) := ( others => '0' );
signal vmmId_i : std_logic_vector(2 downto 0) := b"000";
signal globBcid : std_logic_vector(15 downto 0) := x"FFFF"; --( others => '0' );
signal precCnt : std_logic_vector(7 downto 0) := x"00"; --( others => '0' );
signal globBcid_i : std_logic_vector(15 downto 0);
signal globBCID_etr : std_logic_vector(11 downto 0) := (others => '0'); --globBCID counter as it is coming from ETR
signal eventCounter_i : unsigned(31 downto 0) := to_unsigned(0, 32);
signal wait_Cnt : integer range 0 to 31 := 0;
signal vmmId_cnt : integer range 0 to 7 := 0;
signal trigLatencyCnt : integer := 0;
signal trigLatency : integer := 140; -- 700ns (140x5ns)
signal pfBusy_i : std_logic := '0'; -- control signal to be sent to ETR
signal daqFIFO_wr_en_hdr : std_logic := '0';
signal daqFIFO_wr_en_drv : std_logic := '0';
signal sel_wrenable : std_logic := '0';
signal drv_enable : std_logic := '0';
signal drv_done : std_logic := '0';
signal daqFIFO_din : std_logic_vector(15 downto 0) := ( others => '0' );
signal triggerVmmReadout_i : std_logic := '0';
signal selectDataInput : std_logic_vector(2 downto 0) := (others => '0');
signal sel_cnt : unsigned(2 downto 0) := (others => '0');
signal vmmWord_i : std_logic_vector(15 downto 0) := ( others => '0' );
signal packLen_i : unsigned(11 downto 0) := x"000";
signal packLen_drv2pf_unsg : unsigned(11 downto 0) := x"000";
signal packLen_drv2pf : std_logic_vector(11 downto 0) := x"000";
signal packLen_cnt : unsigned(11 downto 0) := x"000";
signal end_packet_int : std_logic := '0';
signal artValid : std_logic := '0';
signal trraw_synced125_prev : std_logic := '0';
signal clearValid : std_logic := '0';
type stateType is (waitingForNewCycle, increaseCounter, waitForLatency, captureEventID, setEventID, sendHeaderStep1, sendHeaderStep2,
sendHeaderStep3, triggerVmmReadout, waitForData, sendVmmDataStep1, sendVmmDataStep2, formTrailer, sendTrailer, packetDone,
isUDPDone, isTriggerOff, S2, eventDone);
signal state : stateType;
-------------------- Debugging ------------------------------
signal probe0_out : std_logic_vector(132 downto 0);
signal probe1_out : std_logic_vector(200 downto 0);
signal debug_state : std_logic_vector(4 downto 0);
-----------------------------------------------------------------
---------------------- Debugging ------------------------------
-- attribute mark_debug : string;
-- attribute mark_debug of header : signal is "true";
-- attribute mark_debug of globBcid : signal is "true";
-- attribute mark_debug of globBcid_i : signal is "true";
-- attribute mark_debug of precCnt : signal is "true";
-- attribute mark_debug of vmmId_i : signal is "true";
-- attribute mark_debug of daqFIFO_din : signal is "true";
-- attribute mark_debug of vmmWord_i : signal is "true";
-- attribute mark_debug of packLen_i : signal is "true";
-- attribute mark_debug of packLen_cnt : signal is "true";
-- attribute mark_debug of end_packet_int : signal is "true";
-- attribute mark_debug of triggerVmmReadout_i : signal is "true";
-- attribute mark_debug of debug_state : signal is "true";
-- attribute mark_debug of artValid : signal is "true";
-- attribute mark_debug of trraw_synced125 : signal is "true";
-- attribute mark_debug of vmmArtReady : signal is "true";
component ila_pf
port (
clk : in std_logic;
probe0 : in std_logic_vector(132 downto 0);
probe1 : in std_logic_vector(200 downto 0)
);
end component;
component vio_0
port (
clk : in std_logic;
probe_out0 : out std_logic_vector ( 11 downto 0 )
);
end component;
component vmm_driver
port(
------------------------------------
------ General/PF Interface --------
clk : in std_logic;
drv_enable : in std_logic;
drv_done : out std_logic;
pack_len_drv : out std_logic_vector(11 downto 0);
------------------------------------
----- VMM_RO/FIFO2UDP Interface ----
wr_en_fifo2udp : out std_logic;
rd_en_buff : out std_logic;
vmmWordReady : in std_logic
);
end component;
-----------------------------------------------------------------
begin
packetCaptureProc: process(clk, newCycle, vmmEventDone, vmmWordReady, wait_Cnt, UDPDone)
begin
if rising_edge(clk) then
if reset = '1' then
debug_state <= "11111";
eventCounter_i <= to_unsigned(0, 32);
tr_hold <= '0';
pfBusy_i <= '0';
triggerVmmReadout_i <= '0';
rst_l0 <= '1';
sel_wrenable <= '0';
rst_FIFO <= '1';
daqFIFO_wr_en_hdr <= '0';
packLen_cnt <= x"000";
wait_Cnt <= 0;
sel_cnt <= (others => '0');
drv_enable <= '0';
triggerVmmReadout_i <= '0';
end_packet_int <= '0';
state <= waitingForNewCycle;
else
case state is
when waitingForNewCycle =>
debug_state <= "00000";
pfBusy_i <= '0';
triggerVmmReadout_i <= '0';
rst_l0 <= '0';
sel_wrenable <= '0';
drv_enable <= '0';
trigLatencyCnt <= 0;
sel_cnt <= (others => '0');
rst_FIFO <= '0';
if newCycle = '1' then
pfBusy_i <= '1';
state <= increaseCounter;
end if;
when increaseCounter =>
debug_state <= "00001";
eventCounter_i <= eventCounter_i + 1;
state <= waitForLatency;
when waitForLatency =>
debug_state <= "00010";
tr_hold <= '1'; -- Prevent new triggers
if(trigLatencyCnt > trigLatency and is_mmfe8 = '1')then
state <= S2;
elsif(trigLatencyCnt > trigLatency and is_mmfe8 = '0')then
state <= captureEventID;
else
trigLatencyCnt <= trigLatencyCnt + 1;
end if;
when S2 => -- wait for the header elements to be formed
debug_state <= "00010";
-- --tr_hold <= '1'; -- Prevent new triggers
packLen_cnt <= x"000"; -- Reset length count
sel_wrenable <= '0';
vmmId_i <= std_logic_vector(to_unsigned(vmmId_cnt, 3));
state <= captureEventID;
when captureEventID => -- Form Header
debug_state <= "00011";
packLen_cnt <= x"000";
state <= setEventID;
when setEventID =>
debug_state <= "00100";
rst_FIFO <= '0';
daqFIFO_wr_en_hdr <= '0';
if(wait_Cnt < 3)then
wait_Cnt <= wait_Cnt + 1;
state <= setEventID;
else
wait_Cnt <= 0;
state <= sendHeaderStep1;
end if;
when sendHeaderStep1 =>
debug_state <= "00101";
daqFIFO_wr_en_hdr <= '1';
packLen_cnt <= packLen_cnt + 1;
state <= sendHeaderStep2;
when sendHeaderStep2 =>
debug_state <= "00110";
daqFIFO_wr_en_hdr <= '0';
if(wait_Cnt < 3)then
wait_Cnt <= wait_Cnt + 1;
state <= sendHeaderStep2;
else
wait_Cnt <= 0;
state <= sendHeaderStep3;
end if;
when sendHeaderStep3 =>
if(sel_cnt < 5 and vmmReadoutMode = '0')then -- incr the counter to select the other parts of the header
sel_cnt <= sel_cnt + 1;
state <= setEventID;
elsif(sel_cnt < 4 and vmmReadoutMode = '1')then
sel_cnt <= sel_cnt + 1;
state <= setEventID;
else -- the whole header has been sent
state <= triggerVmmReadout;
end if;
when triggerVmmReadout => -- Creates an 136ns pulse to trigger the readout if not at level0 mode
debug_state <= "00111";
sel_cnt <= "110"; -- fix the counter to 4 to select the VMM data for the next steps
sel_wrenable <= '1'; -- grant control to driver
if wait_Cnt < 30 and vmmReadoutMode = '0' then
wait_Cnt <= wait_Cnt + 1;
triggerVmmReadout_i <= '1';
else
triggerVmmReadout_i <= '0';
wait_Cnt <= 0;
state <= waitForData;
end if;
when waitForData =>
debug_state <= "01000";
if (vmmWordReady = '1') then
state <= sendVmmDataStep1;
elsif (vmmEventDone = '1') then
state <= sendTrailer;
end if;
when sendVmmDataStep1 =>
debug_state <= "01001";
drv_enable <= '1';
state <= sendVmmDataStep2;
when sendVmmDataStep2 =>
debug_state <= "01010";
if(drv_done = '1')then
state <= formTrailer;
else
state <= sendVmmDataStep2;
end if;
when formTrailer =>
debug_state <= "01011";
if (vmmEventDone = '1') then
state <= sendTrailer;
elsif (vmmEventDone = '0' and vmmWordReady = '0') then
state <= waitForData;
else -- (vmmWordReady = '1') then
state <= formTrailer;
end if;
when sendTrailer =>
debug_state <= "01100";
packLen_i <= packLen_cnt + packLen_drv2pf_unsg;
state <= packetDone;
when packetDone =>
debug_state <= "01101";
end_packet_int <= '1';
if(is_mmfe8 = '1')then
state <= eventDone;
else
state <= isUDPDone;
end if;
when eventDone =>
debug_state <= "01110";
end_packet_int <= '0';
drv_enable <= '0';
if vmmId_cnt = 7 then
vmmId_cnt <= 0;
state <= isUDPDone;
else
vmmId_cnt <= vmmId_cnt + 1;
sel_cnt <= "000";
sel_wrenable <= '0';
state <= S2;
end if;
-- when resetVMMs =>
-- debug_state <= "01111";
-- rst_vmm <= '1';
-- state <= resetDone;
-- when resetDone =>
-- debug_state <= "10000";
-- if resetting = '0' then
-- rst_vmm <= '0';
-- state <= isUDPDone;
-- rst_vmm <= '0'; -- Prevent from continuously resetting while waiting for UDP Packet
-- end if;
when isUDPDone =>
debug_state <= "01110";
drv_enable <= '0';
end_packet_int <= '0';
rst_l0 <= '1'; -- reset the level0 buffers and the interface with packet_formation
-- pfBusy_i <= '0';
if (UDPDone = '1') then -- Wait for the UDP packet to be sent
state <= isTriggerOff;
end if;
when isTriggerOff => -- Wait for whatever ongoing trigger pulse to go to 0
debug_state <= "01111";
if trraw_synced125 /= '1' then
tr_hold <= '0'; -- Allow new triggers
state <= waitingForNewCycle;
end if;
when others =>
tr_hold <= '0';
state <= waitingForNewCycle;
end case;
end if;
end if;
end process;
muxFIFOData: process( sel_cnt, header, header_l0, vmmWord, vmmArtData125 )
begin
case sel_cnt is
when "000" => daqFIFO_din <= b"1111000" & artValid & "01" &
vmmArtData125(0) & vmmArtData125(1) & vmmArtData125(2) & vmmArtData125(3) & vmmArtData125(4) & vmmArtData125(5);
when "001" => daqFIFO_din <= b"0000000" & artValid & "00" &
vmmArtData125(0) & vmmArtData125(1) & vmmArtData125(2) & vmmArtData125(3) & vmmArtData125(4) & vmmArtData125(5);
when "010" => if (vmmReadoutMode = '0') then daqFIFO_din <= header(63 downto 48); else daqFIFO_din <= header_l0(47 downto 32); end if;
when "011" => if (vmmReadoutMode = '0') then daqFIFO_din <= header(47 downto 32); else daqFIFO_din <= header_l0(31 downto 16); end if;
when "100" => if (vmmReadoutMode = '0') then daqFIFO_din <= header(31 downto 16); else daqFIFO_din <= header_l0(15 downto 0); end if;
when "101" => daqFIFO_din <= header(15 downto 0);
when "110" => daqFIFO_din <= vmmWord;
when others => daqFIFO_din <= (others => '0');
end case;
end process;
muxWrEn: process( sel_wrenable, daqFIFO_wr_en_hdr, daqFIFO_wr_en_drv )
begin
case sel_wrenable is
when '0' => wrenable <= daqFIFO_wr_en_hdr;
when '1' => wrenable <= daqFIFO_wr_en_drv;
when others => wrenable <= '0';
end case;
end process;
vmm_driver_inst: vmm_driver
port map(
------------------------------------
------ General/PF Interface --------
clk => clk,
drv_enable => drv_enable,
drv_done => drv_done,
pack_len_drv => packLen_drv2pf,
------------------------------------
----- VMM_RO/FIFO2UDP Interface ----
wr_en_fifo2udp => daqFIFO_wr_en_drv,
rd_en_buff => rd_ena_buff,
vmmWordReady => vmmWordReady
);
triggerEdgeDetection: process(clk) --125
begin
if rising_edge(clk) then
if trraw_synced125_prev = '0' and trraw_synced125 = '1' then
clearValid <= '1';
trraw_synced125_prev <= trraw_synced125;
else
clearValid <= '0';
trraw_synced125_prev <= trraw_synced125;
end if;
end if;
end process;
LDCE_inst : LDCE
generic map (
INIT => '0')
port map (
Q => artValid,
CLR => clearValid,
D => '1',
G => vmmArtReady,
GE => artEnabled
);
globBcid_i <= globBcid;
vmmWord_i <= vmmWord;
dataout <= daqFIFO_din;
packLen <= std_logic_vector(packLen_i);
end_packet <= end_packet_int;
trigVmmRo <= triggerVmmReadout_i;
vmmId <= vmmId_i;
trigLatency <= 37 + to_integer(unsigned(latency)); --(hard set to 300ns )--to_integer(unsigned(latency));
pfBusy <= pfBusy_i;
globBCID_etr <= glBCID;
artHeader <= b"0000000000" & vmmArtData125;
-- header of level 0 has three 16-bit words from FPGA + one 16-bit word from VMM
header_l0(47 downto 16) <= std_logic_vector(eventCounter_i);
header_l0(15 downto 0) <= b"00000" & vmmId_i & linkHealth_bmsk;
-- 5 & 3 & 8 ;
header(63 downto 32) <= std_logic_vector(eventCounter_i);
header(31 downto 0) <= precCnt & globBcid & b"00000" & vmmId_i;
-- 8 & 16 & 5 & 3
dbg_st_o <= debug_state;
packLen_drv2pf_unsg <= unsigned(packLen_drv2pf);
--ilaPacketFormation: ila_pf
--port map(
-- clk => clk,
-- probe0 => probe0_out,
-- probe1 => probe1_out
--);
probe0_out(9 downto 0) <= std_logic_vector(to_unsigned(trigLatencyCnt, 10));
probe0_out(19 downto 10) <= std_logic_vector(to_unsigned(trigLatency, 10));
probe0_out(20) <= '0';
probe0_out(21) <= artValid;
probe0_out(22) <= trraw_synced125;
probe0_out(23) <= vmmArtReady;
probe0_out(29 downto 24) <= vmmArtData125;
probe0_out(132 downto 30) <= (others => '0');--vmmId_i;
probe1_out(63 downto 0) <= (others => '0');--daqFIFO_din;
probe1_out(64) <= vmmWordReady;
probe1_out(65) <= vmmEventDone;
probe1_out(66) <= '0';
probe1_out(67) <= newCycle;
probe1_out(79 downto 68) <= std_logic_vector(packLen_i);
probe1_out(91 downto 80) <= std_logic_vector(packLen_cnt);
probe1_out(92) <= end_packet_int;
probe1_out(93) <= triggerVmmReadout_i;
probe1_out(109 downto 94) <= latency;
probe1_out(110) <= '0';
probe1_out(142 downto 111) <= std_logic_vector(eventCounter_i);
probe1_out(147 downto 143) <= debug_state;
probe1_out(200 downto 148) <= (others => '0');
end Behavioral; | gpl-3.0 | 574095afc1f03dced6c9f6b5e6a0b454 | 0.461635 | 4.334459 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN16_direct.vhd | 2 | 2,805 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN16_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data driver for EPROC_IN2 module
entity EPROC_IN16_direct is
port (
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (15 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN16_direct;
architecture Behavioral of EPROC_IN16_direct is
signal word10b : std_logic_vector (9 downto 0) := "1100000000"; -- comma
signal word8b_Byte0, word8b_Byte1, word8b_Byte0_s, word8b_Byte1_s : std_logic_vector (7 downto 0) := (others=>'0');
signal word8bRdy, word10bRdy, Byte_index : std_logic := '0';
begin
-------------------------------------------------------------------------------------------
-- input registers
-------------------------------------------------------------------------------------------
input_map: process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
word8b_Byte0_s <= edataIN(7 downto 0);
word8b_Byte1_s <= edataIN(15 downto 8);
word8b_Byte0 <= word8b_Byte0_s;
word8b_Byte1 <= word8b_Byte1_s;
end if;
end process;
-------------------------------------------------------------------------------------------
-- output (code = "00" = data)
-------------------------------------------------------------------------------------------
process(bitCLKx4, rst)
begin
if rst = '1' then
word8bRdy <= '0';
elsif bitCLKx4'event and bitCLKx4 = '1' then
word8bRdy <= not word8bRdy;
end if;
end process;
--
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if word8bRdy = '1' then
Byte_index <= not Byte_index;
end if;
end if;
end process;
--
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if word8bRdy = '1' then
if Byte_index = '0' then
word10b <= "00" & word8b_Byte0;
word10bRdy <= '1';
else
word10b <= "00" & word8b_Byte1;
word10bRdy <= '1';
end if;
else
word10bRdy <= '0';
end if;
end if;
end process;
dataOUT <= word10b;
dataOUTrdy <= word10bRdy;
end Behavioral;
| gpl-3.0 | 127b5f3e59fbd30dbb528d9a98b8f068 | 0.45205 | 3.874309 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/FIR_Filter/fir_filter_imp.vhd | 1 | 1,447 | --------------------------------------------------------------------------------------------------
-- FIR Filter Implementation
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
use work.fir_filter_pkg.all;
--This module is a top-level for implementing the fir filter
entity fir_filter_imp is
port( clk : in std_logic;
rst : in std_logic;
x : in sig;
y : out fir_sig);
end fir_filter_imp;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture imp of fir_filter_imp is
begin
--Instantiate unit under test
uut : entity work.fir_filter(behave)
generic map(h => LOW_PASS_101)
port map( clk => clk,
rst => rst,
x => x,
y => y);
end imp;
| mit | f8bfea2bd749eeecab3b2eb9d3d68b6f | 0.304768 | 6.054393 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/rsa_512/trunk/rtl/montgomery_mult.vhd | 1 | 12,070 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:03:35 11/02/2009
-- Design Name:
-- Module Name: etapas - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity montgomery_mult is
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
n : in std_logic_vector(15 downto 0);
s_prev : in std_logic_vector(15 downto 0);
n_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector( 15 downto 0);
valid_out : out std_logic -- es le valid out TODO : cambiar nombre
);
end montgomery_mult;
architecture Behavioral of montgomery_mult is
component montgomery_step is
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
n : in std_logic_vector(15 downto 0);
s_prev : in std_logic_vector(15 downto 0);
n_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector( 15 downto 0);
valid_out : out std_logic; -- es le valid out TODO : cambiar nombre
busy : out std_logic;
b_req : out std_logic;
a_out : out std_logic_vector(15 downto 0);
n_out : out std_logic_vector(15 downto 0); --señal que indica que el modulo está ocupado y no puede procesar nuevas peticiones
c_step : out std_logic; --genera un pulso cuando termina su computo para avisar al modulo superior
stop : in std_logic
);
end component;
component fifo_512_bram
port (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(15 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(15 downto 0);
full : out std_logic;
empty : out std_logic);
end component;
component fifo_256_feedback
port (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(48 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(48 downto 0);
full : out std_logic;
empty : out std_logic);
end component;
type arr_dat_out is array(0 to 7) of std_logic_vector(15 downto 0);
type arr_val is array(0 to 7) of std_logic;
type arr_b is array(0 to 7) of std_logic_vector(15 downto 0);
signal b_reg, next_b_reg : arr_b;
signal valid_mid, fifo_reqs, fifo_reqs_reg, next_fifo_reqs_reg, stops : arr_val;
signal a_out_mid, n_out_mid, s_out_mid : arr_dat_out; --std_logic_vector(15 downto 0);
--Señales a la fifo
signal wr_en, rd_en, empty : std_logic;
signal fifo_out : std_logic_vector(15 downto 0);
signal fifo_out_feedback, fifo_in_feedback : std_logic_vector(48 downto 0);
signal read_fifo_feedback, empty_feedback : std_logic;
--Señales de entrada al primer PE
signal a_in, s_in, n_in : std_logic_vector(15 downto 0);
signal f_valid, busy_pe : std_logic;
--salida c_step del primer PE para ir contando y saber cuando sacar el valor correcto.
signal c_step, reg_c_step : std_logic;
--contador para saber cuando coño acabamos :)
signal count, next_count : std_logic_vector(7 downto 0);
--señal para escribir el loopback en la fifo de entrada de feedback
signal wr_fifofeed : std_logic;
type state_type is (rst_fifos, wait_start, process_data, dump_feed);
signal state, next_state : state_type;
signal reg_busy : std_logic;
signal reset_fifos : std_logic;
signal count_feedback, next_count_feedback : std_logic_vector(15 downto 0);
begin
--Fifo para almacenar b
fifo_b : fifo_512_bram port map (
clk => clk,
rst => reset_fifos,
din => b,
wr_en => wr_en,
rd_en => rd_en,
dout => fifo_out,
empty => empty
);
--Fifo para el feedback al primer PE
fifo_feed : fifo_256_feedback port map (
clk => clk,
rst => reset_fifos,
din => fifo_in_feedback,
wr_en => wr_fifofeed,
rd_en => read_fifo_feedback,
dout => fifo_out_feedback,
empty => empty_feedback
);
--Primer PE
et_first : montgomery_step port map(
clk => clk,
reset => reset,
valid_in => f_valid,
a => a_in,
b => b_reg(0),
n => n_in,
s_prev => s_in,
n_c => n_c,
s => s_out_mid(0),
valid_out => valid_mid(0),
busy => busy_pe,
b_req => fifo_reqs(0),
a_out => a_out_mid(0),
n_out => n_out_mid(0),
c_step => c_step,
stop => stops(0)
);
--Ultimo PE
et_last : montgomery_step port map(
clk => clk,
reset => reset,
valid_in => valid_mid(6),
a => a_out_mid(6),
b => b_reg(7),
n => n_out_mid(6),
s_prev => s_out_mid(6),
n_c => n_c,
s => s_out_mid(7),
valid_out => valid_mid(7),
b_req => fifo_reqs(7),
a_out => a_out_mid(7),
n_out => n_out_mid(7),
stop => stops(7)
);
g1 : for i in 1 to 6 generate
et_i : montgomery_step port map(
clk => clk,
reset => reset,
valid_in => valid_mid(i-1),
a => a_out_mid(i-1),
b => b_reg(i),
n => n_out_mid(i-1),
s_prev => s_out_mid(i-1),
n_c => n_c,
s => s_out_mid(i),
valid_out => valid_mid(i),
b_req => fifo_reqs(i),
a_out => a_out_mid(i),
n_out => n_out_mid(i),
stop => stops(i)
);
end generate g1;
process(clk, reset)
begin
if(clk = '1' and clk'event) then
if(reset = '1')then
state <= wait_start;
count_feedback <= (others => '0');
reg_busy <= '0';
for i in 0 to 7 loop
b_reg(i) <= (others => '0');
fifo_reqs_reg (i) <= '0';
count <= (others => '0');
reg_c_step <= '0';
end loop;
else
state <= next_state;
reg_busy <= busy_pe;
count_feedback <= next_count_feedback;
for i in 0 to 7 loop
b_reg(i) <= next_b_reg(i);
fifo_reqs_reg (i) <= next_fifo_reqs_reg(i);
count <= next_count;
reg_c_step <= c_step;
end loop;
end if;
end if;
end process;
--Proceso combinacional que controla las lecturas a la fifo
process(fifo_reqs_reg, fifo_out, b, fifo_reqs, b_reg, state, empty)
begin
for i in 0 to 7 loop
next_b_reg(i) <= b_reg(i);
next_fifo_reqs_reg(i) <= fifo_reqs(i);
end loop;
if(state = wait_start) then
next_b_reg(0) <= b;
next_fifo_reqs_reg(0) <= '0'; --anulamos la peticion de b
for i in 1 to 7 loop
next_b_reg(i) <= (others => '0');
next_fifo_reqs_reg(i) <= '0';
end loop;
else
for i in 0 to 7 loop
if(fifo_reqs_reg(i) = '1' and empty = '0') then
next_b_reg(i) <= fifo_out;
end if;
end loop;
end if;
end process;
--Proceso combinacional fsm principal
process( valid_in, b, state, fifo_reqs, a_out_mid, n_out_mid, s_out_mid, valid_mid, a, s_prev, n, busy_pe, empty_feedback, fifo_out_feedback, count, reg_c_step, reset, reg_busy, count_feedback )
begin
--las peticiones a la fifo son las or de los modulos
rd_en <= fifo_reqs(0) or fifo_reqs(1) or fifo_reqs(2) or fifo_reqs(3) or fifo_reqs(4) or fifo_reqs(5) or fifo_reqs(6) or fifo_reqs(7);
next_state <= state;
wr_en <= '0';
fifo_in_feedback <= a_out_mid(7)&n_out_mid(7)&s_out_mid(7)&valid_mid(7);
read_fifo_feedback <= '0';
wr_fifofeed <= '0';
--Controlamos el primer PE
a_in <= a;
s_in <= s_prev;
n_in <= n;
f_valid <= valid_in;
reset_fifos <= reset;
--ponemos las salidas
s <= (others => '0');
valid_out <= '0';
--Incrementamos el contador solo cuando el primer PE termina su cuenta
next_count <= count;
next_count_feedback <= count_feedback;
--El contador solo se incrementa una vez por ciclo de la pipeline, así me evito que cada PE lo incremente
if(reg_c_step = '1') then
next_count <= count + 8;
end if;
--durante el ciclo de la pipeline que sea considerado el ultimo, sacamos los datos
if( count = x"20") then
s <= s_out_mid(0);
valid_out <= valid_mid(0);
end if;
for i in 0 to 7 loop
stops(i) <= '0';
end loop;
case state is
--Esperamos a que tengamos un input y vamos cargando las b's
when wait_start =>
--reset_fifos <= '1';
if(valid_in = '1') then
reset_fifos <= '0';
--next_b_reg(0) <= b;
next_state <= process_data;
--wr_en <= '1';
end if;
when process_data =>
wr_fifofeed <= valid_mid(7);
if(valid_in = '1') then
wr_en <= '1';
end if;
--Miramos si hay que volver a meter datos a la b
if(empty_feedback = '0' and reg_busy = '0') then
read_fifo_feedback <= '1';
next_state <= dump_feed;
next_count_feedback <= x"0000";
end if;
--Si ya hemos sobrepasado el limite paramos y volvemos a la espera
if( count > x"23") then
next_state <= wait_start;
--y
for i in 0 to 7 loop
stops(i) <= '1';
end loop;
next_count <= (others => '0');
end if;
--Vacia la fifo de feedback
when dump_feed =>
if(empty_feedback = '0')
then
next_count_feedback <= count_feedback+1;
end if;
wr_fifofeed <= valid_mid(7);
read_fifo_feedback <= '1';
a_in <= fifo_out_feedback(48 downto 33);
n_in <= fifo_out_feedback(32 downto 17);
s_in <= fifo_out_feedback(16 downto 1);
f_valid <= fifo_out_feedback(0);
if(empty_feedback = '1') then
next_state <= process_data;
end if;
if(count_feedback = x"22") then
read_fifo_feedback <= '0';
next_state <= process_data;
end if;
when rst_fifos =>
next_state <= wait_start;
reset_fifos <= '1';
end case;
end process;
end Behavioral;
| bsd-3-clause | 0730d3aca8c0cbc587592c21327782d4 | 0.486827 | 3.465403 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/temac_10_100_1000_config_vector_sm.vhd | 2 | 11,959 | --------------------------------------------------------------------------------
-- File : temac_10_100_1000_config_vector_sm.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This module is reponsible for bringing up the MAC
-- to enable basic packet transfer in both directions.
-- Due to the lack of a management interface the PHy cannot be
-- accessed and therefore this solution will not work when
-- targeted to a demo platform unless some other method of enabing the PHY
-- is used.
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- The entity declaration for the block level example design.
--------------------------------------------------------------------------------
entity temac_10_100_1000_config_vector_sm is
port(
gtx_clk : in std_logic;
gtx_resetn : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
rx_configuration_vector : out std_logic_vector(79 downto 0);
tx_configuration_vector : out std_logic_vector(79 downto 0)
);
end temac_10_100_1000_config_vector_sm;
architecture rtl of temac_10_100_1000_config_vector_sm is
constant RUN_HALF_DUPLEX : std_logic := '0';
------------------------------------------------------------------------------
-- Component declaration for the synchroniser
------------------------------------------------------------------------------
component temac_10_100_1000_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
-- main state machine
type state_typ is (STARTUP,
RESET_MAC,
CHECK_SPEED);
---------------------------------------------------
-- Signal declarations
signal control_status : state_typ;
signal update_speed_reg : std_logic;
signal update_speed_reg2 : std_logic;
signal update_speed_sync : std_logic;
signal count_shift : std_logic_vector(20 downto 0) := (others => '0');
signal tx_reset : std_logic;
signal tx_enable : std_logic;
signal tx_vlan_enable : std_logic;
signal tx_fcs_enable : std_logic;
signal tx_jumbo_enable : std_logic;
signal tx_fc_enable : std_logic;
signal tx_hd_enable : std_logic;
signal tx_ifg_adjust : std_logic;
signal tx_speed : std_logic_vector(1 downto 0);
signal tx_max_frame_enable : std_logic;
signal tx_max_frame_length : std_logic_vector(14 downto 0);
signal tx_pause_addr : std_logic_vector(47 downto 0);
signal rx_reset : std_logic;
signal rx_enable : std_logic;
signal rx_vlan_enable : std_logic;
signal rx_fcs_enable : std_logic;
signal rx_jumbo_enable : std_logic;
signal rx_fc_enable : std_logic;
signal rx_hd_enable : std_logic;
signal rx_len_type_chk_disable : std_logic;
signal rx_control_len_chk_dis : std_logic;
signal rx_promiscuous : std_logic;
signal rx_speed : std_logic_vector(1 downto 0);
signal rx_max_frame_enable : std_logic;
signal rx_max_frame_length : std_logic_vector(14 downto 0);
signal rx_pause_addr : std_logic_vector(47 downto 0);
signal gtx_reset : std_logic;
begin
gtx_reset <= not gtx_resetn;
rx_configuration_vector <= rx_pause_addr &
'0' & rx_max_frame_length &
'0' & rx_max_frame_enable &
rx_speed &
rx_promiscuous &
'0' & rx_control_len_chk_dis &
rx_len_type_chk_disable &
'0' & rx_hd_enable &
rx_fc_enable &
rx_jumbo_enable &
rx_fcs_enable &
rx_vlan_enable &
rx_enable &
rx_reset;
tx_configuration_vector <= tx_pause_addr &
'0' & tx_max_frame_length &
'0' & tx_max_frame_enable &
tx_speed &
"000" & tx_ifg_adjust &
'0' & tx_hd_enable &
tx_fc_enable &
tx_jumbo_enable &
tx_fcs_enable &
tx_vlan_enable &
tx_enable &
tx_reset;
-- don't reset this - it will always be updated before it is used..
-- it does need an init value (zero)
gen_count : process (gtx_clk)
begin
if gtx_clk'event and gtx_clk = '1' then
count_shift <= count_shift(19 downto 0) & (gtx_reset or tx_reset);
end if;
end process gen_count;
upspeed_sync : temac_10_100_1000_sync_block
port map (
clk => gtx_clk,
data_in => update_speed,
data_out => update_speed_sync
);
-- capture update_spped as only want to react to one edge
capture_update : process (gtx_clk)
begin
if gtx_clk'event and gtx_clk = '1' then
if gtx_reset = '1' then
update_speed_reg <= '0';
update_speed_reg2 <= '0';
else
update_speed_reg <= update_speed_sync;
update_speed_reg2 <= update_speed_reg;
end if;
end if;
end process capture_update;
------------------------------------------------------------------------------
-- Management process. This process sets up the configuration by
-- turning off flow control
------------------------------------------------------------------------------
gen_state : process (gtx_clk)
begin
if gtx_clk'event and gtx_clk = '1' then
if gtx_reset = '1' then
tx_reset <= '0';
tx_enable <= '1';
tx_vlan_enable <= '0';
tx_fcs_enable <= '0';
tx_jumbo_enable <= '1';
tx_fc_enable <= '1';
tx_hd_enable <= RUN_HALF_DUPLEX;
tx_ifg_adjust <= '0';
tx_speed <= mac_speed;
tx_max_frame_enable <= '0';
tx_max_frame_length <= (others => '0');
tx_pause_addr <= X"0605040302DA";
rx_reset <= '0';
rx_enable <= '1';
rx_vlan_enable <= '0';
rx_fcs_enable <= '0';
rx_jumbo_enable <= '1';
rx_fc_enable <= '1';
rx_hd_enable <= RUN_HALF_DUPLEX;
rx_len_type_chk_disable <= '0';
rx_control_len_chk_dis <= '0';
rx_promiscuous <= '0';
rx_speed <= mac_speed;
rx_max_frame_enable <= '0';
rx_max_frame_length <= (others => '0');
rx_pause_addr <= X"0605040302DA";
control_status <= STARTUP;
-- main state machine is kicking off multi cycle accesses in each state so has to
-- stall while they take place
else
case control_status is
when STARTUP =>
-- this state will be ran after reset to wait for count_shift
if count_shift(20) = '0' then
control_status <= RESET_MAC;
end if;
when RESET_MAC =>
assert false
report "Reseting MAC" & cr
severity note;
tx_reset <= '1';
rx_reset <= '1';
rx_speed <= mac_speed;
tx_speed <= mac_speed;
control_status <= CHECK_SPEED;
when CHECK_SPEED =>
-- hold the local resets for 20 gtx cycles to ensure
-- the tx is captured by the mac
if count_shift(20) = '1' then
tx_reset <= '0';
rx_reset <= '0';
end if;
if update_speed_reg = '1' and update_speed_reg2 = '0' then
control_status <= RESET_MAC;
end if;
when others =>
control_status <= STARTUP;
end case;
end if;
end if;
end process gen_state;
end rtl;
| gpl-3.0 | 348dd20465af83591a0ed4ca69525efc | 0.471946 | 4.590787 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/EPROC_FIFO_DRIVER.vhd | 1 | 21,242 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: EPROC_FIFO_DRIVER
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.all;
use work.centralRouter_package.all;
--! a driver for EPROC FIFO, manages block header and sub-chunk trailer
entity EPROC_FIFO_DRIVER is
generic (
GBTid : integer := 0;
egroupID : integer := 0;
epathID : integer := 0;
toHostTimeoutBitn : integer := 8
);
port (
clk40 : in std_logic;
clk160 : in std_logic;
rst : in std_logic;
----------
encoding : in std_logic_vector (1 downto 0);
maxCLEN : in std_logic_vector (2 downto 0);
---------
DIN : in std_logic_vector (9 downto 0);
DIN_RDY : in std_logic;
----------
xoff : in std_logic;
timeCntIn : in std_logic_vector ((toHostTimeoutBitn-1) downto 0);
TimeoutEnaIn: in std_logic;
----------
wordOUT : out std_logic_vector (15 downto 0);
wordOUT_RDY : out std_logic
);
end EPROC_FIFO_DRIVER;
architecture Behavioral of EPROC_FIFO_DRIVER is
--
signal DIN_r : std_logic_vector (7 downto 0) := (others => '0');
signal DIN_CODE_r : std_logic_vector (1 downto 0) := (others => '0');
signal DIN_s : std_logic_vector (9 downto 0);
signal DIN_RDY_r : std_logic := '0';
---
signal receiving_state, data_shift_trig, trailer_shift_trig, trailer_shift_trig_s,
EOC_error, SOC_error, rst_clen_counter, data16bit_rdy,
data16bit_rdy_shifted, truncating_state, truncation_trailer_sent : std_logic := '0';
signal send_trailer_trig : std_logic;
signal DIN_prev_is_zeroByte, DIN_is_zeroByte : std_logic := '0';
signal direct_data_mode, direct_data_boundary_detected : std_logic;
signal trailer_trunc_bit, trailer_cerr_bit, first_subchunk, first_subchunk_on : std_logic := '0';
signal trailer_mod_bits : std_logic_vector (1 downto 0);
signal trailer_type_bits : std_logic_vector (2 downto 0) := (others => '0');
signal EOB_MARK, truncateDataFlag, flushed, data_rdy : std_logic;
signal trailer_shift_trigs, trailer_shift_trig0, header_shift_trigs : std_logic;
signal trailer_shift_trig1 : std_logic := '0';
signal data16bit_rdy_code : std_logic_vector (2 downto 0);
signal trailer, trailer0, trailer1, header, data : std_logic_vector (15 downto 0);
signal wordOUT_s : std_logic_vector (15 downto 0) := (others => '0');
signal pathENA, DIN_RDY_s : std_logic := '0';
signal pathENAtrig, blockCountRdy,timeout_trailer_send_1st_clk : std_logic;
--
signal timeCnt_lastClk : std_logic_vector ((toHostTimeoutBitn-1) downto 0);
signal receiving_state_clk40, do_transmit_timeout_trailers,timout_ena,timeout_trailer_send : std_logic := '0';
--
constant zero_data_trailer : std_logic_vector(15 downto 0) := "0000000000000000"; -- "000"=null chunk, "00"=no truncation & no cerr, '0', 10 bit length is zero;
constant timeout_trailer : std_logic_vector(15 downto 0) := "1010000000000000"; -- "101"=timeout, "00"=no truncation & no cerr, '0', 10 bit length is zero;
--
begin
------------------------------------------------------------
-- time out counter for triggering the send-out of an
-- incomplete block
------------------------------------------------------------
process(clk40,rst)
begin
if rst = '1' then
receiving_state_clk40 <= '0';
elsif rising_edge (clk40) then
receiving_state_clk40 <= receiving_state;
end if;
end process;
--
process(clk40,rst)
begin
if rst = '1' then
timeCnt_lastClk <= (others=>'1');
elsif rising_edge (clk40) then
if receiving_state_clk40 = '1' then
timeCnt_lastClk <= timeCntIn;
end if;
end if;
end process;
--
p0: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk160, do_transmit_timeout_trailers, timeout_trailer_send_1st_clk);
--
process(clk160,rst)
begin
if rst = '1' then
do_transmit_timeout_trailers <= '0';
elsif rising_edge (clk160) then
if timeCnt_lastClk = timeCntIn and timout_ena = '1' and TimeoutEnaIn = '1' then
do_transmit_timeout_trailers <= '1';
elsif ((DIN_RDY = '1' and DIN(9 downto 8) /= "11") or EOB_MARK = '1') then
do_transmit_timeout_trailers <= '0';
end if;
end if;
end process;
--
process(clk160,rst)
begin
if rst = '1' then
timeout_trailer_send <= '0';
elsif rising_edge (clk160) then
if timeout_trailer_send_1st_clk = '1' then
timeout_trailer_send <= '1';
elsif data16bit_rdy = '1' then -- timeout_trailer was sent once, the rest of the block will be filled with null-trailers
timeout_trailer_send <= '0';
end if;
end if;
end process;
--
process(clk160,rst)
begin
if rst = '1' then
timout_ena <= '0';
elsif rising_edge (clk160) then
if receiving_state = '1' then
timout_ena <= '1';
elsif do_transmit_timeout_trailers = '1' then
timout_ena <= '0';
end if;
end if;
end process;
--
---------------------------------------------
-- CLK1: register the input
---------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
if do_transmit_timeout_trailers = '0' then
DIN_s <= DIN;
DIN_RDY_s <= '1';
else
DIN_s <= "0100000000";
DIN_RDY_s <= '1';
end if;
else
DIN_RDY_s <= '0';
end if;
end if;
end process;
-- for the direct data case:
-- register the input byte comparator result
-- for the direct data case to detect zeros as data delimeter
direct_data_mode <= not(encoding(1) or encoding(0));
--
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
if DIN(7 downto 0) = "00000000" then
DIN_is_zeroByte <= '1';
else
DIN_is_zeroByte <= '0';
end if;
end if;
end if;
end process;
-- pipeline the input byte comparator result
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
DIN_prev_is_zeroByte <= DIN_is_zeroByte;
end if;
end if;
end process;
--
direct_data_boundary_detected <= '1' when (DIN_is_zeroByte = '1' and DIN_prev_is_zeroByte = '1') else '0';
--
---------------------------------------------
-- initial enabling of the path:
-- enabled after reset on the first
-- valid input symbol (must be comma!)
-- the first symbol is then lost! as we are sending
-- a bloack header when it is detected
---------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if rst = '1' then
pathENA <= '0';
elsif DIN_RDY_s = '1' then --
pathENA <= '1';
end if;
end if;
end process;
-- trigger to restart the block counter
pathENA1clk: entity work.pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(clk160, pathENA, pathENAtrig);
---------------------------------------------
-- CLK2:
---------------------------------------------
--
DIN_RDY_r <= DIN_RDY_s; --and pathENA; --blockCountRdy;
DIN_r <= DIN_s(7 downto 0);
--process(clk160)
--begin
-- if rising_edge (clk160) then
-- DIN_r <= DIN_s(7 downto 0);
-- end if;
--end process;
--
--process(clk160)
--begin
-- if rising_edge (clk160) then
-- if direct_data_mode = '1' then
-- if DIN_is_zeroByte = '1' and DIN_prev_is_zeroByte = '1' then
-- DIN_CODE_r <= "10"; -- soc
-- else
-- DIN_CODE_r <= "00"; -- data
-- end if;
-- else
-- DIN_CODE_r <= DIN_s(9 downto 8);
-- end if;
-- end if;
--end process;
--
process(direct_data_mode, direct_data_boundary_detected, DIN_s(9 downto 8))
begin
if direct_data_mode = '1' then
DIN_CODE_r <= direct_data_boundary_detected & '0'; -- "10"=soc, "00"=data
else
DIN_CODE_r <= DIN_s(9 downto 8);
end if;
end process;
--
-----------------------------------------------------------
-- clock 3
-- case of the input word code:
-- "00" => data, "01" => EOC, "10" => SOC, "11" => COMMA
-----------------------------------------------------------
process(clk160, rst)
begin
if rst = '1' then
--
receiving_state <= '0';
trailer_trunc_bit <= '1';
trailer_cerr_bit <= '1';
trailer_type_bits <= "000"; -- not a legal code
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
truncating_state <= '0';
--
elsif rising_edge (clk160) then
if DIN_RDY_r = '1' then
case (DIN_CODE_r) is
when "00" => -- data
--
data_shift_trig <= (receiving_state) and (not truncateDataFlag); -- shift-in data if in the receiving state
-- if block filled up after that, chunk trailer and block header will be shifted-in as well
trailer_trunc_bit <= truncateDataFlag; -- truncation mark in case of CLEN_error
trailer_cerr_bit <= truncateDataFlag; -- CLEN_error is '1' in case of receiving data after CLEN is reached
trailer_type_bits <= (not (truncateDataFlag or first_subchunk)) & truncateDataFlag & first_subchunk; -- 001_first, 011_whole, 100_middle, 010_last
trailer_shift_trig <= truncateDataFlag and receiving_state; -- send a trailer once when CLEN value is reached (SOC will rst the chunk-len-counter)
receiving_state <= receiving_state and (not truncateDataFlag); -- switching off receiving in case of truncateDataFlag, waiting for SOC now
EOC_error <= '0';
SOC_error <= not receiving_state; -- if current state is not 'receiving', flag an error, do nothing
rst_clen_counter <= '0';
first_subchunk_on <= '0';
truncating_state <= truncateDataFlag and receiving_state; -- truncation trailer is sent in this 'case' (once)
--
when "01" => -- EOC
--
trailer_shift_trig <= receiving_state or do_transmit_timeout_trailers; -- if '1' => correct state, shift-in a trailer, if not, do nothing
-- sending a trailer is including padding with zeros ('flush') in case of even word count (should be flagged somewhere...)
trailer_trunc_bit <= '0'; -- no truncation, proper ending
trailer_cerr_bit <= '0';
trailer_type_bits <= do_transmit_timeout_trailers & '1' & first_subchunk; -- 'last sub-chunk' or 'whole sub-chunk' mark
EOC_error <= not receiving_state; -- if current state was not 'receiving', flag an error, do nothing
receiving_state <= '0';
--
truncating_state <= truncating_state;
rst_clen_counter <= '0';
first_subchunk_on <= '0';
data_shift_trig <= '0';
SOC_error <= '0';
--
when "10" => -- SOC
--
trailer_shift_trig <= (receiving_state and (not direct_data_mode)) or (truncateDataFlag and (not truncation_trailer_sent)); -- if '1' => incorrect state, shift-in a trailer to finish the unfinished chunk
-- sending a trailer is including padding with zeros ('flush') in case of even word count (should be flagged somewhere...)
trailer_trunc_bit <= '1'; -- truncation mark in case of sending a trailer (this is when EOC was not received)
trailer_cerr_bit <= '1';
trailer_type_bits <= "01" & (first_subchunk or truncateDataFlag); -- 'last sub-chunk' or 'whole sub-chunk' mark
SOC_error <= receiving_state; -- if current state was already 'receiving', flag an error
receiving_state <= not truncateDataFlag; --'1';
rst_clen_counter <= '1';
first_subchunk_on <= '1';
truncating_state <= truncateDataFlag and (not truncation_trailer_sent); -- truncation trailer is sent in this 'case' (once)
--
data_shift_trig <= '0';
EOC_error <= '0';
--
when "11" => -- COMMA
--
-- do nothing
receiving_state <= receiving_state;
truncating_state <= truncating_state;
trailer_trunc_bit <= '0';
trailer_cerr_bit <= '0';
trailer_type_bits <= "000";
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
--
when others =>
end case;
else
receiving_state <= receiving_state;
trailer_trunc_bit <= trailer_trunc_bit;
trailer_cerr_bit <= trailer_cerr_bit;
trailer_type_bits <= trailer_type_bits; --"000";
truncating_state <= truncating_state;
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
end if;
end if;
end process;
-----------------------------------------------------------
-- truncation trailer should be only sent once (the first one)
-----------------------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if truncateDataFlag = '0' then
truncation_trailer_sent <= '0';
else -- truncateDataFlag = '1':
if trailer_shift_trig = '1' then
truncation_trailer_sent <= '1'; -- latch
end if;
end if;
end if;
end process;
--
-----------------------------------------------------------
-- clock3, writing to the shift register
-- data8bit ready pulse
-----------------------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then -- first, try to flush the shift register
trailer_shift_trig_s <= trailer_shift_trig and (not EOB_MARK); -- this trailer is a result of {eoc} or {soc without eoc} or {max clen violation}
end if;
end process;
--
send_trailer_trig <= trailer_shift_trig_s or EOB_MARK;
--
DATA_shift_r: entity work.reg8to16bit -- only for data or 'flush' padding
PORT MAP(
rst => rst,
clk => clk160,
flush => trailer_shift_trig,
din => DIN_r,
din_rdy => data_shift_trig,
-----
flushed => flushed,
dout => data,
dout_rdy => data_rdy
);
-----------------------------------------------------------
-- clock
-- BLOCK_WORD_COUNTER
-----------------------------------------------------------
BLOCK_WORD_COUNTER_inst: entity work.BLOCK_WORD_COUNTER
generic map (GBTid=>GBTid, egroupID=>egroupID, epathID=>epathID)
port map (
CLK => clk160,
RESET => rst,
RESTART => pathENAtrig,
BW_RDY => data16bit_rdy, -- counts everything that is written to EPROC FIFO
EOB_MARK => EOB_MARK, -- End-Of-Block: 'send the chunk trailer' trigger
BLOCK_HEADER_OUT => header,
BLOCK_HEADER_OUT_RDY => header_shift_trigs,
BLOCK_COUNT_RDY => blockCountRdy
);
--
process(clk160)
begin
if rising_edge (clk160) then
if first_subchunk_on = '1' or rst = '1' then
first_subchunk <= '1';
elsif EOB_MARK = '1' then
first_subchunk <= '0';
end if;
end if;
end process;
-----------------------------------------------------------
-- Sub-Chunk Data manager
-- sends a trailer in 2 clocks (current clock and the next)
-----------------------------------------------------------
--
trailer_mod_bits <= trailer_trunc_bit & trailer_cerr_bit;
--
SCDataMANAGER_inst: entity work.SCDataMANAGER
PORT MAP(
CLK => clk160,
rst => rst,
xoff => xoff,
maxCLEN => maxCLEN,
rstCLENcount => rst_clen_counter,
truncateCdata => truncateDataFlag, -- out, next data will be truncated, a trailer will be sent instead
trailerMOD => trailer_mod_bits, -- in, keeps its value till the next DIN_RDY_s
trailerTYPE => trailer_type_bits, -- in, keeps its value till the next DIN_RDY_s
trailerRSRVbit => xoff,
-------
trailerSENDtrig => send_trailer_trig,
dataCNTena => data_shift_trig, -- counts data Bytes (not 16-bit words)data_rdy, -- counts only data (or 'flush' padding), no header, no trailer
-------
trailerOUT => trailer0,
trailerOUTrdy => trailer_shift_trig0
);
--
--
process(clk160)
begin
if rising_edge (clk160) then
trailer_shift_trig1 <= flushed;
trailer1 <= trailer0;
end if;
end process;
--
trailer_shift_trigs <= (trailer_shift_trig0 and (not flushed)) or trailer_shift_trig1;
--
process(trailer_shift_trig1, trailer1, trailer0)
begin
if trailer_shift_trig1 = '1' then
trailer <= trailer1;
else
trailer <= trailer0;
end if;
end process;
-----------------------------------------------------------
-- 16 bit output MUX, goes to a EPROC FIFO
-----------------------------------------------------------
--process(clk160)
--begin
-- if clk160'event and clk160 = '0' then
-- data16bit_rdy_shifted <= data16bit_rdy;
-- end if;
--end process;
--
data16bit_rdy <= data_rdy or trailer_shift_trigs or header_shift_trigs;
data16bit_rdy_code(0) <= (not trailer_shift_trigs) and (data_rdy xor header_shift_trigs);
data16bit_rdy_code(1) <= (not header_shift_trigs) and (data_rdy xor trailer_shift_trigs);
data16bit_rdy_code(2) <= do_transmit_timeout_trailers;
--
--process(data16bit_rdy_code, data, header, trailer)
process(clk160)
begin
if rising_edge (clk160) then
case (data16bit_rdy_code) is
when "001" => -- header
wordOUT_s <= header;
when "010" => -- trailer
wordOUT_s <= trailer;
when "011" => -- data
wordOUT_s <= data;
when "100" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "101" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "110" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "111" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when others =>
--wordOUT_s <= (others => '0');
end case;
end if;
end process;
--
--
process(clk160)
begin
if rising_edge (clk160) then
if rst = '1' then
wordOUT_RDY <= '0';
else
wordOUT_RDY <= data16bit_rdy;-- or data16bit_rdy_shifted;
end if;
end if;
end process;
--
wordOUT <= wordOUT_s;
end Behavioral;
| gpl-3.0 | 139483bea45323d8e3b949a41e7a2fc6 | 0.502919 | 3.916298 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4088/EPROC_IN2_HDLC.vhd | 1 | 7,456 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2015
--! Module Name: EPROC_IN2_HDLC
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
use work.all;
--! HDLC decoder for EPROC_IN2 module
entity EPROC_IN2_HDLC is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (1 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN2_HDLC;
architecture Behavioral of EPROC_IN2_HDLC is
----------------------------------
----------------------------------
signal edataIN_r : std_logic_vector (1 downto 0) := (others=>'1');
signal bit_in_sr,out_sr : std_logic_vector (7 downto 0) := (others=>'1');
signal bit_cnt,error_bit_cnt : std_logic_vector (2 downto 0) := (others=>'0');
signal error_state,error_state_r,error_out : std_logic := '1';
signal edataIN_latch_trig,bit_in,isflag_r,isflag_rr,bit_in_r,bit_in_r_we,sop_marked,remove_zero_r : std_logic := '0';
signal isflag,iserror,remove_zero,out_sr_rdy,dataOUTrdy0,dataOUTrdy1,dataOUTrdy_s,error_out_rdy,error_out_rdy_s : std_logic;
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- input serializer
-------------------------------------------------------------------------------------------
process(bitCLKx2, rst)
begin
if rst = '1' then
edataIN_latch_trig <= '0';
elsif bitCLKx2'event and bitCLKx2 = '1' then
edataIN_latch_trig <= not edataIN_latch_trig;
end if;
end process;
--
process(bitCLKx2, rst)
begin
if rst = '1' then
edataIN_r <= (others=>'1');
elsif bitCLKx2'event and bitCLKx2 = '1' then
if edataIN_latch_trig = '1' then
edataIN_r <= edataIN;
end if;
end if;
end process;
--
process(bitCLKx2)
begin
if bitCLKx2'event and bitCLKx2 = '1' then
if edataIN_latch_trig = '0' then
bit_in <= edataIN_r(0);
else
bit_in <= edataIN_r(1);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock1
-- input shift register
-------------------------------------------------------------------------------------------
process(bitCLKx2, rst)
begin
if rst = '1' then
bit_in_sr <= (others=>'1');
elsif bitCLKx2'event and bitCLKx2 = '1' then
bit_in_sr <= bit_in & bit_in_sr(7 downto 1);
end if;
end process;
--
isflag <= '1' when (bit_in_sr = "01111110") else '0';
iserror <= '1' when (bit_in_sr(7 downto 1) = "1111111") else '0';
remove_zero <= '1' when (bit_in_sr(6 downto 1) = "011111" and isflag_r = '0') else '0';
--
-------------------------------------------------------------------------------------------
--clock2
-- latching the error state, forwarding clean bit sequence
-------------------------------------------------------------------------------------------
process(bitCLKx2, rst)
begin
if rst = '1' then
error_state <= '1';
elsif bitCLKx2'event and bitCLKx2 = '1' then
if iserror = '1' then
error_state <= '1';
elsif isflag = '1' then
error_state <= '0';
end if;
end if;
end process;
--
process(bitCLKx2, rst)
begin
if rst = '1' then
isflag_r <= '0';
isflag_rr <= '0';
bit_in_r_we <= '0';
remove_zero_r <= '0';
error_state_r <= '1';
elsif bitCLKx2'event and bitCLKx2 = '1' then
isflag_r <= isflag;
isflag_rr <= isflag_r;
bit_in_r_we <= not(error_state or remove_zero);
remove_zero_r <= remove_zero;
error_state_r <= error_state;
end if;
end process;
--
bit_in_r <= bit_in_sr(6);
--
-------------------------------------------------------------------------------------------
--clock3
-- output shift register
-------------------------------------------------------------------------------------------
process(bitCLKx2)
begin
if bitCLKx2'event and bitCLKx2 = '1' then
if remove_zero = '0' or isflag_r = '1' or error_state = '1' then --if bit_in_r_we = '1' or isflag_r = '1' then
out_sr <= bit_in_r & out_sr(7 downto 1);
end if;
end if;
end process;
--
process(bitCLKx2, rst)
begin
if rst = '1' then
bit_cnt <= (others=>'0');
elsif bitCLKx2'event and bitCLKx2 = '1' then
if error_state = '1' then
bit_cnt <= (others=>'0');
else
if bit_in_r_we = '1' or isflag_r = '1' then
bit_cnt <= bit_cnt + 1;
end if;
end if;
end if;
end process;
--
out_sr_rdy <= '1' when (bit_cnt = "111" and error_state = '0' and remove_zero_r = '0') else '0';
--
-------------------------------------------------------------------------------------------
--clock3+
-- output latch
-------------------------------------------------------------------------------------------
dataOUTrdy0_pulse: entity work.pulse_pdxx_pwxx (Behavioral) generic map(pd=>2,pw=>1) port map(bitCLKx4,isflag_r,dataOUTrdy0);
dataOUTrdy1_pulse: entity work.pulse_pdxx_pwxx (Behavioral) generic map(pd=>4,pw=>1) port map(bitCLKx4,out_sr_rdy,dataOUTrdy1);
--
dataOUTrdy_s <= dataOUTrdy0 or dataOUTrdy1;
dataOUTrdy <= dataOUTrdy_s or error_out_rdy_s;
--
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if edataIN /= "11" then
error_out <= '0';
elsif error_state = '1' then
error_out <= '1';
end if;
end if;
end process;
--
process(bitCLKx2, rst)
begin
if rst = '1' then
error_bit_cnt <= (others=>'0');
elsif bitCLKx2'event and bitCLKx2 = '1' then
if error_out = '0' then
error_bit_cnt <= (others=>'0');
else
error_bit_cnt <= error_bit_cnt + 1;
end if;
end if;
end process;
--
error_out_rdy <= '1' when (error_bit_cnt = "001" and error_out = '1') else '0';
error_out_rdy_pulse: entity work.pulse_pdxx_pwxx (Behavioral) generic map(pd=>0,pw=>1) port map(bitCLKx4,error_out_rdy,error_out_rdy_s);
--
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if error_state_r = '1' and isflag_r = '1' then
dataOUT(9 downto 8) <= "10"; -- sop
elsif error_state_r = '0' and isflag_r = '1' then
dataOUT(9 downto 8) <= "01"; -- eop
else
dataOUT(9 downto 8) <= error_out & error_out; -- data/error
end if;
--dataOUT(9 downto 8) <= isflag_r & (isflag_r and sop_marked);
end if;
end process;
--
dataOUT(7 downto 0) <= out_sr;
--
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if dataOUTrdy_s = '1' then
sop_marked <= isflag_rr; -- flag is sent
end if;
end if;
end process;
--
end Behavioral;
| gpl-3.0 | 972efdeeab38aa1144e397f9ee48ba89 | 0.473444 | 3.516981 | false | false | false | false |
tdotu/ra | sizeExtend.vhd | 1 | 473 | LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY sizeExtend IS
PORT
(
signd : IN std_logic;
input : IN std_logic_vector(15 downto 0);
output : OUT std_logic_vector(31 downto 0)
);
END sizeExtend;
ARCHITECTURE behavior OF sizeExtend IS
BEGIN
WITH signd SELECT
output <= (15 downto 0 => input, OTHERS => 0) WHEN '0',
(14 downto 0 => input(14 downto 0), OTHERS => input(15)) WHEN '1',
(OTHERS => '0') WHEN OTHERS;
END behavior; | gpl-3.0 | b91b2e8804a419c1d3013ad79cfb1c81 | 0.634249 | 3.051613 | false | false | false | false |
furrtek/portapack-havoc | hardware/portapack_h1/cpld/20170522/top.vhd | 2 | 5,324 | --
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
MCU_D : inout std_logic_vector(7 downto 0);
MCU_DIR : in std_logic;
MCU_IO_STBX : in std_logic;
MCU_LCD_WRX : in std_logic;
MCU_ADDR : in std_logic;
MCU_LCD_TE : out std_logic;
MCU_P2_8 : in std_logic;
MCU_LCD_RDX : in std_logic;
TP_U : out std_logic;
TP_D : out std_logic;
TP_L : out std_logic;
TP_R : out std_logic;
SW_SEL : in std_logic;
SW_ROT_A : in std_logic;
SW_ROT_B : in std_logic;
SW_U : in std_logic;
SW_D : in std_logic;
SW_L : in std_logic;
SW_R : in std_logic;
LCD_RESETX : out std_logic;
LCD_RS : out std_logic;
LCD_WRX : out std_logic;
LCD_RDX : out std_logic;
LCD_DB : inout std_logic_vector(15 downto 0);
LCD_TE : in std_logic;
LCD_BACKLIGHT : out std_logic;
AUDIO_RESETX : out std_logic;
REF_EN : out std_logic;
GPS_RESETX : out std_logic;
GPS_TX_READY : in std_logic;
GPS_TIMEPULSE : in std_logic
);
end top;
architecture rtl of top is
signal switches : std_logic_vector(7 downto 0);
type data_direction_t is (from_mcu, to_mcu);
signal data_dir : data_direction_t;
signal mcu_data_out_lcd : std_logic_vector(7 downto 0);
signal mcu_data_out_io : std_logic_vector(7 downto 0);
signal mcu_data_out : std_logic_vector(7 downto 0);
signal mcu_data_in : std_logic_vector(7 downto 0);
signal lcd_data_in : std_logic_vector(15 downto 0);
signal lcd_data_in_mux : std_logic_vector(7 downto 0);
signal lcd_data_out : std_logic_vector(15 downto 0);
signal lcd_data_in_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_data_out_q : std_logic_vector(7 downto 0) := (others => '0');
signal tp_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_reset_q : std_logic := '1';
signal lcd_backlight_q : std_logic := '0';
signal audio_reset_q : std_logic := '1';
signal ref_en_q : std_logic := '0';
signal dir_read : boolean;
signal dir_write : boolean;
signal lcd_read_strobe : boolean;
signal lcd_write_strobe : boolean;
signal lcd_write : boolean;
signal io_strobe : boolean;
signal io_read_strobe : boolean;
signal io_write_strobe : boolean;
begin
-- I/O data
switches <= LCD_TE & not SW_ROT_B & not SW_ROT_A & not SW_SEL & not SW_U & not SW_D & not SW_L & not SW_R;
TP_U <= tp_q(3) when tp_q(7) = '1' else 'Z';
TP_D <= tp_q(2) when tp_q(6) = '1' else 'Z';
TP_L <= tp_q(1) when tp_q(5) = '1' else 'Z';
TP_R <= tp_q(0) when tp_q(4) = '1' else 'Z';
LCD_BACKLIGHT <= lcd_backlight_q;
MCU_LCD_TE <= LCD_TE;
-- State management
data_dir <= to_mcu when MCU_DIR = '1' else from_mcu;
dir_read <= (data_dir = to_mcu);
dir_write <= (data_dir = from_mcu);
io_strobe <= (MCU_IO_STBX = '0');
io_read_strobe <= io_strobe and dir_read;
lcd_read_strobe <= (MCU_LCD_RDX = '0');
lcd_write <= not lcd_read_strobe;
-- LCD interface
LCD_RS <= MCU_ADDR;
LCD_RDX <= MCU_LCD_RDX;
LCD_WRX <= MCU_LCD_WRX;
lcd_data_out <= lcd_data_out_q & mcu_data_in;
lcd_data_in <= LCD_DB;
LCD_DB <= lcd_data_out when lcd_write else (others => 'Z');
-- Reference clock
REF_EN <= ref_en_q;
-- Peripheral reset control
LCD_RESETX <= not lcd_reset_q;
AUDIO_RESETX <= not audio_reset_q;
GPS_RESETX <= '1';
-- MCU interface
mcu_data_out_lcd <= lcd_data_in(15 downto 8) when lcd_read_strobe else lcd_data_in_q;
mcu_data_out_io <= switches;
mcu_data_out <= mcu_data_out_io when io_read_strobe else mcu_data_out_lcd;
mcu_data_in <= MCU_D;
MCU_D <= mcu_data_out when dir_read else (others => 'Z');
-- Synchronous behaviors:
-- LCD write: Capture LCD high byte on LCD_WRX falling edge.
process(MCU_LCD_WRX, mcu_data_in)
begin
if falling_edge(MCU_LCD_WRX) then
lcd_data_out_q <= mcu_data_in;
end if;
end process;
-- LCD read: Capture LCD low byte on LCD_RD falling edge.
process(MCU_LCD_RDX, lcd_data_in)
begin
if rising_edge(MCU_LCD_RDX) then
lcd_data_in_q <= lcd_data_in(7 downto 0);
end if;
end process;
-- I/O write (to resistive touch panel): Capture data from
-- MCU and hold on TP pins until further notice.
process(MCU_IO_STBX, dir_write, mcu_data_in, MCU_ADDR)
begin
if rising_edge(MCU_IO_STBX) and dir_write then
if MCU_ADDR = '0' then
tp_q <= mcu_data_in;
else
lcd_reset_q <= mcu_data_in(0);
audio_reset_q <= mcu_data_in(1);
ref_en_q <= mcu_data_in(6);
lcd_backlight_q <= mcu_data_in(7);
end if;
end if;
end process;
end rtl;
| gpl-2.0 | 8973ce69f3cfed6a7c3a7f2b422d52fb | 0.64444 | 2.528015 | false | false | false | false |
HackLinux/ION | src/rtl/cpu/ion_cpu.vhdl | 1 | 51,940 | --------------------------------------------------------------------------------
-- ion_cpu.vhdl -- MIPS32r2(tm) compatible CPU core
--------------------------------------------------------------------------------
-- project: ION (http://www.opencores.org/project,ion_cpu)
-- author: Jose A. Ruiz ([email protected])
-- author: Paul Debayan ([email protected])
--------------------------------------------------------------------------------
-- FIXME refactor comments!
--
-- Please read file /doc/ion_project.txt for usage instructions.
--
--------------------------------------------------------------------------------
-- REFERENCES
-- [1] doc/ion_core_ds.pdf -- ION core datasheet .
-- [2] doc/ion_notes.pdf -- Design notes.
--------------------------------------------------------------------------------
--
--### Things with provisional implementation
--
-- 1.- Invalid instruction side effects:
-- Invalid opcodes do trap but the logic that prevents bad opcodes from
-- having side affects has not been tested yet.
-- 2.- Kernel/user status.
-- When in user mode, COP* instructions will trigger a 'CpU' exception.
-- BUT there's no address checking and user code can still access kernel
-- space in this version.
--
--------------------------------------------------------------------------------
-- KNOWN BUGS:
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ion_cpu is
generic(
-- Type of memory to be used for register bank in xilinx HW
XILINX_REGBANK : string := "distributed" -- {distributed|block}
);
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
DATA_MOSI_O : out t_cpumem_mosi;
DATA_MISO_I : in t_cpumem_miso;
CODE_MOSI_O : out t_cpumem_mosi;
CODE_MISO_I : in t_cpumem_miso;
CACHE_CTRL_MOSI_O : out t_cache_mosi; -- Common control MOSI port.
ICACHE_CTRL_MISO_I : in t_cache_miso; -- I-Cache MISO.
DCACHE_CTRL_MISO_I : in t_cache_miso; -- D-Cache MISO.
COP2_MOSI_O : out t_cop2_mosi; -- COP2 interface.
COP2_MISO_I : in t_cop2_miso;
IRQ_I : in std_logic_vector(5 downto 0)
);
end; --entity ion_cpu
architecture rtl of ion_cpu is
--------------------------------------------------------------------------------
-- Memory interface
signal mem_wait : std_logic;
signal data_rd : t_word;
signal data_rd_reg : t_word;
--------------------------------------------------------------------------------
-- Pipeline stage 0
signal p0_pc_reg : t_pc;
signal p0_pc_incremented : t_pc;
signal p0_pc_jump : t_pc;
signal p0_pc_branch : t_pc;
signal p0_pc_target : t_pc;
signal p0_pc_restart : t_pc;
signal p0_pc_load_pending : std_logic;
signal p0_pc_increment : std_logic;
signal p0_pc_next : t_pc;
signal p0_rs_num : t_regnum;
signal p0_rt_num : t_regnum;
signal p0_jump_cond_value : std_logic;
signal p0_rbank_rs_hazard : std_logic;
signal p0_rbank_rt_hazard : std_logic;
--------------------------------------------------------------------------------
-- Pipeline stage 1
signal p1_rbank : t_rbank := (others => X"00000000");
-- IMPORTANT: This attribute is used by Xilinx tools to select how to implement
-- the register bank. If we don't use it, by default XST would infer 2 BRAMs for
-- the 1024-bit 3-port reg bank, which you probably don't want.
-- This can take the values {distributed|block}.
attribute ram_style : string;
attribute ram_style of p1_rbank : signal is XILINX_REGBANK;
signal p1_rs, p1_rt : t_word;
signal p1_rs_rbank : t_word;
signal p1_rt_rbank : t_word;
signal p1_rbank_forward : t_word;
signal p1_rd_num : t_regnum;
signal p1_c0_rs_num : t_regnum;
signal p1_rbank_wr_addr : t_regnum;
signal p1_rbank_we : std_logic;
signal p1_rbank_wr_data : t_word;
signal p1_alu_inp1 : t_word;
signal p1_alu_inp2 : t_word;
signal p1_alu_outp : t_word;
-- ALU control inputs (shortened name for brevity in expressions)
signal p1_ac : t_alu_control;
-- ALU flag outputs (comparison results)
signal p1_alu_flags : t_alu_flags;
-- immediate data, sign- or zero-extended as required by IR
signal p1_data_imm : t_word;
signal p1_branch_offset : t_pc;
signal p1_branch_offset_sex:std_logic_vector(31 downto 18);
signal p1_rbank_rs_hazard : std_logic;
signal p1_rbank_rt_hazard : std_logic;
signal p1_jump_type_set0 : std_logic_vector(1 downto 0);
signal p1_jump_type_set1 : std_logic_vector(1 downto 0);
signal p1_ir_reg : std_logic_vector(31 downto 0);
signal p1_ir_op : std_logic_vector(31 downto 26);
signal p1_ir_fmt : std_logic_vector(25 downto 21);
signal p1_ir_fn : std_logic_vector(5 downto 0);
signal p1_op_special : std_logic;
signal p1_op_special2 : std_logic;
signal p1_exception : std_logic;
signal p1_do_reg_jump : std_logic;
signal p1_do_zero_ext_imm : std_logic;
signal p1_set_cp : std_logic;
signal p1_get_cp : std_logic;
signal p1_set_cp0 : std_logic;
signal p1_get_cp0 : std_logic;
signal p1_set_cp2 : std_logic;
signal p1_get_cp2 : std_logic;
signal p1_rfe : std_logic;
signal p1_eret : std_logic;
signal p1_alu_op2_sel : std_logic_vector(1 downto 0);
signal p1_alu_op2_sel_set0: std_logic_vector(1 downto 0);
signal p1_alu_op2_sel_set1: std_logic_vector(1 downto 0);
signal p1_do_load : std_logic;
signal p1_do_store : std_logic;
signal p1_sw_data : t_word;
signal p1_store_size : std_logic_vector(1 downto 0);
signal p1_we_control : std_logic_vector(5 downto 0);
signal p1_load_alu : std_logic;
signal p1_load_alu_set0 : std_logic;
signal p1_load_alu_set1 : std_logic;
signal p1_ld_upper_hword : std_logic;
signal p1_ld_upper_byte : std_logic;
signal p1_ld_unsigned : std_logic;
signal p1_jump_type : std_logic_vector(1 downto 0);
signal p1_link : std_logic;
signal p1_jump_cond_sel : std_logic_vector(2 downto 0);
signal p1_data_addr : t_addr;
signal p1_data_offset : t_addr;
signal p1_muldiv_result : t_word;
signal p1_muldiv_func : t_mult_function;
signal p1_special_ir_fn : std_logic_vector(7 downto 0);
signal p1_muldiv_dontdisturb : std_logic;
signal p1_muldiv_running : std_logic;
signal p1_muldiv_started : std_logic;
signal p1_muldiv_stall : std_logic;
signal p1_unknown_opcode : std_logic;
signal p1_cp_unavailable : std_logic;
signal p1_hw_irq : std_logic;
signal p1_hw_irq_pending : std_logic;
signal p0_irq_reg : std_logic_vector(5 downto 0);
signal irq_masked : std_logic_vector(5 downto 0);
--------------------------------------------------------------------------------
-- Pipeline stage 2
signal p2_muldiv_started : std_logic;
signal p2_exception : std_logic;
signal p2_rd_addr : std_logic_vector(1 downto 0);
signal p2_rd_mux_control : std_logic_vector(3 downto 0);
signal p2_load_target : t_regnum;
signal p2_do_load : std_logic;
signal p2_ld_upper_hword : std_logic;
signal p2_ld_upper_byte : std_logic;
signal p2_ld_unsigned : std_logic;
signal p2_wback_mux_sel : std_logic_vector(1 downto 0);
signal p2_wback_cop_sel : std_logic;
signal p2_cop_data_rd : t_word;
signal p2_data_word_rd : t_word;
signal p2_data_word_ext : std_logic;
signal p2_load_pending : std_logic;
--------------------------------------------------------------------------------
-- Global control signals
signal load_interlock : std_logic;
-- stall pipeline for any reason
signal stall_pipeline : std_logic;
-- pipeline is stalled for any reason
signal pipeline_stalled : std_logic;
-- pipeline is stalled because CODE or DATA buses are waited
signal stalled_memwait : std_logic;
-- pipeline is stalled because we´re waiting for the mul/div unit result
signal stalled_muldiv : std_logic;
-- pipeline is stalled because of a load instruction interlock
signal stalled_interlock : std_logic;
signal reset_done : std_logic_vector(1 downto 0);
--------------------------------------------------------------------------------
-- CP0 interface signals
signal cp0_mosi : t_cop0_mosi;
signal cp0_miso : t_cop0_miso;
begin
--##############################################################################
-- Register bank & datapath
-- Register indices are 'decoded' out of the instruction word BEFORE loading IR
p0_rs_num <= std_logic_vector(CODE_MISO_I.rd_data(25 downto 21));
with p1_ir_reg(31 downto 26) select p1_rd_num <=
p1_ir_reg(15 downto 11) when "000000",
p1_ir_reg(20 downto 16) when others;
-- This is also called rs2 in the docs
p0_rt_num <= std_logic_vector(CODE_MISO_I.rd_data(20 downto 16));
--------------------------------------------------------------------------------
-- Data input register and input shifter & masker (LB,LBU,LH,LHU,LW)
-- If data can't be latched from the bus when it´s valid due to a stall, it will
-- be registered here.
data_input_register:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if p2_load_pending='1' and DATA_MISO_I.mwait='0' then
data_rd_reg <= DATA_MISO_I.rd_data;
end if;
end if;
end process data_input_register;
-- Data input mux:
data_rd <=
-- If pipeline was stalled when data was valid, use registered value...
data_rd_reg when (p2_do_load='1') and p2_load_pending='0' else
-- ...otherwise get the data straight from the data bus.
DATA_MISO_I.rd_data;
-- Byte and half-word shifter control.
p2_rd_mux_control <= p2_ld_upper_hword & p2_ld_upper_byte & p2_rd_addr;
-- Extension for unused bits will be zero or the sign (bit 7 or bit 15)
p2_data_word_ext <= '0' when p2_ld_unsigned='1' else
-- LH
data_rd(31) when p2_ld_upper_byte='1' and p2_rd_addr="00" else
data_rd(15) when p2_ld_upper_byte='1' and p2_rd_addr="10" else
-- LB
data_rd(7) when p2_rd_addr="11" else
data_rd(15) when p2_rd_addr="10" else
data_rd(23) when p2_rd_addr="01" else
data_rd(31);
-- byte 0 may come from any of the 4 bytes of the input word
with p2_rd_mux_control select p2_data_word_rd(7 downto 0) <=
data_rd(31 downto 24) when "0000",
data_rd(23 downto 16) when "0001",
data_rd(23 downto 16) when "0100",
data_rd(15 downto 8) when "0010",
data_rd( 7 downto 0) when others;
-- byte 1 may come from input bytes 1 or 3 or may be extended for LB, LBU
with p2_rd_mux_control select p2_data_word_rd(15 downto 8) <=
data_rd(31 downto 24) when "0100",
data_rd(15 downto 8) when "0110",
data_rd(15 downto 8) when "1100",
data_rd(15 downto 8) when "1101",
data_rd(15 downto 8) when "1110",
data_rd(15 downto 8) when "1111",
(others => p2_data_word_ext) when others;
-- bytes 2,3 come straight from input or are extended for LH,LHU
with p2_ld_upper_hword select p2_data_word_rd(31 downto 16) <=
(others => p2_data_word_ext) when '0',
data_rd(31 downto 16) when others;
--------------------------------------------------------------------------------
-- Reg bank input multiplexor
-- Select which data is to be written back to the reg bank and where
p1_rbank_wr_addr <= p1_rd_num when p2_do_load='0' and p1_link='0' else
"11111" when p2_do_load='0' and p1_link='1' else
p2_load_target;
p2_wback_mux_sel <=
"00" when p2_do_load='0' and p1_get_cp='0' and p1_link='0' else
"01" when p2_do_load='1' and p1_get_cp='0' and p1_link='0' else
"10" when p2_do_load='0' and p1_get_cp0='1' and p1_link='0' else
"10" when p2_do_load='0' and p1_get_cp2='1' and p1_link='0' else
"11";
p2_wback_cop_sel <= '1' when p1_get_cp2='1' else '0';
with (p2_wback_mux_sel) select p1_rbank_wr_data <=
p1_alu_outp when "00",
p2_data_word_rd when "01",
p0_pc_incremented & "00" when "11",
p2_cop_data_rd when others;
with p2_wback_cop_sel select p2_cop_data_rd <=
COP2_MISO_I.data when '1',
cp0_miso.data when others;
--------------------------------------------------------------------------------
-- Register bank RAM & Rbank WE logic
-- Write data back onto the register bank in P1 stage of regular instructions
-- or in P2 stage of load instructions...
p1_rbank_we <= '1' when (p2_do_load='1' or p1_load_alu='1' or p1_link='1' or
-- ...EXCEPT in some cases:
-- If mfc* triggers privilege trap, don't load reg.
(p1_get_cp0='1' and p1_cp_unavailable='0') or
(p1_get_cp2='1' and p1_cp_unavailable='0')
) and
-- If target register is $zero, ignore write.
p1_rbank_wr_addr/="00000" and
-- If pipeline is stalled for any reason, ignore write.
stall_pipeline='0' and
-- On exception, abort next instruction (by preventing
-- regbank writeback).
p2_exception='0'
else '0';
-- Register bank as triple-port RAM. Should synth to 2 BRAMs unless you use
-- synth attributes to prevent it (see 'ram_style' attribute above) or your
-- FPGA has 3-port BRAMS, or has none.
synchronous_reg_bank:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if p1_rbank_we='1' then
p1_rbank(conv_integer(p1_rbank_wr_addr)) <= p1_rbank_wr_data;
end if;
-- the rbank read port loads in the same conditions as the IR: don't
-- update Rs or Rt if the pipeline is frozen
if stall_pipeline='0' then
p1_rt_rbank <= p1_rbank(conv_integer(p0_rt_num));
p1_rs_rbank <= p1_rbank(conv_integer(p0_rs_num));
end if;
end if;
end process synchronous_reg_bank;
--------------------------------------------------------------------------------
-- Reg bank 'writeback' data forwarding
-- Register writeback data in a DFF in case it needs to be forwarded.
data_forward_register:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if p1_rbank_we='1' then -- no need to check for stall cycles
p1_rbank_forward <= p1_rbank_wr_data;
end if;
end if;
end process data_forward_register;
-- Bypass sync RAM if we're reading and writing to the same address. This saves
-- 1 stall cycle and fixes the data hazard.
p0_rbank_rs_hazard <= '1' when p1_rbank_wr_addr=p0_rs_num and p1_rbank_we='1'
else '0';
p0_rbank_rt_hazard <= '1' when p1_rbank_wr_addr=p0_rt_num and p1_rbank_we='1'
else '0';
p1_rs <= p1_rs_rbank when p1_rbank_rs_hazard='0' else p1_rbank_forward;
p1_rt <= p1_rt_rbank when p1_rbank_rt_hazard='0' else p1_rbank_forward;
--------------------------------------------------------------------------------
-- ALU & ALU input multiplexors
p1_alu_inp1 <= p1_rs;
with p1_alu_op2_sel select p1_alu_inp2 <=
p1_data_imm when "11",
p1_muldiv_result when "01",
--p1_muldiv_result when "10", -- FIXME mux input wasted!
p1_rt when others;
alu_inst : entity work.ION_ALU
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
AC_I => p1_ac,
FLAGS_O => p1_alu_flags,
OP1_I => p1_alu_inp1,
OP2_I => p1_alu_inp2,
RES_O => p1_alu_outp
);
--------------------------------------------------------------------------------
-- Mul/Div block interface
-- Compute the mdiv block function word. If p1_muldiv_func has any value other
-- than MULT_NOTHING a new mdiv operation will start, truncating whatever other
-- operation that may have been in course; which we don't want.
-- So we encode here the function to be performed and make sure the value stays
-- there for only one cycle (the first ALU cycle of the mul/div instruction).
-- (this is what p1_muldiv_dontdisturb is meant to accomplish.)
-- This will eventually be refactored along with the muldiv module.
p1_muldiv_dontdisturb <= (p2_muldiv_started or p1_muldiv_running);
p1_special_ir_fn(7 downto 6) <=
"10" when p1_op_special='1' and p1_muldiv_dontdisturb='0' else
"11" when p1_op_special2='1' and p1_muldiv_dontdisturb='0' else
"00";
p1_special_ir_fn(5 downto 0) <= p1_ir_fn;
with p1_special_ir_fn select p1_muldiv_func <=
MULT_READ_LO when "10010010",
MULT_READ_HI when "10010000",
MULT_WRITE_LO when "10010011",
MULT_WRITE_HI when "10010001",
MULT_MULT when "10011001",
MULT_SIGNED_MULT when "10011000",
MULT_DIVIDE when "10011011",
MULT_SIGNED_DIVIDE when "10011010",
--MULT_MADDU when "11000000",
--MULT_MADD when "11000001",
MULT_NOTHING when others;
mult_div: entity work.ION_MULDIV
port map (
A_I => p1_rs,
B_I => p1_rt,
C_MULT_O => p1_muldiv_result,
PAUSE_O => p1_muldiv_running,
MULT_FN_I => p1_muldiv_func,
CLK_I => CLK_I,
RESET_I => RESET_I
);
-- Active only for the 1st ALU cycle of any mul/div instruction
p1_muldiv_started <= '1' when p1_op_special='1' and
p1_ir_fn(5 downto 3)="011" and
--
p1_muldiv_running='0'
else '0';
-- Stall the pipeline to enable mdiv operation completion.
-- We need p2_muldiv_started to distinguish the cycle before p1_muldiv_running
-- is asserted and the cycle after it deasserts.
-- Otherwise we would reexecute the same muldiv endlessly instruction after
-- deassertion of p1_muldiv_running, since the IR was stalled and still contains
-- the mul opcode...
p1_muldiv_stall <= '1' when
-- Active for the cycle immediately before p1_muldiv_running asserts
-- and NOT for the cycle after it deasserts
(p1_muldiv_started='1' and p2_muldiv_started='0') or
-- Active until operation is complete
p1_muldiv_running = '1'
else '0';
--##############################################################################
-- PC register and branch logic
-- p0_pc_reg will not be incremented on stall cycles
p0_pc_increment <=
'1' when stall_pipeline='0' and p0_pc_load_pending='0'
else '0';
--p0_pc_incremented <= p0_pc_reg + (not stall_pipeline);
p0_pc_incremented <= p0_pc_reg + p0_pc_increment;
-- main pc mux: jump or continue
p0_pc_next <=
cp0_miso.pc_load_value when
cp0_miso.pc_load_en='1' and stall_pipeline='0'
else p0_pc_target when
-- We jump on jump instructions whose condition is met...
((p1_jump_type(1)='1' and p0_jump_cond_value='1' and
-- ...except we abort any jump that follows the victim of an exception
p2_exception='0'))
-- We jump on exceptions too...
-- ... but we only jump at all if the pipeline is not stalled
and stall_pipeline='0'
else p0_pc_incremented;
-- Compute the restart address for this instruction.
-- TODO evaluate cost of this and maybe simplify.
p0_pc_restart <=
p0_pc_reg -1 when -- EPC = Instruction BEFORE jump instruction...
-- ...when the jump conditions are met.
((p1_jump_type(1)='1' and p0_jump_cond_value='1' and
p2_exception='0'))
and stall_pipeline='0'
-- Otherwise EPC points to the next instruction.
else p0_pc_reg + 1;--p0_pc_incremented;
-- Flag p0_pc_load_pending inhibits PC increment when set; this is used to
-- prevent spurious PC increments while an exception is pending.
-- This is a nasty hach that should be refactored...
pc_load_pending_fsm:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
p0_pc_load_pending <= '0';
else
if cp0_miso.pc_load_en='1' and stall_pipeline='1' then
p0_pc_load_pending <= '1';
elsif stall_pipeline='0' and reset_done(0)='1' then
p0_pc_load_pending <= '0';
end if;
end if;
end if;
end process pc_load_pending_fsm;
pc_register:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if cp0_miso.pc_load_en='1' then
-- Load PC with value from COP0: exception vector or ret address.
p0_pc_reg <= cp0_miso.pc_load_value;
else
-- p0_pc_reg holds the same value as external sync ram addr reg
p0_pc_reg <= p0_pc_next;
-- pc_restart = addr saved to EPC on interrupts (@note2)
-- It's the addr of the instruction that "follows" the victim,
-- except when the triggering instruction is in a delay slot. In
-- that case, it the instruction preceding the victim.
-- I.e. all as per the mips32r2 specs.
cp0_mosi.pc_restart <= p0_pc_restart;
end if;
-- Remember if we are in delay slot, in case there's a trap
if (p1_jump_type="00" or p0_jump_cond_value='0') then
cp0_mosi.in_delay_slot <= '0'; -- NOT in a delay slot
else
cp0_mosi.in_delay_slot <= '1'; -- in a delay slot
end if;
end if;
end process pc_register;
-- Common rd/wr address; lowest 2 bits are output as debugging aid only
DATA_MOSI_O.addr <= p1_data_addr(31 downto 0);
-- 'Memory enable' signals for both memory interfaces
DATA_MOSI_O.rd_en <= (p1_do_load) and not pipeline_stalled;
CODE_MOSI_O.rd_en <= (not stall_pipeline) and reset_done(0);
CODE_MOSI_O.wr_be <= "0000";
CODE_MOSI_O.wr_data <= (others => '0');
-- FIXME reset_done should come from COP0
-- reset_done will be asserted after the RESET_I process is finished, when the
-- CPU can start operating normally.
-- We only use it to make sure CODE_MOSI_O.rd_en is not asserted prematurely.
wait_for_end_of_reset:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
reset_done <= "00";
else
reset_done(1) <= reset_done(0);
reset_done(0) <= '1';
end if;
end if;
end process wait_for_end_of_reset;
-- The final value used to access code memory
CODE_MOSI_O.addr(31 downto 2) <= p0_pc_next;
CODE_MOSI_O.addr(1 downto 0) <= "00";
-- compute target of J/JR instructions
p0_pc_jump <= p1_rs(31 downto 2) when p1_do_reg_jump='1' else
p0_pc_reg(31 downto 28) & p1_ir_reg(25 downto 0);
-- compute target of relative branch instructions
p1_branch_offset_sex <= (others => p1_ir_reg(15));
p1_branch_offset <= p1_branch_offset_sex & p1_ir_reg(15 downto 0);
-- p0_pc_reg is the addr of the instruction in delay slot
p0_pc_branch <= p0_pc_reg + p1_branch_offset;
-- decide which jump target is to be used
p0_pc_target <=
p0_pc_jump when p1_jump_type(0)='1' else
p0_pc_branch;
--##############################################################################
-- Instruction decoding and IR
instruction_register:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
p1_ir_reg <= (others => '0');
elsif reset_done(1)='1' then
-- Load the IR with whatever the cache is giving us, provided:
-- 1) The cache is ready (i.e. has already completed the first code
-- refill after RESET_I.
-- 2) The CPU has completed its reset sequence.
-- 3) The pipeline is not stalled (@note4).
if stall_pipeline='0' then
p1_ir_reg <= CODE_MISO_I.rd_data;
end if;
end if;
end if;
end process instruction_register;
-- Zero extension/Sign extension of instruction immediate data
p1_data_imm(15 downto 0) <= p1_ir_reg(15 downto 0);
with p1_do_zero_ext_imm select p1_data_imm(31 downto 16) <=
(others => '0') when '1',
(others => p1_ir_reg(15)) when others;
-- 'Extract' main fields from IR, for convenience
p1_ir_op <= p1_ir_reg(31 downto 26);
p1_ir_fmt <= p1_ir_reg(25 downto 21);
p1_ir_fn <= p1_ir_reg(5 downto 0);
-- Decode jump type, if any, for instructions with op/=0
with p1_ir_op select p1_jump_type_set0 <=
-- FIXME verify that we actually weed out ALL invalid instructions
"10" when "000001", -- BLTZ, BGEZ, BLTZAL, BGTZAL
"11" when "000010", -- J
"11" when "000011", -- JAL
"10" when "000100", -- BEQ
"10" when "010100", -- BEQL
"10" when "000101", -- BNE
"10" when "010101", -- BNEL
"10" when "000110", -- BLEZ
"10" when "000111", -- BGTZ
"00" when others; -- no jump
-- Decode jump type, if any, for instructions with op=0
p1_jump_type_set1 <= "11" when p1_op_special='1' and
p1_ir_reg(5 downto 1)="00100"
else "00";
-- Decode jump type for the instruction in IR (composite of two formats)
p1_jump_type <= p1_jump_type_set0 or p1_jump_type_set1;
p1_link <= '1' when (p1_ir_op="000000" and p1_ir_reg(5 downto 0)="001001") or
(p1_ir_op="000001" and p1_ir_reg(20)='1') or
(p1_ir_op="000011")
else '0';
-- Decode jump condition: encode a mux control signal from IR...
p1_jump_cond_sel <=
"001" when p1_ir_op="000001" and p1_ir_reg(16)='0' else -- op1 < 0 BLTZ*
"101" when p1_ir_op="000001" and p1_ir_reg(16)='1' else -- !(op1 < 0) BNLTZ*
"010" when p1_ir_op="000100" else -- op1 == op2 BEQ
"010" when p1_ir_op="010100" else -- op1 == op2 BEQL
"110" when p1_ir_op="000101" else -- !(op1 == op2) BNE
"110" when p1_ir_op="010101" else -- !(op1 == op2) BNEL
"011" when p1_ir_op="000110" else -- op1 <= 0 BLEZ
"111" when p1_ir_op="000111" else -- !(op1 <= 0) BGTZ
"000"; -- always
-- ... and use mux control signal to select the condition value
with p1_jump_cond_sel select p0_jump_cond_value <=
p1_alu_flags.inp1_lt_zero when "001",
not p1_alu_flags.inp1_lt_zero when "101",
p1_alu_flags.inp1_eq_inp2 when "010",
not p1_alu_flags.inp1_eq_inp2 when "110",
(p1_alu_flags.inp1_lt_inp2 or
p1_alu_flags.inp1_eq_inp2) when "011",
not (p1_alu_flags.inp1_lt_inp2 or
p1_alu_flags.inp1_eq_inp2) when "111",
'1' when others;
-- Decode instructions that launch exceptions
p1_exception <= '1' when
(p1_op_special='1' and p1_ir_reg(5 downto 1)="00110") or -- syscall/break
p1_unknown_opcode='1' or
p1_cp_unavailable='1' or
p1_hw_irq='1'
else '0';
-- Decode MTC0/MFC0 instructions (see @note3)
p1_set_cp <=
'1' when p1_ir_reg(31 downto 26)="010000" and p1_ir_fmt="00100" else -- MTC0
'1' when p1_ir_reg(31 downto 26)="010010" and p1_ir_fmt="00100" else -- MTC2
'1' when p1_ir_reg(31 downto 26)="010010" and p1_ir_fmt="00110" else -- CTC2
'0';
p1_get_cp <=
'1' when p1_ir_reg(31 downto 26)="010000" and p1_ir_fmt="00000" else -- MFC0
'1' when p1_ir_reg(31 downto 26)="010010" and p1_ir_fmt="00000" else -- MFC2
'1' when p1_ir_reg(31 downto 26)="010010" and p1_ir_fmt="00010" else -- CFC2
'0';
p1_set_cp0 <= '1' when p1_ir_reg(27 downto 26)="00" and p1_set_cp='1' else '0';
p1_get_cp0 <= '1' when p1_ir_reg(27 downto 26)="00" and p1_get_cp='1' else '0';
p1_set_cp2 <= '1' when p1_ir_reg(27 downto 26)="10" and p1_set_cp='1' else '0';
p1_get_cp2 <= '1' when p1_ir_reg(27 downto 26)="10" and p1_get_cp='1' else '0';
-- Decode RFE instruction (see @note3)
p1_rfe <= '1' when p1_ir_reg(31 downto 21)="01000010000" and
p1_ir_reg(5 downto 0)="010000"
else '0';
p1_eret <= '1' when p1_ir_reg(31 downto 21)="01000010000" and
p1_ir_reg(5 downto 0)="011000"
else '0';
-- Raise some signals for some particular group of opcodes
p1_op_special <= '1' when p1_ir_op="000000" else '0'; -- group '0' opcodes
p1_op_special2 <= '1' when p1_ir_op="011100" else '0'; -- 'special 2' opcodes
p1_do_reg_jump <= '1' when p1_op_special='1' and p1_ir_fn(5 downto 1)="00100" else '0';
p1_do_zero_ext_imm <=
'1' when (p1_ir_op(31 downto 28)="0011") else -- ANDI, ORI, XORI, LUI
'1' when (p1_ir_op(31 downto 26)="001011") else -- SLTIU
'0'; -- NOTE that ADDIU *does* sign extension.
-- Decode input data mux control (LW, LH, LB, LBU, LHU) and load enable
p1_do_load <= '1' when
p1_ir_op(31 downto 29)="100" and
p1_ir_op(28 downto 26)/="010" and -- LWL
p1_ir_op(28 downto 26)/="110" and -- LWR
p1_ir_op(28 downto 26)/="111" and -- LWR
p2_exception='0' -- abort load if previous instruction triggered trap
else '0';
p1_load_alu_set0 <= '1'
when p1_op_special='1' and
((p1_ir_op(31 downto 29)="000" and p1_ir_op(27 downto 26)="00") or
(p1_ir_op(31 downto 29)="000" and p1_ir_op(27 downto 26)="10") or
(p1_ir_op(31 downto 29)="000" and p1_ir_op(27 downto 26)="11") or
(p1_ir_op(31 downto 29)="000" and p1_ir_op(27 downto 26)="00") or
(p1_ir_op(31 downto 28)="0100" and p1_ir_op(27 downto 26)="00") or
(p1_ir_op(31 downto 28)="0100" and p1_ir_op(27 downto 26)="10") or
(p1_ir_op(31 downto 28)="1000") or
(p1_ir_op(31 downto 28)="1001") or
(p1_ir_op(31 downto 28)="1010" and p1_ir_op(27 downto 26)="10") or
(p1_ir_op(31 downto 28)="1010" and p1_ir_op(27 downto 26)="11") or
(p1_ir_op(31 downto 28)="0010" and p1_ir_op(27 downto 26)="01"))
else '0';
with p1_ir_op select p1_load_alu_set1 <=
'1' when "001000", -- addi
'1' when "001001", -- addiu
'1' when "001010", -- slti
'1' when "001011", -- sltiu
'1' when "001100", -- andi
'1' when "001101", -- ori
'1' when "001110", -- xori
'1' when "001111", -- lui
'0' when others;
p1_load_alu <= (p1_load_alu_set0 or p1_load_alu_set1) and
not p1_unknown_opcode;
p1_ld_upper_hword <= p1_ir_op(27); -- use input upper hword vs. sign extend/zero
p1_ld_upper_byte <= p1_ir_op(26); -- use input upper byte vs. sign extend/zero
p1_ld_unsigned <= p1_ir_op(28); -- sign extend vs. zero extend
-- ALU input-2 selection: use external data for 2x opcodes (loads)
p1_alu_op2_sel_set0 <=
"11" when p1_ir_op(31 downto 30)="10" or p1_ir_op(29)='1' else
"00";
-- ALU input-2 selection: use registers Hi and Lo for MFHI, MFLO
p1_alu_op2_sel_set1 <=
"01" when p1_op_special='1' and (p1_ir_fn="010000" or p1_ir_fn="010010")
else "00";
-- ALU input-2 final selection
p1_alu_op2_sel <= p1_alu_op2_sel_set0 or p1_alu_op2_sel_set1;
-- Decode store operations
p1_do_store <= '1' when
p1_ir_op(31 downto 29)="101" and
(p1_ir_op(28 downto 26)="000" or -- SB
p1_ir_op(28 downto 26)="001" or -- SH
p1_ir_op(28 downto 26)="011") and -- SWH
p2_exception='0' -- abort when previous instruction triggered exception
else '0';
p1_store_size <= p1_ir_op(27 downto 26);
-- Extract source and destination C0 register indices
p1_c0_rs_num <= p1_ir_reg(15 downto 11);
-- Decode ALU control signals
p1_ac.use_slt <= '1' when
(p1_ir_op="000001" and p1_ir_reg(20 downto 16)="01000") or -- TGEI (?)
(p1_ir_op="000000" and p1_ir_reg(5 downto 1)="10101") or -- SLT, SLTU
p1_ir_op="001010" or -- SLTI
p1_ir_op="001011" -- SLTIU
else '0';
p1_ac.arith_unsigned <= p1_ac.use_slt and (p1_ir_reg(0) or p1_ir_op(26));
p1_ac.use_logic(0) <= '1' when (p1_op_special='1' and p1_ir_fn(5 downto 3)/="000") or
-- all immediate arith and logic
p1_ir_op(31 downto 29)="001"
else '0';
p1_ac.use_logic(1) <= '1' when (p1_op_special='1' and p1_ir_fn="100111") else '0';
p1_ac.use_arith <= '1' when p1_ir_op(31 downto 28)="0010" or
(p1_op_special='1' and
(p1_ir_fn(5 downto 2)="1000" or
p1_ir_fn(5 downto 2)="1010"))
else '0';
-- selection of 2nd internal alu operand: {i2, /i2, i2<<16, 0x0}
p1_ac.neg_sel(1)<= '1' when p1_ir_op(29 downto 26) = "1111" else '0';
p1_ac.neg_sel(0)<= '1' when p1_ir_op="001010" or
p1_ir_op="001011" or
p1_ir_op(31 downto 28)="0001" or
(p1_op_special='1' and
(p1_ir_fn="100010" or
p1_ir_fn="100011" or
p1_ir_fn(5 downto 2)="1010"))
else '0';
p1_ac.cy_in <= p1_ac.neg_sel(0);
p1_ac.shift_sel <= p1_ir_fn(1 downto 0);
p1_ac.logic_sel <= "00" when (p1_op_special='1' and p1_ir_fn="100100") else
"01" when (p1_op_special='1' and p1_ir_fn="100101") else
"10" when (p1_op_special='1' and p1_ir_fn="100110") else
"01" when (p1_op_special='1' and p1_ir_fn="100111") else
"00" when (p1_ir_op="001100") else
"01" when (p1_ir_op="001101") else
"10" when (p1_ir_op="001110") else
"11";
p1_ac.shift_amount <= p1_ir_reg(10 downto 6) when p1_ir_fn(2)='0' else p1_rs(4 downto 0);
--------------------------------------------------------------------------------
-- Decoding of CACHE instruction functions
with p1_ir_op select CACHE_CTRL_MOSI_O.function_en <=
'1' when "101111",
'0' when others;
with p1_ir_reg(20 downto 16) select CACHE_CTRL_MOSI_O.function_code <=
"001" when "00000", -- I Index Invalidate
"001" when "00001", -- D Index Invalidate
"010" when "01000", -- I Index Store Tag
"010" when "01001", -- D Index Store Tag
"101" when "10000", -- I Hit Invalidate
"101" when "10001", -- D Hit Invalidate
"100" when "10101", -- D Hit Writeback Invalidate
"000" when others;
CACHE_CTRL_MOSI_O.data_cache <= p1_ir_reg(16); -- 0 for I, 1 for D.
--------------------------------------------------------------------------------
-- Decoding of unimplemented and privileged instructions
-- NOTE: This is a MIPS-I CPU transitioning into a MIPS32r2, therefore the
-- unimplemented set is going to change over time.
-- Unimplemented instructions include:
-- 1.- All instructions above architecture MIPS-I except:
-- 1.1.- eret
-- 2.- Unaligned stores and loads (LWL,LWR,SWL,SWR)
-- 3.- All CP0 instructions other than mfc0 and mtc0
-- 4.- All CPi instructions
-- For the time being, we'll decode them all together.
-- FIXME: some of these should trap but others should just NOP (e.g. EHB)
p1_unknown_opcode <= '1' when
-- decode by 'opcode' field
--(p1_ir_op(31 downto 29)="110" and
-- p1_ir_op(28 downto 26)/="010") or -- LWC2 is valid
--(p1_ir_op(31 downto 29)="111" and
-- p1_ir_op(28 downto 26)/="010") or -- SWC2 is valid
(p1_ir_op(31 downto 29)="010" and
(p1_ir_op(28 downto 26)/="000" and -- COP0 is valid
p1_ir_op(28 downto 26)/="100" and -- BEQL is valid
p1_ir_op(28 downto 26)/="010" and -- COP2 is valid
p1_ir_op(28 downto 26)/="101")) or -- BNEL is valid
p1_ir_op="100010" or -- LWL
p1_ir_op="100110" or -- LWR
p1_ir_op="101010" or -- SWL
p1_ir_op="101110" or -- SWR
p1_ir_op="100111" or
p1_ir_op="101100" or
p1_ir_op="101101" or
-- decode instructions in the 'special2' opcode group
(p1_ir_op="011100" and
(p1_ir_fn="000000" or -- MADD
p1_ir_fn="000001")) or -- MADDU
-- decode instructions in the 'special' opcode group
(p1_ir_op="000000" and
(p1_ir_fn(5 downto 4)="11" or
p1_ir_fn="000001" or
p1_ir_fn="000101" or
p1_ir_fn="001010" or
p1_ir_fn="001011" or
p1_ir_fn="001110" or
p1_ir_fn(5 downto 2)="0101" or
p1_ir_fn(5 downto 2)="0111" or
p1_ir_fn(5 downto 2)="1011")) or
-- decode instructions in the 'regimm' opcode group
(p1_ir_op="000001" and
(p1_ir_reg(20 downto 16)/="00000" and -- BLTZ is valid
p1_ir_reg(20 downto 16)/="00001" and -- BGEZ is valid
p1_ir_reg(20 downto 16)/="10000" and -- BLTZAL is valid
p1_ir_reg(20 downto 16)/="10001")) -- BGEZAL is valid
else '0';
p1_cp_unavailable <= '1' when
(p1_set_cp='1' and (p1_set_cp0='0' and p1_set_cp2='0')) or -- mtc1/3
(p1_get_cp='1' and (p1_get_cp0='0' and p1_get_cp2='0')) or -- mfc1/3
-- FIXME @hack1: ERET in user mode does not trigger trap
((p1_get_cp0='1' or p1_set_cp0='1' or
p1_rfe='1' or -- p1_eret='1' or
p1_get_cp2='1' or p1_set_cp2='1')
and cp0_miso.kernel='0') -- COP0 user mode
-- FIXME CP1/3 logic missing
else '0';
--##############################################################################
-- HW interrupt interface.
-- Register incoming IRQ lines.
interrupt_registers:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
p0_irq_reg <= (others => '0');
else
-- Load p1_hw_irq in lockstep with the IR register, as if the IRQ
-- was part of the opcode.
-- FIXME use the "irq delay" signal?
if stall_pipeline='0' then
if irq_masked/="00000" and p0_irq_reg ="00000" then
p1_hw_irq <= '1';
else
p1_hw_irq <= '0';
end if;
end if;
-- Register interrupt lines every cycle.
p0_irq_reg <= irq_masked;
end if;
end if;
end process interrupt_registers;
-- FIXME this should be done after registering!
with cp0_miso.global_irq_enable select irq_masked <=
IRQ_I and cp0_miso.hw_irq_enable_mask when '1',
(others => '0') when others;
--##############################################################################
-- Pipeline registers & pipeline control logic
-- Stage 1 pipeline register. Involved in ALU control.
pipeline_stage1_register:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
p1_rbank_rs_hazard <= '0';
p1_rbank_rt_hazard <= '0';
elsif stall_pipeline='0' then
p1_rbank_rs_hazard <= p0_rbank_rs_hazard;
p1_rbank_rt_hazard <= p0_rbank_rt_hazard;
end if;
end if;
end process pipeline_stage1_register;
pipeline_stage1_register2:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
p2_muldiv_started <= '0';
else
p2_muldiv_started <= p1_muldiv_running;
end if;
end if;
end process pipeline_stage1_register2;
-- Stage 2 pipeline register. Split in two for convenience.
-- This register deals with two kinds of stalls:
-- * When the pipeline stalls because of a load interlock, this register is
-- allowed to update so that the load operation can complete while the rest of
-- the pipeline is frozen.
-- * When the stall is caused by any other reason, this register freezes with
-- the rest of the machine.
-- Part of stage 2 register that controls load operation
pipeline_stage2_register_load_control:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
-- Clear load control, effectively preventing a load, at RESET_I or if
-- the previous instruction raised an exception.
if RESET_I='1' or p2_exception='1' then
p2_do_load <= '0';
p2_ld_upper_hword <= '0';
p2_ld_upper_byte <= '0';
p2_ld_unsigned <= '0';
p2_load_target <= "00000";
else
-- The P2 registers controlling load writeback are updated...
-- ...if the pipeline is not stalled (@note1)...
if stall_pipeline='0' or
-- or if it is stalled due to a load interlock (@note2).
(stall_pipeline='1' and load_interlock='1') then
-- These signals control the input LOAD mux.
p2_load_target <= p1_rd_num;
p2_ld_upper_hword <= p1_ld_upper_hword;
p2_ld_upper_byte <= p1_ld_upper_byte;
p2_ld_unsigned <= p1_ld_unsigned;
-- p2_do_load gates the reg bank WE and needs extra logic:
-- Disable reg bank writeback if pipeline is stalled; this
-- prevents duplicate writes in case the stall is a mem_wait.
if pipeline_stalled='0' then
p2_do_load <= p1_do_load;
else
p2_do_load <= '0';
end if;
end if;
end if;
end if;
end process pipeline_stage2_register_load_control;
-- P2 register that controls the data input mux.
-- Note this FF is never stalled: all we do here is record whether input data
-- is to be taken straight from the bus of from the input register. The latter
-- will only happen if there was any stall at the moment the data bus had the
-- valid data and it has to be registered.
pipeline_stage2_register_load_pending:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
p2_load_pending <= '0';
elsif (p1_do_load='1') and pipeline_stalled='0' then
p2_load_pending <= '1';
elsif p2_load_pending='1' and DATA_MISO_I.mwait='0' then
p2_load_pending <= '0';
end if;
end if;
end process pipeline_stage2_register_load_pending;
-- All the rest of the stage 2 registers
pipeline_stage2_register_others:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
p2_exception <= '0';
-- Load signals from previous stage only if there is no pipeline stall
-- unless the stall is caused by interlock (@note1).
elsif (stall_pipeline='0' or load_interlock='1') then
p2_rd_addr <= p1_data_addr(1 downto 0);
-- Prevent execution of exception victims and ERETs.
-- FIXME rename p2_exception
p2_exception <= p1_exception or p1_eret;
elsif p1_exception='1' then
p2_exception <= '1';
end if;
end if;
end process pipeline_stage2_register_others;
--------------------------------------------------------------------------------
-- Pipeline control logic (stall control)
-- These are the 4 conditions upon which the pipeline is stalled.
stall_pipeline <=
mem_wait or
load_interlock or
p1_muldiv_stall or
COP2_MISO_I.stall;
-- Either of the two buses will stall the pipeline when waited.
mem_wait <= DATA_MISO_I.mwait or CODE_MISO_I.mwait;
-- FIXME load interlock should happen only if the instruction following
-- the load actually uses the load target register. Something like this:
-- (p1_do_load='1' and (p1_rd_num=p0_rs_num or p1_rd_num=p0_rt_num))
load_interlock <= '1' when
p1_do_load='1' and -- this is a load instruction
pipeline_stalled='0' -- not already stalled (i.e. assert for 1 cycle)
else '0';
-- We need to have a registered version of these
pipeline_stall_registers:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
stalled_interlock <= '0';
stalled_memwait <= '0';
stalled_muldiv <= '0';
else
stalled_memwait <= mem_wait;
stalled_muldiv <= p1_muldiv_stall;
stalled_interlock <= load_interlock;
end if;
end if;
end process pipeline_stall_registers;
pipeline_stalled <= stalled_interlock or stalled_memwait or stalled_muldiv;
--##############################################################################
-- Data memory interface
--------------------------------------------------------------------------------
-- Memory addressing adder (data address generation)
p1_data_offset(31 downto 16) <= (others => p1_data_imm(15));
p1_data_offset(15 downto 0) <= p1_data_imm(15 downto 0);
p1_data_addr <= p1_rs + p1_data_offset;
--------------------------------------------------------------------------------
-- Write enable vector
-- DATA_MOSI_O.wr_be is a function of the write size and alignment
-- size = {00=1,01=2,11=4}; we 3 is MSB, 0 is LSB; big endian => 00 is msb
p1_we_control <= (mem_wait) & (p1_do_store) &
p1_store_size & p1_data_addr(1 downto 0);
-- FIXME: make sure this bug is gone, it should be.
-- Bug: For two SW instructions in a row, the 2nd one will be stalled and lost:
-- the write will never be executed by the cache.
-- Fixed by stalling immediately after asserting DATA_MOSI_O.wr_be.
-- FIXME the above fix has been tested but is still under trial (provisional)
with p1_we_control select DATA_MOSI_O.wr_be <=
"1000" when "010000", -- SB %0
"0100" when "010001", -- SB %1
"0010" when "010010", -- SB %2
"0001" when "010011", -- SB %3
"1100" when "010100", -- SH %0
"0011" when "010110", -- SH %2
"1111" when "011100", -- SW %4
"0000" when others; -- all other combinations are spurious so don't write
-- Data to be stored always comes straight from the reg bank, but it needs to
-- be shifted so that the LSB is aligned to the write address:
p1_sw_data(7 downto 0) <= p1_rt(7 downto 0);
with p1_we_control select p1_sw_data(15 downto 8) <=
p1_rt( 7 downto 0) when "010010", -- SB %2
p1_rt(15 downto 8) when others;
with p1_we_control select p1_sw_data(23 downto 16) <=
p1_rt( 7 downto 0) when "010001", -- SB %1
p1_rt( 7 downto 0) when "010100", -- SH %0
p1_rt(23 downto 16) when others;
with p1_we_control select p1_sw_data(31 downto 24) <=
p1_rt( 7 downto 0) when "010000", -- SB %0
p1_rt(15 downto 8) when "010100", -- SH %0
p1_rt(31 downto 24) when others;
DATA_MOSI_O.wr_data <= p1_sw_data;
--##############################################################################
-- COP0 block.
cp0_mosi.index <= p1_c0_rs_num;
cp0_mosi.we <= p1_set_cp0;
cp0_mosi.data <= p1_rt;
cp0_mosi.pipeline_stalled <= pipeline_stalled;
cp0_mosi.exception <= p1_exception;
cp0_mosi.hw_irq <= p1_hw_irq;
cp0_mosi.hw_irq_reg <= p0_irq_reg;
cp0_mosi.rfe <= p1_rfe;
cp0_mosi.eret <= p1_eret;
cp0_mosi.unknown_opcode <= p1_unknown_opcode;
cp0_mosi.missing_cop <= p1_cp_unavailable;
cp0_mosi.syscall <= not p1_ir_fn(0);
cp0_mosi.stall <= stall_pipeline;
cop0 : entity work.ION_COP0
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
CPU_I => cp0_mosi,
CPU_O => cp0_miso
);
--##############################################################################
-- COP2 interface.
COP2_MOSI_O.reg_rd_en <= p1_get_cp2;
COP2_MOSI_O.reg_wr_en <= p1_set_cp2;
COP2_MOSI_O.data <= p1_rt;
COP2_MOSI_O.reg_rd.index <= CODE_MISO_I.rd_data(20 downto 16) when CODE_MISO_I.rd_data(31 downto 26)="111010" else CODE_MISO_I.rd_data(15 downto 11);
COP2_MOSI_O.reg_rd.sel <= CODE_MISO_I.rd_data(2 downto 0);
COP2_MOSI_O.reg_rd.control <= CODE_MISO_I.rd_data(22);
COP2_MOSI_O.reg_wr.index <= p1_ir_reg(15 downto 11);
COP2_MOSI_O.reg_wr.sel <= p1_ir_reg(2 downto 0);
COP2_MOSI_O.reg_wr.control <= p1_ir_fmt(22);
COP2_MOSI_O.cofun25_en <= '0';
COP2_MOSI_O.cofun16_en <= '0';
COP2_MOSI_O.cofun <= (others => '0');
COP2_MOSI_O.stall <= stall_pipeline;
end architecture rtl;
--------------------------------------------------------------------------------
-- Implementation notes
--------------------------------------------------------------------------------
-- @note1 :
-- This is the meaning of these two signals:
-- pipeline_stalled & stalled_interlock =>
-- "00" => normal state
-- "01" => normal state (makes for easier decoding)
-- "10" => all stages of pipeline stalled, including rbank
-- "11" => all stages of pipeline stalled, except reg bank write port
--
-- Just to clarify, 'stage X stalled' here means that the registers named
-- pX_* don't load.
--
-- The register bank WE is enabled when the pipeline is not stalled and when
-- it is stalled because of a load interlock; so that in case of interlock the
-- load operation can complete while the rest of the pipeline is frozen.
--
-- @note2:
-- All instructions that follow a load instruction are stalled for one cycle.
-- Otherwise the regbank write from the load and post-load instructions would
-- clash. See {[2], sec. ?} for a full explanation.
--
-- @note3:
-- CP0 instructions (mtc0, mfc0 and rfe) are only partially decoded.
-- This is possible because no other VALID MIPS* opcode shares the decoded
-- part; that is, we're not going to misdecode a MIPS32 opcode, but we MIGHT
-- mistake a bad opcode for a COP0; we'll live with that for the time being.
--
-- @note4:
-- The pipeline may be stalled for one of 5 reasons including code bus waits
-- AND data bus waits; we need the code word to be valid when actually fetched,
-- and that means it needs to be valid from the deassertion of code_miso.mwait
-- to the edge after code_mosi.addr changes. See {[2], sec. ?}.
--
--------------------------------------------------------------------------------
| lgpl-3.0 | 09a5265ad6acb91d98907c75a752b693 | 0.559781 | 3.294222 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_IN4_DEC8b10b.vhd | 1 | 8,221 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
use work.centralRouter_package.all;
--! 8b10b decoder for EPROC_IN4 module
entity EPROC_IN4_DEC8b10b is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (3 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
busyOut : out std_logic
);
end EPROC_IN4_DEC8b10b;
architecture Behavioral of EPROC_IN4_DEC8b10b is
----------------------------------
----------------------------------
component KcharTest is
port (
clk : in std_logic;
encoded10in : in std_logic_vector (9 downto 0);
KcharCode : out std_logic_vector (1 downto 0)
);
end component KcharTest;
----------------------------------
----------------------------------
signal EDATAbitstreamSREG : std_logic_vector (23 downto 0) := (others=>'0'); -- 24 bit (4 x 5 = 20, plus 4 more)
signal word10bx2_align_array, word10bx2_align_array_r : word10b_2array_4array_type;
signal word10b_array, word10b_array_s : word10b_2array_type;
signal isk_array : isk_2array_type;
signal comma_valid_bits_or, word10bx2_align_rdy_r,
word10b_array_rdy, word10b_array_rdy_s : std_logic;
signal align_select : std_logic_vector (1 downto 0) := (others=>'0');
signal comma_valid_bits : std_logic_vector (3 downto 0);
signal alignment_sreg : std_logic_vector (4 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- 24 bit input shift register
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
EDATAbitstreamSREG <= (others => '0');
elsif bitCLK'event and bitCLK = '1' then
EDATAbitstreamSREG <= edataIN & EDATAbitstreamSREG(23 downto 4);
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock0
-- input shift register mapping into 10 bit registers
-------------------------------------------------------------------------------------------
input_map: for I in 0 to 3 generate -- 2 10bit-words per alignment, 4 possible alignments
--word10bx2_align_array(I)(0) <= EDATAbitstreamSREG((I+9) downto (I+0)); -- 1st 10 bit word, alligned to bit I
--word10bx2_align_array(I)(1) <= EDATAbitstreamSREG((I+19) downto (I+10)); -- 2nd 10 bit word, alligned to bit I
word10bx2_align_array(I)(0) <= EDATAbitstreamSREG(I+0)&EDATAbitstreamSREG(I+1)&EDATAbitstreamSREG(I+2)&EDATAbitstreamSREG(I+3)&EDATAbitstreamSREG(I+4)&
EDATAbitstreamSREG(I+5)&EDATAbitstreamSREG(I+6)&EDATAbitstreamSREG(I+7)&EDATAbitstreamSREG(I+8)&EDATAbitstreamSREG(I+9); -- 1st 10 bit word, alligned to bit I
word10bx2_align_array(I)(1) <= EDATAbitstreamSREG(I+10)&EDATAbitstreamSREG(I+11)&EDATAbitstreamSREG(I+12)&EDATAbitstreamSREG(I+13)&EDATAbitstreamSREG(I+14)&
EDATAbitstreamSREG(I+15)&EDATAbitstreamSREG(I+16)&EDATAbitstreamSREG(I+17)&EDATAbitstreamSREG(I+18)&EDATAbitstreamSREG(I+19); -- 2nd 10 bit word, alligned to bit I
end generate input_map;
--
-------------------------------------------------------------------------------------------
--clock0
-- K28.5 comma test
-------------------------------------------------------------------------------------------
comma_test: for I in 0 to 3 generate -- 2 10bit-words per alignment, comma is valid if two first words have comma
comma_valid_bits(I) <= '1' when ((word10bx2_align_array(I)(0) = COMMAp or word10bx2_align_array(I)(0) = COMMAn) and
(word10bx2_align_array(I)(1) = COMMAp or word10bx2_align_array(I)(1) = COMMAn)) else '0';
end generate comma_test;
--
comma_valid_bits_or <= comma_valid_bits(3) or comma_valid_bits(2) or comma_valid_bits(1) or comma_valid_bits(0);
--
-------------------------------------------------------------------------------------------
--clock1
-- alignment selector state
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
alignment_sreg <= "00000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
alignment_sreg <= "10000";
else
alignment_sreg <= alignment_sreg(0) & alignment_sreg(4 downto 1);
end if;
end if;
end process;
--
input_reg1: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10bx2_align_array_r <= word10bx2_align_array;
end if;
end process;
--
word10bx2_align_rdy_r <= alignment_sreg(4);
--
process(bitCLK, rst)
begin
if rst = '1' then
align_select <= "00";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
align_select(0) <= (not comma_valid_bits(0)) and (
comma_valid_bits(1) or ( (not comma_valid_bits(1)) and (not comma_valid_bits(2)) and (
comma_valid_bits(3)
)));
align_select(1) <= (not comma_valid_bits(0)) and (not comma_valid_bits(1)) and
(comma_valid_bits(2) or comma_valid_bits(3));
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock2
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg2: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_rdy <= word10bx2_align_rdy_r;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case (align_select) is
when "00" => -- bit0 word got comma => align to bit0
word10b_array <= word10bx2_align_array_r(0);
when "01" => -- bit1 word got comma => align to bit1
word10b_array <= word10bx2_align_array_r(1);
when "10" => -- bit2 word got comma => align to bit2
word10b_array <= word10bx2_align_array_r(2);
when "11" => -- bit3 word got comma => align to bit3
word10b_array <= word10bx2_align_array_r(3);
when others =>
end case;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b K-characters codes: COMMA/SOC/EOC/DATA
-------------------------------------------------------------------------------------------
KcharTests: for I in 0 to 1 generate
KcharTestn: KcharTest
port map(
clk => bitCLK,
encoded10in => word10b_array(I),
KcharCode => isk_array(I)
);
end generate KcharTests;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_s <= word10b_array;
word10b_array_rdy_s <= word10b_array_rdy;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 2 words get aligned and ready as 10 bit word (data 8 bit and data code 2 bit)
-------------------------------------------------------------------------------------------
EPROC_IN4_ALIGN_BLOCK_inst: entity work.EPROC_IN4_ALIGN_BLOCK
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst,
bytes => word10b_array_s,
bytes_rdy => word10b_array_rdy_s,
dataOUT => dataOUT,
dataOUTrdy => dataOUTrdy,
busyOut => busyOut
);
end Behavioral;
| gpl-3.0 | 48a872c7d854281c348e7583da009299 | 0.491911 | 3.841589 | false | false | false | false |
HackLinux/ION | src/application/ion_application.vhdl | 1 | 9,812 | --------------------------------------------------------------------------------
-- ion_application.vhdl -- Sample application for ION core.
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- IMPORTANT:
-- You need to supply your own 3-state bidirectionsl interface at the
-- top level entity. See the DE-1 demo for an example of this.
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
use work.OBJ_CODE_PKG.all;
entity ion_application is
generic(
-- Size of code TCM block in bytes.
-- Set to a power of 2 or to zero to disable code TCM.
TCM_CODE_SIZE : integer := 2048;
-- Contents of code TCM.
--TCM_CODE_INIT : t_obj_code := zero_objcode(2048);
TCM_CODE_INIT : t_obj_code := OBJ_CODE;
-- Size of data TCM block in bytes.
-- Set to a power of 2 or to zero to disable data TCM.
TCM_DATA_SIZE : integer := 2048;
-- Contents of data TCM.
TCM_DATA_INIT : t_obj_code := zero_objcode(2048);
-- Size of external SRAM in 16-bit words.
SRAM_SIZE : integer := 256*1024;
-- Number of wait states to be used for SRAM.
SRAM_WAIT_CYCLES : integer := 3;
-- Size of data cache in lines.
-- Set to a power of 2 or 0 to disable the data cache.
DATA_CACHE_LINES : integer := 128;
-- Size of code cache in lines.
-- Set to a power of 2 or 0 to disable the code cache.
CODE_CACHE_LINES : integer := 128;
-- Type of memory to be used for register bank in xilinx HW
XILINX_REGBANK : string := "distributed" -- {distributed|block}
);
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
-- External SRAM interface.
SRAM_ADDR_O : out std_logic_vector(log2(SRAM_SIZE) downto 1);
SRAM_DATA_I : in std_logic_vector(15 downto 0);
SRAM_DATA_O : out std_logic_vector(15 downto 0);
SRAM_WEn_O : out std_logic;
SRAM_OEn_O : out std_logic;
SRAM_UBn_O : out std_logic;
SRAM_LBn_O : out std_logic;
SRAM_CEn_O : out std_logic;
SRAM_DRIVE_EN_O : out std_logic;
IRQ_I : in std_logic_vector(5 downto 0);
GPIO_0_OUT_O : out std_logic_vector(15 downto 0);
GPIO_0_INP_I : in std_logic_vector(15 downto 0)
);
end; --entity ion_application
architecture rtl of ion_application is
signal code_wb_mosi : t_wishbone_mosi;
signal code_wb_miso : t_wishbone_miso;
signal data_wb_mosi : t_wishbone_mosi;
signal data_wb_miso : t_wishbone_miso;
signal sram_wb_mosi : t_wishbone_mosi;
signal sram_wb_miso : t_wishbone_miso;
signal data_uc_wb_mosi : t_wishbone_mosi;
signal data_uc_wb_miso : t_wishbone_miso;
signal cop2_mosi : t_cop2_mosi;
signal cop2_miso : t_cop2_miso;
signal gpio_miso : t_wishbone_miso;
signal void_miso : t_wishbone_miso;
signal io_mux_ctrl : std_logic_vector(1 downto 0);
signal io_mux_ctrl_reg : std_logic_vector(1 downto 0);
signal io_ce : std_logic_vector(1 downto 0);
---- Address map constants & functions -----------------------------------------
-- GPIO block -- reserve 16 words.
constant GPIO_BASE : t_word := X"ffff0020";
constant GPIO_ASIZE : integer := 26;
-- NOTE: all the functions defined in this entity are "constant functions" that
-- can be used in synthesizable rtl as long as their parameters are constants.
-- Return '1' if high 's' of address 'a' match those of address 'b'.
function adecode(a : t_word; b : t_word; s : integer) return std_logic is
begin
if a(31 downto s+1) = b(31 downto s+1) then
return '1';
else
return '0';
end if;
end function adecode;
begin
-- Core instance -----------------------------------------------------------
core: entity work.ION_CORE
generic map (
TCM_CODE_SIZE => TCM_CODE_SIZE,
TCM_CODE_INIT => TCM_CODE_INIT,
TCM_DATA_SIZE => TCM_DATA_SIZE,
DATA_CACHE_LINES => DATA_CACHE_LINES,
CODE_CACHE_LINES => CODE_CACHE_LINES,
XILINX_REGBANK => XILINX_REGBANK
)
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
CODE_WB_MOSI_O => code_wb_mosi,
CODE_WB_MISO_I => code_wb_miso,
DATA_WB_MOSI_O => data_wb_mosi,
DATA_WB_MISO_I => data_wb_miso,
DATA_UC_WB_MOSI_O => data_uc_wb_mosi,
DATA_UC_WB_MISO_I => data_uc_wb_miso,
COP2_MOSI_O => cop2_mosi,
COP2_MISO_I => cop2_miso,
IRQ_I => IRQ_I
);
-- SRAM refill memory interface --------------------------------------------
--
sram_arbiter: entity work.ION_WISHBONE_ARBITER
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
CODE_MOSI_I => code_wb_mosi,
CODE_MISO_O => code_wb_miso,
DATA_MOSI_I => data_wb_mosi,
DATA_MISO_O => data_wb_miso,
MEM_MOSI_0 => sram_wb_mosi,
MEM_MISO_I => sram_wb_miso
);
--
sram_port: entity work.ION_SRAM16_INTERFACE
generic map (
SRAM_SIZE => SRAM_SIZE,
WAIT_CYCLES => SRAM_WAIT_CYCLES
)
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
WB_MOSI_I => sram_wb_mosi,
WB_MISO_O => sram_wb_miso,
SRAM_ADDR_O => SRAM_ADDR_O,
SRAM_DATA_O => SRAM_DATA_O,
SRAM_DATA_I => SRAM_DATA_I,
SRAM_WEn_O => SRAM_WEn_O,
SRAM_OEn_O => SRAM_OEn_O,
SRAM_UBn_O => SRAM_UBn_O,
SRAM_LBn_O => SRAM_LBn_O,
SRAM_CEn_O => SRAM_CEn_O,
SRAM_DRIVE_EN_O => SRAM_DRIVE_EN_O
);
-- Dummy COP2 for interface testing ----------------------------------------
cop2: entity work.ION_COP2_STUB
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
CPU_MOSI_I => cop2_mosi,
CPU_MISO_O => cop2_miso
);
-- I/O devices -------------------------------------------------------------
-- Decode the index of the IO slave being addressed.
io_mux_ctrl <=
"01" when adecode(data_uc_wb_mosi.adr, GPIO_BASE, GPIO_ASIZE)='1' else
"00";
-- Convert slave index to one-hot enable signal vector.
with io_mux_ctrl select io_ce <=
"01" when "01",
"10" when "10",
"00" when others;
gpio_ports: entity work.ION_GPIO_INTERFACE
generic map (
PORT_WIDTH => 16
)
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
WB_MOSI_I => data_uc_wb_mosi,
WB_MISO_O => gpio_miso,
EN_I => io_ce(0),
GPIO_0_O => GPIO_0_OUT_O,
GPIO_0_I => GPIO_0_INP_I
);
-- IO MISO multiplexor ----
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
io_mux_ctrl_reg <= (others => '0');
elsif data_uc_wb_mosi.cyc='1' then
io_mux_ctrl_reg <= io_mux_ctrl;
end if;
end if;
end process;
with io_mux_ctrl_reg select data_uc_wb_miso <=
gpio_miso when "01",
void_miso when others;
-- MISO to be fed to the core by the UC_WB MISO multiplexor when
-- no valid area is addressed.
void_miso.stall <= '0';
void_miso.ack <= '1';
void_miso.dat <= (others => '0');
end architecture rtl;
| lgpl-3.0 | a0415381a5c5c2285acfb281ae75ea33 | 0.48247 | 3.962843 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Muxer/muxer.vhd | 1 | 3,482 | ----------------------------------------------------------------------------------------------------
-- muxer
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
----------------------------------------------------------------------------------------------------
-- PACKAGE
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
package muxer_pkg is
--muxer componenet declaration
component muxer is
generic( INIT_SEL : std_logic_vector(1 downto 0) := b"10");
port( clk : in std_logic;
clk_2x : in std_logic;
rst : in std_logic;
sig1 : in std_logic_vector;
sig2 : in std_logic_vector;
sigs : out std_logic_vector);
end component;
end package;
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--This entity takes 2 input signals and interlaces them into 1 output signal. During development
--it was determined that the clock inputs must be phase aligned for best results
entity muxer is
generic( INIT_SEL : std_logic_vector(1 downto 0) := b"10");
port( clk : in std_logic;
clk_2x : in std_logic;
rst : in std_logic;
sig1 : in std_logic_vector;
sig2 : in std_logic_vector;
sigs : out std_logic_vector);
end muxer;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture behave of muxer is
signal sig1_reg : std_logic_vector(sig1'range) := (others => '0');
signal sig2_reg : std_logic_vector(sig2'range) := (others => '0');
signal selector : std_logic_vector(1 downto 0) := INIT_SEL;
signal sigs_reg : std_logic_vector(sigs'range) := (others => '0');
begin
--Register the inputs
reg_in : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
sig1_reg <= (others => '0');
sig2_reg <= (others => '0');
else
sig1_reg <= sig1;
sig2_reg <= sig2;
end if;
end if;
end process;
--Selection
update_selection : process(clk_2x)
begin
if(rising_edge(clk_2x)) then
if(rst = '1') then
selector <= INIT_SEL;
else
selector <= std_logic_vector(rotate_left(unsigned(selector), 1));
end if;
end if;
end process;
--Register the output
reg_out : process(clk_2x)
begin
if(rising_edge(clk_2x)) then
if(rst = '1') then
sigs_reg <= (others => '0');
else
case selector is
when b"01" => sigs_reg <= sig1;
when b"10" => sigs_reg <= sig2;
when others => sigs_reg <= (others => '-');
end case;
end if;
end if;
end process;
sigs <= sigs_reg;
end behave;
| mit | 42cde7b0e7e58d96a42c5ebe17a7833e | 0.407237 | 4.533854 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_OUT4_ENC8b10b.vhd | 4 | 6,466 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_OUT4_ENC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! 8b10b encoder for EPROC_OUT4 module
entity EPROC_OUT4_ENC8b10b is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(3 downto 0) -- ready on every bitCLK
);
end EPROC_OUT4_ENC8b10b;
architecture Behavioral of EPROC_OUT4_ENC8b10b is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
component enc8b10_wrap
port (
clk : in std_logic;
rst : in std_logic;
dataCode : in std_logic_vector (1 downto 0); -- 00"data, 01"eop, 10"sop, 11"comma
dataIN : in std_logic_vector (7 downto 0);
dataINrdy : in std_logic;
encDataOut : out std_logic_vector (9 downto 0);
encDataOutrdy : out std_logic
);
end component enc8b10_wrap;
----------------------------------
----------------------------------
component MUX8_Nbit
generic (N : integer := 16);
Port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
data2 : in std_logic_vector((N-1) downto 0);
data3 : in std_logic_vector((N-1) downto 0);
data4 : in std_logic_vector((N-1) downto 0);
data5 : in std_logic_vector((N-1) downto 0);
data6 : in std_logic_vector((N-1) downto 0);
data7 : in std_logic_vector((N-1) downto 0);
sel : in std_logic_vector(2 downto 0);
data_out : out std_logic_vector((N-1) downto 0)
);
end component MUX8_Nbit;
----------------------------------
----------------------------------
constant zeros4bit : std_logic_vector (3 downto 0) := "0000";
signal enc10bit, enc10bit0, enc10bit1 : std_logic_vector (9 downto 0);
signal enc10bit_x2_r : std_logic_vector (19 downto 0) := (others=>'0');
signal request_cycle_cnt, send_count : std_logic_vector (2 downto 0) := (others=>'0');
signal send_out_trig, word_cnt : std_logic := '0';
signal inp_request_trig, inp_request_trig_out, enc10bitRdy : std_logic;
begin
-------------------------------------------------------------------------------------------
-- input handshaking, request cycle 5 CLKs, request is 2 clks wide, 2 bytes at a time
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
request_cycle_cnt <= (others=>'0');
else
if inp_request_trig = '1' then -- meaning request_cycle_cnt = "100"
request_cycle_cnt <= (others=>'0');
else
request_cycle_cnt <= request_cycle_cnt + 1;
end if;
end if;
end if;
end process;
--
inp_request_trig <= '1' when (request_cycle_cnt = "100") else '0';
--
inp_reques1clk: pulse_pdxx_pwxx generic map(pd=>0,pw=>2) port map(bitCLKx4, inp_request_trig, inp_request_trig_out);
getDataTrig <= inp_request_trig_out;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
send_out_trig <= inp_request_trig; -- slow clock output trigger
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b encoding
-------------------------------------------------------------------------------------------
enc8b10bx: enc8b10_wrap
port map (
clk => bitCLKx4,
rst => rst,
dataCode => edataIN(9 downto 8), -- 00"data, 01"eop, 10"sop, 11"comma
dataIN => edataIN(7 downto 0),
dataINrdy => edataINrdy, -- one? CLKx4 after inp_request_trig_out
encDataOut => enc10bit,
encDataOutrdy => enc10bitRdy
);
-------------------------------------------------------------------------------------------
-- sending out 4 bits @ bitCLK
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if enc10bitRdy = '1' then
word_cnt <= not word_cnt;
else
word_cnt <= '0';
end if;
end if;
end process;
--
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if enc10bitRdy = '1' then
if word_cnt = '0' then
enc10bit0 <= enc10bit;
else
enc10bit1 <= enc10bit;
end if;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- slow clock logic
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if send_out_trig = '1' then
send_count <= (others=>'0');
else
send_count <= send_count + 1;
end if;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
enc10bit_x2_r <= (others=>'0');
elsif send_out_trig = '1' then
enc10bit_x2_r <= enc10bit1 & enc10bit0;
end if;
end if;
end process;
--
outmux: MUX8_Nbit
generic map (N=>4)
port map (
data0 => enc10bit_x2_r(3 downto 0),
data1 => enc10bit_x2_r(7 downto 4),
data2 => enc10bit_x2_r(11 downto 8),
data3 => enc10bit_x2_r(15 downto 12),
data4 => enc10bit_x2_r(19 downto 16),
data5 => zeros4bit,
data6 => zeros4bit,
data7 => zeros4bit,
sel => send_count,
data_out => EdataOUT
);
--
end Behavioral;
| gpl-3.0 | 55eb14407727561865e0c43a7f8786ae | 0.476338 | 3.489477 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/configuration/fpga_config_router.vhd | 1 | 13,942 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 05.08.2017
-- Design Name: FPGA Configuration Router
-- Module Name: fpga_config_router - RTL
-- Project Name: MMFE8 - NTUA
-- Target Devices: Artix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2017.2
-- Description: Module that drives the register value bus shift register to the
-- appropriate FPGA register depending on the address.
-- Dependencies: MMFE8 NTUA Project
--
-- Changelog:
--
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity fpga_config_router is
port(
------------------------------------
------ General Interface -----------
clk_125 : in std_logic;
reg_addr : in std_logic_vector(7 downto 0);
reg_rst : in std_logic;
reg_value_bit : in std_logic;
sreg_ena : in std_logic;
------------------------------------
---------- XADC Interface ----------
vmm_id_xadc : out std_logic_vector(15 downto 0);
xadc_sample_size : out std_logic_vector(10 downto 0);
xadc_delay : out std_logic_vector(17 downto 0);
------------------------------------
---------- AXI4SPI Interface -------
myIP_set : out std_logic_vector(31 downto 0);
myMAC_set : out std_logic_vector(47 downto 0);
destIP_set : out std_logic_vector(31 downto 0);
------------------------------------
-------- CKTP/CKBC Interface -------
ckbc_freq : out std_logic_vector(7 downto 0);
cktk_max_num : out std_logic_vector(7 downto 0);
cktp_max_num : out std_logic_vector(15 downto 0);
cktp_skew : out std_logic_vector(7 downto 0);
cktp_period : out std_logic_vector(15 downto 0);
cktp_width : out std_logic_vector(7 downto 0);
------------------------------------
-------- FPGA Config Interface -----
latency : out std_logic_vector(15 downto 0);
tr_delay_limit : out std_logic_vector(15 downto 0);
ckbc_max_num : out std_logic_vector(7 downto 0);
daq_state : out std_logic_vector(7 downto 0);
trig_state : out std_logic_vector(7 downto 0);
ro_state : out std_logic_vector(7 downto 0);
fpga_rst_state : out std_logic_vector(7 downto 0)
);
end fpga_config_router;
architecture RTL of fpga_config_router is
---- shift register enable buses. unused, but added here for index reference
---- 0 (index)
--signal vmm_id_xadc_ena : std_logic := '0';
---- 1
--signal xadc_sample_size_ena : std_logic := '0';
---- 2
--signal xadc_delay_ena : std_logic := '0';
---- 3
--signal destIP_set_ena : std_logic := '0';
---- 4
--signal myIP_set_ena : std_logic := '0';
---- 5
--signal myMAC_set_ena(47 downto 32) : std_logic := '0';
---- 19
--signal myMAC_set_ena(31 downto 0) : std_logic := '0';
---- 6
--signal ckbc_freq_ena : std_logic := '0';
---- 7
--signal cktk_max_num_ena : std_logic := '0';
---- 8
--signal cktp_max_num_ena : std_logic := '0';
---- 9
--signal cktp_skew_ena : std_logic := '0';
---- 10
--signal cktp_period_ena : std_logic := '0';
---- 11
--signal cktp_width_ena : std_logic := '0';
---- 12
--signal latency_ena : std_logic := '0';
---- 13
--signal tr_delay_limit_ena : std_logic := '0';
---- 14
--signal ckbc_max_num_ena : std_logic := '0';
---- 15
--signal daq_state_ena : std_logic := '0';
---- 16
--signal trig_state_ena : std_logic := '0';
---- 17
--signal ro_state_ena : std_logic := '0';
---- 18
--signal fpga_rst_ena : std_logic := '0';
signal ena_bus : std_logic_vector(31 downto 0) := (others => '0');
-- internal registers
signal daq_state_reg : std_logic_vector(7 downto 0) := (others => '0');
signal trig_state_reg : std_logic_vector(7 downto 0) := (others => '0');
signal ro_state_reg : std_logic_vector(7 downto 0) := (others => '0');
signal fpga_rst_reg : std_logic_vector(7 downto 0) := (others => '0');
signal myMAC_0 : std_logic_vector(15 downto 0) := (others => '0');
signal myMAC_1 : std_logic_vector(31 downto 0) := (others => '0');
signal latency_i : std_logic_vector(15 downto 0) := (others => '0');
signal cktk_max_num_i : std_logic_vector(7 downto 0) := (others => '0');
signal ckbc_freq_i : std_logic_vector(7 downto 0) := (others => '0');
signal cktp_max_num_i : std_logic_vector(15 downto 0) := (others => '0');
signal cktp_skew_i : std_logic_vector(7 downto 0) := (others => '0');
signal cktp_period_i : std_logic_vector(15 downto 0) := (others => '0');
signal cktp_width_i : std_logic_vector(7 downto 0) := (others => '0');
signal ckbc_max_num_i : std_logic_vector(7 downto 0) := (others => '0');
signal tr_delay_limit_i : std_logic_vector(15 downto 0) := (others => '0');
signal vmm_id_xadc_i : std_logic_vector(15 downto 0) := (others => '0');
signal xadc_sample_size_i : std_logic_vector(10 downto 0) := (others => '0');
signal xadc_delay_i : std_logic_vector(17 downto 0) := (others => '0');
signal destIP_set_i : std_logic_vector(31 downto 0) := (others => '0');
signal myIP_set_i : std_logic_vector(31 downto 0) := (others => '0');
function bit_reverse(s1:std_logic_vector) return std_logic_vector is
variable rr : std_logic_vector(s1'high downto s1'low);
begin
for ii in s1'high downto s1'low loop
rr(ii) := s1(s1'high-ii);
end loop;
return rr;
end bit_reverse;
begin
router_demux: process(reg_addr, sreg_ena)
begin
case reg_addr is
----- fpga conf ------
when x"ab" => ena_bus(16) <= sreg_ena; ena_bus(15 downto 0) <= (others => '0'); ena_bus(31 downto 17) <= (others => '0'); -- trigger mode
when x"0f" => ena_bus(15) <= sreg_ena; ena_bus(14 downto 0) <= (others => '0'); ena_bus(31 downto 16) <= (others => '0'); -- DAQ state
when x"cd" => ena_bus(17) <= sreg_ena; ena_bus(16 downto 0) <= (others => '0'); ena_bus(31 downto 18) <= (others => '0'); -- readout state
when x"af" => ena_bus(18) <= sreg_ena; ena_bus(17 downto 0) <= (others => '0'); ena_bus(31 downto 19) <= (others => '0'); -- FPGA reset
when x"05" => ena_bus(12) <= sreg_ena; ena_bus(11 downto 0) <= (others => '0'); ena_bus(31 downto 13) <= (others => '0'); -- latency
when x"c1" => ena_bus(7) <= sreg_ena; ena_bus(6 downto 0) <= (others => '0'); ena_bus(31 downto 8) <= (others => '0'); -- CKTK max
when x"c2" => ena_bus(6) <= sreg_ena; ena_bus(5 downto 0) <= (others => '0'); ena_bus(31 downto 7) <= (others => '0'); -- CKBC freq
when x"c3" => ena_bus(8) <= sreg_ena; ena_bus(7 downto 0) <= (others => '0'); ena_bus(31 downto 9) <= (others => '0'); -- CKTP max
when x"c4" => ena_bus(9) <= sreg_ena; ena_bus(8 downto 0) <= (others => '0'); ena_bus(31 downto 10) <= (others => '0'); -- CKTP skew
when x"c5" => ena_bus(10) <= sreg_ena; ena_bus(9 downto 0) <= (others => '0'); ena_bus(31 downto 11) <= (others => '0'); -- CKTP period
when x"c6" => ena_bus(11) <= sreg_ena; ena_bus(10 downto 0) <= (others => '0'); ena_bus(31 downto 12) <= (others => '0'); -- CKTP width
when x"c7" => ena_bus(14) <= sreg_ena; ena_bus(13 downto 0) <= (others => '0'); ena_bus(31 downto 15) <= (others => '0'); -- CKBC max
when x"c8" => ena_bus(13) <= sreg_ena; ena_bus(12 downto 0) <= (others => '0'); ena_bus(31 downto 14) <= (others => '0'); -- trigger delay
----- xADC conf ------
when x"a1" => ena_bus(0) <= sreg_ena; ena_bus(31 downto 1) <= (others => '0'); ena_bus(31 downto 1) <= (others => '0'); -- VMM ID xADC
when x"a2" => ena_bus(1) <= sreg_ena; ena_bus(0 downto 0) <= (others => '0'); ena_bus(31 downto 2) <= (others => '0'); -- xADC sample size
when x"a3" => ena_bus(2) <= sreg_ena; ena_bus(1 downto 0) <= (others => '0'); ena_bus(31 downto 3) <= (others => '0'); -- xADC delay
----- flash IP conf --
when x"b1" => ena_bus(3) <= sreg_ena; ena_bus(2 downto 0) <= (others => '0'); ena_bus(31 downto 4) <= (others => '0'); -- destIP
when x"b2" => ena_bus(4) <= sreg_ena; ena_bus(3 downto 0) <= (others => '0'); ena_bus(31 downto 5) <= (others => '0'); -- myIP
when x"b3" => ena_bus(5) <= sreg_ena; ena_bus(4 downto 0) <= (others => '0'); ena_bus(31 downto 6) <= (others => '0'); -- myMAC(47 downto 32)
when x"b4" => ena_bus(19) <= sreg_ena; ena_bus(18 downto 0) <= (others => '0'); ena_bus(31 downto 20) <= (others => '0'); -- myMAC(31 downto 0)
when others => null;
end case;
end process;
-- drives the enable signal to the correct shift register
sreg_proc: process(clk_125)
begin
if(rising_edge(clk_125))then
if(reg_rst = '1')then
fpga_rst_reg <= (others => '0');
else
----- fpga conf ------
if(ena_bus(16) = '1')then trig_state_reg <= reg_value_bit & trig_state_reg(7 downto 1); else null; end if;
if(ena_bus(15) = '1')then daq_state_reg <= reg_value_bit & daq_state_reg(7 downto 1); else null; end if;
if(ena_bus(17) = '1')then ro_state_reg <= reg_value_bit & ro_state_reg(7 downto 1); else null; end if;
if(ena_bus(18) = '1')then fpga_rst_reg <= reg_value_bit & fpga_rst_reg(7 downto 1); else null; end if;
if(ena_bus(12) = '1')then latency_i <= reg_value_bit & latency_i(15 downto 1); else null; end if;
if(ena_bus(7) = '1')then cktk_max_num_i <= reg_value_bit & cktk_max_num_i(7 downto 1); else null; end if;
if(ena_bus(6) = '1')then ckbc_freq_i <= reg_value_bit & ckbc_freq_i(7 downto 1); else null; end if;
if(ena_bus(8) = '1')then cktp_max_num_i <= reg_value_bit & cktp_max_num_i(15 downto 1); else null; end if;
if(ena_bus(9) = '1')then cktp_skew_i <= reg_value_bit & cktp_skew_i(7 downto 1); else null; end if;
if(ena_bus(10) = '1')then cktp_period_i <= reg_value_bit & cktp_period_i(15 downto 1); else null; end if;
if(ena_bus(11) = '1')then cktp_width_i <= reg_value_bit & cktp_width_i(7 downto 1); else null; end if;
if(ena_bus(14) = '1')then ckbc_max_num_i <= reg_value_bit & ckbc_max_num_i(7 downto 1); else null; end if;
if(ena_bus(13) = '1')then tr_delay_limit_i <= reg_value_bit & tr_delay_limit_i(15 downto 1); else null; end if;
----- xADC conf ------
if(ena_bus(0) = '1')then vmm_id_xadc_i <= reg_value_bit & vmm_id_xadc_i(15 downto 1); else null; end if;
if(ena_bus(1) = '1')then xadc_sample_size_i <= reg_value_bit & xadc_sample_size_i(10 downto 1); else null; end if;
if(ena_bus(2) = '1')then xadc_delay_i <= reg_value_bit & xadc_delay_i(17 downto 1); else null; end if;
----- flash IP conf ----
if(ena_bus(3) = '1')then destIP_set_i <= reg_value_bit & destIP_set_i(31 downto 1); else null; end if;
if(ena_bus(4) = '1')then myIP_set_i <= reg_value_bit & myIP_set_i(31 downto 1); else null; end if;
if(ena_bus(5) = '1')then myMAC_0 <= reg_value_bit & myMAC_0(15 downto 1); else null; end if;
if(ena_bus(19) = '1')then myMAC_1 <= reg_value_bit & myMAC_1(31 downto 1); else null; end if;
end if;
end if;
end process;
latency <= bit_reverse(latency_i);
cktk_max_num <= bit_reverse(cktk_max_num_i);
ckbc_freq <= bit_reverse(ckbc_freq_i);
cktp_max_num <= bit_reverse(cktp_max_num_i);
cktp_skew <= bit_reverse(cktp_skew_i);
cktp_period <= bit_reverse(cktp_period_i);
cktp_width <= bit_reverse(cktp_width_i);
ckbc_max_num <= bit_reverse(ckbc_max_num_i);
tr_delay_limit <= bit_reverse(tr_delay_limit_i);
vmm_id_xadc <= bit_reverse(vmm_id_xadc_i);
xadc_sample_size<= bit_reverse(xadc_sample_size_i);
xadc_delay <= bit_reverse(xadc_delay_i);
destIP_set <= bit_reverse(destIP_set_i);
myIP_set <= bit_reverse(myIP_set_i);
myMAC_set <= bit_reverse(myMAC_0) & bit_reverse(myMAC_1);
daq_state <= bit_reverse(daq_state_reg);
trig_state <= bit_reverse(trig_state_reg);
ro_state <= bit_reverse(ro_state_reg);
fpga_rst_state <= bit_reverse(fpga_rst_reg);
end RTL; | gpl-3.0 | 5de81f835d2e60e8809f229fefacc407 | 0.535648 | 3.154299 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/StdRtlPkg.vhd | 1 | 66,128 | -------------------------------------------------------------------------------
-- Title : Standard RTL Package
-------------------------------------------------------------------------------
-- File : StdRtlPkg.vhd
-- Author : Benjamin Reese
-- Standard : VHDL'93/02, Math Packages
-------------------------------------------------------------------------------
-- Description: This package defines "sl" and "slv" shorthand subtypes for
-- std_logic and std_logic_vector receptively. It also defines
-- many handy utility functions. Nearly every .vhd file should
-- use this package.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
package StdRtlPkg is
-- Typing std_logic(_vector) is annoying
subtype sl is std_logic;
subtype slv is std_logic_vector;
-- Declare arrays of built in types
--type SlvArray is array (natural range <>) of slv; -- not supported in VCS yet (14APRIL2014 -- LLR)
type IntegerArray is array (natural range <>) of integer;
type NaturalArray is array (natural range <>) of natural;
type PositiveArray is array (natural range <>) of positive;
type RealArray is array (natural range <>) of real;
type TimeArray is array (natural range <>) of time;
type BooleanArray is array (natural range <>) of boolean;
-- Declare vector arrays of built in types
--type SlvVectorArray is array (natural range<>, natural range<>) of slv; -- not supported in VCS yet (14APRIL2014 -- LLR)
type IntegerVectorArray is array (natural range<>, natural range<>) of integer;
type NaturalVectorArray is array (natural range<>, natural range<>) of natural;
type PositiveVectorArray is array (natural range<>, natural range<>) of positive;
type RealVectorArray is array (natural range<>, natural range<>) of real;
type TimeVectorArray is array (natural range<>, natural range<>) of time;
type BooleanVectorArray is array (natural range<>, natural range<>) of boolean;
-- Create an arbitrary sized slv with all bits set high or low
function slvAll (size : positive; value : sl) return slv;
function slvZero (size : positive) return slv;
function slvOne (size : positive) return slv;
-- Very useful functions
function isPowerOf2 (number : natural) return boolean;
function isPowerOf2 (vector : slv) return boolean;
function log2 (constant number : positive) return natural;
function bitSize (constant number : natural) return positive;
function bitReverse (a : slv) return slv;
-- Similar to python's range() function
function list (constant start, size, step : integer) return IntegerArray;
-- Simple decoder and mux functions
function decode(v : slv) return slv;
function genmux(s, v : slv) return sl;
-- This should be unnecessary in VHDL 2008
function toBoolean (logic : sl) return boolean;
function toSl (bool : boolean) return sl;
function toString (bool : boolean) return string;
function toBoolean (str : string) return boolean;
-- Unary reduction operators, also unnecessary in VHDL 2008
function uOr (vec : slv) return sl;
function uAnd (vec : slv) return sl;
function uXor (vec : slv) return sl;
-- Test if all bits in a vector are set to a given logic value
function allBits (vec : slv; test : sl) return boolean;
function noBits (vec : slv; test : sl) return boolean;
-- These just use uXor to calculate parity
-- Output is parity bit value needed to achieve that parity given vec.
function evenParity (vec : slv) return sl;
function oddParity (vec : slv) return sl;
-- Functions for counting the number of '1' in a slv bus
function onesCount (vec : slv) return unsigned;
function onesCount (vec : slv) return slv;
-- Gray Code functions
function grayEncode (vec : unsigned) return unsigned;
function grayEncode (vec : slv) return slv;
function grayDecode (vec : unsigned) return unsigned;
function grayDecode (vec : slv) return slv;
-- Linear Feedback Shift Register function
function lfsrShift (lfsr : slv; constant taps : NaturalArray; input : sl := '0') return slv;
function maximum (left, right : integer) return integer;
function minimum (left, right : integer) return integer;
-- One line if-then-else functions. Useful for assigning constants based on generics.
function ite(i : boolean; t : boolean; e : boolean) return boolean;
function ite(i : boolean; t : sl; e : sl) return sl;
function ite(i : boolean; t : slv; e : slv) return slv;
function ite(i : boolean; t : bit_vector; e : bit_vector) return bit_vector;
function ite(i : boolean; t : character; e : character) return character;
function ite(i : boolean; t : string; e : string) return string;
function ite(i : boolean; t : integer; e : integer) return integer;
function ite(i : boolean; t : real; e : real) return real;
function ite(i : boolean; t : time; e : time) return time;
-- conv_std_logic_vector functions
function toSlv(ARG : integer; SIZE : integer) return slv;
-- gets real multiplication
function getRealMult (A, B : real) return real;
function getRealMult (A : integer; B : real) return real;
function getRealMult (A : real; B : integer) return real;
-- gets real division
function getRealDiv (A, B : real) return real;
function getRealDiv (A : integer; B : real) return real;
function getRealDiv (A : real; B : integer) return real;
function adcConversion (ain : real; low : real; high : real; bits : positive; twosComp : boolean) return slv;
--gets a time ratio
function getTimeRatio (T1, T2 : time) return natural; --not supported by Vivado
function getTimeRatio (T1, T2 : real) return natural;
procedure assignSlv (i : inout integer; vector : inout slv; value : in slv);
procedure assignSlv (i : inout integer; vector : inout slv; value : in sl);
procedure assignRecord (i : inout integer; vector : in slv; value : inout slv);
procedure assignRecord (i : inout integer; vector : in slv; value : inout sl);
-- Resize an SLV, either by trimming or padding upper bits
function resizeSlv ( vector : slv; newSize : integer) return slv;
-- Some synthesis tools wont accept unit types
-- pragma translate_off
type frequency is range 0 to 2147483647
units
Hz;
kHz = 1000 Hz;
MHz = 1000 kHz;
GHz = 1000 MHz;
end units;
function toTime(f : frequency) return time;
-- pragma translate_on
-- Add more slv array sizes here as they become needed
type Slv256Array is array (natural range <>) of slv(255 downto 0);
type Slv255Array is array (natural range <>) of slv(254 downto 0);
type Slv254Array is array (natural range <>) of slv(253 downto 0);
type Slv253Array is array (natural range <>) of slv(252 downto 0);
type Slv252Array is array (natural range <>) of slv(251 downto 0);
type Slv251Array is array (natural range <>) of slv(250 downto 0);
type Slv250Array is array (natural range <>) of slv(249 downto 0);
type Slv249Array is array (natural range <>) of slv(248 downto 0);
type Slv248Array is array (natural range <>) of slv(247 downto 0);
type Slv247Array is array (natural range <>) of slv(246 downto 0);
type Slv246Array is array (natural range <>) of slv(245 downto 0);
type Slv245Array is array (natural range <>) of slv(244 downto 0);
type Slv244Array is array (natural range <>) of slv(243 downto 0);
type Slv243Array is array (natural range <>) of slv(242 downto 0);
type Slv242Array is array (natural range <>) of slv(241 downto 0);
type Slv241Array is array (natural range <>) of slv(240 downto 0);
type Slv240Array is array (natural range <>) of slv(239 downto 0);
type Slv239Array is array (natural range <>) of slv(238 downto 0);
type Slv238Array is array (natural range <>) of slv(237 downto 0);
type Slv237Array is array (natural range <>) of slv(236 downto 0);
type Slv236Array is array (natural range <>) of slv(235 downto 0);
type Slv235Array is array (natural range <>) of slv(234 downto 0);
type Slv234Array is array (natural range <>) of slv(233 downto 0);
type Slv233Array is array (natural range <>) of slv(232 downto 0);
type Slv232Array is array (natural range <>) of slv(231 downto 0);
type Slv231Array is array (natural range <>) of slv(230 downto 0);
type Slv230Array is array (natural range <>) of slv(229 downto 0);
type Slv229Array is array (natural range <>) of slv(228 downto 0);
type Slv228Array is array (natural range <>) of slv(227 downto 0);
type Slv227Array is array (natural range <>) of slv(226 downto 0);
type Slv226Array is array (natural range <>) of slv(225 downto 0);
type Slv225Array is array (natural range <>) of slv(224 downto 0);
type Slv224Array is array (natural range <>) of slv(223 downto 0);
type Slv223Array is array (natural range <>) of slv(222 downto 0);
type Slv222Array is array (natural range <>) of slv(221 downto 0);
type Slv221Array is array (natural range <>) of slv(220 downto 0);
type Slv220Array is array (natural range <>) of slv(219 downto 0);
type Slv219Array is array (natural range <>) of slv(218 downto 0);
type Slv218Array is array (natural range <>) of slv(217 downto 0);
type Slv217Array is array (natural range <>) of slv(216 downto 0);
type Slv216Array is array (natural range <>) of slv(215 downto 0);
type Slv215Array is array (natural range <>) of slv(214 downto 0);
type Slv214Array is array (natural range <>) of slv(213 downto 0);
type Slv213Array is array (natural range <>) of slv(212 downto 0);
type Slv212Array is array (natural range <>) of slv(211 downto 0);
type Slv211Array is array (natural range <>) of slv(210 downto 0);
type Slv210Array is array (natural range <>) of slv(209 downto 0);
type Slv209Array is array (natural range <>) of slv(208 downto 0);
type Slv208Array is array (natural range <>) of slv(207 downto 0);
type Slv207Array is array (natural range <>) of slv(206 downto 0);
type Slv206Array is array (natural range <>) of slv(205 downto 0);
type Slv205Array is array (natural range <>) of slv(204 downto 0);
type Slv204Array is array (natural range <>) of slv(203 downto 0);
type Slv203Array is array (natural range <>) of slv(202 downto 0);
type Slv202Array is array (natural range <>) of slv(201 downto 0);
type Slv201Array is array (natural range <>) of slv(200 downto 0);
type Slv200Array is array (natural range <>) of slv(199 downto 0);
type Slv199Array is array (natural range <>) of slv(198 downto 0);
type Slv198Array is array (natural range <>) of slv(197 downto 0);
type Slv197Array is array (natural range <>) of slv(196 downto 0);
type Slv196Array is array (natural range <>) of slv(195 downto 0);
type Slv195Array is array (natural range <>) of slv(194 downto 0);
type Slv194Array is array (natural range <>) of slv(193 downto 0);
type Slv193Array is array (natural range <>) of slv(192 downto 0);
type Slv192Array is array (natural range <>) of slv(191 downto 0);
type Slv191Array is array (natural range <>) of slv(190 downto 0);
type Slv190Array is array (natural range <>) of slv(189 downto 0);
type Slv189Array is array (natural range <>) of slv(188 downto 0);
type Slv188Array is array (natural range <>) of slv(187 downto 0);
type Slv187Array is array (natural range <>) of slv(186 downto 0);
type Slv186Array is array (natural range <>) of slv(185 downto 0);
type Slv185Array is array (natural range <>) of slv(184 downto 0);
type Slv184Array is array (natural range <>) of slv(183 downto 0);
type Slv183Array is array (natural range <>) of slv(182 downto 0);
type Slv182Array is array (natural range <>) of slv(181 downto 0);
type Slv181Array is array (natural range <>) of slv(180 downto 0);
type Slv180Array is array (natural range <>) of slv(179 downto 0);
type Slv179Array is array (natural range <>) of slv(178 downto 0);
type Slv178Array is array (natural range <>) of slv(177 downto 0);
type Slv177Array is array (natural range <>) of slv(176 downto 0);
type Slv176Array is array (natural range <>) of slv(175 downto 0);
type Slv175Array is array (natural range <>) of slv(174 downto 0);
type Slv174Array is array (natural range <>) of slv(173 downto 0);
type Slv173Array is array (natural range <>) of slv(172 downto 0);
type Slv172Array is array (natural range <>) of slv(171 downto 0);
type Slv171Array is array (natural range <>) of slv(170 downto 0);
type Slv170Array is array (natural range <>) of slv(169 downto 0);
type Slv169Array is array (natural range <>) of slv(168 downto 0);
type Slv168Array is array (natural range <>) of slv(167 downto 0);
type Slv167Array is array (natural range <>) of slv(166 downto 0);
type Slv166Array is array (natural range <>) of slv(165 downto 0);
type Slv165Array is array (natural range <>) of slv(164 downto 0);
type Slv164Array is array (natural range <>) of slv(163 downto 0);
type Slv163Array is array (natural range <>) of slv(162 downto 0);
type Slv162Array is array (natural range <>) of slv(161 downto 0);
type Slv161Array is array (natural range <>) of slv(160 downto 0);
type Slv160Array is array (natural range <>) of slv(159 downto 0);
type Slv159Array is array (natural range <>) of slv(158 downto 0);
type Slv158Array is array (natural range <>) of slv(157 downto 0);
type Slv157Array is array (natural range <>) of slv(156 downto 0);
type Slv156Array is array (natural range <>) of slv(155 downto 0);
type Slv155Array is array (natural range <>) of slv(154 downto 0);
type Slv154Array is array (natural range <>) of slv(153 downto 0);
type Slv153Array is array (natural range <>) of slv(152 downto 0);
type Slv152Array is array (natural range <>) of slv(151 downto 0);
type Slv151Array is array (natural range <>) of slv(150 downto 0);
type Slv150Array is array (natural range <>) of slv(149 downto 0);
type Slv149Array is array (natural range <>) of slv(148 downto 0);
type Slv148Array is array (natural range <>) of slv(147 downto 0);
type Slv147Array is array (natural range <>) of slv(146 downto 0);
type Slv146Array is array (natural range <>) of slv(145 downto 0);
type Slv145Array is array (natural range <>) of slv(144 downto 0);
type Slv144Array is array (natural range <>) of slv(143 downto 0);
type Slv143Array is array (natural range <>) of slv(142 downto 0);
type Slv142Array is array (natural range <>) of slv(141 downto 0);
type Slv141Array is array (natural range <>) of slv(140 downto 0);
type Slv140Array is array (natural range <>) of slv(139 downto 0);
type Slv139Array is array (natural range <>) of slv(138 downto 0);
type Slv138Array is array (natural range <>) of slv(137 downto 0);
type Slv137Array is array (natural range <>) of slv(136 downto 0);
type Slv136Array is array (natural range <>) of slv(135 downto 0);
type Slv135Array is array (natural range <>) of slv(134 downto 0);
type Slv134Array is array (natural range <>) of slv(133 downto 0);
type Slv133Array is array (natural range <>) of slv(132 downto 0);
type Slv132Array is array (natural range <>) of slv(131 downto 0);
type Slv131Array is array (natural range <>) of slv(130 downto 0);
type Slv130Array is array (natural range <>) of slv(129 downto 0);
type Slv129Array is array (natural range <>) of slv(128 downto 0);
type Slv128Array is array (natural range <>) of slv(127 downto 0);
type Slv127Array is array (natural range <>) of slv(126 downto 0);
type Slv126Array is array (natural range <>) of slv(125 downto 0);
type Slv125Array is array (natural range <>) of slv(124 downto 0);
type Slv124Array is array (natural range <>) of slv(123 downto 0);
type Slv123Array is array (natural range <>) of slv(122 downto 0);
type Slv122Array is array (natural range <>) of slv(121 downto 0);
type Slv121Array is array (natural range <>) of slv(120 downto 0);
type Slv120Array is array (natural range <>) of slv(119 downto 0);
type Slv119Array is array (natural range <>) of slv(118 downto 0);
type Slv118Array is array (natural range <>) of slv(117 downto 0);
type Slv117Array is array (natural range <>) of slv(116 downto 0);
type Slv116Array is array (natural range <>) of slv(115 downto 0);
type Slv115Array is array (natural range <>) of slv(114 downto 0);
type Slv114Array is array (natural range <>) of slv(113 downto 0);
type Slv113Array is array (natural range <>) of slv(112 downto 0);
type Slv112Array is array (natural range <>) of slv(111 downto 0);
type Slv111Array is array (natural range <>) of slv(110 downto 0);
type Slv110Array is array (natural range <>) of slv(109 downto 0);
type Slv109Array is array (natural range <>) of slv(108 downto 0);
type Slv108Array is array (natural range <>) of slv(107 downto 0);
type Slv107Array is array (natural range <>) of slv(106 downto 0);
type Slv106Array is array (natural range <>) of slv(105 downto 0);
type Slv105Array is array (natural range <>) of slv(104 downto 0);
type Slv104Array is array (natural range <>) of slv(103 downto 0);
type Slv103Array is array (natural range <>) of slv(102 downto 0);
type Slv102Array is array (natural range <>) of slv(101 downto 0);
type Slv101Array is array (natural range <>) of slv(100 downto 0);
type Slv100Array is array (natural range <>) of slv(99 downto 0);
type Slv99Array is array (natural range <>) of slv(98 downto 0);
type Slv98Array is array (natural range <>) of slv(97 downto 0);
type Slv97Array is array (natural range <>) of slv(96 downto 0);
type Slv96Array is array (natural range <>) of slv(95 downto 0);
type Slv95Array is array (natural range <>) of slv(94 downto 0);
type Slv94Array is array (natural range <>) of slv(93 downto 0);
type Slv93Array is array (natural range <>) of slv(92 downto 0);
type Slv92Array is array (natural range <>) of slv(91 downto 0);
type Slv91Array is array (natural range <>) of slv(90 downto 0);
type Slv90Array is array (natural range <>) of slv(89 downto 0);
type Slv89Array is array (natural range <>) of slv(88 downto 0);
type Slv88Array is array (natural range <>) of slv(87 downto 0);
type Slv87Array is array (natural range <>) of slv(86 downto 0);
type Slv86Array is array (natural range <>) of slv(85 downto 0);
type Slv85Array is array (natural range <>) of slv(84 downto 0);
type Slv84Array is array (natural range <>) of slv(83 downto 0);
type Slv83Array is array (natural range <>) of slv(82 downto 0);
type Slv82Array is array (natural range <>) of slv(81 downto 0);
type Slv81Array is array (natural range <>) of slv(80 downto 0);
type Slv80Array is array (natural range <>) of slv(79 downto 0);
type Slv79Array is array (natural range <>) of slv(78 downto 0);
type Slv78Array is array (natural range <>) of slv(77 downto 0);
type Slv77Array is array (natural range <>) of slv(76 downto 0);
type Slv76Array is array (natural range <>) of slv(75 downto 0);
type Slv75Array is array (natural range <>) of slv(74 downto 0);
type Slv74Array is array (natural range <>) of slv(73 downto 0);
type Slv73Array is array (natural range <>) of slv(72 downto 0);
type Slv72Array is array (natural range <>) of slv(71 downto 0);
type Slv71Array is array (natural range <>) of slv(70 downto 0);
type Slv70Array is array (natural range <>) of slv(69 downto 0);
type Slv69Array is array (natural range <>) of slv(68 downto 0);
type Slv68Array is array (natural range <>) of slv(67 downto 0);
type Slv67Array is array (natural range <>) of slv(66 downto 0);
type Slv66Array is array (natural range <>) of slv(65 downto 0);
type Slv65Array is array (natural range <>) of slv(64 downto 0);
type Slv64Array is array (natural range <>) of slv(63 downto 0);
type Slv63Array is array (natural range <>) of slv(62 downto 0);
type Slv62Array is array (natural range <>) of slv(61 downto 0);
type Slv61Array is array (natural range <>) of slv(60 downto 0);
type Slv60Array is array (natural range <>) of slv(59 downto 0);
type Slv59Array is array (natural range <>) of slv(58 downto 0);
type Slv58Array is array (natural range <>) of slv(57 downto 0);
type Slv57Array is array (natural range <>) of slv(56 downto 0);
type Slv56Array is array (natural range <>) of slv(55 downto 0);
type Slv55Array is array (natural range <>) of slv(54 downto 0);
type Slv54Array is array (natural range <>) of slv(53 downto 0);
type Slv53Array is array (natural range <>) of slv(52 downto 0);
type Slv52Array is array (natural range <>) of slv(51 downto 0);
type Slv51Array is array (natural range <>) of slv(50 downto 0);
type Slv50Array is array (natural range <>) of slv(49 downto 0);
type Slv49Array is array (natural range <>) of slv(48 downto 0);
type Slv48Array is array (natural range <>) of slv(47 downto 0);
type Slv47Array is array (natural range <>) of slv(46 downto 0);
type Slv46Array is array (natural range <>) of slv(45 downto 0);
type Slv45Array is array (natural range <>) of slv(44 downto 0);
type Slv44Array is array (natural range <>) of slv(43 downto 0);
type Slv43Array is array (natural range <>) of slv(42 downto 0);
type Slv42Array is array (natural range <>) of slv(41 downto 0);
type Slv41Array is array (natural range <>) of slv(40 downto 0);
type Slv40Array is array (natural range <>) of slv(39 downto 0);
type Slv39Array is array (natural range <>) of slv(38 downto 0);
type Slv38Array is array (natural range <>) of slv(37 downto 0);
type Slv37Array is array (natural range <>) of slv(36 downto 0);
type Slv36Array is array (natural range <>) of slv(35 downto 0);
type Slv35Array is array (natural range <>) of slv(34 downto 0);
type Slv34Array is array (natural range <>) of slv(33 downto 0);
type Slv33Array is array (natural range <>) of slv(32 downto 0);
type Slv32Array is array (natural range <>) of slv(31 downto 0);
type Slv31Array is array (natural range <>) of slv(30 downto 0);
type Slv30Array is array (natural range <>) of slv(29 downto 0);
type Slv29Array is array (natural range <>) of slv(28 downto 0);
type Slv28Array is array (natural range <>) of slv(27 downto 0);
type Slv27Array is array (natural range <>) of slv(26 downto 0);
type Slv26Array is array (natural range <>) of slv(25 downto 0);
type Slv25Array is array (natural range <>) of slv(24 downto 0);
type Slv24Array is array (natural range <>) of slv(23 downto 0);
type Slv23Array is array (natural range <>) of slv(22 downto 0);
type Slv22Array is array (natural range <>) of slv(21 downto 0);
type Slv21Array is array (natural range <>) of slv(20 downto 0);
type Slv20Array is array (natural range <>) of slv(19 downto 0);
type Slv19Array is array (natural range <>) of slv(18 downto 0);
type Slv18Array is array (natural range <>) of slv(17 downto 0);
type Slv17Array is array (natural range <>) of slv(16 downto 0);
type Slv16Array is array (natural range <>) of slv(15 downto 0);
type Slv15Array is array (natural range <>) of slv(14 downto 0);
type Slv14Array is array (natural range <>) of slv(13 downto 0);
type Slv13Array is array (natural range <>) of slv(12 downto 0);
type Slv12Array is array (natural range <>) of slv(11 downto 0);
type Slv11Array is array (natural range <>) of slv(10 downto 0);
type Slv10Array is array (natural range <>) of slv(9 downto 0);
type Slv9Array is array (natural range <>) of slv(8 downto 0);
type Slv8Array is array (natural range <>) of slv(7 downto 0);
type Slv7Array is array (natural range <>) of slv(6 downto 0);
type Slv6Array is array (natural range <>) of slv(5 downto 0);
type Slv5Array is array (natural range <>) of slv(4 downto 0);
type Slv4Array is array (natural range <>) of slv(3 downto 0);
type Slv3Array is array (natural range <>) of slv(2 downto 0);
type Slv2Array is array (natural range <>) of slv(1 downto 0);
type Slv1Array is array (natural range <>) of slv(0 downto 0);
-- Add more slv vector array sizes here as they become needed
type Slv256VectorArray is array (natural range<>, natural range<>) of slv(255 downto 0);
type Slv255VectorArray is array (natural range<>, natural range<>) of slv(254 downto 0);
type Slv254VectorArray is array (natural range<>, natural range<>) of slv(253 downto 0);
type Slv253VectorArray is array (natural range<>, natural range<>) of slv(252 downto 0);
type Slv252VectorArray is array (natural range<>, natural range<>) of slv(251 downto 0);
type Slv251VectorArray is array (natural range<>, natural range<>) of slv(250 downto 0);
type Slv250VectorArray is array (natural range<>, natural range<>) of slv(249 downto 0);
type Slv249VectorArray is array (natural range<>, natural range<>) of slv(248 downto 0);
type Slv248VectorArray is array (natural range<>, natural range<>) of slv(247 downto 0);
type Slv247VectorArray is array (natural range<>, natural range<>) of slv(246 downto 0);
type Slv246VectorArray is array (natural range<>, natural range<>) of slv(245 downto 0);
type Slv245VectorArray is array (natural range<>, natural range<>) of slv(244 downto 0);
type Slv244VectorArray is array (natural range<>, natural range<>) of slv(243 downto 0);
type Slv243VectorArray is array (natural range<>, natural range<>) of slv(242 downto 0);
type Slv242VectorArray is array (natural range<>, natural range<>) of slv(241 downto 0);
type Slv241VectorArray is array (natural range<>, natural range<>) of slv(240 downto 0);
type Slv240VectorArray is array (natural range<>, natural range<>) of slv(239 downto 0);
type Slv239VectorArray is array (natural range<>, natural range<>) of slv(238 downto 0);
type Slv238VectorArray is array (natural range<>, natural range<>) of slv(237 downto 0);
type Slv237VectorArray is array (natural range<>, natural range<>) of slv(236 downto 0);
type Slv236VectorArray is array (natural range<>, natural range<>) of slv(235 downto 0);
type Slv235VectorArray is array (natural range<>, natural range<>) of slv(234 downto 0);
type Slv234VectorArray is array (natural range<>, natural range<>) of slv(233 downto 0);
type Slv233VectorArray is array (natural range<>, natural range<>) of slv(232 downto 0);
type Slv232VectorArray is array (natural range<>, natural range<>) of slv(231 downto 0);
type Slv231VectorArray is array (natural range<>, natural range<>) of slv(230 downto 0);
type Slv230VectorArray is array (natural range<>, natural range<>) of slv(229 downto 0);
type Slv229VectorArray is array (natural range<>, natural range<>) of slv(228 downto 0);
type Slv228VectorArray is array (natural range<>, natural range<>) of slv(227 downto 0);
type Slv227VectorArray is array (natural range<>, natural range<>) of slv(226 downto 0);
type Slv226VectorArray is array (natural range<>, natural range<>) of slv(225 downto 0);
type Slv225VectorArray is array (natural range<>, natural range<>) of slv(224 downto 0);
type Slv224VectorArray is array (natural range<>, natural range<>) of slv(223 downto 0);
type Slv223VectorArray is array (natural range<>, natural range<>) of slv(222 downto 0);
type Slv222VectorArray is array (natural range<>, natural range<>) of slv(221 downto 0);
type Slv221VectorArray is array (natural range<>, natural range<>) of slv(220 downto 0);
type Slv220VectorArray is array (natural range<>, natural range<>) of slv(219 downto 0);
type Slv219VectorArray is array (natural range<>, natural range<>) of slv(218 downto 0);
type Slv218VectorArray is array (natural range<>, natural range<>) of slv(217 downto 0);
type Slv217VectorArray is array (natural range<>, natural range<>) of slv(216 downto 0);
type Slv216VectorArray is array (natural range<>, natural range<>) of slv(215 downto 0);
type Slv215VectorArray is array (natural range<>, natural range<>) of slv(214 downto 0);
type Slv214VectorArray is array (natural range<>, natural range<>) of slv(213 downto 0);
type Slv213VectorArray is array (natural range<>, natural range<>) of slv(212 downto 0);
type Slv212VectorArray is array (natural range<>, natural range<>) of slv(211 downto 0);
type Slv211VectorArray is array (natural range<>, natural range<>) of slv(210 downto 0);
type Slv210VectorArray is array (natural range<>, natural range<>) of slv(209 downto 0);
type Slv209VectorArray is array (natural range<>, natural range<>) of slv(208 downto 0);
type Slv208VectorArray is array (natural range<>, natural range<>) of slv(207 downto 0);
type Slv207VectorArray is array (natural range<>, natural range<>) of slv(206 downto 0);
type Slv206VectorArray is array (natural range<>, natural range<>) of slv(205 downto 0);
type Slv205VectorArray is array (natural range<>, natural range<>) of slv(204 downto 0);
type Slv204VectorArray is array (natural range<>, natural range<>) of slv(203 downto 0);
type Slv203VectorArray is array (natural range<>, natural range<>) of slv(202 downto 0);
type Slv202VectorArray is array (natural range<>, natural range<>) of slv(201 downto 0);
type Slv201VectorArray is array (natural range<>, natural range<>) of slv(200 downto 0);
type Slv200VectorArray is array (natural range<>, natural range<>) of slv(199 downto 0);
type Slv199VectorArray is array (natural range<>, natural range<>) of slv(198 downto 0);
type Slv198VectorArray is array (natural range<>, natural range<>) of slv(197 downto 0);
type Slv197VectorArray is array (natural range<>, natural range<>) of slv(196 downto 0);
type Slv196VectorArray is array (natural range<>, natural range<>) of slv(195 downto 0);
type Slv195VectorArray is array (natural range<>, natural range<>) of slv(194 downto 0);
type Slv194VectorArray is array (natural range<>, natural range<>) of slv(193 downto 0);
type Slv193VectorArray is array (natural range<>, natural range<>) of slv(192 downto 0);
type Slv192VectorArray is array (natural range<>, natural range<>) of slv(191 downto 0);
type Slv191VectorArray is array (natural range<>, natural range<>) of slv(190 downto 0);
type Slv190VectorArray is array (natural range<>, natural range<>) of slv(189 downto 0);
type Slv189VectorArray is array (natural range<>, natural range<>) of slv(188 downto 0);
type Slv188VectorArray is array (natural range<>, natural range<>) of slv(187 downto 0);
type Slv187VectorArray is array (natural range<>, natural range<>) of slv(186 downto 0);
type Slv186VectorArray is array (natural range<>, natural range<>) of slv(185 downto 0);
type Slv185VectorArray is array (natural range<>, natural range<>) of slv(184 downto 0);
type Slv184VectorArray is array (natural range<>, natural range<>) of slv(183 downto 0);
type Slv183VectorArray is array (natural range<>, natural range<>) of slv(182 downto 0);
type Slv182VectorArray is array (natural range<>, natural range<>) of slv(181 downto 0);
type Slv181VectorArray is array (natural range<>, natural range<>) of slv(180 downto 0);
type Slv180VectorArray is array (natural range<>, natural range<>) of slv(179 downto 0);
type Slv179VectorArray is array (natural range<>, natural range<>) of slv(178 downto 0);
type Slv178VectorArray is array (natural range<>, natural range<>) of slv(177 downto 0);
type Slv177VectorArray is array (natural range<>, natural range<>) of slv(176 downto 0);
type Slv176VectorArray is array (natural range<>, natural range<>) of slv(175 downto 0);
type Slv175VectorArray is array (natural range<>, natural range<>) of slv(174 downto 0);
type Slv174VectorArray is array (natural range<>, natural range<>) of slv(173 downto 0);
type Slv173VectorArray is array (natural range<>, natural range<>) of slv(172 downto 0);
type Slv172VectorArray is array (natural range<>, natural range<>) of slv(171 downto 0);
type Slv171VectorArray is array (natural range<>, natural range<>) of slv(170 downto 0);
type Slv170VectorArray is array (natural range<>, natural range<>) of slv(169 downto 0);
type Slv169VectorArray is array (natural range<>, natural range<>) of slv(168 downto 0);
type Slv168VectorArray is array (natural range<>, natural range<>) of slv(167 downto 0);
type Slv167VectorArray is array (natural range<>, natural range<>) of slv(166 downto 0);
type Slv166VectorArray is array (natural range<>, natural range<>) of slv(165 downto 0);
type Slv165VectorArray is array (natural range<>, natural range<>) of slv(164 downto 0);
type Slv164VectorArray is array (natural range<>, natural range<>) of slv(163 downto 0);
type Slv163VectorArray is array (natural range<>, natural range<>) of slv(162 downto 0);
type Slv162VectorArray is array (natural range<>, natural range<>) of slv(161 downto 0);
type Slv161VectorArray is array (natural range<>, natural range<>) of slv(160 downto 0);
type Slv160VectorArray is array (natural range<>, natural range<>) of slv(159 downto 0);
type Slv159VectorArray is array (natural range<>, natural range<>) of slv(158 downto 0);
type Slv158VectorArray is array (natural range<>, natural range<>) of slv(157 downto 0);
type Slv157VectorArray is array (natural range<>, natural range<>) of slv(156 downto 0);
type Slv156VectorArray is array (natural range<>, natural range<>) of slv(155 downto 0);
type Slv155VectorArray is array (natural range<>, natural range<>) of slv(154 downto 0);
type Slv154VectorArray is array (natural range<>, natural range<>) of slv(153 downto 0);
type Slv153VectorArray is array (natural range<>, natural range<>) of slv(152 downto 0);
type Slv152VectorArray is array (natural range<>, natural range<>) of slv(151 downto 0);
type Slv151VectorArray is array (natural range<>, natural range<>) of slv(150 downto 0);
type Slv150VectorArray is array (natural range<>, natural range<>) of slv(149 downto 0);
type Slv149VectorArray is array (natural range<>, natural range<>) of slv(148 downto 0);
type Slv148VectorArray is array (natural range<>, natural range<>) of slv(147 downto 0);
type Slv147VectorArray is array (natural range<>, natural range<>) of slv(146 downto 0);
type Slv146VectorArray is array (natural range<>, natural range<>) of slv(145 downto 0);
type Slv145VectorArray is array (natural range<>, natural range<>) of slv(144 downto 0);
type Slv144VectorArray is array (natural range<>, natural range<>) of slv(143 downto 0);
type Slv143VectorArray is array (natural range<>, natural range<>) of slv(142 downto 0);
type Slv142VectorArray is array (natural range<>, natural range<>) of slv(141 downto 0);
type Slv141VectorArray is array (natural range<>, natural range<>) of slv(140 downto 0);
type Slv140VectorArray is array (natural range<>, natural range<>) of slv(139 downto 0);
type Slv139VectorArray is array (natural range<>, natural range<>) of slv(138 downto 0);
type Slv138VectorArray is array (natural range<>, natural range<>) of slv(137 downto 0);
type Slv137VectorArray is array (natural range<>, natural range<>) of slv(136 downto 0);
type Slv136VectorArray is array (natural range<>, natural range<>) of slv(135 downto 0);
type Slv135VectorArray is array (natural range<>, natural range<>) of slv(134 downto 0);
type Slv134VectorArray is array (natural range<>, natural range<>) of slv(133 downto 0);
type Slv133VectorArray is array (natural range<>, natural range<>) of slv(132 downto 0);
type Slv132VectorArray is array (natural range<>, natural range<>) of slv(131 downto 0);
type Slv131VectorArray is array (natural range<>, natural range<>) of slv(130 downto 0);
type Slv130VectorArray is array (natural range<>, natural range<>) of slv(129 downto 0);
type Slv129VectorArray is array (natural range<>, natural range<>) of slv(128 downto 0);
type Slv128VectorArray is array (natural range<>, natural range<>) of slv(127 downto 0);
type Slv127VectorArray is array (natural range<>, natural range<>) of slv(126 downto 0);
type Slv126VectorArray is array (natural range<>, natural range<>) of slv(125 downto 0);
type Slv125VectorArray is array (natural range<>, natural range<>) of slv(124 downto 0);
type Slv124VectorArray is array (natural range<>, natural range<>) of slv(123 downto 0);
type Slv123VectorArray is array (natural range<>, natural range<>) of slv(122 downto 0);
type Slv122VectorArray is array (natural range<>, natural range<>) of slv(121 downto 0);
type Slv121VectorArray is array (natural range<>, natural range<>) of slv(120 downto 0);
type Slv120VectorArray is array (natural range<>, natural range<>) of slv(119 downto 0);
type Slv119VectorArray is array (natural range<>, natural range<>) of slv(118 downto 0);
type Slv118VectorArray is array (natural range<>, natural range<>) of slv(117 downto 0);
type Slv117VectorArray is array (natural range<>, natural range<>) of slv(116 downto 0);
type Slv116VectorArray is array (natural range<>, natural range<>) of slv(115 downto 0);
type Slv115VectorArray is array (natural range<>, natural range<>) of slv(114 downto 0);
type Slv114VectorArray is array (natural range<>, natural range<>) of slv(113 downto 0);
type Slv113VectorArray is array (natural range<>, natural range<>) of slv(112 downto 0);
type Slv112VectorArray is array (natural range<>, natural range<>) of slv(111 downto 0);
type Slv111VectorArray is array (natural range<>, natural range<>) of slv(110 downto 0);
type Slv110VectorArray is array (natural range<>, natural range<>) of slv(109 downto 0);
type Slv109VectorArray is array (natural range<>, natural range<>) of slv(108 downto 0);
type Slv108VectorArray is array (natural range<>, natural range<>) of slv(107 downto 0);
type Slv107VectorArray is array (natural range<>, natural range<>) of slv(106 downto 0);
type Slv106VectorArray is array (natural range<>, natural range<>) of slv(105 downto 0);
type Slv105VectorArray is array (natural range<>, natural range<>) of slv(104 downto 0);
type Slv104VectorArray is array (natural range<>, natural range<>) of slv(103 downto 0);
type Slv103VectorArray is array (natural range<>, natural range<>) of slv(102 downto 0);
type Slv102VectorArray is array (natural range<>, natural range<>) of slv(101 downto 0);
type Slv101VectorArray is array (natural range<>, natural range<>) of slv(100 downto 0);
type Slv100VectorArray is array (natural range<>, natural range<>) of slv(99 downto 0);
type Slv99VectorArray is array (natural range<>, natural range<>) of slv(98 downto 0);
type Slv98VectorArray is array (natural range<>, natural range<>) of slv(97 downto 0);
type Slv97VectorArray is array (natural range<>, natural range<>) of slv(96 downto 0);
type Slv96VectorArray is array (natural range<>, natural range<>) of slv(95 downto 0);
type Slv95VectorArray is array (natural range<>, natural range<>) of slv(94 downto 0);
type Slv94VectorArray is array (natural range<>, natural range<>) of slv(93 downto 0);
type Slv93VectorArray is array (natural range<>, natural range<>) of slv(92 downto 0);
type Slv92VectorArray is array (natural range<>, natural range<>) of slv(91 downto 0);
type Slv91VectorArray is array (natural range<>, natural range<>) of slv(90 downto 0);
type Slv90VectorArray is array (natural range<>, natural range<>) of slv(89 downto 0);
type Slv89VectorArray is array (natural range<>, natural range<>) of slv(88 downto 0);
type Slv88VectorArray is array (natural range<>, natural range<>) of slv(87 downto 0);
type Slv87VectorArray is array (natural range<>, natural range<>) of slv(86 downto 0);
type Slv86VectorArray is array (natural range<>, natural range<>) of slv(85 downto 0);
type Slv85VectorArray is array (natural range<>, natural range<>) of slv(84 downto 0);
type Slv84VectorArray is array (natural range<>, natural range<>) of slv(83 downto 0);
type Slv83VectorArray is array (natural range<>, natural range<>) of slv(82 downto 0);
type Slv82VectorArray is array (natural range<>, natural range<>) of slv(81 downto 0);
type Slv81VectorArray is array (natural range<>, natural range<>) of slv(80 downto 0);
type Slv80VectorArray is array (natural range<>, natural range<>) of slv(79 downto 0);
type Slv79VectorArray is array (natural range<>, natural range<>) of slv(78 downto 0);
type Slv78VectorArray is array (natural range<>, natural range<>) of slv(77 downto 0);
type Slv77VectorArray is array (natural range<>, natural range<>) of slv(76 downto 0);
type Slv76VectorArray is array (natural range<>, natural range<>) of slv(75 downto 0);
type Slv75VectorArray is array (natural range<>, natural range<>) of slv(74 downto 0);
type Slv74VectorArray is array (natural range<>, natural range<>) of slv(73 downto 0);
type Slv73VectorArray is array (natural range<>, natural range<>) of slv(72 downto 0);
type Slv72VectorArray is array (natural range<>, natural range<>) of slv(71 downto 0);
type Slv71VectorArray is array (natural range<>, natural range<>) of slv(70 downto 0);
type Slv70VectorArray is array (natural range<>, natural range<>) of slv(69 downto 0);
type Slv69VectorArray is array (natural range<>, natural range<>) of slv(68 downto 0);
type Slv68VectorArray is array (natural range<>, natural range<>) of slv(67 downto 0);
type Slv67VectorArray is array (natural range<>, natural range<>) of slv(66 downto 0);
type Slv66VectorArray is array (natural range<>, natural range<>) of slv(65 downto 0);
type Slv65VectorArray is array (natural range<>, natural range<>) of slv(64 downto 0);
type Slv64VectorArray is array (natural range<>, natural range<>) of slv(63 downto 0);
type Slv63VectorArray is array (natural range<>, natural range<>) of slv(62 downto 0);
type Slv62VectorArray is array (natural range<>, natural range<>) of slv(61 downto 0);
type Slv61VectorArray is array (natural range<>, natural range<>) of slv(60 downto 0);
type Slv60VectorArray is array (natural range<>, natural range<>) of slv(59 downto 0);
type Slv59VectorArray is array (natural range<>, natural range<>) of slv(58 downto 0);
type Slv58VectorArray is array (natural range<>, natural range<>) of slv(57 downto 0);
type Slv57VectorArray is array (natural range<>, natural range<>) of slv(56 downto 0);
type Slv56VectorArray is array (natural range<>, natural range<>) of slv(55 downto 0);
type Slv55VectorArray is array (natural range<>, natural range<>) of slv(54 downto 0);
type Slv54VectorArray is array (natural range<>, natural range<>) of slv(53 downto 0);
type Slv53VectorArray is array (natural range<>, natural range<>) of slv(52 downto 0);
type Slv52VectorArray is array (natural range<>, natural range<>) of slv(51 downto 0);
type Slv51VectorArray is array (natural range<>, natural range<>) of slv(50 downto 0);
type Slv50VectorArray is array (natural range<>, natural range<>) of slv(49 downto 0);
type Slv49VectorArray is array (natural range<>, natural range<>) of slv(48 downto 0);
type Slv48VectorArray is array (natural range<>, natural range<>) of slv(47 downto 0);
type Slv47VectorArray is array (natural range<>, natural range<>) of slv(46 downto 0);
type Slv46VectorArray is array (natural range<>, natural range<>) of slv(45 downto 0);
type Slv45VectorArray is array (natural range<>, natural range<>) of slv(44 downto 0);
type Slv44VectorArray is array (natural range<>, natural range<>) of slv(43 downto 0);
type Slv43VectorArray is array (natural range<>, natural range<>) of slv(42 downto 0);
type Slv42VectorArray is array (natural range<>, natural range<>) of slv(41 downto 0);
type Slv41VectorArray is array (natural range<>, natural range<>) of slv(40 downto 0);
type Slv40VectorArray is array (natural range<>, natural range<>) of slv(39 downto 0);
type Slv39VectorArray is array (natural range<>, natural range<>) of slv(38 downto 0);
type Slv38VectorArray is array (natural range<>, natural range<>) of slv(37 downto 0);
type Slv37VectorArray is array (natural range<>, natural range<>) of slv(36 downto 0);
type Slv36VectorArray is array (natural range<>, natural range<>) of slv(35 downto 0);
type Slv35VectorArray is array (natural range<>, natural range<>) of slv(34 downto 0);
type Slv34VectorArray is array (natural range<>, natural range<>) of slv(33 downto 0);
type Slv33VectorArray is array (natural range<>, natural range<>) of slv(32 downto 0);
type Slv32VectorArray is array (natural range<>, natural range<>) of slv(31 downto 0);
type Slv31VectorArray is array (natural range<>, natural range<>) of slv(30 downto 0);
type Slv30VectorArray is array (natural range<>, natural range<>) of slv(29 downto 0);
type Slv29VectorArray is array (natural range<>, natural range<>) of slv(28 downto 0);
type Slv28VectorArray is array (natural range<>, natural range<>) of slv(27 downto 0);
type Slv27VectorArray is array (natural range<>, natural range<>) of slv(26 downto 0);
type Slv26VectorArray is array (natural range<>, natural range<>) of slv(25 downto 0);
type Slv25VectorArray is array (natural range<>, natural range<>) of slv(24 downto 0);
type Slv24VectorArray is array (natural range<>, natural range<>) of slv(23 downto 0);
type Slv23VectorArray is array (natural range<>, natural range<>) of slv(22 downto 0);
type Slv22VectorArray is array (natural range<>, natural range<>) of slv(21 downto 0);
type Slv21VectorArray is array (natural range<>, natural range<>) of slv(20 downto 0);
type Slv20VectorArray is array (natural range<>, natural range<>) of slv(19 downto 0);
type Slv19VectorArray is array (natural range<>, natural range<>) of slv(18 downto 0);
type Slv18VectorArray is array (natural range<>, natural range<>) of slv(17 downto 0);
type Slv17VectorArray is array (natural range<>, natural range<>) of slv(16 downto 0);
type Slv16VectorArray is array (natural range<>, natural range<>) of slv(15 downto 0);
type Slv15VectorArray is array (natural range<>, natural range<>) of slv(14 downto 0);
type Slv14VectorArray is array (natural range<>, natural range<>) of slv(13 downto 0);
type Slv13VectorArray is array (natural range<>, natural range<>) of slv(12 downto 0);
type Slv12VectorArray is array (natural range<>, natural range<>) of slv(11 downto 0);
type Slv11VectorArray is array (natural range<>, natural range<>) of slv(10 downto 0);
type Slv10VectorArray is array (natural range<>, natural range<>) of slv(9 downto 0);
type Slv9VectorArray is array (natural range<>, natural range<>) of slv(8 downto 0);
type Slv8VectorArray is array (natural range<>, natural range<>) of slv(7 downto 0);
type Slv7VectorArray is array (natural range<>, natural range<>) of slv(6 downto 0);
type Slv6VectorArray is array (natural range<>, natural range<>) of slv(5 downto 0);
type Slv5VectorArray is array (natural range<>, natural range<>) of slv(4 downto 0);
type Slv4VectorArray is array (natural range<>, natural range<>) of slv(3 downto 0);
type Slv3VectorArray is array (natural range<>, natural range<>) of slv(2 downto 0);
type Slv2VectorArray is array (natural range<>, natural range<>) of slv(1 downto 0);
type Slv1VectorArray is array (natural range<>, natural range<>) of slv(0 downto 0);
type SlVectorArray is array (natural range<>, natural range<>) of sl;
-- Mux a SlVectorArray into an SLV
function muxSlVectorArray (vec : SlVectorArray; addr : natural; allowOutOfRange : boolean := false) return slv;
end StdRtlPkg;
package body StdRtlPkg is
function slvAll (size : positive; value : sl) return slv is
variable retVar : slv(size-1 downto 0) := (others => value);
begin
return retVar;
end function slvAll;
function slvZero (size : positive) return slv is
begin
return slvAll(size, '0');
end function;
function slvOne (size : positive) return slv is
begin
return slvAll(size, '1');
end function;
function isPowerOf2 (number : natural) return boolean is
begin
return isPowerOf2(toSlv(number, 32));
end function isPowerOf2;
function isPowerOf2 (vector : slv) return boolean is
begin
return (unsigned(vector) /= 0) and
(unsigned(unsigned(vector) and (unsigned(vector)-1)) = 0);
end function isPowerOf2;
---------------------------------------------------------------------------------------------------------------------
-- Function: log2
-- Purpose: Finds the log base 2 of an integer
-- Input is rounded up to nearest power of two.
-- Therefore log2(5) = log2(8) = 3.
-- Arg: number - integer to find log2 of
-- Returns: Integer containing log base two of input.
---------------------------------------------------------------------------------------------------------------------
function log2(constant number : positive) return natural is
begin
return integer(ceil(ieee.math_real.log2(real(number))));
end function;
-- Find number of bits needed to store a number
function bitSize (constant number : natural ) return positive is
begin
if (number = 0 or number = 1) then
return 1;
else
if (isPowerOf2(number)) then
return log2(number) + 1;
else
return log2(number);
end if;
end if;
end function;
-- NOTE: XST will crap its pants if you try to pass a constant to this function
function bitReverse (a : slv) return slv is
variable resultVar : slv(a'range);
alias aa : slv(a'reverse_range) is a;
begin
for i in aa'range loop
resultVar(i) := aa(i);
end loop;
return resultVar;
end;
function list (constant start, size, step : integer) return IntegerArray is
variable retVar : IntegerArray(0 to size-1);
begin
for i in retVar'range loop
retVar(i) := start + (i * step);
end loop;
return retVar;
end function list;
function toBoolean (logic : sl) return boolean is
begin -- function toBoolean
return logic = '1';
end function toBoolean;
function toSl (bool : boolean) return sl is
begin
if (bool) then
return '1';
else
return '0';
end if;
end function toSl;
function toString (bool : boolean) return string is
begin
if (bool) then
return "TRUE";
else
return "FALSE";
end if;
end function toString;
function toBoolean (str : string) return boolean is
begin
if (str = "TRUE" or str = "true") then
return true;
else
return false;
end if;
end function toBoolean;
--------------------------------------------------------------------------------------------------
-- Decode and genmux
--------------------------------------------------------------------------------------------------
-- generic decoder
function decode(v : slv) return slv is
variable res : slv((2**v'length)-1 downto 0);
variable i : integer range res'range;
begin
res := (others => '0');
i := 0;
i := to_integer(unsigned(v));
res(i) := '1';
return res;
end;
-- generic multiplexer
function genmux(s, v : slv) return sl is
variable res : slv(v'length-1 downto 0);
variable i : integer range res'range;
begin
res := v;
i := 0;
i := to_integer(unsigned(s));
return res(i);
end;
---------------------------------------------------------------------------------------------------------------------
-- Unary reduction operators
---------------------------------------------------------------------------------------------------------------------
function uOr (vec : slv) return sl is
begin
for i in vec'range loop
if (vec(i) = '1') then
return '1';
end if;
end loop;
return '0';
end function uOr;
function uAnd (vec : slv) return sl is
begin
for i in vec'range loop
if (vec(i) = '0') then
return '0';
end if;
end loop;
return '1';
end function uAnd;
function uXor (vec : slv) return sl is
variable intVar : sl;
begin
for i in vec'range loop
if (i = vec'left) then
intVar := vec(i);
else
intVar := intVar xor vec(i);
end if;
end loop;
return intVar;
end function uXor;
function allBits (vec : slv; test : sl) return boolean is
begin
for i in vec'range loop
if (vec(i) /= test) then
return false;
end if;
end loop;
return true;
end function;
function noBits (vec : slv; test : sl) return boolean is
begin
for i in vec'range loop
if (vec(i) = test) then
return false;
end if;
end loop;
return true;
end function;
-----------------------------------------------------------------------------
-- Functions to determine parity of arbitrary sized slv
-----------------------------------------------------------------------------
-- returns '1' if vec has even parity
function evenParity (vec : slv)
return sl is
begin
return not uXor(vec);
end function;
-- return '1' if vec has odd parity
function oddParity (vec : slv)
return sl is
begin
return uXor(vec);
end function;
-----------------------------------------------------------------------------
-- Functions for counting the number of '1' in a slv bus
-----------------------------------------------------------------------------
-- New Non-recursive onesCount Function
function onesCount (vec : slv)
return unsigned is
variable retVar : unsigned((bitSize(vec'length)-1) downto 0) := to_unsigned(0,bitSize(vec'length));
begin
for i in vec'range loop
if vec(i) = '1' then
retVar := retVar + 1;
end if;
end loop;
return retVar;
end function;
-- -- Old Recursive onesCount Function
-- function onesCount (vec : slv) return unsigned is
-- variable topVar : slv(vec'high downto vec'low+(vec'length/2));
-- variable bottomVar : slv(topVar'low-1 downto vec'low);
-- variable tmpVar : slv(2 downto 0);
-- begin
-- if (vec'length = 1) then
-- return '0' & unsigned(vec);
-- end if;
-- if (vec'length = 2) then
-- return uAnd(vec) & uXor(vec);
-- end if;
-- if (vec'length = 3) then
-- tmpVar := vec;
-- case tmpVar is
-- when "000" => return "00";
-- when "001" => return "01";
-- when "010" => return "01";
-- when "011" => return "10";
-- when "100" => return "01";
-- when "101" => return "10";
-- when "110" => return "10";
-- when "111" => return "11";
-- when others => return "00";
-- end case;
-- end if;
-- topVar := vec(vec'high downto (vec'high+1)-((vec'length+1)/2));
-- bottomVar := vec(vec'high-((vec'length+1)/2) downto vec'low);
-- return ('0' & onesCount(topVar)) + ('0' & onesCount(bottomVar));
-- end function;
-- SLV variant
function onesCount (vec : slv)
return slv is
variable retVar : slv((bitSize(vec'length)-1) downto 0);
variable cntVar : unsigned((bitSize(vec'length)-1) downto 0);
begin
cntVar := onesCount(vec);
retVar := slv(cntVar);
return retVar;
end function;
-----------------------------------------------------------------------------
-- Functions for encoding and decoding grey codes
-----------------------------------------------------------------------------
-- Get next gray code given binary vector
function grayEncode (vec : unsigned)
return unsigned is
begin
return vec xor shift_right(vec, 1);
end function;
-- SLV variant
function grayEncode (vec : slv)
return slv is
begin
return slv(grayEncode(unsigned(vec)));
end function;
-- Get the binary equivalent of a Gray code created with gray_encode.
function grayDecode (vec : unsigned)
return unsigned is
variable retVar : unsigned(vec'range) := (others => '0');
begin
for i in vec'range loop
if (i = vec'left) then
retVar(i) := vec(i);
else
if (vec'ascending) then
retVar(i) := retVar(i-1) xor vec(i);
else
retVar(i) := retVar(i+1) xor vec(i);
end if;
end if;
end loop;
return retVar;
end function;
-- SLV variant
function grayDecode (vec : slv)
return slv is
variable retVar : slv(vec'range) := (others => '0');
begin
return slv(grayDecode(unsigned(vec)));
end function;
-------------------------------------------------------------------------------------------------
-- Implements an N tap linear feedback shift operation
-- Size of LFSR is variable and determined by length of lfsr parameter
-- Number of taps is variable and determined by length of taps array parameter
-- An input parameter is also available for use in scramblers
-- Output is new lfsr value after one shift operation
-- The lfsr param can be indexed ascending or decending
-- The shift is in the direction of increasing index (left shift for decending, right for ascending)
-------------------------------------------------------------------------------------------------
function lfsrShift (lfsr : slv; constant taps : NaturalArray; input : sl := '0') return slv is
variable retVar : slv(lfsr'range) := (others => '0');
begin
if (lfsr'ascending) then
retVar := input & lfsr(lfsr'left to lfsr'right-1);
else
retVar := lfsr(lfsr'left-1 downto lfsr'right) & input;
end if;
for i in taps'range loop
assert (taps(i) <= lfsr'high) report "lfsrShift() - Tap value exceedes lfsr range" severity failure;
retVar(lfsr'low) := retVar(lfsr'low) xor lfsr(taps(i));
end loop;
return retVar;
end function;
-------------------------------------------------------------------------------------------------
-- One line if-then-else functions.
-------------------------------------------------------------------------------------------------
function ite (i : boolean; t : boolean; e : boolean) return boolean is
begin
if (i) then return t; else return e; end if;
end function ite;
function ite (i : boolean; t : sl; e : sl) return sl is
begin
if (i) then return t; else return e; end if;
end function ite;
function ite (i : boolean; t : slv; e : slv) return slv is
begin
if (i) then return t; else return e; end if;
end function ite;
function ite (i : boolean; t : bit_vector; e : bit_vector) return bit_vector is
begin
if (i) then return t; else return e; end if;
end function ite;
function ite (i : boolean; t : character; e : character) return character is
begin
if (i) then return t; else return e; end if;
end function ite;
function ite (i : boolean; t : string; e : string) return string is
begin
if (i) then return t; else return e; end if;
end function ite;
function ite (i : boolean; t : integer; e : integer) return integer is
begin
if (i) then return t; else return e; end if;
end function ite;
function ite (i : boolean; t : real; e : real) return real is
begin
if (i) then return t; else return e; end if;
end function ite;
function ite (i : boolean; t : time; e : time) return time is
begin
if (i) then return t; else return e; end if;
end function ite;
-----------------------------
-- Min and Max
-----------------------------
function maximum (left, right : integer) return integer is
begin
if left > right then return left;
else return right;
end if;
end maximum;
function minimum (left, right : integer) return integer is
begin
if left < right then return left;
else return right;
end if;
end minimum;
-----------------------------
-- conv_std_logic_vector functions
-- without calling the STD_LOGIC_ARITH library
-----------------------------
-- convert an integer to an STD_LOGIC_VECTOR
function toSlv(ARG : integer; SIZE : integer) return slv is
begin
return slv(to_unsigned(ARG, SIZE));
end;
-----------------------------
-- gets real multiplication
-----------------------------
function getRealMult (A, B : real) return real is
begin
return real(A*B);
end function;
function getRealMult (A : integer; B : real) return real is
begin
return real(real(A)*B);
end function;
function getRealMult (A : real; B : integer) return real is
begin
return real(A*real(B));
end function;
-----------------------------
-- gets real division
-----------------------------
function getRealDiv (A, B : real) return real is
begin
return real(A/B);
end function;
function getRealDiv (A : integer; B : real) return real is
begin
return real(real(A)/B);
end function;
function getRealDiv (A : real; B : integer) return real is
begin
return real(A/real(B));
end function;
-------------------------------------------------------------------------------------------------
-- Simulates an ADC conversion
-------------------------------------------------------------------------------------------------
function adcConversion (
ain : real;
low : real;
high : real;
bits : positive;
twosComp : boolean)
return slv is
variable tmpR : real;
variable tmpI : integer;
variable retSigned : signed(bits-1 downto 0);
variable retUnsigned : unsigned(bits-1 downto 0);
begin
tmpR := ain;
-- Constrain input to full scale range
tmpR := realmin(high, tmpR);
tmpR := realmax(low, tmpR);
-- Scale to [0,1] or [-.5,.5]
tmpR := (tmpR-low)/(high-low) + ite(twosComp, -0.5, 0.0);
-- Scale to number of bits
tmpR := tmpR * real(2**bits);
if (twosComp) then
retSigned := to_signed(integer(round(tmpR)), bits);
return slv(retSigned);
else
retUnsigned := to_unsigned(integer(round(tmpR)), bits);
return slv(retUnsigned);
end if;
end function adcConversion;
-----------------------------
-- gets a time ratio
-----------------------------
function getTimeRatio (T1, T2 : time) return natural is
begin
return natural(T1/T2);
end function;
function getTimeRatio (T1, T2 : real) return natural is
begin
return natural(ROUND(abs(T1/T2)));
end function;
---------------------------------------------------------------------------------------------------------------------
-- Convert a frequency to a period (time).
---------------------------------------------------------------------------------------------------------------------
-- pragma translate_off
function toTime(f : frequency) return time is
begin
return(1.0 sec / (f/Hz));
end function;
--pragma translate_on
-----------------------------
-- Mux a SlVectorArray into an SLV
-----------------------------
function muxSlVectorArray (vec : SlVectorArray;
addr : natural;
allowOutOfRange : boolean := false)
return slv is
variable retVar : slv(vec'range(2));
begin
-- Check the limit of the address
if (addr < vec'length(1)) or (allowOutOfRange = false) then
for i in vec'range(2) loop
retVar(i) := vec(addr, i);
end loop;
else
retVar := (others => '0');
end if;
return retVar;
end function;
procedure assignSlv (
i : inout integer;
vector : inout slv;
value : in slv)
is
variable low : integer;
begin
low := i;
i := i+value'length;
vector(i-1 downto low) := value;
end procedure assignSlv;
procedure assignSlv (
i : inout integer;
vector : inout slv;
value : in sl)
is
variable low : integer;
begin
vector(i) := value;
i := i+1;
end procedure assignSlv;
procedure assignRecord (
i : inout integer;
vector : in slv;
value : inout slv)
is
variable low : integer;
begin
low := i;
i := i+value'length;
value := vector(i-1 downto low);
end procedure assignRecord;
procedure assignRecord (
i : inout integer;
vector : in slv;
value : inout sl)
is
variable low : integer;
begin
value := vector(i);
i := i+1;
end procedure assignRecord;
-- Resize an SLV, either by trimming or padding upper bits
function resizeSlv ( vector : slv; newSize : integer) return slv is
variable retVar : slv(newSize-1 downto 0);
variable top : integer;
begin
retVar := (others=>'0');
top := minimum( newSize, vector'length) - 1;
retVar(top downto 0) := vector(top downto 0);
return retVar;
end function;
end package body StdRtlPkg;
| gpl-3.0 | 078b7cdb264c115b447f71e9cedf9e48 | 0.649906 | 4.214928 | false | false | false | false |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/synth/ZynqDesign_axi_gpio_1_1.vhd | 1 | 9,653 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY ZynqDesign_axi_gpio_1_1 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ZynqDesign_axi_gpio_1_1;
ARCHITECTURE ZynqDesign_axi_gpio_1_1_arch OF ZynqDesign_axi_gpio_1_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ZynqDesign_axi_gpio_1_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ZynqDesign_axi_gpio_1_1_arch: ARCHITECTURE IS "axi_gpio,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ZynqDesign_axi_gpio_1_1_arch : ARCHITECTURE IS "ZynqDesign_axi_gpio_1_1,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ZynqDesign_axi_gpio_1_1_arch: ARCHITECTURE IS "ZynqDesign_axi_gpio_1_1,axi_gpio,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=8,C_GPIO2_WIDTH=32,C_ALL_INPUTS=1,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END ZynqDesign_axi_gpio_1_1_arch;
| mit | d0a50621c10a08dbf4dc6fd7e24c452c | 0.688698 | 3.199536 | false | false | false | false |
tdotu/ra | dLatch.vhd | 1 | 777 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dLatch IS
PORT
(
d : IN std_logic;
c : IN std_logic;
q : OUT std_logic;
qi : OUT std_logic
);
END dLatch;
ARCHITECTURE behaviour OF dLatch IS
COMPONENT rs IS
PORT
(
r : IN std_logic;
s : IN std_logic;
q : OUT std_logic;
qi : OUT std_logic
);
END COMPONENT;
SIGNAL r,s : std_logic;
BEGIN
r <= s nand c;
s <= d nand c;
rsLatch : rs PORT MAP(r, s, q, qi);
END behaviour;
ARCHITECTURE betterBehaviour OF dLatch IS
SIGNAL value : std_logic;
BEGIN
save : PROCESS(d, c)
BEGIN
IF(d = '1' AND (d'event OR c'event)) THEN
value <= c;
END IF;
END PROCESS;
q <= c;
qi <= NOT c;
END betterBehaviour;
| gpl-3.0 | 2c67bef1e3f42a7a01b3b754817a3ec1 | 0.557272 | 2.805054 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_OUT2_ENC8b10b.vhd | 4 | 5,403 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! 8b10b encoder for EPROC_OUT2 module
entity EPROC_OUT2_ENC8b10b is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(1 downto 0)
);
end EPROC_OUT2_ENC8b10b;
architecture Behavioral of EPROC_OUT2_ENC8b10b is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
component enc8b10_wrap
port (
clk : in std_logic;
rst : in std_logic;
dataCode : in std_logic_vector (1 downto 0); -- 00"data, 01"eop, 10"sop, 11"comma
dataIN : in std_logic_vector (7 downto 0);
dataINrdy : in std_logic;
encDataOut : out std_logic_vector (9 downto 0);
encDataOutrdy : out std_logic
);
end component enc8b10_wrap;
----------------------------------
----------------------------------
component MUX8_Nbit
generic (N : integer := 16);
Port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
data2 : in std_logic_vector((N-1) downto 0);
data3 : in std_logic_vector((N-1) downto 0);
data4 : in std_logic_vector((N-1) downto 0);
data5 : in std_logic_vector((N-1) downto 0);
data6 : in std_logic_vector((N-1) downto 0);
data7 : in std_logic_vector((N-1) downto 0);
sel : in std_logic_vector(2 downto 0);
data_out : out std_logic_vector((N-1) downto 0)
);
end component MUX8_Nbit;
----------------------------------
----------------------------------
constant zeros2bit : std_logic_vector (1 downto 0) := (others=>'0');
signal enc10bit, enc10bit_r : std_logic_vector (9 downto 0);
signal request_cycle_cnt, send_count : std_logic_vector (2 downto 0) := (others=>'0');
signal send_out_trig : std_logic := '0';
signal inp_request_trig, inp_request_trig_out : std_logic;
begin
-------------------------------------------------------------------------------------------
-- input handshaking, request cycle 5 CLKs
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
request_cycle_cnt <= (others=>'0');
else
if inp_request_trig = '1' then
request_cycle_cnt <= (others=>'0');
else
request_cycle_cnt <= request_cycle_cnt + 1;
end if;
end if;
end if;
end process;
--
inp_request_trig <= '1' when (request_cycle_cnt = "100") else '0';
--
inp_reques1clk: pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitCLKx4, inp_request_trig, inp_request_trig_out);
getDataTrig <= inp_request_trig_out;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
send_out_trig <= inp_request_trig;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b encoding
-------------------------------------------------------------------------------------------
enc8b10bx: enc8b10_wrap
port map (
clk => bitCLKx4,
rst => rst,
dataCode => edataIN(9 downto 8), -- 00"data, 01"eop, 10"sop, 11"comma
dataIN => edataIN(7 downto 0),
dataINrdy => edataINrdy, -- one? CLKx4 after inp_request_trig_out
encDataOut => enc10bit
);
-------------------------------------------------------------------------------------------
-- sending out 2 bits @ bitCLK
-------------------------------------------------------------------------------------------
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
enc10bit_r <= (others=>'0');
elsif send_out_trig = '1' then
enc10bit_r <= enc10bit;
end if;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if send_out_trig = '1' then
send_count <= (others=>'0');
else
send_count <= send_count + 1;
end if;
end if;
end process;
--
outmux: MUX8_Nbit
generic map (N=>2)
port map (
data0 => enc10bit_r(1 downto 0),
data1 => enc10bit_r(3 downto 2),
data2 => enc10bit_r(5 downto 4),
data3 => enc10bit_r(7 downto 6),
data4 => enc10bit_r(9 downto 8),
data5 => zeros2bit,
data6 => zeros2bit,
data7 => zeros2bit,
sel => send_count,
data_out => EdataOUT
);
--
end Behavioral;
| gpl-3.0 | 60746b0ee4978dae82d97b6e82d521f8 | 0.477698 | 3.430476 | false | false | false | false |
AndyMcC0/UVVM_All | bitvis_vip_avalon_mm/src/vvc_cmd_pkg.vhd | 3 | 7,444 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_cmd_pkg is
--===============================================================================================
-- t_operation
-- - Bitvis defined BFM operations
--===============================================================================================
type t_operation is (
-- UVVM common
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
WRITE, READ, CHECK, RESET, LOCK, UNLOCK);
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 1024;
constant C_VVC_CMD_ADDR_MAX_LENGTH : natural := 64;
constant C_VVC_CMD_BYTE_ENABLE_MAX_LENGTH : natural := 128;
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--===============================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--===============================================================================================
type t_vvc_cmd_record is record
-- Common UVVM fields (Used by td_vvc_framework_common_methods_pkg procedures, and thus mandatory)
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued; -- QUEUED/IMMEDIATE
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
-- VVC dedicated fields
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0); -- Max width may be increased if required
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
byte_enable : std_logic_vector(C_VVC_CMD_BYTE_ENABLE_MAX_LENGTH-1 downto 0);
max_polls : integer;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
operation => NO_OPERATION, -- Default unless overwritten by a common operation
addr => (others => '0'),
data => (others => '0'),
byte_enable => (others => '1'), -- All bytes enabled by default
max_polls => 1,
alert_level => failure,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_command_type,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
delay => 0 ns,
quietness => NON_QUIET
);
--===============================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--===============================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--===============================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1));
end package vvc_cmd_pkg;
--=================================================================================================
--=================================================================================================
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
| mit | c792f50c5152e6f7e2cdf1299d133970 | 0.448818 | 5.133793 | false | false | false | false |
SKravitsky/ECEC412 | MEMWBRegister.vhd | 1 | 1,108 | library ieee;
use ieee.std_logic_1164.all;
entity MEMWBRegister is
port(
clk, MemtoRegIn, RegWriteIn: in std_logic;
WriteRegisterIn: in std_logic_vector(4 downto 0);
ReadDataIn, ALUResultIn: in std_logic_vector(31 downto 0);
MemtoRegOut, RegWriteOut: out std_logic;
WriteRegisterOut: out std_logic_vector(4 downto 0);
ReadDataOut, ALUResultOut: out std_logic_vector(31 downto 0)
);
end MEMWBRegister;
architecture Structural of MEMWBRegister is
signal MemtoReg, RegWrite: std_logic := '0';
signal WriteRegister: std_logic_vector(4 downto 0) := "00000";
signal ReadData, ALUResult: std_logic_vector(31 downto 0) := X"00000000";
begin
MemtoRegOut <= MemtoReg;
RegWriteOut <= RegWrite;
WriteRegisterOut <= WriteRegister;
ReadDataOut <= ReadData;
ALUResultOut <= ALUResult;
process(clk)
begin
if rising_edge(clk) then
MemtoReg <= MemtoRegIn;
RegWrite <= RegWriteIn;
WriteRegister <= WriteRegisterIn;
ReadData <= ReadDataIn;
ALUResult <= ALUResultIn;
end if;
end process;
end Structural;
| apache-2.0 | 6df718f74cabc667fe3594238ec41860 | 0.687726 | 4.103704 | false | false | false | false |
elainemielas/CVUT_BI-PNO | project2/keyboard.vhd | 1 | 3,379 | library ieee;
use ieee.std_logic_1164.all;
entity keyboard is
port (
PS2_DATA : in std_logic; -- serial PS2 input
PS2_CLK : in std_logic; -- serial PS2 clock
KEY_F : out std_logic; -- high for one clock when key 'f' pressed
KEY_U : out std_logic; -- high for one clock when key 'u' pressed
KEY_L : out std_logic; -- high for one clock when key 'l' pressed
KEY_PRESS : out std_logic; -- high for one clock when any key pressed
CLK : in std_logic; -- standard 50MHz clock
RESET : in std_logic
);
end keyboard;
architecture keyboard_body of keyboard is
component RECEIVER
port (
PS2_DATA : in std_logic; -- serial PS2 input
PS2_CLK : in std_logic; -- serial PS2 clock
CLK : in std_logic; -- standard 50MHz clock
RESET : in std_logic;
SCAN_CODE : out std_logic_vector ( 7 downto 0 );
NEW_SC : out std_logic
);
end component;
signal NEW_SC : std_logic;
signal PS2_DATA1, PS2_DATA2, PS2_CLK1, PS2_CLK2 : std_logic;
signal SC : std_logic_vector ( 7 downto 0 );
type T_STATE is ( OK, IGNORE );
signal STATE, NEXT_STATE : T_STATE;
begin
PS2_PR : process ( CLK )
begin
if CLK = '1' and CLK'event then
PS2_DATA1 <= PS2_DATA;
PS2_DATA2 <= PS2_DATA1;
PS2_CLK1 <= PS2_CLK;
PS2_CLK2 <= PS2_CLK1;
end if;
end process;
RECEIVER_COMPONENT : RECEIVER port map ( PS2_DATA2, PS2_CLK2, CLK, RESET, SC, NEW_SC );
--NEW_SC_D <= NEW_SC when rising_edge(clk);
TRANSPR : process ( STATE, SC, NEW_SC )
begin
case STATE is
when OK => if NEW_SC = '1' and ( SC = "11110000" or SC = "11100000" ) then
NEXT_STATE <= IGNORE;
else
NEXT_STATE <= OK;
end if;
when IGNORE => if NEW_SC = '1' and ( SC = "11110000" or SC = "11100000" ) then
NEXT_STATE <= IGNORE;
elsif NEW_SC = '1' then
NEXT_STATE <= OK;
else
NEXT_STATE <= IGNORE;
end if;
end case;
end process;
REGPR : process ( CLK )
begin
if CLK = '1' and CLK'event then
if RESET = '1' then
STATE <= OK;
else
STATE <= NEXT_STATE;
end if;
end if;
end process;
OUTPR : process ( STATE, SC, NEW_SC )
begin
case STATE is
when OK => if NEW_SC = '1' then
case SC is
when "00101011" => KEY_F <= '1';
KEY_U <= '0';
KEY_L <= '0';
KEY_PRESS <= '1';
when "00111100" => KEY_F <= '0';
KEY_U <= '1';
KEY_L <= '0';
KEY_PRESS <= '1';
when "01001011" => KEY_F <= '0';
KEY_U <= '0';
KEY_L <= '1';
KEY_PRESS <= '1';
when "11100000" | "11110000" => KEY_F <= '0';
KEY_U <= '0';
KEY_L <= '0';
KEY_PRESS <= '0';
when others => KEY_F <= '0';
KEY_U <= '0';
KEY_L <= '0';
KEY_PRESS <= '1';
end case;
else
KEY_F <= '0';
KEY_U <= '0';
KEY_L <= '0';
KEY_PRESS <= '0';
end if;
when IGNORE => KEY_F <= '0';
KEY_U <= '0';
KEY_L <= '0';
KEY_PRESS <= '0';
end case;
end process;
end keyboard_BODY;
| mit | 29cdb257d83e64438e9d23944d0fd4d7 | 0.483871 | 3.000888 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/xilinx_image.vhd | 3 | 181,451 | ---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1);
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"afafafafafafafafafafafafafafafaf2308000c241400ac273c243c243c273c",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f230c008c8c3caf00af00af2340afaf",
INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f",
INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac",
INIT_04 => X"8c343c00af03af270003278f0300ac008f34af0000000014008f8fafaf03af27",
INIT_05 => X"008f000c2400142480008f0010af03afaf270003278f0300ac008f3c00103000",
INIT_06 => X"008f8f0010af24af03afaf270003278f8f030000140080008f000c000080af24",
INIT_07 => X"03000004008faf24008f000c0024008f0010000c0024008f00102c008faf3000",
INIT_08 => X"0c000080af24008f0010af27000c8f008f002727afafaf03afaf270003278f8f",
INIT_09 => X"3c03af270003278f8f030000140080008fa0248faf24008f0014248024008f00",
INIT_0A => X"0000000003278f8f030000008c3c0010000c0003afaf270003278f0330008c34",
INIT_0B => X"243c000c343c243c24000c343c243c24000c243c000c243c000c243c03afaf27",
INIT_0C => X"24243c243c243caf243caf24000c24243c243c243caf243caf24000c243c000c",
INIT_0D => X"000c343c243c243c243caf243caf24000c343c243c243c243caf243caf24000c",
INIT_0E => X"243c000c000c243c000c243c000c000c243c000c243c000c000c243c000c243c",
INIT_0F => X"3c000c243c0010000c243c0014008c3c000c243c000c243c000c000c243c000c",
INIT_10 => X"af240010af24afaf03afaf270003278f8f0300000c24000c0024008c3c000c24",
INIT_11 => X"0c8f24000010008f001400008f8faf24008f0010af001400000014008f8f0010",
INIT_12 => X"24008faf240010008f8c002400008f3c000c0024008c002400008f3c000c2400",
INIT_13 => X"0c243c0010ac3c24008c3c000c243c0014248f001428008faf24008f000c24af",
INIT_14 => X"0087000c24000c8faf00008f870010a7afafafaf03afaf270003278f8f030000",
INIT_15 => X"0087a730240097af240010008f8c00008f000087000c24000c00008c00008f00",
INIT_16 => X"000c243c0010ac3c24008c3c000c243c0014248f000c8f2400000c243c001428",
INIT_17 => X"87000c24000c8faf0000008f870010a7afafafafaf03afaf270003278f8f0300",
INIT_18 => X"87a730240097af240010008f8c00008f000087000c24000c00008c00008f0000",
INIT_19 => X"008c00008f000087000c24000c8faf0000008f2400870010a7000c2400142800",
INIT_1A => X"000c240014280087a730240097af240010008f8c00008f000087000c24000c00",
INIT_1B => X"000c00008c00008f0000343c87000c24000c8faf0000000014008f870010a724",
INIT_1C => X"24000c240014280087a730240097af240010008f8c00008f0000343c87000c24",
INIT_1D => X"0c24000c00008c00008f0000343c87000c24000c8faf00000014008f870010a7",
INIT_1E => X"2400000c243c0014280087a730240097af240010008f8c00008f0000343c8700",
INIT_1F => X"af270003278f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c8f",
INIT_20 => X"0c24000c00008c002400008f3c000c24000c8faf00008f8f0010afafaf2403af",
INIT_21 => X"008f8f0010af000c24001428008faf24008faf240010008f8c002400008f3c00",
INIT_22 => X"10008f8c002400008f3c000c24000c00008c002400008f3c000c24000c8faf00",
INIT_23 => X"0010ac3c24008c3c000c243c0014248f000c243c001428008faf24008faf2400",
INIT_24 => X"8f0000008fa000278f0000008f0010afaf03afaf270003278f8f0300000c243c",
INIT_25 => X"00af008000278f0010af001428008faf24008fac008f002700008fa400270000",
INIT_26 => X"10008f8c002400008f3c000c24000c0024008c002400008f3c000c24000c8f24",
INIT_27 => X"24000c0024008c002400008f3c000c24000c8f2400af0084002700008faf2400",
INIT_28 => X"3c000c24000c8f2400af008c002700008faf240010008f8c002400008f3c000c",
INIT_29 => X"8faf24008faf240010008f8c002400008f3c000c24000c0024008c002400008f",
INIT_2A => X"8f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c243c00142800",
INIT_2B => X"000c24000c00008c3c000c24000c8faf00008f8fafaf24af2403afaf27000327",
INIT_2C => X"8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f8c3c",
INIT_2D => X"008f8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f",
INIT_2E => X"240010008f8c243c000c24000c00008c243c000c24000c8faf00008faf240010",
INIT_2F => X"008faf240010008f8c243c000c24000c00008c243c000c24000c8faf24008faf",
INIT_30 => X"0014248f000c243caf240010008f8c243c000c00008c243c000c24000c8faf24",
INIT_31 => X"28008c3caf03af27000003278f8f0300000c243c0010ac3c24008c3c000c243c",
INIT_32 => X"a324af03af270003278f0324001000ac3c24008c3cac008f0024003c8c3c0010",
INIT_33 => X"14003c8c340010240010248c3c00100083a4248fa3001000102400100094008f",
INIT_34 => X"af270003278f0324a4008fa30010ac3cac243cac3cac008c3c240018008c3c00",
INIT_35 => X"0010240010248c3c00100083a4248fa3001000102400100094008fa324afaf03",
INIT_36 => X"3cac0024003c8c248c3c001028008c3c0004008f0010008faf008c34af008c34",
INIT_37 => X"af008fafaf03af270003278f0324a4008fa30010ac243cac3cac3cac3c24008c",
INIT_38 => X"10afafafafaf03afaf270003278f038f00140080a00080af24008faf24008f00",
INIT_39 => X"8f8faf240010af240010248f0004008fa3001428008faf24008fa02400278f00",
INIT_3A => X"008f001028008faf0000000014008f8faf00000014008f8f0010af24af000000",
INIT_3B => X"1000008c008f00008f240014008fa000278f0000302430008f00100000302430",
INIT_3C => X"8f0010008c008fa02400278faf24008f0014248f0000100004008faf24008f00",
INIT_3D => X"2700248c008f0010ac008f00008f24000c8f0000008f2700100000008f248c00",
INIT_3E => X"af03af270003278f0300ac343c343cafaf03af270003278f8f0300000c8f0000",
INIT_3F => X"008fafaf03af270003278f038f0014008faf00008f24008faf302c008f0010af"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"b8afaeadacabaaa9a8a7a6a5a4a3a2a1bd000000a560a4a0bd1d8404a5059c1c",
INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9",
INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf",
INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594",
INIT_04 => X"42420200c4a0bebd00e0bdbec0004300c302c2000007624000c2c3c5c4a0bebd",
INIT_05 => X"00c20000040062024300c20000c4a0bebfbd00e0bdbec0004300c30200404200",
INIT_06 => X"00c2c30000c202c4a0bebfbd00e0bdbebfc0000040004200c20000400042c343",
INIT_07 => X"c000004100c2c24200c20000404200c200000000404200c200404200c2c24243",
INIT_08 => X"00400042c34300c20000c2c20000c440c660c2c3c6c5c4a0bebfbd00e0bdbebf",
INIT_09 => X"02a0bebd00e0bdbebfc0000040004200c24303c2c24200c2006202434200c200",
INIT_0A => X"00000000e0bdbebfc002020042020040000000a0bebfbd00e0bdbec042004242",
INIT_0B => X"44020000440245020600004402450206000044020000440200004402a0bebfbd",
INIT_0C => X"04450246024702a24202a202000004450246024702a24202a202000044020000",
INIT_0D => X"00004402450246024702a24202a20200004402450246024702a24202a2020000",
INIT_0E => X"4402000000004402000044020000000044020000440200000000440200004402",
INIT_0F => X"0200004402000000004402004000420200004402000044020000000044020000",
INIT_10 => X"c2020000c202c0c0a0bebfbd00e0bdbebfc00000000400004005004202000044",
INIT_11 => X"00c40500004000c200406200c2c3c24200c20000c000400007624000c2c30000",
INIT_12 => X"4200c2c202006200c24362420300c30200004005004262420300c30200000400",
INIT_13 => X"004402000043024300420200004402006202c300404200c2c24200c2000004c2",
INIT_14 => X"00c20000040000c4c24300c3c20000c0c0c6c5c4a0bebfbd00e0bdbebfc00000",
INIT_15 => X"00c2c2424200c2c202006200c2436200c30200c200000400004000426200c302",
INIT_16 => X"00004402000043024300420200004402006202c30000c4050000004402004042",
INIT_17 => X"c20000040000c4c2006200c2c30000c0c0c7c6c5c4a0bebfbd00e0bdbebfc000",
INIT_18 => X"c2c2424200c2c202006200c2436200c30200c200000400004000426200c30200",
INIT_19 => X"00426200c30200c20000040000c4c2006200c24300c20000c000000400404200",
INIT_1A => X"00000400404200c2c2424200c2c202006200c2436200c30200c2000004000040",
INIT_1B => X"00004000426200c302624202c30000040000c4c2000007624000c3c20000c202",
INIT_1C => X"0200000400404200c2c2424200c2c202006200c2436200c302624202c3000004",
INIT_1D => X"000400004000426200c302624202c30000040000c4c20007624000c3c20000c2",
INIT_1E => X"05000000440200404200c2c2424200c2c202006200c2436200c302624202c300",
INIT_1F => X"bfbd00e0bdbebfc00000004402000043024300420200004402006202c30000c4",
INIT_20 => X"0004000040004262420300c3020000040000c4c26200c2c30000c0c0c202a0be",
INIT_21 => X"00c2c30000c000000400404200c2c24200c2c202006200c24362420300c30200",
INIT_22 => X"6200c24362420300c302000004000040004262420300c3020000040000c4c262",
INIT_23 => X"000043024300420200004402006202c30000440200404200c2c24200c2c20200",
INIT_24 => X"c2030200c24382c4c2030200c20000c0c0a0bebfbd00e0bdbebfc00000004402",
INIT_25 => X"00c2004262c3c20000c000404200c2c24200c24300c362c30200c24382c40200",
INIT_26 => X"6200c24362420300c30200000400004005004262420300c3020000040000c405",
INIT_27 => X"0400004005004262420300c3020000040000c40500c2004262c30200c2c20200",
INIT_28 => X"020000040000c40500c2004262c30200c2c202006200c24362420300c3020000",
INIT_29 => X"c2c24200c2c202006200c24362420300c30200000400004005004262420300c3",
INIT_2A => X"bebfc00000004402000043024300420200004402006202c30000440200404200",
INIT_2B => X"0000040000400042020000040000c4c26200c2c3c0c202c202a0bebfbd00e0bd",
INIT_2C => X"434202000004000040004242020000040000c4c26200c2c3c202006200c24302",
INIT_2D => X"00c2434202000004000040004242020000040000c4c26200c2c3c202006200c2",
INIT_2E => X"02006200c2434202000004000040004242020000040000c4c20200c2c2020062",
INIT_2F => X"00c2c202006200c2434202000004000040004242020000040000c4c24200c2c2",
INIT_30 => X"006202c300004402c202006200c2434202000040004242020000040000c4c242",
INIT_31 => X"42004202c4a0bebd0000e0bdbebfc00000004402000043024300420200004402",
INIT_32 => X"c202c4a0bebd00e0bdbec0020000004302430042024300c36242030243020040",
INIT_33 => X"40620243020000020062024302004000c24303c2c000000043030040004200c2",
INIT_34 => X"bebd00e0bdbec0024000c2c00000400243030240024300630302004000420200",
INIT_35 => X"0000020062024302004000c24303c2c000000043030040004200c2c202c0c4a0",
INIT_36 => X"02438242040243024402004042004202004000c2004000c2c2004202c2004202",
INIT_37 => X"c200c2c5c4a0bebd00e0bdbec0024000c2c00000430302400240024302430042",
INIT_38 => X"00c0c7c6c5c4a0bebfbd00e0bdbec0c200400042430063c46400c3c34300c200",
INIT_39 => X"c2c3c2020000c202006202c3004100c2c000404200c2c24200c2430362c3c200",
INIT_3A => X"00c200404200c2c2000007624000c3c2c20007624000c3c20000c202c2006200",
INIT_3B => X"4062004200c26200c203004000c26283c4c3020242424200c200000202424242",
INIT_3C => X"c20040004200c2430362c3c2c24200c2006202c3000000004100c2c24200c200",
INIT_3D => X"c362034200c200004300c26200c2030000c4406200c2c30040628200c2044300",
INIT_3E => X"c4a0bebd00e0bdbec0004363034202c5c4a0bebd00e0bdbebfc0000000c44062",
INIT_3F => X"00c2c5c4a0bebd00e0bdbec0c2004000c2c26200c34200c2c2424200c20000c0"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000000000000000ff00000800ff1800350035003300b200",
INIT_01 => X"000000000000000000000000000000000000072000002000d800d800ff700000",
INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000",
INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000200000f000ff00000000e800000000800010100000000000000000f000ff",
INIT_05 => X"0000000000000000000000000000f00000ff00000000e8000000002000ff0000",
INIT_06 => X"0000000000000000f00000ff0000000000e80000ff0000000000002000000000",
INIT_07 => X"e80000ff000000ff000000002000000000000000200000000000000000000010",
INIT_08 => X"0020000000000000000000000007002800380000000000f00000ff0000000000",
INIT_09 => X"20f000ff0000000000e80000ff0000000000000000ff000000000000ff000000",
INIT_0A => X"0000000000000000e8161600002000ff000100f00000ff00000000e800000000",
INIT_0B => X"2a00000256922700000002561227000000002a0000002a0000002a00f00000ff",
INIT_0C => X"032800280028000028000000000200280028002800002800000000002a000000",
INIT_0D => X"0002230029002900290000290000000002430028002900290000290000000002",
INIT_0E => X"2a00000400002a0000002a00000500002a0000002a00000300002a0000002a00",
INIT_0F => X"0000002b00000000002b00000000330000002b0000002b00000200002a000000",
INIT_10 => X"0000000000000000f00000ff0000000000e8000000000001200030330000002b",
INIT_11 => X"010000300000000000ff10000000000000000000000000100000000000000000",
INIT_12 => X"0000000000000000000010241800000000012000300010241800000000000000",
INIT_13 => X"002b00000033000000330000002b000000000000ff0300000000000000000000",
INIT_14 => X"0000000000000000001000000000000000000000f00000ff0000000000e80000",
INIT_15 => X"000000ff00000000000000000000100000100000000000000020000010000010",
INIT_16 => X"00002b00000033000000330000002b0000000000000100003000002b0000ff00",
INIT_17 => X"000000000000000010000000000000000000000000f00000ff0000000000e800",
INIT_18 => X"0000ff0000000000000000000010000010000000000000002000001000001000",
INIT_19 => X"0000100000100000000000000000001000000001000000000000000000ff0000",
INIT_1A => X"00000000ff00000000ff00000000000000000000100000100000000000000020",
INIT_1B => X"00002000001000001010ff3f0000000000000000101000000000000000000000",
INIT_1C => X"0000000000ff00000000ff000000000000000000001000001010ff3f00000000",
INIT_1D => X"000000002000001000001010ff3f000000000000000010000000000000000000",
INIT_1E => X"003000002b0000ff00000000ff000000000000000000001000001010ff3f0000",
INIT_1F => X"00ff0000000000e80000002b00000033000000330000002b0000000000000100",
INIT_20 => X"000000002000001029180000000000000000000010000000000000000012f000",
INIT_21 => X"00000000000000000000ff000000000000000000000000000010291800000000",
INIT_22 => X"00000000102a180000000000000000200000102a180000000000000000000010",
INIT_23 => X"000033000000330000002b000000000000002c0000ff00000000000000000000",
INIT_24 => X"001c1c0000001000001e1e000000000000f00000ff0000000000e80000002b00",
INIT_25 => X"3000000010000000000000ff0000000000000000000010001000000010001000",
INIT_26 => X"00000000102c18000000000000000120003000102c1800000000000000010000",
INIT_27 => X"00000120003000102c1800000000000000010000300000001000100000000000",
INIT_28 => X"000000000001000030000000100010000000000000000000102c180000000000",
INIT_29 => X"000000000000000000000000102c18000000000000000120003000102c180000",
INIT_2A => X"0000e80000002b00000033000000330000002b000000000000002c0000ff0000",
INIT_2B => X"000000000020002c0000000000000000100000000000430012f00000ff000000",
INIT_2C => X"002c0000000000002000002c0000000000000000100000000000000000002c00",
INIT_2D => X"0000002c0000000000002000002c000000000000000010000000000000000000",
INIT_2E => X"0000000000002c0000000000002000002c000000000000000010000000000000",
INIT_2F => X"0000000000000000002c0000000000002000002c000000000000000000000000",
INIT_30 => X"0000000000002c00000000000000002c0000002000002c0000000000000000ff",
INIT_31 => X"0000330000f000ff000000000000e80000002b00000033000000330000002b00",
INIT_32 => X"000000f000ff00000000e8ff0000103300000033000000001035180033000000",
INIT_33 => X"0010400080000000000000320000000000000000000000000000000000000000",
INIT_34 => X"00ff00000000e8000000000000ff33003300003200000035007f000000330000",
INIT_35 => X"00000000000033000000000000000000000000000000000000000000000000f0",
INIT_36 => X"000010352000007f330000000000330000000000000000000000008000000080",
INIT_37 => X"0000000000f000ff00000000e8000000000000ff330000330032003300000033",
INIT_38 => X"000000000000f00000ff00000000e80000ff0000000000000000000000000000",
INIT_39 => X"000000ff0000000000000000000000000000ff00000000000000000010000000",
INIT_3A => X"0000000000000000101000000000000000100000000000000000000000100000",
INIT_3B => X"0010000000001800000000000000001800001616000000000000001616000000",
INIT_3C => X"00000000000000000010000000ff00000000ff0000000000ff000000ff000000",
INIT_3D => X"0010000000000000000000180000000006002810000000000010100000000000",
INIT_3E => X"00f000ff00000000e80000fc0000200000f000ff0000000000e8000006002810",
INIT_3F => X"00000000f000ff00000000e80000ff000000100000ff00000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"4c4844403c3834302c2824201c181410980e00ac04fd2a001800b0000000f001",
INIT_01 => X"504c4844403c3834302c2824201c18141000cc2410200060125c1058fc005450",
INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854",
INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410",
INIT_04 => X"00200000082504f80008100c2500000000100012100d1b020014101410250cf0",
INIT_05 => X"001800980d00040a000018001318251014e80008080425000000080000fa0200",
INIT_06 => X"001020001e101c2025181ce00008181014250000e90000001800982500001801",
INIT_07 => X"250000e0001010fc0010009825570014000700982530001400090a0014140f06",
INIT_08 => X"9825000010010010001810140016a025a42514a8a8a4a025989c60000820181c",
INIT_09 => X"002504f80008a0989c250000e400000010000d1010ff001000080a00ff001000",
INIT_0A => X"000000000818101425030000000000fd003c00251014e8000808042501000020",
INIT_0B => X"8000008878348c0002008878340c000100ae680000ae540000ae3c0025181ce0",
INIT_0C => X"2184009c00b40010d800140200e7070c0024003c00106000140100ae680000ae",
INIT_0D => X"00e7450174008c00a40010c800140400e72105fc0014002c00105000140300e7",
INIT_0E => X"f800008b00ae680000aee000006300ae680000aec80000fe00ae680000aea800",
INIT_0F => X"0000ae5000001300ae4800000700100000ae380000ae2800001400ae680000ae",
INIT_10 => X"1403004b10031c18252024d8000820181c250000980a0005250a25100000ae5c",
INIT_11 => X"05100a250026001400eb2a00101414020014000b140004100d1a020014100011",
INIT_12 => X"0100181c0100030010002170800018000005250a250021708000180000983a00",
INIT_13 => X"ae9c00000510000100100000ae7400000d011c00b2e800101002001000982018",
INIT_14 => X"001000983a00d4181807002810002c1014302c28252024d80008282024250000",
INIT_15 => X"001010ff0100101401000300180021002c80001000982000d425000021002c80",
INIT_16 => X"00aee400000510000100100000aed800000d01140005300a2500aec40000d120",
INIT_17 => X"1000983a00d418181218002810002d101434302c28252024d800082820242500",
INIT_18 => X"1010ff0100101401000300180021002c80001000982000d425000021002c8000",
INIT_19 => X"000021003080001000983a00d4181812180028230010002f1000980a00d00600",
INIT_1A => X"00980a00ce06001010ff0100101401000300180021003080001000982000d425",
INIT_1B => X"00d42500002100348021ffff1000983a00d4181812100d1a0200281000341001",
INIT_1C => X"0100980a00c90a001010ff010010140100030018002100348021ffff10009820",
INIT_1D => X"982000d42500002100388021ffff1000983a00d41818100d1a02002810003310",
INIT_1E => X"0a2500aef00000ca0a001010ff010010140100030018002100388021ffff1000",
INIT_1F => X"24d80008282024250000aee400000510000100100000aed800000d011400053c",
INIT_20 => X"982000d425000021ec8000100000983a00d41c1c21001018002b101418342520",
INIT_21 => X"001018002b1000980a00d20a00101001001014010003001c0021ec8000100000",
INIT_22 => X"03001c0021148000100000982000d425000021148000100000983a00d41c1c23",
INIT_23 => X"000510000100100000aed800000d011400ae140000d20a001010010010140100",
INIT_24 => X"10030000100c21101003000010001f1014259094680008282024250000aee400",
INIT_25 => X"2518000c21101000871000de0a0010100100103c001021108000101c21104000",
INIT_26 => X"030018002158800010000098200005250a250021588000100000983a0005180a",
INIT_27 => X"200005250a250021588000100000983a0005180a2518001c2110400010140100",
INIT_28 => X"0000983a0005180a2518003c2110800010140100030018002158800010000098",
INIT_29 => X"10100100101401000300180021588000100000980a0005250a25002158800010",
INIT_2A => X"9094250000aee400000510000100100000aed800000d011400ae300000760a00",
INIT_2B => X"00982000d42500800000983a00d41c1c240018141018211434252024d8000898",
INIT_2C => X"04800000982000d4250004800000983a00d41c1c2500181410010003001c8000",
INIT_2D => X"001c08800000982000d4250008800000983a00d41c1c2600181410010003001c",
INIT_2E => X"010003001c0c800000982000d425000c800000983a00d41c1c27001410010003",
INIT_2F => X"001410010003001c10800000982000d4250010800000983a00d41c1c12001410",
INIT_30 => X"000d011000ae400010010003001c14800000d4250014800000983a00d41c1cee",
INIT_31 => X"0f002400082504f8000008282024250000aee400000510000100100000aed800",
INIT_32 => X"000110250cf00008080425ff0002252400010024000000082130800024000013",
INIT_33 => X"0b24000000001f01000401f0000006000000321000002a000732000600000010",
INIT_34 => X"14e80008100c25030000100000d82c00280100f00000003000fc000600240000",
INIT_35 => X"003401000401280000060000005d1800003f00075d0006000000180001041825",
INIT_36 => X"00002170800000fc200000100f00200000160008001a00040800000004000004",
INIT_37 => X"0000101410250cf00008181425030000180000c32c01002800f0002000010020",
INIT_38 => X"0a104c48444025383cc00008100c250000f20000000000140100141001001000",
INIT_39 => X"184018ff0003180100050a48000500402f00f30f001010010010102021101000",
INIT_3A => X"0010000a0a00101c12100d1b02001c4810100d1b02001c48003e140e1c121800",
INIT_3B => X"0b2a0000004c2300140f000c001c102110140300ff57ff001000080300ff30ff",
INIT_3C => X"4c000b0000004c102d21101414ff0014000aff1800000200c0001414ff001400",
INIT_3D => X"20230f00004c000c00004c2300140f00f844252100142000122a2300140f0000",
INIT_3E => X"10250cf000080804250000180360000c082504f8000840383c250000f8442521",
INIT_3F => X"00080c082504f80008100c250000f1001010240010ff001000ff010000000d00"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"00008f8faf000c8faf0000008f00008fafaf03afaf270003278f030000008f00",
INIT_01 => X"8f0000003c8fac008fac008fac008f30008fafafafafaf03af270003278f8f03",
INIT_02 => X"0010248f001428008faf24008faf00008f0030003000008f8c008f0010afac00",
INIT_03 => X"10240014008f8f001024001000008f8c008f001024001000008f8c008f001024",
INIT_04 => X"03af270003278f0300008faf03af270003278f0300001024001028008c008f00",
INIT_05 => X"3c000c243c000c343c343caf24afaf03afafaf27000003278f030000343c8faf",
INIT_06 => X"0004008c340010ac24ac343c24ae000c242424000c243cac008f343caf008c34",
INIT_07 => X"8fae000c242424000c24000c0024008f000c243c0014248faf000c8faf008c24",
INIT_08 => X"000000000003278f8f8f0300000c00142c008fac008f24af000c8f0010af2400",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000102040912000000",
INIT_0F => X"fffffffffffffffffffffffffffffffffffffffffffffefcf9f2e4c992000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000606060606050000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000010101010101000000",
INIT_14 => X"3d3d3d3d3d3d676620740a0a747320650a000000000000000000000000000000",
INIT_15 => X"694c7363726d69546e616f6269546f6175206467730a00696920746c6c67730a",
INIT_16 => X"4e490a007420696c54004546455000454d500a6469540030617261736d657061",
INIT_17 => X"544c4c0a0a53200a4c2000454e490a0044414f4c41454e490a0044414f4c4145",
INIT_18 => X"0000000000000000000054204945540a54204d0a542043422f440a2054494920",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000102040912000000000000000000000000000000",
INIT_1F => X"fffffffffffffffffffffefcf9f2e4c992000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000606060606050000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000010101010101000000000000000000000000000000",
INIT_24 => X"7566542055000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000072756570695300736e61756369670a0a727475526e2068616e",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"6200c2c3c20000c4c2430300c30200c2c5c4a0bebfbd00e0bdbec0620200c202",
INIT_01 => X"c240026202c34000c24000c24300c24300c2c0c7c6c5c4a0bebd00e0bdbebfc0",
INIT_02 => X"006202c300404200c2c24200c2c24300c2404202424300c24300c20000c04300",
INIT_03 => X"0002006200c2c300000200404300c24300c200000200404300c24300c2000002",
INIT_04 => X"a0bebd00e0bdbec00200c2c4a0bebd00e0bdbec000000002004042004200c200",
INIT_05 => X"0200004402000044024502c202c5c4a0b0bebfbd0000e0bdbec002624202c3c4",
INIT_06 => X"00400042020000400243630302020000040510000044024300c34202c2004242",
INIT_07 => X"c20200000405100000040000400500c200004402006202c3c20000c4c2004202",
INIT_08 => X"0000000000e0bdb0bebfc000000000404200c24300c302c20000c40000c24200",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"00000000000000000000000000000000010204091224489123468d1a34000000",
INIT_0F => X"fffffffffffffffffffffffffffffefcf9f2e4c99224489123468d1a34000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000003030303030300000000000000",
INIT_12 => X"02010000000000000000000000000000010101020515100b0500fb1a150f0a05",
INIT_13 => X"0000000000000000000000000000000000000000000001504f4e4d4c4b050403",
INIT_14 => X"0a3d3d3d3d3d0a747369540a656d707247000000000000000000000000000000",
INIT_15 => X"6e69736379656e65737470696e656e63622f6920740a006f762f69697420740a",
INIT_16 => X"554d0a0073746c206f00444144410053414c0a6f6e6500306e206c206220726c",
INIT_17 => X"4949540a0a45500a4546005347460a0021534e414c52554d0a0021494e414c52",
INIT_18 => X"0000000000000000000020544f52200a20544f0a2054545420450a00454f562f",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"00000000010204091224489123468d1a34000000000000000000000000000000",
INIT_1F => X"fffffefcf9f2e4c99224489123468d1a34000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000003030303030300000000000000000000000000000000000000",
INIT_22 => X"00000000010101020515100b0500fb1a150f0a05000000000000000000000000",
INIT_23 => X"0000000000000000000001504f4e4d4c4b050403020100000000000000000000",
INIT_24 => X"20203a5441000000000000000000000000000000000000000000000000000000",
INIT_25 => X"00000000000000206d74616e65007420746e6f6e690a006b2074542074696420",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"100000000000070000101f00001000000000f00000ff00000000e8101400001f",
INIT_01 => X"001814100f000000000000000000000000000000000000f000ff0000000000e8",
INIT_02 => X"0000000000ff0000000000000000100000180010001000000000000000000000",
INIT_03 => X"0000000000000000000000001000000000000000000000100000000000000000",
INIT_04 => X"f000ff00000000e817000000f000ff00000000e8100000000000000000000000",
INIT_05 => X"200000320000007801c20000000000f0000000ff0000000000e81010ff1f0000",
INIT_06 => X"00000000800000007f00ff0f7f00000700007f00003200000000002000000000",
INIT_07 => X"0000000700007f0000000001200030000000320000000000000008000000007f",
INIT_08 => X"00000000000000000000e810000100ff0300000000007f000008000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0101010101010101010101010101010000000000000000000000000000000000",
INIT_0B => X"0202020201010101010101010101010101010101010101010101010101010101",
INIT_0C => X"0202020202020202020202020202020202020202020202020202020202020202",
INIT_0D => X"0303030303030303030303030303030303030303030303030303030303030202",
INIT_0E => X"0000000000000000010204091224489123468d1a3468d1a2458a152b56030303",
INIT_0F => X"fffffffffffffefcf9f2e4c99224489123468d1a3468d1a2458a152b56000000",
INIT_10 => X"0000000000000000000000000000000000080808080707000000000000ffffff",
INIT_11 => X"000000000000000000000000000000000101039e9b9794918e0f0c0906030000",
INIT_12 => X"46230000000000000000000095a8c0e00d50c1a1439e5b17d4914e4f0cc98643",
INIT_13 => X"1212121212000000000000000000202429303a48619123c7a4815d3a17b08d69",
INIT_14 => X"003d3d3d3d3d0069686e650073616c6165121212121212121212121212121212",
INIT_15 => X"67730a65206d67730a69657467730a7474206e616954006e69206f63696d6954",
INIT_16 => X"4d4550003a65656674002149215300542041006e6773003020746c73656e696c",
INIT_17 => X"4f43494d0044410044410054205453000a53205443204d4550000a4c20544320",
INIT_18 => X"0000000000000000000000454e414f420045524d00454f5253524100534e4920",
INIT_19 => X"00000000000000000000000000000000000000000000000000001212ed515302",
INIT_1A => X"0101010000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0101010101010101010101010101010101010101010101010101010101010101",
INIT_1C => X"0202020202020202020202020202020202020202020202020101010101010101",
INIT_1D => X"0303030303030303030303030303030303030202020202020202020202020202",
INIT_1E => X"1224489123468d1a3468d1a2458a152b56030303030303030303030303030303",
INIT_1F => X"9224489123468d1a3468d1a2458a152b56000000000000000000000001020409",
INIT_20 => X"0000000000080808080707000000000000fffffffffffffffffffefcf9f2e4c9",
INIT_21 => X"000000000101039e9b9794918e0f0c0906030000000000000000000000000000",
INIT_22 => X"95a8c0e00d50c1a1439e5b17d4914e4f0cc98643000000000000000000000000",
INIT_23 => X"0000202429303a48619123c7a4815d3a17b08d69462300000000000000000000",
INIT_24 => X"6379204552121212121212121212121212121212121212121200000000000000",
INIT_25 => X"0000000000000000622063676e000a7469696d676e4200737770205568732072",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"250014101400dc101025400020400024242025181ce000080804252500000c00",
INIT_01 => X"20250224ff1000001c000018000014ff0010041c181410250cf0000820181c25",
INIT_02 => X"0004010400ea080000000100000421000425ff2b010700000000140013000000",
INIT_03 => X"0c04000400181c00140300042a002400001c001f0200042a0024000018002a01",
INIT_04 => X"2504f80008080425420008082504f80008100c25250002050004020000002000",
INIT_05 => X"0000ae6c000080407d000110013c38252c3034c80000080804254224feff0808",
INIT_06 => X"002e000000003300fc00fffffc0000f90103fc00aea800000014300014000050",
INIT_07 => X"100000f90103fc00980a0005250a251000aecc00001a011c1c009118180000fc",
INIT_08 => X"0b0705030008382c30342525006000cae90010000020fc20009d180009100100",
INIT_09 => X"9d97958b89837f716d6b67656159534f4947433d3b352f2b29251f1d1713110d",
INIT_0A => X"5b514b3d393733251b19150f0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a3",
INIT_0B => X"231d0b09fdf7f3ebe7dfd3cfcdc9c1bbb7b1afa5a399918d857f7b756f67615d",
INIT_0C => X"efe7e3ddd7cfc5bdb3aba5a195938d878381776b69655f5957514b413b39332d",
INIT_0D => X"d1cbc7b9b3ada9a1978f8b7773716d5f5b5955473d3b37352b291d130501f9f5",
INIT_0E => X"010204091224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78e5dfd7",
INIT_0F => X"f9f2e4c99224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78000000",
INIT_10 => X"070001020301010000000101010102030718110a03fcf5231c150e0700fffefc",
INIT_11 => X"0000010303010100010059647285a0c80b90212807e6c5a483a5846342210007",
INIT_12 => X"8a4500030103030001000100ae6472856dc80b90212807e6c5a483a584634221",
INIT_13 => X"38373635340005010300010001005d689c8b41d117a245c8833ef9b46f5914cf",
INIT_14 => X"003d3d3d3d3d006e696773007420616c6e2b2c2d2e2f30313233343d3c3b3a39",
INIT_15 => X"20740073616f2074006f722020740069727367646e65000a73646e6170756e65",
INIT_16 => X"422052002073646161000a4c00530020545300652074000a3168656d72756d20",
INIT_17 => X"4e4150550021530021490020544948000a4550495543422052000a4546495543",
INIT_18 => X"0908070605040302010000535354504900535945005352415520440054205344",
INIT_19 => X"6159534f4947433d3b352f2b29251f1d1713110d0b07050300002246cb153520",
INIT_1A => X"0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a39d97958b89837f716d6b6765",
INIT_1B => X"cdc9c1bbb7b1afa5a399918d857f7b756f67615d5b514b3d393733251b19150f",
INIT_1C => X"95938d878381776b69655f5957514b413b39332d231d0b09fdf7f3ebe7dfd3cf",
INIT_1D => X"73716d5f5b5955473d3b37352b291d130501f9f5efe7e3ddd7cfc5bdb3aba5a1",
INIT_1E => X"3468d1a2458a152b56ac59b367cf9e3c78e5dfd7d1cbc7b9b3ada9a1978f8b77",
INIT_1F => X"3468d1a2458a152b56ac59b367cf9e3c78000000010204091224489123468d1a",
INIT_20 => X"010102030718110a03fcf5231c150e0700fffefcf9f2e4c99224489123468d1a",
INIT_21 => X"7285a0c80b90212807e6c5a483a5846342210007070001020301010000000101",
INIT_22 => X"ae6472856dc80b90212807e6c5a483a584634221000001030301010001005964",
INIT_23 => X"01005d689c8b41d117a245c8833ef9b46f5914cf8a4500030103030001000100",
INIT_24 => X"616f4953542b2c2d2e2f30313233343d3c3b3a39383736353400050103000100",
INIT_25 => X"0000000100000000656e6b2064000a656f636d206e6500216f756f41652c7465",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
| gpl-3.0 | e27d71ba36b36621e7e13a80cbc40da9 | 0.843319 | 5.6374 | false | false | false | false |
simoesusp/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE115/RAM.vhd | 1 | 6,890 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY RAM IS
PORT
(
address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END RAM;
ARCHITECTURE SYN OF ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "cpuram.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 32768,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
widthad_a => 15,
width_a => 16,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "cpuram.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
-- Retrieval info: PRIVATE: WidthData NUMERIC "16"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "cpuram.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | d099fb7e40b801daf4912786069754fd | 0.670972 | 3.5261 | false | false | false | false |
Wynjones1/gbvhdl | src/common.vhd | 1 | 4,491 | library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
use work.types.all;
package common is
-- impure function init_mem(input_file : in string) return
function r_table(input : std_logic_vector(2 downto 0)) return register_t;
function d_table(input : std_logic_vector(1 downto 0)) return register_t;
function s_table(input : std_logic_vector(1 downto 0)) return register_t;
function q_table(input : std_logic_vector(1 downto 0)) return register_t;
function f_table(input : std_logic_vector(2 downto 0)) return alu_op_t;
function l_table(input : std_logic_vector(2 downto 0)) return alu_op_t;
function need_to_jump(cc : std_logic_vector(1 downto 0); flags : std_logic_vector(7 downto 4)) return boolean;
function read_slv(file fp : text) return std_logic_vector;
end;
-- TODO: Maybe add report for invalid values.
package body common is
function r_table(input : std_logic_vector(2 downto 0)) return register_t is
begin
case input is
when "111" => return register_a;
when "000" => return register_b;
when "001" => return register_c;
when "010" => return register_d;
when "011" => return register_e;
when "100" => return register_h;
when "101" => return register_l;
when others => return register_l; -- TODO: Fix
end case;
end function;
function d_table(input : std_logic_vector(1 downto 0)) return register_t is
begin
case input is
when "00" => return register_bc;
when "01" => return register_de;
when "10" => return register_hl;
when "11" => return register_sp;
when others => return register_sp; -- TODO: Fix
end case;
end function;
function s_table(input : std_logic_vector(1 downto 0)) return register_t is
begin
return d_table(input);
end function;
function q_table(input : std_logic_vector(1 downto 0)) return register_t is
begin
case input is
when "00" => return register_bc;
when "01" => return register_de;
when "10" => return register_hl;
when "11" => return register_af;
when others => return register_af; -- TODO: Fix
end case;
end function;
function f_table(input : std_logic_vector(2 downto 0)) return alu_op_t is
begin
case input is
when "000" => return alu_op_add;
when "001" => return alu_op_adc;
when "010" => return alu_op_sub;
when "011" => return alu_op_sbc;
when "100" => return alu_op_and;
when "101" => return alu_op_xor;
when "110" => return alu_op_or;
when "111" => return alu_op_cp;
when others => return alu_op_invalid;
end case;
end function;
function l_table(input : std_logic_vector(2 downto 0)) return alu_op_t is
begin
case input is
when "000" => return alu_op_rlc;
when "001" => return alu_op_rrc;
when "010" => return alu_op_rl;
when "011" => return alu_op_rr;
when "100" => return alu_op_sla;
when "101" => return alu_op_sra;
when "110" => return alu_op_swap;
when "111" => return alu_op_srl;
when others => return alu_op_invalid;
end case;
end function;
function need_to_jump(
cc : std_logic_vector(1 downto 0);
flags : std_logic_vector(7 downto 4))
return boolean is
begin
return ((cc = "00") and (flags(ZERO_BIT) = '0')) or -- NZ
((cc = "01") and (flags(ZERO_BIT) = '1')) or -- Z
((cc = "10") and (flags(CARRY_BIT) = '0')) or -- NC
((cc = "11") and (flags(CARRY_BIT) = '1')); -- C
end function;
function read_slv(file fp : text) return std_logic_vector is
variable bv : bit_vector(15 downto 0);
variable slv : std_logic_vector(15 downto 0);
variable li : line;
begin
if endfile(fp) then
return "UUUUUUUUUUUUUUUU";
end if;
readline(fp, li);
read(li, bv);
for i in 0 to 15 loop
if bv(i) = '1' then
slv(i) := '1';
else
slv(i) := '0';
end if;
end loop;
return slv;
end function;
end common;
| mit | e49a7ceb4fefe96ed03c9565bd3f208b | 0.549321 | 3.610129 | false | false | false | false |
AndyMcC0/UVVM_All | bitvis_vip_i2c/src/i2c_vvc.vhd | 1 | 22,592 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.i2c_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_vvc_framework_common_methods_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--=================================================================================================
entity i2c_vvc is
generic (
GC_INSTANCE_IDX : natural := 1; -- Instance index for this I2C_VVCT instance
GC_MASTER_MODE : boolean := true;
GC_I2C_CONFIG : t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT; -- Behavior specification for BFM
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning
);
port (
i2c_vvc_if : inout t_i2c_if := init_i2c_if_signals(VOID)
);
end entity i2c_vvc;
--=================================================================================================
--=================================================================================================
architecture behave of i2c_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated Queue
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_i2c_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_i2c_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_i2c_transaction_info(GC_INSTANCE_IDX);
begin
--===============================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--===============================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_I2C_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--===============================================================================================
--===============================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--===============================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, shared_vvc_cmd, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command executor
-- - Fetch and execute the commands
--===============================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean;
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
while true loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- Set the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Check if command is a BFM access
if v_cmd.operation = MASTER_TRANSMIT or
v_cmd.operation = MASTER_CHECK or
v_cmd.operation = MASTER_RECEIVE or
v_cmd.operation = SLAVE_TRANSMIT or
v_cmd.operation = SLAVE_CHECK or
v_cmd.operation = SLAVE_RECEIVE then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_command_is_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when MASTER_TRANSMIT =>
transaction_info.data := v_cmd.data;
transaction_info.num_bytes := v_cmd.num_bytes;
if GC_MASTER_MODE then -- master transmit
transaction_info.addr := v_cmd.addr;
transaction_info.continue := v_cmd.continue;
i2c_master_transmit(addr_value => v_cmd.addr,
data => v_cmd.data(0 to v_cmd.num_bytes-1),
msg => format_msg(v_cmd),
i2c_if => i2c_vvc_if,
continue => v_cmd.continue,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
else -- attempted master transmit when in slave mode
alert(error, "Master transmit called when VVC is in slave mode.", C_SCOPE);
end if;
when MASTER_RECEIVE =>
if GC_MASTER_MODE then -- master receive
transaction_info.addr := v_cmd.addr;
transaction_info.continue := v_cmd.continue;
transaction_info.num_bytes := v_cmd.num_bytes;
check_value(v_cmd.num_bytes <= C_VVC_CMD_DATA_MAX_LENGTH, error, "Verifying number of bytes to receive.", C_SCOPE, ID_NEVER);
i2c_master_receive(addr_value => v_cmd.addr,
data => v_read_data(0 to v_cmd.num_bytes-1),
msg => format_msg(v_cmd),
i2c_if => i2c_vvc_if,
continue => v_cmd.continue,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data);
else -- attempted master receive when in slave mode
alert(error, "Master receive called when VVC is in slave mode.", C_SCOPE);
end if;
when MASTER_CHECK =>
transaction_info.data := v_cmd.data;
transaction_info.num_bytes := v_cmd.num_bytes;
if GC_MASTER_MODE then -- master check
transaction_info.addr := v_cmd.addr;
transaction_info.continue := v_cmd.continue;
i2c_master_check(addr_value => v_cmd.addr,
data_exp => v_cmd.data(0 to v_cmd.num_bytes-1),
msg => format_msg(v_cmd),
i2c_if => i2c_vvc_if,
continue => v_cmd.continue,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
else -- attempted master check when in slave mode
alert(error, "Master check called when VVC is in slave mode.", C_SCOPE);
end if;
when MASTER_QUICK_CMD =>
if GC_MASTER_MODE then -- master check
transaction_info.addr := v_cmd.addr;
transaction_info.exp_ack := v_cmd.exp_ack;
transaction_info.continue := v_cmd.continue;
i2c_master_quick_command( addr_value => v_cmd.addr,
msg => format_msg(v_cmd),
i2c_if => i2c_vvc_if,
rw_bit => v_cmd.rw_bit,
exp_ack => v_cmd.exp_ack,
continue => v_cmd.continue,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
else -- attempted master quick command when in slave mode
alert(error, "Master quick command called when VVC is in slave mode.", C_SCOPE);
end if;
when SLAVE_TRANSMIT =>
transaction_info.data := v_cmd.data;
transaction_info.num_bytes := v_cmd.num_bytes;
if not GC_MASTER_MODE then -- slave transmit
i2c_slave_transmit(data => v_cmd.data(0 to v_cmd.num_bytes-1),
msg => format_msg(v_cmd),
i2c_if => i2c_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
else -- attempted slave transmit when in master mode
alert(error, "Slave transmit called when VVC is in master mode.", C_SCOPE);
end if;
when SLAVE_RECEIVE =>
if not GC_MASTER_MODE then -- requires slave mode
transaction_info.num_bytes := v_cmd.num_bytes;
check_value(v_cmd.num_bytes <= C_VVC_CMD_DATA_MAX_LENGTH, error, "Verifying number of bytes to receive.", C_SCOPE, ID_NEVER);
i2c_slave_receive( data => v_read_data(0 to v_cmd.num_bytes-1),
msg => format_msg(v_cmd),
i2c_if => i2c_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data);
else -- wrong mode
alert(error, "Slave receive called when VVC is in master mode.", C_SCOPE);
end if;
when SLAVE_CHECK =>
transaction_info.data := v_cmd.data;
transaction_info.num_bytes := v_cmd.num_bytes;
if not GC_MASTER_MODE then -- slave check
i2c_slave_check(data_exp => v_cmd.data(0 to v_cmd.num_bytes-1),
msg => format_msg(v_cmd),
i2c_if => i2c_vvc_if,
exp_rw_bit => v_cmd.rw_bit,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
else -- attempted slave check when in master mode
alert(error, "Slave check called when VVC is in master mode.", C_SCOPE);
end if;
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.i2c_bit_time;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, vvc_config.msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--===============================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--===============================================================================================
end behave;
| mit | 15d54b550560215d961b97d01da2196c | 0.494556 | 4.410777 | false | true | false | false |
AndyMcC0/UVVM_All | uvvm_vvc_framework/src/ti_data_fifo_pkg.vhd | 1 | 8,415 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_data_queue_pkg.all;
package ti_data_fifo_pkg is
shared variable shared_data_fifo : t_data_queue;
------------------------------------------
-- uvvm_fifo_init
------------------------------------------
-- This function allocates space in the buffer and returns an index that
-- must be used to access the FIFO.
--
-- - Parameters:
-- - buffer_size_in_bits (natural) - The size of the FIFO
--
-- - Returns: The index of the initiated FIFO (natural).
-- Returns 0 on error.
--
impure function uvvm_fifo_init(
buffer_size_in_bits : natural
) return natural;
------------------------------------------
-- uvvm_fifo_init
------------------------------------------
-- This procedure allocates space in the buffer at the given buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be initialized.
-- - buffer_size_in_bits (natural) - The size of the FIFO
--
procedure uvvm_fifo_init(
buffer_idx : natural;
buffer_size_in_bits : natural
);
------------------------------------------
-- uvvm_fifo_put
------------------------------------------
-- This procedure puts data into a FIFO with index buffer_idx.
-- The size of the data is unconstrained, meaning that
-- it can be any size. Pushing data with a size that is
-- larger than the FIFO size results in wrapping, i.e.,
-- that when reaching the end the data remaining will over-
-- write the data that was written first.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be pushed to.
-- - data - The data that shall be pushed (slv)
--
procedure uvvm_fifo_put(
buffer_idx : natural;
data : std_logic_vector
);
------------------------------------------
-- uvvm_fifo_get
------------------------------------------
-- This function returns the data from the FIFO
-- and removes the returned data from the FIFO.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the FIFO (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to get() from an empty FIFO is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to get() a larger value than the FIFO size is allowed
-- but triggers a TB_WARNING.
--
--
impure function uvvm_fifo_get(
buffer_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_fifo_flush
------------------------------------------
-- This procedure empties the FIFO given
-- by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be flushed.
--
procedure uvvm_fifo_flush(
buffer_idx : natural
);
------------------------------------------
-- uvvm_fifo_peek
------------------------------------------
-- This function returns the data from the FIFO
-- without removing it.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the FIFO. The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty FIFO is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the FIFO size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function uvvm_fifo_peek(
buffer_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_fifo_get_count
------------------------------------------
-- This function returns a natural indicating the number of elements
-- currently occupying the FIFO given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
--
-- - Returns: The number of elements occupying the FIFO (natural).
--
--
impure function uvvm_fifo_get_count(
buffer_idx : natural
) return natural;
------------------------------------------
-- uvvm_fifo_get_max_count
------------------------------------------
-- This function returns a natural indicating the maximum number
-- of elements that can occupy the FIFO given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
--
-- - Returns: The maximum number of elements that can be placed
-- in the FIFO (natural).
--
--
impure function uvvm_fifo_get_max_count(
buffer_idx : natural
) return natural;
end package ti_data_fifo_pkg;
package body ti_data_fifo_pkg is
impure function uvvm_fifo_init(
buffer_size_in_bits : natural
) return natural is
begin
return shared_data_fifo.init_queue(buffer_size_in_bits, "UVVM_FIFO");
end function;
procedure uvvm_fifo_init(
buffer_idx : natural;
buffer_size_in_bits : natural
) is
begin
shared_data_fifo.init_queue(buffer_idx, buffer_size_in_bits, "UVVM_FIFO");
end procedure;
procedure uvvm_fifo_put(
buffer_idx : natural;
data : std_logic_vector
) is
begin
shared_data_fifo.push_back(buffer_idx, data);
end procedure;
impure function uvvm_fifo_get(
buffer_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_fifo.pop_front(buffer_idx, entry_size_in_bits);
end function;
procedure uvvm_fifo_flush(
buffer_idx : natural
) is
begin
shared_data_fifo.flush(buffer_idx);
end procedure;
impure function uvvm_fifo_peek(
buffer_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_fifo.peek_front(buffer_idx, entry_size_in_bits);
end function;
impure function uvvm_fifo_get_count(
buffer_idx : natural
) return natural is
begin
return shared_data_fifo.get_count(buffer_idx);
end function;
impure function uvvm_fifo_get_max_count(
buffer_idx : natural
) return natural is
begin
return shared_data_fifo.get_queue_count_max(buffer_idx);
end function;
end package body ti_data_fifo_pkg;
| mit | 6372a706c926a261cff6f460c763776e | 0.532383 | 4.466561 | false | false | false | false |
elainemielas/CVUT_BI-PNO | project2/keyboard_old.vhd | 1 | 3,251 | library ieee;
use ieee.std_logic_1164.all;
entity keyboard is
port (
PS2_DATA : in std_logic; -- serial PS2 input
PS2_CLK : in std_logic; -- serial PS2 clock
KEY_F : out std_logic; -- high for one clock when key 'f' pressed
KEY_U : out std_logic; -- high for one clock when key 'u' pressed
KEY_L : out std_logic; -- high for one clock when key 'l' pressed
KEY_PRESS : out std_logic; -- high for one clock when any key pressed
CLK : in std_logic; -- standard 50MHz clock
RESET : in std_logic
);
end keyboard;
architecture keyboard_body of keyboard is
component RECEIVER
port (
PS2_DATA : in std_logic; -- serial PS2 input
PS2_CLK : in std_logic; -- serial PS2 clock
CLK : in std_logic; -- standard 50MHz clock
RESET : in std_logic;
SCAN_CODE : out std_logic_vector ( 7 downto 0 );
NEW_SC : out std_logic
);
end component;
signal NEW_SC, NEW_SC_D : std_logic;
signal PS2_DATA1, PS2_DATA2, PS2_CLK1, PS2_CLK2 : std_logic;
signal SC : std_logic_vector ( 7 downto 0 );
signal IGNORE_NEXT : std_logic := '0';
begin
-- DECODE : process ( CLK )
-- begin
-- if CLK = '1' and CLK'event then
-- if RESET = '1' or NEW_SC = '0' then
-- --KEY_F <= '0';
-- --KEY_U <= '0';
-- --KEY_L <= '0';
-- --KEY_PRESS <= '0';
-- else
-- --KEY_F <= '0';
-- --KEY_U <= '0';
-- --KEY_L <= '0';
-- --KEY_PRESS <= '0';
--
-- IGNORE_NEXT <= '0';
--
-- if IGNORE_NEXT = '0' then
-- --IGNORE_NEXT <= '1';
-- case SC is
---- when "00101011" => KEY_F <= '1';
---- KEY_PRESS <= '1';
---- when "00101100" => KEY_U <= '1';
---- KEY_PRESS <= '1';
---- when "01001011" => KEY_L <= '1';
---- KEY_PRESS <= '1';
-- when "11110000" | "11100000" => IGNORE_NEXT <= '1';
---- when others => KEY_PRESS <= '1';
-- end case;
-- else
-- IGNORE_NEXT <= '1';
-- end if;
-- end if;
-- end if;
-- end process;
DECODE : process ( CLK )
begin
if CLK = '1' and CLK'event then
if RESET = '1' then
IGNORE_NEXT <= '0';
elsif NEW_SC = '1' then
if SC = "11110000" or SC = "11100000" then
IGNORE_NEXT <= '1';
else
IGNORE_NEXT <= '0';
end if;
end if;
end if;
end process;
PS2_PR : process ( CLK )
begin
if CLK = '1' and CLK'event then
PS2_DATA1 <= PS2_DATA;
PS2_DATA2 <= PS2_DATA1;
PS2_CLK1 <= PS2_CLK;
PS2_CLK2 <= PS2_CLK1;
end if;
end process;
RECEIVER_COMPONENT : RECEIVER port map ( PS2_DATA2, PS2_CLK2, CLK, RESET, SC, NEW_SC );
NEW_SC_D <= NEW_SC when rising_edge(clk);
SC_OUT_PR : process ( CLK )
begin
if CLK = '1' and CLK'event then
if NEW_SC_D = '1' and IGNORE_NEXT = '0' then
KEY_F <= '0';
KEY_U <= '0';
KEY_L <= '0';
KEY_PRESS <= '1';
case SC is
when "00101011" => KEY_F <= '1';
when "00111100" => KEY_U <= '1';
when "01001011" => KEY_L <= '1';
when others => null;
end case;
else
KEY_F <= '0';
KEY_U <= '0';
KEY_L <= '0';
KEY_PRESS <= '0';
end if;
end if;
end process;
end keyboard_BODY;
| mit | e14424a9c0d3239a5e065a111c2174ce | 0.506613 | 2.677924 | false | false | false | false |
ashtonchase/logic_analyzer | test/tb_storage.vhd | 1 | 11,153 | -------------------------------------------------------------------------------
-- Title : Logic Analyzer Storage Testbench
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : storage.vhd
-- Created : 2016-02-29
-- Last update: 2016-02-29
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: Testbench for storage.vhd
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-03-07 1.0 Henny Created
-- 2016-03-09 1.0.1 Henny Tested all the major functionality of storage
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity tb_storage is
end entity tb_storage;
architecture behave of tb_storage is
signal clk : std_logic;
signal reset : std_logic;
-- In side of the storage
signal data_in : std_logic_vector(31 downto 0);
signal valid_in : std_logic := '0';
signal last_in : std_logic := '0';
signal ready_in : std_logic := '0';
signal full : std_logic := '0';
signal empty : std_logic := '0';
signal flush : std_logic := '0';
-- Out side of storage
signal data_out : std_logic_vector(7 downto 0);
signal valid_out : std_logic := '0';
signal last_out : std_logic := '0';
signal ready_out : std_logic := '0';
-- Parameters to change to test
signal data : unsigned(31 downto 0) := x"A5A51234";
signal data_at_out : unsigned(31 downto 0) := (others => '0');
signal correct_data_value : unsigned(31 downto 0) := data;
begin
clk_proc : process
begin
clk <= '0';
wait for 5ns;
loop
wait for 5ns;
clk <= '1';
wait for 5ns;
clk <= '0';
end loop;
end process clk_proc;
-- Calling Instance of Storage
storage : entity work.storage
generic map ( FIFO_SIZE=>32 )
port map (
clk => clk,
reset => reset,
in_fifo_tdata => data_in,
in_fifo_tvalid => valid_in,
in_fifo_tlast => last_in,
in_fifo_tready => ready_in,
in_fifo_tfull => full,
in_fifo_tempty => empty,
in_fifo_tflush => flush,
--Output FIFO interface to UART
out_fifo_tdata => data_out,
out_fifo_tvalid => valid_out,
out_fifo_tlast => last_out,
out_fifo_tready => ready_out
);
----------------------------------------------
-- inputs words into the "storage"
----------------------------------------------
input_main_pr : process
-- Puts an incrementing word into storage, delay conctrols how often
procedure store_word(delay : integer := 0) is
begin
valid_in <= '0'; -- will be overwritten if delay=0
data_in <= std_logic_vector(data);
data <= data + x"01010101";
-- will wait that many clock cycles before writing another word
for i in 1 to delay loop
wait until rising_edge(clk);
end loop;
valid_in <= '1';
wait until ready_in='1' and rising_edge(clk);
-- if delay/=0 then
valid_in <= '0';
-- end if;
end procedure;
begin
reset <= '1';
wait for 20ns;
report "De-asserting reset";
reset <= '0';
wait until ready_in='1';
wait until rising_edge(clk);
-- Quick Storage
for idx in 0 to 4 loop
store_word(0);
end loop;
-- Sweeps Slow Storage
for idx in 8 to 23 loop
store_word(idx);
end loop;
wait for 50ns;
------------------------------------
-- Test last
report "(1) Inputting last word";
last_in <= '1';
store_word(3);
wait for 100ns;
last_in <= '0';
------------------------------------
-- Try to Store Data before last word has been outputted
-- It will sit here until output_pr has read everything out
store_word(7);
------------------------------------
-- Feeding word in, to see if it will read out if waiting for data to be outputted
wait for 1us;
store_word(3);
wait for 100ns;
------------------------------------
-- Fill the entire FIFO, testing full signal
report "(2) Testing Full flag";
for idx in 0 to 28 loop -- already has 2 values in it
store_word(0);
end loop;
last_in <= '1';
store_word(0); -- if I change speeds here and put tlast, in breaks ***************
last_in <= '0';
-- Waits 5 clock cycles for full to go high before throwing an error
for i in 0 to 4 loop
wait until rising_edge(clk);
if full='1' then
exit;
end if;
end loop;
assert full='1' report "FIFO should be full" severity error;
------------------------------------
-- Test Flush
report "(3) Flushing the FIFO";
flush <= '1';
wait for 92ns;
assert full='0' report "FIFO should be less than full (actually empty)" severity error;
assert empty='1' report "FIFO should be empty" severity error;
flush <= '0';
------------------------------------
-- Fill the entire FIFO, testing reading out the full FIFO
report "(4) Fill the FIFO with last value";
for idx in 0 to 30 loop
store_word(0);
end loop;
last_in <= '1';
store_word(0); -- if I change speeds here and put tlast, in breaks ***************
last_in <= '0';
-- Waits 5 clock cycles for full to go high before throwing an error
for i in 0 to 4 loop
wait until rising_edge(clk);
if full='1' then
exit;
end if;
end loop;
assert full='1' report "FIFO should be full" severity error;
------------------------------------
-- Fill the entire FIFO with no last, handle having no last value
wait until empty='1';
report "(5) Filling the FIFO with no last value";
for idx in 0 to 31 loop
store_word(1);
end loop;
-- Try and write another word
wait until ready_in='1' and rising_edge(clk);
store_word(1);
------------------------------------
wait for 1us; -- wait for out to finish its pull tests
report "(END) Finished Testbench";
wait;
end process input_main_pr;
----------------------------------------------
-- outputs words into the "storage"
----------------------------------------------
output_main_pr : process
-- Pulls words out of storage
--**************** Cannot handle a delay of 0 maybe 1
procedure pull_word(delay : integer := 0) is
begin
wait until rising_edge(clk);
for idx in 0 to 3 loop
ready_out <= '1';
wait until rising_edge(clk) and valid_out='1';
data_at_out(7+idx*8 downto idx*8) <= unsigned(data_out);
ready_out <= '0';
-- will wait that many clock cycles before writing another word
for i in 1 to delay loop
wait until rising_edge(clk);
end loop;
end loop;
if data_at_out/=correct_data_value then
report "**************Pulled wrong value out " severity error;
end if;
correct_data_value <= correct_data_value + x"01010101";
end procedure;
begin
wait until empty='0';
------------------------------------
-- Pulling at different rates
for idx in 22 downto 2 loop
wait for 50ns;
pull_word(idx);
assert empty='0' report "FIFO should not be empty, pulled tlast" severity error;
end loop;
------------------------------------
-- Testing handling of last word
wait for 300ns;
pull_word(5);
assert empty='1' report "FIFO should be empty, pulled tlast" severity error;
------------------------------------
-- Testing handling of reading only word
wait for 300ns;
pull_word(5);
assert empty='1' report "FIFO should be empty, pulled tlast" severity error;
------------------------------------
-- Testing reading out when there is nothing there
wait for 100ns;
pull_word(5);
------------------------------------
-- Wait until empty, read out the entire FIFO (has last value=31)
wait until empty='1';
correct_data_value <= data; -- reset what data is being stored, since a lot of data was flushed
for i in 0 to 31 loop
pull_word(3);
end loop;
-- Waits 5 clock cycles for full to go high before throwing an error
for i in 0 to 4 loop
wait until rising_edge(clk);
if empty='1' then
exit;
end if;
end loop;
assert empty='1' report "FIFO should be empty" severity error;
------------------------------------
-- Wait until empty, read out the entire FIFO (no last value)
for i in 0 to 31 loop
pull_word(1);
end loop;
-- Try and read another word
wait for 250ns;
pull_word(1);
--*********** tests still needed
-- Fast read out, I didn't design it to work
wait;
end process output_main_pr;
end architecture behave;
| gpl-2.0 | 1794f1c4787c4cb4c7dc5bca69acbb1c | 0.476195 | 4.727851 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.