repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/EPROC_IN4_DEC8b10b.vhd | 2 | 8,288 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
use work.centralRouter_package.all;
--! 8b10b decoder for EPROC_IN4 module
entity EPROC_IN4_DEC8b10b is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (3 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
busyOut : out std_logic
);
end EPROC_IN4_DEC8b10b;
architecture Behavioral of EPROC_IN4_DEC8b10b is
----------------------------------
----------------------------------
component KcharTest is
port (
clk : in std_logic;
encoded10in : in std_logic_vector (9 downto 0);
KcharCode : out std_logic_vector (1 downto 0)
);
end component KcharTest;
----------------------------------
----------------------------------
signal EDATAbitstreamSREG : std_logic_vector (23 downto 0) := (others=>'0'); -- 24 bit (4 x 5 = 20, plus 4 more)
signal word10bx2_align_array, word10bx2_align_array_r : word10b_2array_4array_type;
signal word10b_array, word10b_array_s : word10b_2array_type;
signal isk_array : isk_2array_type;
signal comma_valid_bits_or, word10bx2_align_rdy_r,
word10b_array_rdy, word10b_array_rdy_s, word10b_array_rdy_s1 : std_logic;
signal align_select : std_logic_vector (1 downto 0) := (others=>'0');
signal comma_valid_bits : std_logic_vector (3 downto 0);
signal alignment_sreg : std_logic_vector (4 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- 24 bit input shift register
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
EDATAbitstreamSREG <= (others => '0');
elsif bitCLK'event and bitCLK = '1' then
EDATAbitstreamSREG <= edataIN & EDATAbitstreamSREG(23 downto 4);
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock0
-- input shift register mapping into 10 bit registers
-------------------------------------------------------------------------------------------
input_map: for I in 0 to 3 generate -- 2 10bit-words per alignment, 4 possible alignments
--word10bx2_align_array(I)(0) <= EDATAbitstreamSREG((I+9) downto (I+0)); -- 1st 10 bit word, alligned to bit I
--word10bx2_align_array(I)(1) <= EDATAbitstreamSREG((I+19) downto (I+10)); -- 2nd 10 bit word, alligned to bit I
word10bx2_align_array(I)(0) <= EDATAbitstreamSREG(I+0)&EDATAbitstreamSREG(I+1)&EDATAbitstreamSREG(I+2)&EDATAbitstreamSREG(I+3)&EDATAbitstreamSREG(I+4)&
EDATAbitstreamSREG(I+5)&EDATAbitstreamSREG(I+6)&EDATAbitstreamSREG(I+7)&EDATAbitstreamSREG(I+8)&EDATAbitstreamSREG(I+9); -- 1st 10 bit word, alligned to bit I
word10bx2_align_array(I)(1) <= EDATAbitstreamSREG(I+10)&EDATAbitstreamSREG(I+11)&EDATAbitstreamSREG(I+12)&EDATAbitstreamSREG(I+13)&EDATAbitstreamSREG(I+14)&
EDATAbitstreamSREG(I+15)&EDATAbitstreamSREG(I+16)&EDATAbitstreamSREG(I+17)&EDATAbitstreamSREG(I+18)&EDATAbitstreamSREG(I+19); -- 2nd 10 bit word, alligned to bit I
end generate input_map;
--
-------------------------------------------------------------------------------------------
--clock0
-- K28.5 comma test
-------------------------------------------------------------------------------------------
comma_test: for I in 0 to 3 generate -- 2 10bit-words per alignment, comma is valid if two first words have comma
comma_valid_bits(I) <= '1' when ((word10bx2_align_array(I)(0) = COMMAp or word10bx2_align_array(I)(0) = COMMAn) and
(word10bx2_align_array(I)(1) = COMMAp or word10bx2_align_array(I)(1) = COMMAn)) else '0';
end generate comma_test;
--
comma_valid_bits_or <= comma_valid_bits(3) or comma_valid_bits(2) or comma_valid_bits(1) or comma_valid_bits(0);
--
-------------------------------------------------------------------------------------------
--clock1
-- alignment selector state
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
alignment_sreg <= "00000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
alignment_sreg <= "10000";
else
alignment_sreg <= alignment_sreg(0) & alignment_sreg(4 downto 1);
end if;
end if;
end process;
--
input_reg1: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10bx2_align_array_r <= word10bx2_align_array;
end if;
end process;
--
word10bx2_align_rdy_r <= alignment_sreg(4);
--
process(bitCLK, rst)
begin
if rst = '1' then
align_select <= "00";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
align_select(0) <= (not comma_valid_bits(0)) and (
comma_valid_bits(1) or ( (not comma_valid_bits(1)) and (not comma_valid_bits(2)) and (
comma_valid_bits(3)
)));
align_select(1) <= (not comma_valid_bits(0)) and (not comma_valid_bits(1)) and
(comma_valid_bits(2) or comma_valid_bits(3));
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock2
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg2: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_rdy <= word10bx2_align_rdy_r;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case (align_select) is
when "00" => -- bit0 word got comma => align to bit0
word10b_array <= word10bx2_align_array_r(0);
when "01" => -- bit1 word got comma => align to bit1
word10b_array <= word10bx2_align_array_r(1);
when "10" => -- bit2 word got comma => align to bit2
word10b_array <= word10bx2_align_array_r(2);
when "11" => -- bit3 word got comma => align to bit3
word10b_array <= word10bx2_align_array_r(3);
when others =>
end case;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b K-characters codes: COMMA/SOC/EOC/DATA
-------------------------------------------------------------------------------------------
KcharTests: for I in 0 to 1 generate
KcharTestn: KcharTest
port map(
clk => bitCLK,
encoded10in => word10b_array(I),
KcharCode => isk_array(I)
);
end generate KcharTests;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_s <= word10b_array;
word10b_array_rdy_s <= word10b_array_rdy;
end if;
end process;
--
word10b_array_rdy_s1 <= word10b_array_rdy_s;
-------------------------------------------------------------------------------------------
-- 2 words get aligned and ready as 10 bit word (data 8 bit and data code 2 bit)
-------------------------------------------------------------------------------------------
EPROC_IN4_ALIGN_BLOCK_inst: entity work.EPROC_IN4_ALIGN_BLOCK
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst,
bytes => word10b_array_s,
bytes_rdy => word10b_array_rdy_s1,
dataOUT => dataOUT,
dataOUTrdy => dataOUTrdy,
busyOut => busyOut
);
end Behavioral;
| gpl-3.0 | 0f7a958aa61eb0f018690686e7f4c55f | 0.494088 | 3.810575 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/arp.vhd | 2 | 26,146 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP lookup in cache
-- request cache fill through ARP protocol if required
-- cache is simple 1 deep
-- Handle ARP protocol
-- Respond to ARP requests and replies
-- Ignore pkts that are not ARP
-- Ignore pkts that are not addressed to us
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Added req for mac tx and wait for grant
-- Revision 0.03 - Added data_out_first
-- Revision 0.04 - Added arp response timeout
-- Revision 0.05 - Added arp cache reset control
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.arp_types.all;
entity arp is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 1; -- (added for compatibility with arpv2. this value not used in this impl)
MAX_ARP_ENTRIES : integer := 1 -- (added for compatibility with arpv2. this value not used in this impl)
);
Port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
data_in_last : in STD_LOGIC; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0);
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
control : in arp_control_type;
req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received
);
end arp;
architecture Behavioral of arp is
type req_state_type is (IDLE,LOOKUP,REQUEST,WAIT_REPLY,PAUSE1,PAUSE2,PAUSE3);
type rx_state_type is (IDLE,PARSE,PROCESS_ARP,WAIT_END);
type rx_event_type is (NO_EVENT,DATA);
type count_mode_type is (RST,INCR,HOLD);
type arp_oper_type is (NOP,REQUEST,REPLY);
type set_clr_type is (SET, CLR, HOLD);
type tx_state_type is (IDLE,WAIT_MAC,SEND);
type arp_entry_type is record
ip : std_logic_vector (31 downto 0);
mac : std_logic_vector (47 downto 0);
is_valid : std_logic;
reply_required : std_logic;
end record;
-- state variables
signal req_state : req_state_type;
signal req_ip_addr : std_logic_vector (31 downto 0); -- IP address to lookup
signal mac_addr_found : STD_LOGIC_VECTOR (47 downto 0); -- mac address found
signal mac_addr_valid_reg: std_logic;
signal send_request_needed : std_logic;
signal tx_mac_chn_reqd : std_logic;
signal freq_scaler : unsigned (31 downto 0); -- scales data_in_clk downto 1Hz
signal timer : unsigned (7 downto 0); -- counts seconds timeout
signal timeout_reg : std_logic;
signal rx_state : rx_state_type;
signal rx_count : unsigned (7 downto 0);
signal arp_operation : arp_oper_type;
signal arp_req_count : unsigned (7 downto 0);
signal arp_entry : arp_entry_type; -- arp entry store
signal new_arp_entry : arp_entry_type;
signal tx_state : tx_state_type;
signal tx_count : unsigned (7 downto 0);
-- FIXME - remove these debug state signals
signal arp_err_data : std_logic_vector (7 downto 0);
signal set_err_data : std_logic;
attribute keep : string;
attribute keep of arp_err_data : signal is "true";
-- requester control signals
signal next_req_state : req_state_type;
signal set_req_state : std_logic;
signal set_req_ip : std_logic;
signal set_mac_addr : std_logic;
signal set_mac_addr_invalid : std_logic;
signal set_send_req : std_logic;
signal clear_send_req : std_logic;
signal set_timer : count_mode_type; -- timer reset, count, hold control
signal timer_enable : std_logic; -- enable the timer counting
signal set_timeout : set_clr_type; -- control the timeout register
-- rx control signals
signal next_rx_state : rx_state_type;
signal set_rx_state : std_logic;
signal rx_event : rx_event_type;
signal rx_count_mode : count_mode_type;
signal set_arp_oper : std_logic;
signal arp_oper_set_val : arp_oper_type;
signal dataval : std_logic_vector (7 downto 0);
signal set_arp_entry_request : std_logic;
signal set_mac5 : std_logic;
signal set_mac4 : std_logic;
signal set_mac3 : std_logic;
signal set_mac2 : std_logic;
signal set_mac1 : std_logic;
signal set_mac0 : std_logic;
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
-- tx control signals
signal next_tx_state : tx_state_type;
signal set_tx_state : std_logic;
signal tx_count_mode : count_mode_type;
signal clear_reply_req : std_logic;
signal set_chn_reqd : set_clr_type;
signal kill_data_out_valid : std_logic;
-- function to determine whether the rx pkt is an arp pkt and whether we want to process it
-- Returns 1 if we should discard
-- The following will make us ignore the frame (all values hexadecimal):
-- PDU type /= 0806
-- Protocol Type /= 0800
-- Hardware Type /= 1
-- Hardware Length /= 6
-- Protocol Length /= 4
-- Operation /= 1 or 2
-- Target IP /= our IP (i.er. message is not meant for us)
--
function not_our_arp(data : STD_LOGIC_VECTOR; count : unsigned; our_ip : std_logic_vector) return std_logic is
begin
if
(count = 12 and data /= x"08") or -- PDU type 0806 : ARP
(count = 13 and data /= x"06") or
(count = 14 and data /= x"00") or -- HW type 1 : eth
(count = 15 and data /= x"01") or
(count = 16 and data /= x"08") or -- Protocol 0800 : IP
(count = 17 and data /= x"00") or
(count = 18 and data /= x"06") or -- HW Length 6
(count = 19 and data /= x"04") or -- protocol length 4
(count = 20 and data /= x"00") or -- operation 1 or 2 (req or reply)
(count = 21 and data /= x"01" and data /= x"02") or
(count = 38 and data /= our_ip(31 downto 24)) or -- target IP is ours
(count = 39 and data /= our_ip(23 downto 16)) or
(count = 40 and data /= our_ip(15 downto 8)) or
(count = 41 and data /= our_ip(7 downto 0))
then
return '1';
else
return '0';
end if;
end function not_our_arp;
begin
req_combinatorial : process (
-- input signals
arp_req_req,
-- state variables
req_state, req_ip_addr, mac_addr_found, mac_addr_valid_reg, send_request_needed, arp_entry,
freq_scaler, timer, timeout_reg,
-- control signals
next_req_state, set_req_state, set_req_ip, set_mac_addr, control,
set_mac_addr_invalid,set_send_req, clear_send_req, set_timer, timer_enable, set_timeout
)
begin
-- set output followers
if arp_req_req.lookup_req = '1' then
arp_req_rslt.got_err <= '0';
else
arp_req_rslt.got_err <= timeout_reg;
end if;
-- zero time response to lookup request if already in cache
if arp_req_req.lookup_req = '1' and arp_req_req.ip = arp_entry.ip and arp_entry.is_valid = '1' then
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_entry.mac;
elsif arp_req_req.lookup_req = '1' then
arp_req_rslt.got_mac <= '0'; -- hold off got_mac while req is there as arp_entry will not be correct yet
arp_req_rslt.mac <= arp_entry.mac;
else
arp_req_rslt.got_mac <= mac_addr_valid_reg;
arp_req_rslt.mac <= mac_addr_found;
end if;
-- set signal defaults
next_req_state <= IDLE;
set_req_state <= '0';
set_req_ip <= '0';
set_mac_addr <= '0';
set_mac_addr_invalid <= '0';
set_send_req <= '0';
clear_send_req <= '0';
set_timer <= INCR; -- default is timer running, unless we hold or reset it
set_timeout <= HOLD;
timer_enable <= '0';
-- combinatorial logic
if freq_scaler = x"00000000" then
timer_enable <= '1';
end if;
-- REQ FSM
case req_state is
when IDLE =>
set_timer <= RST;
if arp_req_req.lookup_req = '1' then
-- check if we already have the info in cache
if arp_req_req.ip = arp_entry.ip and arp_entry.is_valid = '1' then
-- already have this IP
set_mac_addr <= '1';
else
set_timeout <= CLR;
next_req_state <= LOOKUP;
set_req_state <= '1';
set_req_ip <= '1';
set_mac_addr_invalid <= '1';
end if;
end if;
when LOOKUP =>
if arp_entry.ip = req_ip_addr and arp_entry.is_valid = '1' then
-- already have this IP
next_req_state <= IDLE;
set_req_state <= '1';
set_mac_addr <= '1';
else
-- need to request mac for this IP
set_send_req <= '1';
set_timer <= RST;
next_req_state <= REQUEST;
set_req_state <= '1';
end if;
when REQUEST =>
clear_send_req <= '1';
next_req_state <= WAIT_REPLY;
set_req_state <= '1';
when WAIT_REPLY =>
if arp_entry.is_valid = '1' then
-- have reply, go back to LOOKUP state to see if it is the right one
next_req_state <= LOOKUP;
set_req_state <= '1';
end if;
if timer >= ARP_TIMEOUT then
set_timeout <= SET;
next_req_state <= PAUSE1;
set_req_state <= '1';
end if;
when PAUSE1 =>
next_req_state <= PAUSE2;
set_req_state <= '1';
when PAUSE2 =>
next_req_state <= PAUSE3;
set_req_state <= '1';
when PAUSE3 =>
next_req_state <= IDLE;
set_req_state <= '1';
end case;
end process;
req_sequential : process (data_in_clk,reset)
begin
if rising_edge(data_in_clk) then
if reset = '1' then
-- reset state variables
req_state <= IDLE;
req_ip_addr <= (others => '0');
mac_addr_found <= (others => '0');
mac_addr_valid_reg <= '0';
send_request_needed <= '0';
freq_scaler <= to_unsigned(CLOCK_FREQ,32);
timer <= (others => '0');
timeout_reg <= '0';
else
-- Next req_state processing
if set_req_state = '1' then
req_state <= next_req_state;
else
req_state <= req_state;
end if;
-- Latch the requested IP address
if set_req_ip = '1' then
req_ip_addr <= arp_req_req.ip;
else
req_ip_addr <= req_ip_addr;
end if;
-- send request to TX&RX FSMs to send an ARP request
if set_send_req = '1' then
send_request_needed <= '1';
elsif clear_send_req = '1' then
send_request_needed <= '0';
else
send_request_needed <= send_request_needed;
end if;
-- Set the found mac address
if set_mac_addr = '1' then
mac_addr_found <= arp_entry.mac;
mac_addr_valid_reg <= '1';
elsif set_mac_addr_invalid = '1' then
mac_addr_found <= (others => '0');
mac_addr_valid_reg <= '0';
else
mac_addr_found <= mac_addr_found;
mac_addr_valid_reg <= mac_addr_valid_reg;
end if;
-- freq scaling and 1-sec timer
if freq_scaler = x"00000000" then
freq_scaler <= to_unsigned(CLOCK_FREQ,32);
else
freq_scaler <= freq_scaler - 1;
end if;
-- timer processing
case set_timer is
when RST =>
timer <= x"00";
when INCR =>
if timer_enable = '1' then
timer <= timer + 1;
else
timer <= timer;
end if;
when HOLD =>
timer <= timer;
end case;
-- timeout latching
case set_timeout is
when CLR => timeout_reg <= '0';
when SET => timeout_reg <= '1';
when HOLD => timeout_reg <= timeout_reg;
end case;
end if;
end if;
end process;
rx_combinatorial : process (
-- input signals
data_in, data_in_valid, data_in_last, our_ip_address,
-- state variables
rx_state, rx_count, arp_operation, arp_req_count, arp_err_data,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode, set_arp_oper, arp_oper_set_val,
dataval,set_mac5,set_mac4,set_mac3,set_mac2,set_mac1,set_mac0,set_ip3,set_ip2,set_ip1,set_ip0, set_err_data,
set_arp_entry_request)
begin
-- set output followers
req_count <= STD_LOGIC_VECTOR(arp_req_count);
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_arp_oper <= '0';
arp_oper_set_val <= NOP;
dataval <= (others => '0');
set_mac5 <= '0';
set_mac4 <= '0';
set_mac3 <= '0';
set_mac2 <= '0';
set_mac1 <= '0';
set_mac0 <= '0';
set_ip3 <= '0';
set_ip2 <= '0';
set_ip1 <= '0';
set_ip0 <= '0';
set_arp_entry_request <= '0';
set_err_data <= '0';
-- determine event (if any)
if data_in_valid = '1' then
rx_event <= DATA;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
next_rx_state <= PARSE;
set_rx_state <= '1';
rx_count_mode <= INCR;
end case;
when PARSE =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
rx_count_mode <= INCR;
-- handle early frame termination
if data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
else
-- check for end of frame. Also, detect and discard if not our frame
if rx_count = 42 then
next_rx_state <= PROCESS_ARP;
set_rx_state <= '1';
elsif not_our_arp(data_in,rx_count,our_ip_address) = '1' then
dataval <= data_in;
set_err_data <= '1';
next_rx_state <= WAIT_END;
set_rx_state <= '1';
elsif rx_count = 21 then
-- capture ARP operation
case data_in is
when x"01" =>
arp_oper_set_val <= REQUEST;
set_arp_oper <= '1';
when x"02" =>
arp_oper_set_val <= REPLY;
set_arp_oper <= '1';
when others => -- ignore other values
end case;
-- capture source mac addr
elsif rx_count = 22 then
set_mac5 <= '1';
dataval <= data_in;
elsif rx_count = 23 then
set_mac4 <= '1';
dataval <= data_in;
elsif rx_count = 24 then
set_mac3 <= '1';
dataval <= data_in;
elsif rx_count = 25 then
set_mac2 <= '1';
dataval <= data_in;
elsif rx_count = 26 then
set_mac1 <= '1';
dataval <= data_in;
elsif rx_count = 27 then
set_mac0 <= '1';
dataval <= data_in;
-- capture source ip addr
elsif rx_count = 28 then
set_ip3 <= '1';
dataval <= data_in;
elsif rx_count = 29 then
set_ip2 <= '1';
dataval <= data_in;
elsif rx_count = 30 then
set_ip1 <= '1';
dataval <= data_in;
elsif rx_count = 31 then
set_ip0 <= '1';
dataval <= data_in;
end if;
end if;
end case;
when PROCESS_ARP =>
next_rx_state <= WAIT_END;
set_rx_state <= '1';
case arp_operation is
when NOP => -- (nothing to do)
when REQUEST =>
set_arp_entry_request <= '1';
arp_oper_set_val <= NOP;
set_arp_oper <= '1';
when REPLY =>
set_arp_entry_request <= '1';
arp_oper_set_val <= NOP;
set_arp_oper <= '1';
end case;
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
end case;
end case;
end process;
rx_sequential : process (data_in_clk)
begin
if rising_edge(data_in_clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"00";
arp_operation <= NOP;
arp_req_count <= x"00";
-- reset arp entry store
arp_entry.ip <= x"00000000";
arp_entry.mac <= x"000000000000";
arp_entry.is_valid <= '0';
arp_entry.reply_required <= '0';
arp_err_data <= (others => '0');
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST =>
rx_count <= x"00";
when INCR =>
rx_count <= rx_count + 1;
when HOLD =>
rx_count <= rx_count;
end case;
-- err data
if set_err_data = '1' then
arp_err_data <= data_in;
else
arp_err_data <= arp_err_data;
end if;
-- arp operation processing
if set_arp_oper = '1' then
arp_operation <= arp_oper_set_val;
else
arp_operation <= arp_operation;
end if;
-- source mac capture
if (set_mac5 = '1') then new_arp_entry.mac(47 downto 40) <= dataval; end if;
if (set_mac4 = '1') then new_arp_entry.mac(39 downto 32) <= dataval; end if;
if (set_mac3 = '1') then new_arp_entry.mac(31 downto 24) <= dataval; end if;
if (set_mac2 = '1') then new_arp_entry.mac(23 downto 16) <= dataval; end if;
if (set_mac1 = '1') then new_arp_entry.mac(15 downto 8) <= dataval; end if;
if (set_mac0 = '1') then new_arp_entry.mac(7 downto 0) <= dataval; end if;
-- source ip capture
if (set_ip3 = '1') then new_arp_entry.ip(31 downto 24) <= dataval; end if;
if (set_ip2 = '1') then new_arp_entry.ip(23 downto 16) <= dataval; end if;
if (set_ip1 = '1') then new_arp_entry.ip(15 downto 8) <= dataval; end if;
if (set_ip0 = '1') then new_arp_entry.ip(7 downto 0) <= dataval; end if;
-- set arp entry request
if control.clear_cache = '1' then
arp_entry.ip <= x"00000000";
arp_entry.mac <= x"000000000000";
arp_entry.is_valid <= '0';
arp_entry.reply_required <= '0';
elsif set_arp_entry_request = '1' then
-- copy info from new entry to arp_entry and set reply required
arp_entry.mac <= new_arp_entry.mac;
arp_entry.ip <= new_arp_entry.ip;
arp_entry.is_valid <= '1';
if arp_operation = REQUEST then
arp_entry.reply_required <= '1';
else
arp_entry.reply_required <= '0';
end if;
-- count another ARP pkt received
arp_req_count <= arp_req_count + 1;
elsif clear_reply_req = '1' then
-- note: clear_reply_req is set by tx logic, but handled in the clk domain of the rx
-- maintain arp entry state, but reset the reply required flag
arp_entry.mac <= arp_entry.mac;
arp_entry.ip <= arp_entry.ip;
arp_entry.is_valid <= arp_entry.is_valid;
arp_entry.reply_required <= '0';
arp_req_count <= arp_req_count;
elsif send_request_needed = '1' then
-- set up the arp entry to take the request to be transmitted out by the TX FSM
arp_entry.ip <= req_ip_addr;
arp_entry.mac <= (others => '0');
arp_entry.is_valid <= '0';
arp_entry.reply_required <= '0';
else
arp_entry <= arp_entry;
arp_req_count <= arp_req_count;
end if;
end if;
end if;
end process;
tx_combinatorial : process (
-- input signals
data_out_ready, send_request_needed, mac_tx_granted, our_mac_address, our_ip_address,
-- state variables
tx_state, tx_count, tx_mac_chn_reqd, arp_entry,
-- control signals
next_rx_state, set_rx_state, tx_count_mode, kill_data_out_valid,
set_chn_reqd, clear_reply_req)
begin
-- set output followers
mac_tx_req <= tx_mac_chn_reqd;
-- set initial values for combinatorial outputs
data_out_first <= '0';
case tx_state is
when SEND =>
if data_out_ready = '1' and kill_data_out_valid = '0' then
data_out_valid <= '1';
else
data_out_valid <= '0';
end if;
when OTHERS => data_out_valid <= '0';
end case;
-- set signal defaults
next_tx_state <= IDLE;
set_tx_state <= '0';
tx_count_mode <= HOLD;
data_out <= x"00";
data_out_last <= '0';
clear_reply_req <= '0';
set_chn_reqd <= HOLD;
kill_data_out_valid <= '0';
-- TX FSM
case tx_state is
when IDLE =>
tx_count_mode <= RST;
if arp_entry.reply_required = '1' then
set_chn_reqd <= SET;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
elsif send_request_needed = '1' then
set_chn_reqd <= SET;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
else
set_chn_reqd <= CLR;
end if;
when WAIT_MAC =>
tx_count_mode <= RST;
if mac_tx_granted = '1' then
next_tx_state <= SEND;
set_tx_state <= '1';
end if;
-- TODO - should handle timeout here
when SEND =>
if data_out_ready = '1' then
tx_count_mode <= INCR;
end if;
case tx_count is
when x"00" =>
data_out_first <= data_out_ready;
data_out <= x"ff"; -- dst = broadcast
when x"01" => data_out <= x"ff";
when x"02" => data_out <= x"ff";
when x"03" => data_out <= x"ff";
when x"04" => data_out <= x"ff";
when x"05" => data_out <= x"ff";
when x"06" => data_out <= our_mac_address (47 downto 40); -- src = our mac
when x"07" => data_out <= our_mac_address (39 downto 32);
when x"08" => data_out <= our_mac_address (31 downto 24);
when x"09" => data_out <= our_mac_address (23 downto 16);
when x"0a" => data_out <= our_mac_address (15 downto 8);
when x"0b" => data_out <= our_mac_address (7 downto 0);
when x"0c" => data_out <= x"08"; -- pkt type = 0806 : ARP
when x"0d" => data_out <= x"06";
when x"0e" => data_out <= x"00"; -- HW type = 0001 : eth
when x"0f" => data_out <= x"01";
when x"10" => data_out <= x"08"; -- protocol = 0800 : ip
when x"11" => data_out <= x"00";
when x"12" => data_out <= x"06"; -- HW size = 06
when x"13" => data_out <= x"04"; -- prot size = 04
when x"14" => data_out <= x"00"; -- opcode =
when x"15" =>
if arp_entry.is_valid = '1' then
data_out <= x"02"; -- 02 : REPLY if arp_entry valid
else
data_out <= x"01"; -- 01 : REQ if arp_entry invalid
end if;
when x"16" => data_out <= our_mac_address (47 downto 40); -- sender mac
when x"17" => data_out <= our_mac_address (39 downto 32);
when x"18" => data_out <= our_mac_address (31 downto 24);
when x"19" => data_out <= our_mac_address (23 downto 16);
when x"1a" => data_out <= our_mac_address (15 downto 8);
when x"1b" => data_out <= our_mac_address (7 downto 0);
when x"1c" => data_out <= our_ip_address (31 downto 24); -- sender ip
when x"1d" => data_out <= our_ip_address (23 downto 16);
when x"1e" => data_out <= our_ip_address (15 downto 8);
when x"1f" => data_out <= our_ip_address (7 downto 0);
when x"20" => data_out <= arp_entry.mac (47 downto 40); -- target mac
when x"21" => data_out <= arp_entry.mac (39 downto 32);
when x"22" => data_out <= arp_entry.mac (31 downto 24);
when x"23" => data_out <= arp_entry.mac (23 downto 16);
when x"24" => data_out <= arp_entry.mac (15 downto 8);
when x"25" => data_out <= arp_entry.mac (7 downto 0);
when x"26" => data_out <= arp_entry.ip (31 downto 24); -- target ip
when x"27" => data_out <= arp_entry.ip (23 downto 16);
when x"28" => data_out <= arp_entry.ip (15 downto 8);
when x"29" =>
data_out <= arp_entry.ip(7 downto 0);
data_out_last <= '1';
when x"2a" =>
clear_reply_req <= '1'; -- reset the reply request (done in the rx clk process domain)
kill_data_out_valid <= '1'; -- data is no longer valid
next_tx_state <= IDLE;
set_tx_state <= '1';
when others =>
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end case;
end process;
tx_sequential : process (data_out_clk,reset)
begin
if rising_edge(data_out_clk) then
if reset = '1' then
-- reset state variables
tx_state <= IDLE;
tx_mac_chn_reqd <= '0';
else
-- Next rx_state processing
if set_tx_state = '1' then
tx_state <= next_tx_state;
else
tx_state <= tx_state;
end if;
-- tx_count processing
case tx_count_mode is
when RST =>
tx_count <= x"00";
when INCR =>
tx_count <= tx_count + 1;
when HOLD =>
tx_count <= tx_count;
end case;
-- control access request to mac tx chn
case set_chn_reqd is
when SET => tx_mac_chn_reqd <= '1';
when CLR => tx_mac_chn_reqd <= '0';
when HOLD => tx_mac_chn_reqd <= tx_mac_chn_reqd;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 205e831165219c3d3ead199ee9d30edc | 0.565211 | 2.956689 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/configuration/udp_reply_handler.vhd | 1 | 5,174 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 25.04.2017 11:05:21
-- Design Name: UDP Reply Handler
-- Module Name: udp_reply_handler - RTL
-- Project Name: NTUA-BNL VMM3 Readout Firmware
-- Target Devices: Xilinx xc7a200t-2fbg484
-- Tool Versions: Vivado 2016.4
-- Description: Module that sends UDP replies to the configuration software
-- via UDP.
--
-- Dependencies:
--
-- Changelog:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity udp_reply_handler is
Port(
------------------------------------
------- General Interface ----------
clk : in std_logic;
enable : in std_logic;
serial_number : in std_logic_vector(31 downto 0);
reply_done : out std_logic;
------------------------------------
---- FIFO Data Select Interface ----
wr_en_conf : out std_logic;
dout_conf : out std_logic_vector(15 downto 0);
packet_len_conf : out std_logic_vector(11 downto 0);
end_conf : out std_logic
);
end udp_reply_handler;
architecture RTL of udp_reply_handler is
signal sn_i : std_logic_vector(31 downto 0) := (others => '0');
signal cnt_packet : unsigned(11 downto 0) := (others => '0');
signal cnt_len : unsigned(11 downto 0) := (others => '0');
type stateType is (ST_IDLE, ST_WAIT_0, ST_WR_HIGH, ST_WR_LOW, ST_WAIT_1, ST_COUNT_AND_DRIVE, ST_DONE);
signal state : stateType := ST_IDLE;
begin
-- FSM that samples the S/N and sends it back to the configuration software
-- as a UDP reply
UDP_reply_FSM: process(clk)
begin
if(rising_edge(clk))then
if(enable = '0')then
sn_i <= (others => '0');
cnt_len <= (others => '0');
wr_en_conf <= '0';
cnt_packet <= (others => '0');
end_conf <= '0';
reply_done <= '0';
state <= ST_IDLE;
else
case state is
-- sample the serial number and start writing data
when ST_IDLE =>
sn_i <= serial_number;
state <= ST_WAIT_0;
-- a wait state
when ST_WAIT_0 =>
state <= ST_WR_HIGH;
-- wr_en FIFO high
when ST_WR_HIGH =>
wr_en_conf <= '1';
state <= ST_WR_LOW;
-- wr_en FIFO low
when ST_WR_LOW =>
wr_en_conf <= '0';
cnt_len <= cnt_len + 1;
state <= ST_WAIT_1;
-- a wait state
when ST_WAIT_1 =>
state <= ST_COUNT_AND_DRIVE;
-- increment the counter to select a different dout
when ST_COUNT_AND_DRIVE =>
if(cnt_packet < 3)then
cnt_packet <= cnt_packet + 1;
state <= ST_WAIT_0;
else
end_conf <= '1';
state <= ST_DONE;
end if;
-- stay here until reset by flow_fsm
when ST_DONE =>
reply_done <= '1';
end_conf <= '0';
when others =>
sn_i <= (others => '0');
wr_en_conf <= '0';
cnt_packet <= (others => '0');
cnt_len <= (others => '0');
end_conf <= '0';
reply_done <= '0';
state <= ST_IDLE;
end case;
end if;
end if;
end process;
-- MUX that drives the apporpiate data to the UDP FIFO
dout_conf_MUX: process(cnt_packet, sn_i)
begin
case cnt_packet is
when "00" => dout_conf <= sn_i(31 downto 16);
when "01" => dout_conf <= sn_i(15 downto 0);
when "10" => dout_conf <= x"C0CA";
when "11" => dout_conf <= x"C01A";
when others => dout_conf <= (others => '0');
end case;
end process;
packet_len_conf <= std_logic_vector(cnt_len);
end RTL; | gpl-3.0 | e16d123236dc9d805ee0aed1178a5768 | 0.492462 | 3.931611 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_OUT8.vhd | 1 | 4,911 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT8
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee,work;
use ieee.std_logic_1164.all;
use work.all;
--! E-link processor, 8bit output
entity EPROC_OUT8 is
generic (do_generate : boolean := true);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
getDataTrig : out std_logic; -- @ bitCLKx4
ENCODING : in std_logic_vector (3 downto 0);
EDATA_OUT : out std_logic_vector (7 downto 0);
TTCin : in std_logic_vector (8 downto 0);
DATA_IN : in std_logic_vector (9 downto 0);
DATA_RDY : in std_logic
);
end EPROC_OUT8;
architecture Behavioral of EPROC_OUT8 is
constant zeros8bit : std_logic_vector (7 downto 0) := (others=>'0');
signal EdataOUT_ENC8b10b_case, EdataOUT_direct_case, EdataOUT_HDLC_case, EdataOUT_TTC3_case, EdataOUT_TTC4_case : std_logic_vector (7 downto 0);
signal rst_s, rst_case000, rst_case001, rst_case010, rst_case011 : std_logic;
signal getDataTrig_ENC8b10b_case, getDataTrig_direct_case, getDataTrig_HDLC_case, getDataTrig_TTC_cases : std_logic;
begin
gen_enabled: if do_generate = true generate
rst_s <= rst or (not ENA);
-------------------------------------------------------------------------------------------
-- case 0: direct data, no delimeter...
-------------------------------------------------------------------------------------------
rst_case000 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "000")) else '1';
--
getDataTrig_direct_case <= '1' when (ENCODING(2 downto 0) = "000") else '0';
EdataOUT_direct_case <= (others=>'0');
--
-------------------------------------------------------------------------------------------
-- case 1: DEC8b10b
-------------------------------------------------------------------------------------------
rst_case001 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "001")) else '1';
--
ENC8b10b_case: entity work.EPROC_OUT8_ENC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case001,
getDataTrig => getDataTrig_ENC8b10b_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_ENC8b10b_case
);
--
-------------------------------------------------------------------------------------------
-- case 2: HDLC
-------------------------------------------------------------------------------------------
rst_case010 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "010")) else '1';
--
getDataTrig_HDLC_case <= '0'; --'1' when (ENCODING(2 downto 0) = "010") else '0';
EdataOUT_HDLC_case <= (others=>'0'); --<---TBD
--
-------------------------------------------------------------------------------------------
-- case 3&4: TTC-3 & TTC-4
-------------------------------------------------------------------------------------------
rst_case011 <= '0' when ((rst_s = '0') and ((ENCODING(2 downto 0) = "011") or (ENCODING(2 downto 0) = "100"))) else '1';
--
getDataTrig_TTC_cases <= '0'; --'1' when ((ENCODING(2 downto 0) = "011") or (ENCODING(2 downto 0) = "100")) else '0';
--
ttc_r: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst_case011 = '1' then
EdataOUT_TTC3_case <= zeros8bit;
EdataOUT_TTC4_case <= zeros8bit;
else
EdataOUT_TTC3_case <= TTCin(1) & TTCin(7 downto 2) & TTCin(0);
EdataOUT_TTC4_case <= TTCin(8 downto 2) & TTCin(0);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- output data and busy according to the encoding settings
-------------------------------------------------------------------------------------------
dataOUTmux: entity work.MUX8_Nbit
generic map (N=>8)
port map(
data0 => EdataOUT_direct_case,
data1 => EdataOUT_ENC8b10b_case,
data2 => EdataOUT_HDLC_case,
data3 => EdataOUT_TTC3_case,
data4 => EdataOUT_TTC4_case,
data5 => zeros8bit,
data6 => zeros8bit,
data7 => zeros8bit,
sel => ENCODING(2 downto 0),
data_out => EDATA_OUT
);
--
getDataTrig <= ENA and (getDataTrig_TTC_cases or getDataTrig_HDLC_case or getDataTrig_ENC8b10b_case or getDataTrig_direct_case);
--
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
EDATA_OUT <= (others=>'0');
getDataTrig <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 | 111cf47f03067573349fc62fff4327b6 | 0.465893 | 3.737443 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4088/EPROC_FIFO_DRIVER.vhd | 1 | 21,682 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: EPROC_FIFO_DRIVER
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.all;
use work.centralRouter_package.all;
--! a driver for EPROC FIFO, manages block header and sub-chunk trailer
entity EPROC_FIFO_DRIVER is
generic (
GBTid : integer := 0;
egroupID : integer := 0;
epathID : integer := 0;
toHostTimeoutBitn : integer := 8
);
port (
clk40 : in std_logic;
clk160 : in std_logic;
rst : in std_logic;
----------
encoding : in std_logic_vector (1 downto 0);
maxCLEN : in std_logic_vector (2 downto 0);
---------
DIN : in std_logic_vector (9 downto 0);
DIN_RDY : in std_logic;
----------
xoff : in std_logic;
timeCntIn : in std_logic_vector ((toHostTimeoutBitn-1) downto 0);
TimeoutEnaIn: in std_logic;
----------
wordOUT : out std_logic_vector (15 downto 0);
wordOUT_RDY : out std_logic
);
end EPROC_FIFO_DRIVER;
architecture Behavioral of EPROC_FIFO_DRIVER is
--
signal BLOCK_HEADER : std_logic_vector (31 downto 0) := (others => '0');
signal DIN_r : std_logic_vector (7 downto 0) := (others => '0');
signal DIN_CODE_r : std_logic_vector (1 downto 0) := (others => '0');
signal DIN_s : std_logic_vector (9 downto 0);
signal DIN_RDY_r : std_logic := '0';
---
signal receiving_state, data_shift_trig, trailer_shift_trig, trailer_shift_trig_s,
EOC_error, SOC_error, rst_clen_counter, data16bit_rdy,
data16bit_rdy_shifted, truncating_state, truncation_trailer_sent : std_logic := '0';
signal send_trailer_trig : std_logic;
signal DIN_prev_is_zeroByte, DIN_is_zeroByte : std_logic := '0';
signal direct_data_mode, direct_data_boundary_detected : std_logic;
signal trailer_trunc_bit, trailer_cerr_bit, first_subchunk, first_subchunk_on : std_logic := '0';
signal trailer_mod_bits : std_logic_vector (1 downto 0);
signal trailer_type_bits : std_logic_vector (2 downto 0) := (others => '0');
signal EOB_MARK, truncateDataFlag, flushed, data_rdy : std_logic;
signal trailer_shift_trigs, trailer_shift_trig0, header_shift_trigs : std_logic;
signal trailer_shift_trig1 : std_logic := '0';
signal data16bit_rdy_code : std_logic_vector (2 downto 0);
signal trailer, trailer0, trailer1, header, data : std_logic_vector (15 downto 0);
signal wordOUT_s : std_logic_vector (15 downto 0) := (others => '0');
signal pathENA, DIN_RDY_s : std_logic := '0';
signal pathENAtrig, blockCountRdy,timeout_trailer_send_1st_clk : std_logic;
--
signal timeCnt_lastClk : std_logic_vector ((toHostTimeoutBitn-1) downto 0);
signal receiving_state_clk40, do_transmit_timeout_trailers,timout_ena,timeout_trailer_send : std_logic := '0';
--
constant zero_data_trailer : std_logic_vector(15 downto 0) := "0000000000000000"; -- "000"=null chunk, "00"=no truncation & no cerr, '0', 10 bit length is zero;
constant timeout_trailer : std_logic_vector(15 downto 0) := "1010000000000000"; -- "101"=timeout, "00"=no truncation & no cerr, '0', 10 bit length is zero;
--
begin
------------------------------------------------------------
-- time out counter for triggering the send-out of an
-- incomplete block
------------------------------------------------------------
process(clk40,rst)
begin
if rst = '1' then
receiving_state_clk40 <= '0';
elsif rising_edge (clk40) then
receiving_state_clk40 <= receiving_state;
end if;
end process;
--
process(clk40,rst)
begin
if rst = '1' then
timeCnt_lastClk <= (others=>'1');
elsif rising_edge (clk40) then
if receiving_state_clk40 = '1' then
timeCnt_lastClk <= timeCntIn;
end if;
end if;
end process;
--
p0: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk160, do_transmit_timeout_trailers, timeout_trailer_send_1st_clk);
--
process(clk160,rst)
begin
if rst = '1' then
do_transmit_timeout_trailers <= '0';
elsif rising_edge (clk160) then
if timeCnt_lastClk = timeCntIn and timout_ena = '1' and TimeoutEnaIn = '1' then
do_transmit_timeout_trailers <= '1';
elsif ((DIN_RDY = '1' and DIN(9 downto 8) /= "11") or EOB_MARK = '1') then
do_transmit_timeout_trailers <= '0';
end if;
end if;
end process;
--
process(clk160,rst)
begin
if rst = '1' then
timeout_trailer_send <= '0';
elsif rising_edge (clk160) then
if timeout_trailer_send_1st_clk = '1' then
timeout_trailer_send <= '1';
elsif data16bit_rdy = '1' then -- timeout_trailer was sent once, the rest of the block will be filled with null-trailers
timeout_trailer_send <= '0';
end if;
end if;
end process;
--
process(clk160,rst)
begin
if rst = '1' then
timout_ena <= '0';
elsif rising_edge (clk160) then
if receiving_state = '1' then
timout_ena <= '1';
elsif do_transmit_timeout_trailers = '1' then
timout_ena <= '0';
end if;
end if;
end process;
--
---------------------------------------------
-- CLK1: register the input
---------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
if do_transmit_timeout_trailers = '0' then
DIN_s <= DIN;
DIN_RDY_s <= '1';
else
DIN_s <= "0100000000";
DIN_RDY_s <= '1';
end if;
else
DIN_RDY_s <= '0';
end if;
end if;
end process;
-- for the direct data case:
-- register the input byte comparator result
-- for the direct data case to detect zeros as data delimeter
direct_data_mode <= not(encoding(1) or encoding(0));
--
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
if DIN(7 downto 0) = "00000000" then
DIN_is_zeroByte <= '1';
else
DIN_is_zeroByte <= '0';
end if;
end if;
end if;
end process;
-- pipeline the input byte comparator result
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
DIN_prev_is_zeroByte <= DIN_is_zeroByte;
end if;
end if;
end process;
--
direct_data_boundary_detected <= '1' when (DIN_is_zeroByte = '1' and DIN_prev_is_zeroByte = '1') else '0';
--
---------------------------------------------
-- initial enabling of the path:
-- enabled after reset on the first
-- valid input symbol (must be comma!)
-- the first symbol is then lost! as we are sending
-- a bloack header when it is detected
---------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if rst = '1' then
pathENA <= '0';
elsif DIN_RDY_s = '1' then --
pathENA <= '1';
end if;
end if;
end process;
-- trigger to restart the block counter
pathENA1clk: entity work.pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(clk160, pathENA, pathENAtrig);
---------------------------------------------
-- CLK2:
---------------------------------------------
--
DIN_RDY_r <= DIN_RDY_s; --and pathENA; --blockCountRdy;
DIN_r <= DIN_s(7 downto 0);
--process(clk160)
--begin
-- if rising_edge (clk160) then
-- DIN_r <= DIN_s(7 downto 0);
-- end if;
--end process;
--
--process(clk160)
--begin
-- if rising_edge (clk160) then
-- if direct_data_mode = '1' then
-- if DIN_is_zeroByte = '1' and DIN_prev_is_zeroByte = '1' then
-- DIN_CODE_r <= "10"; -- soc
-- else
-- DIN_CODE_r <= "00"; -- data
-- end if;
-- else
-- DIN_CODE_r <= DIN_s(9 downto 8);
-- end if;
-- end if;
--end process;
--
process(direct_data_mode, direct_data_boundary_detected, DIN_s(9 downto 8))
begin
if direct_data_mode = '1' then
DIN_CODE_r <= direct_data_boundary_detected & '0'; -- "10"=soc, "00"=data
else
DIN_CODE_r <= DIN_s(9 downto 8);
end if;
end process;
--
-----------------------------------------------------------
-- clock 3
-- case of the input word code:
-- "00" => data, "01" => EOC, "10" => SOC, "11" => COMMA
-----------------------------------------------------------
process(clk160, rst)
begin
if rst = '1' then
--
receiving_state <= '0';
trailer_trunc_bit <= '1';
trailer_cerr_bit <= '1';
trailer_type_bits <= "000"; -- not a legal code
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
truncating_state <= '0';
--
elsif rising_edge (clk160) then
if DIN_RDY_r = '1' then
case (DIN_CODE_r) is
when "00" => -- data
--
data_shift_trig <= (receiving_state) and (not truncateDataFlag); -- shift-in data if in the receiving state
-- if block filled up after that, chunk trailer and block header will be shifted-in as well
trailer_trunc_bit <= truncateDataFlag; -- truncation mark in case of CLEN_error
trailer_cerr_bit <= truncateDataFlag; -- CLEN_error is '1' in case of receiving data after CLEN is reached
trailer_type_bits <= (not (truncateDataFlag or first_subchunk)) & truncateDataFlag & first_subchunk; -- 001_first, 011_whole, 100_middle, 010_last
trailer_shift_trig <= truncateDataFlag and receiving_state; -- send a trailer once when CLEN value is reached (SOC will rst the chunk-len-counter)
receiving_state <= receiving_state and (not truncateDataFlag); -- switching off receiving in case of truncateDataFlag, waiting for SOC now
EOC_error <= '0';
SOC_error <= not receiving_state; -- if current state is not 'receiving', flag an error, do nothing
rst_clen_counter <= '0';
first_subchunk_on <= '0';
truncating_state <= truncateDataFlag and receiving_state; -- truncation trailer is sent in this 'case' (once)
--
when "01" => -- EOC
--
trailer_shift_trig <= receiving_state or do_transmit_timeout_trailers; -- if '1' => correct state, shift-in a trailer, if not, do nothing
-- sending a trailer is including padding with zeros ('flush') in case of even word count (should be flagged somewhere...)
trailer_trunc_bit <= '0'; -- no truncation, proper ending
trailer_cerr_bit <= '0';
trailer_type_bits <= do_transmit_timeout_trailers & '1' & first_subchunk; -- 'last sub-chunk' or 'whole sub-chunk' mark
EOC_error <= not receiving_state; -- if current state was not 'receiving', flag an error, do nothing
receiving_state <= '0';
--
truncating_state <= truncating_state;
rst_clen_counter <= '0';
first_subchunk_on <= '0';
data_shift_trig <= '0';
SOC_error <= '0';
--
when "10" => -- SOC
--
trailer_shift_trig <= (receiving_state and (not direct_data_mode)) or (truncateDataFlag and (not truncation_trailer_sent)); -- if '1' => incorrect state, shift-in a trailer to finish the unfinished chunk
-- sending a trailer is including padding with zeros ('flush') in case of even word count (should be flagged somewhere...)
trailer_trunc_bit <= '1'; -- truncation mark in case of sending a trailer (this is when EOC was not received)
trailer_cerr_bit <= '1';
trailer_type_bits <= "01" & (first_subchunk or truncateDataFlag); -- 'last sub-chunk' or 'whole sub-chunk' mark
SOC_error <= receiving_state; -- if current state was already 'receiving', flag an error
receiving_state <= not truncateDataFlag; --'1';
rst_clen_counter <= '1';
first_subchunk_on <= '1';
truncating_state <= truncateDataFlag and (not truncation_trailer_sent); -- truncation trailer is sent in this 'case' (once)
--
data_shift_trig <= '0';
EOC_error <= '0';
--
when "11" => -- COMMA
--
-- do nothing
receiving_state <= receiving_state;
truncating_state <= truncating_state;
trailer_trunc_bit <= '0';
trailer_cerr_bit <= '0';
trailer_type_bits <= "000";
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
--
when others =>
end case;
else
receiving_state <= receiving_state;
trailer_trunc_bit <= trailer_trunc_bit;
trailer_cerr_bit <= trailer_cerr_bit;
trailer_type_bits <= trailer_type_bits; --"000";
truncating_state <= truncating_state;
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
end if;
end if;
end process;
-----------------------------------------------------------
-- truncation trailer should be only sent once (the first one)
-----------------------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if truncateDataFlag = '0' then
truncation_trailer_sent <= '0';
else -- truncateDataFlag = '1':
if trailer_shift_trig = '1' then
truncation_trailer_sent <= '1'; -- latch
end if;
end if;
end if;
end process;
--
-----------------------------------------------------------
-- clock3, writing to the shift register
-- data8bit ready pulse
-----------------------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then -- first, try to flush the shift register
trailer_shift_trig_s <= trailer_shift_trig and (not EOB_MARK); -- this trailer is a result of {eoc} or {soc without eoc} or {max clen violation}
end if;
end process;
--
send_trailer_trig <= trailer_shift_trig_s or EOB_MARK;
--
DATA_shift_r: entity work.reg8to16bit -- only for data or 'flush' padding
PORT MAP(
rst => rst,
clk => clk160,
flush => trailer_shift_trig,
din => DIN_r,
din_rdy => data_shift_trig,
-----
flushed => flushed,
dout => data,
dout_rdy => data_rdy
);
-----------------------------------------------------------
-- clock
-- BLOCK_WORD_COUNTER
-----------------------------------------------------------
--BLOCK_HEADER <= "1010101111001101" & "00000" & "0000" & egroupID & '0' & epathID; -- 0xABCD_
--std_logic_vector(to_unsigned(GBTid, 5))
-- [0xABCD_16] [[00000_5] [GBTid_5 egroupID_3 epathID_3]]
BLOCK_HEADER <= "1010101111001101" & "00000" & (std_logic_vector(to_unsigned(GBTid, 5))) & (std_logic_vector(to_unsigned(egroupID, 3))) & (std_logic_vector(to_unsigned(epathID, 3)));
--
BLOCK_WORD_COUNTER_inst: entity work.BLOCK_WORD_COUNTER
PORT MAP(
CLK => clk160,
RESET => rst,
RESTART => pathENAtrig,
BW_RDY => data16bit_rdy, -- counts everything that is written to EPROC FIFO
BLOCK_HEADER => BLOCK_HEADER,
EOB_MARK => EOB_MARK, -- End-Of-Block: 'send the chunk trailer' trigger
BLOCK_HEADER_OUT => header,
BLOCK_HEADER_OUT_RDY => header_shift_trigs,
BLOCK_COUNT_RDY => blockCountRdy
);
--
process(clk160)
begin
if rising_edge (clk160) then
if first_subchunk_on = '1' or rst = '1' then
first_subchunk <= '1';
elsif EOB_MARK = '1' then
first_subchunk <= '0';
end if;
end if;
end process;
-----------------------------------------------------------
-- Sub-Chunk Data manager
-- sends a trailer in 2 clocks (current clock and the next)
-----------------------------------------------------------
--
trailer_mod_bits <= trailer_trunc_bit & trailer_cerr_bit;
--
SCDataMANAGER_inst: entity work.SCDataMANAGER
PORT MAP(
CLK => clk160,
rst => rst,
xoff => xoff,
maxCLEN => maxCLEN,
rstCLENcount => rst_clen_counter,
truncateCdata => truncateDataFlag, -- out, next data will be truncated, a trailer will be sent instead
trailerMOD => trailer_mod_bits, -- in, keeps its value till the next DIN_RDY_s
trailerTYPE => trailer_type_bits, -- in, keeps its value till the next DIN_RDY_s
trailerRSRVbit => xoff,
-------
trailerSENDtrig => send_trailer_trig,
dataCNTena => data_shift_trig, -- counts data Bytes (not 16-bit words)data_rdy, -- counts only data (or 'flush' padding), no header, no trailer
-------
trailerOUT => trailer0,
trailerOUTrdy => trailer_shift_trig0
);
--
--
process(clk160)
begin
if rising_edge (clk160) then
trailer_shift_trig1 <= flushed;
trailer1 <= trailer0;
end if;
end process;
--
trailer_shift_trigs <= (trailer_shift_trig0 and (not flushed)) or trailer_shift_trig1;
--
process(trailer_shift_trig1, trailer1, trailer0)
begin
if trailer_shift_trig1 = '1' then
trailer <= trailer1;
else
trailer <= trailer0;
end if;
end process;
-----------------------------------------------------------
-- 16 bit output MUX, goes to a EPROC FIFO
-----------------------------------------------------------
--process(clk160)
--begin
-- if clk160'event and clk160 = '0' then
-- data16bit_rdy_shifted <= data16bit_rdy;
-- end if;
--end process;
--
data16bit_rdy <= data_rdy or trailer_shift_trigs or header_shift_trigs;
data16bit_rdy_code(0) <= (not trailer_shift_trigs) and (data_rdy xor header_shift_trigs);
data16bit_rdy_code(1) <= (not header_shift_trigs) and (data_rdy xor trailer_shift_trigs);
data16bit_rdy_code(2) <= do_transmit_timeout_trailers;
--
--process(data16bit_rdy_code, data, header, trailer)
process(clk160)
begin
if rising_edge (clk160) then
case (data16bit_rdy_code) is
when "001" => -- header
wordOUT_s <= header;
when "010" => -- trailer
wordOUT_s <= trailer;
when "011" => -- data
wordOUT_s <= data;
when "100" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "101" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "110" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "111" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when others =>
--wordOUT_s <= (others => '0');
end case;
end if;
end process;
--
--
process(clk160)
begin
if rising_edge (clk160) then
if rst = '1' then
wordOUT_RDY <= '0';
else
wordOUT_RDY <= data16bit_rdy;-- or data16bit_rdy_shifted;
end if;
end if;
end process;
--
wordOUT <= wordOUT_s;
end Behavioral;
| gpl-3.0 | 4f9b404fb62a15e8eeaadc10cfefd978 | 0.505212 | 3.880795 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_IN2_ALIGN_BLOCK.vhd | 1 | 1,553 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2_ALIGN_BLOCK
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
use work.centralRouter_package.all;
--!
entity EPROC_IN2_ALIGN_BLOCK is
port (
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
bytes : in std_logic_vector(9 downto 0);
bytes_rdy : in std_logic;
------------
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
------------
busyOut : out std_logic
);
end EPROC_IN2_ALIGN_BLOCK;
architecture Behavioral of EPROC_IN2_ALIGN_BLOCK is
begin
-------------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------------
dec_8b10: entity work.dec_8b10_wrap --
port map(
RESET => rst,
RBYTECLK => bitCLKx4,
ABCDEIFGHJ_IN => bytes,
HGFEDCBA => dataOUT(7 downto 0),
ISK => dataOUT(9 downto 8),
BUSY => busyOut
);
--
rdy_pipe: entity work.pulse_pdxx_pwxx generic map(pd=>1,pw=>1) port map(bitCLKx4,bytes_rdy,dataOUTrdy);
--
end Behavioral;
| gpl-3.0 | 5aa64c1048ca97eb89552542b30aa264 | 0.448165 | 3.921717 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN2_ALIGN_BLOCK.vhd | 1 | 1,822 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2_ALIGN_BLOCK
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
use work.centralRouter_package.all;
--!
entity EPROC_IN2_ALIGN_BLOCK is
port (
bitCLK : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
bytes : in std_logic_vector(9 downto 0);
bytes_rdy : in std_logic;
------------
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
------------
busyOut : out std_logic
);
end EPROC_IN2_ALIGN_BLOCK;
architecture Behavioral of EPROC_IN2_ALIGN_BLOCK is
signal dataOUTrdy_s : std_logic := '0';
begin
-------------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------------
dec_8b10: entity work.dec_8b10_wrap --
port map(
RESET => rst,
RBYTECLK => bitCLK,
ABCDEIFGHJ_IN => bytes,
HGFEDCBA => dataOUT(7 downto 0),
ISK => dataOUT(9 downto 8),
BUSY => busyOut
);
--
process(bitCLK)
begin
if rising_edge(bitCLK) then
if bytes_rdy = '1' then
dataOUTrdy_s <= '1';
else
dataOUTrdy_s <= '0';
end if;
end if;
end process;
--
rdy_pipe: entity work.pulse_pdxx_pwxx generic map(pd=>1,pw=>1) port map(bitCLKx4,dataOUTrdy_s,dataOUTrdy);
--
end Behavioral;
| gpl-3.0 | 5e40712e9c24607dcf0349c7917fcc55 | 0.45225 | 3.868365 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN4_direct.vhd | 4 | 3,202 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN4_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data driver for EPROC_IN2 module
entity EPROC_IN4_direct is
port (
bitCLK : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (3 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN4_direct;
architecture Behavioral of EPROC_IN4_direct is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
signal word10b : std_logic_vector (9 downto 0) := "1100000000"; -- comma
signal word8b : std_logic_vector (7 downto 0) := (others=>'0');
signal inpcount : std_logic := '0';
signal word8bRdy, word10bRdy : std_logic := '0';
begin
-------------------------------------------------------------------------------------------
-- input counter 0 to 1
-------------------------------------------------------------------------------------------
input_count: process(bitCLK, rst)
begin
if rst = '1' then
inpcount <= '0';
elsif bitCLK'event and bitCLK = '1' then
inpcount <= not inpcount;
end if;
end process;
-------------------------------------------------------------------------------------------
-- input mapping
-------------------------------------------------------------------------------------------
input_map: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case inpcount is
when '0' => word8b(3 downto 0) <= edataIN;
when '1' => word8b(7 downto 4) <= edataIN;
when others =>
end case;
end if;
end process;
-------------------------------------------------------------------------------------------
-- output (code = "00" = data)
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word8bRdy <= inpcount;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if word8bRdy = '1' then
word10b <= "00" & word8b; -- data
word10bRdy <= '1';
else
word10bRdy <= '0';
end if;
end if;
end process;
dataOUT <= word10b;
dataOUTrdy_pulse: pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(bitCLKx4, word10bRdy, dataOUTrdy);
end Behavioral;
| gpl-3.0 | f3be60ad5c0273087d220b7a11f7811e | 0.417239 | 4.34464 | false | false | false | false |
atti92/heterogenhomework | project1/solution1/syn/vhdl/fir_hw_mul_18s_15s_33_3.vhd | 1 | 2,684 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.2
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fir_hw_mul_18s_15s_33_3_MAC3S_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(18 - 1 downto 0);
b: in std_logic_vector(15 - 1 downto 0);
p: out std_logic_vector(33 - 1 downto 0));
end entity;
architecture behav of fir_hw_mul_18s_15s_33_3_MAC3S_0 is
signal tmp_product : std_logic_vector(33 - 1 downto 0);
signal a_i : std_logic_vector(18 - 1 downto 0);
signal b_i : std_logic_vector(15 - 1 downto 0);
signal p_tmp : std_logic_vector(33 - 1 downto 0);
signal a_reg0 : std_logic_vector(18 - 1 downto 0);
signal b_reg0 : std_logic_vector(15 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(33 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed(a_reg0) * signed(b_reg0))), 33));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity fir_hw_mul_18s_15s_33_3 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of fir_hw_mul_18s_15s_33_3 is
component fir_hw_mul_18s_15s_33_3_MAC3S_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
fir_hw_mul_18s_15s_33_3_MAC3S_0_U : component fir_hw_mul_18s_15s_33_3_MAC3S_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| gpl-2.0 | ba0bb13ac77a1a05561f7b99e508c3a6 | 0.545455 | 3.153937 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_FIFO_DRIVER.vhd | 1 | 23,393 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: EPROC_FIFO_DRIVER
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.all;
use work.centralRouter_package.all;
--! a driver for EPROC FIFO, manages block header and sub-chunk trailer
entity EPROC_FIFO_DRIVER is
generic (
GBTid : integer := 0;
egroupID : integer := 0;
epathID : integer := 0;
toHostTimeoutBitn : integer := 8
);
port (
clk40 : in std_logic;
clk160 : in std_logic;
rst : in std_logic;
----------
encoding : in std_logic_vector (1 downto 0);
maxCLEN : in std_logic_vector (2 downto 0);
---------
DIN : in std_logic_vector (9 downto 0);
DIN_RDY : in std_logic;
----------
xoff : in std_logic;
timeCntIn : in std_logic_vector ((toHostTimeoutBitn-1) downto 0);
TimeoutEnaIn: in std_logic;
----------
wordOUT : out std_logic_vector (15 downto 0);
wordOUT_RDY : out std_logic
);
end EPROC_FIFO_DRIVER;
architecture Behavioral of EPROC_FIFO_DRIVER is
--
signal DIN_r : std_logic_vector (7 downto 0) := (others => '0');
signal DIN_CODE_r : std_logic_vector (1 downto 0) := (others => '0');
signal DIN_s : std_logic_vector (9 downto 0);
signal DIN_RDY_r : std_logic := '0';
---
signal receiving_state, data_shift_trig, trailer_shift_trig, trailer_shift_trig_s,
EOC_error, SOC_error, rst_clen_counter, data16bit_rdy,
data16bit_rdy_shifted, truncating_state, truncation_trailer_sent : std_logic := '0';
signal send_trailer_trig,data_shift_trig_s : std_logic;
signal DIN_prev_is_zeroByte, DIN_is_zeroByte : std_logic := '0';
signal direct_data_mode, direct_data_boundary_detected : std_logic;
signal trailer_trunc_bit, trailer_cerr_bit, first_subchunk, first_subchunk_on : std_logic := '0';
signal trailer_mod_bits : std_logic_vector (1 downto 0);
signal trailer_type_bits : std_logic_vector (2 downto 0) := (others => '0');
signal EOB_MARK, truncateDataFlag, flushed, flush_trig, data_rdy : std_logic;
signal trailer_shift_trigs, trailer_shift_trig0, header_shift_trigs : std_logic;
signal trailer_shift_trig1 : std_logic := '0';
signal data16bit_rdy_code : std_logic_vector (2 downto 0);
signal trailer, trailer0, trailer1, header, data : std_logic_vector (15 downto 0);
signal wordOUT_s : std_logic_vector (15 downto 0) := (others => '0');
signal pathENA, DIN_RDY_s : std_logic := '0';
signal pathENAtrig, blockCountRdy,timeout_trailer_send,xoff_s : std_logic;
--
signal timeCnt_lastClk : std_logic_vector ((toHostTimeoutBitn-1) downto 0);
signal do_transmit_timeout_trailers,timout_ena,truncation_from_timeout,truncating_state_clk40 : std_logic := '0';
signal zero_trailer_send_pulse_count : std_logic_vector (2 downto 0) := (others=>'0');
signal zero_trailer_send_pulse,truncation_from_timeout_trig,timeout_event_clk0,timeout_event_clk1,data_on_input,data_on_input_clk40 : std_logic;
--
constant zero_data_trailer : std_logic_vector(15 downto 0) := "0000000000000000"; -- "000"=null chunk, "00"=no truncation & no cerr, '0', 10 bit length is zero;
constant timeout_trailer : std_logic_vector(15 downto 0) := "1010000000000000"; -- "101"=timeout, "00"=no truncation & no cerr, '0', 10 bit length is zero;
signal work_state,sop_in : std_logic := '0';
--
begin
------------------------------------------------------------
-- time out counter for triggering the send-out of an
-- incomplete block
------------------------------------------------------------
--data_on_input <= '1' when (DIN_RDY = '1' and DIN(9 downto 8) /= "11" and truncating_state_clk40 = '0') else '0';
--
process(clk160,rst)
begin
if rst = '1' then
data_on_input <= '0';
elsif rising_edge (clk160) then
if DIN_RDY = '1' then
if DIN(9 downto 8) /= "11" then -- data
data_on_input <= not truncating_state_clk40;
if DIN(9 downto 8) = "10" then -- sop
sop_in <= '1';
else
sop_in <= '0';
end if;
else
data_on_input <= '0';
sop_in <= '0';
end if;
else
data_on_input <= '0';
end if;
end if;
end process;
--
tcdc: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>5) port map(clk160, data_on_input, data_on_input_clk40);
--
process(clk40,rst)
begin
if rst = '1' then
timeCnt_lastClk <= (others=>'1');
truncating_state_clk40 <= '0';
work_state <= '0';
elsif rising_edge (clk40) then
if TimeoutEnaIn = '0' then
timeCnt_lastClk <= (others=>'1');
truncating_state_clk40 <= '0';
work_state <= '0';
else
truncating_state_clk40 <= truncating_state; -- cdc
--
if timeCntIn(0) = '1' then
work_state <= TimeoutEnaIn;
end if;
--
if (data_on_input_clk40 = '1' or timout_ena = '0') and work_state = '1' then
timeCnt_lastClk <= timeCntIn; -- [valid data] or [disabled timeout] re-set counter cycle start point
end if;
end if;
end if;
end process;
--
--
process(clk40,rst)
begin
if rst = '1' then
timeout_event_clk0 <= '0';
elsif rising_edge (clk40) then --
if timeCnt_lastClk = timeCntIn then
timeout_event_clk0 <= TimeoutEnaIn;
else
timeout_event_clk0 <= '0';
end if;
--
timeout_event_clk1 <= timeout_event_clk0 and (not sop_in);
--
end if;
end process;
--
--t0: entity work.pulse_pdxx_pwxx generic map(pd=>1,pw=>1) port map(clk40, timeout_event_clk0, timeout_event_clk1);
--
truncation_from_timeout <= timeout_event_clk0 and (not sop_in);
p0: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk160, truncation_from_timeout, truncation_from_timeout_trig);
--
--
process(clk160,rst)
begin
if rst = '1' then
do_transmit_timeout_trailers <= '0';
elsif rising_edge (clk160) then
if timeout_event_clk1 = '1' then --timeCnt_lastClk = timeCntIn and timout_ena = '1' and TimeoutEnaIn = '1' then
do_transmit_timeout_trailers <= TimeoutEnaIn;
elsif (data_on_input = '1' or EOB_MARK = '1') then
do_transmit_timeout_trailers <= '0';
end if;
end if;
end process;
--
--
p1: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk160, do_transmit_timeout_trailers, timeout_trailer_send);
xoff_s <= xoff or truncation_from_timeout;
--
process(clk160,rst)
begin
if rst = '1' then
timout_ena <= '0';
elsif rising_edge (clk160) then
if do_transmit_timeout_trailers = '1' then
timout_ena <= '0';
elsif receiving_state = '1' then
timout_ena <= '1';
end if;
end if;
end process;
--
---------------------------------------------
-- CLK1: register the input
---------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
DIN_s <= DIN;
DIN_RDY_s <= '1';
else
DIN_RDY_s <= '0';
end if;
end if;
end process;
-- for the direct data case:
-- register the input byte comparator result
-- for the direct data case to detect zeros as data delimeter
direct_data_mode <= not(encoding(1) or encoding(0));
--
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
if DIN(7 downto 0) = "00000000" then
DIN_is_zeroByte <= '1';
else
DIN_is_zeroByte <= '0';
end if;
end if;
end if;
end process;
-- pipeline the input byte comparator result
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
DIN_prev_is_zeroByte <= DIN_is_zeroByte;
end if;
end if;
end process;
--
direct_data_boundary_detected <= '1' when (DIN_is_zeroByte = '1' and DIN_prev_is_zeroByte = '1') else '0';
--
---------------------------------------------
-- initial enabling of the path:
-- enabled after reset on the first
-- valid input symbol (must be comma!)
-- the first symbol is then lost! as we are sending
-- a bloack header when it is detected
---------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if rst = '1' then
pathENA <= '0';
elsif DIN_RDY_s = '1' then --
pathENA <= '1';
end if;
end if;
end process;
-- trigger to restart the block counter
pathENA1clk: entity work.pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(clk160, pathENA, pathENAtrig);
---------------------------------------------
-- CLK2:
---------------------------------------------
--
DIN_RDY_r <= (DIN_RDY_s and (not truncateDataFlag)) or truncation_from_timeout_trig; --and pathENA; --blockCountRdy;
DIN_r <= DIN_s(7 downto 0);
--
process(direct_data_mode, direct_data_boundary_detected, DIN_s(9 downto 8), truncateDataFlag)
begin
if direct_data_mode = '1' then
DIN_CODE_r <= direct_data_boundary_detected & '0'; -- "10"=soc, "00"=data
else
if truncateDataFlag = '0' then
DIN_CODE_r <= DIN_s(9 downto 8);
else
DIN_CODE_r <= "00";
end if;
end if;
end process;
--
-----------------------------------------------------------
-- clock 3
-- case of the input word code:
-- "00" => data, "01" => EOC, "10" => SOC, "11" => COMMA
-----------------------------------------------------------
process(clk160, rst)
begin
if rst = '1' then
--
receiving_state <= '0';
trailer_trunc_bit <= '1';
trailer_cerr_bit <= '1';
trailer_type_bits <= "000"; -- not a legal code
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
truncating_state <= '0';
--
elsif rising_edge (clk160) then
if DIN_RDY_r = '1' then
case (DIN_CODE_r) is
when "00" => -- data
--
data_shift_trig <= (receiving_state) and (not truncateDataFlag); -- shift-in data if in the receiving state
-- if block filled up after that, chunk trailer and block header will be shifted-in as well
trailer_trunc_bit <= truncateDataFlag; -- truncation mark in case of CLEN_error
trailer_cerr_bit <= truncateDataFlag; -- CLEN_error is '1' in case of receiving data after CLEN is reached
trailer_type_bits <= (not (truncateDataFlag or first_subchunk)) & truncateDataFlag & first_subchunk; -- 001_first, 011_whole, 100_middle, 010_last
trailer_shift_trig <= truncateDataFlag and receiving_state; -- send a trailer once when CLEN value is reached (SOC will rst the chunk-len-counter)
receiving_state <= receiving_state and (not truncateDataFlag); -- switching off receiving in case of truncateDataFlag, waiting for SOC now
EOC_error <= '0';
SOC_error <= not receiving_state; -- if current state is not 'receiving', flag an error, do nothing
rst_clen_counter <= '0';
first_subchunk_on <= '0';
truncating_state <= truncateDataFlag and receiving_state; -- truncation trailer is sent in this 'case' (once)
--
when "01" => -- EOC
--
trailer_shift_trig <= receiving_state or do_transmit_timeout_trailers; -- if '1' => correct state, shift-in a trailer, if not, do nothing
-- sending a trailer is including padding with zeros ('flush') in case of even word count (should be flagged somewhere...)
trailer_trunc_bit <= '0'; -- no truncation, proper ending
trailer_cerr_bit <= '0';
trailer_type_bits <= do_transmit_timeout_trailers & '1' & first_subchunk; -- 'last sub-chunk' or 'whole sub-chunk' mark
EOC_error <= not receiving_state; -- if current state was not 'receiving', flag an error, do nothing
receiving_state <= '0';
--
truncating_state <= truncating_state;
rst_clen_counter <= '0';
first_subchunk_on <= '0';
data_shift_trig <= '0';
SOC_error <= '0';
--
when "10" => -- SOC
--
trailer_shift_trig <= (receiving_state and (not direct_data_mode)) or (truncateDataFlag and (not truncation_trailer_sent)); -- if '1' => incorrect state, shift-in a trailer to finish the unfinished chunk
-- sending a trailer is including padding with zeros ('flush') in case of even word count (should be flagged somewhere...)
trailer_trunc_bit <= '1'; -- truncation mark in case of sending a trailer (this is when EOC was not received)
trailer_cerr_bit <= '1';
trailer_type_bits <= "01" & (first_subchunk or truncateDataFlag); -- 'last sub-chunk' or 'whole sub-chunk' mark
SOC_error <= receiving_state; -- if current state was already 'receiving', flag an error
receiving_state <= not truncateDataFlag; --'1';
rst_clen_counter <= '1';
first_subchunk_on <= '1';
truncating_state <= truncateDataFlag and (not truncation_trailer_sent); -- truncation trailer is sent in this 'case' (once)
--
data_shift_trig <= '0';
EOC_error <= '0';
--
when "11" => -- COMMA
--
-- do nothing
receiving_state <= receiving_state;
truncating_state <= truncating_state;
trailer_trunc_bit <= '0';
trailer_cerr_bit <= '0';
trailer_type_bits <= "000";
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
--
when others =>
end case;
else
receiving_state <= receiving_state;
trailer_trunc_bit <= trailer_trunc_bit;
trailer_cerr_bit <= trailer_cerr_bit;
trailer_type_bits <= trailer_type_bits; --"000";
truncating_state <= truncating_state;
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
end if;
end if;
end process;
-----------------------------------------------------------
-- truncation trailer should be only sent once (the first one)
-----------------------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if truncateDataFlag = '0' then
truncation_trailer_sent <= '0';
else -- truncateDataFlag = '1':
if trailer_shift_trig = '1' then
truncation_trailer_sent <= '1'; -- latch, send only one truncation trailer
end if;
end if;
end if;
end process;
--
-----------------------------------------------------------
-- clock3, writing to the shift register
-- data8bit ready pulse
-----------------------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then -- first, try to flush the shift register
trailer_shift_trig_s <= trailer_shift_trig and (not EOB_MARK); -- this trailer is a result of {eoc} or {soc without eoc} or {max clen violation}
end if;
end process;
--
send_trailer_trig <= trailer_shift_trig_s or EOB_MARK; -- or truncation_from_timeout_trig;
data_shift_trig_s <= data_shift_trig;
flush_trig <= trailer_shift_trig;-- and (not truncateDataFlag); -- no need for flush in truncation case
--
DATA_shift_r: entity work.reg8to16bit -- only for data or 'flush' padding
PORT MAP(
rst => rst,
clk => clk160,
flush => flush_trig, --trailer_shift_trig,
din => DIN_r,
din_rdy => data_shift_trig_s,
-----
flushed => flushed,
dout => data,
dout_rdy => data_rdy
);
-----------------------------------------------------------
-- clock
-- BLOCK_WORD_COUNTER
-----------------------------------------------------------
BLOCK_WORD_COUNTER_inst: entity work.BLOCK_WORD_COUNTER
generic map (GBTid=>GBTid, egroupID=>egroupID, epathID=>epathID)
port map (
CLK => clk160,
RESET => rst,
RESTART => pathENAtrig,
BW_RDY => data16bit_rdy, -- counts everything that is written to EPROC FIFO
EOB_MARK => EOB_MARK, -- End-Of-Block: 'send the chunk trailer' trigger
BLOCK_HEADER_OUT => header,
BLOCK_HEADER_OUT_RDY => header_shift_trigs,
BLOCK_COUNT_RDY => blockCountRdy
);
--
process(clk160)
begin
if rising_edge (clk160) then
if first_subchunk_on = '1' or rst = '1' then
first_subchunk <= '1';
elsif EOB_MARK = '1' then
first_subchunk <= '0';
end if;
end if;
end process;
-----------------------------------------------------------
-- Sub-Chunk Data manager
-- sends a trailer in 2 clocks (current clock and the next)
-----------------------------------------------------------
--
trailer_mod_bits <= trailer_trunc_bit & trailer_cerr_bit;
--
SCDataMANAGER_inst: entity work.SCDataMANAGER
PORT MAP(
CLK => clk160,
rst => rst,
xoff => xoff_s,
maxCLEN => maxCLEN,
rstCLENcount => rst_clen_counter,
truncateCdata => truncateDataFlag, -- out, next data will be truncated, a trailer will be sent instead
trailerMOD => trailer_mod_bits, -- in, keeps its value till the next DIN_RDY_s
trailerTYPE => trailer_type_bits, -- in, keeps its value till the next DIN_RDY_s
trailerRSRVbit => xoff_s,
-------
trailerSENDtrig => send_trailer_trig,
dataCNTena => data_shift_trig_s, -- counts data Bytes (not 16-bit words)data_rdy, -- counts only data (or 'flush' padding), no header, no trailer
-------
trailerOUT => trailer0,
trailerOUTrdy => trailer_shift_trig0
);
--
--
process(clk160)
begin
if rising_edge (clk160) then
trailer_shift_trig1 <= flushed;
trailer1 <= trailer0;
end if;
end process;
--
trailer_shift_trigs <= (trailer_shift_trig0 and (not flushed)) or trailer_shift_trig1;
--
process(trailer_shift_trig1, trailer1, trailer0)
begin
if trailer_shift_trig1 = '1' then
trailer <= trailer1;
else
trailer <= trailer0;
end if;
end process;
-----------------------------------------------------------
-- 16 bit output MUX, goes to a EPROC FIFO
-----------------------------------------------------------
--process(clk160)
--begin
-- if clk160'event and clk160 = '0' then
-- data16bit_rdy_shifted <= data16bit_rdy;
-- end if;
--end process;
--
data16bit_rdy <= data_rdy or trailer_shift_trigs or header_shift_trigs or timeout_trailer_send or zero_trailer_send_pulse;
data16bit_rdy_code(0) <= (not trailer_shift_trigs) and (data_rdy xor header_shift_trigs);
data16bit_rdy_code(1) <= (not header_shift_trigs) and (data_rdy xor trailer_shift_trigs);
data16bit_rdy_code(2) <= do_transmit_timeout_trailers;
--
--process(data16bit_rdy_code, data, header, trailer)
process(clk160)
begin
if rising_edge (clk160) then
case (data16bit_rdy_code) is
when "001" => -- header
wordOUT_s <= header;
when "010" => -- trailer
wordOUT_s <= trailer;
when "011" => -- data
wordOUT_s <= data;
when "100" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "101" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "110" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "111" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when others =>
--wordOUT_s <= (others => '0');
end case;
end if;
end process;
--
--
process(clk160)
begin
if rising_edge (clk160) then
if do_transmit_timeout_trailers = '0' then
zero_trailer_send_pulse_count <= (others=>'0');
else
zero_trailer_send_pulse_count <= zero_trailer_send_pulse_count + 1;
end if;
end if;
end process;
--
zero_trailer_send_pulse <= '1' when (zero_trailer_send_pulse_count = "111") else '0';
--
--
process(clk160)
begin
if rising_edge (clk160) then
if rst = '1' then
wordOUT_RDY <= '0';
else
wordOUT_RDY <= data16bit_rdy;-- or data16bit_rdy_shifted;
end if;
end if;
end process;
--
wordOUT <= wordOUT_s;
end Behavioral;
| gpl-3.0 | 0f73677cb7536c111958f38ded3a7168 | 0.510153 | 3.88588 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/rsa_512/trunk/rtl/pe_wrapper.vhd | 1 | 4,609 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:08:19 10/29/2009
-- Design Name:
-- Module Name: montgomery - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pe_wrapper is
port(
clk : in std_logic;
reset : in std_logic;
ab_valid : in std_logic;
valid_in : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
n : in std_logic_vector(15 downto 0);
s_prev : in std_logic_vector(15 downto 0);
n_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector( 15 downto 0);
data_ready : out std_logic;
fifo_req : out std_logic;
m_val : out std_logic;
reset_the_PE : in std_logic); -- estamos preparados para aceptar el siguiente dato
end pe_wrapper;
architecture Behavioral of pe_wrapper is
component pe is
port ( clk : in std_logic;
reset : in std_logic;
a_j : in std_logic_vector(15 downto 0);
b_i : in std_logic_vector(15 downto 0);
s_prev : in std_logic_vector(15 downto 0); --entrada de la s anterior para la suma
m : in std_logic_vector(15 downto 0);
n_j : in std_logic_vector(15 downto 0);
s_next : out std_logic_vector(15 downto 0); --salida con la siguiente s
aj_bi : out std_logic_vector(15 downto 0); --salida de multiplicador reutilizado para calcular a*b
ab_valid_in : in std_logic; --indica que los datos de entrada en el multiplicador son validos
valid_in : in std_logic; --todas las entradas son validas, y la m está calculada
ab_valid_out : out std_logic; --indica que la multiplicacion de un a y b validos se ha realizado con exito
valid_out : out std_logic;
fifo_req : out std_logic);
end component;
component m_calc is
port(
clk : in std_logic;
reset : in std_logic;
ab : in std_logic_vector (15 downto 0);
t : in std_logic_vector (15 downto 0);
n_cons : in std_logic_vector (15 downto 0);
m : out std_logic_vector (15 downto 0);
mult_valid : in std_logic;
m_valid : out std_logic);
end component;
signal aj_bi, m, next_m, m_out : std_logic_vector(15 downto 0);
signal mult_valid, valid_m, valid_m_reg : std_logic; --lo registro para compararlos
begin
pe_0 : pe port map(
clk => clk,
reset => reset,
a_j => a,
b_i => b,
s_prev => s_prev,
m => m,
n_j => n,
s_next => s,
aj_bi => aj_bi,
ab_valid_in => ab_valid,
valid_in => valid_in,
ab_valid_out => mult_valid,
valid_out => data_ready,
fifo_req => fifo_req);
mcons_0 : m_calc port map(
clk => clk,
reset => reset,
ab => aj_bi,
t => s_prev,
n_cons => n_c,
m => m_out,
mult_valid => mult_valid,
m_valid => valid_m);
process(clk, reset)
begin
if(clk = '1' and clk'event) then
if(reset = '1')then
m <= (others => '0' );
valid_m_reg <= '0';
else
m <= next_m;
valid_m_reg <= valid_m;
end if;
end if;
end process;
process(m_out, valid_m, valid_m_reg, m)
begin
m_val <= valid_m_reg;
if(valid_m = '1' and valid_m_reg = '0') then
next_m <= m_out;
else
next_m <= m;
end if;
end process;
end Behavioral;
| bsd-3-clause | 60d7101a1db4e4d9fefa487f45b96da3 | 0.472771 | 3.68131 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/EPROC_IN2_DEC8b10b.vhd | 2 | 6,320 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
use work.centralRouter_package.all;
--! 8b10b decoder for EPROC_IN2 module
entity EPROC_IN2_DEC8b10b is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (1 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
busyOut : out std_logic
);
end EPROC_IN2_DEC8b10b;
architecture Behavioral of EPROC_IN2_DEC8b10b is
signal EDATAbitstreamSREG : std_logic_vector (11 downto 0) := (others=>'0'); -- 12 bit (2 x 5 = 10, plus 2 more)
signal word10b_align_array, word10b_align_array_r : word10b_2array_type;
signal word10b, word10b_s : std_logic_vector (9 downto 0) := (others=>'0');
signal isk : std_logic_vector (1 downto 0) := (others=>'0');
signal comma_valid_bits_or, word10b_align_rdy_r,
word10b_rdy, word10b_rdy_s, word10b_rdy_s1 : std_logic;
signal align_select : std_logic := '0';
signal comma_valid_bits : std_logic_vector (1 downto 0);
signal alignment_sreg : std_logic_vector (4 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- input shift register
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
EDATAbitstreamSREG <= (others => '0');
elsif bitCLK'event and bitCLK = '1' then
EDATAbitstreamSREG <= edataIN & EDATAbitstreamSREG(11 downto 2);
end if;
end process;
-------------------------------------------------------------------------------------------
--clock0
-- input shift register mapping into 10 bit registers
-------------------------------------------------------------------------------------------
input_map: for I in 0 to 1 generate -- 1 10bit-word per alignment, 2 possible alignments
--word10b_align_array(I) <= EDATAbitstreamSREG((I+9) downto (I+0)); -- 10 bit word, alligned to bit I
word10b_align_array(I) <= EDATAbitstreamSREG(I+0)&EDATAbitstreamSREG(I+1)&EDATAbitstreamSREG(I+2)&EDATAbitstreamSREG(I+3)&EDATAbitstreamSREG(I+4)&
EDATAbitstreamSREG(I+5)&EDATAbitstreamSREG(I+6)&EDATAbitstreamSREG(I+7)&EDATAbitstreamSREG(I+8)&EDATAbitstreamSREG(I+9); -- 10 bit word, alligned to bit I
end generate input_map;
-------------------------------------------------------------------------------------------
--clock0
-- K28.5 comma test
-------------------------------------------------------------------------------------------
comma_test: for I in 0 to 1 generate -- 1 10bit-word per alignment, comma is valid if two first words have comma...
comma_valid_bits(I) <= '1' when (word10b_align_array(I) = COMMAp or word10b_align_array(I) = COMMAn) else '0';
end generate comma_test;
--
comma_valid_bits_or <= comma_valid_bits(1) or comma_valid_bits(0);
--
-------------------------------------------------------------------------------------------
--clock1
-- alignment selector state
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
alignment_sreg <= "00000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
alignment_sreg <= "10000";
else
alignment_sreg <= alignment_sreg(0) & alignment_sreg(4 downto 1);
end if;
end if;
end process;
--
input_reg1: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_align_array_r <= word10b_align_array;
end if;
end process;
--
word10b_align_rdy_r <= alignment_sreg(4);
--
process(bitCLK, rst)
begin
if rst = '1' then
align_select <= '0';
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
align_select <= (not comma_valid_bits(0)) and comma_valid_bits(1);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock2
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg2: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_rdy <= word10b_align_rdy_r;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case (align_select) is
when '0' => -- bit0 word got comma => align to bit0
word10b <= word10b_align_array_r(0);
when '1' => -- bit1 word got comma => align to bit1
word10b <= word10b_align_array_r(1);
when others =>
end case;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------------
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_s <= word10b;
word10b_rdy_s <= word10b_rdy;
end if;
end process;
--
word10b_rdy_s1 <= word10b_rdy_s;
----
-------------------------------------------------------------------------------------------
-- 1 8b word get aligned and ready as 10 bit word (data and data code)
-------------------------------------------------------------------------------------------
EPROC_IN2_ALIGN_BLOCK_inst: entity work.EPROC_IN2_ALIGN_BLOCK
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst,
bytes => word10b_s,
bytes_rdy => word10b_rdy_s1,
dataOUT => dataOUT,
dataOUTrdy => dataOUTrdy,
busyOut => busyOut
);
end Behavioral;
| gpl-3.0 | 4be341b8d6a00dd245d3c1db77fe8a03 | 0.469146 | 3.9599 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/EPROC_IN2.vhd | 1 | 4,824 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! E-link processor, 2bit input
entity EPROC_IN2 is
generic (do_generate : boolean := true);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
swap_inputbits : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (1 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN2;
architecture Behavioral of EPROC_IN2 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
--
signal edata_in_s : std_logic_vector (1 downto 0);
--
signal DATA_OUT_direct : std_logic_vector (9 downto 0);
signal DATA_RDY_direct : std_logic;
---
signal DATA_OUT_8b10b_decoded : std_logic_vector (9 downto 0);
signal DATA_RDY_8b10b_decoded : std_logic;
---
signal DATA_OUT_HDLC_decoded : std_logic_vector (9 downto 0);
signal DATA_RDY_HDLC_decoded : std_logic;
---
signal DATA_RDY_sig : std_logic;
signal DATA_OUT_s : std_logic_vector (9 downto 0);
signal RESTART_sig, rst_case00, rst_case01, rst_case10 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
--
in_sel: process(swap_inputbits,EDATA_IN)
begin
if swap_inputbits = '1' then
edata_in_s <= EDATA_IN(0) & EDATA_IN(1);
else
edata_in_s <= EDATA_IN;
end if;
end process;
--
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
rst_case00 <= '0' when ((RESTART_sig = '0') and (ENCODING = "00")) else '1';
--
direct_data_case: entity work.EPROC_IN2_direct
port map(
bitCLK => bitCLK,
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => edata_in_s,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= '0' when ((RESTART_sig = '0') and (ENCODING = "01")) else '1';
--
dec8b10b_case: entity work.EPROC_IN2_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => edata_in_s,
dataOUT => DATA_OUT_8b10b_decoded,
dataOUTrdy => DATA_RDY_8b10b_decoded,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
rst_case10 <= '0' when ((RESTART_sig = '0') and (ENCODING = "10")) else '1';
--
decHDLC_case: entity work.EPROC_IN2_HDLC
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case10,
edataIN => edata_in_s,
dataOUT => DATA_OUT_HDLC_decoded,
dataOUTrdy => DATA_RDY_HDLC_decoded
);
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_decoded,
data2 => DATA_OUT_HDLC_decoded,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_decoded,
data2 => DATA_RDY_HDLC_decoded,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 | f85290ee4e8761684d9c2ecc12d69ec5 | 0.475539 | 3.63253 | false | false | false | false |
qynvi/rtl-doorlock | doorlock.vhd | 1 | 5,245 | -- William Fan
-- 02/14/2011
-- RTL for a door locking asic
-- Base Features:
-- * Idle LED Red
-- * Unlock LED Green
-- * Accepts any 3 inputs, then unlocks on specific correct sequence
-- * Automatic re-idle, code entry time limit of 3 seconds total
-- Additional Features:
-- * Software reset and wrong input LED
-- * Never goes idle if button is held down
-- * Supports simultaneous keypresses
-- * Supports separate keypress and unlock time limit windows
library ieee;
use ieee.std_logic_1164.all;
entity doorlock is
generic (
-- set a modular time limit for key entry
tlimit: integer := 150_000_000; -- 3 seconds
-- set the amount of time it stays unlocked
ulimit: integer := 150_000_000; -- 3 seconds
-- use a bit vector to mask the buttons, 1(switch)-2-3-4-5
-- the right code sequence is 4-3-2 on the lock and can be modified as a generic here
secret1: std_logic_vector(4 downto 0) := "01101";
secret2: std_logic_vector(4 downto 0) := "01011";
secret3: std_logic_vector(4 downto 0) := "00111";
nokey: std_logic_vector(4 downto 0) := "01111");
port (clk,rst,key1,key2,key3,key4,key5: in std_logic;
led_idle,led_unlock,led_reset: out std_logic);
end doorlock;
architecture dl of doorlock is
type state is (idle,wait1,push2,wait2,push3,wait3,verify,reset,unlock);
signal pr_state,nx_state: state;
attribute enum_encoding: string;
attribute enum_encoding of state: type is "sequential";
signal kp: std_logic_vector(4 downto 0);
shared variable cv: natural range 0 to tlimit := 1;
shared variable kcounter: natural range 0 to tlimit := 0;
begin
kp <= (key1 & key2 & key3 & key4 & key5);
process (clk,rst)
begin
if (rst='1') then
pr_state <= idle;
kcounter := 0;
elsif (clk'event and clk='1') then
kcounter := kcounter + 1;
if (kcounter>=cv) then
pr_state <= nx_state;
kcounter := 0;
end if;
end if;
end process;
process (pr_state,kp)
-- Need to wait to tell the user they are wrong no matter
-- what three buttons they press therefore track with
-- three variables, masked with the input, using a
-- temporary buffer vector
variable input1: std_logic_vector(4 downto 0) := "00000";
variable input2: std_logic_vector(4 downto 0) := "00000";
variable input3: std_logic_vector(4 downto 0) := "00000";
variable temp: std_logic_vector(4 downto 0);
begin
case pr_state is
when idle =>
led_idle <= '1';
led_unlock <= '0';
led_reset <= '0';
cv := tlimit;
if (kp/=nokey) then
-- immediately store the keypress
temp := kp;
cv := 0;
nx_state <= wait1;
else
nx_state <= idle;
end if;
when wait1 =>
cv := tlimit;
led_idle <= '0';
led_unlock <= '0';
led_reset <= '0';
if (kp=nokey) then
-- store input iff user releases the key
input1 := temp;
-- force next state
cv := 0;
nx_state <= push2;
elsif (kp=temp) then
-- if they're spamming the button, loop the wait state
cv := 0;
nx_state <= wait1;
else
-- if somehow the debouncer failed, default return to idle after a while
nx_state <= reset;
end if;
when push2 =>
led_idle <= '0';
led_unlock <= '0';
led_reset <= '0';
cv := tlimit;
if (kp/=nokey) then
temp := kp;
cv := 0;
nx_state <= wait2;
else
nx_state <= reset;
end if;
when wait2 =>
led_idle <= '0';
led_unlock <= '0';
led_reset <= '0';
cv := tlimit;
if (kp=nokey) then
input2 := temp;
cv := 0;
nx_state <= push3;
elsif (kp=temp) then
cv := 0;
nx_state <= wait2;
else
nx_state <= reset;
end if;
when push3 =>
led_idle <= '0';
led_unlock <= '0';
led_reset <= '0';
cv := tlimit;
if (kp/=nokey) then
temp := kp;
cv := 0;
nx_state <= wait3;
else
nx_state <= reset;
end if;
when wait3 =>
led_idle <= '0';
led_unlock <= '0';
led_reset <= '0';
cv := tlimit;
if (kp=nokey) then
input3 := temp;
cv := 0;
nx_state <= verify;
elsif (kp=temp) then
cv := 0;
nx_state <= wait3;
else
nx_state <= reset;
end if;
when verify =>
led_idle <= '0';
led_unlock <= '0';
led_reset <= '0';
cv := tlimit;
-- this is the easiest way to check the code without imposing
-- a limit on how long the CPU can take to evaluate the inputs
if (input3=secret3) then
if (input2=secret2) then
if (input1=secret1) then
cv := 0;
nx_state <= unlock;
else
cv := 0;
nx_state <= reset;
end if;
else
cv := 0;
nx_state <= reset;
end if;
else
cv := 0;
nx_state <= reset;
end if;
when reset =>
led_idle <= '0';
led_unlock <= '0';
led_reset <= '1';
cv := tlimit;
nx_state <= idle;
when unlock =>
led_idle <= '0';
led_unlock <= '1';
led_reset <= '0';
cv := ulimit;
nx_state <= reset;
end case;
end process;
end architecture;
| mit | 8a07c6ae041cb94e45db51a96ef983b4 | 0.55939 | 3.098051 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/Testbenches/USB_tb.vhd | 1 | 8,880 | --Copyright 2017 Christoffer Mathiesen
---Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
---
---1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
---
---2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
---documentation and/or other materials provided with the distribution.
---
---3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
---software without specific prior written permission.
---
---THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
---THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
---BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
---GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
---LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_MISC.all;
use IEEE.NUMERIC_STD.all;
Entity USB_tb is
end USB_tb;
---This testbench shows a simple write request followed up by a read request.
---The data is not encrypted in this tb
---The tb is self-testing, but the main purpose of it is to make
---waveforms so that you can check your own implementation
---It should be possible to use this code for testing if other frequencies/baud rates
---are faulty.
Architecture behavioral of USB_tb is
constant BAUD_RATE : integer := 115200; --baud of 115200
constant CLOCK_RATE : integer := 100_000_000; --100MHz (10 ns)
Component USB_TOP is
generic ( data_addr_width : integer := 6;
BAUD_RATE : integer := BAUD_RATE; --baud of 115200
CLOCK_RATE : integer := CLOCK_RATE; --100MHz (10 ns)
OVERSAMPLES : integer := 4);
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
TXD : out STD_LOGIC;
RXD : in STD_LOGIC;
RAM_ADDR : out STD_LOGIC_VECTOR (data_addr_width-1 downto 0);
RAM_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
RAM_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0);
RAM_WE : out STD_LOGIC;
READY_FOR_DATA : in STD_LOGIC;
RSA_DONE : in STD_LOGIC;
DATA_READY : out STD_LOGIC);
end component;
Component mem_array is
GENERIC(
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 6);
Port(
ADDR : in STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
DATAIN : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
clk : in std_logic;
WE : in std_logic;
OUTPUT : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0)
);
end component;
constant ASCII_ASTERISK : STD_LOGIC_VECTOR(7 downto 0) := x"2A"; --*
constant ASCII_B : STD_LOGIC_VECTOR(7 downto 0) := x"42"; --B
constant ASCII_D : STD_LOGIC_VECTOR(7 downto 0) := x"44"; --D
constant ASCII_E : STD_LOGIC_VECTOR(7 downto 0) := x"45"; --E
constant ASCII_H : STD_LOGIC_VECTOR(7 downto 0) := x"48"; --H
constant ASCII_J : STD_LOGIC_VECTOR(7 downto 0) := x"4A"; --J
constant ASCII_W : STD_LOGIC_VECTOR(7 downto 0) := x"57"; --W
constant ASCII_R : STD_LOGIC_VECTOR(7 downto 0) := x"52"; --R
constant ASCII_M : STD_LOGIC_VECTOR(7 downto 0) := x"4D"; --M
constant ASCII_I : STD_LOGIC_VECTOR(7 downto 0) := x"49"; --I
constant ASCII_T : STD_LOGIC_VECTOR(7 downto 0) := x"54"; --T
constant clk_period : time := 1 sec * 1/CLOCK_RATE;
constant bit_period : time := clk_period*CLOCK_RATE/BAUD_RATE;
signal bool : boolean := true;
Signal TXD_PIN, RXD_PIN, READY_FOR_DATA, RSA_DONE, DATA_READY, CLK, RESET, RAM_WE : STD_LOGIC := '0';
Signal RAM_DATA_IN, RAM_DATA_OUT : STD_LOGIC_VECTOR(7 downto 0);
Signal RAM_ADDR : STD_LOGIC_VECTOR(5 downto 0);
signal done : std_logic := '0';
signal tst_data : STD_LOGIC_VECTOR(7 downto 0);
signal TMP : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
test_USB_TOP: USB_TOP Port Map(CLK => CLK,
RESET => RESET,
TXD => TXD_PIN,
RXD => RXD_PIN,
RAM_ADDR => RAM_ADDR,
RAM_DATA_IN => RAM_DATA_OUT,
RAM_DATA_OUT => RAM_DATA_IN,
RAM_WE => RAM_WE,
READY_FOR_DATA => READY_FOR_DATA,
RSA_DONE => RSA_DONE,
DATA_READY => DATA_READY);
test_RAM: mem_array Port Map (
ADDR => RAM_ADDR,
DATAIN => RAM_DATA_IN,
clk => clk,
WE => RAM_WE,
OUTPUT => RAM_DATA_OUT
);
--Create the clock
process
begin
CLK <= NOT CLK;
wait for clk_period/2;
end process;
--Main test process
process
begin
--first reset the circuits
reset <= '1';
RXD_PIN <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period;
--Set so that we can get, but not send data.
READY_FOR_DATA <= '1';
RSA_DONE <= '0';
--Start transmission into the circuit
RXD_PIN <= '0'; --start bit
wait for bit_period; --time it takes to transmit one bit with 100MHz and 115200 baud
--Send *
for I in 0 to 7 loop
RXD_PIN <= ASCII_ASTERISK(I);
wait for bit_period;
end loop;
RXD_PIN <= '1'; --stop bit
wait for bit_period*2;
RXD_PIN <= '0'; --start bit
wait for bit_period;
--Send W
for I in 0 to 7 loop
RXD_PIN <= ASCII_W(I);
wait for bit_period;
end loop;
RXD_PIN <= '1'; --stop bit
wait for bit_period;
--send 64 bytes of data. Use the tst_data and dec by 1 each itteration
for I in 0 to 63 loop
TMP <= STD_LOGIC_VECTOR(to_unsigned(I,8));
RXD_PIN <= '0'; --start bit
wait for bit_period;
--send the data
for J in 0 to 7 loop
RXD_PIN <= TMP(J);
if I < 63 or J < 7 then --last time we can't wait as we need to check the RAM
wait for bit_period;
end if;
end loop;
if I = 63 then
wait until RAM_WE = '0';
wait for clk_period;
end if;
RXD_PIN <= '1'; --stop bit
--report errors
assert RAM_DATA_OUT = TMP
report "The value put to memory is not the same as the one written on the RXD_PIN!"
severity error;
wait for bit_period;
end loop;
--Now we should have values in the memory. Simulate that we have encrypted them by setting flags
READY_FOR_DATA <= '0';
RSA_DONE <= '1';
--Send request *R
wait for bit_period * 25;
RXD_PIN <= '0'; --start bit
wait for bit_period*1; --time it takes to transmit one bit with 100MHz and 115200 baud
--Send *
for I in 0 to 7 loop
RXD_PIN <= ASCII_ASTERISK(I);
wait for bit_period;
end loop;
RXD_PIN <= '1'; --stop bit
wait for bit_period;
RXD_PIN <= '0'; --start bit
wait for bit_period;
--Send R
for I in 0 to 7 loop
RXD_PIN <= ASCII_R(I);
if I < 7 then
wait for bit_period;
end if;
end loop;
--wait for clk_period;
--Now it should start reading the memory, put it into the FIFO and then the TXD will start transmitting
wait until TXD_PIN = '0'; --wait until the start bit on TXD
RXD_PIN <= '1'; --stop bit
wait for bit_period*3/2; --set to halfway into a bit-transmission
for J in 0 to 7 loop
tst_data(J) <= TXD_PIN;
wait for bit_period;
end loop;
assert tst_data = ASCII_ASTERISK
report "The first character sent is not '*'!"
severity error;
wait until TXD_PIN = '0';
wait for bit_period*3/2;
for J in 0 to 7 loop
tst_data(J) <= TXD_PIN;
wait for bit_period;
end loop;
assert tst_data = ASCII_M
report "The second character sent is not 'M'!"
severity error;
wait until TXD_PIN = '0';
wait for bit_period*3/2;
for I in 0 to 63 loop
TMP <= STD_LOGIC_VECTOR(to_unsigned(I,8));
--send the data
for J in 0 to 7 loop
tst_data(J) <= TXD_PIN;
wait for bit_period;
end loop;
bool <= to_integer(unsigned(tst_data)) = to_integer(unsigned(tmp));
wait for 0 ns; --update bool
--report errors
assert bool
report "The value out from TXD_PIN is not the same as the one written previously!"
severity error;
if I < 63 then
wait until TXD_PIN = '0'; --Wait for start bit
wait for bit_period*3/2;
end if;
end loop;
done <= '1';
wait for clk_period;
report "Testbench complete! If no errors, run was successful!" severity FAILURE;
wait;
end process;
--timeout
process
begin
wait for 5000*bit_period;
report "Testbench failed! Something hanged!" severity failure;
wait;
end process;
end behavioral;
| bsd-3-clause | 8801ba1d62b982b5efb62cb793f8a14e | 0.65259 | 3.370019 | false | false | false | false |
EltonBroering/Estacionamento-Inteligente-com-portas-logicas | Central2.vhd | 1 | 24,172 | -- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 32-bit"
-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
-- CREATED "Thu May 22 09:35:24 2014"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY Central2 IS
PORT
(
Vaga4 : IN STD_LOGIC;
Vaga5 : IN STD_LOGIC;
Vaga6 : IN STD_LOGIC;
Vaga7 : IN STD_LOGIC;
Vaga8 : IN STD_LOGIC;
Vaga9 : IN STD_LOGIC;
Vaga12 : IN STD_LOGIC;
Vaga13 : IN STD_LOGIC;
Vaga14 : IN STD_LOGIC;
Vaga15 : IN STD_LOGIC;
VagaD1 : IN STD_LOGIC;
Vaga16 : IN STD_LOGIC;
Vaga17 : IN STD_LOGIC;
Vaga18 : IN STD_LOGIC;
Vaga19 : IN STD_LOGIC;
Vaga20 : IN STD_LOGIC;
Vaga21 : IN STD_LOGIC;
Vaga22 : IN STD_LOGIC;
Vaga23 : IN STD_LOGIC;
Vaga24 : IN STD_LOGIC;
Vaga25 : IN STD_LOGIC;
Vaga26 : IN STD_LOGIC;
Vaga27 : IN STD_LOGIC;
Vaga28 : IN STD_LOGIC;
Vaga29 : IN STD_LOGIC;
Vaga30 : IN STD_LOGIC;
VagaD2 : IN STD_LOGIC;
Vaga31 : IN STD_LOGIC;
Vaga32 : IN STD_LOGIC;
Vaga33 : IN STD_LOGIC;
Vaga34 : IN STD_LOGIC;
Vaga35 : IN STD_LOGIC;
Vaga36 : IN STD_LOGIC;
Vaga37 : IN STD_LOGIC;
Vaga38 : IN STD_LOGIC;
Vaga39 : IN STD_LOGIC;
Vaga40 : IN STD_LOGIC;
Vaga41 : IN STD_LOGIC;
Vaga42 : IN STD_LOGIC;
Vaga43 : IN STD_LOGIC;
Vaga44 : IN STD_LOGIC;
Vaga45 : IN STD_LOGIC;
VagaD3 : IN STD_LOGIC;
Vaga46 : IN STD_LOGIC;
Vaga47 : IN STD_LOGIC;
Vaga48 : IN STD_LOGIC;
Vaga49 : IN STD_LOGIC;
Vaga50 : IN STD_LOGIC;
Vaga51 : IN STD_LOGIC;
Vaga52 : IN STD_LOGIC;
Vaga53 : IN STD_LOGIC;
Vaga54 : IN STD_LOGIC;
Vaga55 : IN STD_LOGIC;
Vaga56 : IN STD_LOGIC;
Vaga57 : IN STD_LOGIC;
Vaga58 : IN STD_LOGIC;
Vaga59 : IN STD_LOGIC;
Vaga60 : IN STD_LOGIC;
VagaD4 : IN STD_LOGIC;
Vaga1 : IN STD_LOGIC;
Vaga2 : IN STD_LOGIC;
Vaga3 : IN STD_LOGIC;
vaga10 : IN STD_LOGIC;
Vaga11 : IN STD_LOGIC;
Led_Vaga1 : OUT STD_LOGIC;
Led_Vaga2 : OUT STD_LOGIC;
Led_Vaga3 : OUT STD_LOGIC;
Led_Vaga4 : OUT STD_LOGIC;
Led_Vaga5 : OUT STD_LOGIC;
Led_Vaga6 : OUT STD_LOGIC;
Led_Vaga7 : OUT STD_LOGIC;
Led_Vaga8 : OUT STD_LOGIC;
Led_Vaga9 : OUT STD_LOGIC;
Led_Vaga10 : OUT STD_LOGIC;
Led_Vaga11 : OUT STD_LOGIC;
Led_Vaga12 : OUT STD_LOGIC;
Led_Vaga13 : OUT STD_LOGIC;
Led_Vaga14 : OUT STD_LOGIC;
Led_Vaga15 : OUT STD_LOGIC;
Led_Vaga_Deficiente : OUT STD_LOGIC;
display_dezena : OUT STD_LOGIC;
Led_Vaga16 : OUT STD_LOGIC;
Led_Vaga17 : OUT STD_LOGIC;
Led_Vaga18 : OUT STD_LOGIC;
Led_Vaga19 : OUT STD_LOGIC;
Led_Vaga20 : OUT STD_LOGIC;
Led_Vaga21 : OUT STD_LOGIC;
Led_Vaga22 : OUT STD_LOGIC;
Led_Vaga23 : OUT STD_LOGIC;
Led_Vaga24 : OUT STD_LOGIC;
Led_Vaga25 : OUT STD_LOGIC;
Led_Vaga26 : OUT STD_LOGIC;
Led_Vaga27 : OUT STD_LOGIC;
Led_Vaga28 : OUT STD_LOGIC;
Led_Vaga29 : OUT STD_LOGIC;
Led_Vaga30 : OUT STD_LOGIC;
Led_Vaga_Deficiente2 : OUT STD_LOGIC;
display_unidade_12 : OUT STD_LOGIC;
display_unidade_22 : OUT STD_LOGIC;
display_unidade_32 : OUT STD_LOGIC;
display_unidade_42 : OUT STD_LOGIC;
display_dezena2 : OUT STD_LOGIC;
display_unidade_11 : OUT STD_LOGIC;
display_unidade_21 : OUT STD_LOGIC;
display_unidade_31 : OUT STD_LOGIC;
display_unidade_41 : OUT STD_LOGIC;
Led_Vaga31 : OUT STD_LOGIC;
Led_Vaga32 : OUT STD_LOGIC;
Led_Vaga33 : OUT STD_LOGIC;
Led_Vaga34 : OUT STD_LOGIC;
Led_Vaga35 : OUT STD_LOGIC;
Led_Vaga36 : OUT STD_LOGIC;
Led_Vaga37 : OUT STD_LOGIC;
Led_Vaga38 : OUT STD_LOGIC;
Led_Vaga39 : OUT STD_LOGIC;
Led_Vaga40 : OUT STD_LOGIC;
Led_Vaga41 : OUT STD_LOGIC;
Led_Vaga42 : OUT STD_LOGIC;
Led_Vaga43 : OUT STD_LOGIC;
Led_Vaga44 : OUT STD_LOGIC;
Led_Vaga45 : OUT STD_LOGIC;
Led_Vaga46 : OUT STD_LOGIC;
Led_Vaga47 : OUT STD_LOGIC;
Led_Vaga48 : OUT STD_LOGIC;
Led_Vaga49 : OUT STD_LOGIC;
Led_Vaga50 : OUT STD_LOGIC;
Led_Vaga51 : OUT STD_LOGIC;
Led_Vaga52 : OUT STD_LOGIC;
Led_Vaga53 : OUT STD_LOGIC;
Led_Vaga54 : OUT STD_LOGIC;
Led_Vaga55 : OUT STD_LOGIC;
Led_Vaga56 : OUT STD_LOGIC;
Led_Vaga57 : OUT STD_LOGIC;
Led_Vaga58 : OUT STD_LOGIC;
Led_Vaga59 : OUT STD_LOGIC;
Led_Vaga60 : OUT STD_LOGIC;
display_unidade_23 : OUT STD_LOGIC;
display_unidade_33 : OUT STD_LOGIC;
display_unidade_43 : OUT STD_LOGIC;
Led_Vaga_Deficiente3 : OUT STD_LOGIC;
display_unidade_13 : OUT STD_LOGIC;
display_dezena3 : OUT STD_LOGIC;
display_unidade_14 : OUT STD_LOGIC;
display_unidade_24 : OUT STD_LOGIC;
display_unidade_34 : OUT STD_LOGIC;
display_unidade_44 : OUT STD_LOGIC;
display_dezena4 : OUT STD_LOGIC;
Led_Vaga_Deficiente4 : OUT STD_LOGIC;
DezenaF1 : OUT STD_LOGIC;
DezenaF2 : OUT STD_LOGIC;
DezenaF3 : OUT STD_LOGIC;
DezenaF4 : OUT STD_LOGIC;
UnidadeF1 : OUT STD_LOGIC;
UnidadeF2 : OUT STD_LOGIC;
UnidadeF3 : OUT STD_LOGIC;
UnidadeF4 : OUT STD_LOGIC;
VagaDeficiente : OUT STD_LOGIC;
v1 : OUT STD_LOGIC;
v2 : OUT STD_LOGIC;
v3 : OUT STD_LOGIC;
v4 : OUT STD_LOGIC
);
END Central2;
ARCHITECTURE bdf_type OF Central2 IS
ATTRIBUTE black_box : BOOLEAN;
ATTRIBUTE noopt : BOOLEAN;
COMPONENT \74283_0\
PORT(A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
COUT : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_0\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_0\: COMPONENT IS true;
COMPONENT \74283_1\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_1\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_1\: COMPONENT IS true;
COMPONENT \74283_2\
PORT(A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
COUT : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_2\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_2\: COMPONENT IS true;
COMPONENT \74283_3\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_3\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_3\: COMPONENT IS true;
COMPONENT \74283_4\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_4\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_4\: COMPONENT IS true;
COMPONENT \74283_5\
PORT(A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
COUT : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_5\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_5\: COMPONENT IS true;
COMPONENT sensordeled
PORT(Vaga1 : IN STD_LOGIC;
Vaga2 : IN STD_LOGIC;
Vaga3 : IN STD_LOGIC;
Vaga4 : IN STD_LOGIC;
Vaga5 : IN STD_LOGIC;
Vaga6 : IN STD_LOGIC;
Vaga7 : IN STD_LOGIC;
Vaga8 : IN STD_LOGIC;
Vaga9 : IN STD_LOGIC;
Vaga10 : IN STD_LOGIC;
Vaga11 : IN STD_LOGIC;
Vaga12 : IN STD_LOGIC;
Vaga13 : IN STD_LOGIC;
Vaga14 : IN STD_LOGIC;
Vaga15 : IN STD_LOGIC;
Vaga16 : IN STD_LOGIC;
Led_Vaga1 : OUT STD_LOGIC;
Led_Vaga2 : OUT STD_LOGIC;
Led_Vaga3 : OUT STD_LOGIC;
Led_Vaga4 : OUT STD_LOGIC;
Led_Vaga5 : OUT STD_LOGIC;
Led_Vaga6 : OUT STD_LOGIC;
Led_Vaga7 : OUT STD_LOGIC;
Led_Vaga8 : OUT STD_LOGIC;
Led_Vaga9 : OUT STD_LOGIC;
Led_Vaga10 : OUT STD_LOGIC;
Led_Vaga11 : OUT STD_LOGIC;
Led_Vaga12 : OUT STD_LOGIC;
Led_Vaga13 : OUT STD_LOGIC;
Led_Vaga14 : OUT STD_LOGIC;
Led_Vaga15 : OUT STD_LOGIC;
Led_Vaga_Deficiente : OUT STD_LOGIC;
pin_name1 : OUT STD_LOGIC;
pin_name2 : OUT STD_LOGIC;
pin_name3 : OUT STD_LOGIC;
pin_name4 : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT dec10b
PORT(P0 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
P2 : IN STD_LOGIC;
P3 : IN STD_LOGIC;
P4 : IN STD_LOGIC;
display_unidade_1 : OUT STD_LOGIC;
display_unidade_2 : OUT STD_LOGIC;
display_unidade_3 : OUT STD_LOGIC;
display_unidade_4 : OUT STD_LOGIC;
display_dezena1 : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT multiplex
PORT(P0 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
P2 : IN STD_LOGIC;
P3 : IN STD_LOGIC;
display_unidade_0 : OUT STD_LOGIC;
display_unidade_1 : OUT STD_LOGIC;
display_unidade_2 : OUT STD_LOGIC;
display_unidade_3 : OUT STD_LOGIC;
display_dezena : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_10 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_11 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_12 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_14 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_15 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_16 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_17 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_18 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_88 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_24 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_26 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_27 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_28 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_29 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_30 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_31 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_32 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_33 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_34 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_35 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_36 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_37 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_38 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_39 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_40 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_41 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_42 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_43 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_44 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_45 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_46 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_47 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_48 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_49 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_50 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_51 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_89 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_57 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_59 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_60 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_61 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_62 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_63 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_64 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_65 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_66 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_67 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_68 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_69 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_70 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_71 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_72 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_73 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_74 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_75 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_76 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_77 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_78 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_79 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_80 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_81 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_82 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_83 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_84 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_85 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_86 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_87 : STD_LOGIC;
BEGIN
Led_Vaga_Deficiente <= SYNTHESIZED_WIRE_76;
display_dezena <= SYNTHESIZED_WIRE_51;
Led_Vaga_Deficiente2 <= SYNTHESIZED_WIRE_79;
display_unidade_12 <= SYNTHESIZED_WIRE_6;
display_unidade_22 <= SYNTHESIZED_WIRE_2;
display_unidade_32 <= SYNTHESIZED_WIRE_7;
display_unidade_42 <= SYNTHESIZED_WIRE_5;
display_dezena2 <= SYNTHESIZED_WIRE_57;
display_unidade_11 <= SYNTHESIZED_WIRE_0;
display_unidade_21 <= SYNTHESIZED_WIRE_1;
display_unidade_31 <= SYNTHESIZED_WIRE_3;
display_unidade_41 <= SYNTHESIZED_WIRE_4;
display_unidade_23 <= SYNTHESIZED_WIRE_65;
display_unidade_33 <= SYNTHESIZED_WIRE_67;
display_unidade_43 <= SYNTHESIZED_WIRE_68;
Led_Vaga_Deficiente3 <= SYNTHESIZED_WIRE_77;
display_unidade_13 <= SYNTHESIZED_WIRE_64;
display_dezena3 <= SYNTHESIZED_WIRE_18;
display_unidade_14 <= SYNTHESIZED_WIRE_70;
display_unidade_24 <= SYNTHESIZED_WIRE_66;
display_unidade_34 <= SYNTHESIZED_WIRE_71;
display_unidade_44 <= SYNTHESIZED_WIRE_69;
display_dezena4 <= SYNTHESIZED_WIRE_24;
Led_Vaga_Deficiente4 <= SYNTHESIZED_WIRE_78;
v1 <= SYNTHESIZED_WIRE_72;
v2 <= SYNTHESIZED_WIRE_73;
v3 <= SYNTHESIZED_WIRE_74;
v4 <= SYNTHESIZED_WIRE_75;
SYNTHESIZED_WIRE_48 <= '1';
SYNTHESIZED_WIRE_49 <= '1';
b2v_Bloco1 : sensordeled
PORT MAP(Vaga1 => Vaga1,
Vaga2 => Vaga2,
Vaga3 => Vaga3,
Vaga4 => Vaga4,
Vaga5 => Vaga5,
Vaga6 => Vaga6,
Vaga7 => Vaga7,
Vaga8 => Vaga8,
Vaga9 => Vaga9,
Vaga10 => vaga10,
Vaga11 => Vaga11,
Vaga12 => Vaga12,
Vaga13 => Vaga13,
Vaga14 => Vaga14,
Vaga15 => Vaga15,
Vaga16 => VagaD1,
Led_Vaga1 => Led_Vaga1,
Led_Vaga2 => Led_Vaga2,
Led_Vaga3 => Led_Vaga3,
Led_Vaga4 => Led_Vaga4,
Led_Vaga5 => Led_Vaga5,
Led_Vaga6 => Led_Vaga6,
Led_Vaga7 => Led_Vaga7,
Led_Vaga8 => Led_Vaga8,
Led_Vaga9 => Led_Vaga9,
Led_Vaga10 => Led_Vaga10,
Led_Vaga11 => Led_Vaga11,
Led_Vaga12 => Led_Vaga12,
Led_Vaga13 => Led_Vaga13,
Led_Vaga14 => Led_Vaga14,
Led_Vaga15 => Led_Vaga15,
Led_Vaga_Deficiente => SYNTHESIZED_WIRE_76,
pin_name1 => SYNTHESIZED_WIRE_72,
pin_name2 => SYNTHESIZED_WIRE_73,
pin_name3 => SYNTHESIZED_WIRE_74,
pin_name4 => SYNTHESIZED_WIRE_75);
b2v_Bloco2 : sensordeled
PORT MAP(Vaga1 => Vaga16,
Vaga2 => Vaga17,
Vaga3 => Vaga18,
Vaga4 => Vaga19,
Vaga5 => Vaga20,
Vaga6 => Vaga21,
Vaga7 => Vaga22,
Vaga8 => Vaga23,
Vaga9 => Vaga24,
Vaga10 => Vaga25,
Vaga11 => Vaga26,
Vaga12 => Vaga27,
Vaga13 => Vaga28,
Vaga14 => Vaga29,
Vaga15 => Vaga30,
Vaga16 => VagaD2,
Led_Vaga1 => Led_Vaga16,
Led_Vaga2 => Led_Vaga17,
Led_Vaga3 => Led_Vaga18,
Led_Vaga4 => Led_Vaga19,
Led_Vaga5 => Led_Vaga20,
Led_Vaga6 => Led_Vaga21,
Led_Vaga7 => Led_Vaga22,
Led_Vaga8 => Led_Vaga23,
Led_Vaga9 => Led_Vaga24,
Led_Vaga10 => Led_Vaga25,
Led_Vaga11 => Led_Vaga26,
Led_Vaga12 => Led_Vaga27,
Led_Vaga13 => Led_Vaga28,
Led_Vaga14 => Led_Vaga29,
Led_Vaga15 => Led_Vaga30,
Led_Vaga_Deficiente => SYNTHESIZED_WIRE_79,
pin_name1 => SYNTHESIZED_WIRE_80,
pin_name2 => SYNTHESIZED_WIRE_81,
pin_name3 => SYNTHESIZED_WIRE_82,
pin_name4 => SYNTHESIZED_WIRE_83);
b2v_Bloco3 : sensordeled
PORT MAP(Vaga1 => Vaga31,
Vaga2 => Vaga32,
Vaga3 => Vaga33,
Vaga4 => Vaga34,
Vaga5 => Vaga35,
Vaga6 => Vaga36,
Vaga7 => Vaga37,
Vaga8 => Vaga38,
Vaga9 => Vaga39,
Vaga10 => Vaga40,
Vaga11 => Vaga41,
Vaga12 => Vaga42,
Vaga13 => Vaga43,
Vaga14 => Vaga44,
Vaga15 => Vaga45,
Vaga16 => VagaD3,
Led_Vaga1 => Led_Vaga31,
Led_Vaga2 => Led_Vaga32,
Led_Vaga3 => Led_Vaga33,
Led_Vaga4 => Led_Vaga34,
Led_Vaga5 => Led_Vaga35,
Led_Vaga6 => Led_Vaga36,
Led_Vaga7 => Led_Vaga37,
Led_Vaga8 => Led_Vaga38,
Led_Vaga9 => Led_Vaga39,
Led_Vaga10 => Led_Vaga40,
Led_Vaga11 => Led_Vaga41,
Led_Vaga12 => Led_Vaga42,
Led_Vaga13 => Led_Vaga43,
Led_Vaga14 => Led_Vaga44,
Led_Vaga15 => Led_Vaga45,
Led_Vaga_Deficiente => SYNTHESIZED_WIRE_77,
pin_name1 => SYNTHESIZED_WIRE_84,
pin_name2 => SYNTHESIZED_WIRE_85,
pin_name3 => SYNTHESIZED_WIRE_86,
pin_name4 => SYNTHESIZED_WIRE_87);
b2v_Bloco4 : sensordeled
PORT MAP(Vaga1 => Vaga46,
Vaga2 => Vaga47,
Vaga3 => Vaga48,
Vaga4 => Vaga49,
Vaga5 => Vaga50,
Vaga6 => Vaga51,
Vaga7 => Vaga52,
Vaga8 => Vaga53,
Vaga9 => Vaga54,
Vaga10 => Vaga55,
Vaga11 => Vaga56,
Vaga12 => Vaga57,
Vaga13 => Vaga58,
Vaga14 => Vaga59,
Vaga15 => Vaga60,
Vaga16 => VagaD4,
Led_Vaga1 => Led_Vaga46,
Led_Vaga2 => Led_Vaga47,
Led_Vaga3 => Led_Vaga48,
Led_Vaga4 => Led_Vaga49,
Led_Vaga5 => Led_Vaga50,
Led_Vaga6 => Led_Vaga51,
Led_Vaga7 => Led_Vaga52,
Led_Vaga8 => Led_Vaga53,
Led_Vaga9 => Led_Vaga54,
Led_Vaga10 => Led_Vaga55,
Led_Vaga11 => Led_Vaga56,
Led_Vaga12 => Led_Vaga57,
Led_Vaga13 => Led_Vaga58,
Led_Vaga14 => Led_Vaga59,
Led_Vaga15 => Led_Vaga60,
Led_Vaga_Deficiente => SYNTHESIZED_WIRE_78,
pin_name1 => SYNTHESIZED_WIRE_13,
pin_name2 => SYNTHESIZED_WIRE_14,
pin_name3 => SYNTHESIZED_WIRE_15,
pin_name4 => SYNTHESIZED_WIRE_16);
b2v_inst : 74283_0
PORT MAP(A1 => SYNTHESIZED_WIRE_0,
A2 => SYNTHESIZED_WIRE_1,
B2 => SYNTHESIZED_WIRE_2,
A3 => SYNTHESIZED_WIRE_3,
A4 => SYNTHESIZED_WIRE_4,
B4 => SYNTHESIZED_WIRE_5,
B1 => SYNTHESIZED_WIRE_6,
B3 => SYNTHESIZED_WIRE_7,
SUM4 => SYNTHESIZED_WIRE_11,
COUT => SYNTHESIZED_WIRE_12,
SUM1 => SYNTHESIZED_WIRE_8,
SUM2 => SYNTHESIZED_WIRE_9,
SUM3 => SYNTHESIZED_WIRE_10);
b2v_inst1 : dec10b
PORT MAP(P0 => SYNTHESIZED_WIRE_8,
P1 => SYNTHESIZED_WIRE_9,
P2 => SYNTHESIZED_WIRE_10,
P3 => SYNTHESIZED_WIRE_11,
P4 => SYNTHESIZED_WIRE_12,
display_unidade_1 => SYNTHESIZED_WIRE_26,
display_unidade_2 => SYNTHESIZED_WIRE_27,
display_unidade_3 => SYNTHESIZED_WIRE_29,
display_unidade_4 => SYNTHESIZED_WIRE_30,
display_dezena1 => SYNTHESIZED_WIRE_50);
b2v_inst10 : multiplex
PORT MAP(P0 => SYNTHESIZED_WIRE_13,
P1 => SYNTHESIZED_WIRE_14,
P2 => SYNTHESIZED_WIRE_15,
P3 => SYNTHESIZED_WIRE_16,
display_unidade_0 => SYNTHESIZED_WIRE_70,
display_unidade_1 => SYNTHESIZED_WIRE_66,
display_unidade_2 => SYNTHESIZED_WIRE_71,
display_unidade_3 => SYNTHESIZED_WIRE_69,
display_dezena => SYNTHESIZED_WIRE_24);
b2v_inst11 : 74283_1
PORT MAP(CIN => SYNTHESIZED_WIRE_17,
A1 => SYNTHESIZED_WIRE_18,
A2 => SYNTHESIZED_WIRE_88,
B2 => SYNTHESIZED_WIRE_88,
A3 => SYNTHESIZED_WIRE_88,
A4 => SYNTHESIZED_WIRE_88,
B4 => SYNTHESIZED_WIRE_88,
B1 => SYNTHESIZED_WIRE_24,
B3 => SYNTHESIZED_WIRE_88,
SUM4 => SYNTHESIZED_WIRE_40,
SUM1 => SYNTHESIZED_WIRE_41,
SUM2 => SYNTHESIZED_WIRE_37,
SUM3 => SYNTHESIZED_WIRE_42);
b2v_inst12 : 74283_2
PORT MAP(A1 => SYNTHESIZED_WIRE_26,
A2 => SYNTHESIZED_WIRE_27,
B2 => SYNTHESIZED_WIRE_28,
A3 => SYNTHESIZED_WIRE_29,
A4 => SYNTHESIZED_WIRE_30,
B4 => SYNTHESIZED_WIRE_31,
B1 => SYNTHESIZED_WIRE_32,
B3 => SYNTHESIZED_WIRE_33,
SUM4 => SYNTHESIZED_WIRE_46,
COUT => SYNTHESIZED_WIRE_47,
SUM1 => SYNTHESIZED_WIRE_43,
SUM2 => SYNTHESIZED_WIRE_44,
SUM3 => SYNTHESIZED_WIRE_45);
b2v_inst13 : 74283_3
PORT MAP(CIN => SYNTHESIZED_WIRE_34,
A1 => SYNTHESIZED_WIRE_35,
A2 => SYNTHESIZED_WIRE_36,
B2 => SYNTHESIZED_WIRE_37,
A3 => SYNTHESIZED_WIRE_38,
A4 => SYNTHESIZED_WIRE_39,
B4 => SYNTHESIZED_WIRE_40,
B1 => SYNTHESIZED_WIRE_41,
B3 => SYNTHESIZED_WIRE_42,
SUM4 => DezenaF4,
SUM1 => DezenaF1,
SUM2 => DezenaF2,
SUM3 => DezenaF3);
b2v_inst14 : dec10b
PORT MAP(P0 => SYNTHESIZED_WIRE_43,
P1 => SYNTHESIZED_WIRE_44,
P2 => SYNTHESIZED_WIRE_45,
P3 => SYNTHESIZED_WIRE_46,
P4 => SYNTHESIZED_WIRE_47,
display_unidade_1 => UnidadeF1,
display_unidade_2 => UnidadeF2,
display_unidade_3 => UnidadeF3,
display_unidade_4 => UnidadeF4,
display_dezena1 => SYNTHESIZED_WIRE_34);
SYNTHESIZED_WIRE_89 <= NOT(SYNTHESIZED_WIRE_48);
SYNTHESIZED_WIRE_88 <= NOT(SYNTHESIZED_WIRE_49);
b2v_inst2 : 74283_4
PORT MAP(CIN => SYNTHESIZED_WIRE_50,
A1 => SYNTHESIZED_WIRE_51,
A2 => SYNTHESIZED_WIRE_89,
B2 => SYNTHESIZED_WIRE_89,
A3 => SYNTHESIZED_WIRE_89,
A4 => SYNTHESIZED_WIRE_89,
B4 => SYNTHESIZED_WIRE_89,
B1 => SYNTHESIZED_WIRE_57,
B3 => SYNTHESIZED_WIRE_89,
SUM4 => SYNTHESIZED_WIRE_39,
SUM1 => SYNTHESIZED_WIRE_35,
SUM2 => SYNTHESIZED_WIRE_36,
SUM3 => SYNTHESIZED_WIRE_38);
b2v_inst3 : dec10b
PORT MAP(P0 => SYNTHESIZED_WIRE_59,
P1 => SYNTHESIZED_WIRE_60,
P2 => SYNTHESIZED_WIRE_61,
P3 => SYNTHESIZED_WIRE_62,
P4 => SYNTHESIZED_WIRE_63,
display_unidade_1 => SYNTHESIZED_WIRE_32,
display_unidade_2 => SYNTHESIZED_WIRE_28,
display_unidade_3 => SYNTHESIZED_WIRE_33,
display_unidade_4 => SYNTHESIZED_WIRE_31,
display_dezena1 => SYNTHESIZED_WIRE_17);
b2v_inst4 : 74283_5
PORT MAP(A1 => SYNTHESIZED_WIRE_64,
A2 => SYNTHESIZED_WIRE_65,
B2 => SYNTHESIZED_WIRE_66,
A3 => SYNTHESIZED_WIRE_67,
A4 => SYNTHESIZED_WIRE_68,
B4 => SYNTHESIZED_WIRE_69,
B1 => SYNTHESIZED_WIRE_70,
B3 => SYNTHESIZED_WIRE_71,
SUM4 => SYNTHESIZED_WIRE_62,
COUT => SYNTHESIZED_WIRE_63,
SUM1 => SYNTHESIZED_WIRE_59,
SUM2 => SYNTHESIZED_WIRE_60,
SUM3 => SYNTHESIZED_WIRE_61);
b2v_inst5 : multiplex
PORT MAP(P0 => SYNTHESIZED_WIRE_72,
P1 => SYNTHESIZED_WIRE_73,
P2 => SYNTHESIZED_WIRE_74,
P3 => SYNTHESIZED_WIRE_75,
display_unidade_0 => SYNTHESIZED_WIRE_0,
display_unidade_1 => SYNTHESIZED_WIRE_1,
display_unidade_2 => SYNTHESIZED_WIRE_3,
display_unidade_3 => SYNTHESIZED_WIRE_4,
display_dezena => SYNTHESIZED_WIRE_51);
VagaDeficiente <= SYNTHESIZED_WIRE_76 OR SYNTHESIZED_WIRE_77 OR SYNTHESIZED_WIRE_78 OR SYNTHESIZED_WIRE_79;
b2v_inst7 : multiplex
PORT MAP(P0 => SYNTHESIZED_WIRE_80,
P1 => SYNTHESIZED_WIRE_81,
P2 => SYNTHESIZED_WIRE_82,
P3 => SYNTHESIZED_WIRE_83,
display_unidade_0 => SYNTHESIZED_WIRE_6,
display_unidade_1 => SYNTHESIZED_WIRE_2,
display_unidade_2 => SYNTHESIZED_WIRE_7,
display_unidade_3 => SYNTHESIZED_WIRE_5,
display_dezena => SYNTHESIZED_WIRE_57);
b2v_inst8 : multiplex
PORT MAP(P0 => SYNTHESIZED_WIRE_84,
P1 => SYNTHESIZED_WIRE_85,
P2 => SYNTHESIZED_WIRE_86,
P3 => SYNTHESIZED_WIRE_87,
display_unidade_0 => SYNTHESIZED_WIRE_64,
display_unidade_1 => SYNTHESIZED_WIRE_65,
display_unidade_2 => SYNTHESIZED_WIRE_67,
display_unidade_3 => SYNTHESIZED_WIRE_68,
display_dezena => SYNTHESIZED_WIRE_18);
END bdf_type; | gpl-2.0 | 2261a1b7ec6baec4f7b3748d2676a44c | 0.664198 | 2.796067 | false | false | false | false |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/ram_init.vhd | 1 | 1,752 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
entity ram is
port(
data : in std_logic_vector(7 downto 0);
write_addr : in std_logic_vector(7 downto 0);
read_addr : in std_logic_vector(7 downto 0);
w_enable : in std_logic;
r_enable : in std_logic;
clk, rst : in std_logic;
data_out : out std_logic_vector(7 downto 0));
end ram;
architecture mixed of ram is
type mem_type is array(255 downto 0) of std_logic_vector(7 downto 0);
signal mem_data : mem_type;
begin
process(clk, rst)
begin
if(rst = '1') then
mem_data(0) <= X"0A";
mem_data(1) <= X"02";
mem_data(2) <= X"31";
mem_data(3) <= X"0E";
mem_data(4) <= X"E3";
mem_data(5) <= X"B4";
mem_data(6) <= X"25";
mem_data(7) <= X"86";
mem_data(8) <= X"77";
mem_data(9) <= X"98";
mem_data(10) <= X"29";
mem_data(11) <= X"10";
mem_data(12) <= X"1F";
report "RAM data set." ;
end if;
if (falling_edge(clk)) then
if (w_enable = '1') then
mem_data(conv_integer(write_addr)) <= data;
report "Memory write addr: " & integer'image(conv_integer(write_addr)) & " data: " & integer'image(conv_integer(data));
end if;
if (r_enable = '1') then
data_out <= mem_data(conv_integer(read_addr));
report "Memory read addr: " & integer'image(conv_integer(read_addr)) & " data: " & integer'image(conv_integer(mem_data(conv_integer(read_addr))));
end if;
end if;
end process;
end mixed;
| unlicense | 0172660c07f28cfa59fdd2fdbef278cb | 0.531393 | 3.139785 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_A/RSA_Security_Token_Keyboard_Version/LCD.vhdl | 1 | 6,133 |
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use work.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------------
--FPGA to DMC16207 LCD interface. Takes care of inititation and after that sits
--ready to take commands from the top module to print, clear or row-change.
-------------------------------------------------------------------------------
entity LCD is
Port (INPUT : in STD_LOGIC_VECTOR (7 downto 0); --ASCII IN
CLK : in STD_LOGIC; --FPGA Clock (100MHz)
ARESETN : in STD_LOGIC; --RESET
DATA_BUS : out STD_LOGIC_VECTOR (7 downto 0);--DB 7 downto DB 0
RW : out STD_LOGIC := '0'; --RW signal (unused as of now)
RS : out STD_LOGIC; --RS signal
E : out STD_LOGIC; --E (200Hz)
MODE_SELECT : in STD_LOGIC_VECTOR (1 downto 0); --Select cmd to be done
RDY_CMD : out STD_LOGIC := '0'; --Ready for cmd from top module
DO_CMD : in STD_LOGIC); --Cmd to be done from top module
--STEP : out STD_LOGIC_VECTOR (3 downto 0) := (others => '0'));
end LCD;
architecture Behaviour of LCD is
Signal INPUT_2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
Signal clock_div_1, clock_div_2: unsigned (7 downto 0) := (others => '0');
Signal clock_div_3, init_state : unsigned (3 downto 0) := (others => '0');
Signal E_toggle, e_step : STD_LOGIC := '0';
begin
-------------------------------------CLOCK DIVIDER----------------------------
--Divides a clock from 100MHz to 400Hz in 3 steps.
------------------------------------------------------------------------------
clock_divider: process (clk)
begin
if rising_edge(clk) then
if ARESETN = '0' then
clock_div_1 <= (others => '0');
clock_div_2 <= (others => '0');
clock_div_3 <= (others => '0');
E_toggle <= '0';
else
clock_div_1 <= clock_div_1 + 1;
if (clock_div_1 = x"C8") then -- div_1 = 100(C8/2) => 1000kHz
clock_div_1 <= x"00";
clock_div_2 <= clock_div_2 + 2; --use +1 to half the frequency
end if;
if (clock_div_2 = x"FA") then -- div_2 = 250(FA) => 4kHz
clock_div_2 <= x"00";
clock_div_3 <= clock_div_3 + 1;
end if;
if (clock_div_3 = x"A") then -- div_3 = 10(A) => 400Hz
clock_div_3 <= x"0";
E_toggle <= NOT E_toggle; --Every 2.5ms => E_toggle = 400Hz
end if;
end if;
end if;
end process clock_divider;
---------------------------------State and Data changes------------------------
--Happens on high flank as on E low flank the action will be executed. Switches
--between having the E 1 and 0 each high flank of E_toggle, and is as such half
--the frequency of E_toggle (200Hz).
-------------------------------------------------------------------------------
E_process: process (E_toggle)
begin
if rising_edge(E_toggle) then
if e_step = '0' then
---------------------------------------------------Initilazion takes 8 E-cycles
if init_state < 8 then
init_state <= init_state + 1;
e_step <= '1';
case init_state is
when x"4" => --Display OFF
RS <= '0';
RW <= '0';
DATA_BUS <= "00001000";
when x"5" => --Clear Display
RS <= '0';
RW <= '0';
DATA_BUS <= "00000001";
when x"6" => --Entry Mode Set
RS <= '0';
RW <= '0';
DATA_BUS <= "00000110";
when x"7" => --Display ON (Blink and Cursor ON)
RS <= '0';
RW <= '0';
DATA_BUS <= "00001111";
RDY_CMD <= '1';
when others => --Function set command (step 0,1,2,3)
RS <= '0';
RW <= '0';
DATA_BUS <= "00111100";
end case;
-----------------------------------------------------Normal operation selection
elsif DO_CMD = '1' then
e_step <= '1';
RDY_CMD <= '0';
case MODE_SELECT is
when "00" => --CLEAR DISPAY
RS <= '0';
RW <= '0';
DATA_BUS <= "00000001";
when "01" => --Print INPUT on DISPLAY
RS <= '1';
RW <= '0';
DATA_BUS <= INPUT;
if INPUT = "00000000" then --if char is '\0', don't print it
e_step <= '0';
end if;
when "10" => --CHANGE ROW
RS <= '0';
RW <= '0';
DATA_BUS <= "11000000";
when others => --CLEAR DISPLAY
RS <= '0';
RW <= '0';
DATA_BUS <= "00000001";
end case;
else --Because we don't print '\0' we have to reset RDY_CMD here
RDY_CMD <= '1';
end if;
else
e_step <= '0';
RDY_CMD <= '1';
end if;
E <= e_step;
end if;
end process E_process;
end architecture; | bsd-3-clause | 235e1e70b2ace75e31c05d3179e477f6 | 0.560248 | 3.551245 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/USB_CMD_PARSER.vhd | 1 | 14,496 |
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_MISC.all;
use IEEE.NUMERIC_STD.all;
entity USB_CMD_PARSER is
generic ( data_addr_width : integer;
Frequency : integer);
Port ( RXD_BYTE : in STD_LOGIC_VECTOR (7 downto 0); --Input byte from the serial-to-parallell translator
TXD_BYTE : out STD_LOGIC_VECTOR (7 downto 0); --Output byte to the parallell-to-serial translator
RAM_ADDR : out STD_LOGIC_VECTOR (data_addr_width-1 downto 0) := (others => '1'); --RAM ADDR where the RSA (signed) message is
RAM_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); --DATA from the active RAM cell
RAM_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0); --DATA to be written to active RAM cell if WE is high
VALID_DATA_IN : in STD_LOGIC; --Flag to the parallell-to-serial translator to tell it that there's a new byte on the bus
VALID_DATA_OUT : out STD_LOGIC; --Flag from the serial-to-parallell translator to tell that there's a new byte on the bus
RAM_WE : out STD_LOGIC; --RAM Write Enable flag
RSA_DONE : in STD_LOGIC; --Flag from RSA module that the values in RAM are the signed message
READY_FOR_DATA : in STD_LOGIC; --Flag from RSA module that it is ready to recive a new message to sign
RESET : in STD_LOGIC; --Reset for module. When high all registers and counters resets at next high flank of the clock
CLK : in STD_LOGIC; --Global clock signal
DATA_READY : out STD_LOGIC := '0'; --Flag for 64 byte recieved
FIFO_EMPTY : in STD_LOGIC);
end USB_CMD_PARSER;
--USB_CMD_PARSER is a module that recives whole bytes from RXD_Controller and parses them as
--either command or data.
--The commands are all this module accepts, and any other data recieved is disgarded.
--Everything that is to be sent is put in the TXD_FIFO in order of how it should be sent.
--The commands are all on the form '*' followed by the command specific character, and are as follows:
--*I - Request ID. The parser will respond with *IHEJ
--*W[64 byte] - Write request. Depending on READY_FOR_DATA flag, this will either
--respond with *B for "busy" or *D when all 64 bytes has been written to memory
--*R -- Request encrypted data. Depending on DATA_READY flag, this will either
--respond with *B for "busy" or *M[64 bytes], where the 64 bytes are the encrypted data
--In certain cases if data is either not recieved or not provided, the module will respond
--with *T for timeout
architecture Behavioral of USB_CMD_PARSER is
constant ASCII_ASTERISK : STD_LOGIC_VECTOR(7 downto 0) := x"2A"; --*
constant ASCII_B : STD_LOGIC_VECTOR(7 downto 0) := x"42"; --B
constant ASCII_D : STD_LOGIC_VECTOR(7 downto 0) := x"44"; --D
constant ASCII_E : STD_LOGIC_VECTOR(7 downto 0) := x"45"; --E
constant ASCII_H : STD_LOGIC_VECTOR(7 downto 0) := x"48"; --H
constant ASCII_J : STD_LOGIC_VECTOR(7 downto 0) := x"4A"; --J
constant ASCII_W : STD_LOGIC_VECTOR(7 downto 0) := x"57"; --W
constant ASCII_R : STD_LOGIC_VECTOR(7 downto 0) := x"52"; --R
constant ASCII_M : STD_LOGIC_VECTOR(7 downto 0) := x"4D"; --M
constant ASCII_I : STD_LOGIC_VECTOR(7 downto 0) := x"49"; --I
constant ASCII_T : STD_LOGIC_VECTOR(7 downto 0) := x"54"; --T
--No. They are not in alphabetical order. Deal with it
type STATES is (IDLE, TRANSLATE_CMD, DO_CMD); --States for the overarching functionality
type CMDS is (TIMEOUT, RECIVE_DATA, TRANSMIT_DATA, TRANSMIT_ID, TRANSMIT_BUSY); --Depending on flags and inputs different commands are to be executed
signal TIMEOUT_COUNTER : integer range 0 to Frequency/2 := 0;
signal BYTE_COUNTER : unsigned (7 downto 0) := (others => '0'); --Counter to keep track of what byte in memory to read/write
signal HEADER_COUNTER : unsigned (1 downto 0) := (others => '0'); --counter to keep track of if an * or a message specific char is to be sent
signal STATE : STATES := IDLE;
signal CMD : CMDS;
signal flag : std_logic := '0';
Signal DATA_READY_S : STD_LOGIC;
begin
DATA_READY <= DATA_READY_S;
process(clk)
variable RECIVED_DATA : STD_LOGIC_VECTOR(7 downto 0);
--Procedure for IDLE state
procedure IDLE
(DATA : in STD_LOGIC_VECTOR(7 downto 0); --Data form RXD
signal STATE : out STATES) is
begin
if DATA = ASCII_ASTERISK then --Procede iff the header * is detected
state <= TRANSLATE_CMD;
end if;
end IDLE;
--Procedure for TRANSLATE_CMD state
procedure TRANSLATE
(DATA : in STD_LOGIC_VECTOR(7 downto 0); --Data from RXD
signal STATE : out STATES;
signal CMD : out CMDS;
signal RAM_ADDR : out STD_LOGIC_VECTOR(data_addr_width-1 downto 0)) is
begin
case DATA is
--Write request
when ASCII_W =>
STATE <= DO_CMD;
--If ready for recieving data we can execute this command
if READY_FOR_DATA = '1' then
CMD <= RECIVE_DATA;
else --otherwise we have to tell the PC that we're busy
CMD <= TRANSMIT_BUSY;
end if;
--Request of data from the PC
when ASCII_R =>
STATE <= DO_CMD;
--If the RSA is done and in memory, and no other active transmit jobs, we can transmit it to the PC
if RSA_DONE = '1' AND FIFO_EMPTY = '1' then
CMD <= TRANSMIT_DATA;
RAM_ADDR <= (others => '0');
else --Otherwise tell the PC that the unit is busy
CMD <= TRANSMIT_BUSY;
end if;
--Request of ID-sequence from the PC
when ASCII_I =>
STATE <= DO_CMD;
CMD <= TRANSMIT_ID;
--Illegal command. Go back to idle
when others =>
STATE <= IDLE;
end case;
end TRANSLATE;
--Procedure for DO_CMD state
procedure DO_CMD
(DATA : in STD_LOGIC_VECTOR(7 downto 0); --Data form RXD as input
BYTE_COUNT : in unsigned(7 downto 0); --Byte_counter as input
HEADER_COUNT : in unsigned(1 downto 0); --Header_counter as input
CMD : in CMDS; --current CMD as input
VALID_DATA_IN : in STD_LOGIC; --VALID_DATA_IN as input
variable byte_count_var, header_count_var : in integer; --integer versions of the counters as inputs
signal STATE : out STATES; --May change current state
signal RAM_ADDR : out STD_LOGIC_VECTOR(data_addr_width-1 downto 0); --May change RAM_ADDR
signal RAM_WE, VALID_DATA_OUT : out STD_LOGIC; --May change WE and VALID flags
signal RAM_DATA_OUT, TXD_BYTE : out STD_LOGIC_VECTOR (7 downto 0);--May change RAM_DATA_OUT and TXD
signal BYTE_COUNTER : out unsigned(7 downto 0); --May change the counters
signal HEADER_COUNTER : out unsigned(1 downto 0)) is
begin
case CMD is
--Recieve data case. Write the following 64 bytes to the RAM
when RECIVE_DATA =>
if BYTE_COUNT_var > 63 then --all bytes have been written
RAM_ADDR <= (others => '1'); --Reset signals that are not used anymore
RAM_WE <= '0';
RAM_DATA_OUT <= (others => '0');
VALID_DATA_OUT <= '1';
DATA_READY_S <= '1';
if header_count_var = 0 then -- When the message is recived, tell the PC by sending *D
TXD_BYTE <= ASCII_ASTERISK;
HEADER_COUNTER <= HEADER_COUNT + 1;
else
TXD_BYTE <= ASCII_D;
HEADER_COUNTER <= (others => '0');
STATE <= IDLE;
BYTE_COUNTER <= (others => '0');
end if;
elsif VALID_DATA_IN = '1' then --Write the current number to the current cell in memory
DATA_READY_S <= '0';
RAM_ADDR <= STD_LOGIC_VECTOR(BYTE_COUNT(5 downto 0));
RAM_DATA_OUT <= DATA;
RAM_WE <= '1';
BYTE_COUNTER <= BYTE_COUNT + 1; --inc the RAM ptr
end if;
--Tansmit data case. Write the first 64 bytes in RAM to the port
when TRANSMIT_DATA =>
VALID_DATA_OUT <= '1';
--First write the header *M for signal to the PC that a message is comming
if HEADER_COUNT_var = 0 then
TXD_BYTE <= ASCII_ASTERISK;
HEADER_COUNTER <= HEADER_COUNT + 1;
elsif HEADER_COUNT_var = 1 then
TXD_BYTE <= ASCII_M;
HEADER_COUNTER <= HEADER_COUNT + 1;
BYTE_COUNTER <= BYTE_COUNT + 1;
elsif BYTE_COUNT_VAR > 63 then --all bytes has been transmitted
STATE <= IDLE;
RAM_ADDR <= (others => '0');
BYTE_COUNTER <= (others => '0');
TXD_BYTE <= RAM_DATA_IN;
else --Put the data to the serial out
RAM_ADDR <= STD_LOGIC_VECTOR(BYTE_COUNT(5 downto 0));
TXD_BYTE <= RAM_DATA_IN;
BYTE_COUNTER <= BYTE_COUNT + 1;
end if;
when TRANSMIT_ID =>
--First write the header *I for signal to the PC that an ID is comming
if HEADER_COUNT_var = 0 then
TXD_BYTE <= ASCII_ASTERISK;
HEADER_COUNTER <= HEADER_COUNT + 1;
elsif HEADER_COUNT_var = 1 then
TXD_BYTE <= ASCII_I;
HEADER_COUNTER <= HEADER_COUNT + 1;
else
--Put the ID on the serial out. The ID is: HEJ
case BYTE_COUNT_VAR is
when 0 =>
TXD_BYTE <= ASCII_H;
BYTE_COUNTER <= BYTE_COUNT + 1;
when 1 =>
TXD_BYTE <= ASCII_E;
BYTE_COUNTER <= BYTE_COUNT + 1;
when others =>
TXD_BYTE <= ASCII_J; --Last char to be transmitted. Return to IDLE state
STATE <= IDLE;
HEADER_COUNTER <= (others => '0');
BYTE_COUNTER <= (others => '0');
end case;
end if;
VALID_DATA_OUT <= '1';
when TRANSMIT_BUSY =>
--First write the header *B for signal to tell PC that unit is busy
if HEADER_COUNT_var = 0 then
TXD_BYTE <= ASCII_ASTERISK;
HEADER_COUNTER <= HEADER_COUNT + 1;
else
TXD_BYTE <= ASCII_B;
HEADER_COUNTER <= (others => '0');
STATE <= IDLE;
end if;
VALID_DATA_OUT <= '1';
when TIMEOUT =>
RAM_ADDR <= (others => '1'); --Reset signals that are not used anymore
RAM_WE <= '0';
RAM_DATA_OUT <= (others => '0');
VALID_DATA_OUT <= '1';
BYTE_COUNTER <= (others => '0');
if HEADER_COUNT_var = 0 then
TXD_BYTE <= ASCII_ASTERISK;
HEADER_COUNTER <= HEADER_COUNT + 1;
else
TXD_BYTE <= ASCII_T;
HEADER_COUNTER <= (others => '0');
STATE <= IDLE;
end if;
end case;
end DO_CMD;
variable BYTE_COUNT_VAR : integer := 0;
variable HEADER_COUNT_VAR : integer := 0;
begin
if rising_edge(clk) then
if RESET = '1' then --synchronous reset
STATE <= IDLE;
-- CMD <= NONE;
VALID_DATA_OUT <= '0';
RAM_ADDR <= (others => '0');
RAM_DATA_OUT <= (others => '0');
RAM_WE <= '0';
TXD_BYTE <= (others => '0');
BYTE_COUNTER <= (others => '0');
HEADER_COUNTER <= (others => '0');
TIMEOUT_COUNTER <= 0;
DATA_READY_S <= '0';
else
if DATA_READY_S = '1' and READY_FOR_DATA = '1' then
DATA_READY_S <= '0';
end if;
case STATE is
when IDLE => --Reset everything
VALID_DATA_OUT <= '0';
RAM_ADDR <= (others => '0');
RAM_DATA_OUT <= (others => '0');
RAM_WE <= '0';
TXD_BYTE <= (others => '0');
BYTE_COUNTER <= (others => '0');
HEADER_COUNTER <= (others => '0');
TIMEOUT_COUNTER <= 0;
--If we have a valid input and that input is * then we are going to the TRANSLATE_CMD state
if VALID_DATA_IN = '1' then
RECIVED_DATA := RXD_BYTE; --create variable for procedure
--Use the procedure IDLE with the signals and variables that it desires
IDLE(RECIVED_DATA, STATE);
end if;
--Parse the command
when TRANSLATE_CMD =>
--Timeout counter
if TIMEOUT_COUNTER < Frequency/2-1 then --If not timeout yet, increase the counter
TIMEOUT_COUNTER <= TIMEOUT_COUNTER + 1;
end if;
if VALID_DATA_IN = '1' then
RECIVED_DATA := RXD_BYTE; --create variable for procedure
--Use the procedure TRANSLATE with the signals and variables that it desires
TRANSLATE(RECIVED_DATA, STATE, CMD, RAM_ADDR);
TIMEOUT_COUNTER <= 0;
elsif TIMEOUT_COUNTER >= Frequency/2-1 then
STATE <= DO_CMD;
CMD <= TIMEOUT;
TIMEOUT_COUNTER <= 0;
end if;
--Do the command that was decided from TRANSLATE
when DO_CMD =>
RECIVED_DATA := RXD_BYTE;
BYTE_COUNT_VAR := to_integer(BYTE_COUNTER); --create variables for procedure
HEADER_COUNT_VAR := to_integer(HEADER_COUNTER);
--Use the procedure DO_CMD with the signals and variables that it desires unless timeout
DO_CMD(DATA => RECIVED_DATA,
BYTE_COUNT => BYTE_COUNTER,
HEADER_COUNT => HEADER_COUNTER,
CMD => CMD,
VALID_DATA_IN => VALID_DATA_IN,
BYTE_COUNT_VAR => BYTE_COUNT_VAR,
HEADER_COUNT_VAR => HEADER_COUNT_VAR, --inputs
STATE => STATE,
RAM_ADDR => RAM_ADDR,
RAM_WE => RAM_WE,
VALID_DATA_OUT => VALID_DATA_OUT,
RAM_DATA_OUT => RAM_DATA_OUT,
TXD_BYTE => TXD_BYTE,
BYTE_COUNTER => BYTE_COUNTER,
HEADER_COUNTER => HEADER_COUNTER); --outputs
--Timeout counter
if TIMEOUT_COUNTER < Frequency/2-1 then --If not timeout yet, increase the counter
TIMEOUT_COUNTER <= TIMEOUT_COUNTER + 1;
else --Timeout. Proceed to send *T
CMD <= TIMEOUT;
TIMEOUT_COUNTER <= 0;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
| bsd-3-clause | e3840a315491a756b725b4918fff8a44 | 0.648041 | 3.40122 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/configuration/config_logic.vhd | 1 | 33,862 | ----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Panagiotis Gkountoumis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- Changelog:
-- 02.08.2016 Added ONLY_CONF_ONCE as a state to prevent multiple configuratoins
-- of the VMM. (Reid Pinkham)
-- 16.09.2016 Added additional elsif in state = CHECK for dynamic IP configuration
-- (Lev Kurilenko)
--
----------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity config_logic is
Port (
clk125 : in std_logic;
clk200 : in std_logic;
clk_in : in std_logic;
reset : in std_logic;
user_data_in : in std_logic_vector (7 downto 0);
user_data_out : out std_logic_vector (63 downto 0);
udp_rx : in udp_rx_type;
resp_data : out udp_response;
send_error : out std_logic;
user_conf : out std_logic;
user_wr_en : in std_logic;
user_last : in std_logic;
configuring : in std_logic;
-- we_conf : out std_logic;
vmm_id : out std_logic_vector(15 downto 0);
cfg_bit_out : out std_logic;
VMM_SCK : out std_logic;
VMM_SDO : in std_logic;
status : out std_logic_vector(3 downto 0);
start_vmm_conf : in std_logic;
conf_done : out std_logic;
ext_trigger : out std_logic;
ACQ_sync : out std_logic_vector(15 downto 0);
udp_header : in std_logic;
packet_length : in std_logic_vector (15 downto 0);
VMM_CS : out std_logic;
ena_conf : out std_logic;
xadc_busy : in std_logic;
xadc_start : out std_logic;
vmm_id_xadc : out std_logic_vector(15 downto 0);
xadc_sample_size : out std_logic_vector(10 downto 0);
xadc_delay : out std_logic_vector(17 downto 0);
myIP_set : out std_logic_vector(31 downto 0); --Lev
myMAC_set : out std_logic_vector(47 downto 0); --Lev
destIP_set : out std_logic_vector(31 downto 0); --Lev
newip_start : out std_logic --Lev
);
end config_logic;
architecture rtl of config_logic is
signal packet_length_int : integer := 0;
signal reading_packet : std_logic := '0';
signal user_last_int : std_logic := '0';
signal count, timeout : integer := 0;
signal last_synced200 : std_logic := '0';
signal i,w,del_cnt : integer := 0;
signal del_cnt2 : integer := 0;
signal counter, k, j : integer := 0;
signal sig_out : std_logic_vector(292 downto 0);
signal sn : std_logic_vector(31 downto 0);
signal vmm_id_int : std_logic_vector(15 downto 0);
signal cmd : std_logic_vector(15 downto 0);
signal user_data_in_int : std_logic_vector(7 downto 0);
signal status_int : std_logic_vector(3 downto 0);
signal user_wr_en_int : std_logic := '0';
signal cfg_bit_out_i : std_logic := '0';
signal VMM_SCK_i : std_logic := '0';
signal start_conf_process : std_logic := '0';
signal conf_done_i : std_logic := '0';
signal cnt_array, cnt_pause : integer := 0;
signal MainFSMstate : std_logic_vector(3 downto 0);
signal ConfFSMstate : std_logic_vector(3 downto 0);
signal test_data_int : std_logic_vector(31 downto 0);
signal delay_data : std_logic_vector(7 downto 0);
signal udp_header_int : std_logic := '0';
signal cs_int : std_logic := '1';
signal VMM_SDO_i : std_logic := '0';
type data_buffer is array(0 to 60) of std_logic_vector(31 downto 0);
signal conf_data : data_buffer;
signal reply_package : std_logic_vector(63 downto 0);
signal udp_response_int : udp_response;
signal start_vmm_conf_int : std_logic := '0';
signal start_vmm_conf_synced : std_logic := '0';
-- signal we_conf_int : std_logic := '0';
signal vmm_we_int : std_logic := '0';
signal cnt_cktk : integer := 0;
signal DAQ_START_STOP : std_logic_vector(31 downto 0);
signal dest_port : std_logic_vector(15 downto 0);
signal data_length : integer := 0;
signal cnt_reply : integer := 0;
signal cnt_conf_18 : integer := 0;
signal cnt_conf_96 : integer := 0;
signal delay_user_last : std_logic := '0';
signal ena_conf_i : std_logic := '1';
signal ERROR : std_logic_vector(15 downto 0);
signal vmm_id_xadc_i : std_logic_vector(15 downto 0);
signal xadc_sample_size_i : std_logic_vector(10 downto 0);
signal xadc_delay_i : std_logic_vector(17 downto 0);
-----------------------------------------------------------
-- IP Signal LEV
signal newip_counter : integer := 0; --Lev
-----------------------------------------------------------
type tx_state is (IDLE, SerialNo, VMMID, COMMAND, DATA, CHECK, VMM_CONF, DELAY, FPGA_CONF, XADC_Init, XADC, SEND_REPLY, TEST, REPLY);
signal state : tx_state;
type state_t is (START, SEND1,SEND0, PAUSE_ONE, FINISHED, ONLY_CONF_ONCE);
signal conf_state : state_t;
attribute keep : string;
attribute dont_touch : string;
attribute keep of sn : signal is "true";
attribute keep of vmm_id_int : signal is "true";
attribute keep of user_last_int : signal is "true";
attribute keep of cmd : signal is "true";
attribute keep of count : signal is "true";
attribute keep of last_synced200 : signal is "true";
attribute keep of reading_packet : signal is "true";
attribute keep of user_data_in_int : signal is "true";
attribute keep of user_wr_en_int : signal is "true";
attribute keep of packet_length_int : signal is "true";
attribute keep of cfg_bit_out_i : signal is "true";
attribute keep of status_int : signal is "true";
attribute keep of start_conf_process : signal is "true";
attribute keep of conf_done_i : signal is "true";
attribute keep of cnt_array : signal is "true";
attribute keep of DAQ_START_STOP : signal is "true";
attribute dont_touch of DAQ_START_STOP : signal is "true";
attribute keep of user_wr_en : signal is "true";
attribute dont_touch of user_wr_en : signal is "true";
attribute keep of MainFSMstate : signal is "true";
attribute keep of ConfFSMstate : signal is "true";
attribute keep of test_data_int : signal is "true";
attribute keep of delay_data : signal is "true";
attribute keep of i : signal is "true";
attribute keep of VMM_SCK_i : signal is "true";
attribute keep of udp_header_int : signal is "true";
attribute keep of j : signal is "true";
attribute keep of start_vmm_conf_int : signal is "true";
attribute keep of start_vmm_conf_synced : signal is "true";
attribute keep of dest_port : signal is "true";
attribute keep of cnt_conf_18 : signal is "true";
attribute keep of cnt_conf_96 : signal is "true";
-- attribute keep of vmm_id_xadc_i : signal is "true";
-- attribute keep of xadc_sample_size_i : signal is "true";
-- attribute keep of xadc_delay_i : signal is "true";
-- attribute keep of vmm_we_int : signal is "true";
-- attribute dont_touch of vmm_we_int : signal is "true";
attribute keep of cnt_cktk : signal is "true";
attribute dont_touch of cnt_cktk : signal is "true";
attribute keep of k : signal is "true";
attribute dont_touch of k : signal is "true";
attribute keep of cs_int : signal is "true";
attribute dont_touch of cs_int : signal is "true";
attribute keep of counter : signal is "true";
attribute dont_touch of counter : signal is "true";
attribute keep of del_cnt : signal is "true";
attribute dont_touch of del_cnt : signal is "true";
attribute keep of VMM_SDO_i : signal is "true";
attribute dont_touch of VMM_SDO_i : signal is "true";
attribute keep of ena_conf_i : signal is "true";
attribute dont_touch of ena_conf_i : signal is "true";
component ila_user_FIFO IS
PORT (
clk : IN std_logic;
probe0 : IN std_logic_vector(292 DOWNTO 0)
);
end component;
-----------------------------------------------------------
-- NEW IP Signals LEV
-----------------------------------------------------------
--attribute keep of conf_data : signal is "true"; --Lev
attribute keep of newip_counter : signal is "true"; --Lev
attribute keep of myIP_set : signal is "true"; --Lev
attribute keep of myMAC_set : signal is "true"; --Lev
attribute keep of destIP_set : signal is "true"; --Lev
begin
process (clk125)
begin
if clk125'event and clk125 = '1' then
user_wr_en_int <= user_wr_en;
delay_data <= user_data_in;
delay_user_last <= user_last;
end if;
end process;
user_last_int <= user_last;
user_data_in_int <= user_data_in;
--synced_to_125: process(clk125)
-- begin
-- if rising_edge(clk125) then
-- start_vmm_conf_synced <= start_vmm_conf_int;
-- end if;
-- end process;
------------------------ IDLE 0000
------------------------ VMM_CONF 0001
------------------------ XADC 0010
------------------------ RESET FPGA 0011
------------------------ DAQ OFF 1000
------------------------ FPGA_CONF 1001
------------------------ REPLY 1011
------------------------ DAQ ON 1111
process (clk125, state, configuring, cmd, reading_packet, count, packet_length_int, user_wr_en_int, last_synced200, user_wr_en, dest_port)
-- variable i : natural range 0 to 10 := 0; --1ms
begin
if clk125'event and clk125 = '1' then
if reset = '1' then
state <= IDLE;
else
case state is
when IDLE =>
MainFSMstate <= "0000";
status_int <= "0000";
count <= 0;
j <= 3;
cnt_array <= 0;
sn <= (others=> '0');
vmm_id_int <= x"0000";
cmd <= x"0000";
-- cs_int <= '1';
if user_wr_en = '1' then
state <= DATA;
end if;
when DATA =>
MainFSMstate <= "0001";
if j = 0 then
cnt_array <= cnt_array + 1;
conf_data(cnt_array)(8*j+ 7 downto 8*j) <= delay_data;
j <= 3;
else
conf_data(cnt_array)(8*j+ 7 downto 8*j) <= delay_data;
j <= j - 1;
end if;
if delay_user_last = '1' then
-- cnt_array <= 0;
-- count <= 4;
j <= 0;
state <= SerialNo;
end if;
when SerialNo =>
MainFSMstate <= "0010";
-- count <= count - 1;
sn <= conf_data(0);
reply_package(63 downto 32) <= sn;
state <= VMMID;
when VMMID =>
MainFSMstate <= "0011";
vmm_id_int <= conf_data(1)(31 downto 16);
packet_length_int <= to_integer(unsigned(packet_length));
data_length <= packet_length_int - 8;
reply_package(31 downto 16) <= vmm_id_int;
state <= COMMAND;
when COMMAND =>
MainFSMstate <= "0100";
cmd <= conf_data(1)(15 downto 0);
reply_package(15 downto 0) <= cmd;
state <= CHECK;
when CHECK =>
MainFSMstate <= "0101";
if dest_port = x"1778" then -- 6008 VMM CONFIGURATION
state <= VMM_CONF;
-- if vmm_id_int /= x"ffff" then
status_int <= "0001";
-- else
-- status_int <= "0010";
-- end if;
elsif dest_port = x"19C8" or dest_port = x"1777" then -- 6600 FPGA CONFIGURATION
cmd <= conf_data(1)(31 downto 16);
vmm_id_int <= conf_data(1)(15 downto 0);
state <= FPGA_CONF;
status_int <= "1001";
count <= 0;
elsif dest_port = x"19CC" then -- 6604 Flash Configuration --Lev
-- wait a few clock cycles to initatiate New IP Set --Lev
-- wait around 10 clock cycles --Lev
newip_start <= '1'; --Lev
newip_counter <= newip_counter + 1; --Lev
myIP_set <= conf_data(2)(31 downto 0); --Lev
myMAC_set(47 downto 32) <= conf_data(3)(15 downto 0); --Lev
myMAC_set(31 downto 0) <= conf_data(4)(31 downto 0); --Lev
destIP_set <= conf_data(5)(31 downto 0); --Lev
if (newip_counter = 10) then
newip_counter <= 0;
newip_start <= '0';
state <= IDLE;
end if;
elsif dest_port = x"19D0" then -- 6608 XADC
state <= XADC_Init;
status_int <= "0100";
xadc_start <= '1';
if cnt_array > 0 then -- If it is not an empty packet
vmm_id_xadc_i <= conf_data(0)(15 downto 0);
xadc_sample_size_i <= conf_data(1)(10 downto 0);
xadc_delay_i <= conf_data(2)(17 downto 0);
else -- is an empty packet
vmm_id_xadc_i <= "0000000000000000";
xadc_sample_size_i <= "01111111111"; -- 1023 packets
xadc_delay_i <= "011111111111111111"; -- 1023 samples over ~0.7 seconds
end if;
else
count <= 0;
state <= IDLE;
end if;
when VMM_CONF =>
MainFSMstate <= "0110";
if timeout = 5000000 then
state <= IDLE;
timeout <= 0;
ERROR <= x"ffff";
else
timeout <= timeout + 1;
end if;
if conf_done_i = '1' then
-- user_data_out <= reply_package;
state <= DELAY;-- SEND_REPLY;
-- reading_packet <= '0';
ERROR <= x"0000";
status_int <= "1011";
end if;
when DELAY =>
if del_cnt2 = 10 then
state <= REPLY;
del_cnt2 <= 0;
else
del_cnt2 <= del_cnt2 + 1;
end if;
when XADC_Init => -- Initialize the XADC
MainFSMstate <= "0111";
state <= XADC;
xadc_start <= '0';
when XADC => --Main XADC State
if (xadc_busy = '0') then -- if xadc is done
state <= IDLE;
else
state <= XADC;
end if;
when FPGA_CONF =>
MainFSMstate <= "1011";
-- DAQ_START_STOP <= conf_data(count+2);
-------------------------------------set this for the real configuration
-- if count*8 <= data_length then
-- if conf_data(count + 2) = x"00000000" and conf_data(count + 3) = x"00000004" then -- EXTERNAL
-- ext_trigger <= '1';
-- elsif conf_data(count + 2) = x"00000000" and conf_data(count + 3) = x"00000007" then -- PULSER
-- ext_trigger <= '0';
-- elsif conf_data(count + 2) = x"00001111" and conf_data(count + 3) = x"00000001" then -- DAQ ON
-- status_int <= "1111";
-- elsif conf_data(count + 2) = x"00001111" and conf_data(count + 3) = x"00000000" then -- DAQ OFF
-- status_int <= "1000";
-- elsif conf_data(count + 2) = x"ffffffff" and conf_data(count + 3) = x"ffff8000" then -- RESET FPGA
-- status_int <= "0011";
-- else
-- state <= IDLE;
-- end if;
-- else
-- count <= 0;
-- state <= IDLE;
-- end if;
-------------------------------------set this for the real configuration
DAQ_START_STOP <= conf_data(4);
if conf_data(5) = x"00000004" and conf_data(4) = x"00000000" then -- EXTERNAL
ext_trigger <= '1';
state <= TEST;
elsif conf_data(5) = x"00000007" and conf_data(4) = x"00000000" then -- PULSER
ext_trigger <= '0';
state <= TEST;
elsif conf_data(5) = x"00000001" and conf_data(4) = x"0000000f" then -- DAQ ON
status_int <= "1111";
state <= TEST;
elsif conf_data(5) = x"00000000" and conf_data(4) = x"0000000f" then -- DAQ OFF
status_int <= "1000";
state <= TEST;
elsif conf_data(4) = x"ffffffff" and conf_data(5) = x"ffff8000" then -- RESET FPGA
status_int <= "0011";
state <= IDLE;
elsif conf_data(4) = x"00000005" then -- Latency
ACQ_sync <= conf_data(5)(15 downto 0);
state <= IDLE;
else
state <= TEST;
end if;
when TEST =>
if count < 10 then
DAQ_START_STOP <= conf_data(count);
count <= count + 1;
else
count <= 0;
state <= IDLE;
end if;
when REPLY =>
state <= IDLE;
-- if cnt_reply = 0 then
---- user_data_out_i <= conf_data_out_i;
-- user_data_out <= reply_package;
-- cnt_reply <= cnt_reply + 1;
-- elsif cnt_reply = 1 then
-- user_data_out_i <= (others => '0');
-- cnt_reply <= cnt_reply + 1;
-- end_packet_conf_int <= '1';
-- we_conf_int <= '0';
-- elsif cnt_reply > 1 and cnt_reply < 100 then
-- cnt_reply <= cnt_reply + 1;
-- else
-- cnt_reply <= 0;
-- state <= IDLE;
---- state <= DAQ_INIT;
-- end_packet_conf_int <= '1';
-- end if;
when others =>
end case;
end if;
end if;
end process;
--synced_to_clkin: process(clk_in)
-- begin
-- if rising_edge(clk_in) then
-- start_vmm_conf_synced <= start_vmm_conf;
-- end if;
-- end process;
sync_start_vmm_conf: process(clk200)
begin
if rising_edge(clk200) then
if start_vmm_conf = '1' then
start_vmm_conf_synced <= '1';
end if;
if w = 40 then
start_vmm_conf_synced <= '0';
w <= 0;
else
w <= w + 1;
end if;
end if;
end process;
config_vmm_fsm : process( clk_in, conf_state, k, i, counter, del_cnt)
begin
if rising_edge( clk_in) then
if reset = '1' or status_int = "0011" then
conf_state <= START;
else
case conf_state is
when START =>
ConfFSMstate <= "0001";
cnt_conf_96 <= 0;
cnt_conf_18 <= 0;
cs_int <= '1';
counter <= 1728;
i <= 31;
k <= 2;
cfg_bit_out_i <= '0';
VMM_SCK_i <= '0';
test_data_int <= conf_data(k);
conf_done_i <= '0';
if start_vmm_conf = '1' then
conf_state <= SEND0;
cs_int <= '0';
ena_conf_i <= '0';
end if;
when SEND0 =>
ConfFSMstate <= "0010";
VMM_SCK_i <= '1';
cnt_cktk <= cnt_cktk + 1;
if cnt_conf_96 < 96 then
cnt_conf_96 <= cnt_conf_96 + 1;
conf_state <= SEND1;
else
cnt_conf_96 <= 0;
conf_state <= PAUSE_ONE;
VMM_SCK_i <= '0';
cnt_conf_18 <= cnt_conf_18 + 1;
cs_int <= '1';
end if;
if cnt_conf_18 = 18 then
conf_state <= FINISHED;
end if;
if k <= packet_length_int - 1 then
test_data_int <= conf_data(k);
if i /= 0 then
cfg_bit_out_i <= conf_data(k)(i);--(0);
i <= i - 1;
else
cfg_bit_out_i <= conf_data(k)(0);
k <= k + 1;
i <= 31;
end if;
end if;
when SEND1 =>
if cnt_conf_96 = 0 then
cs_int <= '0';
end if;
ConfFSMstate <= "0011";
VMM_SCK_i <= '0';
if (counter - 2) >= 0 then
if cnt_conf_96 /= 96 then
counter <= counter - 1;
end if;
conf_state <= SEND0;
else
conf_state <= FINISHED;
end if;
when PAUSE_ONE =>
ConfFSMstate <= "1111";
VMM_SCK_i <= '0';
cfg_bit_out_i <= '0';
i <= 31;
if cnt_pause = 10 then
conf_state <= SEND1;
cnt_pause <= 0;
else
cnt_pause <= cnt_pause + 1;
end if;
when FINISHED =>
cnt_conf_96 <= 0;
cnt_conf_18 <= 0;
cs_int <= '0';
ena_conf_i <= '1';
ConfFSMstate <= "0100";
cfg_bit_out_i <= '0';
if del_cnt = 5 then
conf_done_i <= '1';
del_cnt <= del_cnt + 1;
elsif del_cnt = 100 then
conf_state <= ONLY_CONF_ONCE;
del_cnt <= 0;
else
del_cnt <= del_cnt + 1;
end if;
VMM_SCK_i <= '0';
counter <= 0;
cs_int <= '1';
cnt_cktk <= 0;
when ONLY_CONF_ONCE =>
ConfFSMstate <= "0101";
if (start_vmm_conf = '0') then
conf_state <= START;
else
conf_state <= ONLY_CONF_ONCE;
end if;
end case;
end if;
end if;
end process config_vmm_fsm ;
start_vmm_conf_int <= start_vmm_conf;
vmm_id <= vmm_id_int;
dest_port <= udp_rx.hdr.dst_port;
vmm_id_xadc <=vmm_id_xadc_i;
xadc_sample_size <= xadc_sample_size_i;
xadc_delay <= xadc_delay_i;
status <= status_int;
conf_done <= conf_done_i;
cfg_bit_out <= cfg_bit_out_i;
VMM_SCK <= VMM_SCK_i;
-- ila_conf_logic : ila_user_FIFO
-- port map(
-- clk => clk125,
-- probe0 => sig_out
-- );
--we_conf <= we_conf_int;
--vmm_we_int <= vmm_we;
VMM_CS <= cs_int;
VMM_SDO_i <= VMM_SDO;
ena_conf <= ena_conf_i;
sig_out(7 downto 0) <= delay_data;
sig_out(8) <= start_vmm_conf_int;--user_fifo_empty;
sig_out(9) <= start_vmm_conf_synced;--user_fifo_en_main;--'0'; --user_fifo_en;
sig_out(10) <= udp_header_int;--send_error_int;
sig_out(11) <= user_wr_en;
sig_out(43 downto 12) <= sn;
sig_out(59 downto 44) <= vmm_id_int;
sig_out(75 downto 60) <= cmd;
sig_out(83 downto 76) <= std_logic_vector(to_unsigned(count, sig_out(83 downto 76)'length));
sig_out(91 downto 84) <= std_logic_vector(to_unsigned(cnt_array, 8));
sig_out(92) <= user_last_int;
sig_out(93) <= last_synced200;
--sig_out(110) <= reading_packet;
sig_out(101 downto 94) <= user_data_in_int;
sig_out(102) <= user_wr_en_int;
sig_out(103) <= VMM_SCK_i;--user_conf_int;
sig_out(104) <= cfg_bit_out_i;--reset_fifo_int;
sig_out(112 downto 105) <= std_logic_vector(to_unsigned(packet_length_int, sig_out(112 downto 105)'length));
sig_out(113) <= conf_done_i;--configuring_int;
sig_out(117 downto 114) <= status_int;
sig_out(118) <= start_conf_process;
sig_out(122 downto 119) <= MainFSMstate;
sig_out(126 downto 123) <= ConfFSMstate;
sig_out(134 downto 127) <= std_logic_vector(to_unsigned(i, sig_out(135 downto 128)'length));
sig_out(166 downto 135) <= test_data_int;
sig_out(174 downto 167) <= std_logic_vector(to_unsigned(j, sig_out(175 downto 168)'length));
sig_out(190 downto 175) <= std_logic_vector(to_unsigned(counter, sig_out(190 downto 175)'length));
sig_out(198 downto 191) <= std_logic_vector(to_unsigned(k, sig_out(198 downto 191)'length));
sig_out(214 downto 199) <= dest_port;
sig_out(246 downto 215) <= DAQ_START_STOP;
sig_out(247) <= cs_int;
sig_out(255 downto 248) <= std_logic_vector(to_unsigned(cnt_conf_18, sig_out(255 downto 248)'length));
sig_out(263 downto 256) <= std_logic_vector(to_unsigned(cnt_conf_96, sig_out(255 downto 248)'length));
sig_out(264) <= VMM_SDO_i;
sig_out(265) <= ena_conf_i;
--sig_out(262 downto 247) <= vmm_id_xadc_i;
--sig_out(273 downto 263) <= xadc_sample_size_i;
--sig_out(291 downto 274) <= xadc_delay_i;
sig_out(292 downto 266) <= (others => '0');
end rtl;
| gpl-3.0 | 3f1e8fc9c6b0ab61b99cd09d7cc9f305 | 0.390497 | 4.521565 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/testbench/tb_clockgen.vhd | 1 | 2,082 | --------------------------------------------------------------------------------------------------
-- Clock generator for test-benches
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package tb_clockgen_pkg is
component tb_clockgen is
generic( PERIOD : time := 30ns;
DUTY_CYCLE : real := 0.50);
port( clk : out std_logic);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Clock generator for test-benches/simulations. Do not use for synthesis designs. When used
-- simultaneously with other clock-generators should result in phase-aligned clocks.
entity tb_clockgen is
generic( --Duration of one clock cycle in seconds. Cycle starts at low logic.
PERIOD : time := 30ns;
--Percentage of the cycle spent at high logic. Valid Values between 0 and 1.
DUTY_CYCLE : real := 0.50);
port( --The generated clock signal
clk : out std_logic);
end tb_clockgen;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of tb_clockgen is
signal clock : std_logic;
begin
clk <= clock;
tictoc: process
begin
clock <= '1';
wait for (PERIOD - (PERIOD * DUTY_CYCLE));
clock <= '0';
wait for (PERIOD * DUTY_CYCLE);
end process;
end behave; | mit | 04b7e328058eec5ebfef23024c8b19db | 0.383285 | 5.931624 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_IN16.vhd | 1 | 3,919 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 08/03/2014
--! Module Name: EPROC_IN16
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! E-link processor, 16bit input
entity EPROC_IN16 is
generic (do_generate : boolean := true);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (15 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN16;
architecture Behavioral of EPROC_IN16 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
signal DATA_OUT_direct,DATA_OUT_8b10b_case,DATA_OUT_HDLC_case,DATA_OUT_s : std_logic_vector (9 downto 0);
signal DATA_RDY_direct,DATA_RDY_8b10b_case,DATA_RDY_HDLC_case,DATA_RDY_sig : std_logic;
signal RESTART_sig, rst_case00, rst_case01 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
rst_case00 <= RESTART_sig or (ENCODING(1) or ENCODING(0));
--
EPROC_IN16_direct_inst: entity work.EPROC_IN16_direct
port map(
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= RESTART_sig or (ENCODING(1) or (not ENCODING(0)));
--
EPROC_IN16_DEC8b10b_inst: entity work.EPROC_IN16_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_8b10b_case,
dataOUTrdy => DATA_RDY_8b10b_case,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
-- TBD
DATA_OUT_HDLC_case <= (others=>'0');
DATA_RDY_HDLC_case <= '0';
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_case,
data2 => DATA_OUT_HDLC_case,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_case,
data2 => DATA_RDY_HDLC_case,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 | 98b1ccafec8ab4a64960839be0b7035a | 0.45828 | 3.793804 | false | false | false | false |
HackLinux/ION | src/testbench/standalone/wb_bridge_tb.vhdl | 1 | 8,989 | --##############################################################################
-- wb_bridge_tb.vhdl --
--
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Project packages.
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
-- Tst bench support packages.
use std.textio.all;
use work.txt_util.all;
entity WB_BRIDGE_TB is
end;
architecture testbench of WB_BRIDGE_TB is
-- Length of simulation in clock cycles.
constant SIMULATION_LENGTH : integer := 100;
-- Simulation clock rate
constant CLOCK_RATE : integer := 50e6;
-- Simulation clock period
constant T : time := (1.0e9/real(CLOCK_RATE)) * 1 ns;
--------------------------------------------------------------------------------
-- Core interface.
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal ion_mosi : t_cpumem_mosi;
signal ion_miso : t_cpumem_miso;
signal wb_mosi : t_wishbone_mosi;
signal wb_miso : t_wishbone_miso;
--------------------------------------------------------------------------------
-- Uncached data WB bridge.
type t_natural_table is array(natural range <>) of natural;
-- Wait states simulated by uncached WB port (elements used in succession).
constant UNCACHED_WS : t_natural_table (0 to 3) := (4,1,3,2);
signal uwb_wait_ctr : natural;
signal uwb_cycle_count : natural := 0;
signal uwb_address : t_word;
type t_ram_table is array(natural range <>) of t_word;
shared variable debug_regs: t_ram_table(0 to 15);
--------------------------------------------------------------------------------
-- Logging signals & simulation control.
shared variable error_count : integer := 0;
--------------------------------------------------------------------------------
--
procedure ion_idle(signal mosi : out t_cpumem_mosi) is
begin
mosi.rd_en <= '0';
mosi.wr_be <= "0000";
end procedure ion_idle;
procedure ion_read(
signal clk : in std_logic;
signal mosi : inout t_cpumem_mosi;
signal miso : in t_cpumem_miso;
address : in std_logic_vector(31 downto 0);
data : out std_logic_vector(31 downto 0)
) is
begin
-- Align this read cycle with the next clock edge.
wait until clk'event and clk='1';
write(output, "Reading from ["& hstr(address)& "]..."& lf);
mosi.rd_en <= '1';
mosi.addr <= std_logic_vector(address);
-- Wait until the next clock edge.
wait until clk'event and clk='1';
-- (An overlapping CPI cycle would start in this cycle; we are not
-- simulating overlapping cycles in this simple TB.)
-- Now, if wait is asserted...
if miso.mwait = '1' then
-- ...wait until it is deasserted...
wait until clk'event and clk='1' and miso.mwait = '0';
else
-- ...otherwise the cycle ends here.
-- Take data from MISO and we're done.
data := miso.rd_data;
end if;
wait until clk'event and clk='1';
wait until clk'event and clk='1';
wait until clk'event and clk='1';
mosi.rd_en <= '0';
end procedure ion_read;
procedure ion_write(
signal clk : in std_logic;
signal mosi : inout t_cpumem_mosi;
signal miso : in t_cpumem_miso;
address : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0)
) is
begin
-- Align this read cycle with the next clock edge.
wait until clk'event and clk='1';
write(output, "Writing to ["& hstr(address)& "]..."& lf);
mosi.wr_be <= "1111"; -- FIXME simulating full word writes only
mosi.addr <= std_logic_vector(address);
mosi.wr_data <= data;
-- Wait until the next clock edge.
wait until clk'event and clk='1';
-- (An overlapping CPI cycle would start in this cycle; we are not
-- simulating overlapping cycles in this simple TB.)
-- Now, if wait is asserted...
if miso.mwait = '1' then
-- ...wait until it is deasserted...
wait until clk'event and clk='1' and miso.mwait = '0';
else
-- ...otherwise the cycle ends here.
end if;
mosi.wr_be <= "0000";
end procedure ion_write;
procedure check_data (
rd_data : in std_logic_vector(31 downto 0);
good_data : in std_logic_vector(31 downto 0)
) is
begin
if rd_data /= good_data then
error_count := error_count + 1;
end if;
assert rd_data = good_data
report "Invalid data: got "& hstr(rd_data)& ", expected "& hstr(good_data)
severity warning;
end procedure check_data;
--------------------------------------------------------------------------------
begin
-- UUT instantiation -------------------------------------------------------
bridge: entity work.ION_WISHBONE_BRIDGE
port map (
CLK_I => clk,
RESET_I => reset,
ION_MOSI_I => ion_mosi,
ION_MISO_O => ion_miso,
WISHBONE_MOSI_O => wb_mosi,
WISHBONE_MISO_I => wb_miso
);
-- Master clock: free running clock used as main module clock --------------
run_master_clock:
process(clk)
begin
clk <= not clk after T/2;
end process run_master_clock;
-- Main simulation process -------------------------------------------------
drive_uut:
process
variable rd_data : std_logic_vector(31 downto 0);
begin
wait for T*4;
reset <= '0';
wait for T*4;
ion_idle(ion_mosi);
wait for T*1;
ion_write(clk, ion_mosi, ion_miso, X"90000000", X"12345678");
ion_read(clk, ion_mosi, ion_miso, X"90000000", rd_data);
check_data(rd_data, X"12345678");
ion_idle(ion_mosi);
wait for T*4;
ion_write(clk, ion_mosi, ion_miso, X"90000004", X"11223344");
ion_read(clk, ion_mosi, ion_miso, X"90000004", rd_data);
check_data(rd_data, X"11223344");
-- We're done; stop the simulation.
if error_count = 0 then
write(output, "######## TEST PASSED ########"& lf);
else
write(output, "######## TEST FAILED ########"& lf);
end if;
assert 1=0
report "TB finished"
severity failure;
end process drive_uut;
-- Uncached WB port --------------------------------------------------------
uncached_wb_port:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
uwb_wait_ctr <= UNCACHED_WS((uwb_cycle_count) mod UNCACHED_WS'length);
wb_miso.ack <= '0';
wb_miso.dat <= (others => '1');
uwb_address <= (others => '0');
elsif wb_mosi.stb = '1' then
if uwb_wait_ctr > 0 then
-- Access in progress, decrement wait counter...
uwb_wait_ctr <= uwb_wait_ctr - 1;
wb_miso.ack <= '0';
uwb_address <= wb_mosi.adr;
else
-- Access finished, wait counter reached zero.
-- Prepare the wait counter for the next access...
uwb_wait_ctr <= UNCACHED_WS((uwb_cycle_count+1) mod UNCACHED_WS'length);
-- ...and drive the slave WB bus.
wb_miso.ack <= '1';
-- Termination is different for read and write accesses:
if wb_mosi.we = '1' then
-- Write access: do the simulated write.
debug_regs(0) := wb_mosi.dat;
else
-- Read access: simulate read & WB slave multiplexor.
wb_miso.dat <= debug_regs(0);
end if;
end if;
else
-- No WB access is going on: restore the wait counter to its
-- idle state and deassert ACK.
uwb_wait_ctr <= UNCACHED_WS((uwb_cycle_count) mod UNCACHED_WS'length);
wb_miso.ack <= '0';
end if;
-- Keep track of how many accesses we have performed.
-- We use this to select a number of wait states from a table.
if wb_mosi.stb = '1' and uwb_wait_ctr = 0 then
uwb_cycle_count <= uwb_cycle_count + 1;
end if;
end if;
end process uncached_wb_port;
-- stall the WB bus as long as the wait counter is not zero.
wb_miso.stall <=
'1' when wb_mosi.stb = '1' and uwb_wait_ctr > 0 else
'0';
end architecture testbench;
| lgpl-3.0 | 8abaf47097cf266bebfaea34d73e185d | 0.496941 | 4.184823 | false | false | false | false |
HackLinux/ION | src/rtl/obj/obj_code_pkg.vhdl | 1 | 80,356 | --------------------------------------------------------------------------------
-- obj_code_pkg.vhdl -- Application object code in vhdl constant string format.
--------------------------------------------------------------------------------
-- Built for project 'CPU tester'.
--------------------------------------------------------------------------------
-- This file contains object code in the form of a VHDL byte table constant.
-- This constant can be used to initialize FPGA memories for synthesis or
-- simulation.
-- Note that the object code is stored as a plain byte table in byte address
-- order. This table knows nothing of data endianess and can be used to
-- initialize 32-, 16- or 8-bit-wide memory -- memory initialization functions
-- can be found in package mips_pkg.
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
package OBJ_CODE_PKG is
-- Simulation or synthesis parameters ------------------------------------------
constant CODE_MEM_SIZE : integer := 4096;
constant DATA_MEM_SIZE : integer := 1024;
-- Memory initialization data --------------------------------------------------
constant OBJ_CODE : t_obj_code(0 to 10563) := (
X"10", X"00", X"00", X"74", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"40", X"1a", X"68", X"00", X"33", X"5a", X"00", X"7c",
X"23", X"5a", X"ff", X"e0", X"13", X"40", X"00", X"06",
X"00", X"00", X"00", X"00", X"40", X"1a", X"68", X"00",
X"03", X"00", X"c8", X"21", X"23", X"7b", X"00", X"01",
X"42", X"00", X"00", X"18", X"23", X"7b", X"00", X"01",
X"40", X"1a", X"70", X"00", X"8f", X"5a", X"ff", X"fc",
X"33", X"5a", X"ff", X"c0", X"3b", X"5a", X"00", X"40",
X"17", X"40", X"ff", X"f6", X"03", X"e0", X"d0", X"21",
X"0f", X"f0", X"08", X"5f", X"00", X"00", X"00", X"00",
X"03", X"40", X"f8", X"21", X"10", X"00", X"ff", X"f1",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"a8", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"34", X"1c", X"00", X"00",
X"34", X"1e", X"00", X"00", X"34", X"1b", X"00", X"00",
X"3c", X"04", X"bf", X"c0", X"24", X"84", X"22", X"ea",
X"0f", X"f0", X"08", X"a1", X"00", X"00", X"00", X"00",
X"3c", X"02", X"00", X"40", X"34", X"42", X"84", X"11",
X"40", X"82", X"60", X"00", X"00", X"00", X"00", X"00",
X"40", X"03", X"60", X"00", X"00", X"00", X"00", X"00",
X"24", X"04", X"00", X"01", X"03", X"64", X"20", X"22",
X"10", X"80", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"04", X"00", X"2c",
X"03", X"44", X"20", X"22", X"10", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"03", X"dc", X"f0", X"20", X"17", X"80", X"00", X"07",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c1", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"0b", X"f0", X"00", X"9d",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c5", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"24", X"bb", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"34", X"1c", X"00", X"00",
X"24", X"18", X"00", X"42", X"24", X"19", X"00", X"99",
X"00", X"00", X"00", X"0d", X"20", X"18", X"00", X"01",
X"24", X"17", X"00", X"42", X"03", X"37", X"b8", X"22",
X"12", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"33", X"59", X"00", X"7c",
X"24", X"17", X"00", X"24", X"03", X"37", X"b8", X"22",
X"12", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"17", X"00", X"02",
X"03", X"77", X"b8", X"22", X"12", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"18", X"00", X"42", X"24", X"19", X"00", X"99",
X"00", X"00", X"00", X"0c", X"20", X"18", X"00", X"01",
X"24", X"17", X"00", X"42", X"03", X"37", X"b8", X"22",
X"12", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"33", X"59", X"00", X"7c",
X"24", X"17", X"00", X"20", X"03", X"37", X"b8", X"22",
X"12", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"17", X"00", X"03",
X"03", X"77", X"b8", X"22", X"12", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"03", X"dc", X"f0", X"20", X"17", X"80", X"00", X"07",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c1", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"0b", X"f0", X"00", X"d7",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c5", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"24", X"da", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"34", X"1c", X"00", X"00",
X"24", X"09", X"80", X"10", X"24", X"02", X"00", X"01",
X"a1", X"22", X"00", X"00", X"24", X"02", X"00", X"42",
X"10", X"00", X"00", X"02", X"24", X"0b", X"00", X"79",
X"24", X"0c", X"00", X"85", X"24", X"04", X"00", X"04",
X"03", X"64", X"20", X"22", X"10", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"33", X"59", X"00", X"7c", X"24", X"04", X"00", X"00",
X"03", X"24", X"20", X"22", X"10", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"33", X"59", X"fc", X"00", X"24", X"04", X"04", X"00",
X"03", X"24", X"20", X"22", X"10", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"a1", X"20", X"00", X"00", X"24", X"02", X"00", X"10",
X"a1", X"22", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"24", X"0b", X"00", X"79",
X"00", X"00", X"00", X"00", X"24", X"0b", X"00", X"04",
X"03", X"6b", X"58", X"22", X"11", X"60", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"02", X"00", X"20", X"a1", X"22", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"24", X"0b", X"00", X"79", X"00", X"00", X"00", X"00",
X"24", X"04", X"00", X"05", X"03", X"64", X"20", X"22",
X"10", X"80", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"33", X"59", X"00", X"7c",
X"24", X"04", X"00", X"00", X"03", X"24", X"20", X"22",
X"10", X"80", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"33", X"59", X"fc", X"00",
X"34", X"04", X"80", X"00", X"03", X"24", X"20", X"22",
X"10", X"80", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"a1", X"20", X"00", X"00",
X"03", X"dc", X"f0", X"20", X"17", X"80", X"00", X"07",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c1", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"0b", X"f0", X"01", X"25",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c5", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"23", X"47", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"34", X"1c", X"00", X"00",
X"3c", X"02", X"12", X"34", X"34", X"42", X"56", X"78",
X"3c", X"03", X"45", X"67", X"34", X"63", X"89", X"a0",
X"3c", X"04", X"78", X"9a", X"34", X"84", X"bc", X"de",
X"3c", X"05", X"8a", X"bc", X"34", X"a5", X"de", X"f0",
X"24", X"09", X"80", X"20", X"ad", X"22", X"00", X"00",
X"ad", X"23", X"00", X"04", X"ad", X"24", X"00", X"08",
X"ad", X"25", X"00", X"0c", X"8d", X"2a", X"00", X"0c",
X"8d", X"2b", X"00", X"08", X"8d", X"2c", X"00", X"04",
X"8d", X"2d", X"00", X"00", X"00", X"4d", X"68", X"22",
X"11", X"a0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"00", X"6c", X"60", X"22",
X"11", X"80", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"00", X"8b", X"58", X"22",
X"11", X"60", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"00", X"aa", X"50", X"22",
X"11", X"40", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"03", X"dc", X"f0", X"20",
X"17", X"80", X"00", X"07", X"00", X"00", X"00", X"00",
X"3c", X"04", X"bf", X"c0", X"24", X"84", X"22", X"c1",
X"0f", X"f0", X"08", X"a1", X"00", X"00", X"00", X"00",
X"0b", X"f0", X"01", X"58", X"00", X"00", X"00", X"00",
X"3c", X"04", X"bf", X"c0", X"24", X"84", X"22", X"c5",
X"0f", X"f0", X"08", X"a1", X"00", X"00", X"00", X"00",
X"3c", X"04", X"bf", X"c0", X"24", X"84", X"23", X"85",
X"0f", X"f0", X"08", X"a1", X"00", X"00", X"00", X"00",
X"34", X"1c", X"00", X"00", X"3c", X"09", X"a0", X"00",
X"3c", X"02", X"12", X"34", X"34", X"42", X"56", X"78",
X"3c", X"03", X"45", X"67", X"34", X"63", X"89", X"a0",
X"3c", X"04", X"78", X"9a", X"34", X"84", X"bc", X"de",
X"3c", X"05", X"8a", X"bc", X"34", X"a5", X"de", X"f0",
X"ad", X"22", X"00", X"00", X"00", X"00", X"00", X"00",
X"34", X"07", X"42", X"42", X"8d", X"27", X"00", X"00",
X"00", X"e2", X"38", X"22", X"10", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"03", X"dc", X"f0", X"20", X"17", X"80", X"00", X"07",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c1", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"0b", X"f0", X"01", X"7b",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c5", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"23", X"09", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"34", X"1c", X"00", X"00",
X"3c", X"09", X"80", X"00", X"24", X"08", X"00", X"80",
X"bd", X"21", X"00", X"00", X"21", X"08", X"ff", X"ff",
X"15", X"00", X"ff", X"fd", X"21", X"29", X"00", X"20",
X"3c", X"05", X"90", X"00", X"8c", X"a4", X"00", X"04",
X"8c", X"a6", X"00", X"08", X"3c", X"14", X"00", X"08",
X"36", X"94", X"00", X"08", X"00", X"d4", X"a0", X"22",
X"12", X"80", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"3c", X"14", X"00", X"04",
X"36", X"94", X"00", X"04", X"00", X"94", X"a0", X"22",
X"12", X"80", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"00", X"00", X"00", X"00",
X"3c", X"03", X"80", X"00", X"3c", X"06", X"18", X"02",
X"34", X"c6", X"68", X"09", X"ac", X"66", X"00", X"08",
X"8c", X"67", X"00", X"08", X"00", X"e6", X"30", X"22",
X"10", X"c0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"00", X"00", X"00", X"00",
X"34", X"06", X"00", X"42", X"34", X"08", X"00", X"42",
X"34", X"0a", X"00", X"42", X"34", X"0c", X"00", X"42",
X"a0", X"66", X"00", X"00", X"80", X"67", X"00", X"00",
X"a0", X"68", X"00", X"40", X"80", X"69", X"00", X"40",
X"24", X"1a", X"00", X"42", X"14", X"fa", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"1a", X"00", X"09",
X"00", X"00", X"00", X"00", X"a0", X"6a", X"00", X"70",
X"a0", X"6c", X"00", X"90", X"80", X"6d", X"00", X"90",
X"80", X"6b", X"00", X"70", X"15", X"7a", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ba", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"06", X"00", X"34", X"34", X"08", X"00", X"34",
X"34", X"0a", X"00", X"34", X"34", X"0c", X"00", X"34",
X"a0", X"66", X"00", X"01", X"80", X"67", X"00", X"01",
X"a0", X"68", X"00", X"41", X"80", X"69", X"00", X"41",
X"24", X"1a", X"00", X"34", X"14", X"fa", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"1a", X"00", X"09",
X"00", X"00", X"00", X"00", X"a0", X"6a", X"00", X"71",
X"a0", X"6c", X"00", X"91", X"80", X"6d", X"00", X"91",
X"80", X"6b", X"00", X"71", X"15", X"7a", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ba", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"06", X"00", X"74", X"34", X"08", X"00", X"74",
X"34", X"0a", X"00", X"74", X"34", X"0c", X"00", X"74",
X"a0", X"66", X"00", X"02", X"80", X"67", X"00", X"02",
X"a0", X"68", X"00", X"42", X"80", X"69", X"00", X"42",
X"24", X"1a", X"00", X"74", X"14", X"fa", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"1a", X"00", X"09",
X"00", X"00", X"00", X"00", X"a0", X"6a", X"00", X"72",
X"a0", X"6c", X"00", X"92", X"80", X"6d", X"00", X"92",
X"80", X"6b", X"00", X"72", X"15", X"7a", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ba", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"06", X"00", X"89", X"34", X"08", X"00", X"89",
X"34", X"0a", X"00", X"89", X"34", X"0c", X"00", X"89",
X"a0", X"66", X"00", X"03", X"90", X"67", X"00", X"03",
X"a0", X"68", X"00", X"43", X"90", X"69", X"00", X"43",
X"24", X"1a", X"00", X"89", X"14", X"fa", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"1a", X"00", X"09",
X"00", X"00", X"00", X"00", X"a0", X"6a", X"00", X"73",
X"a0", X"6c", X"00", X"93", X"90", X"6d", X"00", X"93",
X"90", X"6b", X"00", X"73", X"15", X"7a", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ba", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"06", X"00", X"24", X"34", X"08", X"00", X"24",
X"34", X"0a", X"00", X"24", X"34", X"0c", X"00", X"24",
X"a0", X"66", X"01", X"33", X"80", X"67", X"01", X"33",
X"a0", X"68", X"01", X"73", X"80", X"69", X"01", X"73",
X"24", X"1a", X"00", X"24", X"14", X"fa", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"1a", X"00", X"09",
X"00", X"00", X"00", X"00", X"a0", X"6a", X"01", X"a3",
X"a0", X"6c", X"01", X"c3", X"80", X"6d", X"01", X"c3",
X"80", X"6b", X"01", X"a3", X"15", X"7a", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ba", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"06", X"00", X"43", X"34", X"08", X"00", X"43",
X"34", X"0a", X"00", X"43", X"34", X"0c", X"00", X"43",
X"a0", X"66", X"01", X"31", X"80", X"67", X"01", X"31",
X"a0", X"68", X"01", X"71", X"80", X"69", X"01", X"71",
X"24", X"1a", X"00", X"43", X"14", X"fa", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"1a", X"00", X"09",
X"00", X"00", X"00", X"00", X"a0", X"6a", X"01", X"a1",
X"a0", X"6c", X"01", X"c1", X"80", X"6d", X"01", X"c1",
X"80", X"6b", X"01", X"a1", X"15", X"7a", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ba", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"06", X"00", X"97", X"34", X"08", X"00", X"97",
X"34", X"0a", X"00", X"97", X"34", X"0c", X"00", X"97",
X"a0", X"66", X"01", X"32", X"90", X"67", X"01", X"32",
X"a0", X"68", X"01", X"72", X"90", X"69", X"01", X"72",
X"24", X"1a", X"00", X"97", X"14", X"fa", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"1a", X"00", X"09",
X"00", X"00", X"00", X"00", X"a0", X"6a", X"01", X"a2",
X"a0", X"6c", X"01", X"c2", X"90", X"6d", X"01", X"c2",
X"90", X"6b", X"01", X"a2", X"15", X"7a", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ba", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"06", X"00", X"77", X"34", X"08", X"00", X"77",
X"34", X"0a", X"00", X"77", X"34", X"0c", X"00", X"77",
X"a0", X"66", X"01", X"30", X"80", X"67", X"01", X"30",
X"a0", X"68", X"01", X"70", X"80", X"69", X"01", X"70",
X"24", X"1a", X"00", X"77", X"14", X"fa", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"1a", X"00", X"09",
X"00", X"00", X"00", X"00", X"a0", X"6a", X"01", X"a0",
X"a0", X"6c", X"01", X"c0", X"80", X"6d", X"01", X"c0",
X"80", X"6b", X"01", X"a0", X"15", X"7a", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ba", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"06", X"00", X"24", X"34", X"08", X"00", X"24",
X"34", X"0a", X"00", X"24", X"34", X"0c", X"00", X"24",
X"a0", X"66", X"02", X"33", X"80", X"67", X"02", X"33",
X"a0", X"68", X"02", X"73", X"80", X"69", X"02", X"73",
X"24", X"1a", X"00", X"24", X"14", X"fa", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"1a", X"00", X"09",
X"00", X"00", X"00", X"00", X"a0", X"6a", X"02", X"a3",
X"a0", X"6c", X"02", X"c3", X"80", X"6d", X"02", X"c3",
X"80", X"6b", X"02", X"a3", X"15", X"7a", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ba", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"06", X"00", X"d3", X"34", X"08", X"00", X"d3",
X"34", X"0a", X"00", X"d3", X"34", X"0c", X"00", X"d3",
X"a0", X"66", X"03", X"31", X"90", X"67", X"03", X"31",
X"a0", X"68", X"03", X"71", X"90", X"69", X"03", X"71",
X"24", X"1a", X"00", X"d3", X"14", X"fa", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"1a", X"00", X"09",
X"00", X"00", X"00", X"00", X"a0", X"6a", X"03", X"a1",
X"a0", X"6c", X"03", X"c1", X"90", X"6d", X"03", X"c1",
X"90", X"6b", X"03", X"a1", X"15", X"7a", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ba", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"06", X"00", X"47", X"34", X"08", X"00", X"47",
X"34", X"0a", X"00", X"47", X"34", X"0c", X"00", X"47",
X"a0", X"66", X"02", X"32", X"80", X"67", X"02", X"32",
X"a0", X"68", X"02", X"72", X"80", X"69", X"02", X"72",
X"24", X"1a", X"00", X"47", X"14", X"fa", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"1a", X"00", X"09",
X"00", X"00", X"00", X"00", X"a0", X"6a", X"02", X"a2",
X"a0", X"6c", X"02", X"c2", X"80", X"6d", X"02", X"c2",
X"80", X"6b", X"02", X"a2", X"15", X"7a", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ba", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"06", X"00", X"77", X"34", X"08", X"00", X"77",
X"34", X"0a", X"00", X"77", X"34", X"0c", X"00", X"77",
X"a0", X"66", X"03", X"30", X"80", X"67", X"03", X"30",
X"a0", X"68", X"03", X"70", X"80", X"69", X"03", X"70",
X"24", X"1a", X"00", X"77", X"14", X"fa", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"1a", X"00", X"09",
X"00", X"00", X"00", X"00", X"a0", X"6a", X"03", X"a0",
X"a0", X"6c", X"03", X"c0", X"80", X"6d", X"03", X"c0",
X"80", X"6b", X"03", X"a0", X"15", X"7a", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ba", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"03", X"dc", X"f0", X"20", X"17", X"80", X"00", X"07",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c1", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"0b", X"f0", X"02", X"b5",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c5", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"23", X"28", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"34", X"1c", X"00", X"00",
X"3c", X"09", X"80", X"00", X"24", X"08", X"00", X"80",
X"bd", X"20", X"00", X"00", X"21", X"08", X"ff", X"ff",
X"15", X"00", X"ff", X"fd", X"21", X"29", X"00", X"20",
X"3c", X"09", X"80", X"00", X"3c", X"03", X"03", X"e0",
X"34", X"63", X"00", X"08", X"ad", X"23", X"00", X"00",
X"ad", X"20", X"00", X"04", X"00", X"00", X"00", X"00",
X"01", X"20", X"f8", X"09", X"00", X"00", X"00", X"00",
X"03", X"dc", X"f0", X"20", X"17", X"80", X"00", X"07",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c1", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"0b", X"f0", X"02", X"d5",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c5", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"23", X"a4", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"34", X"1c", X"00", X"00",
X"3c", X"02", X"12", X"34", X"34", X"42", X"56", X"78",
X"3c", X"03", X"45", X"67", X"34", X"63", X"89", X"a0",
X"3c", X"04", X"78", X"9a", X"34", X"84", X"bc", X"de",
X"3c", X"05", X"8a", X"bc", X"34", X"a5", X"de", X"f0",
X"00", X"43", X"30", X"20", X"3c", X"09", X"57", X"9b",
X"35", X"29", X"e0", X"18", X"00", X"c9", X"48", X"22",
X"11", X"20", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"00", X"85", X"30", X"20",
X"3c", X"14", X"03", X"57", X"36", X"94", X"9b", X"ce",
X"00", X"d4", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"85", X"30", X"20", X"20", X"c6", X"d0", X"34",
X"3c", X"14", X"03", X"57", X"36", X"94", X"6c", X"02",
X"00", X"d4", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"85", X"30", X"20", X"20", X"c6", X"70", X"43",
X"3c", X"14", X"03", X"58", X"36", X"94", X"0c", X"11",
X"00", X"d4", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"85", X"30", X"20", X"24", X"c6", X"d0", X"34",
X"3c", X"14", X"03", X"57", X"36", X"94", X"6c", X"02",
X"00", X"d4", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"85", X"30", X"20", X"24", X"c6", X"70", X"43",
X"3c", X"14", X"03", X"58", X"36", X"94", X"0c", X"11",
X"00", X"d4", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"43", X"30", X"21", X"3c", X"09", X"57", X"9b",
X"35", X"29", X"e0", X"18", X"00", X"c9", X"48", X"22",
X"11", X"20", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"00", X"85", X"30", X"21",
X"3c", X"14", X"03", X"57", X"36", X"94", X"9b", X"ce",
X"00", X"d4", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"85", X"30", X"21", X"20", X"c6", X"d0", X"34",
X"3c", X"14", X"03", X"57", X"36", X"94", X"6c", X"02",
X"00", X"d4", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"85", X"30", X"21", X"20", X"c6", X"70", X"43",
X"3c", X"14", X"03", X"58", X"36", X"94", X"0c", X"11",
X"00", X"d4", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"43", X"30", X"22", X"3c", X"09", X"cc", X"cc",
X"35", X"29", X"cc", X"d8", X"00", X"c9", X"48", X"22",
X"11", X"20", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"00", X"85", X"30", X"22",
X"3c", X"14", X"ed", X"dd", X"36", X"94", X"dd", X"ee",
X"00", X"d4", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"43", X"30", X"23", X"3c", X"09", X"cc", X"cc",
X"35", X"29", X"cc", X"d8", X"00", X"c9", X"48", X"22",
X"11", X"20", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"00", X"85", X"30", X"23",
X"3c", X"14", X"ed", X"dd", X"36", X"94", X"dd", X"ee",
X"00", X"d4", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"03", X"dc", X"f0", X"20", X"17", X"80", X"00", X"07",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c1", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"0b", X"f0", X"03", X"57",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c5", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"23", X"c3", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"34", X"1c", X"00", X"00",
X"3c", X"02", X"12", X"34", X"34", X"42", X"56", X"78",
X"3c", X"03", X"45", X"67", X"34", X"63", X"89", X"a0",
X"3c", X"04", X"78", X"9a", X"34", X"84", X"bc", X"de",
X"3c", X"05", X"8a", X"bc", X"34", X"a5", X"de", X"f0",
X"00", X"43", X"40", X"2a", X"24", X"14", X"00", X"01",
X"01", X"14", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"62", X"40", X"2a", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"85", X"40", X"2a", X"24", X"14", X"00", X"00",
X"01", X"14", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"a4", X"40", X"2a", X"24", X"14", X"00", X"01",
X"01", X"14", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"43", X"40", X"2b", X"24", X"14", X"00", X"01",
X"01", X"14", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"62", X"40", X"2b", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"85", X"40", X"2b", X"24", X"14", X"00", X"01",
X"01", X"14", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"a4", X"40", X"2b", X"24", X"14", X"00", X"00",
X"01", X"14", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"02", X"70", X"43", X"24", X"03", X"b1", X"e0",
X"28", X"48", X"7f", X"ff", X"24", X"14", X"00", X"01",
X"01", X"14", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"28", X"48", X"70", X"00", X"24", X"14", X"00", X"00",
X"01", X"14", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"28", X"68", X"80", X"00", X"24", X"14", X"00", X"00",
X"01", X"14", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"28", X"68", X"d8", X"f0", X"24", X"14", X"00", X"01",
X"01", X"14", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"02", X"70", X"43", X"34", X"03", X"80", X"80",
X"2c", X"48", X"7f", X"ff", X"24", X"14", X"00", X"01",
X"01", X"14", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"2c", X"48", X"70", X"00", X"24", X"14", X"00", X"00",
X"01", X"14", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"2c", X"68", X"80", X"00", X"24", X"14", X"00", X"00",
X"01", X"14", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"2c", X"68", X"d8", X"f0", X"24", X"14", X"00", X"01",
X"01", X"14", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"03", X"dc", X"f0", X"20", X"17", X"80", X"00", X"07",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c1", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"0b", X"f0", X"03", X"d1",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c5", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"24", X"20", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"34", X"1c", X"00", X"00",
X"3c", X"02", X"12", X"34", X"34", X"42", X"56", X"78",
X"3c", X"03", X"45", X"67", X"34", X"63", X"89", X"a0",
X"3c", X"04", X"78", X"9a", X"34", X"84", X"bc", X"de",
X"3c", X"05", X"8a", X"bc", X"34", X"a5", X"de", X"f0",
X"00", X"43", X"30", X"24", X"3c", X"09", X"00", X"24",
X"35", X"29", X"00", X"20", X"00", X"c9", X"48", X"22",
X"11", X"20", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"00", X"85", X"30", X"24",
X"3c", X"14", X"08", X"98", X"36", X"94", X"9c", X"d0",
X"00", X"d4", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"30", X"a6", X"d0", X"34", X"34", X"14", X"d0", X"30",
X"00", X"d4", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"85", X"30", X"25", X"3c", X"14", X"fa", X"be",
X"36", X"94", X"fe", X"fe", X"00", X"d4", X"a0", X"22",
X"12", X"80", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"34", X"a6", X"d0", X"34",
X"3c", X"14", X"8a", X"bc", X"36", X"94", X"de", X"f4",
X"00", X"d4", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"85", X"30", X"26", X"3c", X"14", X"f2", X"26",
X"36", X"94", X"62", X"2e", X"00", X"d4", X"a0", X"22",
X"12", X"80", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"38", X"a6", X"d0", X"34",
X"3c", X"14", X"8a", X"bc", X"36", X"94", X"0e", X"c4",
X"00", X"d4", X"a0", X"22", X"12", X"80", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"85", X"30", X"27", X"3c", X"14", X"05", X"41",
X"36", X"94", X"01", X"01", X"00", X"d4", X"a0", X"22",
X"12", X"80", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"03", X"dc", X"f0", X"20",
X"17", X"80", X"00", X"07", X"00", X"00", X"00", X"00",
X"3c", X"04", X"bf", X"c0", X"24", X"84", X"22", X"c1",
X"0f", X"f0", X"08", X"a1", X"00", X"00", X"00", X"00",
X"0b", X"f0", X"04", X"22", X"00", X"00", X"00", X"00",
X"3c", X"04", X"bf", X"c0", X"24", X"84", X"22", X"c5",
X"0f", X"f0", X"08", X"a1", X"00", X"00", X"00", X"00",
X"3c", X"04", X"bf", X"c0", X"24", X"84", X"24", X"3f",
X"0f", X"f0", X"08", X"a1", X"00", X"00", X"00", X"00",
X"34", X"1c", X"00", X"00", X"24", X"04", X"01", X"00",
X"24", X"05", X"00", X"20", X"00", X"85", X"00", X"1b",
X"00", X"00", X"40", X"12", X"00", X"00", X"48", X"10",
X"24", X"07", X"00", X"08", X"01", X"07", X"38", X"22",
X"10", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"06", X"00", X"00",
X"01", X"26", X"30", X"22", X"10", X"c0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"04", X"01", X"01", X"24", X"05", X"00", X"20",
X"00", X"85", X"00", X"1b", X"00", X"00", X"40", X"12",
X"00", X"00", X"48", X"10", X"24", X"07", X"00", X"08",
X"01", X"07", X"38", X"22", X"10", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"06", X"00", X"01", X"01", X"26", X"30", X"22",
X"10", X"c0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"04", X"01", X"01",
X"24", X"05", X"00", X"20", X"00", X"85", X"00", X"1a",
X"00", X"00", X"40", X"12", X"00", X"00", X"48", X"10",
X"24", X"07", X"00", X"08", X"01", X"07", X"38", X"22",
X"10", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"06", X"00", X"01",
X"01", X"26", X"30", X"22", X"10", X"c0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"04", X"01", X"00", X"24", X"05", X"ff", X"f9",
X"00", X"85", X"00", X"1a", X"00", X"00", X"40", X"12",
X"00", X"00", X"48", X"10", X"24", X"07", X"ff", X"dc",
X"01", X"07", X"38", X"22", X"10", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"06", X"00", X"04", X"01", X"26", X"30", X"22",
X"10", X"c0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"04", X"ff", X"00",
X"24", X"05", X"00", X"07", X"00", X"85", X"00", X"1a",
X"00", X"00", X"40", X"12", X"00", X"00", X"48", X"10",
X"24", X"07", X"ff", X"dc", X"01", X"07", X"38", X"22",
X"10", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"06", X"ff", X"fc",
X"01", X"26", X"30", X"22", X"10", X"c0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"04", X"ff", X"01", X"24", X"05", X"00", X"07",
X"00", X"85", X"00", X"1a", X"00", X"00", X"40", X"12",
X"00", X"00", X"48", X"10", X"24", X"07", X"ff", X"dc",
X"01", X"07", X"38", X"22", X"10", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"06", X"ff", X"fd", X"01", X"26", X"30", X"22",
X"10", X"c0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"04", X"00", X"10",
X"24", X"05", X"00", X"20", X"00", X"85", X"00", X"19",
X"00", X"00", X"40", X"12", X"00", X"00", X"48", X"10",
X"24", X"07", X"02", X"00", X"01", X"07", X"38", X"22",
X"10", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"07", X"00", X"00",
X"01", X"27", X"38", X"22", X"10", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"3c", X"04", X"80", X"00", X"34", X"84", X"00", X"10",
X"24", X"05", X"00", X"20", X"00", X"85", X"00", X"19",
X"00", X"00", X"40", X"12", X"00", X"00", X"48", X"10",
X"24", X"07", X"02", X"00", X"01", X"07", X"38", X"22",
X"10", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"07", X"00", X"10",
X"01", X"27", X"38", X"22", X"10", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"04", X"00", X"10", X"3c", X"05", X"80", X"00",
X"34", X"a5", X"00", X"20", X"00", X"85", X"00", X"19",
X"00", X"00", X"40", X"12", X"00", X"00", X"48", X"10",
X"24", X"07", X"02", X"00", X"01", X"07", X"38", X"22",
X"10", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"07", X"00", X"08",
X"01", X"27", X"38", X"22", X"10", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"3c", X"04", X"80", X"00", X"34", X"84", X"00", X"10",
X"24", X"05", X"ff", X"ff", X"00", X"85", X"00", X"19",
X"00", X"00", X"40", X"12", X"00", X"00", X"48", X"10",
X"3c", X"07", X"7f", X"ff", X"34", X"e7", X"ff", X"f0",
X"01", X"07", X"38", X"22", X"10", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"3c", X"07", X"80", X"00", X"34", X"e7", X"00", X"0f",
X"01", X"27", X"38", X"22", X"10", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"04", X"00", X"10", X"24", X"05", X"00", X"20",
X"00", X"85", X"00", X"18", X"00", X"00", X"40", X"12",
X"00", X"00", X"48", X"10", X"24", X"07", X"02", X"00",
X"01", X"07", X"38", X"22", X"10", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"07", X"00", X"00", X"01", X"27", X"38", X"22",
X"10", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"3c", X"04", X"80", X"00",
X"34", X"84", X"00", X"10", X"24", X"05", X"00", X"20",
X"00", X"85", X"00", X"18", X"00", X"00", X"40", X"12",
X"00", X"00", X"48", X"10", X"24", X"07", X"02", X"00",
X"01", X"07", X"38", X"22", X"10", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"07", X"ff", X"f0", X"01", X"27", X"38", X"22",
X"10", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"04", X"00", X"20",
X"3c", X"05", X"80", X"00", X"34", X"a5", X"00", X"10",
X"00", X"85", X"00", X"18", X"00", X"00", X"40", X"12",
X"00", X"00", X"48", X"10", X"24", X"07", X"02", X"00",
X"01", X"07", X"38", X"22", X"10", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"07", X"ff", X"f0", X"01", X"27", X"38", X"22",
X"10", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"3c", X"04", X"80", X"00",
X"34", X"84", X"00", X"10", X"3c", X"05", X"80", X"00",
X"34", X"a5", X"00", X"20", X"00", X"85", X"00", X"18",
X"00", X"00", X"40", X"12", X"00", X"00", X"48", X"10",
X"24", X"07", X"02", X"00", X"01", X"07", X"38", X"22",
X"10", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"3c", X"07", X"3f", X"ff",
X"34", X"e7", X"ff", X"e8", X"01", X"27", X"38", X"22",
X"10", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"03", X"dc", X"f0", X"20",
X"17", X"80", X"00", X"07", X"00", X"00", X"00", X"00",
X"3c", X"04", X"bf", X"c0", X"24", X"84", X"22", X"c1",
X"0f", X"f0", X"08", X"a1", X"00", X"00", X"00", X"00",
X"0b", X"f0", X"05", X"10", X"00", X"00", X"00", X"00",
X"3c", X"04", X"bf", X"c0", X"24", X"84", X"22", X"c5",
X"0f", X"f0", X"08", X"a1", X"00", X"00", X"00", X"00",
X"3c", X"04", X"bf", X"c0", X"24", X"84", X"23", X"e2",
X"0f", X"f0", X"08", X"a1", X"00", X"00", X"00", X"00",
X"34", X"1c", X"00", X"00", X"3c", X"02", X"12", X"34",
X"34", X"42", X"56", X"78", X"3c", X"03", X"45", X"67",
X"34", X"63", X"89", X"a0", X"3c", X"04", X"78", X"9a",
X"34", X"84", X"bc", X"de", X"3c", X"05", X"8a", X"bc",
X"34", X"a5", X"de", X"f0", X"34", X"19", X"00", X"00",
X"10", X"42", X"00", X"05", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"10", X"42", X"00", X"05",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"10", X"42", X"ff", X"fc", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"24", X"17", X"00", X"03",
X"03", X"37", X"b8", X"22", X"12", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"19", X"00", X"00", X"10", X"43", X"00", X"03",
X"23", X"39", X"00", X"01", X"10", X"00", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"17", X"00", X"01", X"03", X"37", X"b8", X"22",
X"12", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"34", X"19", X"00", X"00",
X"04", X"81", X"00", X"05", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"04", X"81", X"00", X"05",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"04", X"81", X"ff", X"fc", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"24", X"17", X"00", X"03",
X"03", X"37", X"b8", X"22", X"12", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"19", X"00", X"00", X"04", X"01", X"00", X"05",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"04", X"01", X"00", X"05", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"04", X"01", X"ff", X"fc",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"24", X"17", X"00", X"03", X"03", X"37", X"b8", X"22",
X"12", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"34", X"19", X"00", X"00",
X"04", X"a1", X"00", X"03", X"23", X"39", X"00", X"01",
X"10", X"00", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"17", X"00", X"01",
X"03", X"37", X"b8", X"22", X"12", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"19", X"00", X"00", X"3c", X"18", X"bf", X"c0",
X"27", X"18", X"15", X"94", X"04", X"91", X"00", X"0b",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"03", X"f8", X"c0", X"22", X"13", X"00", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"3c", X"18", X"bf", X"c0", X"27", X"18", X"15", X"b8",
X"04", X"91", X"00", X"0b", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"03", X"f8", X"c0", X"22",
X"13", X"00", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"3c", X"18", X"bf", X"c0",
X"27", X"18", X"15", X"dc", X"04", X"91", X"ff", X"f0",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"03", X"f8", X"c0", X"22", X"13", X"00", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"17", X"00", X"03", X"03", X"37", X"b8", X"22",
X"12", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"34", X"19", X"00", X"00",
X"3c", X"18", X"bf", X"c0", X"27", X"18", X"16", X"18",
X"04", X"11", X"00", X"0b", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"03", X"f8", X"c0", X"22",
X"13", X"00", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"3c", X"18", X"bf", X"c0",
X"27", X"18", X"16", X"3c", X"04", X"11", X"00", X"0b",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"03", X"f8", X"c0", X"22", X"13", X"00", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"3c", X"18", X"bf", X"c0", X"27", X"18", X"16", X"60",
X"04", X"11", X"ff", X"f0", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"03", X"f8", X"c0", X"22",
X"13", X"00", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"17", X"00", X"03",
X"03", X"37", X"b8", X"22", X"12", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"19", X"00", X"00", X"04", X"b1", X"00", X"03",
X"23", X"39", X"00", X"01", X"10", X"00", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"17", X"00", X"01", X"03", X"37", X"b8", X"22",
X"12", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"34", X"19", X"00", X"00",
X"1c", X"80", X"00", X"05", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"1c", X"80", X"00", X"05",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"1c", X"80", X"ff", X"fc", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"24", X"17", X"00", X"03",
X"03", X"37", X"b8", X"22", X"12", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"19", X"00", X"00", X"1c", X"00", X"00", X"03",
X"23", X"39", X"00", X"01", X"10", X"00", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"17", X"00", X"01", X"03", X"37", X"b8", X"22",
X"12", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"34", X"19", X"00", X"00",
X"1c", X"a0", X"00", X"03", X"23", X"39", X"00", X"01",
X"10", X"00", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"17", X"00", X"01",
X"03", X"37", X"b8", X"22", X"12", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"19", X"00", X"00", X"18", X"80", X"00", X"03",
X"23", X"39", X"00", X"01", X"10", X"00", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"17", X"00", X"01", X"03", X"37", X"b8", X"22",
X"12", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"34", X"19", X"00", X"00",
X"18", X"00", X"00", X"05", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"18", X"00", X"00", X"05",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"18", X"00", X"ff", X"fc", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"24", X"17", X"00", X"03",
X"03", X"37", X"b8", X"22", X"12", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"19", X"00", X"00", X"18", X"a0", X"00", X"05",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"18", X"a0", X"00", X"05", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"18", X"a0", X"ff", X"fc",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"24", X"17", X"00", X"03", X"03", X"37", X"b8", X"22",
X"12", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"34", X"19", X"00", X"00",
X"04", X"80", X"00", X"03", X"23", X"39", X"00", X"01",
X"10", X"00", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"17", X"00", X"01",
X"03", X"37", X"b8", X"22", X"12", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"19", X"00", X"00", X"04", X"00", X"00", X"03",
X"23", X"39", X"00", X"01", X"10", X"00", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"17", X"00", X"01", X"03", X"37", X"b8", X"22",
X"12", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"34", X"19", X"00", X"00",
X"04", X"a0", X"00", X"05", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"04", X"a0", X"00", X"05",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"04", X"a0", X"ff", X"fc", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"24", X"17", X"00", X"03",
X"03", X"37", X"b8", X"22", X"12", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"19", X"00", X"00", X"04", X"90", X"00", X"03",
X"23", X"39", X"00", X"01", X"10", X"00", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"17", X"00", X"01", X"03", X"37", X"b8", X"22",
X"12", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"34", X"19", X"00", X"00",
X"04", X"10", X"00", X"03", X"23", X"39", X"00", X"01",
X"10", X"00", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"24", X"17", X"00", X"01",
X"03", X"37", X"b8", X"22", X"12", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"19", X"00", X"00", X"3c", X"18", X"bf", X"c0",
X"27", X"18", X"18", X"ec", X"04", X"b0", X"00", X"0b",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"03", X"f8", X"c0", X"22", X"13", X"00", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"3c", X"18", X"bf", X"c0", X"27", X"18", X"19", X"10",
X"04", X"b0", X"00", X"0b", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"03", X"f8", X"c0", X"22",
X"13", X"00", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"3c", X"18", X"bf", X"c0",
X"27", X"18", X"19", X"34", X"04", X"b0", X"ff", X"f0",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"03", X"f8", X"c0", X"22", X"13", X"00", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"17", X"00", X"03", X"03", X"37", X"b8", X"22",
X"12", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"34", X"19", X"00", X"00",
X"14", X"43", X"00", X"05", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"14", X"43", X"00", X"05",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"14", X"43", X"ff", X"fc", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"24", X"17", X"00", X"03",
X"03", X"37", X"b8", X"22", X"12", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"19", X"00", X"00", X"14", X"42", X"00", X"03",
X"23", X"39", X"00", X"01", X"10", X"00", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"17", X"00", X"01", X"03", X"37", X"b8", X"22",
X"12", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"03", X"dc", X"f0", X"20",
X"17", X"80", X"00", X"07", X"00", X"00", X"00", X"00",
X"3c", X"04", X"bf", X"c0", X"24", X"84", X"22", X"c1",
X"0f", X"f0", X"08", X"a1", X"00", X"00", X"00", X"00",
X"0b", X"f0", X"06", X"7e", X"00", X"00", X"00", X"00",
X"3c", X"04", X"bf", X"c0", X"24", X"84", X"22", X"c5",
X"0f", X"f0", X"08", X"a1", X"00", X"00", X"00", X"00",
X"3c", X"04", X"bf", X"c0", X"24", X"84", X"24", X"01",
X"0f", X"f0", X"08", X"a1", X"00", X"00", X"00", X"00",
X"34", X"1c", X"00", X"00", X"3c", X"02", X"12", X"34",
X"34", X"42", X"56", X"78", X"3c", X"03", X"45", X"67",
X"34", X"63", X"89", X"a0", X"3c", X"04", X"78", X"9a",
X"34", X"84", X"bc", X"de", X"3c", X"05", X"8a", X"bc",
X"34", X"a5", X"de", X"f0", X"34", X"19", X"00", X"00",
X"0b", X"f0", X"06", X"92", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"0b", X"f0", X"06", X"95",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"0b", X"f0", X"06", X"8f", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"24", X"17", X"00", X"03",
X"03", X"37", X"b8", X"22", X"12", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"19", X"00", X"00", X"3c", X"18", X"bf", X"c0",
X"27", X"18", X"1a", X"7c", X"0f", X"f0", X"06", X"a9",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"03", X"f8", X"c0", X"22", X"13", X"00", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"3c", X"18", X"bf", X"c0", X"27", X"18", X"1a", X"a0",
X"0f", X"f0", X"06", X"b2", X"23", X"39", X"00", X"01",
X"23", X"9c", X"00", X"01", X"03", X"f8", X"c0", X"22",
X"13", X"00", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"3c", X"18", X"bf", X"c0",
X"27", X"18", X"1a", X"c4", X"0f", X"f0", X"06", X"a0",
X"23", X"39", X"00", X"01", X"23", X"9c", X"00", X"01",
X"03", X"f8", X"c0", X"22", X"13", X"00", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"17", X"00", X"03", X"03", X"37", X"b8", X"22",
X"12", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"03", X"dc", X"f0", X"20",
X"17", X"80", X"00", X"07", X"00", X"00", X"00", X"00",
X"3c", X"04", X"bf", X"c0", X"24", X"84", X"22", X"c1",
X"0f", X"f0", X"08", X"a1", X"00", X"00", X"00", X"00",
X"0b", X"f0", X"06", X"c8", X"00", X"00", X"00", X"00",
X"3c", X"04", X"bf", X"c0", X"24", X"84", X"22", X"c5",
X"0f", X"f0", X"08", X"a1", X"00", X"00", X"00", X"00",
X"3c", X"04", X"bf", X"c0", X"24", X"84", X"24", X"7d",
X"0f", X"f0", X"08", X"a1", X"00", X"00", X"00", X"00",
X"34", X"1c", X"00", X"00", X"3c", X"02", X"12", X"34",
X"34", X"42", X"56", X"78", X"3c", X"03", X"45", X"67",
X"34", X"63", X"89", X"a0", X"3c", X"04", X"78", X"9a",
X"34", X"84", X"bc", X"de", X"3c", X"05", X"8a", X"bc",
X"34", X"a5", X"de", X"f0", X"3c", X"11", X"a0", X"00",
X"34", X"06", X"00", X"42", X"34", X"08", X"00", X"42",
X"34", X"0a", X"00", X"42", X"34", X"0c", X"00", X"42",
X"a2", X"26", X"00", X"10", X"82", X"27", X"00", X"10",
X"a2", X"28", X"00", X"50", X"82", X"29", X"00", X"50",
X"24", X"1a", X"00", X"42", X"14", X"fa", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"1a", X"00", X"09",
X"00", X"00", X"00", X"00", X"a2", X"2a", X"00", X"80",
X"a2", X"2c", X"00", X"a0", X"82", X"2d", X"00", X"a0",
X"82", X"2b", X"00", X"80", X"15", X"7a", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ba", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"06", X"00", X"c3", X"34", X"08", X"00", X"c3",
X"34", X"0a", X"00", X"c3", X"34", X"0c", X"00", X"c3",
X"a2", X"26", X"00", X"21", X"92", X"27", X"00", X"21",
X"a2", X"28", X"00", X"61", X"92", X"29", X"00", X"61",
X"24", X"1a", X"00", X"c3", X"14", X"fa", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"1a", X"00", X"09",
X"00", X"00", X"00", X"00", X"a2", X"2a", X"00", X"91",
X"a2", X"2c", X"00", X"b1", X"92", X"2d", X"00", X"b1",
X"92", X"2b", X"00", X"91", X"15", X"7a", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ba", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"06", X"00", X"44", X"34", X"08", X"00", X"44",
X"34", X"0a", X"00", X"44", X"34", X"0c", X"00", X"44",
X"a2", X"26", X"00", X"32", X"82", X"27", X"00", X"32",
X"a2", X"28", X"00", X"72", X"82", X"29", X"00", X"72",
X"24", X"1a", X"00", X"44", X"14", X"fa", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"1a", X"00", X"09",
X"00", X"00", X"00", X"00", X"a2", X"2a", X"00", X"a2",
X"a2", X"2c", X"00", X"c2", X"82", X"2d", X"00", X"c2",
X"82", X"2b", X"00", X"a2", X"15", X"7a", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ba", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"06", X"00", X"85", X"34", X"08", X"00", X"85",
X"34", X"0a", X"00", X"85", X"34", X"0c", X"00", X"85",
X"a2", X"26", X"00", X"43", X"92", X"27", X"00", X"43",
X"a2", X"28", X"00", X"83", X"92", X"29", X"00", X"83",
X"24", X"1a", X"00", X"85", X"14", X"fa", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"1a", X"00", X"09",
X"00", X"00", X"00", X"00", X"a2", X"2a", X"00", X"b3",
X"a2", X"2c", X"00", X"d3", X"92", X"2d", X"00", X"d3",
X"92", X"2b", X"00", X"b3", X"15", X"7a", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ba", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"3c", X"06", X"39", X"40", X"34", X"c6", X"41", X"42",
X"3c", X"08", X"39", X"40", X"35", X"08", X"41", X"42",
X"3c", X"0a", X"39", X"40", X"35", X"4a", X"41", X"42",
X"3c", X"0c", X"39", X"40", X"35", X"8c", X"41", X"42",
X"3c", X"0e", X"39", X"40", X"35", X"ce", X"41", X"42",
X"ae", X"26", X"00", X"00", X"8e", X"27", X"00", X"00",
X"ae", X"28", X"00", X"40", X"8e", X"29", X"00", X"40",
X"14", X"ee", X"00", X"0b", X"00", X"00", X"00", X"00",
X"15", X"2e", X"00", X"09", X"00", X"00", X"00", X"00",
X"ae", X"2a", X"00", X"70", X"ae", X"2c", X"00", X"90",
X"8e", X"2d", X"00", X"90", X"8e", X"2b", X"00", X"70",
X"15", X"6e", X"00", X"03", X"00", X"00", X"00", X"00",
X"11", X"ae", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"3c", X"06", X"01", X"23",
X"34", X"c6", X"45", X"67", X"3c", X"08", X"01", X"23",
X"35", X"08", X"45", X"67", X"3c", X"0a", X"01", X"23",
X"35", X"4a", X"45", X"67", X"3c", X"0c", X"01", X"23",
X"35", X"8c", X"45", X"67", X"3c", X"0e", X"01", X"23",
X"35", X"ce", X"45", X"67", X"ae", X"26", X"00", X"04",
X"8e", X"27", X"00", X"04", X"ae", X"28", X"00", X"44",
X"8e", X"29", X"00", X"44", X"14", X"ee", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"2e", X"00", X"09",
X"00", X"00", X"00", X"00", X"ae", X"2a", X"00", X"74",
X"ae", X"2c", X"00", X"94", X"8e", X"2d", X"00", X"94",
X"8e", X"2b", X"00", X"74", X"15", X"6e", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ae", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"06", X"12", X"34", X"24", X"08", X"12", X"34",
X"24", X"0a", X"12", X"34", X"24", X"0c", X"12", X"34",
X"24", X"0e", X"12", X"34", X"a6", X"26", X"00", X"00",
X"86", X"27", X"00", X"00", X"a6", X"28", X"00", X"40",
X"86", X"29", X"00", X"40", X"14", X"ee", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"2e", X"00", X"09",
X"00", X"00", X"00", X"00", X"a6", X"2a", X"00", X"70",
X"a6", X"2c", X"00", X"90", X"86", X"2d", X"00", X"90",
X"86", X"2b", X"00", X"70", X"15", X"6e", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ae", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"06", X"56", X"78", X"24", X"08", X"56", X"78",
X"24", X"0a", X"56", X"78", X"24", X"0c", X"56", X"78",
X"24", X"0e", X"56", X"78", X"a6", X"26", X"00", X"02",
X"86", X"27", X"00", X"02", X"a6", X"28", X"00", X"42",
X"86", X"29", X"00", X"42", X"14", X"ee", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"2e", X"00", X"09",
X"00", X"00", X"00", X"00", X"a6", X"2a", X"00", X"72",
X"a6", X"2c", X"00", X"92", X"86", X"2d", X"00", X"92",
X"86", X"2b", X"00", X"72", X"15", X"6e", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ae", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"24", X"06", X"56", X"78", X"24", X"08", X"56", X"78",
X"24", X"0a", X"56", X"78", X"24", X"0c", X"56", X"78",
X"24", X"0e", X"56", X"78", X"a6", X"26", X"00", X"02",
X"96", X"27", X"00", X"02", X"a6", X"28", X"00", X"42",
X"96", X"29", X"00", X"42", X"14", X"ee", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"2e", X"00", X"09",
X"00", X"00", X"00", X"00", X"a6", X"2a", X"00", X"72",
X"a6", X"2c", X"00", X"92", X"96", X"2d", X"00", X"92",
X"96", X"2b", X"00", X"72", X"15", X"6e", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ae", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"34", X"06", X"cd", X"ef", X"34", X"08", X"cd", X"ef",
X"34", X"0a", X"cd", X"ef", X"34", X"0c", X"cd", X"ef",
X"34", X"0e", X"cd", X"ef", X"a6", X"26", X"00", X"04",
X"96", X"27", X"00", X"04", X"a6", X"28", X"00", X"44",
X"96", X"29", X"00", X"44", X"14", X"ee", X"00", X"0b",
X"00", X"00", X"00", X"00", X"15", X"2e", X"00", X"09",
X"00", X"00", X"00", X"00", X"a6", X"2a", X"00", X"74",
X"a6", X"2c", X"00", X"94", X"96", X"2d", X"00", X"94",
X"96", X"2b", X"00", X"74", X"15", X"6e", X"00", X"03",
X"00", X"00", X"00", X"00", X"11", X"ae", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"03", X"dc", X"f0", X"20", X"17", X"80", X"00", X"07",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c1", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"0b", X"f0", X"07", X"c9",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c5", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"24", X"9c", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"34", X"1c", X"00", X"00",
X"3c", X"02", X"12", X"34", X"34", X"42", X"56", X"78",
X"3c", X"03", X"45", X"67", X"34", X"63", X"89", X"a0",
X"3c", X"04", X"78", X"9a", X"34", X"84", X"bc", X"de",
X"3c", X"05", X"8a", X"bc", X"34", X"a5", X"de", X"f0",
X"24", X"0a", X"00", X"0d", X"24", X"0b", X"00", X"11",
X"00", X"02", X"a9", X"c0", X"3c", X"13", X"1a", X"2b",
X"36", X"73", X"3c", X"00", X"02", X"b3", X"98", X"22",
X"12", X"60", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"00", X"04", X"ad", X"c0",
X"3c", X"13", X"6f", X"00", X"02", X"b3", X"98", X"22",
X"12", X"60", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"01", X"42", X"a8", X"04",
X"3c", X"13", X"8a", X"cf", X"02", X"b3", X"98", X"22",
X"12", X"60", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"01", X"64", X"a8", X"04",
X"3c", X"13", X"79", X"bc", X"02", X"b3", X"98", X"22",
X"12", X"60", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"00", X"05", X"a9", X"c2",
X"3c", X"13", X"01", X"15", X"36", X"73", X"79", X"bd",
X"02", X"b3", X"98", X"22", X"12", X"60", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"04", X"ab", X"42", X"3c", X"13", X"00", X"03",
X"36", X"73", X"c4", X"d5", X"02", X"b3", X"98", X"22",
X"12", X"60", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"01", X"45", X"a8", X"06",
X"3c", X"13", X"00", X"04", X"36", X"73", X"55", X"e6",
X"02", X"b3", X"98", X"22", X"12", X"60", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"01", X"64", X"a8", X"06", X"24", X"13", X"3c", X"4d",
X"02", X"b3", X"98", X"22", X"12", X"60", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"00", X"05", X"a9", X"c3", X"3c", X"13", X"ff", X"15",
X"36", X"73", X"79", X"bd", X"02", X"b3", X"98", X"22",
X"12", X"60", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"00", X"05", X"ae", X"03",
X"24", X"13", X"ff", X"8a", X"02", X"b3", X"98", X"22",
X"12", X"60", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"01", X"45", X"a8", X"07",
X"3c", X"13", X"ff", X"fc", X"36", X"73", X"55", X"e6",
X"02", X"b3", X"98", X"22", X"12", X"60", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"01", X"64", X"a8", X"07", X"24", X"13", X"3c", X"4d",
X"02", X"b3", X"98", X"22", X"12", X"60", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"03", X"dc", X"f0", X"20", X"17", X"80", X"00", X"07",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c1", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"0b", X"f0", X"08", X"33",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c5", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"24", X"f9", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"34", X"1c", X"00", X"00",
X"3c", X"02", X"12", X"34", X"34", X"42", X"56", X"78",
X"3c", X"03", X"45", X"67", X"34", X"63", X"89", X"a0",
X"3c", X"04", X"78", X"9a", X"34", X"84", X"bc", X"de",
X"3c", X"05", X"8a", X"bc", X"34", X"a5", X"de", X"f0",
X"00", X"00", X"00", X"4c", X"00", X"00", X"00", X"00",
X"03", X"dc", X"f0", X"20", X"17", X"80", X"00", X"07",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c1", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"0b", X"f0", X"08", X"4f",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"c5", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"17", X"c0", X"00", X"09",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"cc", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"24", X"09", X"80", X"18",
X"ad", X"3e", X"00", X"00", X"0b", X"f0", X"08", X"57",
X"00", X"00", X"00", X"00", X"3c", X"04", X"bf", X"c0",
X"24", X"84", X"22", X"db", X"0f", X"f0", X"08", X"a1",
X"00", X"00", X"00", X"00", X"0b", X"f0", X"08", X"55",
X"00", X"00", X"00", X"00", X"48", X"c2", X"00", X"00",
X"48", X"c3", X"08", X"00", X"48", X"c4", X"10", X"00",
X"48", X"c5", X"18", X"00", X"48", X"82", X"00", X"00",
X"48", X"83", X"08", X"01", X"48", X"84", X"10", X"02",
X"48", X"85", X"18", X"03", X"48", X"46", X"00", X"00",
X"3c", X"07", X"12", X"34", X"34", X"e7", X"56", X"78",
X"00", X"c7", X"38", X"22", X"10", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"48", X"46", X"08", X"00", X"3c", X"07", X"45", X"67",
X"34", X"e7", X"89", X"a0", X"00", X"c7", X"38", X"22",
X"10", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"48", X"46", X"10", X"00",
X"3c", X"07", X"78", X"9a", X"34", X"e7", X"bc", X"de",
X"00", X"c7", X"38", X"22", X"10", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"48", X"46", X"18", X"00", X"3c", X"07", X"8a", X"bc",
X"34", X"e7", X"de", X"f0", X"00", X"c7", X"38", X"22",
X"10", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"48", X"06", X"00", X"00",
X"3c", X"07", X"12", X"34", X"34", X"e7", X"56", X"78",
X"00", X"c7", X"38", X"22", X"10", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"48", X"06", X"08", X"01", X"3c", X"07", X"25", X"67",
X"34", X"e7", X"89", X"a0", X"00", X"c7", X"38", X"22",
X"10", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"48", X"06", X"10", X"02",
X"3c", X"07", X"58", X"9a", X"34", X"e7", X"bc", X"de",
X"00", X"c7", X"38", X"22", X"10", X"e0", X"00", X"02",
X"00", X"00", X"00", X"00", X"23", X"9c", X"00", X"01",
X"48", X"06", X"18", X"03", X"3c", X"07", X"6a", X"bc",
X"34", X"e7", X"de", X"f0", X"00", X"c7", X"38", X"22",
X"10", X"e0", X"00", X"02", X"00", X"00", X"00", X"00",
X"23", X"9c", X"00", X"01", X"03", X"e0", X"00", X"08",
X"00", X"00", X"00", X"00", X"24", X"05", X"80", X"00",
X"80", X"82", X"00", X"00", X"10", X"40", X"00", X"04",
X"20", X"84", X"00", X"01", X"a0", X"a2", X"00", X"00",
X"10", X"00", X"ff", X"fb", X"00", X"00", X"00", X"00",
X"03", X"e0", X"00", X"08", X"00", X"00", X"00", X"00",
X"49", X"4f", X"4e", X"20", X"4d", X"49", X"50", X"53",
X"20", X"6f", X"70", X"63", X"6f", X"64", X"65", X"20",
X"74", X"65", X"73", X"74", X"65", X"72", X"0a", X"0a",
X"00", X"4f", X"4b", X"0a", X"00", X"45", X"52", X"52",
X"4f", X"52", X"0a", X"00", X"0a", X"54", X"65", X"73",
X"74", X"20", X"50", X"41", X"53", X"53", X"45", X"44",
X"0a", X"0a", X"00", X"0a", X"54", X"65", X"73", X"74",
X"20", X"46", X"41", X"49", X"4c", X"45", X"44", X"0a",
X"0a", X"00", X"45", X"6e", X"74", X"65", X"72", X"69",
X"6e", X"67", X"20", X"75", X"73", X"65", X"72", X"20",
X"6d", X"6f", X"64", X"65", X"2e", X"2e", X"2e", X"2e",
X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"20",
X"00", X"44", X"61", X"74", X"61", X"20", X"43", X"61",
X"63", X"68", X"65", X"20", X"62", X"61", X"73", X"69",
X"63", X"20", X"74", X"65", X"73", X"74", X"2e", X"2e",
X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"20", X"00",
X"43", X"6f", X"64", X"65", X"20", X"43", X"61", X"63",
X"68", X"65", X"20", X"62", X"61", X"73", X"69", X"63",
X"20", X"74", X"65", X"73", X"74", X"2e", X"2e", X"2e",
X"2e", X"2e", X"2e", X"2e", X"2e", X"20", X"00", X"44",
X"45", X"42", X"55", X"47", X"20", X"72", X"65", X"67",
X"69", X"73", X"74", X"65", X"72", X"73", X"20", X"28",
X"54", X"42", X"20", X"6f", X"6e", X"6c", X"79", X"29",
X"2e", X"2e", X"2e", X"2e", X"20", X"00", X"41", X"63",
X"63", X"65", X"73", X"73", X"20", X"74", X"6f", X"20",
X"47", X"50", X"49", X"4f", X"20", X"72", X"65", X"67",
X"69", X"73", X"74", X"65", X"72", X"73", X"2e", X"2e",
X"2e", X"2e", X"2e", X"20", X"00", X"4c", X"6f", X"61",
X"64", X"20", X"69", X"6e", X"74", X"65", X"72", X"6c",
X"6f", X"63", X"6b", X"73", X"2e", X"2e", X"2e", X"2e",
X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e",
X"2e", X"2e", X"20", X"00", X"41", X"64", X"64", X"2a",
X"2f", X"53", X"75", X"62", X"2a", X"2e", X"2e", X"2e",
X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e",
X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e",
X"2e", X"20", X"00", X"53", X"6c", X"74", X"2a", X"20",
X"6f", X"70", X"63", X"6f", X"64", X"65", X"73", X"2e",
X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e",
X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e",
X"20", X"00", X"42", X"72", X"61", X"6e", X"63", X"68",
X"20", X"6f", X"70", X"63", X"6f", X"64", X"65", X"73",
X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e",
X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"20",
X"00", X"4a", X"75", X"6d", X"70", X"20", X"6f", X"70",
X"63", X"6f", X"64", X"65", X"73", X"2e", X"2e", X"2e",
X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e",
X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"20", X"00",
X"4c", X"6f", X"67", X"69", X"63", X"20", X"6f", X"70",
X"63", X"6f", X"64", X"65", X"73", X"2e", X"2e", X"2e",
X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e",
X"2e", X"2e", X"2e", X"2e", X"2e", X"20", X"00", X"4d",
X"75", X"6c", X"2a", X"2f", X"44", X"69", X"76", X"2a",
X"20", X"6f", X"70", X"63", X"6f", X"64", X"65", X"73",
X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e",
X"2e", X"2e", X"2e", X"2e", X"20", X"00", X"4d", X"61",
X"64", X"64", X"2a", X"2f", X"4d", X"73", X"75", X"62",
X"2a", X"20", X"6f", X"70", X"63", X"6f", X"64", X"65",
X"73", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e",
X"2e", X"2e", X"2e", X"20", X"00", X"4c", X"6f", X"61",
X"64", X"2f", X"53", X"74", X"6f", X"72", X"65", X"20",
X"6f", X"70", X"63", X"6f", X"64", X"65", X"73", X"2e",
X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e",
X"2e", X"2e", X"20", X"00", X"53", X"68", X"69", X"66",
X"74", X"20", X"6f", X"70", X"63", X"6f", X"64", X"65",
X"73", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e",
X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e",
X"2e", X"20", X"00", X"42", X"72", X"65", X"61", X"6b",
X"2f", X"53", X"79", X"73", X"63", X"61", X"6c", X"6c",
X"20", X"6f", X"70", X"63", X"6f", X"64", X"65", X"73",
X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e",
X"20", X"00", X"48", X"57", X"20", X"69", X"6e", X"74",
X"65", X"72", X"72", X"75", X"70", X"74", X"73", X"20",
X"28", X"54", X"42", X"20", X"6f", X"6e", X"6c", X"79",
X"29", X"2e", X"2e", X"2e", X"2e", X"2e", X"2e", X"20",
X"00", X"43", X"4f", X"50", X"32", X"20", X"69", X"6e",
X"74", X"65", X"72", X"66", X"61", X"63", X"65", X"20",
X"28", X"54", X"42", X"20", X"6f", X"6e", X"6c", X"79",
X"29", X"2e", X"2e", X"2e", X"2e", X"2e", X"20", X"00",
X"3c", X"1b", X"a0", X"00", X"27", X"7b", X"00", X"3c",
X"af", X"7d", X"ff", X"f0", X"af", X"7f", X"ff", X"ec",
X"af", X"68", X"ff", X"e8", X"af", X"69", X"ff", X"e4",
X"af", X"6a", X"ff", X"e0", X"03", X"60", X"e8", X"21",
X"40", X"08", X"70", X"00", X"8d", X"1a", X"00", X"00",
X"40", X"1b", X"68", X"00", X"07", X"70", X"00", X"2d",
X"00", X"00", X"00", X"00", X"00", X"1a", X"4e", X"82",
X"39", X"28", X"00", X"1f", X"11", X"00", X"00", X"1f",
X"39", X"28", X"00", X"1c", X"11", X"00", X"00", X"13",
X"00", X"00", X"00", X"00", X"3c", X"08", X"20", X"01",
X"ad", X"1a", X"04", X"00", X"8f", X"aa", X"ff", X"e0",
X"8f", X"a9", X"ff", X"e4", X"8f", X"a8", X"ff", X"e8",
X"8f", X"bf", X"ff", X"ec", X"8f", X"bd", X"ff", X"f0",
X"40", X"1b", X"70", X"00", X"40", X"1a", X"68", X"00",
X"00", X"1a", X"d7", X"c2", X"33", X"5a", X"00", X"01",
X"17", X"40", X"00", X"03", X"23", X"7b", X"00", X"04",
X"03", X"60", X"00", X"08", X"00", X"00", X"00", X"00",
X"23", X"7b", X"00", X"04", X"03", X"60", X"00", X"08",
X"42", X"00", X"00", X"10", X"33", X"5b", X"00", X"3f",
X"3b", X"68", X"00", X"20", X"11", X"00", X"00", X"14",
X"3b", X"68", X"00", X"21", X"11", X"00", X"00", X"1c",
X"00", X"00", X"00", X"00", X"3c", X"08", X"20", X"01",
X"ad", X"1a", X"04", X"00", X"0b", X"f0", X"09", X"5b",
X"00", X"00", X"00", X"00", X"33", X"5b", X"00", X"3f",
X"3b", X"68", X"00", X"00", X"11", X"00", X"00", X"1e",
X"3b", X"68", X"00", X"04", X"11", X"00", X"00", X"29",
X"00", X"00", X"00", X"00", X"3c", X"08", X"20", X"01",
X"ad", X"1a", X"04", X"00", X"0b", X"f0", X"09", X"5b",
X"00", X"00", X"00", X"00", X"8d", X"1a", X"00", X"04",
X"03", X"e0", X"00", X"08", X"00", X"00", X"00", X"00",
X"0f", X"f0", X"0a", X"05", X"3c", X"0a", X"80", X"00",
X"00", X"00", X"40", X"21", X"03", X"6a", X"48", X"24",
X"15", X"20", X"00", X"03", X"00", X"0a", X"50", X"42",
X"15", X"40", X"ff", X"fc", X"25", X"08", X"00", X"01",
X"0b", X"f0", X"09", X"bb", X"01", X"00", X"d8", X"21",
X"0f", X"f0", X"0a", X"05", X"3c", X"0a", X"80", X"00",
X"00", X"00", X"40", X"21", X"03", X"6a", X"48", X"24",
X"11", X"20", X"00", X"03", X"00", X"0a", X"50", X"42",
X"15", X"40", X"ff", X"fc", X"25", X"08", X"00", X"01",
X"0b", X"f0", X"09", X"bb", X"01", X"00", X"d8", X"21",
X"0f", X"f0", X"0a", X"05", X"00", X"00", X"00", X"00",
X"00", X"1a", X"41", X"82", X"31", X"08", X"00", X"1f",
X"00", X"1a", X"4a", X"c2", X"31", X"29", X"00", X"1f",
X"01", X"09", X"50", X"21", X"00", X"0a", X"50", X"23",
X"25", X"4a", X"00", X"1f", X"01", X"5b", X"d8", X"04",
X"01", X"5b", X"d8", X"06", X"0b", X"f0", X"09", X"bb",
X"01", X"1b", X"d8", X"06", X"0f", X"f0", X"0a", X"05",
X"00", X"00", X"00", X"00", X"00", X"1a", X"41", X"82",
X"31", X"08", X"00", X"1f", X"00", X"1a", X"4a", X"c2",
X"31", X"29", X"00", X"1f", X"01", X"28", X"48", X"23",
X"00", X"09", X"58", X"23", X"25", X"6b", X"00", X"1f",
X"01", X"1b", X"48", X"04", X"3c", X"0a", X"ff", X"ff",
X"35", X"4a", X"ff", X"ff", X"01", X"6a", X"50", X"04",
X"01", X"6a", X"50", X"06", X"01", X"0a", X"50", X"04",
X"01", X"2a", X"48", X"24", X"01", X"40", X"50", X"27",
X"0f", X"f0", X"0a", X"05", X"00", X"1a", X"d1", X"40",
X"00", X"1a", X"d1", X"42", X"03", X"6a", X"d8", X"24",
X"03", X"69", X"d8", X"25", X"0b", X"f0", X"09", X"bb",
X"00", X"00", X"00", X"00", X"00", X"1a", X"4c", X"02",
X"31", X"29", X"00", X"1f", X"3c", X"08", X"bf", X"c0",
X"25", X"08", X"27", X"14", X"00", X"09", X"48", X"c0",
X"01", X"09", X"40", X"20", X"01", X"00", X"00", X"08",
X"00", X"00", X"00", X"00", X"0b", X"f0", X"09", X"5b",
X"00", X"00", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"60", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"61", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"62", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"63", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"64", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"65", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"66", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"67", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"af", X"bb", X"ff", X"e8", X"0b", X"f0", X"09", X"c3",
X"af", X"bb", X"ff", X"e4", X"0b", X"f0", X"09", X"c3",
X"af", X"bb", X"ff", X"e0", X"0b", X"f0", X"09", X"c3",
X"37", X"6b", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"6c", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"6d", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"6e", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"6f", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"70", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"71", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"72", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"73", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"74", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"75", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"76", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"77", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"78", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"79", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"7a", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"7b", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"37", X"7c", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"af", X"bb", X"ff", X"ec", X"0b", X"f0", X"09", X"c3",
X"37", X"7e", X"00", X"00", X"0b", X"f0", X"09", X"c3",
X"af", X"bb", X"ff", X"f0", X"af", X"bf", X"00", X"00",
X"00", X"1a", X"dd", X"42", X"33", X"7b", X"00", X"1f",
X"3c", X"08", X"bf", X"c0", X"25", X"08", X"28", X"44",
X"00", X"1b", X"d8", X"c0", X"01", X"1b", X"40", X"20",
X"01", X"00", X"f8", X"09", X"00", X"00", X"00", X"00",
X"8f", X"bf", X"00", X"00", X"03", X"e0", X"00", X"08",
X"00", X"00", X"00", X"00", X"03", X"e0", X"00", X"08",
X"34", X"1b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"34", X"3b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"34", X"5b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"34", X"7b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"34", X"9b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"34", X"bb", X"00", X"00", X"03", X"e0", X"00", X"08",
X"34", X"db", X"00", X"00", X"03", X"e0", X"00", X"08",
X"34", X"fb", X"00", X"00", X"03", X"e0", X"00", X"08",
X"8f", X"bb", X"ff", X"e8", X"03", X"e0", X"00", X"08",
X"8f", X"bb", X"ff", X"e4", X"03", X"e0", X"00", X"08",
X"8f", X"bb", X"ff", X"e0", X"03", X"e0", X"00", X"08",
X"35", X"7b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"35", X"9b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"35", X"bb", X"00", X"00", X"03", X"e0", X"00", X"08",
X"35", X"db", X"00", X"00", X"03", X"e0", X"00", X"08",
X"35", X"fb", X"00", X"00", X"03", X"e0", X"00", X"08",
X"36", X"1b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"36", X"3b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"36", X"5b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"36", X"7b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"36", X"9b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"36", X"bb", X"00", X"00", X"03", X"e0", X"00", X"08",
X"36", X"db", X"00", X"00", X"03", X"e0", X"00", X"08",
X"36", X"fb", X"00", X"00", X"03", X"e0", X"00", X"08",
X"37", X"1b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"37", X"3b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"37", X"5b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"37", X"7b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"37", X"9a", X"00", X"00", X"03", X"e0", X"00", X"08",
X"8f", X"bb", X"ff", X"f0", X"03", X"e0", X"00", X"08",
X"37", X"db", X"00", X"00", X"03", X"e0", X"00", X"08",
X"8f", X"bb", X"ff", X"ec" );
constant INIT_DATA : t_obj_code(0 to 0) := (others => X"00");
end package OBJ_CODE_PKG;
| lgpl-3.0 | 1fc90cdc8f9ccbef459b111a553871de | 0.412527 | 1.735776 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/configuration/select_vmm.vhd | 1 | 4,640 | ----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity select_vmm is
Port (
clk_in : in std_logic;
vmm_id : in std_logic_vector(15 downto 0);
conf_di : in std_logic;
conf_di_vec : out std_logic_vector(8 downto 1);
conf_do : out std_logic;
conf_do_vec : in std_logic_vector(8 downto 1);
cktk_out : in std_logic;
cktk_out_vec : out std_logic_vector(8 downto 1);
conf_wen : in std_logic;
conf_wen_vec : out std_logic_vector(8 downto 1);
conf_ena : in std_logic;
conf_ena_vec : out std_logic_vector(8 downto 1)
);
end select_vmm;
architecture Behavioral of select_vmm is
begin
fill_fifo : process(clk_in, vmm_id)
begin
if rising_edge(clk_in) then
if vmm_id = x"0001" then
conf_wen_vec(1) <= conf_wen;
cktk_out_vec(1) <= cktk_out;
conf_ena_vec(1) <= conf_ena;
conf_do <= conf_do_vec(1);
conf_di_vec(1) <= conf_di;
elsif vmm_id = x"0002" then
conf_wen_vec(2) <= conf_wen;
cktk_out_vec(2) <= cktk_out;
conf_ena_vec(2) <= conf_ena;
conf_do <= conf_do_vec(2);
conf_di_vec(2) <= conf_di;
elsif vmm_id = x"0003" then
conf_wen_vec(3) <= conf_wen;
cktk_out_vec(3) <= cktk_out;
conf_ena_vec(3) <= conf_ena;
conf_do <= conf_do_vec(3);
conf_di_vec(3) <= conf_di;
elsif vmm_id = x"0004" then
conf_wen_vec(4) <= conf_wen;
cktk_out_vec(4) <= cktk_out;
conf_ena_vec(4) <= conf_ena;
conf_do <= conf_do_vec(4);
conf_di_vec(4) <= conf_di;
elsif vmm_id = x"0005" then
conf_wen_vec(5) <= conf_wen;
cktk_out_vec(5) <= cktk_out;
conf_ena_vec(5) <= conf_ena;
conf_do <= conf_do_vec(5);
conf_di_vec(5) <= conf_di;
elsif vmm_id = x"0006" then
conf_wen_vec(6) <= conf_wen;
cktk_out_vec(6) <= cktk_out;
conf_ena_vec(6) <= conf_ena;
conf_do <= conf_do_vec(6);
conf_di_vec(6) <= conf_di;
elsif vmm_id = x"0007" then
conf_wen_vec(7) <= conf_wen;
cktk_out_vec(7) <= cktk_out;
conf_ena_vec(7) <= conf_ena;
conf_do <= conf_do_vec(7);
conf_di_vec(7) <= conf_di;
elsif vmm_id = x"0008" then
conf_wen_vec(8) <= conf_wen;
cktk_out_vec(8) <= cktk_out;
conf_ena_vec(8) <= conf_ena;
conf_do <= conf_do_vec(8);
conf_di_vec(8) <= conf_di;
else
conf_wen_vec <= (others => '0');
cktk_out_vec <= (others => '0');
conf_ena_vec <= (others => '0');
conf_di_vec <= (others => '0');
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | e82ec2b74aaa9f6a64b0fc59c3b264fd | 0.410129 | 3.822076 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/arp_REQ.vhd | 2 | 12,101 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_REQ - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle requests for ARP resolution
-- responds from single entry cache or searches external arp store, or asks to send a request
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created from arp.vhd 0.2
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
entity arp_req is
generic (
no_default_gateway : boolean := true; -- set to false if communicating with devices accessed
-- through a "default gateway or router"
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5 -- # wrong nwk pkts received before set error
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type; -- request for a translation from IP to MAC
arp_req_rslt : out arp_req_rslt_type; -- the result
-- external arp store signals
arp_store_req : out arp_store_rdrequest_t; -- requesting a lookup or store
arp_store_result : in arp_store_result_t; -- the result
-- network request signals
arp_nwk_req : out arp_nwk_request_t; -- requesting resolution via the network
arp_nwk_result : in arp_nwk_result_t; -- the result
-- system signals
clear_cache : in std_logic; -- clear the internal cache
nwk_gateway : in std_logic_vector(31 downto 0); -- IP address of default gateway
nwk_mask : in std_logic_vector(31 downto 0); -- Net mask
clk : in std_logic;
reset : in std_logic
);
end arp_req;
architecture Behavioral of arp_req is
type req_state_t is (IDLE, LOOKUP, WAIT_REPLY, PAUSE1, PAUSE2, PAUSE3);
type set_cntr_t is (HOLD, CLR, INCR);
type set_clr_type is (SET, CLR, HOLD);
-- state variables
signal req_state : req_state_t;
signal req_ip_addr : std_logic_vector (31 downto 0); -- IP address to lookup
signal arp_entry_cache : arp_entry_t; -- single entry cache for fast response
signal cache_valid : std_logic; -- single entry cache is valid
signal nwk_rx_cntr : unsigned(7 downto 0); -- counts nwk rx pkts that dont satisfy
signal freq_scaler : unsigned (31 downto 0); -- scales data_in_clk downto 1Hz
signal timer : unsigned (7 downto 0); -- counts seconds timeout
signal timeout_reg : std_logic;
-- busses
signal next_req_state : req_state_t;
signal arp_entry_val : arp_entry_t;
-- requester control signals
signal set_req_state : std_logic;
signal set_req_ip : std_logic;
signal store_arp_cache : std_logic;
signal set_nwk_rx_cntr : set_cntr_t;
signal set_timer : set_cntr_t; -- timer reset, count, hold control
signal timer_enable : std_logic; -- enable the timer counting
signal set_timeout : set_clr_type; -- control the timeout register
signal clear_cache_valid : std_logic;
signal l_arp_req_req_ip : std_logic_vector(31 downto 0); -- local network IP address for resolution
begin
default_GW: if (not no_default_gateway) generate
default_gw_comb_p: process (arp_req_req.ip, nwk_gateway, nwk_mask) is
begin -- process default_gw_comb_p
-- translate IP addresses to local IP address if necessary
if ((nwk_mask and arp_req_req.ip) = (nwk_mask and nwk_gateway)) then
-- on local network
l_arp_req_req_ip <= arp_req_req.ip;
else
-- on remote network
l_arp_req_req_ip <= nwk_gateway;
end if;
end process default_gw_comb_p;
end generate default_GW;
no_default_GW: if (no_default_gateway) generate
no_default_gw_comb_p: process (arp_req_req.ip) is
begin -- process no_default_gw_comb_p
l_arp_req_req_ip <= arp_req_req.ip;
end process no_default_gw_comb_p;
end generate no_default_GW;
req_combinatorial : process (
arp_entry_cache.ip, arp_entry_cache.mac, arp_nwk_result.entry, arp_nwk_result.entry.ip,
arp_nwk_result.entry.mac, arp_nwk_result.status, arp_req_req.lookup_req,
arp_store_result.entry, arp_store_result.entry.mac, arp_store_result.status, cache_valid,
clear_cache, freq_scaler, l_arp_req_req_ip, nwk_rx_cntr, req_ip_addr, req_state,
timeout_reg, timer)
begin
-- set output followers
arp_req_rslt.got_mac <= '0'; -- set initial value of request result outputs
arp_req_rslt.got_err <= '0';
arp_req_rslt.mac <= (others => '0');
arp_store_req.req <= '0';
arp_store_req.ip <= (others => '0');
arp_nwk_req.req <= '0';
arp_nwk_req.ip <= (others => '0');
-- zero time response to lookup request if already in cache
if arp_req_req.lookup_req = '1' and l_arp_req_req_ip = arp_entry_cache.ip and cache_valid = '1' then
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_entry_cache.mac;
elsif arp_req_req.lookup_req = '1' then
-- hold off got_mac while req is there as arp_entry will not be correct yet
arp_req_rslt.got_mac <= '0';
arp_req_rslt.mac <= arp_entry_cache.mac;
else
arp_req_rslt.got_mac <= cache_valid;
arp_req_rslt.mac <= arp_entry_cache.mac;
end if;
if arp_req_req.lookup_req = '1' then
-- ensure any existing error report is killed at the start of a request
arp_req_rslt.got_err <= '0';
else
arp_req_rslt.got_err <= timeout_reg;
end if;
-- set signal defaults
next_req_state <= IDLE;
set_req_state <= '0';
set_req_ip <= '0';
store_arp_cache <= '0';
arp_entry_val.ip <= (others => '0');
arp_entry_val.mac <= (others => '0');
set_nwk_rx_cntr <= HOLD;
set_timer <= INCR; -- default is timer running, unless we hold or reset it
set_timeout <= HOLD;
timer_enable <= '0';
clear_cache_valid <= clear_cache;
-- combinatorial logic
if freq_scaler = x"00000000" then
timer_enable <= '1';
end if;
-- REQ FSM
case req_state is
when IDLE =>
set_timer <= CLR;
if arp_req_req.lookup_req = '1' then
-- check if we already have the info in cache
if l_arp_req_req_ip = arp_entry_cache.ip and cache_valid = '1' then
-- already have this IP - feed output back
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_entry_cache.mac;
else
clear_cache_valid <= '1'; -- remove cache entry
set_timeout <= CLR;
next_req_state <= LOOKUP;
set_req_state <= '1';
set_req_ip <= '1';
end if;
end if;
when LOOKUP =>
-- put request on the store
arp_store_req.ip <= req_ip_addr;
arp_store_req.req <= '1';
case arp_store_result.status is
when FOUND =>
-- update the cache
arp_entry_val <= arp_store_result.entry;
store_arp_cache <= '1';
-- and feed output back
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_store_result.entry.mac;
next_req_state <= IDLE;
set_req_state <= '1';
when NOT_FOUND =>
-- need to request from the network
set_timer <= CLR;
set_nwk_rx_cntr <= CLR;
arp_nwk_req.req <= '1';
arp_nwk_req.ip <= req_ip_addr;
next_req_state <= WAIT_REPLY;
set_req_state <= '1';
when others =>
-- just keep waiting - no timeout (assumes lookup with either succeed or fail)
end case;
when WAIT_REPLY =>
case arp_nwk_result.status is
when RECEIVED =>
if arp_nwk_result.entry.ip = req_ip_addr then
-- store into cache
arp_entry_val <= arp_nwk_result.entry;
store_arp_cache <= '1';
-- and feed output back
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_nwk_result.entry.mac;
next_req_state <= IDLE;
set_req_state <= '1';
else
if nwk_rx_cntr > ARP_MAX_PKT_TMO then
set_timeout <= SET;
next_req_state <= IDLE;
set_req_state <= '1';
else
set_nwk_rx_cntr <= INCR;
end if;
end if;
when error =>
set_timeout <= SET;
when others =>
if timer >= ARP_TIMEOUT then
set_timeout <= SET;
next_req_state <= PAUSE1;
set_req_state <= '1';
end if;
end case;
when PAUSE1 =>
next_req_state <= PAUSE2;
set_req_state <= '1';
when PAUSE2 =>
next_req_state <= PAUSE3;
set_req_state <= '1';
when PAUSE3 =>
next_req_state <= IDLE;
set_req_state <= '1';
end case;
end process;
req_sequential : process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
req_state <= IDLE;
req_ip_addr <= (others => '0');
arp_entry_cache.ip <= (others => '0');
arp_entry_cache.mac <= (others => '0');
cache_valid <= '0';
nwk_rx_cntr <= (others => '0');
freq_scaler <= to_unsigned(CLOCK_FREQ, 32);
timer <= (others => '0');
timeout_reg <= '0';
else
-- Next req_state processing
if set_req_state = '1' then
req_state <= next_req_state;
else
req_state <= req_state;
end if;
-- Latch the requested IP address
if set_req_ip = '1' then
req_ip_addr <= l_arp_req_req_ip;
else
req_ip_addr <= req_ip_addr;
end if;
-- network received counter
case set_nwk_rx_cntr is
when CLR => nwk_rx_cntr <= (others => '0');
when INCR => nwk_rx_cntr <= nwk_rx_cntr + 1;
when HOLD => nwk_rx_cntr <= nwk_rx_cntr;
end case;
-- set the arp_entry_cache
if clear_cache_valid = '1' then
arp_entry_cache <= arp_entry_cache;
cache_valid <= '0';
elsif store_arp_cache = '1' then
arp_entry_cache <= arp_entry_val;
cache_valid <= '1';
else
arp_entry_cache <= arp_entry_cache;
cache_valid <= cache_valid;
end if;
-- freq scaling and 1-sec timer
if freq_scaler = x"00000000" then
freq_scaler <= to_unsigned(CLOCK_FREQ, 32);
else
freq_scaler <= freq_scaler - 1;
end if;
-- timer processing
case set_timer is
when CLR =>
timer <= x"00";
when INCR =>
if timer_enable = '1' then
timer <= timer + 1;
else
timer <= timer;
end if;
when HOLD =>
timer <= timer;
end case;
-- timeout latching
case set_timeout is
when CLR => timeout_reg <= '0';
when SET => timeout_reg <= '1';
when HOLD => timeout_reg <= timeout_reg;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | c44c7d34c94ef1850a264b48e8e30330 | 0.526072 | 3.688205 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Multirate/decimator.vhd | 1 | 3,709 | --------------------------------------------------------------------------------------------------
-- Decimator
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package decimator_pkg is
component decimator is
generic( h : coefficient_array);
port( clk_high : in std_logic;
clk_low : in std_logic;
rst : in std_logic;
sig_high : in sig;
sig_low : out sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
use work.demuxer_pkg.all;
use work.multichannel_fir_filter_pkg.all;
entity decimator is
generic( h : coefficient_array);
port( clk_high : in std_logic;
clk_low : in std_logic;
rst : in std_logic;
sig_high : in sig;
sig_low : out sig);
end decimator;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of decimator is
constant H0 : coefficient_array(1 to (h'length+1)/2)
:= slice_coefficient_array(h, 2, 1, 0);
constant H1 : coefficient_array(1 to (h'length+1)/2)
:= slice_coefficient_array(h, 2, 2, 0);
signal sig1 : sig := (others => '0');
signal sig2 : sig := (others => '0');
signal filtered1 : fir_sig := (others => '0');
signal filtered2 : fir_sig := (others => '0');
signal sum : fir_sig := (others => '0');
begin
--Demux the signal
--NOTE: If this design were to ever support decimation factor > 2, the demux would need to send
--out the signal to the parallel lines in descending order.
demux_sig : demuxer
generic map(INIT_SEL => b"01")--start demux on the lowest channel, demux should rotate right
port map( clk => clk_low,
clk_2x => clk_high,
rst => rst,
sigs => std_logic_vector(sig_high),
sig(sig1) => sig1,
sig(sig2) => sig2);
--Low pass the demuxed signals using the multichannel approach
anti_alias : multichannel_fir_filter
generic map(h0 => H0,
h1 => H1,
INIT_SEL => b"10")
port map( clk => clk_low,
clk_2x => clk_high,
rst => rst,
x1 => sig1,
x2 => sig2,
y1 => filtered1,
y2 => filtered2);
--Sum the 2 filtered signals together
update_sum : process(clk_low)
begin
if(rising_edge(clk_low)) then
if(rst = '1') then
sum <= (others => '0');
else
sum <= filtered1 + filtered2;
end if;
end if;
end process;
sig_low <= sum(30 downto 15);
end behave;
| mit | a61e800b9257caf6c63d9a8bdf04b76e | 0.398221 | 4.613184 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN4_ALIGN_BLOCK.vhd | 1 | 5,626 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4_ALIGN_BLOCK
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
use work.centralRouter_package.all;
--! continuously aligns 4bit bit-stream to two commas
entity EPROC_IN4_ALIGN_BLOCK is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
bytes : in word10b_2array_type; -- 8b10b encoded
bytes_rdy : in std_logic;
------------
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
------------
busyOut : out std_logic
);
end EPROC_IN4_ALIGN_BLOCK;
architecture Behavioral of EPROC_IN4_ALIGN_BLOCK is
signal bytes_r : word10b_2array_type := ((others=>'0'),(others=>'0'));
signal byte1_in_rdy,byte0_in_rdy,send_state : std_logic := '0';
signal byte1_out_rdy_s,byte0_out_rdy_s : std_logic;
signal byte_in,byte_1,dataOUT_s : std_logic_vector(9 downto 0) := (others => '0');
signal byte1_out_rdy,byte0_out_rdy,byte_in_rdy,byte_1_rdy,dataOUTrdy_s, bytes_rdy_r : std_logic := '0';
signal byte_count : std_logic_vector(0 downto 0) := "0";
begin
process(bitCLK)
begin
if rising_edge(bitCLK) then
if bytes_rdy = '1' then
byte_1 <= bytes(1);
byte_1_rdy <= '1';
else
byte_1_rdy <= '0';
end if;
end if;
end process;
--
process(bitCLK)
begin
if rising_edge(bitCLK) then
if bytes_rdy = '1' then
byte_in <= bytes(0);
byte_in_rdy <= '1';
elsif byte_1_rdy = '1' then
byte_in <= byte_1;
byte_in_rdy <= '1';
else
byte_in_rdy <= '0';
end if;
end if;
end process;
--
process(bitCLK)
begin
if rising_edge(bitCLK) then
byte0_in_rdy <= bytes_rdy;
byte1_in_rdy <= byte0_in_rdy;
byte0_out_rdy <= byte0_in_rdy;
byte1_out_rdy <= byte1_in_rdy;
end if;
end process;
--
rdy_pipe0: entity work.pulse_pdxx_pwxx generic map(pd=>1,pw=>1) port map(bitCLKx4,byte0_out_rdy,byte0_out_rdy_s);
rdy_pipe1: entity work.pulse_pdxx_pwxx generic map(pd=>1,pw=>1) port map(bitCLKx4,byte1_out_rdy,byte1_out_rdy_s);
--
---------------------------------------------------------------------------------------------
---- clock1
---- input register
---------------------------------------------------------------------------------------------
--process(bitCLKx2, rst)
--begin
-- if rst = '1' then
-- bytes_rdy_r <= '0';
-- elsif rising_edge(bitCLKx2) then
-- if bytes_rdy = '1' then
-- bytes_rdy_r <= not bytes_rdy_r;
-- else
-- bytes_rdy_r <= '0';
-- end if;
-- end if;
--end process;
----
--input_latch: process(bitCLKx2)
--begin
-- if rising_edge(bitCLKx2) then
-- if bytes_rdy = '1' then
-- bytes_r <= bytes;
-- end if;
-- end if;
--end process;
----
----
--process(bitCLKx2, rst)
--begin
-- if rst = '1' then
-- send_state <= '0';
-- elsif rising_edge(bitCLKx2) then
-- if bytes_rdy = '1' then
-- send_state <= '1';
-- else
-- if byte_count = "1" then
-- send_state <= '0';
-- end if;
-- end if;
-- end if;
--end process;
----
--process(bitCLKx2)
--begin
-- if rising_edge(bitCLKx2) then
-- if send_state = '1' then
-- byte_count <= byte_count + 1;
-- else
-- byte_count <= "0";
-- end if;
-- end if;
--end process;
----
---------------------------------------------------------------------------------------------
---- clock2
----
---------------------------------------------------------------------------------------------
--process(bitCLKx4)
--begin
-- if rising_edge(bitCLKx4) then
-- if send_state = '1' then
-- dataOUTrdy_s <= not dataOUTrdy_s;
-- else
-- dataOUTrdy_s <= '0';
-- end if;
-- end if;
--end process;
----
---------------------------------------------------------------------------------------------
----
---------------------------------------------------------------------------------------------
--out_select_proc: process(byte_count, bytes_r)
--begin
-- case (byte_count) is
-- when "0" => dataOUT_s <= bytes_r(0);
-- when "1" => dataOUT_s <= bytes_r(1);
-- when others =>
-- end case;
--end process;
----
-------------------------------------------------------------------------------------------
-- dataOUT_s (@bitCLKx4) & dataOUTrdy_s (@bitCLKx4, 2nd clock) can be used when
-- decoder is moved up
-------------------------------------------------------------------------------------------
dec_8b10: entity work.dec_8b10_wrap
port map(
RESET => rst,
RBYTECLK => bitCLK, --bitCLKx4,
ABCDEIFGHJ_IN => byte_in, --dataOUT_s,
HGFEDCBA => dataOUT(7 downto 0),
ISK => dataOUT(9 downto 8),
BUSY => busyOut
);
--
dataOUTrdy <= byte0_out_rdy_s or byte1_out_rdy_s; --dataOUTrdy_s;
----
end Behavioral;
| gpl-3.0 | fbd727853e617dd80e36d67d513e3611 | 0.433878 | 3.399396 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/ipv4_types.vhd | 1 | 5,977 | --
--
-- Purpose: This package defines types for use in IPv4
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.axi.all;
use work.arp_types.all;
package ipv4_types is
constant IP_BC_ADDR : std_logic_vector (31 downto 0) := x"c0a800ff";
-- constant MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"1458D001AA73";
constant MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"ffffffffffff";
--------------
-- IPv4 TX --
--------------
-- coding for result in tx
constant IPTX_RESULT_NONE : std_logic_vector (1 downto 0) := "00";
constant IPTX_RESULT_SENDING : std_logic_vector (1 downto 0) := "01";
constant IPTX_RESULT_ERR : std_logic_vector (1 downto 0) := "10";
constant IPTX_RESULT_SENT : std_logic_vector (1 downto 0) := "11";
type ipv4_tx_header_type is record
protocol : std_logic_vector (7 downto 0);
data_length : std_logic_vector (15 downto 0); -- user data size, bytes
dst_ip_addr : std_logic_vector (31 downto 0);
end record;
type ipv4_tx_type is record
hdr : ipv4_tx_header_type; -- header to tx
data : axi_out_type; -- tx axi bus
end record;
--------------
-- IPv4 RX --
--------------
-- coding for last_error_code in rx hdr
constant RX_EC_NONE : std_logic_vector (3 downto 0) := x"0";
constant RX_EC_ET_ETH : std_logic_vector (3 downto 0) := x"1"; -- early termination in ETH hdr phase
constant RX_EC_ET_IP : std_logic_vector (3 downto 0) := x"2"; -- early termination in IP hdr phase
constant RX_EC_ET_USER : std_logic_vector (3 downto 0) := x"3"; -- early termination in USER DATA phase
type ipv4_rx_header_type is record
is_valid : std_logic;
protocol : std_logic_vector (7 downto 0);
data_length : std_logic_vector (15 downto 0); -- user data size, bytes
src_ip_addr : std_logic_vector (31 downto 0);
num_frame_errors : std_logic_vector (7 downto 0);
last_error_code : std_logic_vector (3 downto 0); -- see RX_EC_xxx constants
is_broadcast : std_logic; -- set if the msg received is a broadcast
end record;
type ipv4_rx_type is record
hdr : ipv4_rx_header_type; -- header received
data : axi_in_type; -- rx axi bus
end record;
type ip_control_type is record
arp_controls : arp_control_type;
end record;
-------------
-- ICMP TX --
-------------
type icmp_tx_header_type is record
dst_ip_addr : std_logic_vector (31 downto 0); -- not part of the real header
icmp_pay_len : std_logic_vector (15 downto 0); -- not part of the real header
icmp_type : std_logic_vector (7 downto 0);
icmp_code : std_logic_vector (7 downto 0);
icmp_chksum : std_logic_vector (15 downto 0);
icmp_ident : std_logic_vector (15 downto 0);
icmp_seqNum : std_logic_vector (15 downto 0);
end record;
type icmp_tx_type is record
hdr : icmp_tx_header_type;
payload : axi_out_type; -- tx axi bus
end record;
-------------
-- ICMP RX --
-------------
type icmp_rx_header_type is record
src_ip_addr : std_logic_vector (31 downto 0); -- not part of the real header
icmp_type : std_logic_vector (7 downto 0);
icmp_code : std_logic_vector (7 downto 0);
icmp_chksum : std_logic_vector (15 downto 0);
icmp_ident : std_logic_vector (15 downto 0);
icmp_seqNum : std_logic_vector (15 downto 0);
end record;
type icmp_rx_type is record
hdr : icmp_rx_header_type;
payload : axi_in_type;
end record;
------------
-- UDP TX --
------------
-- coding for result in tx
constant UDPTX_RESULT_NONE : std_logic_vector (1 downto 0) := "00";
constant UDPTX_RESULT_SENDING : std_logic_vector (1 downto 0) := "01";
constant UDPTX_RESULT_ERR : std_logic_vector (1 downto 0) := "10";
constant UDPTX_RESULT_SENT : std_logic_vector (1 downto 0) := "11";
type udp_tx_header_type is record
dst_ip_addr : std_logic_vector (31 downto 0);
dst_port : std_logic_vector (15 downto 0);
src_port : std_logic_vector (15 downto 0);
data_length : std_logic_vector (15 downto 0); -- user data size, bytes
checksum : std_logic_vector (15 downto 0);
end record;
type udp_tx_type is record
hdr : udp_tx_header_type; -- header received
data : axi_out_type; -- tx axi bus
end record;
------------
-- UDP RX --
------------
type udp_rx_header_type is record
is_valid : std_logic;
src_ip_addr : std_logic_vector (31 downto 0);
src_port : std_logic_vector (15 downto 0);
dst_port : std_logic_vector (15 downto 0);
data_length : std_logic_vector (15 downto 0); -- user data size, bytes
end record;
type udp_rx_type is record
hdr : udp_rx_header_type; -- header received
data : axi_in_type; -- rx axi bus
end record;
type udp_addr_type is record
ip_addr : std_logic_vector (31 downto 0);
port_num : std_logic_vector (15 downto 0);
end record;
type udp_control_type is record
ip_controls : ip_control_type;
end record;
type udp_response is record
resp_header : std_logic_vector (31 downto 0);
resp_data : std_logic_vector (15 downto 0);
end record;
type resp_data is record
sn : std_logic_vector (31 downto 0);
vmm_id : std_logic_vector (15 downto 0);
cmd : std_logic_vector (15 downto 0);
error : std_logic_vector (31 downto 0);
end record;
type resp_header is record
test : std_logic_vector (15 downto 0);
end record;
end ipv4_types;
| gpl-3.0 | c2d7b0f78ea50715becde91e45ed2114 | 0.56868 | 3.243082 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/Testbenches/RSA_512_tb.vhd | 1 | 9,759 |
--Copyright 2017 Christoffer Mathiesen
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity RSA_512_tb is
end RSA_512_tb;
--This is an improved version of the tb from the original creators of
--RSA_512.
--The original can be found in the folder containing the RSA_512 code
--The tb is self-testing. If you want to check exponent- modulo- and r_c values of your own, you can freely insert them
--instead of the ones there currently. Take note that you'll have to MANUALLY calculate the result of the
--encryption of ( message_1^exponent_1 ) mod modulo_1
--Useful tool to do just that can be found at http://www.mobilefish.com/services/big_number_equation/big_number_equation.php#equation_output
--The tb will take about 0.6 ms of in-simulation time.
architecture behavior of RSA_512_tb is
-- Component Declaration
component rsa_top
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
start_in : in std_logic;
x : in std_logic_vector(15 downto 0);
y : in std_logic_vector(15 downto 0);
m : in std_logic_vector(15 downto 0);
r_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector(15 downto 0);
valid_out : out std_logic;
bit_size : in std_logic_vector(15 downto 0)
);
end component;
--constants (values to test)
constant sanity_check : std_logic_vector(511 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";--RSA with val 1 should always result in 1
constant message_1 : std_logic_vector(511 downto 0) := x"abc123abc123abc123abc123abc123abc123abc123abc123abc123abc123abcabc123abc123abc123abc123abc123abc123abc123abc123abc123abc123abc12";
constant exponent_1 : std_logic_vector(511 downto 0) := x"b15f20094a5fbcd7605b23bb7dbe7d421556df00d266c649d019cfc87eae543f703f6870013851130d3a2ed993ef76a1c377a96b95fe326f7326a319bae5fe01"; --encrypt exponent
constant exponent_2 : std_logic_vector(511 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001"; --decrypt exponent
constant modulo_1 : std_logic_vector(511 downto 0) := x"bb847f2d87e8030926eea2a0a3f89877e6f63c1e2f65f3791e9c85549f48863a1dcc9f8b477c36dfea2573c49fc59259efe83b9996d093b4be09666e904cb17f";
constant R_C_1 : std_logic_vector(511 downto 0) := x"8F80651391C778113C509FDD5C205AE6648A94DBC225A1ECA53F149BCF135AFCAC7E47DF209AC030325E1904AD7D260E236CE56D6753F488E3E489D50A6C2B0E";
constant result_1 : std_logic_vector(511 downto 0) := x"AF42E73EE103ED7F96C40FB6FC14B483031239E4FC813C30B208C68042C9E08789E5D22E59163194498D3DB158AC6F5282943D81D5E59F518086A19BC0B33D9D";--result encrypting message_1
--Inputs
signal clk : std_logic := '1';
signal reset : std_logic := '0';
signal valid_in : std_logic := '0';
signal start_in : std_logic := '0';
signal x : std_logic_vector(15 downto 0) := (others => '0');
signal y : std_logic_vector(15 downto 0) := (others => '0');
signal m : std_logic_vector(15 downto 0) := (others => '0');
signal r_c : std_logic_vector(15 downto 0) := (others => '0');
signal bit_size : std_logic_vector(15 downto 0) := x"0200";
--Outputs
signal s : std_logic_vector(15 downto 0);
signal valid_out : std_logic;
signal result : std_logic_vector(511 downto 0) := (others => '0');
-- Clock period definitions
constant clk_period : time := 1 ns;
--resetting
procedure reset_circuit (modulo : in STD_LOGIC_VECTOR(15 downto 0);
signal reset, valid_in, start_in : out STD_LOGIC;
signal m : out STD_LOGIC_VECTOR(15 downto 0)) is
begin
--hard reset
valid_in <= '0';
start_in <= '0';
reset <= '1';
wait for 10 ns;
reset <= '0';
wait for clk_period*10;
--set up for n_c calculation
m <= modulo;
start_in <= '1';
wait for clk_period;
start_in <= '0';
wait for clk_period*7;
end procedure reset_circuit;
begin
RSA_512 : rsa_top port map (
clk => clk,
reset => reset,
valid_in => valid_in,
start_in => start_in,
x => x,
y => y,
m => m,
r_c => r_c,
s => s,
valid_out => valid_out,
bit_size => bit_size
);
--clock process
process
begin
clk <= not clk;
wait for clk_period/2;
end process;
--Stimulus process
process
begin
--Reset the circuit
reset_circuit(modulo => modulo_1(15 downto 0),
reset => reset,
valid_in => valid_in,
start_in => start_in,
m => m
);
--Have a sanity check with the value 1.
for J in 0 to 31 loop
valid_in <= '1';
x <= sanity_check(16*J+15 downto 16*J);
y <= exponent_1(16*J+15 downto 16*J);
m <= modulo_1(16*J+15 downto 16*J);
r_c <= r_c_1(16*J+15 downto 16*J);
wait for clk_period;
end loop;
valid_in <= '0';
wait until valid_out = '1';
--read all 32 words
for J in 0 to 31 loop
wait for clk_period;
result(16*J+15 downto 16*J) <= s;
end loop;
wait for clk_period * 10;
wait for clk_period/2;
assert result = sanity_check
report "The encrypted value was not 1 after encryption. Something is very wrong! Double check the validity of the Exponent, Modulo and R_C values"
severity failure;
--Reset the circuit
reset_circuit(modulo => modulo_1(15 downto 0),
reset => reset,
valid_in => valid_in,
start_in => start_in,
m => m
);
--Try to encrypt the message message_1.
for J in 0 to 31 loop
valid_in <= '1';
x <= message_1(16*J+15 downto 16*J);
y <= exponent_1(16*J+15 downto 16*J);
m <= modulo_1(16*J+15 downto 16*J);
r_c <= r_c_1(16*J+15 downto 16*J);
wait for clk_period;
end loop;
valid_in <= '0';
wait until valid_out = '1';
--read all 32 words
for J in 0 to 31 loop
wait for clk_period;
result(16*J+15 downto 16*J) <= s;
end loop;
wait for clk_period * 10;
wait for clk_period/2;
assert result = result_1
report "The encrypted message does not match the theoretical result!"
severity failure;
--Reset the circuit
reset_circuit(modulo => modulo_1(15 downto 0),
reset => reset,
valid_in => valid_in,
start_in => start_in,
m => m
);
--Try to decrypt the result from previous.
for J in 0 to 31 loop
valid_in <= '1';
x <= result(16*J+15 downto 16*J);
y <= exponent_2(16*J+15 downto 16*J);
m <= modulo_1(16*J+15 downto 16*J);
r_c <= r_c_1(16*J+15 downto 16*J);
wait for clk_period;
end loop;
valid_in <= '0';
wait until valid_out = '1';
--read all 32 words
for J in 0 to 31 loop
wait for clk_period;
result(16*J+15 downto 16*J) <= s;
end loop;
wait for clk_period * 10;
wait for clk_period/2;
assert result = message_1
report "The decryption did not result in the original message!"
severity failure;
report "The testbench finished successfully!"
severity failure;
wait;
end process;
process
begin
wait for 1 ms;
report "It has gone way too long with the standard clock of 1ns! Make sure all the flags are being set correctly and that the memories are functional!"
severity failure;
end process;
end behavior;
| bsd-3-clause | 5a95fe82023178e7454f724149bc682d | 0.622502 | 3.716299 | false | false | false | false |
HackLinux/ION | src/testbench/ion_cpu_tb.vhdl | 1 | 15,208 | --##############################################################################
-- ion_cpu_tb.vhdl -- Test bench for standalone CPU.
--
-- Simulates the CPU connected to fake memory on both buses.
-- The size and contents of the simulated memory are defined in package
-- sim_params_pkg.
--
--------------------------------------------------------------------------------
-- MEMORY MAP (except IO areas, see below):
--
-- Code ROM Data RAM
-- -----------------------------
-- Code [00000000..FFFFFFFF] : R/O
-- Data [00000000..BFBFFFFF] : R/W
-- Data [BFC00000..BFCFFFFF] : R/O
-- Data [BFD00000..FFFFFFFF] : R/W
-- -----------------------------
--
-- Note we only simulate two separate blocks, ROM for code and RAM for data.
-- Both are mirrored all over the decoded memory spaces.
-- The code ROM is accessible from the data bus so that SW constants can be
-- easily reached.
--
--------------------------------------------------------------------------------
-- FIXME no support for simulating external IRQs.
--------------------------------------------------------------------------------
-- SIMULATED IO DEVICES:
-- Apart from the fake UART implemented in package ion_tb_pkg, this test bench
-- simulates the following ports:
--
-- 20010020: Debug register 0 (R/W). -- FIXME unimplemented
-- 20010024: Debug register 1 (R/W). -- FIXME unimplemented
-- 20010028: Debug register 2 (R/W). -- FIXME unimplemented
-- 2001002c: Debug register 3 (R/W). -- FIXME unimplemented
-- 20010030: Wait states for simulated code memory accesses (W/o).
-- 20010034: Wait states for simulated data memory accesses (W/o).
--
-- NOTE: These addresses are for write accesses only. For read accesses, the
-- debug registers 0..3 are mirrored over all the io address range 2001xxxxh.
--
-- The debug registers 0 to 3 can only be used to test 32-bit i/o.
-- All of these registers can only be addressed as 32-bit words. Any other type
-- of access will yield undefined results.
--
-- These registers are only write-enabled if the generic ENABLE_DEBUG_REGISTERS
-- is TRUE.
--------------------------------------------------------------------------------
-- Console logging:
--
-- The TB implements a simple, fake console at address 0x20000000.
-- Any bytes written to that address will be logged to text file
-- "hw_sim_console_log.txt".
--
-- IMPORTANT: The code that echoes UART TX data to the simulation console does
-- line buffering; it will not print anything until it gets a CR (0x0d), and
-- will ifnore LFs (0x0a). Bear this in mind if you see no output when you
-- expect it.
--
--------------------------------------------------------------------------------
-- WARNING: This TB will only work on Modelsim; uses custom library SignalSpy.
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Project packages.
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
-- Tst bench support packages.
use std.textio.all;
use work.txt_util.all;
use work.ION_TB_PKG.all;
-- Simulation parameters defined in the SW makefile (generated package).
use work.SIM_PARAMS_PKG.all;
-- Hardware parameters & memory contents from SW build (generated package).
use work.OBJ_CODE_PKG.all;
entity ION_CPU_TB is
generic (
CODE_WCYCLES : integer := 1;
DATA_WCYCLES : integer := 0;
ENABLE_DEBUG_REGISTERS : boolean := false
);
end;
architecture testbench of ION_CPU_TB is
-- Simulation clock rate
constant CLOCK_RATE : integer := 50e6;
-- Simulation clock period
constant T : time := (1.0e9/real(CLOCK_RATE)) * 1 ns;
--------------------------------------------------------------------------------
-- Memory.
-- For CPU verification, we'll connect a data array to the CPU data port with no
-- intervening cache, like TCMs.
-- For the data array, we'll use the data memory size and initialization values.
constant DTCM_SIZE : integer := DATA_MEM_SIZE;
constant DTCM_ADDR_SIZE : integer := log2(DTCM_SIZE);
-- Using shared variables for big memory arrays speeds up simulation a lot;
-- see Modelsim 6.3 User Manual, section on 'Modelling Memory'.
-- WARNING: I have only tested this construct with Modelsim SE 6.3.
shared variable dtcm : t_word_table(0 to DTCM_SIZE-1) := (others => X"00000000");
signal dtcm_addr : std_logic_vector(DTCM_ADDR_SIZE downto 2);
signal dtcm_data : t_word;
signal data_dtcm_ce : std_logic;
signal data_dtcm_ce_reg : std_logic;
signal data_rd_en_reg : std_logic;
signal dtcm_wait : std_logic;
signal data_ctcm_ce : std_logic;
signal data_dtcm : t_word;
signal data_ctcm : t_word;
-- For the code array, we'll use the code memory size and initialization values.
constant CTCM_SIZE : integer := CODE_MEM_SIZE;
constant CTCM_ADDR_SIZE : integer := log2(CTCM_SIZE);
shared variable ctcm : t_word_table(0 to CTCM_SIZE-1) := objcode_to_wtable(obj_code, CTCM_SIZE);
signal ctcm_addr : std_logic_vector(CTCM_ADDR_SIZE downto 2);
signal ctcm_data : t_word;
signal ctcm_wait : std_logic;
signal code_wait_ctr : integer range -2 to 63;
signal data_wait_ctr : integer range -2 to 63;
signal code_ctcm_ce_reg : std_logic;
signal code_ctcm : t_word;
--------------------------------------------------------------------------------
-- CPU interface.
signal clk : std_logic := '0';
signal clk_delayed : std_logic;
signal reset : std_logic := '1';
signal data_mosi : t_cpumem_mosi;
signal data_miso : t_cpumem_miso;
signal code_mosi : t_cpumem_mosi;
signal code_miso : t_cpumem_miso;
signal cache_mosi : t_cache_mosi;
signal icache_miso : t_cache_miso;
signal dcache_miso : t_cache_miso;
signal irq : std_logic_vector(7 downto 0);
--------------------------------------------------------------------------------
-- Debug registers.
signal debug_reg_ce : std_logic;
signal wait_states_code : unsigned(5 downto 0) := (others => '0');
signal wait_states_data : unsigned(5 downto 0) := (others => '0');
--------------------------------------------------------------------------------
-- Logging signals & simulation control.
signal done : std_logic := '0';
-- Log file
file log_file: TEXT open write_mode is "hw_sim_log.txt";
-- Console output log file
file con_file: TEXT open write_mode is "hw_sim_console_log.txt";
-- All the info needed by the logger is here
signal log_info : t_log_info;
--------------------------------------------------------------------------------
begin
cpu: entity work.ION_CPU
generic map (
XILINX_REGBANK => "distributed"
)
port map (
CLK_I => clk,
RESET_I => reset,
DATA_MOSI_O => data_mosi,
DATA_MISO_I => data_miso,
CODE_MOSI_O => code_mosi,
CODE_MISO_I => code_miso,
CACHE_CTRL_MOSI_O => cache_mosi,
CACHE_CTRL_MISO_I => cache_miso,
IRQ_I => irq
);
-- Master clock: free running clock used as main module clock --------------
run_master_clock:
process(done, clk)
begin
if done = '0' then
clk <= not clk after T/2;
end if;
end process run_master_clock;
clk_delayed <= clk after 1 ns;
-- Main simulation process: reset MCU and wait for fixed period ------------
drive_uut:
process
variable l : line;
begin
wait for T*4;
reset <= '0';
wait for T*SIMULATION_LENGTH;
-- Flush console output to log console file (in case the end of the
-- simulation caught an unterminated line in the buffer)
if log_info.con_line_ix > 1 then
write(l, log_info.con_line_buf(1 to log_info.con_line_ix));
writeline(con_file, l);
end if;
print("TB finished");
done <= '1';
wait;
end process drive_uut;
-- Data memory -------------------------------------------------------------
dtcm_addr <= data_mosi.addr(dtcm_addr'high downto 2);
data_miso.mwait <= dtcm_wait;
data_ctcm_ce <= '1' when data_mosi.addr(31 downto 20) = X"bfc" else '0';
data_dtcm_ce <= '1' when data_mosi.addr(31 downto 28) /= X"2" and
data_ctcm_ce='0'
else '0';
-- Simulated data RAM write port.
-- Note we ignore the wait states; we get the data when it's in DATA_MOSI
-- and let the CPU deal with the simulated wait states.
-- This is the behavior expected from a real ION bus slave.
simulated_dtcm_write:
process(clk)
begin
if clk'event and clk='1' then
if data_dtcm_ce='1' then
if data_mosi.wr_be(0)='1' then
dtcm(to_integer(unsigned(dtcm_addr)))(7 downto 0) := data_mosi.wr_data(7 downto 0);
end if;
if data_mosi.wr_be(1)='1' then
dtcm(to_integer(unsigned(dtcm_addr)))(15 downto 8) := data_mosi.wr_data(15 downto 8);
end if;
if data_mosi.wr_be(2)='1' then
dtcm(to_integer(unsigned(dtcm_addr)))(23 downto 16) := data_mosi.wr_data(23 downto 16);
end if;
if data_mosi.wr_be(3)='1' then
dtcm(to_integer(unsigned(dtcm_addr)))(31 downto 24) := data_mosi.wr_data(31 downto 24);
end if;
end if;
end if;
end process simulated_dtcm_write;
-- Simulated data RAM read port.
data_memory:
process(clk)
begin
if clk'event and clk='1' and data_dtcm_ce='1' then
-- Update data bus the cycle after rd_en is asserted if there's no
-- wait states, or the cycle after wait goes low otherwise.
--if (to_integer(wait_states_data)=0) or (data_wait_ctr = 1) then
data_dtcm <= dtcm(to_integer(unsigned(dtcm_addr)));
--end if;
end if;
end process data_memory;
-- Simulated code RAM read port connected to the data bus.
code_memory_as_data:
process(clk)
begin
if clk'event and clk='1' and data_ctcm_ce='1' then
-- Update data bus the cycle after rd_en is asserted if there's no
-- wait states, or the cycle after wait goes low otherwise.
if (to_integer(wait_states_data)=0) or (data_wait_ctr = 1) then
data_ctcm <= ctcm(to_integer(unsigned(dtcm_addr)));
end if;
end if;
end process code_memory_as_data;
-- Read data will come from either the code array or the data array; we
-- to drive the mux with a delayed CE, the data bus is pipelined.
-- The data abus will be driven only when the ION bus specs say so, to
-- help pinpoint bugs in the bus logic.
data_miso.rd_data <=
data_dtcm when data_dtcm_ce_reg='1' and data_wait_ctr=0 else
data_ctcm when data_dtcm_ce_reg='0' and data_wait_ctr=0 else
(others => 'Z');
-- TODO Debug IO register inputs are unimplemented.
data_mem_wait_states:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
data_wait_ctr <= -2;
elsif data_dtcm_ce='1' and (data_mosi.rd_en='1' or data_mosi.wr_be/="0000") then
data_wait_ctr <= to_integer(wait_states_data);
elsif data_wait_ctr >= -1 then
data_wait_ctr <= data_wait_ctr - 1;
else
data_wait_ctr <= -2;
end if;
data_dtcm_ce_reg <= data_dtcm_ce;
data_rd_en_reg <= data_mosi.rd_en;
end if;
end process data_mem_wait_states;
dtcm_wait <= '1' when data_wait_ctr > 0 else '0';
-- Code memory -------------------------------------------------------------
ctcm_addr <= code_mosi.addr(ctcm_addr'high downto 2);
code_miso.mwait <= ctcm_wait;
code_memory:
process(clk)
begin
if clk'event and clk='1' then
-- Update data bus the cycle after rd_en is asserted if there's no
-- wait states, or the cycle after wait goes low otherwise.
if (to_integer(wait_states_code)=0) or (code_wait_ctr = 1) then
code_ctcm <= ctcm(to_integer(unsigned(ctcm_addr)));
end if;
end if;
end process code_memory;
code_miso.rd_data <=
code_ctcm when code_wait_ctr <= 0 else
(others => 'Z');
code_mem_wait_states:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
code_wait_ctr <= -2;
elsif code_mosi.rd_en='1' then
code_wait_ctr <= to_integer(wait_states_code);
elsif code_wait_ctr >= -1 then
code_wait_ctr <= code_wait_ctr - 1;
else
code_wait_ctr <= -2;
end if;
code_ctcm_ce_reg <= code_mosi.rd_en;
end if;
end process code_mem_wait_states;
ctcm_wait <= '1' when code_wait_ctr > 0 else '0';
-- Debug registers ---------------------------------------------------------
debug_reg_ce <= '1' when data_mosi.addr(31 downto 16) = X"2001" else '0';
debug_register_writes:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
wait_states_code <= to_unsigned(CODE_WCYCLES,wait_states_code'length);
wait_states_data <= to_unsigned(DATA_WCYCLES,wait_states_data'length);
else
if debug_reg_ce='1' and data_mosi.wr_be/="0000" and
ENABLE_DEBUG_REGISTERS then
case data_mosi.addr(15 downto 0) is
when X"0030" =>
wait_states_code <= unsigned(data_mosi.wr_data(5 downto 0));
when X"0034" =>
wait_states_data <= unsigned(data_mosi.wr_data(5 downto 0));
when others => -- ignore access.
end case;
end if;
end if;
end if;
end process debug_register_writes;
-- Placeholder signals, to be completed ------------------------------------
irq <= (others => '0');
icache_miso.present <= '0';
dcache_miso.present <= '0';
-- Logging process: launch logger function ---------------------------------
log_execution:
process
begin
log_cpu_activity(clk_delayed, reset, done,
"ION_CPU_TB", "cpu",
log_info, "log_info",
LOG_TRIGGER_ADDRESS, log_file, con_file);
wait;
end process log_execution;
end architecture testbench;
| lgpl-3.0 | dfabd6161643c9f5769a63df1880663d | 0.531365 | 4.008434 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/LFSR/tb_LFSR.vhd | 1 | 2,331 | ----------------------------------------------------------------------------------------------------
-- LFSR Test-bench Top Level
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tb_clockgen_pkg.all;
use work.tb_write_csv_pkg.all;
use work.lfsr_pkg.all;
--This module is a test-bench for simulating the LFSR
entity tb_lfsr is
end tb_lfsr;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture sim of tb_lfsr is
signal rst : std_logic := '0';
signal clk : std_logic := '0';
signal feedback : std_logic_vector(0 downto 0) := (others => '0');
signal polynomial : std_logic_vector(15 downto 0) := (others => '0');
signal seed : std_logic_vector(15 downto 0) := (others => '0');
signal pr_num : std_logic_vector(15 downto 0) := (others => '0');
begin
--Instantiate clock generator
clk1 : tb_clockgen
generic map(PERIOD => 10ns,
DUTY_CYCLE => 0.50)
port map( clk => clk);
--Instantiate unit under test
uut : entity work.lfsr(structural)
port map( clk => clk,
rst => rst,
poly_mask => polynomial,
seed => seed,
feedin => feedback,
feedout => feedback,
history => pr_num);
writer : tb_write_csv
generic map(FILENAME => "prng.csv")
port map( clk => clk,
data => pr_num);
--Main Process
main: process
begin
polynomial <= (15 => '1', 14 => '1', 12 => '1', 3 =>'1', others => '0');
seed <= (others => '1');
rst <= '1';
wait for 11ns;
rst <= '0';
wait;
end process;
end sim;
| mit | cc69e093dba8ec2a884cf6382d2fd58d | 0.371943 | 4.928118 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/arp_STORE_br.vhd | 2 | 10,776 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_STORE_br - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- ARP storage table using block ram with lookup based on IP address
-- implements upto 255 entries with sequential search
-- uses round robin overwrite when full (LRU would be better, but ...)
--
-- store may take a number of cycles and the request is latched
-- lookup may take a number of cycles. Assumes that request signals remain valid during lookup
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_unsigned.all;
use work.arp_types.all;
entity arp_STORE_br is
generic (
MAX_ARP_ENTRIES : integer := 255 -- max entries in the store
);
port (
-- read signals
read_req : in arp_store_rdrequest_t; -- requesting a lookup or store
read_result : out arp_store_result_t; -- the result
-- write signals
write_req : in arp_store_wrrequest_t; -- requesting a lookup or store
-- control and status signals
clear_store : in std_logic; -- erase all entries
entry_count : out unsigned(7 downto 0); -- how many entries currently in store
-- system signals
clk : in std_logic;
reset : in std_logic
);
end arp_STORE_br;
architecture Behavioral of arp_STORE_br is
type st_state_t is (IDLE, PAUSE, SEARCH, FOUND, NOT_FOUND);
type ip_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(31 downto 0);
type mac_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(47 downto 0);
subtype addr_t is integer range 0 to MAX_ARP_ENTRIES;
type count_mode_t is (RST, INCR, HOLD);
type mode_t is (MREAD, MWRITE);
-- state variables
signal ip_ram : ip_ram_t; -- will be implemented as block ram
signal mac_ram : mac_ram_t; -- will be implemented as block ram
signal st_state : st_state_t;
signal next_write_addr : addr_t; -- where to make the next write
signal num_entries : addr_t; -- number of entries in the store
signal next_read_addr : addr_t; -- next addr to read from
signal entry_found : arp_entry_t; -- entry found in search
signal mode : mode_t; -- are we writing or reading?
signal req_entry : arp_entry_t; -- entry latched from req
-- busses
signal next_st_state : st_state_t;
signal arp_entry_val : arp_entry_t;
signal mode_val : mode_t;
signal write_addr : addr_t; -- actual write address to use
signal read_result_int : arp_store_result_t;
-- control signals
signal set_st_state : std_logic;
signal set_next_write_addr : count_mode_t;
signal set_num_entries : count_mode_t;
signal set_next_read_addr : count_mode_t;
signal write_ram : std_logic;
signal set_entry_found : std_logic;
signal set_mode : std_logic;
function read_status(status : arp_store_rslt_t; signal mode : mode_t) return arp_store_rslt_t is
variable ret : arp_store_rslt_t;
begin
case status is
when IDLE =>
ret := status;
when others =>
if mode = MWRITE then
ret := BUSY;
else
ret := status;
end if;
end case;
return ret;
end read_status;
begin
combinatorial : process (
-- input signals
read_req, write_req, clear_store, reset,
-- state variables
ip_ram, mac_ram, st_state, next_write_addr, num_entries,
next_read_addr, entry_found, mode, req_entry,
-- busses
next_st_state, arp_entry_val, mode_val, write_addr, read_result_int,
-- control signals
set_st_state, set_next_write_addr, set_num_entries, set_next_read_addr, set_entry_found,
write_ram, set_mode
)
begin
-- set output followers
read_result_int.status <= IDLE;
read_result_int.entry <= entry_found;
entry_count <= to_unsigned(num_entries, 8);
-- set bus defaults
next_st_state <= IDLE;
mode_val <= MREAD;
write_addr <= next_write_addr;
-- set signal defaults
set_st_state <= '0';
set_next_write_addr <= HOLD;
set_num_entries <= HOLD;
set_next_read_addr <= HOLD;
write_ram <= '0';
set_entry_found <= '0';
set_mode <= '0';
-- STORE FSM
case st_state is
when IDLE =>
if write_req.req = '1' then
-- need to search to see if this IP already there
set_next_read_addr <= RST; -- start lookup from beginning
mode_val <= MWRITE;
set_mode <= '1';
next_st_state <= PAUSE;
set_st_state <= '1';
elsif read_req.req = '1' then
set_next_read_addr <= RST; -- start lookup from beginning
mode_val <= MREAD;
set_mode <= '1';
next_st_state <= PAUSE;
set_st_state <= '1';
end if;
when PAUSE =>
-- wait until read addr is latched and we get first data out of the ram
read_result_int.status <= read_status(BUSY, mode);
set_next_read_addr <= INCR;
next_st_state <= SEARCH;
set_st_state <= '1';
when SEARCH =>
read_result_int.status <= read_status(SEARCHING, mode);
-- check if have a match at this entry
if req_entry.ip = arp_entry_val.ip and next_read_addr <= num_entries then
-- found it
set_entry_found <= '1';
next_st_state <= FOUND;
set_st_state <= '1';
elsif next_read_addr > num_entries or next_read_addr >= MAX_ARP_ENTRIES then
-- reached end of entry table
read_result_int.status <= read_status(NOT_FOUND, mode);
next_st_state <= NOT_FOUND;
set_st_state <= '1';
else
-- no match at this entry , go to next
set_next_read_addr <= INCR;
end if;
when FOUND =>
read_result_int.status <= read_status(FOUND, mode);
if mode = MWRITE then
write_addr <= next_read_addr - 1;
write_ram <= '1';
next_st_state <= IDLE;
set_st_state <= '1';
elsif read_req.req = '0' then -- wait in this state until request de-asserted
next_st_state <= IDLE;
set_st_state <= '1';
end if;
when NOT_FOUND =>
read_result_int.status <= read_status(NOT_FOUND, mode);
if mode = MWRITE then
-- need to write into the next free slot
write_addr <= next_write_addr;
write_ram <= '1';
set_next_write_addr <= INCR;
if num_entries < MAX_ARP_ENTRIES then
-- if not full, count another entry (if full, it just wraps)
set_num_entries <= INCR;
end if;
next_st_state <= IDLE;
set_st_state <= '1';
elsif read_req.req = '0' then -- wait in this state until request de-asserted
next_st_state <= IDLE;
set_st_state <= '1';
end if;
end case;
end process;
sequential : process (clk)
begin
if rising_edge(clk) then
-- ram processing
if write_ram = '1' then
ip_ram(write_addr) <= req_entry.ip;
mac_ram(write_addr) <= req_entry.mac;
end if;
if next_read_addr < MAX_ARP_ENTRIES then
arp_entry_val.ip <= ip_ram(next_read_addr);
arp_entry_val.mac <= mac_ram(next_read_addr);
else
arp_entry_val.ip <= (others => '0');
arp_entry_val.mac <= (others => '0');
end if;
read_result <= read_result_int;
if reset = '1' or clear_store = '1' then
-- reset state variables
st_state <= IDLE;
next_write_addr <= 0;
num_entries <= 0;
next_read_addr <= 0;
entry_found.ip <= (others => '0');
entry_found.mac <= (others => '0');
req_entry.ip <= (others => '0');
req_entry.mac <= (others => '0');
mode <= MREAD;
else
-- Next req_state processing
if set_st_state = '1' then
st_state <= next_st_state;
else
st_state <= st_state;
end if;
-- mode setting and write request latching
if set_mode = '1' then
mode <= mode_val;
if mode_val = MWRITE then
req_entry <= write_req.entry;
else
req_entry.ip <= read_req.ip;
req_entry.mac <= (others => '0');
end if;
else
mode <= mode;
req_entry <= req_entry;
end if;
-- latch entry found
if set_entry_found = '1' then
entry_found <= arp_entry_val;
else
entry_found <= entry_found;
end if;
-- next_write_addr counts and wraps
case set_next_write_addr is
when HOLD => next_write_addr <= next_write_addr;
when RST => next_write_addr <= 0;
when INCR => if next_write_addr < MAX_ARP_ENTRIES-1 then next_write_addr <= next_write_addr + 1; else next_write_addr <= 0; end if;
end case;
-- num_entries counts and holds at max
case set_num_entries is
when HOLD => num_entries <= num_entries;
when RST => num_entries <= 0;
when INCR => if next_write_addr < MAX_ARP_ENTRIES then num_entries <= num_entries + 1; else num_entries <= num_entries; end if;
end case;
-- next_read_addr counts and wraps
case set_next_read_addr is
when HOLD => next_read_addr <= next_read_addr;
when RST => next_read_addr <= 0;
when INCR => if next_read_addr < MAX_ARP_ENTRIES then next_read_addr <= next_read_addr + 1; else next_read_addr <= 0; end if;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 94fa84a616858d191d7daecd1c87679b | 0.522736 | 3.806429 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN2_direct.vhd | 3 | 3,427 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN2_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data driver for EPROC_IN2 module
entity EPROC_IN2_direct is
port (
bitCLK : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (1 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN2_direct;
architecture Behavioral of EPROC_IN2_direct is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
signal word10b : std_logic_vector (9 downto 0) := "1100000000"; -- comma
signal word8b : std_logic_vector (7 downto 0) := (others=>'0');
signal inpcount : std_logic_vector (1 downto 0) := (others=>'0');
signal word8bRdy, word10bRdy : std_logic := '0';
begin
-------------------------------------------------------------------------------------------
-- input counter 0 to 3
-------------------------------------------------------------------------------------------
input_count: process(bitCLK, rst)
begin
if rst = '1' then
inpcount <= (others=>'0');
elsif bitCLK'event and bitCLK = '1' then
inpcount <= inpcount + 1;
end if;
end process;
-------------------------------------------------------------------------------------------
-- input mapping
-------------------------------------------------------------------------------------------
input_map: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case inpcount is
when "00" => word8b(1 downto 0) <= edataIN;
when "01" => word8b(3 downto 2) <= edataIN;
when "10" => word8b(5 downto 4) <= edataIN;
when "11" => word8b(7 downto 6) <= edataIN;
when others =>
end case;
end if;
end process;
-------------------------------------------------------------------------------------------
-- output (code = "00" = data)
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if inpcount = "11" then
word8bRdy <= '1';
else
word8bRdy <= '0';
end if;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if word8bRdy = '1' then
word10b <= "00" & word8b; -- data
word10bRdy <= '1';
else
word10bRdy <= '0';
end if;
end if;
end process;
dataOUT <= word10b;
dataOUTrdy_pulse: pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(bitCLKx4, word10bRdy, dataOUTrdy);
end Behavioral;
| gpl-3.0 | 80b8b6d2e705df781390ac66512a22c9 | 0.42136 | 4.246592 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/FIR_Filter/multichannel_fir_filter.vhd | 1 | 5,840 | --------------------------------------------------------------------------------------------------
-- Multi-channel FIR Filter
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package multichannel_fir_filter_pkg is
--FIR filter component declaration
component multichannel_fir_filter is
generic( h0 : coefficient_array;
h1 : coefficient_array;
INIT_SEL : std_logic_vector(1 downto 0) := b"01");
port( clk : in std_logic;
clk_2x : in std_logic;
rst : in std_logic;
x1 : in sig;
x2 : in sig;
y1 : out fir_sig;
y2 : out fir_sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
use work.multichannel_fir_tap_pkg.all;
use work.muxer_pkg.all;
use work.demuxer_pkg.all;
entity multichannel_fir_filter is
generic( h0 : coefficient_array;
h1 : coefficient_array;
INIT_SEL : std_logic_vector(1 downto 0) := b"01");
port( clk : in std_logic;
clk_2x : in std_logic;
rst : in std_logic;
x1 : in sig;
x2 : in sig;
y1 : out fir_sig;
y2 : out fir_sig);
end multichannel_fir_filter;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of multichannel_fir_filter is
constant INPUT_MUXER_INIT_SEL : std_logic_vector
:= INIT_SEL;
--account for past delay by rotating left
constant OUTPUT_MUXER_INIT_SEL : std_logic_vector
:= std_logic_vector(rotate_left(unsigned(INIT_SEL), h0'length));
signal xs : std_logic_vector(NUM_SIG_BITS-1 downto 0) := (others => '0');
signal x_chain : sig_array(h0'range) := (others => (others => '0'));
signal running_sum : fir_sig_array(h0'range) := (others => (others => '0'));
signal y1_slv : std_logic_vector(y1'range) := (others => '0');
signal y2_slv : std_logic_vector(y2'range) := (others => '0');
begin
--mux input signals into one signal
mux_sigs : muxer
generic map(INIT_SEL => INPUT_MUXER_INIT_SEL)
port map(clk => clk,
clk_2x => clk_2x,
rst => rst,
sig1 => std_logic_vector(x1),
sig2 => std_logic_vector(x2),
sigs => xs);
filter_loop : for tap in h0'low to h0'high generate
--Setup the initial selection for the coefficient muxers. The selection is dependent on the
--current tap. The rotate right accounts for coef reg delay inside the tap.
constant COEF_MUXER_INIT_SEL : std_logic_vector
:= std_logic_vector(rotate_right(rotate_left(unsigned(INIT_SEL), tap-h0'low),1));
signal coef : std_logic_vector(coefficient'range) := (others => '0');
begin
--choose the coefficient
mux_coefs : muxer
generic map(INIT_SEL => COEF_MUXER_INIT_SEL)
port map( clk => clk,
clk_2x => clk_2x,
rst => rst,
sig1 => std_logic_vector(h0(tap)),
sig2 => std_logic_vector(h1(tap)),
sigs => coef);
--generate taps of the fir filter
head_tap_gen : if tap = h0'low generate
head_tap : multichannel_fir_tap
port map(clk => clk_2x,
rst => rst,
coef => signed(coef),
sig_in => signed(xs),
sig_out => x_chain(tap),
sum_in => (others => '0'),
sum_out => running_sum(tap));
end generate; --if head tap
tail_taps_gen : if tap /= h0'low generate
tail_tap : multichannel_fir_tap
port map(clk => clk_2x,
rst => rst,
coef => signed(coef),
sig_in => x_chain(tap-1),
sig_out => x_chain(tap),
sum_in => running_sum(tap-1),
sum_out => running_sum(tap));
end generate; --if tail taps
end generate; --filter loop
--demux running sum to outputs
demux_sigs : demuxer
generic map(INIT_SEL => OUTPUT_MUXER_INIT_SEL)
port map(clk => clk,
clk_2x => clk_2x,
rst => rst,
sigs => std_logic_vector(running_sum(h0'high)),
sig1 => y1_slv,
sig2 => y2_slv);
y1 <= signed(y1_slv);
y2 <= signed(y2_slv);
end behave;
| mit | 30d78e3d7ab7f47b0e2d2a6c619c9be0 | 0.410274 | 4.374532 | false | false | false | false |
rkrajnc/minimig-mist | rtl/tg68k/TG68K_Pack.vhd | 1 | 10,542 | ------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2013 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package TG68K_Pack is
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_AnXn1, ld_AnXn2, st_dAn1, ld_AnXnbd1, ld_AnXnbd2, ld_AnXnbd3,
ld_229_1, ld_229_2, ld_229_3, ld_229_4, st_229_1, st_229_2, st_229_3, st_229_4,
st_AnXn1, st_AnXn2, bra1, bsr1, bsr2, nopnop, dbcc1, movem1, movem2, movem3,
andi, op_AxAy, cmpm, link1, link2, unlink1, unlink2, int1, int2, int3, int4, rte1,
rte2, rte3, rte4, rte5, trap00, trap0, trap1, trap2, trap3,
trap4, trap5, trap6, movec1, movep1, movep2, movep3, movep4, movep5, rota1, bf1,
mul1, mul2, mul_end1, mul_end2, div1, div2, div3, div4, div_end1, div_end2, pack1, pack2, pack3);
constant opcMOVE : integer := 0; --
constant opcMOVEQ : integer := 1; --
constant opcMOVESR : integer := 2; --
constant opcMOVECCR : integer := 3; --
constant opcADD : integer := 4; --
constant opcADDQ : integer := 5; --
constant opcOR : integer := 6; --
constant opcAND : integer := 7; --
constant opcEOR : integer := 8; --
constant opcCMP : integer := 9; --
constant opcROT : integer := 10; --
constant opcCPMAW : integer := 11;
constant opcEXT : integer := 12; --
constant opcABCD : integer := 13; --
constant opcSBCD : integer := 14; --
constant opcBITS : integer := 15; --
constant opcSWAP : integer := 16; --
constant opcScc : integer := 17; --
constant andiSR : integer := 18; --
constant eoriSR : integer := 19; --
constant oriSR : integer := 20; --
constant opcMULU : integer := 21; --
constant opcDIVU : integer := 22; --
constant dispouter : integer := 23; --
constant rot_nop : integer := 24; --
constant ld_rot_cnt : integer := 25; --
constant writePC_add : integer := 26; --
constant ea_data_OP1 : integer := 27; --
constant ea_data_OP2 : integer := 28; --
constant use_XZFlag : integer := 29; --
constant get_bfoffset : integer := 30; --
constant save_memaddr : integer := 31; --
constant opcCHK : integer := 32; --
constant movec_rd : integer := 33; --
constant movec_wr : integer := 34; --
constant Regwrena : integer := 35; --
constant update_FC : integer := 36; --
constant linksp : integer := 37; --
constant movepl : integer := 38; --
constant update_ld : integer := 39; --
constant OP1addr : integer := 40; --
constant write_reg : integer := 41; --
constant changeMode : integer := 42; --
constant ea_build : integer := 43; --
constant trap_chk : integer := 44; --
constant store_ea_data : integer := 45; --
constant addrlong : integer := 46; --
constant postadd : integer := 47; --
constant presub : integer := 48; --
constant subidx : integer := 49; --
constant no_Flags : integer := 50; --
constant use_SP : integer := 51; --
constant to_CCR : integer := 52; --
constant to_SR : integer := 53; --
constant OP2out_one : integer := 54; --
constant OP1out_zero : integer := 55; --
constant mem_addsub : integer := 56; --
constant addsub : integer := 57; --
constant directPC : integer := 58; --
constant direct_delta : integer := 59; --
constant directSR : integer := 60; --
constant directCCR : integer := 61; --
constant exg : integer := 62; --
constant get_ea_now : integer := 63; --
constant ea_to_pc : integer := 64; --
constant hold_dwr : integer := 65; --
constant to_USP : integer := 66; --
constant from_USP : integer := 67; --
constant write_lowlong : integer := 68; --
constant write_reminder : integer := 69; --
constant movem_action : integer := 70; --
constant briefext : integer := 71; --
constant get_2ndOPC : integer := 72; --
constant mem_byte : integer := 73; --
constant longaktion : integer := 74; --
constant opcRESET : integer := 75; --
constant opcBF : integer := 76; --
constant opcBFwb : integer := 77; --
constant opcPACK : integer := 78; --
constant lastOpcBit : integer := 78;
type rTG68K_opc is record
opcMOVE : bit;
opcMOVEQ : bit;
opcMOVESR : bit;
opcMOVECCR : bit;
opcADD : bit;
opcADDQ : bit;
opcOR : bit;
opcAND : bit;
opcEOR : bit;
opcCMP : bit;
opcROT : bit;
opcCPMAW : bit;
opcEXT : bit;
opcABCD : bit;
opcSBCD : bit;
opcBITS : bit;
opcSWAP : bit;
opcScc : bit;
andiSR : bit;
eoriSR : bit;
oriSR : bit;
opcMULU : bit;
opcDIVU : bit;
dispouter : bit;
rot_nop : bit;
ld_rot_cnt : bit;
writePC_add : bit;
ea_data_OP1 : bit;
ea_data_OP2 : bit;
use_XZFlag : bit;
get_bfoffset : bit;
save_memaddr : bit;
opcCHK : bit;
movec_rd : bit;
movec_wr : bit;
Regwrena : bit;
update_FC : bit;
linksp : bit;
movepl : bit;
update_ld : bit;
OP1addr : bit;
write_reg : bit;
changeMode : bit;
ea_build : bit;
trap_chk : bit;
store_ea_data : bit;
addrlong : bit;
postadd : bit;
presub : bit;
subidx : bit;
no_Flags : bit;
use_SP : bit;
to_CCR : bit;
to_SR : bit;
OP2out_one : bit;
OP1out_zero : bit;
mem_addsub : bit;
addsub : bit;
directPC : bit;
direct_delta : bit;
directSR : bit;
directCCR : bit;
exg : bit;
get_ea_now : bit;
ea_to_pc : bit;
hold_dwr : bit;
to_USP : bit;
from_USP : bit;
write_lowlong : bit;
write_reminder : bit;
movem_action : bit;
briefext : bit;
get_2ndOPC : bit;
mem_byte : bit;
longaktion : bit;
opcRESET : bit;
opcBF : bit;
opcBFwb : bit;
opcPACK : bit;
end record;
component TG68K_ALU
generic(
MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode : integer := 0 --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
);
port(
clk : in std_logic;
Reset : in std_logic;
clkena_lw : in std_logic:='1';
execOPC : in bit;
exe_condition : in std_logic;
exec_tas : in std_logic;
long_start : in bit;
non_aligned : in std_logic;
movem_presub : in bit;
set_stop : in bit;
Z_error : in bit;
rot_bits : in std_logic_vector(1 downto 0);
exec : in bit_vector(lastOpcBit downto 0);
OP1out : in std_logic_vector(31 downto 0);
OP2out : in std_logic_vector(31 downto 0);
reg_QA : in std_logic_vector(31 downto 0);
reg_QB : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(15 downto 0);
datatype : in std_logic_vector(1 downto 0);
exe_opcode : in std_logic_vector(15 downto 0);
exe_datatype : in std_logic_vector(1 downto 0);
sndOPC : in std_logic_vector(15 downto 0);
last_data_read : in std_logic_vector(15 downto 0);
data_read : in std_logic_vector(15 downto 0);
FlagsSR : in std_logic_vector(7 downto 0);
micro_state : in micro_states;
bf_ext_in : in std_logic_vector(7 downto 0);
bf_ext_out : out std_logic_vector(7 downto 0);
bf_width : in std_logic_vector(4 downto 0);
bf_loffset : in std_logic_vector(4 downto 0);
bf_offset : in std_logic_vector(31 downto 0);
set_V_Flag_out : out bit;
Flags_out : out std_logic_vector(7 downto 0);
c_out_out : out std_logic_vector(2 downto 0);
addsub_q_out : out std_logic_vector(31 downto 0);
ALUout : out std_logic_vector(31 downto 0)
);
end component;
end;
| gpl-3.0 | cf715298080f9f57632af3ee754a40cf | 0.467653 | 3.666783 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/mem_array.vhd | 1 | 2,873 |
--Copyright 2017 Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use std.textio.ALL;
entity mem_array is
GENERIC(
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 6;
INIT_FILE : string := "RAM.mif");
Port(
ADDR : in STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
DATAIN : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
clk : in std_logic;
WE : in std_logic;
OUTPUT : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0)
);
end mem_array;
architecture dataflow of mem_array is
Type MEMORY_ARRAY is ARRAY (0 to 2**(ADDR_WIDTH)-1) of STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
impure function init_memory_wfile(mif_file_name : in string) return MEMORY_ARRAY is
file mif_file : text open read_mode is mif_file_name;
variable mif_line : line;
variable temp_bv : bit_vector(DATA_WIDTH-1 downto 0);
variable temp_mem : MEMORY_ARRAY;
begin
for i in MEMORY_ARRAY'range loop
readline(mif_file, mif_line);
read(mif_line, temp_bv);
temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
signal memory : MEMORY_ARRAY;--:=(init_memory_wfile(INIT_FILE));
begin
process(clk, WE)
begin
if (clk'EVENT and clk = '1') then
if (WE = '1') then
memory(to_integer(unsigned(ADDR))) <= DATAIN;
end if;
end if;
end process;
OUTPUT <= memory(to_integer(unsigned(ADDR)));
end dataflow; | bsd-3-clause | 9275433f04e1da2f55954737aee7e114 | 0.737208 | 3.815405 | false | false | false | false |
HackLinux/ION | src/testbench/ion_core_tb.vhdl | 1 | 18,175 | --##############################################################################
-- ion_core_tb.vhdl -- Test bench for full ION core.
--
-- Simulates the full ION core, which includes TCM and caches.
--
--------------------------------------------------------------------------------
-- KNOWN BUGS AND MISSING THINGS:
--
-- WB bridge not simulated with wait states.
-- WB bridge not simulated with 8 or 16 bit accesses, only 32.
--
--------------------------------------------------------------------------------
-- SIMULATED IO DEVICES:
--
-- This TB simulates the following IO devices as support for the test SW:
--
-- Address Name Size Access Purpose
---------------------------------------------------------------------------
-- ffff8000: DbgTxD : 8 : b : Debug UART TX buffer (W/o).
-- ffff8020: DbgRW0 : 32 : w : Debug register 0 (R/W).
-- ffff8024: DbgRW1 : 32 : w : Debug register 1 (R/W).
-- ffff8018: ExitReg : 32 : w : Exit register (W/o).
--
-- (b support byte access, w support word access).
--
-- The fake UART is implemented in package ion_tb_pkg, not as a proper WB
-- register but directly on the CPU buses.
-- The exit register is another ion_tb_pkg fake-register used to terminate the
-- execution of the TB; upon writing on it, the TB will stop and a success/fail
-- message will be output (success is 0, failure anything else).
-- All other debug registers are simulated as WB registers so they can be used
-- to verify the operation of the WB bridge.
--
--------------------------------------------------------------------------------
-- SIMULATED MEMORY:
--
-- Data cache refill port
-----------------------------
-- 80000000 4KB RAM (word access only).
-- 90000000 256MB ROM (test pattern).
--
--------------------------------------------------------------------------------
-- Console logging:
--
-- Console output (at address 0xffff8000) is logged to text file
-- "hw_sim_console_log.txt".
--
-- IMPORTANT: The code that echoes UART TX data to the simulation console does
-- line buffering; it will not print anything until it gets a CR (0x0d), and
-- will ignore LFs (0x0a). Bear this in mind if you see no output when you
-- expect it.
--
-- Console logging is done by monitoring CPU writes to the UART, NOT by looking
-- at the TxD pin. It will NOT catch baud-related problems, etc.
--------------------------------------------------------------------------------
-- WARNING: Will only work on Modelsim 6.3+; uses proprietary library SignalSpy.
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Project packages.
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
-- Tst bench support packages.
use std.textio.all;
use work.txt_util.all;
use work.ION_TB_PKG.all;
-- Simulation parameters defined in the SW makefile (generated package).
use work.SIM_PARAMS_PKG.all;
-- Hardware parameters & memory contents from SW build (generated package).
use work.OBJ_CODE_PKG.all;
entity ION_CORE_TB is
end;
architecture testbench of ION_CORE_TB is
-- Simulation clock rate
constant CLOCK_RATE : integer := 50e6;
-- Simulation clock period
constant T : time := (1.0e9/real(CLOCK_RATE)) * 1 ns;
--------------------------------------------------------------------------------
-- Core interface.
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal code_wb_mosi : t_wishbone_mosi;
signal code_wb_miso : t_wishbone_miso;
signal data_wb_mosi : t_wishbone_mosi;
signal data_wb_miso : t_wishbone_miso;
signal data_uc_wb_mosi : t_wishbone_mosi;
signal data_uc_wb_miso : t_wishbone_miso;
signal cop2_mosi : t_cop2_mosi;
signal cop2_miso : t_cop2_miso;
signal irq : std_logic_vector(5 downto 0);
--------------------------------------------------------------------------------
-- Memory refill ports.
type t_natural_table is array(natural range <>) of natural;
-- Wait states simulated by data refill port (elements used in succession).
constant DATA_WS : t_natural_table (0 to 3) := (4,1,3,2);
signal data_wait_ctr : natural;
signal data_cycle_count : natural := 0;
signal data_address : t_word;
type t_ram_table is array(natural range <>) of t_word;
shared variable ram : t_ram_table(0 to 4095);
signal code_wait_ctr : natural;
signal code_cycle_count : natural := 0;
signal code_address : t_word;
--------------------------------------------------------------------------------
-- Uncached data WB bridge.
-- Wait states simulated by uncached WB port (elements used in succession).
-- FIXME wait state simulation disabled!
constant UNCACHED_WS : t_natural_table (0 to 3) := (0,0,0,0); --(4,1,3,2);
signal uwb_wait_ctr : natural;
signal uwb_cycle_count : natural := 0;
signal uwb_address : t_word;
shared variable debug_regs: t_ram_table(0 to 3);
--------------------------------------------------------------------------------
-- Logging signals & simulation control.
signal done : std_logic := '0';
-- Log file
file log_file: TEXT open write_mode is "hw_sim_log.txt";
-- Console output log file
file con_file: TEXT open write_mode is "hw_sim_console_log.txt";
-- All the info needed by the logger is here
signal log_info : t_log_info;
--------------------------------------------------------------------------------
begin
core: entity work.ION_CORE
generic map (
TCM_CODE_SIZE => CODE_MEM_SIZE,
TCM_CODE_INIT => OBJ_CODE,
TCM_DATA_SIZE => DATA_MEM_SIZE,
CODE_CACHE_LINES => 128,
DATA_CACHE_LINES => 128
)
port map (
CLK_I => clk,
RESET_I => reset,
CODE_WB_MOSI_O => code_wb_mosi,
CODE_WB_MISO_I => code_wb_miso,
DATA_WB_MOSI_O => data_wb_mosi,
DATA_WB_MISO_I => data_wb_miso,
DATA_UC_WB_MOSI_O => data_uc_wb_mosi,
DATA_UC_WB_MISO_I => data_uc_wb_miso,
COP2_MOSI_O => cop2_mosi,
COP2_MISO_I => cop2_miso,
IRQ_I => irq
);
-- Master clock: free running clock used as main module clock --------------
run_master_clock:
process(done, clk)
begin
if done = '0' then
clk <= not clk after T/2;
end if;
end process run_master_clock;
-- Main simulation process: reset MCU and wait for fixed period ------------
drive_uut:
process
variable l : line;
begin
wait for T*4;
reset <= '0';
wait for T*SIMULATION_LENGTH;
-- Flush console output to log console file (in case the end of the
-- simulation caught an unterminated line in the buffer)
if log_info.con_line_ix > 1 then
write(l, log_info.con_line_buf(1 to log_info.con_line_ix));
writeline(con_file, l);
end if;
print("TB finished");
done <= '1';
file_close(con_file);
wait;
end process drive_uut;
-- Data refill port interface ----------------------------------------------
-- Crudely simulate a WB interface with a variable number of delay cycles.
-- The number of wait cycles is taken from a table for variety's sake, this
-- model does not approach a real WB slave but should exercise the cache
-- sufficiently to flush out major bugs.
-- Note that this interface does NOT overlap successive reads nor cycles
-- with zero wait states!
-- TODO optional simulation of overlapped reads & zero waits.
data_refill_port:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
data_wait_ctr <= DATA_WS((data_cycle_count) mod DATA_WS'length);
data_wb_miso.ack <= '0';
data_wb_miso.dat <= (others => '1');
data_address <= (others => '0');
elsif data_wb_mosi.stb = '1' then
if data_wait_ctr > 0 then
-- Access in progress, decrement wait counter...
data_wait_ctr <= data_wait_ctr - 1;
data_wb_miso.ack <= '0';
data_address <= data_wb_mosi.adr;
else
-- Access finished, wait counter reached zero.
-- Prepare the wait counter for the next access...
data_wait_ctr <= DATA_WS((data_cycle_count+1) mod DATA_WS'length);
-- ...and drive the slave WB bus.
data_wb_miso.ack <= '1';
-- Termination is different for read and write accesses:
if data_wb_mosi.we = '1' then
-- Write access: do the simulated write.
-- FIXME do address decoding.
-- FIXME support byte & halfword writes.
ram(conv_integer(data_address(13 downto 2))) := data_wb_mosi.dat;
else
-- Read access: simulate read & WB slave multiplexor.
-- For simplicity´s sake, do the address decoding
-- right here and select between RAM and ROM.
if data_address(31 downto 28) = X"9" then
-- Fake data: low 16 bits of address replicated twice.
data_wb_miso.dat <= data_wb_mosi.adr(15 downto 0) &
data_wb_mosi.adr(15 downto 0);
elsif data_address(31 downto 28) = X"8" then
-- Simulated RAM.
data_wb_miso.dat <= ram(conv_integer(data_address(13 downto 2)));
else
-- Unmapped area: read zeros.
-- TODO should raise some sort of alert.
data_wb_miso.dat <= (others => '0');
end if;
end if;
end if;
else
-- No WB access is going on: restore the wait counter to its
-- idle state and deassert ACK.
data_wait_ctr <= DATA_WS((data_cycle_count) mod DATA_WS'length);
data_wb_miso.ack <= '0';
end if;
-- Keep track of how many accesses we have performed.
-- We use this to select a number of wait states from a table.
if data_wb_mosi.stb = '1' and data_wait_ctr = 0 then
data_cycle_count <= data_cycle_count + 1;
end if;
end if;
end process data_refill_port;
-- stall the WB bus as long as the wait counter is not zero.
data_wb_miso.stall <=
'1' when data_wb_mosi.stb = '1' and data_wait_ctr > 0 else
'0';
-- Code refill port interface ----------------------------------------------
-- We do the same as for the data refill port, except we don't need to
-- support write cycles here.
-- the memory we will be reading is the same as the data bus -- no need to
-- simulate any arbitration.
-- Also, there's no test pattern ROM in this bus.
code_refill_port:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
code_wait_ctr <= DATA_WS((code_cycle_count) mod DATA_WS'length);
code_wb_miso.ack <= '0';
code_wb_miso.dat <= (others => '1');
code_address <= (others => '0');
elsif code_wb_mosi.stb = '1' then
if code_wait_ctr > 0 then
-- Access in progress, decrement wait counter...
code_wait_ctr <= code_wait_ctr - 1;
code_wb_miso.ack <= '0';
code_address <= code_wb_mosi.adr;
else
-- Access finished, wait counter reached zero.
-- Prepare the wait counter for the next access...
code_wait_ctr <= DATA_WS((code_cycle_count+1) mod DATA_WS'length);
-- ...and drive the slave WB bus.
code_wb_miso.ack <= '1';
-- We will ignore write accesses on this bus.
-- (We are already asserting that there aren't any anyway.)
-- FIXME add assertion
if data_wb_mosi.we = '0' then
-- Read access: simulate read & WB slave multiplexor.
if code_address(31 downto 28) = X"8" then
-- Simulated RAM.
code_wb_miso.dat <= ram(conv_integer(code_address(13 downto 2)));
else
-- Cached, unmapped area: read zeros.
-- TODO should raise some sort of alert.
code_wb_miso.dat <= (others => '0');
end if;
end if;
end if;
else
-- No WB access is going on: restore the wait counter to its
-- idle state and deassert ACK.
code_wait_ctr <= DATA_WS((code_cycle_count) mod DATA_WS'length);
code_wb_miso.ack <= '0';
end if;
-- Keep track of how many accesses we have performed.
-- We use this to select a number of wait states from a table.
if code_wb_mosi.stb = '1' and code_wait_ctr = 0 then
code_cycle_count <= code_cycle_count + 1;
end if;
end if;
end process code_refill_port;
-- stall the WB bus as long as the wait counter is not zero.
code_wb_miso.stall <=
'1' when code_wb_mosi.stb = '1' and code_wait_ctr > 0 else
'0';
-- Uncached WB port --------------------------------------------------------
-- We only have the debug register on this WB bus so we will not bother
-- decoding the address and multiplexing the MISOs, etc.
uncached_wb_port:
process(clk)
variable debug_port : natural;
begin
if clk'event and clk='1' then
if reset = '1' then
uwb_wait_ctr <= UNCACHED_WS((uwb_cycle_count) mod UNCACHED_WS'length);
data_uc_wb_miso.ack <= '0';
data_uc_wb_miso.dat <= (others => '1');
uwb_address <= (others => '0');
elsif data_uc_wb_mosi.stb = '1' then
debug_port := conv_integer(data_uc_wb_mosi.adr(3 downto 2));
if uwb_wait_ctr > 0 then
-- Access in progress, decrement wait counter...
uwb_wait_ctr <= data_wait_ctr - 1;
data_uc_wb_miso.ack <= '0';
uwb_address <= data_wb_mosi.adr;
else
-- Access finished, wait counter reached zero.
-- Prepare the wait counter for the next access...
uwb_wait_ctr <= UNCACHED_WS((uwb_cycle_count+1) mod UNCACHED_WS'length);
-- ...and drive the slave WB bus.
data_uc_wb_miso.ack <= '1';
-- Termination is different for read and write accesses:
if data_uc_wb_mosi.we = '1' then
-- Write access: do the simulated write.
debug_regs(debug_port) := data_uc_wb_mosi.dat;
else
-- Read access: simulate read & WB slave multiplexor.
data_uc_wb_miso.dat <= debug_regs(debug_port);
end if;
end if;
else
-- No WB access is going on: restore the wait counter to its
-- idle state and deassert ACK.
uwb_wait_ctr <= UNCACHED_WS((uwb_cycle_count) mod UNCACHED_WS'length);
data_uc_wb_miso.ack <= '0';
end if;
-- Keep track of how many accesses we have performed.
-- We use this to select a number of wait states from a table.
if data_uc_wb_mosi.stb = '1' and uwb_wait_ctr = 0 then
uwb_cycle_count <= uwb_cycle_count + 1;
end if;
end if;
end process uncached_wb_port;
-- stall the WB bus as long as the wait counter is not zero.
data_uc_wb_miso.stall <=
'1' when data_uc_wb_mosi.stb = '1' and uwb_wait_ctr > 0 else
'0';
-- Dummy COP2 for interface testing ----------------------------------------
cop2: entity work.ION_COP2_STUB
port map (
CLK_I => clk,
RESET_I => reset,
CPU_MOSI_I => cop2_mosi,
CPU_MISO_O => cop2_miso
);
-- HW interrupt simulation -------------------------------------------------
-- All we do here is "feed back" into the hardware the value of a fake
-- register implemented in ion_tb_pkg.
interrupt_registers:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
irq <= (others => '0');
else
irq <= log_info.hw_irq;
end if;
end if;
end process interrupt_registers;
-- Logging process: launch logger function ---------------------------------
log_execution:
process
begin
log_cpu_activity(clk, reset, done,
"ION_CORE_TB", "core/cpu",
log_info, "log_info",
LOG_TRIGGER_ADDRESS, log_file, con_file);
wait;
end process log_execution;
end architecture testbench;
| lgpl-3.0 | f822daaa3fe2cb6c4a32d4f70df6b7ea | 0.49348 | 4.318128 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Biphase_Decomp/tb_biphase_decomp.vhd | 1 | 2,204 | ----------------------------------------------------------------------------------------------------
-- Bi-Phase Decomposition Testbench
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.biphase_decomp_pkg.all;
--This module is a test-bench for simulating the bi-phase decomposition module
entity tb_biphase_decomp is
end tb_biphase_decomp;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture sim of tb_biphase_decomp is
signal rst : std_logic;
signal clk : std_logic;
signal count_data : std_logic_vector(15 downto 0);
signal x0 : std_logic_vector(15 downto 0);
signal x1 : std_logic_vector(15 downto 0);
begin
--Instantiate clock generator
clk1 : tb_clockgen
generic map(PERIOD => 30ns,
DUTY_CYCLE => 0.50)
port map( clk => clk);
--count_process
counter: process(clk, rst)
variable counter : unsigned (15 downto 0) := (others => '0');
begin
if(rst = '1') then
counter := (others => '0');
else
if(rising_edge(clk)) then
counter := counter + 1;
end if;
end if;
count_data <= std_logic_vector(counter);
end process;
--UUT
uut : biphase_decomp
port map( clk => clk,
rst => rst,
x => count_data,
x0 => x0,
x1 => x1);
--Main Process
main: process
begin
rst <= '1';
wait for 50ns;
rst <= '0';
wait;
end process;
end sim;
| mit | 915c46568238d28fcf27c28521760ddf | 0.391561 | 4.963964 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Pulse_Gen/pulse_gen.vhd | 1 | 2,321 | --------------------------------------------------------------------------------------------------
-- Pulse Generator
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package pulse_gen_pkg is
component pulse_gen is
generic( CLKS_PER_PULSE : positive := 1);
port( clk : in std_logic;
rst : in std_logic;
pulse : out std_logic);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.count_gen_pkg.all;
entity pulse_gen is
generic( CLKS_PER_PULSE : positive := 1);
port( clk : in std_logic;
rst : in std_logic;
pulse : out std_logic);
end pulse_gen;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture rtl of pulse_gen is
constant MAX_COUNT : positive := CLKS_PER_PULSE-1;
signal count : integer;
signal end_count : std_logic;
signal rst_clock_counter : std_logic;
begin
--This counter counts the number of clocks since last pulse
--This counter resets when the count reaches CLKS_PER_PULSE
--This counter counts every clock cycle
clock_counter : count_gen
port map( clk => clk,
rst => rst_clock_counter,
en => '1',
count => count);
end_count <= '1' when count = MAX_COUNT else '0';
rst_clock_counter <= end_count or rst;
pulse <= end_count;
end rtl;
| mit | c7b0ad94fe2b78abd6759c0b9889d391 | 0.358466 | 5.592771 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/IPv4_RX.vhd | 2 | 22,407 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4_RX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP RX
-- doesnt handle reassembly
-- checks and filters for IP protocol
-- checks and filters for IP addr
-- Handle IPv4 protocol
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Improved error handling
-- Revision 0.03 - Added handling of broadcast address
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity IPv4_RX is
port (
-- IP Layer signals
ip_rx : out ipv4_rx_type;
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
-- system signals
clk : in std_logic; -- same clock used to clock mac data and ip data
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
rx_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- MAC layer RX signals
mac_data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in std_logic; -- indicates data_in valid on clock
mac_data_in_last : in std_logic -- indicates last data in frame
);
end IPv4_RX;
architecture Behavioral of IPv4_RX is
type rx_state_type is (IDLE, ETH_HDR, IP_HDR, USER_DATA, WAIT_END, ERR);
type rx_event_type is (NO_EVENT, DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_count_mode_type is (RST, INCR, SET_VAL, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- state variables
signal rx_state : rx_state_type;
signal rx_count : unsigned (15 downto 0);
signal src_ip : std_logic_vector (31 downto 0); -- src IP captured from input
signal dst_ip : std_logic_vector (23 downto 0); -- 1st 3 bytes of dst IP captured from input
signal is_broadcast_reg : std_logic;
signal protocol : std_logic_vector (7 downto 0); -- src protocol captured from input
signal data_len : std_logic_vector (15 downto 0); -- src data length captured from input
signal ip_rx_start_reg : std_logic; -- indicates start of user data
signal hdr_valid_reg : std_logic; -- indicates that hdr data is valid
signal frame_err_cnt : unsigned (7 downto 0); -- number of frame errors
signal error_code_reg : std_logic_vector (3 downto 0);
signal rx_pkt_counter : unsigned (7 downto 0); -- number of rx frames received for us
-- rx control signals
signal next_rx_state : rx_state_type;
signal set_rx_state : std_logic;
signal rx_event : rx_event_type;
signal rx_count_mode : settable_count_mode_type;
signal set_dst_ip3 : std_logic;
signal set_dst_ip2 : std_logic;
signal set_dst_ip1 : std_logic;
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
signal set_protocol : std_logic;
signal set_len_H : std_logic;
signal set_len_L : std_logic;
signal set_ip_rx_start : set_clr_type;
signal set_hdr_valid : set_clr_type;
signal set_frame_err_cnt : count_mode_type;
signal dataval : std_logic_vector (7 downto 0);
signal rx_count_val : unsigned (15 downto 0);
signal set_error_code : std_logic;
signal error_code_val : std_logic_vector (3 downto 0);
signal set_pkt_cnt : count_mode_type;
signal set_data_last : std_logic;
signal dst_ip_rx : std_logic_vector (31 downto 0);
signal set_is_broadcast : set_clr_type;
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | Version | *Header | Service Type | Total Length including header |
-- | (4) | Length | (ignored) | (in bytes) |
-- --------------------------------------------------------------------------------------------
-- | Identification | Flags | Fragment Offset |
-- | | | (in 32 bit words) |
-- --------------------------------------------------------------------------------------------
-- | Time To Live | Protocol | Header Checksum |
-- | (ignored) | | |
-- --------------------------------------------------------------------------------------------
-- | Source IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Destination IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Options (if any - ignored) | Padding |
-- | | (if needed) |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
--
-- * - in 32 bit words
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
rx_combinatorial : process (
-- input signals
mac_data_in, mac_data_in_valid, mac_data_in_last, our_ip_address,
-- state variables
rx_state, rx_count, src_ip, dst_ip, protocol, data_len, ip_rx_start_reg, hdr_valid_reg,
frame_err_cnt, error_code_reg, rx_pkt_counter, is_broadcast_reg,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode,
set_ip3, set_ip2, set_ip1, set_ip0, set_protocol, set_len_H, set_len_L,
set_dst_ip3, set_dst_ip2, set_dst_ip1,
set_ip_rx_start, set_hdr_valid, set_frame_err_cnt, dataval, rx_count_val,
set_error_code, error_code_val, set_pkt_cnt, set_data_last, dst_ip_rx, set_is_broadcast
)
begin
-- set output followers
ip_rx_start <= ip_rx_start_reg;
ip_rx.hdr.is_valid <= hdr_valid_reg;
ip_rx.hdr.protocol <= protocol;
ip_rx.hdr.data_length <= data_len;
ip_rx.hdr.src_ip_addr <= src_ip;
ip_rx.hdr.num_frame_errors <= std_logic_vector(frame_err_cnt);
ip_rx.hdr.last_error_code <= error_code_reg;
ip_rx.hdr.is_broadcast <= is_broadcast_reg;
rx_pkt_count <= std_logic_vector(rx_pkt_counter);
-- transfer data upstream if in user data phase
if rx_state = USER_DATA then
ip_rx.data.data_in <= mac_data_in;
ip_rx.data.data_in_valid <= mac_data_in_valid;
ip_rx.data.data_in_last <= set_data_last;
else
ip_rx.data.data_in <= (others => '0');
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
end if;
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_ip3 <= '0';
set_ip2 <= '0';
set_ip1 <= '0';
set_ip0 <= '0';
set_dst_ip3 <= '0';
set_dst_ip2 <= '0';
set_dst_ip1 <= '0';
set_protocol <= '0';
set_len_H <= '0';
set_len_L <= '0';
set_ip_rx_start <= HOLD;
set_hdr_valid <= HOLD;
set_frame_err_cnt <= HOLD;
rx_count_val <= x"0000";
set_error_code <= '0';
error_code_val <= RX_EC_NONE;
set_pkt_cnt <= HOLD;
dataval <= (others => '0');
set_data_last <= '0';
dst_ip_rx <= (others => '0');
set_is_broadcast <= HOLD;
-- determine event (if any)
if mac_data_in_valid = '1' then
rx_event <= DATA;
dataval <= mac_data_in;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
rx_count_mode <= INCR;
set_hdr_valid <= CLR;
next_rx_state <= ETH_HDR;
set_rx_state <= '1';
end case;
when ETH_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if rx_count = x"000d" then
rx_count_mode <= RST;
next_rx_state <= IP_HDR;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_ETH;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
set_data_last <= '1';
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
else
case rx_count is
when x"000c" =>
if mac_data_in /= x"08" then -- ignore pkts that are not type=IP
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"000d" =>
if mac_data_in /= x"00" then -- ignore pkts that are not type=IP
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when others => -- ignore other bytes in eth header
end case;
end if;
end case;
when IP_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if rx_count = x"0013" then
rx_count_val <= x"0001"; -- start counter at 1
rx_count_mode <= SET_VAL;
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_IP;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
set_data_last <= '1';
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
else
case rx_count is
when x"0000" =>
if mac_data_in /= x"45" then -- ignore pkts that are not v4 with 5 header words
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0002" => set_len_H <= '1';
when x"0003" => set_len_L <= '1';
when x"0006" =>
if (mac_data_in(7) = '1') or (mac_data_in (4 downto 0) /= "00000") then
-- ignore pkts that require reassembly (MF=1 or frag offst /= 0)
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0007" =>
if mac_data_in /= x"00" then -- ignore pkts that require reassembly (frag offst /= 0)
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0009" => set_protocol <= '1';
when x"000c" => set_ip3 <= '1';
when x"000d" => set_ip2 <= '1';
when x"000e" => set_ip1 <= '1';
when x"000f" => set_ip0 <= '1';
when x"0010" => set_dst_ip3 <= '1';
if ((mac_data_in /= our_ip_address(31 downto 24)) and
(mac_data_in /= IP_BC_ADDR(31 downto 24)))then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0011" => set_dst_ip2 <= '1';
if ((mac_data_in /= our_ip_address(23 downto 16)) and
(mac_data_in /= IP_BC_ADDR(23 downto 16)))then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0012" => set_dst_ip1 <= '1';
if ((mac_data_in /= our_ip_address(15 downto 8)) and
(mac_data_in /= IP_BC_ADDR(15 downto 8)))then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0013" =>
if ((mac_data_in /= our_ip_address(7 downto 0)) and
(mac_data_in /= IP_BC_ADDR(7 downto 0)))then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
else
next_rx_state <= USER_DATA;
set_pkt_cnt <= INCR; -- count another pkt
set_rx_state <= '1';
set_ip_rx_start <= SET;
end if;
-- now have the dst IP addr
dst_ip_rx <= dst_ip & mac_data_in;
if dst_ip_rx = IP_BC_ADDR then
set_is_broadcast <= SET;
else
set_is_broadcast <= CLR;
end if;
set_hdr_valid <= SET; -- header values are now valid, although the pkt may not be for us
--if dst_ip_rx = our_ip_address or dst_ip_rx = IP_BC_ADDR then
-- next_rx_state <= USER_DATA;
-- set_pkt_cnt <= INCR; -- count another pkt received
-- set_rx_state <= '1';
-- set_ip_rx_start <= SET;
--else
-- next_rx_state <= WAIT_END;
-- set_rx_state <= '1';
--end if;
when others => -- ignore other bytes in ip header
end case;
end if;
end case;
when USER_DATA =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
-- note: data gets transfered upstream as part of "output followers" processing
if rx_count = unsigned(data_len) then
set_ip_rx_start <= CLR;
rx_count_mode <= RST;
set_data_last <= '1';
if mac_data_in_last = '1' then
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_ip_rx_start <= CLR;
else
next_rx_state <= WAIT_END;
end if;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
-- check for early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_USER;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
end if;
end if;
end case;
when ERR =>
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
if mac_data_in_last = '0' then
set_data_last <= '1';
next_rx_state <= WAIT_END;
set_rx_state <= '1';
else
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
end if;
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if mac_data_in_last = '1' then
set_data_last <= '1';
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
set_ip_rx_start <= CLR;
end if;
end case;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
rx_sequential : process (clk)--, reset)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"0000";
src_ip <= (others => '0');
dst_ip <= (others => '0');
protocol <= (others => '0');
data_len <= (others => '0');
ip_rx_start_reg <= '0';
hdr_valid_reg <= '0';
is_broadcast_reg <= '0';
frame_err_cnt <= (others => '0');
error_code_reg <= RX_EC_NONE;
rx_pkt_counter <= x"00";
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST => rx_count <= x"0000";
when INCR => rx_count <= rx_count + 1;
when SET_VAL => rx_count <= rx_count_val;
when HOLD => rx_count <= rx_count;
end case;
-- frame error count processing
case set_frame_err_cnt is
when RST => frame_err_cnt <= x"00";
when INCR => frame_err_cnt <= frame_err_cnt + 1;
when HOLD => frame_err_cnt <= frame_err_cnt;
end case;
-- ip pkt processing
case set_pkt_cnt is
when RST => rx_pkt_counter <= x"00";
when INCR => rx_pkt_counter <= rx_pkt_counter + 1;
when HOLD => rx_pkt_counter <= rx_pkt_counter;
end case;
-- source ip capture
if (set_ip3 = '1') then src_ip(31 downto 24) <= dataval; end if;
if (set_ip2 = '1') then src_ip(23 downto 16) <= dataval; end if;
if (set_ip1 = '1') then src_ip(15 downto 8) <= dataval; end if;
if (set_ip0 = '1') then src_ip(7 downto 0) <= dataval; end if;
-- dst ip capture
if (set_dst_ip3 = '1') then dst_ip(23 downto 16) <= dataval; end if;
if (set_dst_ip2 = '1') then dst_ip(15 downto 8) <= dataval; end if;
if (set_dst_ip1 = '1') then dst_ip(7 downto 0) <= dataval; end if;
if (set_protocol = '1') then
protocol <= dataval;
else
protocol <= protocol;
end if;
if (set_len_H = '1') then
data_len (15 downto 8) <= dataval;
data_len (7 downto 0) <= x"00";
elsif (set_len_L = '1') then
-- compute data length, taking into account that we need to subtract the header length
data_len <= std_logic_vector(unsigned(data_len(15 downto 8) & dataval) - 20);
else
data_len <= data_len;
end if;
case set_ip_rx_start is
when SET => ip_rx_start_reg <= '1';
when CLR => ip_rx_start_reg <= '0';
when HOLD => ip_rx_start_reg <= ip_rx_start_reg;
end case;
case set_is_broadcast is
when SET => is_broadcast_reg <= '1';
when CLR => is_broadcast_reg <= '0';
when HOLD => is_broadcast_reg <= is_broadcast_reg;
end case;
case set_hdr_valid is
when SET => hdr_valid_reg <= '1';
when CLR => hdr_valid_reg <= '0';
when HOLD => hdr_valid_reg <= hdr_valid_reg;
end case;
-- set error code
if set_error_code = '1' then
error_code_reg <= error_code_val;
else
error_code_reg <= error_code_reg;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | daebfdbb342cd2a0075242dd5e920929 | 0.413442 | 4.046776 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/SCDataMANAGER.vhd | 4 | 5,210 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: SCDataMANAGER - Sub-Chunk Data Manager
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE,work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
--! sub-chunk data manager,
--! inserts sub-chunk trailer at the end of the chunk/block
entity SCDataMANAGER is
Port (
CLK : in std_logic;
rst : in std_logic;
xoff : in std_logic;
maxCLEN : in std_logic_vector (2 downto 0); -- (15 downto 0);
rstCLENcount : in std_logic;
truncateCdata : out std_logic; -- maximum allowed chunk length is reached of xoff received - truncation mark
-------------
trailerMOD : in std_logic_vector (1 downto 0); -- keeps its value till the next DIN_RDY_s
trailerTYPE : in std_logic_vector (2 downto 0); -- keeps its value till the next DIN_RDY_s
trailerRSRVbit : in std_logic; --
-------------
trailerSENDtrig : in std_logic;
dataCNTena : in std_logic; -- counts only data (or 'flush' padding), no header, no trailer
-------------
trailerOUT : out std_logic_vector (15 downto 0);
trailerOUTrdy : out std_logic
);
end SCDataMANAGER;
architecture Behavioral of SCDataMANAGER is
----
signal truncate_state, sc_counter_rst, first_byte_count_rst : std_logic := '0';
signal truncate_data_flag, rst_fall, rstCLENcount_s, trailerSENDtrig_next_clk : std_logic;
signal sc_data_count : std_logic_vector(9 downto 0) := (others => '0');
signal schunk_length : std_logic_vector(9 downto 0);
signal chunk_data_count : std_logic_vector(11 downto 0);
signal trailer_s : std_logic_vector(15 downto 0);
constant zero_data_trailer : std_logic_vector(15 downto 0) := "0000000000000000"; -- "000"=null chunk, "00"=no truncation & no cerr, '0', 10 bit length is zero;
----
begin
rst_fall_pulse: entity work.pulse_fall_pw01 PORT MAP(CLK, rst, rst_fall);
-----------------------------------------------------------------
-- chunk data counter,
-- counts to MAX_COUNT then rises MAX_REACHED
-- used for chunk data truncation
-----------------------------------------------------------------
rstCLENcount_s <= rstCLENcount or rst_fall;
--
CD_COUNTER_inst: entity work.CD_COUNTER
PORT MAP(
CLK => CLK,
RESET => rstCLENcount_s,
xoff => xoff,
COUNT_ENA => dataCNTena,
MAX_COUNT => maxCLEN,
count_out => chunk_data_count, -- the whole chunk data counter, used for data truncation
truncate_data => truncate_data_flag
);
--
truncate_state_latch: process(rstCLENcount, CLK)
begin
if rstCLENcount = '1' then
truncate_state <= '0';
elsif CLK'event and CLK = '1' then
if truncate_data_flag = '1' and trailerSENDtrig = '1' then -- first trigger goes through
truncate_state <= '1';
end if;
end if;
end process;
--
truncateCdata <= truncate_data_flag;
--
-----------------------------------------------------------------
-- trailer: in case of zero data (last word of a block is left)
-----------------------------------------------------------------
zero_data_case: entity work.pulse_pdxx_pwxx generic map(pd=>1,pw=>2) PORT MAP(CLK, trailerSENDtrig, trailerSENDtrig_next_clk);
--process(CLK)
--begin
-- if CLK'event and CLK = '1' then
-- trailerSENDtrig_next_clk <= trailerSENDtrig;
-- end if;
--end process;
--
-----------------------------------------------------------------
-- Sub-Chunk Trailer bits
-----------------------------------------------------------------
schunk_length <= sc_data_count; -- chunk_data_count(9 downto 0); --
trailer_s <= trailerTYPE & trailerMOD & trailerRSRVbit & schunk_length;
--
process(trailerSENDtrig_next_clk, trailer_s)
begin
if trailerSENDtrig_next_clk = '1' then
trailerOUT <= zero_data_trailer; -- in case the only a space for a single 16-bit word is left, null-chunk is sent (ignored by software)
else
trailerOUT <= trailer_s;
end if;
end process;
--
trailerOUTrdy <= trailerSENDtrig and (not truncate_state); -- same clock!
-----------------------------------------------------------------
-- sub-chunk data counter
-----------------------------------------------------------------
sc_counter_rst <= rst_fall or rstCLENcount;
--
sub_chunk_counter: process(CLK)
begin
if CLK'event and CLK = '1' then
if sc_counter_rst = '1' or (dataCNTena = '0' and trailerSENDtrig = '1') then
sc_data_count <= (others => '0');
else
if dataCNTena = '1' then --and first_byte_count_rst = '0' then
if trailerSENDtrig = '1' then
sc_data_count <= "0000000001";
else
sc_data_count <= sc_data_count + 1;
end if;
end if;
end if;
end if;
end process;
--
end Behavioral;
| gpl-3.0 | 2545e7de282c22c0905926881f86f5ed | 0.534165 | 3.873606 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/elinkInterface_top.vhd | 1 | 8,085 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 17/08/2015
--! Module Name: FIFO2Elink
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
--! Use standard library
library work, ieee, std;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.all;
use work.centralRouter_package.all;
use work.elinkInterface_package.all;
use ieee.std_logic_textio.all;
use std.textio.all;
--! consists of 1 E-path
entity elinkInterface_top is
port (
clk_200_in_n : in std_logic;
clk_200_in_p : in std_logic;
sys_reset_n : in std_logic;
rst_sw : in std_logic;
locked : out std_logic;
clk40_out : out std_logic;
rst_state : out std_logic;
------
emu_ena : in std_logic;
--
edata_clk : out std_logic;
edata : out std_logic_vector (15 downto 0);
edata_rdy : out std_logic
------
);
end elinkInterface_top;
architecture Behavioral of elinkInterface_top is
----------------------------------
----------------------------------
component CR_CLKs
port
(-- Clock in ports
clk200_in_p : in std_logic;
clk200_in_n : in std_logic;
-- Clock out ports
clk40 : out std_logic;
clk80 : out std_logic;
clk160 : out std_logic;
clk320 : out std_logic;
clk240 : out std_logic;
-- Status and control signals
resetn : in std_logic;
locked : out std_logic
);
end component;
ATTRIBUTE SYN_BLACK_BOX : BOOLEAN;
ATTRIBUTE SYN_BLACK_BOX OF CR_CLKs : COMPONENT IS TRUE;
ATTRIBUTE BLACK_BOX_PAD_PIN : STRING;
ATTRIBUTE BLACK_BOX_PAD_PIN OF CR_CLKs : COMPONENT IS "clk200_in_p,clk200_in_n,clk40,clk80,clk160,clk320,resetn,locked";
----------------------------------
----------------------------------
constant block_size : std_logic_vector(8 downto 0) := (others=>'1'); -- block is 1Kbyte
signal block_word_count : std_logic_vector(8 downto 0) := (others=>'0');
signal packet_counter : std_logic_vector(7 downto 0) := (others=>'0');
signal count : std_logic_vector(7 downto 0) := (others=>'0');
signal packet_data : std_logic_vector(15 downto 0);
signal clk40, clk80, clk160, clk320, clk240 : std_logic;
signal startup_case : std_logic := '1';
signal efifoRe,send_sop,edata_rdy_r : std_logic := '0';
signal rst,fifo_flush,data_on_elink,efifoWe,efifoPfull,efifoHF,send_eop,emu_ena_s,block_done : std_logic;
signal efifoDin : std_logic_vector(17 downto 0) := (others=>'0');
signal efifoDout : std_logic_vector(15 downto 0);
begin
--------------------------------------------------------------------
-- clocks
--------------------------------------------------------------------
clk0: CR_CLKs
port map (
-- Clock in ports
clk200_in_p => clk_200_in_p,
clk200_in_n => clk_200_in_n,
-- Clock out ports
clk40 => clk40,
clk80 => clk80,
clk160 => clk160,
clk320 => clk320,
clk240 => clk240,
-- Status and control signals
resetn => sys_reset_n,
locked => locked
);
--
clk40_out <= clk40;
--
--------------------------------------------------------------------
-- reset and fifo flush sequence
--------------------------------------------------------------------
rst0: entity work.CRresetManager
port map (
clk40 => clk40,
rst_soft => rst_sw,
cr_rst => rst,
cr_fifo_flush => fifo_flush
);
--
rst_state <= rst;
--
--------------------------------------------------------------------
-- user data source: counter @ clk160
--------------------------------------------------------------------
send_eop <= '1' when (count = packet_size) else '0';
--
process(clk160)
begin
if rising_edge(clk160) then
send_sop <= send_eop; -- nex clock after eop is sent
if emu_ena = '1' then
startup_case <= '0';
end if;
if send_eop = '1' then
packet_counter <= packet_counter + 1;
end if;
end if;
end process;
--
emu_ena_s <= emu_ena and not (send_eop or send_sop or startup_case);
--
process(clk160)
begin
if rising_edge(clk160) then
if efifoPfull = '0' then -- only when not full
if emu_ena_s = '1' then -- when data emulator is enabled in simulation module
count <= count + 1;
else
count <= (others=>'0');
end if;
end if;
end if;
end process;
--
process(clk160)
begin
if rising_edge(clk160) then
if efifoPfull = '1' or emu_ena = '0' then
efifoWe <= '0';
efifoDin <= "11" & x"0000";
else
efifoWe <= '1';
if send_sop = '1' or startup_case = '1' then
efifoDin <= "10" & x"0000";
elsif send_eop = '1' then
efifoDin <= "01" & x"0000";
else
efifoDin <= "00" & packet_data;
end if;
end if;
end if;
end process;
--
--packet_data <= packet_counter & count;
--packet_data <= "11111111" & count;
--packet_data <= (others=>'1');
--packet_data <= x"fc" & x"fd";
--packet_data <= x"7e" & x"f" & count(3 downto 0);
packet_data <= x"fe" & x"f" & count(3 downto 0);
--
--------------------------------------------------------------------
-- elink transmitter
--------------------------------------------------------------------
elink_tx: entity work.FIFO2Elink
generic map (
OutputDataRate => elinkRate,
elinkEncoding => elinkEncoding
)
port map (
clk40 => clk40,
clk80 => clk80,
clk160 => clk160,
rst => rst,
fifo_flush => fifo_flush,
------
efifoDin => efifoDin, -- [data_code,2bit][data,16bit]
efifoWe => efifoWe,
efifoPfull => efifoPfull,
efifoWclk => clk160,
------
DATA1bitOUT => data_on_elink
------
);
--------------------------------------------------------------------
-- elink receiver
--------------------------------------------------------------------
elink_rx: entity work.Elink2FIFO
generic map (
InputDataRate => elinkRate,
elinkEncoding => elinkEncoding
)
port map (
clk40 => clk40,
clk80 => clk80,
clk160 => clk160,
rst => rst,
fifo_flush => fifo_flush,
------
DATA1bitIN => data_on_elink,
------
efifoRclk => clk160,
efifoRe => efifoRe,
efifoHF => efifoHF, -- half-full flag: 1 KByte block is ready to be read
efifoDout => efifoDout
------
);
--------------------------------------------------------------------
-- user data acquisition
--------------------------------------------------------------------
block_re_latch: process(clk160)
begin
if rising_edge(clk160) then
if block_done = '1' or rst = '1' then
efifoRe <= '0';
elsif efifoHF = '1' then -- one 1Kbyte block is ready
efifoRe <= '1';
end if;
end if;
end process;
--
block_done <= '1' when (block_word_count = block_size) else '0';
--
block_word_counter: process(clk160)
begin
if rising_edge(clk160) then
if efifoRe = '1' and block_done = '0' then
block_word_count <= block_word_count + 1;
else
block_word_count <= (others=>'0');
end if;
end if;
end process;
--
edata_rdy0: process(clk160)
begin
if rising_edge(clk160) then
edata_rdy_r <= efifoRe;
end if;
end process;
--
edata_clk <= clk160;
edata_rdy <= edata_rdy_r;
edata <= efifoDout;
--
end Behavioral;
| gpl-3.0 | 23023a1bfc6a0c09006c22193bbbc077 | 0.466543 | 3.746525 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN16_ALIGN_BLOCK.vhd | 2 | 4,451 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/27/2014
--! Module Name: EPROC_IN16_ALIGN_BLOCK
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
use work.centralRouter_package.all;
--! continuously aligns 16bit bit-stream to a comma
entity EPROC_IN16_ALIGN_BLOCK is
port (
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
bytes : in word10b_8array_type;
bytes_rdy : in std_logic;
------------
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
------------
busyOut : out std_logic
);
end EPROC_IN16_ALIGN_BLOCK;
architecture Behavioral of EPROC_IN16_ALIGN_BLOCK is
signal bytes_r : word10b_8array_type := ((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0'),(others=>'0'),(others=>'0'),(others=>'0'),(others=>'0'));
signal send_state : std_logic := '0';
signal dataOUT_s : std_logic_vector(9 downto 0) := (others => '0');
signal dataOUTrdy_s, bytes_rdy_r : std_logic := '0';
signal byte_count : std_logic_vector(2 downto 0) := "000";
begin
-------------------------------------------------------------------------------------------
-- clock1
-- input register
-------------------------------------------------------------------------------------------
process(bitCLKx2, rst)
begin
if rst = '1' then
bytes_rdy_r <= '0';
elsif rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
bytes_rdy_r <= not bytes_rdy_r;
else
bytes_rdy_r <= '0';
end if;
end if;
end process;
--
input_latch: process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
bytes_r <= bytes;
end if;
end if;
end process;
--
process(bitCLKx2, rst)
begin
if rst = '1' then
send_state <= '0';
elsif rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
send_state <= '1';
else
if byte_count = "111" then
send_state <= '0';
end if;
end if;
end if;
end process;
--
process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if send_state = '1' then
byte_count <= byte_count + 1;
else
byte_count <= "000";
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- clock2
--
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if rising_edge(bitCLKx4) then
if send_state = '1' then
dataOUTrdy_s <= not dataOUTrdy_s;
else
dataOUTrdy_s <= '0';
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------------
out_select_proc: process(byte_count, bytes_r)
begin
case (byte_count) is
when "000" => dataOUT_s <= bytes_r(0);
when "001" => dataOUT_s <= bytes_r(1);
when "010" => dataOUT_s <= bytes_r(2);
when "011" => dataOUT_s <= bytes_r(3);
when "100" => dataOUT_s <= bytes_r(4);
when "101" => dataOUT_s <= bytes_r(5);
when "110" => dataOUT_s <= bytes_r(6);
when "111" => dataOUT_s <= bytes_r(7);
when others =>
end case;
end process;
--
-------------------------------------------------------------------------------------------
-- dataOUT_s (@bitCLKx4) & dataOUTrdy_s (@bitCLKx4, 2nd clock) can be used when
-- decoder is moved up
-------------------------------------------------------------------------------------------
dec_8b10: entity work.dec_8b10_wrap
port map(
RESET => rst,
RBYTECLK => bitCLKx4,
ABCDEIFGHJ_IN => dataOUT_s,
HGFEDCBA => dataOUT(7 downto 0),
ISK => dataOUT(9 downto 8),
BUSY => busyOut
);
--
dataOUTrdy <= dataOUTrdy_s;
--
end Behavioral;
| gpl-3.0 | c7f0f1b5916e80907457ea4e2030421a | 0.424624 | 3.952931 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/readout/l0_deserializer_decoder.vhd | 1 | 12,667 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 20.04.2017 11:46:44
-- Design Name: Level-0 Deserializer/Decoder
-- Module Name: l0_deserializer_decoder - RTL
-- Project Name: NTUA-BNL VMM3 Readout Firmware
-- Target Devices: Xilinx xc7a200t-2fbg484
-- Tool Versions: Vivado 2016.4
-- Description: Implementation of data0/data1 sampling and deserialization, comma
-- character recognition, and 8b/10b decoding.
--
-- Dependencies:
--
-- Changelog:
-- 30.04.2017: Changed the way wr_en is asserted to comply with the halved wr_clk
-- of the vmm level-0 data buffer. (Christos Bakalis)
-- 20.06.2017: Removed pipeline. (Christos Bakalis)
-- 29.06.2017: Swapped clk_des with IDDR to ease timing closure. (Christos Bakalis)
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
use work.StdRtlPkg.all;
use work.Code8b10bPkg.all;
use UNISIM.VComponents.all;
entity l0_deserializer_decoder is
Port(
------------------------------------
------- General Interface ----------
clk_ckdt : in std_logic; -- will be forwarded to the VMM
level_0 : in std_logic; -- level-0 signal
------------------------------------
-------- Buffer Interface ----------
inhib_wr : in std_logic;
dout_dec : out std_logic_vector(7 downto 0);
commas_true : out std_logic;
wr_en : out std_logic;
------------------------------------
---------- VMM Interface -----------
vmm_data0 : in std_logic;
vmm_data1 : in std_logic
);
end l0_deserializer_decoder;
architecture RTL of l0_deserializer_decoder is
component Decoder8b10b
generic (
TPD_G : time := 1 ns;
NUM_BYTES_G : positive := 2;
RST_POLARITY_G : sl := '1';
RST_ASYNC_G : boolean := false);
port(
clk : in sl;
clkEn : in sl := '1';
rst : in sl;
dataIn : in slv(NUM_BYTES_G*10-1 downto 0);
dataOut : out slv(NUM_BYTES_G*8-1 downto 0);
dataKOut : out slv(NUM_BYTES_G-1 downto 0);
codeErr : out slv(NUM_BYTES_G-1 downto 0);
dispErr : out slv(NUM_BYTES_G-1 downto 0)
);
end component;
-- deserializing IDDR and Shift Register
signal ddr_sreg : std_logic_vector(11 downto 0) := (others => '0');
signal data0_pos : std_logic := '0';
signal data0_neg : std_logic := '0';
signal data1_pos : std_logic := '0';
signal data1_neg : std_logic := '0';
signal ddr_buff : std_logic_vector(3 downto 0) := (others => '0');
-- alignment logic
constant comma_p : std_logic_vector(9 downto 0) := "0101111100";
constant comma_n : std_logic_vector(9 downto 0) := "1010000011";
type word10b_2array_type is array (0 to 2) of std_logic_vector(9 downto 0); -- 2 words of 10bit
signal word10b_align_array, word10b_align_array_r : word10b_2array_type;
signal comma_valid_bits_p : std_logic_vector(2 downto 0) := (others => '0');
signal comma_valid_bits_n : std_logic_vector(2 downto 0) := (others => '0');
signal comma_valid_p : std_logic := '0';
signal comma_valid_n : std_logic := '0';
signal align_sreg_p : std_logic_vector(4 downto 0) := (others => '0');
signal align_sreg_n : std_logic_vector(4 downto 0) := (others => '0');
-- word selection logic and decoder
signal pos_p : std_logic_vector(2 downto 0) := (others => '0');
signal pos_n : std_logic_vector(2 downto 0) := (others => '0');
signal align_select : std_logic_vector(2 downto 0) := (others => '0');
signal word10b_rdy : std_logic := '0';
signal align_sel_p : std_logic := '0';
signal align_sel_n : std_logic := '0';
signal dec_en : std_logic := '0';
signal L0_8B_data : std_logic_vector(7 downto 0) := (others => '0');
signal L0_8B_data_i : std_logic_vector(7 downto 0) := (others => '0');
signal L0_8B_K : std_logic_vector(0 downto 0) := (others => '0');
signal din_dec : std_logic_vector(9 downto 0) := (others => '0');
-- comma counter
signal cnt_commas : unsigned(4 downto 0) := (others => '0');
constant cnt_thr : unsigned(4 downto 0) := "11111"; -- 6 consecutive commas
begin
------------------------------------------
-------- DDR and Shift Register ----------
------------------------------------------
IDDR_inst_data0: IDDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'
INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'
SRTYPE => "SYNC") -- Set/Reset type: "SYNC" or "ASYNC"
port map (
Q1 => data0_pos, -- 1-bit output for positive edge of clock
Q2 => data0_neg, -- 1-bit output for negative edge of clock
C => clk_ckdt, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D => vmm_data0, -- 1-bit DDR data input
R => '0', -- 1-bit reset
S => '0' -- 1-bit set
);
IDDR_inst_data1: IDDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'
INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'
SRTYPE => "SYNC") -- Set/Reset type: "SYNC" or "ASYNC"
port map (
Q1 => data1_pos, -- 1-bit output for positive edge of clock
Q2 => data1_neg, -- 1-bit output for negative edge of clock
C => clk_ckdt, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D => vmm_data1, -- 1-bit DDR data input
R => '0', -- 1-bit reset
S => '0' -- 1-bit set
);
sreg_proc: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
ddr_buff(3) <= data0_pos;
ddr_buff(2) <= data1_pos;
ddr_buff(1) <= data0_neg;
ddr_buff(0) <= data1_neg;
ddr_sreg <= ddr_buff & ddr_sreg(11 downto 4);
end if;
end process;
------------------------------------------
------------------------------------------
-------- Alignment Logic -----------------
------------------------------------------
--- 10 bit array
input_map: for I in 0 to 2 generate -- 1 10bit-word per alignment, 2 possible alignments
word10b_align_array(I) <= ddr_sreg(I+9)&ddr_sreg(I+8)&ddr_sreg(I+7)&ddr_sreg(I+6)&ddr_sreg(I+5)&
ddr_sreg(I+4)&ddr_sreg(I+3)&ddr_sreg(I+2)&ddr_sreg(I+1)&ddr_sreg(I+0); -- 10 bit word, alligned to bit I
end generate input_map;
comma_test_p: for I in 0 to 2 generate -- 1 10bit-word per alignment, comma is valid if two first words have comma...
comma_valid_bits_p(I) <= '1' when (word10b_align_array(I) = comma_p) else '0';
end generate comma_test_p;
comma_test_n: for I in 0 to 2 generate -- 1 10bit-word per alignment, comma is valid if two first words have comma...
comma_valid_bits_n(I) <= '1' when (word10b_align_array(I) = comma_n) else '0';
end generate comma_test_n;
comma_valid_p <= comma_valid_bits_p(2) or comma_valid_bits_p(1) or comma_valid_bits_p(0);
comma_valid_n <= comma_valid_bits_n(2) or comma_valid_bits_n(1) or comma_valid_bits_n(0);
-- alignment shift register for Comma_P
align_sreg_p_proc: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
if comma_valid_p = '1' then
align_sreg_p <= "10000";
else
align_sreg_p <= align_sreg_p(0) & align_sreg_p(4 downto 1);
end if;
end if;
end process;
-- alignment shift register for Comma_N
align_sreg_n_proc: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
if comma_valid_n = '1' then
align_sreg_n <= "10000";
else
align_sreg_n <= align_sreg_n(0) & align_sreg_n(4 downto 1);
end if;
end if;
end process;
------------------------------------------
------------------------------------------
---- Word Selection Logic and Decoder ----
------------------------------------------
-- latch the 10-bit word array position while receiving commas
latch_pos: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
if(comma_valid_p = '1')then
pos_p <= comma_valid_bits_p;
else null;
end if;
if(comma_valid_n = '1')then
pos_n <= comma_valid_bits_n;
else null;
end if;
end if;
end process;
-- select the correct 10-bit word from the array
sel_fromArray: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
if(align_sel_p = '1')then
align_select <= pos_p;
elsif(align_sel_n = '1')then
align_select <= pos_n;
end if;
end if;
end process;
-- register the 10-bit word
input_reg1: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
word10b_align_array_r <= word10b_align_array;
end if;
end process;
-- final register stage before the decoder + word selection
reg_final: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
dec_en <= word10b_rdy;
case align_select is
when "001" => -- bit0 word got comma => align to bit0
din_dec <= word10b_align_array_r(0);
when "010" => -- bit1 word got comma => align to bit1
din_dec <= word10b_align_array_r(1);
when "100" => -- bit1 word got comma => align to bit1
din_dec <= word10b_align_array_r(2);
when others =>
end case;
end if;
end process;
Decoder8b10b_inst: Decoder8b10b
generic map (
TPD_G => 1 ns,
NUM_BYTES_G => 1,
RST_POLARITY_G => '1',
RST_ASYNC_G => false)
port map(
clk => clk_ckdt,
clkEn => dec_en,
rst => '0',
dataIn => din_dec,
dataOut => L0_8B_data,
dataKOut => L0_8B_K,
codeErr => open,
dispErr => open
);
------------------------------------------
------------------------------------------
----------- Misc Processes ---------------
------------------------------------------
-- process that counts commas
cnt_commas_proc: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
if(L0_8B_data_i /= x"BC")then
cnt_commas <= (others => '0');
commas_true <= '0';
else
if(cnt_commas = cnt_thr)then
commas_true <= '1';
else
commas_true <= '0';
cnt_commas <= cnt_commas + 1;
end if;
end if;
end if;
end process;
-- process that scans for non-comma characters and asserts the FIFO wr_en
wr_ena_proc: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
if(inhib_wr = '0' and dec_en = '1' and L0_8B_data /= x"BC")then
wr_en <= '1';
else
wr_en <= '0';
end if;
L0_8B_data_i <= L0_8B_data;
end if;
end process;
------------------------------------------
word10b_rdy <= align_sreg_p(4) or align_sreg_n(4);
align_sel_p <= align_sreg_p(0);
align_sel_n <= align_sreg_n(0);
dout_dec <= L0_8B_data_i;
end RTL;
| gpl-3.0 | 1176e9e760a47b78ca931825f6b33739 | 0.523644 | 3.474218 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Muxer/demuxer.vhd | 1 | 4,036 | ----------------------------------------------------------------------------------------------------
-- demuxer
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
----------------------------------------------------------------------------------------------------
-- PACKAGE
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
package demuxer_pkg is
--demuxer componenet declaration
component demuxer is
generic( INIT_SEL : std_logic_vector(1 downto 0) := b"01");
port( clk : in std_logic;
clk_2x : in std_logic;
rst : in std_logic;
sigs : in std_logic_vector;
sig1 : out std_logic_vector;
sig2 : out std_logic_vector);
end component;
end package;
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--This entity takes 2 input signals and interlaces them into 1 output signal. During development
--it was determined that the clock inputs must be phase aligned for best results
entity demuxer is
generic( INIT_SEL : std_logic_vector(1 downto 0) := b"01");
port( clk : in std_logic;
clk_2x : in std_logic;
rst : in std_logic;
sigs : in std_logic_vector;
sig1 : out std_logic_vector;
sig2 : out std_logic_vector);
end demuxer;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture behave of demuxer is
signal sigs_reg : std_logic_vector(sig1'range) := (others => '0');
signal selector : std_logic_vector(INIT_SEL'range) := INIT_SEL;
signal sel1 : std_logic_vector(sig1'range) := (others => '0');
signal sel2 : std_logic_vector(sig2'range) := (others => '0');
signal selx : std_logic_vector(sig1'range) := (others => '0');
signal sig1_reg : std_logic_vector(sig1'range) := (others => '0');
signal sig2_reg : std_logic_vector(sig2'range) := (others => '0');
begin
--Register the input
reg_in : process(clk_2x)
begin
if(rising_edge(clk_2x)) then
if(rst = '1') then
sigs_reg <= (others => '0');
else
sigs_reg <= sigs;
end if;
end if;
end process;
--Selection
update_selection : process(clk_2x)
begin
if(rising_edge(clk_2x)) then
if(rst = '1') then
selector <= INIT_SEL;
else
selector <= std_logic_vector(rotate_right(unsigned(selector), 1));
end if;
end if;
end process;
--Register the selection
reg_sel : process(clk_2x)
begin
if(rising_edge(clk_2x)) then
if(rst = '1') then
sel1 <= (others => '0');
sel2 <= (others => '0');
else
case selector is
when b"01" => sel1 <= sigs;
when b"10" => sel2 <= sigs;
when others => selx <= sigs;
end case;
end if;
end if;
end process;
--Register the output
reg_out : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
sig1_reg <= (others => '0');
sig2_reg <= (others => '0');
else
sig1_reg <= sel1;
sig2_reg <= sel2;
end if;
end if;
end process;
sig1 <= sig1_reg;
sig2 <= sig2_reg;
end behave;
| mit | 438defd035589c796dbc3f742d3bc821 | 0.418484 | 4.339785 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/FIFO2Elink.vhd | 2 | 8,819 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 17/08/2015
--! Module Name: FIFO2Elink
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
--! consists of 1 E-path
entity FIFO2Elink is
generic (
OutputDataRate : integer := 80; -- 80 / 160 / 320 MHz
elinkEncoding : std_logic_vector (1 downto 0) -- 00-direct data / 01-8b10b encoding / 10-HDLC encoding
);
port (
clk40 : in std_logic;
clk80 : in std_logic;
clk160 : in std_logic;
clk320 : in std_logic;
rst : in std_logic;
fifo_flush : in std_logic;
------
efifoDin : in std_logic_vector (17 downto 0); -- [data_code,2bit][data,16bit]
efifoWe : in std_logic;
efifoPfull : out std_logic;
efifoWclk : in std_logic;
------
DATA1bitOUT : out std_logic; -- serialized output
elink2bit : out std_logic_vector (1 downto 0); -- 2 bits @ clk40, can interface 2-bit of GBT frame
elink4bit : out std_logic_vector (3 downto 0); -- 4 bits @ clk40, can interface 4-bit of GBT frame
elink8bit : out std_logic_vector (7 downto 0) -- 8 bits @ clk40, can interface 8-bit of GBT frame
------
);
end FIFO2Elink;
architecture Behavioral of FIFO2Elink is
----
signal efifoRE, doutRdy : std_logic;
signal efifoDout : std_logic_vector(9 downto 0);
signal dout2bit : std_logic_vector(1 downto 0);
signal bitCount1,dout2bit_r : std_logic := '0';
signal dout4bit, dout4bit_r : std_logic_vector(3 downto 0);
signal dout8bit, dout8bit_r : std_logic_vector(7 downto 0);
signal bitCount2 : std_logic_vector(1 downto 0) := "00";
signal bitCount3 : std_logic_vector(2 downto 0) := "000";
----
begin
------------------------------------------------------------
-- EPATH_FIFO
------------------------------------------------------------
UEF: entity work.upstreamEpathFifoWrap
port map(
rst => rst,
fifoFLUSH => fifo_flush,
---
wr_clk => efifoWclk,
wr_en => efifoWe,
din => efifoDin,
---
rd_clk => clk160,
rd_en => efifoRE,
dout => efifoDout,
doutRdy => doutRdy,
---
full => open,
empty => open,
prog_full => efifoPfull
);
--
------------------------------------------------------------
-- E-PATH case 80 MHz
------------------------------------------------------------
OutputDataRate80: if OutputDataRate = 80 generate
EPROC_OUT2bit: entity work.EPROC_OUT2
port map(
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => rst,
ENA => '1', -- always enabled here
swap_outbits => '0', -- when '1', the output bits will be swapped
getDataTrig => efifoRE,
ENCODING => ("00" & elinkEncoding), -- 0000-direct data / 0001-8b10b encoding / 0010-HDLC encoding / others are used for TTC formats
EDATA_OUT => dout2bit, -- @ 40MHz
TTCin => "00", -- not in use here
DATA_IN => efifoDout, -- 10-bit data in
DATA_RDY => doutRdy
);
--
-------------------------------------------
-- serialization of the 2-bit data output:
-------------------------------------------
process(clk80)
begin
if rising_edge(clk80) then
bitCount1 <= not bitCount1;
end if;
end process;
--
process(clk80)
begin
if rising_edge(clk80) then
if bitCount1 = '0' then
dout2bit_r <= dout2bit(1);
end if;
end if;
end process;
---
process(clk80) -- serialized output
begin
if rising_edge(clk80) then
if bitCount1 = '0' then
DATA1bitOUT <= dout2bit(0);
else
DATA1bitOUT <= dout2bit_r;
end if;
end if;
end process;
---
elink2bit <= dout2bit; -- 2 bits @ clk40, can interface 2-bit of GBT frame
elink4bit <= (others=>'0'); -- 4 bits @ clk40, can interface 4-bit of GBT frame
elink8bit <= (others=>'0'); -- 8 bits @ clk40, can interface 8-bit of GBT frame
--
end generate OutputDataRate80;
------------------------------------------------------------
-- E-PATH case 160 MHz
------------------------------------------------------------
OutputDataRate160: if OutputDataRate = 160 generate
EPROC_OUT4bit: entity work.EPROC_OUT4
port map(
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => rst,
ENA => '1', -- always enabled here
getDataTrig => efifoRE,
ENCODING => ("00" & elinkEncoding), -- 0000-direct data / 0001-8b10b encoding / 0010-HDLC encoding / others are used for TTC formats
EDATA_OUT => dout4bit, -- @ 40MHz
TTCin => "00000", -- not in use here
DATA_IN => efifoDout, -- 10-bit data in
DATA_RDY => doutRdy
);
--
-------------------------------------------
-- serialization of the 4-bit data output:
-------------------------------------------
process(clk160)
begin
if rising_edge(clk160) then
bitCount2 <= bitCount2 + 1;
end if;
end process;
--
process(clk160)
begin
if rising_edge(clk160) then
if bitCount2 = "00" then
dout4bit_r <= dout4bit;
end if;
end if;
end process;
---
process(clk160) -- serialized output
begin
if rising_edge(clk160) then
case bitCount2 is
when "00" => DATA1bitOUT <= dout4bit(0);
when "01" => DATA1bitOUT <= dout4bit_r(1);
when "10" => DATA1bitOUT <= dout4bit_r(2);
when "11" => DATA1bitOUT <= dout4bit_r(3);
when others =>
end case;
end if;
end process;
---
elink2bit <= (others=>'0'); -- 2 bits @ clk40, can interface 2-bit of GBT frame
elink4bit <= dout4bit; -- 4 bits @ clk40, can interface 4-bit of GBT frame
elink8bit <= (others=>'0'); -- 8 bits @ clk40, can interface 8-bit of GBT frame
--
end generate OutputDataRate160;
------------------------------------------------------------
-- E-PATH case 320 MHz
------------------------------------------------------------
OutputDataRate320: if OutputDataRate = 320 generate
EPROC_OUT8bit: entity work.EPROC_OUT8
port map(
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => rst,
ENA => '1', -- always enabled here
getDataTrig => efifoRE,
ENCODING => ("00" & elinkEncoding), -- 0000-direct data / 0001-8b10b encoding / 0010-HDLC encoding / others are used for TTC formats
EDATA_OUT => dout8bit, -- @ 40MHz
TTCin => "000000000", -- not in use here
DATA_IN => efifoDout, -- 10-bit data in
DATA_RDY => doutRdy
);
--
-------------------------------------------
-- serialization of the 8-bit data output:
-------------------------------------------
process(clk320)
begin
if rising_edge(clk320) then
bitCount3 <= bitCount3 + 1;
end if;
end process;
--
process(clk320)
begin
if rising_edge(clk320) then
if bitCount3 = "000" then
dout8bit_r <= dout8bit;
end if;
end if;
end process;
---
process(clk320) -- serialized output
begin
if rising_edge(clk320) then
case bitCount3 is
when "000" => DATA1bitOUT <= dout8bit(0);
when "001" => DATA1bitOUT <= dout8bit_r(1);
when "010" => DATA1bitOUT <= dout8bit_r(2);
when "011" => DATA1bitOUT <= dout8bit_r(3);
when "100" => DATA1bitOUT <= dout8bit_r(4);
when "101" => DATA1bitOUT <= dout8bit_r(5);
when "110" => DATA1bitOUT <= dout8bit_r(6);
when "111" => DATA1bitOUT <= dout8bit_r(7);
when others =>
end case;
end if;
end process;
---
elink2bit <= (others=>'0'); -- 2 bits @ clk40, can interface 2-bit of GBT frame
elink4bit <= (others=>'0'); -- 4 bits @ clk40, can interface 4-bit of GBT frame
elink8bit <= dout8bit; -- 8 bits @ clk40, can interface 8-bit of GBT frame
--
end generate OutputDataRate320;
------------------------------------------------------------
-- unsupported Data Rate
------------------------------------------------------------
unsupported_Data_Rate: if OutputDataRate /= 80 and OutputDataRate /= 160 and OutputDataRate /= 320 generate
---
DATA1bitOUT <= '0'; -- serialized output
elink2bit <= (others=>'0'); -- 2 bits @ clk40, can interface 2-bit of GBT frame
elink4bit <= (others=>'0'); -- 4 bits @ clk40, can interface 4-bit of GBT frame
elink8bit <= (others=>'0'); -- 8 bits @ clk40, can interface 8-bit of GBT frame
--
end generate unsupported_Data_Rate;
end Behavioral;
| gpl-3.0 | 174cea5d93c70cd48a1aa542fb4e463e | 0.521828 | 3.587876 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/readout/event_timing_reset.vhd | 1 | 7,060 | ----------------------------------------------------------------------------------------
-- Company: NTU ATHENS - BNL
-- Engineer: Paris Moschovakos
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Paris Moschovakos
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 21.07.2016
-- Design Name:
-- Module Name: event_timing_reset.vhd
-- Project Name: MMFE8
-- Target Devices: Artix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
--
-- Changelog:
-- 09.09.2016 Added a glBCID counter for periodic soft reset of VMMs which takes place
-- every 102us if DAQ is on and if not in the middle of read-out. (Christos Bakalis)
-- 15.09.2016 Optimized the periodic soft reset process. (Paris Moschovakos)
--
----------------------------------------------------------------------------------------
library UNISIM;
library ieee;
use ieee.numeric_std.all;
use IEEE.numeric_bit.all;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use UNISIM.vcomponents.all;
entity event_timing_reset is
port(
hp_clk : in std_logic; -- High precision clock 1 GHz
clk : in std_logic; -- Main clock
clk_10_phase45 : in std_logic; -- Drives the reset
bc_clk : in std_logic; -- 40MHz
daqEnable : in std_logic; -- From flow FSM
pfBusy : in std_logic; -- From packet formation
reset : in std_logic; -- Reset
glBCID : out std_logic_vector(11 downto 0);
prec_cnt : out std_logic_vector(4 downto 0); -- 5 bits are more than enough (32) while 1-25 used
state_rst_out : out std_logic_vector(2 downto 0); -- For debugging purposes
rst_o : out std_logic; -- For debugging purposes
rst_done_o : out std_logic; -- For debugging purposes
vmm_ena_vec : out std_logic_vector(8 downto 1);
vmm_wen_vec : out std_logic_vector(8 downto 1);
reset_latched : out std_logic
);
end event_timing_reset;
architecture Behavioral of event_timing_reset is
-- Signals
signal glBCID_i : std_logic_vector(11 downto 0) := b"000000000000";
signal prec_cnt_i : std_logic_vector(4 downto 0) := b"00000";
signal state_nxt : std_logic_vector(2 downto 0);
signal vmm_wen_int, vmm_ena_int : std_logic;
signal acq_rst_int, acq_rst_d : std_logic;
signal state_rst : std_logic_vector(2 downto 0) := "000";
signal reset_latched_i : std_logic;
signal rst_done : std_logic;
signal rst_done_pre : std_logic:='0';
signal vmm_ena_vec_i : std_logic_vector(8 downto 1) := ( others => '0' );
signal vmm_wen_vec_i : std_logic_vector(8 downto 1) := ( others => '0' );
signal rst_i : std_logic := '0'; -- Internal reset related to glBCID counter
constant glBCID_limit : std_logic_vector(11 downto 0) := b"010000000000"; -- 1024*T(10MHz~100ns) = 102 us
-- Components if any
begin
-- Processes
synchronousSoftReset: process (clk_10_phase45, reset, reset_latched_i, state_rst)
begin
if rising_edge (clk_10_phase45) then
if reset_latched_i = '1' then
case state_rst is
when "000" => -- reset step 1
vmm_ena_vec_i <= x"00";
vmm_wen_vec_i <= x"00";
state_rst <= "001";
rst_done <= '0';
when "001" => -- reset step 2
vmm_ena_vec_i <= x"00";
vmm_wen_vec_i <= x"00";
state_rst <= "010";
rst_done <= '0';
when "010" => -- reset step 3
vmm_ena_vec_i <= x"00";
vmm_wen_vec_i <= x"FF";
state_rst <= "011";
when "011" => -- reset step 4
vmm_ena_vec_i <= x"00";
vmm_wen_vec_i <= x"00";
rst_done <= '1';
state_rst <= "000";
when others =>
state_rst <= "000";
end case;
elsif daqEnable = '1' then
vmm_ena_vec_i <= x"FF";
vmm_wen_vec_i <= x"00";
else
vmm_ena_vec_i <= x"00";
vmm_wen_vec_i <= x"00";
end if;
end if;
end process;
latchResetProc: process (clk, rst_done, rst_done_pre, reset, rst_i)
begin
if rising_edge(clk) then
if rst_done = '0' and rst_done_pre = '1' then
reset_latched_i <= '0';
elsif reset = '1' then
reset_latched_i <= '1';
elsif rst_i = '1' then -- internal reset. globBCID has reached limit
reset_latched_i <= '1';
end if;
end if;
end process;
latchResetProcAuxiliary: process (clk, rst_done)
begin
if rising_edge(clk) then
rst_done_pre <= rst_done;
end if;
end process;
globalBCIDproc: process (bc_clk, rst_done, daqEnable, pfBusy, glBCID_i)
begin
if rising_edge(bc_clk) then
if rst_done = '1' then
glBCID_i <= b"000000000000";
rst_i <= '0';
else
glBCID_i <= glBCID_i + 1;
if(pfBusy /= '1' and daqEnable = '1' and glBCID_i > glBCID_limit) then
rst_i <= '1';
else
rst_i <= '0';
end if;
end if;
end if;
end process;
--process (bc_clk)
-- begin
-- if (bc_clk'event and bc_clk = '1') then
-- end if;
--end process;
--process (bc_clk)
-- -- this process is an edge detect for acq_rst
-- begin
-- if rising_edge (bc_clk) then
-- end if;
--end process;
-- Signal assignment
-- prec_cnt <= prec_cnt_i;
glBCID <= glBCID_i;
reset_latched <= reset_latched_i;
vmm_ena_vec <= vmm_ena_vec_i;
vmm_wen_vec <= vmm_wen_vec_i;
------- Debugging signals assertion ---------
state_rst_out <= state_rst;
rst_o <= rst_i;
rst_done_o <= rst_done;
-- Instantiations if any
end Behavioral; | gpl-3.0 | 1e7ed300c770e0e0eda510ba9ae2eea2 | 0.525637 | 3.585576 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/EPROC_IN4_ALIGN_BLOCK.vhd | 2 | 5,112 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4_ALIGN_BLOCK
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.STD_LOGIC_1164.ALL;
use ieee.STD_LOGIC_UNSIGNED.ALL;
use work.all;
use work.centralRouter_package.all;
--! continuously aligns 4bit bit-stream to two commas
entity EPROC_IN4_ALIGN_BLOCK is
Port (
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
bytes : in word10b_2array_type; -- 8b10b encoded
bytes_rdy : in std_logic;
------------
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
------------
busyOut : out std_logic
);
end EPROC_IN4_ALIGN_BLOCK;
architecture Behavioral of EPROC_IN4_ALIGN_BLOCK is
signal bytes_rdy_enabled : std_logic;
signal bytes_r, bytes_c3 : word10b_2array_type := ((others=>'0'),(others=>'0'));
signal bytes_rdy_r, send_state : std_logic := '0';
signal dataOUT_s : std_logic_vector(9 downto 0) := (others => '0');
signal dataOUTrdy_s, dataOUTrdy_c3, dataOUTrdy_s1, bytes_rdy_s : std_logic := '0';
signal byte_count, byte_count_c3 : std_logic_vector(0 downto 0) := "0";
signal dataOUT_s_fe : std_logic_vector(9 downto 0);
begin
-------------------------------------------------------------------------------------------
-- clock1
-- input register
-------------------------------------------------------------------------------------------
bytes_rdy_enabled <= bytes_rdy;
--
process(bitCLKx2, rst)
begin
if rst = '1' then
bytes_rdy_s <= '0';
elsif bitCLKx2'event and bitCLKx2 = '1' then
if bytes_rdy_enabled = '1' then
bytes_rdy_s <= not bytes_rdy_s;
else
bytes_rdy_s <= '0';
end if;
end if;
end process;
--
input_latch: process(bitCLKx2, rst)
begin
if rst = '1' then
bytes_r <= ((others=>'0'),(others=>'0'));
elsif bitCLKx2'event and bitCLKx2 = '1' then
if bytes_rdy_enabled = '1' then
bytes_r <= bytes;
end if;
end if;
end process;
--
bytes_rdy_r <= bytes_rdy_s and bytes_rdy_enabled;
--
process(bitCLKx2)
begin
if bitCLKx2'event and bitCLKx2 = '1' then
if bytes_rdy_r = '1' then
byte_count <= "0";
else
if send_state = '1' then
byte_count <= byte_count + 1;
else
byte_count <= "0";
end if;
end if;
end if;
end process;
--
--
process(bitCLKx2, rst)
begin
if rst = '1' then
send_state <= '0';
elsif bitCLKx2'event and bitCLKx2 = '1' then
if bytes_rdy_r = '1' then
send_state <= '1';
else
if byte_count = "1" then
send_state <= '0';
end if;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- clock2
--
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if send_state = '1' then
dataOUTrdy_s <= not dataOUTrdy_s;
else
dataOUTrdy_s <= '0';
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- clock3*
-- bitCLKx2 -> bitCLKx4
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
bytes_c3 <= bytes_r;
dataOUTrdy_c3 <= dataOUTrdy_s;
byte_count_c3 <= byte_count;
end if;
end process;
--
out_select_proc: process(byte_count_c3, bytes_c3)
begin
case (byte_count_c3) is
when "0" => dataOUT_s <= bytes_c3(0);
when "1" => dataOUT_s <= bytes_c3(1);
when others =>
end case;
end process;
--
-------------------------------------------------------------------------------------------
-- clock4*
--
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
dataOUTrdy_s1 <= dataOUTrdy_c3;
end if;
end process;
--
dec_8b10: entity work.dec_8b10_wrap
port map(
RESET => rst,
RBYTECLK => bitCLKx4,
ABCDEIFGHJ_IN => dataOUT_s,
HGFEDCBA => dataOUT_s_fe(7 downto 0),
ISK => dataOUT_s_fe(9 downto 8),
BUSY => busyOut
);
--
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
dataOUT <= dataOUT_s_fe;
--dataOUTrdy <= dataOUTrdy_s1;
end if;
end process;
--
dataOUTrdy <= dataOUTrdy_s1;
--
end Behavioral;
| gpl-3.0 | dacb992642efc5d95339143198230e36 | 0.450117 | 3.742313 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/arp_SYNC.vhd | 2 | 4,794 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:09:01 02/20/2012
-- Design Name:
-- Module Name: arp_SYNC - Behavioral - synchronises between rx and tx clock domains
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
entity arp_SYNC is
port (
-- REQ to TX
arp_nwk_req : in arp_nwk_request_t; -- request for a translation from IP to MAC
send_who_has : out std_logic;
ip_entry : out std_logic_vector (31 downto 0);
-- RX to TX
recv_who_has : in std_logic; -- this is for us, we will respond
arp_entry_for_who_has : in arp_entry_t;
send_I_have : out std_logic;
arp_entry : out arp_entry_t;
-- RX to REQ
I_have_received : in std_logic;
nwk_result_status : out arp_nwk_rslt_t;
-- System Signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic
);
end arp_SYNC;
architecture Behavioral of arp_SYNC is
type sync_state_t is (IDLE, HOLD1, HOLD2);
-- state registers
signal ip_entry_state : sync_state_t;
signal arp_entry_state : sync_state_t;
signal ip_entry_reg : std_logic_vector (31 downto 0);
signal arp_entry_reg : arp_entry_t;
-- synchronisation registers
signal send_who_has_r1 : std_logic;
signal send_who_has_r2 : std_logic;
signal send_I_have_r1 : std_logic;
signal send_I_have_r2 : std_logic;
begin
combinatorial : process (
-- input signals
arp_nwk_req, recv_who_has, arp_entry_for_who_has, I_have_received, reset,
-- state
ip_entry_state, ip_entry_reg, arp_entry_state, arp_entry_reg,
-- synchronisation registers
send_who_has_r1, send_who_has_r2,
send_I_have_r1, send_I_have_r2
)
begin
-- set output followers
send_who_has <= send_who_has_r2;
ip_entry <= ip_entry_reg;
send_I_have <= send_I_have_r2;
arp_entry <= arp_entry_reg;
-- combinaltorial outputs
if I_have_received = '1' then
nwk_result_status <= RECEIVED;
else
nwk_result_status <= IDLE;
end if;
end process;
-- process for stablisising RX clock domain data registers
-- essentially holds data registers ip_entry and arp_entry static for 2 rx clk cycles
-- during transfer to TX clk domain
rx_sequential : process (tx_clk)
begin
if rising_edge(tx_clk) then
if reset = '1' then
-- reset state variables
ip_entry_reg <= (others => '0');
arp_entry_reg.ip <= (others => '0');
arp_entry_reg.mac <= (others => '0');
else
-- normal (non reset) processing
case ip_entry_state is
when IDLE =>
if arp_nwk_req.req = '1' then
ip_entry_reg <= arp_nwk_req.ip;
ip_entry_state <= HOLD1;
else
ip_entry_reg <= ip_entry_reg;
ip_entry_state <= IDLE;
end if;
when HOLD1 =>
ip_entry_reg <= ip_entry_reg;
ip_entry_state <= HOLD2;
when HOLD2 =>
ip_entry_reg <= ip_entry_reg;
ip_entry_state <= IDLE;
end case;
case arp_entry_state is
when IDLE =>
if recv_who_has = '1' then
arp_entry_reg <= arp_entry_for_who_has;
arp_entry_state <= HOLD1;
else
arp_entry_reg <= arp_entry_reg;
arp_entry_state <= IDLE;
end if;
when HOLD1 =>
arp_entry_reg <= arp_entry_reg;
arp_entry_state <= HOLD2;
when HOLD2 =>
arp_entry_reg <= arp_entry_reg;
arp_entry_state <= IDLE;
end case;
end if;
end if;
end process;
-- process for syncing to the TX clock domain
-- clocks control signals through 2 layers of tx clocking
tx_sequential : process (tx_clk)
begin
if rising_edge(tx_clk) then
if reset = '1' then
-- reset state variables
send_who_has_r1 <= '0';
send_who_has_r2 <= '0';
send_I_have_r1 <= '0';
send_I_have_r2 <= '0';
else
-- normal (non reset) processing
send_who_has_r1 <= arp_nwk_req.req;
send_who_has_r2 <= send_who_has_r1;
send_I_have_r1 <= recv_who_has;
send_I_have_r2 <= send_I_have_r1;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | dcb037c9eebae7152a2315652dc997a2 | 0.537547 | 3.45389 | false | false | false | false |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/ALU_mem.vhd | 1 | 3,010 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ALU_ram is
port(
clk,rst : in std_logic;
reg_addr : in std_logic_vector(3 downto 0);
mem_addr : in std_logic_vector(7 downto 0);
result : in std_logic_vector(7 downto 0);
operand : in std_logic_vector(1 downto 0);
reg_addr_out : out std_logic_vector(3 downto 0);
reg_data_out : out std_logic_vector(7 downto 0);
reg_write_enable : out std_logic;
mem_re, mem_we : out std_logic;
mem_read_out : out std_logic_vector(7 downto 0)
);
end ALU_ram;
architecture mixed of ALU_ram is
component ram is
generic(
data_width : natural := 8;
addr_width : natural := 8);
port(
clk,rst : in std_logic;
data : in std_logic_vector(data_width-1 downto 0);
write_addr : in std_logic_vector(addr_width-1 downto 0);
read_addr : in std_logic_vector(addr_width-1 downto 0);
w_enable : inout std_logic;
r_enable : inout std_logic;
data_out : out std_logic_vector(data_width-1 downto 0));
end component;
signal mem_write_addr : std_logic_vector(7 downto 0);
signal mem_read_addr : std_logic_vector(7 downto 0);
signal mem_result : std_logic_vector(7 downto 0);
signal mem_write_enable : std_logic;
signal mem_read_enable : std_logic;
signal mem_data_out : std_logic_vector(7 downto 0);
begin
c0: ram port map(clk, rst, mem_result, mem_write_addr, mem_read_addr, mem_write_enable, mem_read_enable, mem_data_out);
--For Debug
mem_re <= mem_read_enable;
mem_we <= mem_write_enable;
mem_read_out <= mem_data_out;
process(reg_addr, mem_addr, result, operand)
begin
case operand is
when "00" => --no op
mem_write_addr <= "00000000";
mem_read_addr <= "00000000";
mem_result <= "00000000";
mem_write_enable <= '0';
mem_read_enable <= '0';
mem_data_out <= "00000000";
reg_addr_out <= "0000";
reg_data_out <= "00000000";
reg_write_enable <= '0';
when "01" => --R <= ALU
mem_write_enable <= '0';
mem_read_enable <= '0';
reg_addr_out <= reg_addr;
reg_data_out <= result;
reg_write_enable <= '1';
when "10" => --R <= Mem
mem_read_addr <= mem_addr;
mem_read_enable <= '1';
mem_write_enable <= '0';
reg_addr_out <= reg_addr;
reg_write_enable <= '1';
reg_data_out <= mem_data_out;
when "11" => --Mem <= R
mem_write_addr <= mem_addr;
mem_write_enable <= '1';
mem_read_enable <= '0';
reg_write_enable <= '0';
mem_result <= result;
when others =>
mem_write_addr <= "00000000";
mem_read_addr <= "00000000";
mem_result <= "00000000";
mem_write_enable <= '0';
mem_read_enable <= '0';
mem_data_out <= "00000000";
reg_addr_out <= "0000";
reg_data_out <= "00000000";
reg_write_enable <= '0';
end case;
end process;
end mixed;
| unlicense | b8b9237ad1ca658074c26bb921458a25 | 0.58505 | 3.135417 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/ping_reply_processor.vhd | 1 | 10,736 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 02.04.2017
-- Design Name: Ping Reply Processor
-- Module Name: ping_reply_processor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions: Vivado 2016.2
-- Description: This module receives a ping/echo request packet from ICMP_RX and
-- forwards an appropriate echo reply to ICMP_TX.
--
-- Dependencies: Xilinx FIFO IP
--
-- Changelog:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
entity ping_reply_processor is
Port(
-- ICMP RX interface
icmp_rx_start : in std_logic;
icmp_rxi : in icmp_rx_type;
-- system signals
tx_clk : in std_logic;
rx_clk : in std_logic;
reset : in std_logic;
fifo_init : in std_logic;
-- ICMP/UDP mux interface
sel_icmp : out std_logic;
-- ICMP TX interface
icmp_tx_start : out std_logic;
icmp_tx_ready : in std_logic;
icmp_txo : out icmp_tx_type;
icmp_tx_is_idle : in std_logic
);
end ping_reply_processor;
architecture Behavioral of ping_reply_processor is
COMPONENT icmp_payload_buffer
PORT(
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
type rx_state_type is (IDLE, CNT_LEN, CHK_TYPE_CODE, WAIT_FOR_TX);
type tx_state_type is (IDLE, SET_HDR, START, WAIT_FOR_EMPTY, DELAY);
signal ping_rx_state : rx_state_type := IDLE;
signal ping_tx_state : tx_state_type := IDLE;
signal payLen_count_ug : unsigned (15 downto 0) := (others => '0');
signal chksum_out_ug : unsigned (15 downto 0) := (others => '0');
signal tx_ena : std_logic := '0';
signal rd_ena : std_logic := '0';
signal rst_fifo_fsm : std_logic := '0';
signal rst_fifo : std_logic := '0';
signal fifo_empty : std_logic := '0';
signal fifo_full : std_logic := '0';
signal data_last : std_logic := '0';
signal data_valid : std_logic := '0';
signal data_valid_reg : std_logic := '0';
begin
--------------------------------------------------------------------------
-- combinatorial process to implement FSM RX and determine control signals
--------------------------------------------------------------------------
ping_FSM_RX: process(rx_clk)
begin
if(rising_edge(rx_clk))then
if(reset = '1')then
payLen_count_ug <= (others => '0');
chksum_out_ug <= (others => '0');
tx_ena <= '0';
ping_rx_state <= IDLE;
else
case ping_rx_state is
when IDLE =>
if(icmp_rx_start = '1' and icmp_rxi.hdr.icmp_type = x"08")then
if(icmp_rxi.payload.data_in_valid = '1' and icmp_rxi.payload.data_in_last = '0')then
payLen_count_ug <= payLen_count_ug + 1;
ping_rx_state <= CNT_LEN;
elsif(icmp_rx_start = '1' and icmp_rxi.payload.data_in_valid = '1' and icmp_rxi.payload.data_in_last = '1')then
-- payload is only one-byte long
payLen_count_ug <= payLen_count_ug + 1;
ping_rx_state <= CHK_TYPE_CODE;
else
ping_rx_state <= IDLE;
end if;
else
payLen_count_ug <= (others => '0');
chksum_out_ug <= (others => '0');
tx_ena <= '0';
ping_rx_state <= IDLE;
end if;
when CNT_LEN =>
payLen_count_ug <= payLen_count_ug + 1;
if(icmp_rxi.payload.data_in_last = '1')then
chksum_out_ug <= unsigned(icmp_rxi.hdr.icmp_chksum);
ping_rx_state <= CHK_TYPE_CODE;
else
ping_rx_state <= CNT_LEN;
end if;
when CHK_TYPE_CODE =>
if(icmp_rxi.hdr.icmp_type = x"08" and icmp_rxi.hdr.icmp_code = x"00")then -- echo request
chksum_out_ug <= chksum_out_ug + "0000100000000000"; -- plus 2048 in dec
payLen_count_ug <= payLen_count_ug;
tx_ena <= '1';
ping_rx_state <= WAIT_FOR_TX;
else
chksum_out_ug <= (others => '0');
payLen_count_ug <= (others => '0');
tx_ena <= '0';
ping_rx_state <= IDLE;
end if;
when WAIT_FOR_TX =>
chksum_out_ug <= chksum_out_ug;
if(fifo_empty = '1')then
tx_ena <= '0';
ping_rx_state <= IDLE;
else
tx_ena <= '1';
ping_rx_state <= WAIT_FOR_TX;
end if;
when others =>
ping_rx_state <= IDLE;
end case;
end if;
end if;
end process;
ping_FSM_TX: process(tx_clk)
begin
if(rising_edge(tx_clk))then
if(reset = '1')then
rd_ena <= '0';
rst_fifo_fsm <= '0';
data_last <= '0';
data_valid <= '0';
icmp_tx_start <= '0';
sel_icmp <= '0';
ping_tx_state <= IDLE;
else
case ping_tx_state is
when IDLE =>
rst_fifo_fsm <= '0';
if(tx_ena = '1')then
sel_icmp <= '1';
ping_tx_state <= SET_HDR;
else
sel_icmp <= '0';
ping_tx_state <= IDLE;
end if;
when SET_HDR =>
icmp_txo.hdr.dst_ip_addr <= icmp_rxi.hdr.src_ip_addr;
icmp_txo.hdr.icmp_pay_len <= std_logic_vector(payLen_count_ug); -- payload length in bytes
------------------------
icmp_txo.hdr.icmp_type <= x"00"; -- reply
icmp_txo.hdr.icmp_code <= x"00"; -- reply
icmp_txo.hdr.icmp_chksum <= std_logic_vector(chksum_out_ug); -- old checksum + 2048(in dec)
icmp_txo.hdr.icmp_ident <= icmp_rxi.hdr.icmp_ident; -- CC
icmp_txo.hdr.icmp_seqNum <= icmp_rxi.hdr.icmp_seqNum; -- CC
icmp_tx_start <= '1';
ping_tx_state <= START;
when START =>
if(icmp_tx_ready = '1')then
rd_ena <= '1';
data_valid <= '1';
icmp_tx_start <= '0';
ping_tx_state <= WAIT_FOR_EMPTY;
else
rd_ena <= '0';
data_valid <= '0';
icmp_tx_start <= '1';
ping_tx_state <= START;
end if;
when WAIT_FOR_EMPTY =>
if(fifo_empty = '1')then
rd_ena <= '0';
data_valid <= '0';
data_last <= '1';
rst_fifo_fsm <= '1';
ping_tx_state <= DELAY;
else
rd_ena <= '1';
data_valid <= '1';
data_last <= '0';
ping_tx_state <= WAIT_FOR_EMPTY;
end if;
when DELAY =>
data_last <= '0';
rst_fifo_fsm <= '1';
if(icmp_tx_is_idle = '1')then
ping_tx_state <= IDLE;
else
ping_tx_state <= DELAY;
end if;
when others =>
ping_tx_state <= IDLE;
end case;
end if;
end if;
end process;
fdre_valid_0 : process(tx_clk)
begin
if(rising_edge(tx_clk))then
if(reset = '1')then
data_valid_reg <= '0';
else
data_valid_reg <= data_valid;
end if;
end if;
end process;
fdre_valid_1 : process(tx_clk)
begin
if(rising_edge(tx_clk))then
if(reset = '1')then
icmp_txo.payload.data_out_valid <= '0';
else
icmp_txo.payload.data_out_valid <= data_valid_reg;
end if;
end if;
end process;
fifo_payload_buffer: icmp_payload_buffer
PORT MAP (
rst => rst_fifo,
wr_clk => rx_clk,
rd_clk => tx_clk,
din => icmp_rxi.payload.data_in,
wr_en => icmp_rxi.payload.data_in_valid,
rd_en => rd_ena,
dout => icmp_txo.payload.data_out,
full => fifo_full,
empty => fifo_empty
);
icmp_txo.payload.data_out_last <= data_last;
rst_fifo <= rst_fifo_fsm or fifo_init;
end Behavioral;
| gpl-3.0 | ed75f01daca226e6fd69c97e37f6bc8f | 0.438804 | 3.980719 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN2_HDLC.vhd | 3 | 6,959 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2015
--! Module Name: EPROC_IN2_HDLC
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
use work.all;
--! HDLC decoder for EPROC_IN2 module
entity EPROC_IN2_HDLC is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (1 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN2_HDLC;
architecture Behavioral of EPROC_IN2_HDLC is
----------------------------------
----------------------------------
signal edataIN_r : std_logic_vector (1 downto 0) := (others=>'1');
signal bit_in_sr,out_sr : std_logic_vector (7 downto 0) := (others=>'1');
signal bit_cnt,error_bit_cnt : std_logic_vector (2 downto 0) := (others=>'0');
signal error_state,error_state_r,error_out : std_logic := '1';
signal edataIN_latch_trig,bit_in,isflag_r,isflag_rr,bit_in_r,bit_in_r_we,remove_zero_r : std_logic := '0';
signal isflag,iserror,remove_zero,out_sr_rdy,dataOUTrdy_s,error_out_rdy,remove_zero_state : std_logic;
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- input serializer
-------------------------------------------------------------------------------------------
process(bitCLKx2, rst)
begin
if rst = '1' then
edataIN_latch_trig <= '0';
elsif bitCLKx2'event and bitCLKx2 = '1' then
edataIN_latch_trig <= not edataIN_latch_trig;
end if;
end process;
--
process(bitCLKx2, rst)
begin
if rst = '1' then
edataIN_r <= (others=>'1');
elsif bitCLKx2'event and bitCLKx2 = '1' then
if edataIN_latch_trig = '1' then
edataIN_r <= edataIN;
end if;
end if;
end process;
--
process(bitCLKx2)
begin
if bitCLKx2'event and bitCLKx2 = '1' then
if edataIN_latch_trig = '0' then
bit_in <= edataIN_r(0);
else
bit_in <= edataIN_r(1);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock1
-- input shift register
-------------------------------------------------------------------------------------------
process(bitCLKx2, rst)
begin
if rst = '1' then
bit_in_sr <= (others=>'1');
elsif bitCLKx2'event and bitCLKx2 = '1' then
bit_in_sr <= bit_in & bit_in_sr(7 downto 1);
end if;
end process;
--
isflag <= '1' when (bit_in_sr = "01111110") else '0';
iserror <= '1' when (bit_in_sr(7 downto 1) = "1111111") else '0';
remove_zero <= '1' when (bit_in_sr(7 downto 2) = "011111" and isflag = '0' and error_state = '0') else '0';
--
-------------------------------------------------------------------------------------------
--clock2
-- latching the error state, forwarding clean bit sequence
-------------------------------------------------------------------------------------------
process(bitCLKx2, rst)
begin
if rst = '1' then
error_state <= '1';
elsif bitCLKx2'event and bitCLKx2 = '1' then
if iserror = '1' then
error_state <= '1';
elsif isflag = '1' then
error_state <= '0';
end if;
end if;
end process;
--
process(bitCLKx2, rst)
begin
if rst = '1' then
isflag_r <= '0';
isflag_rr <= '0';
--bit_in_r_we <= '0';
remove_zero_r <= '0';
error_state_r <= '1';
elsif bitCLKx2'event and bitCLKx2 = '1' then
isflag_r <= isflag;
isflag_rr <= isflag_r;
--bit_in_r_we <= not(error_state or remove_zero);
remove_zero_r <= remove_zero;
error_state_r <= error_state;
end if;
end process;
--
bit_in_r_we <= not(error_state or remove_zero);
--
bit_in_r <= bit_in_sr(7);
--
-------------------------------------------------------------------------------------------
--clock3
-- output shift register
-------------------------------------------------------------------------------------------
process(bitCLKx2)
begin
if bitCLKx2'event and bitCLKx2 = '1' then
if remove_zero = '0' then
out_sr <= bit_in_r & out_sr(7 downto 1);
end if;
end if;
end process;
--
process(bitCLKx2, rst)
begin
if rst = '1' then
bit_cnt <= (others=>'0');
elsif bitCLKx2'event and bitCLKx2 = '1' then
if error_state = '1' then
bit_cnt <= (others=>'0');
else
if bit_in_r_we = '1' or isflag_r = '1' then
bit_cnt <= bit_cnt + 1;
end if;
end if;
end if;
end process;
--
process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if bit_cnt = "111" and error_state = '0' and remove_zero = '0' then
out_sr_rdy <= '1';
else
out_sr_rdy <= '0';
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock3+
-- output latch
-------------------------------------------------------------------------------------------
dataOUTrdy_s <= isflag_r or out_sr_rdy or error_out_rdy;
out_rdy_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitCLKx4,dataOUTrdy_s,dataOUTrdy);
--
process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if bit_in_sr /= x"ff" then
error_out <= '0';
elsif error_state = '1' then
error_out <= '1';
end if;
end if;
end process;
--
process(bitCLKx2, rst)
begin
if rst = '1' then
error_bit_cnt <= (others=>'0');
elsif bitCLKx2'event and bitCLKx2 = '1' then
if error_out = '0' then
error_bit_cnt <= (others=>'0');
else
error_bit_cnt <= error_bit_cnt + 1;
end if;
end if;
end process;
--
error_out_rdy <= '1' when (error_bit_cnt = "001" and error_out = '1') else '0';
--
process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if error_state_r = '1' and isflag = '1' then
dataOUT(9 downto 8) <= "10"; -- sop
elsif error_state_r = '0' and isflag = '1' then
dataOUT(9 downto 8) <= "01"; -- eop
else
dataOUT(9 downto 8) <= error_out & error_out; -- 00-data, 11-error
end if;
end if;
end process;
--
dataOUT(7 downto 0) <= out_sr;
--
end Behavioral;
| gpl-3.0 | 5a424f0798cf66b5caf3b155216e3175 | 0.454376 | 3.579733 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Biphase_Decomp/biphase_decomp.vhd | 1 | 3,287 | ----------------------------------------------------------------------------------------------------
-- Bi-Phase Decomposition
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
----------------------------------------------------------------------------------------------------
-- PACKAGE
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package biphase_decomp_pkg is
component biphase_decomp is
port( clk : in std_logic;
rst : in std_logic;
x : in std_logic_vector;
x0 : out std_logic_vector;
x1 : out std_logic_vector);
end component;
end package;
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity biphase_decomp is
port( clk : in std_logic;
rst : in std_logic;
x : in std_logic_vector;
x0 : out std_logic_vector;
x1 : out std_logic_vector);
end biphase_decomp;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE (structural)
----------------------------------------------------------------------------------------------------
architecture structural of biphase_decomp is
signal output_choice : std_logic;
signal x_reg : std_logic_vector(x'range);
signal x0_reg : std_logic_vector(x'range);
signal x1_reg : std_logic_vector(x'range);
begin
--Latch on to the input
x_latch : process(clk, rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
x_reg <= (others => '0');
else
x_reg <= x;
end if;
end if;
end process;
--Select output
--TODO: for larger than biphase implement this part using a circular shift register with a single bit for each output
tictoc : process(clk, rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
output_choice <= '0';
else
output_choice <= not output_choice;
end if;
end if;
end process;
--Send data to the current output
muxing : process(clk, rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
x0_reg <= (others => '0');
x1_reg <= (others => '0');
else
if(output_choice = '0') then
x0_reg <= x_reg;
else
x1_reg <= x_reg;
end if;
end if;
end if;
end process;
--connect registers to output
x0 <= x0_reg;
x1 <= x1_reg;
end structural;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE (behavioral)
----------------------------------------------------------------------------------------------------
--architecture behave of biphase_decomp is
--begin
--
--end behave;
| mit | c0f8b5487181142e27e95ac787b5c285 | 0.371463 | 5.072531 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Filter_Bank/filter_bank.vhd | 1 | 12,174 | --------------------------------------------------------------------------------------------------
-- 3-stage Filter Bank
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package filter_bank_pkg is
--FIR filter component declaration
component filter_bank is
generic( analysis_low : coefficient_array;
analysis_high : coefficient_array;
synthesis_low : coefficient_array;
synthesis_high : coefficient_array);
port( clk0 : in std_logic;
clk1 : in std_logic;
clk2 : in std_logic;
clk3 : in std_logic;
rst : in std_logic;
x : in sig;
y : out sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
use work.decomposition_pkg.all;
use work.reconstruction_pkg.all;
--synthesis translate_off
use work.tb_write_csv_pkg.all;
--synthesis translate_on
entity filter_bank is
generic( analysis_low : coefficient_array;
analysis_high : coefficient_array;
synthesis_low : coefficient_array;
synthesis_high : coefficient_array);
port( clk0 : in std_logic;
clk1 : in std_logic;
clk2 : in std_logic;
clk3 : in std_logic;
rst : in std_logic;
x : in sig;
y : out sig);
end filter_bank;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of filter_bank is
constant BANK0_FILE : string := "X:\Education\Masters Thesis\matlab\filter_bank\bank0.csv";
constant BANK1_FILE : string := "X:\Education\Masters Thesis\matlab\filter_bank\bank1.csv";
constant BANK2_FILE : string := "X:\Education\Masters Thesis\matlab\filter_bank\bank2.csv";
constant BANK3_FILE : string := "X:\Education\Masters Thesis\matlab\filter_bank\bank3.csv";
constant BANK4_FILE : string := "X:\Education\Masters Thesis\matlab\filter_bank\bank4.csv";
constant BANK5_FILE : string := "X:\Education\Masters Thesis\matlab\filter_bank\bank5.csv";
constant BANK6_FILE : string := "X:\Education\Masters Thesis\matlab\filter_bank\bank6.csv";
constant BANK7_FILE : string := "X:\Education\Masters Thesis\matlab\filter_bank\bank7.csv";
-- Numerics NM : N -> stage, M -> bank
signal down_y00 : sig := (others => '0');
signal down_y01 : sig := (others => '0');
signal down_y10 : sig := (others => '0');
signal down_y11 : sig := (others => '0');
signal down_y12 : sig := (others => '0');
signal down_y13 : sig := (others => '0');
signal down_y20 : sig := (others => '0');
signal down_y21 : sig := (others => '0');
signal down_y22 : sig := (others => '0');
signal down_y23 : sig := (others => '0');
signal down_y24 : sig := (others => '0');
signal down_y25 : sig := (others => '0');
signal down_y26 : sig := (others => '0');
signal down_y27 : sig := (others => '0');
signal up_y00 : sig := (others => '0');
signal up_y01 : sig := (others => '0');
signal up_y10 : sig := (others => '0');
signal up_y11 : sig := (others => '0');
signal up_y12 : sig := (others => '0');
signal up_y13 : sig := (others => '0');
signal up_y20 : sig := (others => '0');
signal up_y21 : sig := (others => '0');
signal up_y22 : sig := (others => '0');
signal up_y23 : sig := (others => '0');
signal up_y24 : sig := (others => '0');
signal up_y25 : sig := (others => '0');
signal up_y26 : sig := (others => '0');
signal up_y27 : sig := (others => '0');
begin
------- Stage 0 Decomposition ---------------------
stage0_decomp : decomposition
generic map(low_pass => analysis_low,
high_pass => analysis_high)
port map( clk_low => clk1,
clk_high => clk0,
rst => rst,
x => x,
y_low => down_y00,
y_high => down_y01);
------- Stage 1 Decomposition ---------------------
stage1_bank0_decomp : decomposition
generic map(low_pass => analysis_low,
high_pass => analysis_high)
port map( clk_low => clk2,
clk_high => clk1,
rst => rst,
x => down_y00,
y_low => down_y10,
y_high => down_y11);
stage1_bank1_decomp : decomposition
generic map(low_pass => analysis_low,
high_pass => analysis_high)
port map( clk_low => clk2,
clk_high => clk1,
rst => rst,
x => down_y01,
y_low => down_y12,
y_high => down_y13);
------- Stage 2 Decomposition ---------------------
stage2_bank0_decomp : decomposition
generic map(low_pass => analysis_low,
high_pass => analysis_high)
port map( clk_low => clk3,
clk_high => clk2,
rst => rst,
x => down_y10,
y_low => down_y20,
y_high => down_y21);
stage2_bank1_decomp : decomposition
generic map(low_pass => analysis_low,
high_pass => analysis_high)
port map( clk_low => clk3,
clk_high => clk2,
rst => rst,
x => down_y11,
y_low => down_y22,
y_high => down_y23);
stage2_bank2_decomp : decomposition
generic map(low_pass => analysis_low,
high_pass => analysis_high)
port map( clk_low => clk3,
clk_high => clk2,
rst => rst,
x => down_y12,
y_low => down_y24,
y_high => down_y25);
stage2_bank3_decomp : decomposition
generic map(low_pass => analysis_low,
high_pass => analysis_high)
port map( clk_low => clk3,
clk_high => clk2,
rst => rst,
x => down_y13,
y_low => down_y26,
y_high => down_y27);
------- Filter Bank Region --------------------------
up_y20 <= down_y20;
up_y21 <= down_y21;
up_y22 <= down_y22;
up_y23 <= down_y23;
up_y24 <= down_y24;
up_y25 <= down_y25;
up_y26 <= down_y26;
up_y27 <= down_y27;
--synthesis translate_off
--Output to files for review
writer20 : tb_write_csv
generic map(FILENAME => BANK0_FILE)
port map( clk => clk3,
data => std_logic_vector(down_y20));
writer21 : tb_write_csv
generic map(FILENAME => BANK1_FILE)
port map( clk => clk3,
data => std_logic_vector(down_y21));
writer22 : tb_write_csv
generic map(FILENAME => BANK2_FILE)
port map( clk => clk3,
data => std_logic_vector(down_y22));
writer23 : tb_write_csv
generic map(FILENAME => BANK3_FILE)
port map( clk => clk3,
data => std_logic_vector(down_y23));
writer24 : tb_write_csv
generic map(FILENAME => BANK4_FILE)
port map( clk => clk3,
data => std_logic_vector(down_y24));
writer25 : tb_write_csv
generic map(FILENAME => BANK5_FILE)
port map( clk => clk3,
data => std_logic_vector(down_y25));
writer26 : tb_write_csv
generic map(FILENAME => BANK6_FILE)
port map( clk => clk3,
data => std_logic_vector(down_y26));
writer27 : tb_write_csv
generic map(FILENAME => BANK7_FILE)
port map( clk => clk3,
data => std_logic_vector(down_y27));
--synthesis translate_on
------- Stage 2 Reconstruction --------------------
stage2_bank0_recon : reconstruction
generic map(low_pass => synthesis_low,
high_pass => synthesis_high)
port map( clk_low => clk3,
clk_high => clk2,
rst => rst,
x_low => up_y20,
x_high => up_y21,
y => up_y10);
stage2_bank1_recon : reconstruction
generic map(low_pass => synthesis_low,
high_pass => synthesis_high)
port map( clk_low => clk3,
clk_high => clk2,
rst => rst,
x_low => up_y22,
x_high => up_y23,
y => up_y11);
stage2_bank2_recon : reconstruction
generic map(low_pass => synthesis_low,
high_pass => synthesis_high)
port map( clk_low => clk3,
clk_high => clk2,
rst => rst,
x_low => up_y24,
x_high => up_y25,
y => up_y12);
stage2_bank3_recon : reconstruction
generic map(low_pass => synthesis_low,
high_pass => synthesis_high)
port map( clk_low => clk3,
clk_high => clk2,
rst => rst,
x_low => up_y26,
x_high => up_y27,
y => up_y13);
------- Stage 1 Reconstruction --------------------
-- up_y10 <= down_y10;
-- up_y11 <= down_y11;
-- up_y12 <= down_y12;
-- up_y13 <= down_y13;
stage1_bank0_recon : reconstruction
generic map(low_pass => synthesis_low,
high_pass => synthesis_high)
port map( clk_low => clk2,
clk_high => clk1,
rst => rst,
x_low => up_y10,
x_high => up_y11,
y => up_y00);
stage1_bank1_recon : reconstruction
generic map(low_pass => synthesis_low,
high_pass => synthesis_high)
port map( clk_low => clk2,
clk_high => clk1,
rst => rst,
x_low => up_y12,
x_high => up_y13,
y => up_y01);
------- Stage 0 Reconstruction --------------------
-- up_y00 <= down_y00;
-- up_y01 <= down_y01;
stage0_bank0_recon : reconstruction
generic map(low_pass => synthesis_low,
high_pass => synthesis_high)
port map( clk_low => clk1,
clk_high => clk0,
rst => rst,
x_low => up_y00,
x_high => up_y01,
y => y);
end behave;
| mit | 7fd73e22686c758efb8b74c004778a6c | 0.417447 | 4.013848 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/LFSR/LFSR.vhd | 1 | 11,203 | ----------------------------------------------------------------------------------------------------
-- Linear Feedback Shift Register
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
----------------------------------------------------------------------------------------------------
-- PACKAGE
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package lfsr_pkg is
component lfsr is
port( clk : in std_logic;
rst : in std_logic;
poly_mask : in std_logic_vector;
seed : in std_logic_vector;
feedin : in std_logic_vector;
feedout : out std_logic_vector;
history : out std_logic_vector);
end component;
function xor_Reduce(bits: std_logic_vector) return std_logic;
end package;
----------------------------------------------------------------------------------------------------
-- PACKAGE BODY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package body lfsr_pkg is
-- XOR's all the bits in a vector. Useful for checking the parity of a vector.
-- bits: Logic vector
-- returns: result of all the bits XOR'd together
function xor_Reduce(bits: std_logic_vector) return std_logic is
begin
if(bits'low = bits'high) then
return bits(bits'low);
else
if(bits'ascending) then
return bits(bits'low) xor xor_Reduce(bits(bits'low+1 to bits'high));
else
return bits(bits'low) xor xor_Reduce(bits(bits'high downto bits'low+1));
end if;
end if;
end function;
end package body;
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.lfsr_pkg.all;
use work.reduce_pkg.reduce_xor;
--Linear feedback shift register
--Using this module requires that the feedout be fed-back into feedin at some point. The feedback
--would normally be done internally, except some designs require modifying the feedback before
--returning it to the shift register. To support such robust designs the feedback is always
--expected to be performed at a higher level, even when simple feedback is all that is required
--(e.g. feedin<=feedout;)
entity lfsr is
port( --Process clock, on every rising edge the LFSR updates the feedback with a new value and
--shifts previous values into the history.
clk : in std_logic;
--Asynchronous reset. While high: resets the LFSR to the seed value and sets the poly_mask
--used for the feedback polynomial
rst : in std_logic;
--Place '1's in the bits where the polynomial calls for taps. Read up on LFSR's before
--selecting a polynomial, not all choices will yield "good" random numbers.
--(e.g. X^5 + X^3 + 1 would be poly_mask(4 downto 0) <= "10100";)
poly_mask : in std_logic_vector;
--Must be identical in length to poly_mask. Initial value of the shift register. Is only
--set during rst = '1'. DO NOT SET TO ALL '0's
seed : in std_logic_vector;
--Return path for the feedback. Feeds directly into the shift register.
feedin : in std_logic_vector;
--Outbound path of the feedback. This value is the result of the polynomial. Feedback
--this value to this module using feedin port. Some designs call for xor'ing this value
--with another value before returning to feedin. Wider feedback signal generate multiple
--feedback bits per clock cycle, but can be difficult for timing.
feedout : out std_logic_vector;
--This output contains the history of the feedback which is also used to calculate the
--subsequent feedback. The history has to be seeded, hence the seed input. It can also
--be used to source pseudorandom values.
history : out std_logic_vector);
end lfsr;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE (structural)
----------------------------------------------------------------------------------------------------
architecture structural of lfsr is
signal poly_mask_reg : std_logic_vector(poly_mask'range) := (others => '0');
--All of these internal signals need to be defined in the same 0-to-'length range-order to make
--optimal use of the 'range attribute
signal shift_reg : std_logic_vector(0 to (feedin'length + poly_mask'length-1)) := (others => '0');
alias data_in : std_logic_vector(0 to (feedin'length-1)) is shift_reg(0 to (feedin'length-1));
alias polynomial : std_logic_vector(0 to (poly_mask'length-1)) is shift_reg(feedin'length to (feedin'length + poly_mask'length-1));
signal result : std_logic_vector(0 to (feedout'length-1)) := (others => '0');
begin
--load the left-most bits of shift_reg with the feedin
data_in <= feedin;
--Process to shift the feedback through a shift-register
shifter: process(clk, rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
--Typical vector assignments preserve the left-to-right bit order. We need to preserve the
--0 to n order for this assignment. The seed may not always be defined 0-to-n, but at
--least we know polynomial is 0-to-n.
for n in seed'low to seed'high loop
polynomial(n-seed'low) <= seed(n);
end loop;
--Set the polynomial mask when only while reset is asserted.
poly_mask_reg <= poly_mask;
else
--shift_reg is a concatenation of data_in and polynomial. By assigning the left-most
--bits of shift_reg to polynomial(the right-most bits), we achieve a right shift.
polynomial <= shift_reg(polynomial'range);
end if;
end if;
end process;
--The shift register updates every clock cycle, when it does, this generate loop calculates the
--feedback result. The result is the modulus-2 summation of specified polynomial taps.
--Modulus-2 addition is simply an xor operation.
calc_feedback: for outbit in result'reverse_range generate
signal polynomial_window : std_logic_vector(polynomial'range);
signal final_polynomial : std_logic_vector(polynomial'range);
signal iResult : std_logic := '0';
begin
--Lines up the polynomial with the current outbit
polynomial_window <= shift_reg(outbit + polynomial'low + 1 to outbit + polynomial'high + 1);
--This loop will handle situations when the poly_mask is not a 0-based ascending ranged vector
loop_taps: for tap in poly_mask_reg'range generate
final_polynomial(tap-poly_mask'low) <= poly_mask_reg(tap-poly_mask'low) and polynomial_window(tap-poly_mask'low);
end generate;
--Finally we need to find the modulus-2 summation of the final polynomial for this outbit
reducer: reduce_xor
port map(data => final_polynomial,
result => iResult);
result(outbit) <= iResult;
end generate;
--Before feeding the result back to the shift register, pass it to the higher level first.
feedout <= result;
--Output the polynomial portion of the shift register.
history <= polynomial;
end structural;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE (behavioral)
----------------------------------------------------------------------------------------------------
architecture behave of lfsr is
signal poly_mask_reg : std_logic_vector(poly_mask'range) := (others => '0');
--All of these internal signals need to be defined in the same 0-to-'length range order to make optimal use of the 'range attribute
signal shift_reg : std_logic_vector(0 to (feedin'length + poly_mask'length-1)) := (others => '0');
alias data_in : std_logic_vector(0 to (feedin'length-1)) is shift_reg(0 to (feedin'length-1));
alias polynomial : std_logic_vector(0 to (poly_mask'length-1)) is shift_reg(feedin'length to (feedin'length + poly_mask'length-1));
signal result : std_logic_vector(0 to (feedout'length-1));
begin
--load the left-most bits of shift_reg with the feedin
data_in <= feedin;
--Process to shift the feedback through a shift-register
shifter: process(clk, rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
--Typical vector assignments preserve the left-to-right bit order. We need to preserve the
--0 to n order for this assignment. The seed may not always be defined 0-to-n, but at
--least we know polynomial is 0-to-n.
for n in seed'low to seed'high loop
polynomial(n-seed'low) <= seed(n);
end loop;
--Set the polynomial mask when only while reset is asserted.
poly_mask_reg <= poly_mask;
else
--shift_reg is a concatenation of data_in and polynomial. By assigning the left-most
--bits of shift_reg to polynomial(the right-most bits), we achieve a right shift.
polynomial <= shift_reg(polynomial'range);
end if;
end if;
end process;
--The shift register updates every clock cycle, when it does, this process calculates the feedback result
--The result is the modulus-2 summation of specified polynomial taps.
--Modulus-2 addition is simply an xor operation.
process(polynomial)
variable tmp : std_logic_vector(0 to (result'length + polynomial'length-1));
begin
tmp := (others => '0');
tmp(result'length to (result'length + polynomial'length-1)) := polynomial;--way to say polynomial'(range + scalar)?
for outbit in result'reverse_range loop --It is critical that the result is calculated from right to left. This ensures the feedback history is preserved
for tap in poly_mask_reg'range loop
if(poly_mask_reg(tap) = '1') then
tmp(outbit) := tmp(outbit) xor tmp(tap-poly_mask_reg'low+outbit+1); --subtracting poly_mask_reg'low is to handle situations where the poly_mask_reg'range is not 0-based (e.g. 1 to 15)
end if;
end loop;
end loop;
--left-most bits of the temporary variable contains the result.
result <= tmp(result'range);
end process;
--Before feeding the result back to the shift register, pass it to the higher level first.
feedout(feedout'range) <= result(result'range);
--Output the polynomial portion of the shift register.
history <= polynomial;
end behave;
| mit | 7a54fd36eca7c616006e66aeb0b1feea | 0.579666 | 4.449166 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_IN2.vhd | 1 | 4,595 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! 80 Mbps E-link processor, 2bit input @ clk40
entity EPROC_IN2 is
generic (do_generate : boolean := true);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
swap_inputbits : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (1 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN2;
architecture Behavioral of EPROC_IN2 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
signal edata_in_s : std_logic_vector (1 downto 0);
signal DATA_OUT_direct,DATA_OUT_8b10b_case,DATA_OUT_HDLC_case,DATA_OUT_s : std_logic_vector (9 downto 0);
signal DATA_RDY_direct,DATA_RDY_8b10b_case,DATA_RDY_HDLC_case,DATA_RDY_sig : std_logic;
signal RESTART_sig, rst_case00, rst_case01, rst_case10 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
--
in_sel: process(swap_inputbits,EDATA_IN)
begin
if swap_inputbits = '1' then
edata_in_s <= EDATA_IN(0) & EDATA_IN(1);
else
edata_in_s <= EDATA_IN;
end if;
end process;
--
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
--
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
rst_case00 <= '0' when ((RESTART_sig = '0') and (ENCODING = "00")) else '1';
--
direct_data_case: entity work.EPROC_IN2_direct
port map(
bitCLK => bitCLK,
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => edata_in_s,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= '0' when ((RESTART_sig = '0') and (ENCODING = "01")) else '1';
--
dec8b10b_case: entity work.EPROC_IN2_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => edata_in_s,
dataOUT => DATA_OUT_8b10b_case,
dataOUTrdy => DATA_RDY_8b10b_case,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
rst_case10 <= '0' when ((RESTART_sig = '0') and (ENCODING = "10")) else '1';
--
decHDLC_case: entity work.EPROC_IN2_HDLC
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case10,
edataIN => edata_in_s,
dataOUT => DATA_OUT_HDLC_case,
dataOUTrdy => DATA_RDY_HDLC_case
);
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_case,
data2 => DATA_OUT_HDLC_case,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_case,
data2 => DATA_RDY_HDLC_case,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 | 2910638cbec64cc79393a79fe41292db | 0.466376 | 3.643933 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/readout/vmmSignalsDemux.vhd | 1 | 3,955 | -- Company: NTU ATHENS - BNL
-- Engineer: Paris Moschovakos
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Paris Moschovakos
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 21.07.2016
-- Design Name:
-- Module Name: vmmSignalsDemux.vhd - Behavioral
-- Project Name: MMFE8
-- Target Devices: Artix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
--
-- Changelog:
--
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vmmSignalsDemux is
Port ( selVMM : in STD_LOGIC_VECTOR (2 downto 0);
vmm_data0_vec : in STD_LOGIC_VECTOR (8 downto 1);
vmm_data1_vec : in STD_LOGIC_VECTOR (8 downto 1);
vmm_data0 : out STD_LOGIC;
vmm_data1 : out STD_LOGIC;
vmm_cktk : in STD_LOGIC;
vmm_ckdt_enable : out STD_LOGIC_VECTOR (8 downto 1);
vmm_cktk_vec : out STD_LOGIC_VECTOR (8 downto 1)
);
end vmmSignalsDemux;
architecture Behavioral of vmmSignalsDemux is
begin
vmm_data0 <= vmm_data0_vec(1) when (selVMM = b"000") else
vmm_data0_vec(2) when (selVMM = b"001") else
vmm_data0_vec(3) when (selVMM = b"010") else
vmm_data0_vec(4) when (selVMM = b"011") else
vmm_data0_vec(5) when (selVMM = b"100") else
vmm_data0_vec(6) when (selVMM = b"101") else
vmm_data0_vec(7) when (selVMM = b"110") else
vmm_data0_vec(8) when (selVMM = b"111");
vmm_data1 <= vmm_data1_vec(1) when (selVMM = b"000") else
vmm_data1_vec(2) when (selVMM = b"001") else
vmm_data1_vec(3) when (selVMM = b"010") else
vmm_data1_vec(4) when (selVMM = b"011") else
vmm_data1_vec(5) when (selVMM = b"100") else
vmm_data1_vec(6) when (selVMM = b"101") else
vmm_data1_vec(7) when (selVMM = b"110") else
vmm_data1_vec(8) when (selVMM = b"111");
vmm_ckdt_enable(1) <= '1' when (selVMM = b"000") else '0';
vmm_ckdt_enable(2) <= '1' when (selVMM = b"001") else '0';
vmm_ckdt_enable(3) <= '1' when (selVMM = b"010") else '0';
vmm_ckdt_enable(4) <= '1' when (selVMM = b"011") else '0';
vmm_ckdt_enable(5) <= '1' when (selVMM = b"100") else '0';
vmm_ckdt_enable(6) <= '1' when (selVMM = b"101") else '0';
vmm_ckdt_enable(7) <= '1' when (selVMM = b"110") else '0';
vmm_ckdt_enable(8) <= '1' when (selVMM = b"111") else '0';
vmm_cktk_vec(1) <= vmm_cktk when (selVMM = b"000") else '0';
vmm_cktk_vec(2) <= vmm_cktk when (selVMM = b"001") else '0';
vmm_cktk_vec(3) <= vmm_cktk when (selVMM = b"010") else '0';
vmm_cktk_vec(4) <= vmm_cktk when (selVMM = b"011") else '0';
vmm_cktk_vec(5) <= vmm_cktk when (selVMM = b"100") else '0';
vmm_cktk_vec(6) <= vmm_cktk when (selVMM = b"101") else '0';
vmm_cktk_vec(7) <= vmm_cktk when (selVMM = b"110") else '0';
vmm_cktk_vec(8) <= vmm_cktk when (selVMM = b"111") else '0';
end Behavioral; | gpl-3.0 | 9760a1722e5afe34ff817d8a05558f26 | 0.564349 | 3.265896 | false | false | false | false |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/sim/ZynqDesign_axi_gpio_0_0.vhd | 1 | 8,824 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY ZynqDesign_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ZynqDesign_axi_gpio_0_0;
ARCHITECTURE ZynqDesign_axi_gpio_0_0_arch OF ZynqDesign_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ZynqDesign_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 1,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
gpio_io_o => gpio_io_o,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END ZynqDesign_axi_gpio_0_0_arch;
| mit | 4adaf8611fe9c86bf7fdc418f704046f | 0.680077 | 3.256089 | false | false | false | false |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/sim/ZynqDesign_rst_processing_system7_0_100M_0.vhd | 1 | 5,947 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY ZynqDesign_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END ZynqDesign_rst_processing_system7_0_100M_0;
ARCHITECTURE ZynqDesign_rst_processing_system7_0_100M_0_arch OF ZynqDesign_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ZynqDesign_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END ZynqDesign_rst_processing_system7_0_100M_0_arch;
| mit | bb80d52aa7c82197fc3d1bd48ae6cd41 | 0.71061 | 3.608617 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/imports/ipv4_types.vhd | 1 | 4,569 | --
--
-- Purpose: This package defines types for use in IPv4
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.axi.all;
use work.arp_types.all;
package ipv4_types is
constant IP_BC_ADDR : std_logic_vector (31 downto 0) := x"c0a800ff";
-- constant MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"1458D001AA73";
constant MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"ffffffffffff";
--------------
-- IPv4 TX --
--------------
-- coding for result in tx
constant IPTX_RESULT_NONE : std_logic_vector (1 downto 0) := "00";
constant IPTX_RESULT_SENDING : std_logic_vector (1 downto 0) := "01";
constant IPTX_RESULT_ERR : std_logic_vector (1 downto 0) := "10";
constant IPTX_RESULT_SENT : std_logic_vector (1 downto 0) := "11";
type ipv4_tx_header_type is record
protocol : std_logic_vector (7 downto 0);
data_length : std_logic_vector (15 downto 0); -- user data size, bytes
dst_ip_addr : std_logic_vector (31 downto 0);
end record;
type ipv4_tx_type is record
hdr : ipv4_tx_header_type; -- header to tx
data : axi_out_type; -- tx axi bus
end record;
--------------
-- IPv4 RX --
--------------
-- coding for last_error_code in rx hdr
constant RX_EC_NONE : std_logic_vector (3 downto 0) := x"0";
constant RX_EC_ET_ETH : std_logic_vector (3 downto 0) := x"1"; -- early termination in ETH hdr phase
constant RX_EC_ET_IP : std_logic_vector (3 downto 0) := x"2"; -- early termination in IP hdr phase
constant RX_EC_ET_USER : std_logic_vector (3 downto 0) := x"3"; -- early termination in USER DATA phase
type ipv4_rx_header_type is record
is_valid : std_logic;
protocol : std_logic_vector (7 downto 0);
data_length : std_logic_vector (15 downto 0); -- user data size, bytes
src_ip_addr : std_logic_vector (31 downto 0);
num_frame_errors : std_logic_vector (7 downto 0);
last_error_code : std_logic_vector (3 downto 0); -- see RX_EC_xxx constants
is_broadcast : std_logic; -- set if the msg received is a broadcast
end record;
type ipv4_rx_type is record
hdr : ipv4_rx_header_type; -- header received
data : axi_in_type; -- rx axi bus
end record;
type ip_control_type is record
arp_controls : arp_control_type;
end record;
------------
-- UDP TX --
------------
-- coding for result in tx
constant UDPTX_RESULT_NONE : std_logic_vector (1 downto 0) := "00";
constant UDPTX_RESULT_SENDING : std_logic_vector (1 downto 0) := "01";
constant UDPTX_RESULT_ERR : std_logic_vector (1 downto 0) := "10";
constant UDPTX_RESULT_SENT : std_logic_vector (1 downto 0) := "11";
type udp_tx_header_type is record
dst_ip_addr : std_logic_vector (31 downto 0);
dst_port : std_logic_vector (15 downto 0);
src_port : std_logic_vector (15 downto 0);
data_length : std_logic_vector (15 downto 0); -- user data size, bytes
checksum : std_logic_vector (15 downto 0);
end record;
type udp_tx_type is record
hdr : udp_tx_header_type; -- header received
data : axi_out_type; -- tx axi bus
end record;
------------
-- UDP RX --
------------
type udp_rx_header_type is record
is_valid : std_logic;
src_ip_addr : std_logic_vector (31 downto 0);
src_port : std_logic_vector (15 downto 0);
dst_port : std_logic_vector (15 downto 0);
data_length : std_logic_vector (15 downto 0); -- user data size, bytes
end record;
type udp_rx_type is record
hdr : udp_rx_header_type; -- header received
data : axi_in_type; -- rx axi bus
end record;
type udp_addr_type is record
ip_addr : std_logic_vector (31 downto 0);
port_num : std_logic_vector (15 downto 0);
end record;
type udp_control_type is record
ip_controls : ip_control_type;
end record;
type udp_response is record
resp_header : std_logic_vector (31 downto 0);
resp_data : std_logic_vector (15 downto 0);
end record;
type resp_data is record
sn : std_logic_vector (31 downto 0);
vmm_id : std_logic_vector (15 downto 0);
cmd : std_logic_vector (15 downto 0);
error : std_logic_vector (31 downto 0);
end record;
type resp_header is record
test : std_logic_vector (15 downto 0);
end record;
end ipv4_types;
| gpl-3.0 | c2196a3ff089a7cc39b65f31afbeb21e | 0.589407 | 3.076768 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/readout/vmm_readout_wrapper.vhd | 1 | 13,224 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 28.04.2017 12:39:23
-- Design Name: VMM Readout Wrapper
-- Module Name: vmm_readout_wrapper - RTL
-- Project Name: NTUA-BNL VMM3 Readout Firmware
-- Target Devices: Xilinx xc7a200t-2fbg484
-- Tool Versions: Vivado 2016.4
-- Description: Wrapper that contains the two main components that implement the
-- VMM3 readout, namely vmm_readout (old continouous mode) and L0_wrapper (level-0)
-- mode.
--
-- Dependencies:
--
-- Changelog:
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
use UNISIM.VComponents.all;
entity vmm_readout_wrapper is
generic(is_mmfe8 : std_logic;
vmmReadoutMode : std_logic);
Port(
------------------------------------
--- Continuous Readout Interface ---
clkTkProc : in std_logic; -- Used to clock checking for data process
clkDtProc : in std_logic; -- Used to clock word readout process
clk : in std_logic; -- Main clock
--
daq_enable : in std_logic;
trigger_pulse : in std_logic; -- Trigger
cktk_max : in std_logic_vector(7 downto 0); -- Max number of CKTKs
--
dt_state_o : out std_logic_vector(3 downto 0); -- for debugging
dt_cntr_st_o : out std_logic_vector(3 downto 0); -- for debugging
------------------------------------
---- Level-0 Readout Interface -----
clk_ckdt : in std_logic; -- will be forwarded to the VMM
rst_buff : in std_logic; -- reset the level-0 buffer
rst_intf_proc : in std_logic; -- reset the pf interface
--
level_0 : in std_logic; -- level-0 signal
wr_accept : in std_logic; -- buffer acceptance window
--
vmm_conf : in std_logic; -- high during VMM configuration
daq_on_inhib : out std_logic; -- prevent daq_on state before checking link health
------------------------------------
---- Packet Formation Interface ----
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(15 downto 0);
vmmEventDone : out std_logic;
rd_ena_buff : in std_logic; -- read the readout buffer (level0 or continuous)
vmmId : in std_logic_vector(2 downto 0); -- VMM to be readout
linkHealth_bmsk : out std_logic_vector(8 downto 1); -- status of comma alignment links
------------------------------------
---------- VMM3 Interface ----------
vmm_data0_vec : in std_logic_vector(8 downto 1); -- Single-ended data0 from VMM
vmm_data1_vec : in std_logic_vector(8 downto 1); -- Single-ended data1 from VMM
vmm_ckdt_glbl : out std_logic; -- Strobe to VMM CKDT
vmm_ckdt_enable : out std_logic_vector(8 downto 1); -- Enable signal for VMM CKDT
vmm_cktk_vec : out std_logic_vector(8 downto 1) -- Strobe to VMM CKTK
);
end vmm_readout_wrapper;
architecture RTL of vmm_readout_wrapper is
component vmm_readout is
Port(
clkTkProc : in std_logic; -- Used to clock checking for data process
clkDtProc : in std_logic; -- Used to clock word readout process
clk : in std_logic; -- Used for fast switching between processes
vmm_data0_vec : in std_logic_vector(8 downto 1); -- Single-ended data0 from VMM
vmm_data1_vec : in std_logic_vector(8 downto 1); -- Single-ended data1 from VMM
vmm_ckdt_enable : out std_logic_vector(8 downto 1); -- Enable signal for VMM CKDT
vmm_cktk_vec : out std_logic_vector(8 downto 1); -- Strobe to VMM CKTK
vmm_ckdt : out std_logic; -- Strobe to VMM CKDT
daq_enable : in std_logic;
trigger_pulse : in std_logic; -- Trigger
cktk_max : in std_logic_vector(7 downto 0);
vmmId : in std_logic_vector(2 downto 0); -- VMM to be readout
ethernet_fifo_wr_en : out std_logic; -- To be used for reading out seperate FIFOs in VMMx8 parallel readout
vmm_data_buf : buffer std_logic_vector(37 downto 0);
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(15 downto 0);
vmmEventDone : out std_logic;
rd_en : in std_logic;
dt_state_o : out std_logic_vector(3 downto 0);
dt_cntr_st_o : out std_logic_vector(3 downto 0)
);
end component;
component level0_wrapper is
Generic(is_mmfe8 : std_logic;
vmmReadoutMode : std_logic);
Port(
------------------------------------
------- General Interface ----------
clk_ckdt : in std_logic; -- will be forwarded to the VMM
clk : in std_logic; -- buffer read domain
rst_buff : in std_logic; -- reset buffer
level_0 : in std_logic; -- level-0 signal
wr_accept : in std_logic; -- buffer acceptance window
vmm_conf : in std_logic; -- high during VMM configuration
daq_on_inhib : out std_logic; -- prevent daq_on state before checking link health
------------------------------------
---- Packet Formation Interface ----
rd_ena_buff : in std_logic;
rst_intf_proc : in std_logic; -- reset the pf interface
vmmId : in std_logic_vector(2 downto 0); -- VMM to be readout
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(15 downto 0);
vmmEventDone : out std_logic;
linkHealth_bmsk : out std_logic_vector(8 downto 1);
------------------------------------
---------- VMM3 Interface ----------
vmm_data0_vec : in std_logic_vector(8 downto 1); -- Single-ended data0 from VMM
vmm_data1_vec : in std_logic_vector(8 downto 1); -- Single-ended data1 from VMM
vmm_cktk_vec : out std_logic_vector(8 downto 1) -- Strobe to VMM CKTK
);
end component;
signal data0_in_vec_cont : std_logic_vector(8 downto 1) := (others => '0');
signal data1_in_vec_cont : std_logic_vector(8 downto 1) := (others => '0');
signal cktk_out_vec_cont : std_logic_vector(8 downto 1) := (others => '0');
signal vmm_ckdt_enable_cont : std_logic_vector(8 downto 1) := (others => '0');
signal vmmWord_cont : std_logic_vector(15 downto 0) := (others => '0');
signal rd_en_cont : std_logic := '0';
signal vmmWordReady_cont : std_logic := '0';
signal vmmEventDone_cont : std_logic := '0';
signal vmm_ckdt_cont : std_logic := '0';
signal data0_in_vec_l0 : std_logic_vector(8 downto 1) := (others => '0');
signal data1_in_vec_l0 : std_logic_vector(8 downto 1) := (others => '0');
signal cktk_out_vec_l0 : std_logic_vector(8 downto 1) := (others => '0');
signal vmmWord_l0 : std_logic_vector(15 downto 0) := (others => '0');
signal rd_en_l0 : std_logic := '0';
signal vmmWordReady_l0 : std_logic := '0';
signal vmmEventDone_l0 : std_logic := '0';
signal vmm_ckdt_glbl_i : std_logic := '0';
begin
-- continuous mode module instantiation
continuousReadoutMode: if vmmReadoutMode = '0' generate
readout_vmm_cont: vmm_readout
port map(
clkTkProc => clkTkProc,
clkDtProc => clkDtProc,
clk => clk,
vmm_data0_vec => data0_in_vec_cont,
vmm_data1_vec => data1_in_vec_cont,
vmm_ckdt_enable => vmm_ckdt_enable_cont,
vmm_cktk_vec => cktk_out_vec_cont,
vmm_ckdt => vmm_ckdt_cont,
daq_enable => daq_enable,
trigger_pulse => trigger_pulse,
cktk_max => cktk_max,
vmmId => vmmId,
ethernet_fifo_wr_en => open,
vmm_data_buf => open,
rd_en => rd_en_cont,
vmmWordReady => vmmWordReady_cont,
vmmWord => vmmWord_cont,
vmmEventDone => vmmEventDone_cont,
dt_state_o => dt_state_o,
dt_cntr_st_o => dt_cntr_st_o
);
end generate continuousReadoutMode;
level0_readout_case : if vmmReadoutMode = '1' generate
readout_vmm_l0: level0_wrapper
generic map(is_mmfe8 => is_mmfe8, vmmReadoutMode => vmmReadoutMode)
port map(
------------------------------------
------- General Interface ----------
clk_ckdt => clk_ckdt, -- vmm_ckdt_glbl_i ??
clk => clk,
rst_buff => rst_buff,
level_0 => level_0,
wr_accept => wr_accept,
vmm_conf => vmm_conf,
daq_on_inhib => daq_on_inhib,
------------------------------------
---- Packet Formation Interface ----
rd_ena_buff => rd_ena_buff,
rst_intf_proc => rst_intf_proc,
vmmId => vmmId,
vmmWordReady => vmmWordReady_l0,
vmmWord => vmmWord_l0,
vmmEventDone => vmmEventDone_l0,
linkHealth_bmsk => linkHealth_bmsk,
------------------------------------
---------- VMM3 Interface ----------
vmm_data0_vec => data0_in_vec_l0,
vmm_data1_vec => data1_in_vec_l0,
vmm_cktk_vec => cktk_out_vec_l0
);
end generate level0_readout_case;
-- multiplexer/demultiplexer for different mode cases
vmm_io_muxDemux: process(vmmWordReady_cont, vmmEventDone_cont, vmmWord_cont, vmm_ckdt_enable_cont, cktk_out_vec_cont, rd_ena_buff,
vmmWordReady_l0, vmmEventDone_l0, vmmWord_l0, cktk_out_vec_l0, vmm_data0_vec, vmm_data1_vec)
begin
case vmmReadoutMode is
when '0' =>
-- outputs
vmmWordReady <= vmmWordReady_cont;
vmmEventDone <= vmmEventDone_cont;
vmmWord <= vmmWord_cont;
vmm_ckdt_enable <= vmm_ckdt_enable_cont;
vmm_cktk_vec <= cktk_out_vec_cont;
-- inputs
rd_en_cont <= rd_ena_buff;
rd_en_l0 <= '0';
data0_in_vec_cont <= vmm_data0_vec;
data1_in_vec_cont <= vmm_data1_vec;
data0_in_vec_l0 <= (others => '0');
data1_in_vec_l0 <= (others => '0');
when '1' =>
-- outputs
vmmWordReady <= vmmWordReady_l0;
vmmEventDone <= vmmEventDone_l0;
vmmWord <= vmmWord_l0;
vmm_ckdt_enable <= x"FF";
vmm_cktk_vec <= cktk_out_vec_l0;
-- inputs
rd_en_cont <= '0';
rd_en_l0 <= rd_ena_buff;
data0_in_vec_cont <= (others => '0');
data1_in_vec_cont <= (others => '0');
data0_in_vec_l0 <= vmm_data0_vec;
data1_in_vec_l0 <= vmm_data1_vec;
when others =>
-- outputs
vmmWordReady <= '0';
vmmEventDone <= '0';
vmmWord <= (others => '0');
vmm_ckdt_enable <= (others => '0');
vmm_cktk_vec <= (others => '0');
-- inputs
data0_in_vec_cont <= (others => '0');
data1_in_vec_cont <= (others => '0');
data0_in_vec_l0 <= (others => '0');
data1_in_vec_l0 <= (others => '0');
end case;
end process;
CKDT_BUFGMUX: BUFGMUX
port map(O => vmm_ckdt_glbl_i, I0 => vmm_ckdt_cont, I1 => clk_ckdt, S => vmmReadoutMode);
vmm_ckdt_glbl <= vmm_ckdt_glbl_i;
end RTL;
| gpl-3.0 | 8e361081a2d04d960e4a351f987efffe | 0.513612 | 3.926366 | false | false | false | false |
tdotu/ra | control.vhd | 1 | 1,663 | LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY control IS
PORT
(
instruction : IN std_logic_vector(5 downto 0);
RegDst : OUT std_logic;
Branch : OUT std_logic_vector(1 downto 0);
MemtoReg : OUT std_logic;
ALUOp : OUT std_logic_vector(3 downto 0);
MemWrite : OUT std_logic;
ALUSrc : OUT std_logic;
RegWrite : OUT std_logic
);
END control;
ARCHITECTURE behavior OF control IS
BEGIN
WITH instruction SELECT -- 00 = Branch
Branch <= "10" WHEN "000000", -- 3 downto 0 = equal zero or not equal zero
"11" WHEN "001111",
"00" WHEN OTHERS;
WITH instruction SELECT -- 01 = ALU
ALUOp <= "0000" WHEN "010000", -- 3 downto 0 = ALU-Code
"0001" WHEN "010001",
"0010" WHEN "010010",
"0110" WHEN "010110",
"0111" WHEN "010111",
"1100" WHEN "011100",
"1111" WHEN "100000",
"1111" WHEN OTHERS;
WITH instruction SELECT
MemWrite <= '1' WHEN "100000",
'0' WHEN OTHERS;
WITH instruction SELECT
MemtoReg <= '1' WHEN "100001",
'0' WHEN OTHERS;
WITH instruction SELECT
ALUSrc <= '1' WHEN "100000",
'1' WHEN "100001",
'0' WHEN OTHERS;
WITH instruction SELECT
RegWrite <= '1' WHEN "010000",
'1' WHEN "010001",
'1' WHEN "010010",
'1' WHEN "010110",
'1' WHEN "010111",
'1' WHEN "011100",
'0' WHEN OTHERS;
WITH instruction SELECT
RegDst <= '1' WHEN "010000",
'1' WHEN "010001",
'1' WHEN "010010",
'1' WHEN "010110",
'1' WHEN "010111",
'1' WHEN "011100",
'0' WHEN OTHERS;
END behavior; | gpl-3.0 | e8abae3ca948a56af822844f93620faa | 0.558028 | 3.241715 | false | false | false | false |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/interrupt_handler.vhd | 1 | 8,836 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
entity interrupt_handler is
port (
data_in1, data_in2 : in std_logic_vector(7 downto 0);
raddr1, raddr2 : inout std_logic_vector(3 downto 0);
raddr_write : out std_logic_vector(3 downto 0);
reg_re, reg_we : out std_logic;
data_out : out std_logic_vector(7 downto 0);
PC_in : in std_logic_vector(7 downto 0);
PC_out : out std_logic_vector(7 downto 0);
interrupt_reg_data : in std_logic_vector(7 downto 0);
interrupt_reg_we : in std_logic;
interrupt_or_return_happened, interrupt_or_return_handled : out std_logic;
return_opcode : in std_logic;
clk, rst : in std_logic
);
end entity;
architecture behav of interrupt_handler is
signal interrupt_reg : std_logic_vector(7 downto 0);
signal count : integer range 0 to 20;
signal scratch_PC : std_logic_vector(7 downto 0);
signal scratch_interrupt_reg : std_logic_vector(7 downto 0);
signal raddr1_out, raddr2_out, raddr_read : std_logic_vector(3 downto 0);
signal re, we, rise_we : std_logic;
signal interrupt_happened, interrupt_handled, return_happened, return_handled : std_logic;
component scratch_pad is
port (
data_in1, data_in2 : in std_logic_vector(7 downto 0);
raddr_write1, raddr_write2 : in std_logic_vector(3 downto 0);
data_out : out std_logic_vector(7 downto 0);
raddr_read : in std_logic_vector(3 downto 0);
re, we, clk : in std_logic
);
end component;
begin
scratch_pad1 : scratch_pad
port map (
data_in1 => data_in1,
data_in2 => data_in2,
raddr_write1 => raddr1_out,
raddr_write2 => raddr2_out,
data_out => data_out,
raddr_read => raddr_read,
re => re,
we => we,
clk => clk
);
process (clk, rst) is
variable verify : std_logic_vector(3 downto 0);
variable tmp_sr: std_logic_vector(7 downto 0);
variable tmp_scratch_interrupt_reg : std_logic_vector(7 downto 0);
begin
if (rst = '1') then
interrupt_reg <= X"00";
interrupt_happened <= '0';
interrupt_handled <= '0';
return_happened <= '0';
return_handled <= '0';
elsif (rising_edge(clk)) then
verify := interrupt_reg(7 downto 4) and interrupt_reg(3 downto 0);
if (interrupt_happened = '0') then
if (verify /= "0000") then
interrupt_happened <= '1';
interrupt_handled <= '0';
return_happened <= '0';
return_handled <= '0';
count <= 0;
scratch_PC <= PC_in;
if (verify(3) = '1') then
PC_out <= "00010100";
scratch_interrupt_reg <= (interrupt_reg and "01111111" );
interrupt_reg <= ("00000000" );
elsif (verify(2) = '1') then
PC_out <= "00100000";
scratch_interrupt_reg <= (interrupt_reg and "10111111" );
interrupt_reg <= ("00000000");
elsif (verify(1) = '1') then
PC_out <= "01000000";
scratch_interrupt_reg <= (interrupt_reg and "11011111" );
interrupt_reg <= ( "00000000" );
elsif (verify(0) = '1') then
PC_out <= "10000000";
scratch_interrupt_reg <= (interrupt_reg and "11101111" );
interrupt_reg <= ("00000000");
end if;
end if;
elsif (interrupt_handled = '0') then
if (count = 0) then
count <= count + 1;
elsif (count = 1) then
count <= count + 1;
raddr1 <= X"0";
raddr2 <= X"1";
reg_re <= '1';
rise_we <= '1';
elsif (count = 2) then
count <= count + 1;
raddr1 <= X"2";
raddr2 <= X"3";
reg_re <= '1';
rise_we <= '1';
elsif (count = 3) then
count <= count + 1;
raddr1 <= X"4";
raddr2 <= X"5";
reg_re <= '1';
rise_we <= '1';
elsif (count = 4) then
count <= count + 1;
raddr1 <= X"6";
raddr2 <= X"7";
reg_re <= '1';
rise_we <= '1';
elsif (count = 5) then
count <= count + 1;
raddr1 <= X"8";
raddr2 <= X"9";
reg_re <= '1';
rise_we <= '1';
elsif (count = 6) then
count <= count + 1;
raddr1 <= X"A";
raddr2 <= X"B";
reg_re <= '1';
rise_we <= '1';
elsif (count = 7) then
count <= count + 1;
raddr1 <= X"C";
raddr2 <= X"D";
reg_re <= '1';
rise_we <= '1';
elsif (count = 8) then
count <= 9;
raddr1 <= X"E";
raddr2 <= X"F";
reg_re <= '1';
rise_we <= '1';
elsif (count = 9) then
interrupt_handled <= '1';
interrupt_happened <= '0';
reg_re <= '0';
reg_we <= '0';
we <= '0';
re <= '0';
rise_we <= '0';
end if;
end if;
--------------------------------------------------------------------------- checking for next interrupt
if (return_opcode = '1') then
return_happened <= '1';
return_handled <= '0';
interrupt_happened <= '0';
interrupt_handled <= '0';
count <= 0;
elsif (return_happened = '1') then
report "Return from interrupt";
tmp_sr := interrupt_reg or scratch_interrupt_reg;
verify := tmp_sr(7 downto 4) and tmp_sr(3 downto 0);
if (verify /= "0000") then
if (count = 0) then
if (verify(3) = '1') then
PC_out <= "00010100";
tmp_scratch_interrupt_reg := (tmp_sr and "01111111" );
--interrupt_reg <= ("00000000" );
elsif (verify(2) = '1') then
PC_out <= "00100000";
tmp_scratch_interrupt_reg := (tmp_sr and "10111111" );
--interrupt_reg <= ("00000000");
elsif (verify(1) = '1') then
PC_out <= "01000000";
tmp_scratch_interrupt_reg := (tmp_sr and "11011111" );
--interrupt_reg <= ( "00000000" );
elsif (verify(0) = '1') then
PC_out <= "10000000";
tmp_scratch_interrupt_reg := (tmp_sr and "11101111" );
--interrupt_reg <= ("00000000");
end if;
count <= count + 1;
elsif (count = 1) then
count <= count + 1;
elsif (count = 2) then
return_happened <= '0';
return_handled <= '1';
count <= 0;
interrupt_reg <= X"00";
scratch_interrupt_reg <= tmp_scratch_interrupt_reg;
end if;
else
report "No interrupt. Return to normal";
if (count = 0) then
count <= count + 1;
PC_out <= scratch_PC;
interrupt_reg <= interrupt_reg or scratch_interrupt_reg;
report "count = 0";
elsif (count = 1) then
count <= count + 1;
raddr_read <= X"0";
rise_we <= '1';
re <= '1';
elsif (count = 2) then
count <= count + 1;
raddr_read <= X"1";
rise_we <= '1';
re <= '1';
elsif (count = 3) then
count <= count + 1;
raddr_read <= X"2";
rise_we <= '1';
re <= '1';
elsif (count = 4) then
count <= count + 1;
raddr_read <= X"3";
rise_we <= '1';
re <= '1';
elsif (count = 5) then
count <= count + 1;
raddr_read <= X"4";
rise_we <= '1';
re <= '1';
elsif (count = 6) then
count <= count + 1;
raddr_read <= X"5";
rise_we <= '1';
re <= '1';
elsif (count = 7) then
count <= count + 1;
raddr_read <= X"6";
rise_we <= '1';
re <= '1';
elsif (count = 8) then
count <= count + 1;
raddr_read <= X"7";
rise_we <= '1';
re <= '1';
elsif (count = 9) then
count <= count + 1;
raddr_read <= X"8";
rise_we <= '1';
re <= '1';
elsif (count = 10) then
count <= count + 1;
raddr_read <= X"9";
rise_we <= '1';
re <= '1';
elsif (count = 11) then
count <= count + 1;
raddr_read <= X"A";
rise_we <= '1';
re <= '1';
elsif (count = 12) then
count <= count + 1;
raddr_read <= X"B";
rise_we <= '1';
re <= '1';
elsif (count = 13) then
count <= count + 1;
raddr_read <= X"C";
rise_we <= '1';
re <= '1';
elsif (count = 14) then
count <= count + 1;
raddr_read <= X"D";
rise_we <= '1';
re <= '1';
elsif (count = 15) then
count <= count + 1;
raddr_read <= X"E";
rise_we <= '1';
re <= '1';
elsif (count = 16) then
count <= count + 1;
raddr_read <= X"F";
rise_we <= '1';
re <= '1';
elsif (count = 17) then
count <= 0;
return_happened <= '0';
return_handled <= '1';
reg_we <= '0';
reg_re <= '0';
re <= '0';
we <= '0';
rise_we <= '0';
end if;
end if;
end if;
elsif (falling_edge(clk)) then
if (interrupt_reg_we = '1') then
interrupt_reg <= interrupt_reg or interrupt_reg_data;
end if;
if ((interrupt_happened = '1') and (interrupt_handled = '0')) then
raddr1_out <= raddr1;
raddr2_out <= raddr2;
we <= rise_we;
end if;
if ((return_happened = '1') and (return_handled = '0')) then
raddr_write <= raddr_read;
reg_we <= rise_we;
end if;
end if;
end process;
process (interrupt_happened, interrupt_handled, return_happened, return_handled)
begin
interrupt_or_return_happened <= interrupt_happened or return_happened;
interrupt_or_return_handled <= interrupt_handled or return_handled;
end process;
end architecture;
| unlicense | 994afc2ef3fb4a0e5586f3d4e3b791bd | 0.541761 | 2.899902 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/sgmii_10_100_1000/ipcore_dir/temac_10_100_1000/example_design/axi_ipif/temac_10_100_1000_ipif_pkg.vhd | 2 | 8,714 | -- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: temac_10_100_1000_ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-------------------------------------------------------------------------------
-- Component Definitions
-------------------------------------------------------------------------------
component temac_10_100_1000_counter_f
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end component;
component temac_10_100_1000_pselect_f
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end component;
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function max2 (num1, num2 : integer) return integer;
function clog2(x : positive) return natural;
end ipif_pkg;
package body ipif_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
end package body ipif_pkg;
| gpl-3.0 | d5dbb9c6d72e5b40ed148d9963f34da4 | 0.517558 | 4.654915 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/EPROC_IN4.vhd | 2 | 4,172 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! E-link processor, 4bit input
entity EPROC_IN4 is
generic (do_generate : boolean := true);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (3 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN4;
architecture Behavioral of EPROC_IN4 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
--
signal DATA_OUT_direct : std_logic_vector (9 downto 0);
signal DATA_RDY_direct : std_logic;
---
signal DATA_OUT_8b10b_decoded : std_logic_vector (9 downto 0);
signal DATA_RDY_8b10b_decoded : std_logic;
---
signal DATA_OUT_HDLC_decoded : std_logic_vector (9 downto 0);
signal DATA_RDY_HDLC_decoded : std_logic;
---
signal DATA_RDY_sig : std_logic;
signal DATA_OUT_s : std_logic_vector (9 downto 0);
signal RESTART_sig, rst_case00, rst_case01 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
rst_case00 <= RESTART_sig or (ENCODING(1) or ENCODING(0));
--
EPROC_IN4_direct_inst: entity work.EPROC_IN4_direct
port map(
bitCLK => bitCLK,
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= RESTART_sig or (ENCODING(1) or (not ENCODING(0)));
--
EPROC_IN4_DEC8b10b_inst: entity work.EPROC_IN4_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_8b10b_decoded,
dataOUTrdy => DATA_RDY_8b10b_decoded,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
-- TBD
DATA_OUT_HDLC_decoded <= (others=>'0');
DATA_RDY_HDLC_decoded <= '0';
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_decoded,
data2 => DATA_OUT_HDLC_decoded,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_decoded,
data2 => DATA_RDY_HDLC_decoded,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 | 536beeb3a3117a265c25fe970396b04c | 0.469799 | 3.748428 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4088/EPROC_IN2.vhd | 1 | 4,503 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! E-link processor, 2bit input
entity EPROC_IN2 is
generic (do_generate : boolean := true);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (1 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN2;
architecture Behavioral of EPROC_IN2 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
--
signal DATA_OUT_direct : std_logic_vector (9 downto 0);
signal DATA_RDY_direct : std_logic;
---
signal DATA_OUT_8b10b_decoded : std_logic_vector (9 downto 0);
signal DATA_RDY_8b10b_decoded : std_logic;
---
signal DATA_OUT_HDLC_decoded : std_logic_vector (9 downto 0);
signal DATA_RDY_HDLC_decoded : std_logic;
---
signal DATA_RDY_sig : std_logic;
signal DATA_OUT_s : std_logic_vector (9 downto 0);
signal RESTART_sig, rst_case00, rst_case01, rst_case10 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
rst_case00 <= '0' when ((RESTART_sig = '0') and (ENCODING = "00")) else '1';
--
direct_data_case: entity work.EPROC_IN2_direct
port map(
bitCLK => bitCLK,
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= '0' when ((RESTART_sig = '0') and (ENCODING = "01")) else '1';
--
dec8b10b_case: entity work.EPROC_IN2_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_8b10b_decoded,
dataOUTrdy => DATA_RDY_8b10b_decoded,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
rst_case10 <= '0' when ((RESTART_sig = '0') and (ENCODING = "10")) else '1';
--
decHDLC_case: entity work.EPROC_IN2_HDLC
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case10,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_HDLC_decoded,
dataOUTrdy => DATA_RDY_HDLC_decoded
);
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_decoded,
data2 => DATA_OUT_HDLC_decoded,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_decoded,
data2 => DATA_RDY_HDLC_decoded,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 | 07c171227e4ed8a235953f14e589b30a | 0.470131 | 3.715347 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4088/BLOCK_WORD_COUNTER.vhd | 1 | 4,900 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: BLOCK_WORD_COUNTER
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.centralRouter_package.all;
--! counts block words, inserts block header
entity BLOCK_WORD_COUNTER is
Port (
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
RESTART : IN std_logic;
BW_RDY : in STD_LOGIC; -- Block Word Ready Enable
-------------
BLOCK_HEADER : in STD_LOGIC_VECTOR(31 downto 0);
-------------
EOB_MARK : out STD_LOGIC; -- End Of Block flag to send the trailer
BLOCK_HEADER_OUT : out STD_LOGIC_VECTOR(15 downto 0); --> sending block header
BLOCK_HEADER_OUT_RDY : out STD_LOGIC; --> sending block header
-------------
BLOCK_COUNT_RDY : out STD_LOGIC
);
end BLOCK_WORD_COUNTER;
architecture Behavioral of BLOCK_WORD_COUNTER is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
signal count_sig : STD_LOGIC_VECTOR (9 downto 0) := (others => '0');
signal seq_num : STD_LOGIC_VECTOR (4 downto 0) := (others => '0');
signal SOB_MARK0, SOB_MARK1, seqCNTcase, seqCNTtrig : STD_LOGIC;
signal SOB_MARK, EOB_MARK_sig, EOB_MARK_sig_clk1, blockCountRdy : STD_LOGIC := '0';
-- two first words are always sent in the beginning of a block transmittion
constant count_offset : STD_LOGIC_VECTOR (9 downto 0) := "0000000001"; --(others => '0');
begin
ce: process(CLK)
begin
if CLK'event and CLK = '1' then
if RESET = '1' or RESTART = '1' then
blockCountRdy <= '0';
elsif SOB_MARK1 = '1' then
blockCountRdy <= '1';
end if;
end if;
end process;
--
BLOCK_COUNT_RDY <= blockCountRdy;
--------------------------------------------------------------
-- counting block words, data partition
--------------------------------------------------------------
counter: process(CLK)
begin
if CLK'event and CLK = '1' then
if RESET = '1' then
count_sig <= (others => '0');
else
if EOB_MARK_sig = '1' or RESTART = '1' then
count_sig <= count_offset;
elsif BW_RDY = '1' then
count_sig <= count_sig + 1;
end if;
end if;
end if;
end process;
--------------------------------------------------------------
-- End Of Block trigger out for the
-- sub-chunk data manager to insert a trailer
--------------------------------------------------------------
EOB_MARK_sig <= '1' when (count_sig = BLOCK_WORDn) else '0'; -- there is one more space left, for the trailer
EOB_MARK <= EOB_MARK_sig;
--------------------------------------------------------------
-- Block Sequence counter, 5 bit
--------------------------------------------------------------
seqCNTcase <= EOB_MARK_sig or RESTART;
seqCNTtrig_pulse: pulse_pdxx_pwxx generic map(pd=>2,pw=>1) PORT MAP(CLK, seqCNTcase, seqCNTtrig);
--process(CLK)
--begin
-- if CLK'event and CLK = '1' then
-- EOB_MARK_sig_clk1 <= EOB_MARK_sig;
-- end if;
--end process;
--
scounter: process(CLK)
begin
if CLK'event and CLK = '1' then
if RESET = '1' then
seq_num <= (others => '0');
else
if seqCNTtrig = '1' then
seq_num <= seq_num + 1;
end if;
end if;
end if;
end process;
--------------------------------------------------------------
-- Start Of Block Mark to insert block header
--------------------------------------------------------------
SOB_MARK <= '1' when (count_sig = count_offset) else '0';
--------------------------------------------------------------
-- Start Of Block produces 2 triggers
-- to send 2 words, as header is 32bit
--------------------------------------------------------------
SOB_MARK0_PULSE: pulse_pdxx_pwxx PORT MAP(CLK, SOB_MARK, SOB_MARK0); -- FIFO WE to send word0
SOB_MARK1_PULSE: pulse_pdxx_pwxx GENERIC MAP(pd=>1,pw=>1) PORT MAP(CLK, SOB_MARK0, SOB_MARK1); -- FIFO WE to send word1
--
BLOCK_HEADER_OUT <= (seq_num & BLOCK_HEADER(10 downto 0)) when (SOB_MARK0 = '1') else
BLOCK_HEADER(31 downto 16) when (SOB_MARK1 = '1') else
(others => '0');
BLOCK_HEADER_OUT_RDY <= SOB_MARK0 or SOB_MARK1;
end Behavioral; | gpl-3.0 | b70055ac2a052beecb63ebd2fa79f706 | 0.474082 | 3.849175 | false | false | false | false |
HackLinux/ION | src/testbench/common/ion_tb_pkg.vhdl | 1 | 22,481 | --------------------------------------------------------------------------------
-- mips_tb_pkg.vhdl -- Functions and data for the simulation test benches.
--------------------------------------------------------------------------------
-- Most of this file deals with the 'simulation log': the CPU execution history
-- is logged to a text file for easy comparison to a similar log written by the
-- software simulator. This is meant as a debugging tool and is explained in
-- some detail in the project doc.
-- It is used as a verification tool at least while no other verification test
-- bench exists.
--------------------------------------------------------------------------------
-- FIXME Console logging code should be here too
--------------------------------------------------------------------------------
-- WARNING:
-- This package contains arguably the worst code of the project; in order
-- to expedite things, a number of trial-and-error hacks have been performed on
-- the code below. Mostly, the adjustment of the displayed PC.
-- This is just the kind of hdl you don't want prospective employers to see :)
-- At least the synthesis tools never get to see it, it's simulation only.
--
-- The problem is: each change in the CPU state is logged in a text line, in
-- which the address of the instruction that caused the change is included.
-- From outside the CPU it is not always trivial to find out what instruction
-- caused what change (pipeline delays, cache stalls, etc.).
-- I think the logging rules should be pretty stable now but I might have to
-- tweak them again as the cache implementation changes. Eventually I aim to
-- make this code fully independent of the cache implementation; it should
-- only depend on the cpu. I will do this step by step, as I do all the rest.
--------------------------------------------------------------------------------
-- NOTES (tagged in the code as @note1, etc.):
--
-- note1:
-- The multiplier LO/HI register change logging has been disabled (commented
-- out) until fixed (it fails in code sample 'adventure').
-- Please note it's the LOGGING that fails, not the instruction.
--
--------------------------------------------------------------------------------
library ieee,modelsim_lib;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
use modelsim_lib.util.all;
use std.textio.all;
use work.txt_util.all;
package ION_TB_PKG is
-- Address of the simulated UART; a single TxB register.
constant TB_UART_ADDRESS : t_word := X"FFFF8000";
constant TB_HW_IRQ_ADDRESS : t_word := X"FFFF8010";
constant TB_MSG_REG_ADDRESS : t_word := X"FFFF8018";
-- Maximum line size of for console output log. Lines longer than this will be
-- truncated.
constant CONSOLE_LOG_LINE_SIZE : integer := 1024*4;
type t_pc_queue is array(0 to 3) of t_word;
type t_log_info is record
rbank : t_rbank;
prev_rbank : t_rbank;
epc_reg : t_pc;
prev_epc : t_pc;
sr_bev_reg : std_logic;
cp0_status : std_logic_vector(15 downto 0);
prev_status : t_word;
p1_set_cp0 : std_logic;
p1_eret : std_logic;
pc_mtc0 : t_word;
pc_m : t_pc_queue;
reg_hi, reg_lo : t_word;
prev_hi, prev_lo : t_word;
mdiv_count_reg : std_logic_vector(5 downto 0);
prev_count_reg : std_logic_vector(5 downto 0);
data_rd_en : std_logic;
p1_rbank_we : std_logic;
--p1_cop2_load : std_logic;
code_rd_en : std_logic;
wr_be : std_logic_vector(3 downto 0);
present_data_wr_addr : t_word;
present_data_wr : t_word;
present_data_rd_addr : t_word;
present_code_rd_addr : t_word;
stall_pipeline : std_logic;
pending_data_rd_addr : t_word;
pending_data_wr_addr : t_word;
pending_data_wr_pc : t_word;
pending_data_wr : t_word;
pending_data_wr_we : std_logic_vector(3 downto 0);
pending_load_target : std_logic_vector(4 downto 0);
word_loaded : t_word;
--word_loaded_cop2 : t_word;
io_wr_data : t_word;
mdiv_address : t_word;
mdiv_pending : boolean;
exception : std_logic;
exception_prev : std_logic_vector(1 downto 0);
exception_pc : t_word;
data_rd_address : t_word;
load : std_logic;
--load_cop2 : std_logic;
read_pending : boolean;
lwc2_pending : boolean;
write_pending : boolean;
debug : t_word;
-- Meant to be connected to the CPU IRQ lines in the TB.
hw_irq : std_logic_vector(5 downto 0);
-- Console log line buffer --------------------------------------
con_line_buf : string(1 to CONSOLE_LOG_LINE_SIZE);
con_line_ix : integer;
-- Log trigger --------------------------------------------------
-- Enable logging after fetching from a given address -----------
log_trigger_address : t_word;
log_triggered : boolean;
end record t_log_info;
procedure log_pseudoconsole(
signal data : t_byte;
file con_file : TEXT;
signal info : inout t_log_info);
procedure log_cpu_activity(
signal clk : in std_logic;
signal reset : in std_logic;
signal done : inout std_logic;
base_entity : string;
cpu_name : string;
signal info : inout t_log_info;
signal_name : string;
trigger_addr : in t_word;
file l_file : TEXT;
file con_file : TEXT);
end package;
package body ION_TB_PKG is
procedure log_cpu_status(
signal info : inout t_log_info;
file l_file : TEXT;
file con_file : TEXT;
signal done : inout std_logic) is
variable i : integer;
variable ri : std_logic_vector(7 downto 0);
variable full_pc, temp, temp2 : t_word;
variable k : integer := 2;
variable log_trap_status : boolean := false;
begin
-- Trigger logging if the CPU fetches from trigger address
if (info.log_trigger_address = info.present_code_rd_addr) and
info.code_rd_en='1' then
info.log_triggered <= true;
assert 1=0
report "Log triggered by fetch from address 0x"& hstr(info.log_trigger_address)
severity note;
end if;
-- This is the address of the opcode that triggered the changed we're
-- about to log
full_pc := info.pc_m(k);
-- Log memory writes ----------------------------------------
if info.write_pending then
-- Regular S* opcodes AND SWC2 opcode.
if conv_integer(info.pending_data_wr_pc) <= conv_integer(full_pc) then
ri := X"0" & info.pending_data_wr_we;
temp := info.pending_data_wr;
if info.pending_data_wr_we(3)='0' then
temp := temp and X"00ffffff";
end if;
if info.pending_data_wr_we(2)='0' then
temp := temp and X"ff00ffff";
end if;
if info.pending_data_wr_we(1)='0' then
temp := temp and X"ffff00ff";
end if;
if info.pending_data_wr_we(0)='0' then
temp := temp and X"ffffff00";
end if;
if info.log_triggered then
print(l_file, "("& hstr(info.pending_data_wr_pc) &") ["&
hstr(info.pending_data_wr_addr) &"] |"&
hstr(ri)& "|="&
hstr(temp)& " WR" );
end if;
info.debug <= info.pending_data_wr_pc;
info.write_pending <= false;
end if;
end if;
-- Log register bank activity.
-- NOTE: in previous versions we used to do this only at the 1st cycle of
--- instructions, mistakenly. Reg changes need to be logged as soon as
-- they happen.
if true then --info.code_rd_en='1' then
-- Log register changes -------------------------------------
ri := X"00";
for i in 0 to 31 loop
if info.prev_rbank(i)/=info.rbank(i)
and info.prev_rbank(i)(0)/='U' then
if info.log_triggered then
print(l_file, "("& hstr(info.pc_m(k-0))& ") "&
"["& hstr(ri)& "]="& hstr(info.rbank(i)));
end if;
end if;
ri := ri + 1;
end loop;
-- Log aux register changes ---------------------------------
-- Mult/div module, register LO
if info.prev_lo /= info.reg_lo and info.prev_lo(0)/='U' then
-- Adjust opcode PC when LO came from the mul module
if info.mdiv_pending then
temp2 := info.mdiv_address;
info.mdiv_pending <= false;
else
temp2 := info.pc_m(k-2);
end if;
if info.log_triggered then
-- FIXME removed temporarily until fixed (@note1)
--print(l_file, "("& hstr(temp2)& ") [LO]="& hstr(info.reg_lo));
end if;
end if;
-- Mult/div module, register HI
if info.prev_hi /= info.reg_hi and info.prev_hi(0)/='U' then
-- Adjust opcode PC when HI came from the mul module
if info.mdiv_pending then
temp2 := info.mdiv_address;
info.mdiv_pending <= false;
else
temp2 := info.pc_m(k-2);
end if;
if info.log_triggered then
-- FIXME removed temporarily until fixed (@note1)
--print(l_file, "("& hstr(temp2)& ") [HI]="& hstr(info.reg_hi));
end if;
end if;
-- CP0, register EPC
if info.prev_epc /= info.epc_reg and info.epc_reg(31)/='U' then
temp := info.epc_reg & "00";
if info.log_triggered then
-- The instruction that caused the EP change is the last
-- recorded trap/syscall exception.
print(l_file, "("& hstr(info.exception_pc)& ") [EP]="& hstr(temp));
end if;
info.prev_epc <= info.epc_reg;
--log_trap_status := true;
else
--log_trap_status := false;
end if;
-- CP0, register SR
-- If SR changed by mtc0 instruction, get the mtc0 address
if (info.p1_set_cp0='1' or info.p1_eret='1') and info.cp0_status(4)='0' then
info.pc_mtc0 <= info.pc_m(k-1);
end if;
-- Build SR from separate CPU signals
temp := X"00" & "0" & info.sr_bev_reg & "000000" & info.cp0_status;
if info.prev_status /= temp and info.cp0_status(0)/='U' then
if info.log_triggered then
--if log_trap_status then
if info.exception_prev(1) = '1' then
-- The instruction that caused the SR change is the last
-- recorded trap/syscall exception.
-- @hack2
--print(l_file, "("& hstr(info.exception_pc)& ") [SR]="& hstr(temp));
temp2 := X"00000000";
print(l_file, "("& hstr(temp2)& ") [SR]="& hstr(temp));
else
-- The instruction that caused the change is mtc0
-- @hack2
--print(l_file, "("& hstr(info.pc_mtc0)& ") [SR]="& hstr(temp));
temp2 := X"00000000";
print(l_file, "("& hstr(temp2)& ") [SR]="& hstr(temp));
end if;
end if;
info.prev_status <= temp;
end if;
-- Save present cycle info to compare the next cycle --------
info.prev_rbank <= info.rbank;
info.prev_hi <= info.reg_hi;
info.prev_lo <= info.reg_lo;
end if;
info.exception_prev(1) <= info.exception_prev(0);
info.exception_prev(0) <= info.exception;
-- Update instruction address table only at the 1st cycle of each
-- instruction.
if info.code_rd_en='1' then
info.pc_m(3) <= info.pc_m(2);
info.pc_m(2) <= info.pc_m(1);
info.pc_m(1) <= info.pc_m(0);
info.pc_m(0) <= info.present_code_rd_addr;
end if;
-- When we see an exception, overwrite last element of fetch address queue
-- because we know it's not going to be executed and it would ruin the log.
if info.exception='1' then
-- Yet another crude hack, who's counting...
info.pc_m(0) <= X"BFC00180";
end if;
-- Log memory reads ------------------------------------------
if info.read_pending and info.log_triggered then
if info.load='1' and info.p1_rbank_we='1' and not info.lwc2_pending then
-- Log memory read cycle.
print(l_file, "("& hstr(info.pc_m(1)) &") ["&
hstr(info.pending_data_rd_addr) &"] <"&
"**"& ">="&
hstr(info.word_loaded)& " RD" );
-- Also log here the register change (here we have the PC info that
-- we will have lost if we wait to log it at the beginning of the
-- next log function invocation).
ri := X"00" + info.pending_load_target;
-- Log only if the target register actually changed...
if info.prev_rbank(conv_integer(ri)) /= info.word_loaded then
print(l_file, "("& hstr(info.pc_m(1))& ") "&
"["& hstr(ri)& "]="& hstr(info.word_loaded));
-- ...and prevent this change from appearing twice in the log
-- by setting the previous value to the new value.
info.prev_rbank(conv_integer(ri)) <= info.word_loaded;
end if;
info.read_pending <= false;
end if;
--if info.load_cop2='1' and info.stall_pipeline='0' and info.lwc2_pending then
-- -- Log LWC2 memory read cycle.
-- print(l_file, "("& hstr(info.pc_m(1)) &") ["&
-- hstr(info.pending_data_rd_addr) &"] <"&
-- "**"& ">="& hstr(info.word_loaded_cop2)& " RD" );
-- info.read_pending <= false;
-- info.lwc2_pending <= false;
--end if;
end if;
if info.exception='1' then
info.exception_pc <= info.pc_m(1);
end if;
if info.wr_be/="0000" then
--assert 1=0
--report "write"
--severity note;
info.write_pending <= true;
info.pending_data_wr_we <= info.wr_be;
info.pending_data_wr_addr <= info.present_data_wr_addr;
info.pending_data_wr_pc <= info.pc_m(k-1);
info.pending_data_wr <= info.present_data_wr;
end if;
if info.data_rd_en='1' then
info.read_pending <= true;
info.pending_data_rd_addr <= info.present_data_rd_addr;
--info.lwc2_pending <= (info.p1_cop2_load='1');
end if;
-- FIXME should use state register.
if info.mdiv_count_reg="100000" then
info.mdiv_address <= info.pc_m(1);
info.mdiv_pending <= true;
end if;
info.prev_count_reg <= info.mdiv_count_reg;
-- Monitor bus activity for access to simulated debug registers ------------
if info.wr_be /= "0000" then
if info.present_data_wr_addr = TB_UART_ADDRESS then
-- Simulated UART TX register: data comes from low byte.
log_pseudoconsole(info.io_wr_data(7 downto 0), con_file, info);
elsif info.present_data_wr_addr = TB_HW_IRQ_ADDRESS then
-- Simulated HW interrupt register.
info.hw_irq <= info.io_wr_data(5 downto 0);
elsif info.present_data_wr_addr = TB_MSG_REG_ADDRESS then
-- Message to test bench from SW. Data word will be the accumulated
-- number of errors.
-- Log the register write now (the simulation will be stopped) so
-- that the log matches the SWSIM log.
ri := X"00" + info.wr_be;
print(l_file, "("& hstr(info.pc_m(k-1)) &") ["&
hstr(info.present_data_wr_addr) &"] |"&
hstr(ri)& "|="&
hstr(info.io_wr_data)& " WR" );
-- Display success/failure message according to number of errors.
assert conv_integer(info.io_wr_data) /= 0
report "Test PASSED"
severity failure;
assert conv_integer(info.io_wr_data) = 0
report "Test FAILED ("& str(conv_integer(info.io_wr_data))&
" errors)."
severity failure;
done <= '1';
else
-- Ignore all other bus writes.
end if;
end if;
end procedure log_cpu_status;
procedure log_pseudoconsole(
signal data : t_byte;
file con_file : TEXT;
signal info : inout t_log_info
) is
variable uart_data : integer;
variable buf : line;
begin
uart_data := conv_integer(unsigned(data));
-- UART TX data goes to output after a bit of line-buffering
-- and editing
if uart_data = 10 then
-- CR received: print output string and clear it.
-- Print buffer to the log file...
print(con_file, info.con_line_buf(1 to info.con_line_ix));
-- ...to simulator console...
write(buf, info.con_line_buf(1 to info.con_line_ix));
writeline(output,buf);
-- ...and clear buffer.
info.con_line_ix <= 1;
for i in 1 to info.con_line_buf'high loop
info.con_line_buf(i) <= ' ';
end loop;
elsif uart_data = 13 then
-- ignore LF
else
-- append char to output string
if info.con_line_ix < info.con_line_buf'high then
info.con_line_buf(info.con_line_ix) <= character'val(uart_data);
info.con_line_ix <= info.con_line_ix + 1;
end if;
end if;
end procedure log_pseudoconsole;
procedure log_cpu_activity(
signal clk : in std_logic;
signal reset : in std_logic;
signal done : inout std_logic;
base_entity : string;
cpu_name : string;
signal info : inout t_log_info;
signal_name : string;
trigger_addr : in t_word;
file l_file : TEXT;
file con_file : TEXT) is
begin
init_signal_spy("/"&base_entity&"/"&cpu_name&"/p1_rbank", signal_name&".rbank", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/code_mosi_o.addr", signal_name&".present_code_rd_addr", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/stall_pipeline", signal_name&".stall_pipeline", 0);
--init_signal_spy("/"&base_entity&"/"&cpu_name&"/mult_div/hireg", signal_name&".reg_hi", 0);
--init_signal_spy("/"&base_entity&"/"&cpu_name&"/mult_div/loreg", signal_name&".reg_lo", 0);
--init_signal_spy("/"&base_entity&"/"&cpu_name&"/mult_div/count_reg", signal_name&".mdiv_count_reg", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/cop0/epc_reg", signal_name&".epc_reg", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/cop0/cp0_status", signal_name&".cp0_status", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/cop0/sr_reg.bev", signal_name&".sr_bev_reg", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/p1_set_cp0", signal_name&".p1_set_cp0", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/p1_eret", signal_name&".p1_eret", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/data_mosi_o.rd_en", signal_name&".data_rd_en", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/p1_rbank_we", signal_name&".p1_rbank_we", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/code_mosi_o.rd_en", signal_name&".code_rd_en", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/p2_do_load", signal_name&".load", 0);
--init_signal_spy("/"&base_entity&"/"&cpu_name&"/p1_cop2_load", signal_name&".load_cop2", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/data_mosi_o.addr", signal_name&".present_data_wr_addr", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/data_mosi_o.wr_data", signal_name&".present_data_wr", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/data_mosi_o.wr_be", signal_name&".wr_be", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/p2_data_word_rd", signal_name&".word_loaded", 0);
--init_signal_spy("/"&base_entity&"/"&cpu_name&"/data_rd", signal_name&".word_loaded_cop2", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/data_mosi_o.addr", signal_name&".present_data_rd_addr", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/p1_exception", signal_name&".exception", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/data_mosi_o.wr_data", signal_name&".io_wr_data", 0);
init_signal_spy("/"&base_entity&"/"&cpu_name&"/p2_load_target", signal_name&".pending_load_target", 0);
--init_signal_spy("/"&base_entity&"/"&cpu_name&"/p1_cop2_load", signal_name&".p1_cop2_load", 0);
while done='0' loop
wait until clk'event and clk='1';
if reset='1' then
-- FIXME should use real reset vector here
info.pc_m <= (others => X"00000000");
-- By default logging is DISABLED by triggering with an impossible
-- fetch address. Logging must be enabled from outside by
-- setting log_trigger_address to a suitable value.
info.log_trigger_address <= trigger_addr;
info.log_triggered <= false;
info.debug <= (others => '0');
info.hw_irq <= (others => '0');
info.con_line_ix <= 1; -- uart log line buffer is empty
else
log_cpu_status(info, l_file, con_file, done);
end if;
end loop;
end procedure log_cpu_activity;
end package body;
| lgpl-3.0 | 04b5e33b0cc97e63e5587f39d433ebf1 | 0.526178 | 3.786593 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/rsa_512/trunk/rtl/m_calc.vhd | 1 | 2,040 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:33:10 10/29/2009
-- Design Name:
-- Module Name: m_calc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity m_calc is
port(
clk : in std_logic;
reset : in std_logic;
ab : in std_logic_vector (15 downto 0);
t : in std_logic_vector (15 downto 0);
n_cons : in std_logic_vector (15 downto 0);
m : out std_logic_vector (15 downto 0);
mult_valid : in std_logic; -- indica que los datos de entrada son validos
m_valid : out std_logic); -- la m calculada es valida
end m_calc;
architecture Behavioral of m_calc is
signal sum_res, next_sum_res : std_logic_vector(15 downto 0);
signal mult_valid_1, mult_valid_2 : std_logic; --delay del valido a lo largo del calculo
signal mult : std_logic_vector(31 downto 0);
begin
mult <= sum_res * n_cons;
process(clk, reset)
begin
if(clk = '1' and clk'event) then
if(reset = '1') then
sum_res <= (others => '0');
mult_valid_1 <= '0';
mult_valid_2 <= '0';
else
sum_res <= next_sum_res;
mult_valid_1 <= mult_valid;
mult_valid_2 <= mult_valid_1;
end if;
end if;
end process;
process(ab, t, mult_valid_2)
begin
m <= mult(15 downto 0);
next_sum_res <= ab+t;
m_valid <= mult_valid_2;
end process;
end Behavioral;
| bsd-3-clause | e3d1aa89349986ae346898a9f70e3eb2 | 0.534314 | 3.511188 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/CDCC.vhd | 1 | 3,579 | ----------------------------------------------------------------------------------
-- Company: NTU ATHENS - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 19.12.2016 13:35:28
-- Design Name: Clock Domain Crossing Circuit
-- Module Name: CDCC - RTL
-- Project Name: CDCC
-- Target Devices: All Xilinx devices
-- Tool Versions: Vivado 2016.2
-- Description: This design instantiates a number of cascaded DFFs, which are used
-- to synchronize data that are crossing clock domains. The user must provide the
-- source clock and the destination clock, as well as the number of bits that are
-- to be synchronized.
--
-- Changelog:
-- 13.01.2017 Added ASYNC_REG attribute to the XDC constraints file, and also
-- added an extra layer of registers for the input signals. (Christos Bakalis)
-- 02.03.2017 Removed FDREs and added simple clocked processes. (Christos Bakalis)
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VComponents.all;
entity CDCC is
generic(
NUMBER_OF_BITS : integer := 8); -- number of signals to be synced
port(
clk_src : in std_logic; -- input clk (source clock)
clk_dst : in std_logic; -- input clk (dest clock)
data_in : in std_logic_vector(NUMBER_OF_BITS - 1 downto 0); -- data to be synced
data_out_s : out std_logic_vector(NUMBER_OF_BITS - 1 downto 0) -- synced data to clk_dst
);
end CDCC;
architecture RTL of CDCC is
signal data_in_reg : std_logic_vector(NUMBER_OF_BITS - 1 downto 0) := (others => '0');
signal data_sync_stage_0 : std_logic_vector(NUMBER_OF_BITS - 1 downto 0) := (others => '0');
signal data_out_s_int : std_logic_vector(NUMBER_OF_BITS - 1 downto 0) := (others => '0');
attribute ASYNC_REG : string;
attribute ASYNC_REG of data_sync_stage_0 : signal is "TRUE";
attribute ASYNC_REG of data_out_s_int : signal is "TRUE";
begin
-------------------------------------------------------
-- Register the input signals
-------------------------------------------------------
register_input_proc: process(clk_src)
begin
if(rising_edge(clk_src))then
data_in_reg <= data_in;
end if;
end process;
-------------------------------------------------------
-- Double synchronization
-------------------------------------------------------
meta_proc: process(clk_dst)
begin
if(rising_edge(clk_dst))then
data_sync_stage_0 <= data_in_reg;
data_out_s_int <= data_sync_stage_0;
end if;
end process;
data_out_s <= data_out_s_int;
end RTL; | gpl-3.0 | d4196d98bbc72323bee3a2419aa21a99 | 0.593462 | 3.98109 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_A/RSA_Security_Token_Keyboard_Version/ModMult.vhd | 1 | 6,187 | ----------------------------------------------------------------------
---- ----
---- Modular Multiplier ----
---- RSA Public Key Cryptography IP Core ----
---- ----
---- This file is part of the BasicRSA project ----
---- http://www.opencores.org/ ----
---- ----
---- To Do: ----
---- - Speed and efficiency improvements ----
---- - Possible revisions for good engineering/coding practices ----
---- ----
---- Author(s): ----
---- - Steven R. McQueen, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2003 Steven R. McQueen ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
--
-- This module implements the modular multiplier for the RSA Public Key Cypher. It expects
-- to receive a multiplicand on th MPAND bus, a multiplier on the MPLIER bus, and a modulus
-- on the MODULUS bus. The multiplier and multiplicand must have a value less than the modulus.
--
-- A Shift-and-Add algorithm is used in this module. For each bit of the multiplier, the
-- multiplicand value is shifted. For each '1' bit of the multiplier, the shifted multiplicand
-- value is added to the product. To ensure that the product is always expressed as a remainder
-- two subtractions are performed on the product, P2 = P1-modulus, and P3 = P1-(2*modulus).
-- The high-order bits of these results are used to determine whether P sould be copied from
-- P1, P2, or P3.
--
-- The operation ends when all '1' bits in the multiplier have been used.
--
-- Comments, questions and suggestions may be directed to the author at [email protected].
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity modmult is
Generic (MPWID: integer := 72);
Port ( mpand : in std_logic_vector(MPWID-1 downto 0);
mplier : in std_logic_vector(MPWID-1 downto 0);
modulus : in std_logic_vector(MPWID-1 downto 0);
product : out std_logic_vector(MPWID-1 downto 0);
clk : in std_logic;
ds : in std_logic;
reset : in std_logic;
ready : out std_logic);
end modmult;
architecture modmult1 of modmult is
signal mpreg: std_logic_vector(MPWID-1 downto 0);
signal mcreg, mcreg1, mcreg2: std_logic_vector(MPWID+1 downto 0);
signal modreg1, modreg2: std_logic_vector(MPWID+1 downto 0);
signal prodreg, prodreg1, prodreg2, prodreg3, prodreg4: std_logic_vector(MPWID+1 downto 0);
--signal count: integer;
signal modstate: std_logic_vector(1 downto 0);
signal first: std_logic;
begin
-- final result...
product <= prodreg4(MPWID-1 downto 0);
-- add shifted value if place bit is '1', copy original if place bit is '0'
with mpreg(0) select
prodreg1 <= prodreg + mcreg when '1',
prodreg when others;
-- subtract modulus and subtract modulus * 2.
prodreg2 <= prodreg1 - modreg1;
prodreg3 <= prodreg1 - modreg2;
-- negative results mean that we subtracted too much...
modstate <= prodreg3(mpwid+1) & prodreg2(mpwid+1);
-- select the correct modular result and copy it....
with modstate select
prodreg4 <= prodreg1 when "11",
prodreg2 when "10",
prodreg3 when others;
-- meanwhile, subtract the modulus from the shifted multiplicand...
mcreg1 <= mcreg - modreg1;
-- select the correct modular value and copy it.
with mcreg1(MPWID) select
mcreg2 <= mcreg when '1',
mcreg1 when others;
ready <= first;
combine: process (clk, first, ds, mpreg, reset) is
begin
if reset = '1' then
first <= '1';
elsif rising_edge(clk) then
if first = '1' then
-- First time through, set up registers to start multiplication procedure
-- Input values are sampled only once
if ds = '1' then
mpreg <= mplier;
mcreg <= "00" & mpand;
modreg1 <= "00" & modulus;
modreg2 <= '0' & modulus & '0';
prodreg <= (others => '0');
first <= '0';
end if;
else
-- when all bits have been shifted out of the multiplicand, operation is over
-- Note: this leads to at least one waste cycle per multiplication
if mpreg = 0 then
first <= '1';
else
-- shift the multiplicand left one bit
mcreg <= mcreg2(MPWID downto 0) & '0';
-- shift the multiplier right one bit
mpreg <= '0' & mpreg(MPWID-1 downto 1);
-- copy intermediate product
prodreg <= prodreg4;
end if;
end if;
end if;
end process combine;
end modmult1;
| bsd-3-clause | ce079e385dd5307957bcf5b9183b3bf5 | 0.598351 | 3.874139 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/CRresetManager.vhd | 3 | 2,733 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 09/11/2014
--! Module Name: CRresetManager
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library work, ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
--!
entity CRresetManager is
port (
clk40 : in std_logic;
rst_soft : in std_logic;
cr_rst : out std_logic;
cr_fifo_flush : out std_logic
);
end CRresetManager;
architecture Behavioral of CRresetManager is
--
constant fifoFLUSHcount_max : std_logic_vector (7 downto 0) := "10000000";
constant commonRSTcount_max : std_logic_vector (7 downto 0) := (others=>'1');
signal cr_rst_r,cr_rst_rr,fifoFLUSH : std_logic := '1';
signal rstTimerCount : std_logic_vector (7 downto 0) := (others=>'0');
--
begin
------------------------------------------------------------
-- clock domain crossing appreg_clk to clk40
------------------------------------------------------------
rst_cdc: process(clk40)
begin
if rising_edge(clk40) then
cr_rst_r <= rst_soft;
end if;
end process;
--
------------------------------------------------------------
--
------------------------------------------------------------
--
rstTimerCounter: process(clk40)
begin
if rising_edge(clk40) then
if cr_rst_r = '1' then
rstTimerCount <= (others=>'0');
else -- after cr_rst_r is deasserted:
if rstTimerCount = commonRSTcount_max then -- stop counting
rstTimerCount <= rstTimerCount; -- freese counter
else
rstTimerCount <= rstTimerCount + 1;
end if;
end if;
end if;
end process;
--
cr_rst_out: process(clk40)
begin
if rising_edge(clk40) then
if cr_rst_r = '1' then
cr_rst_rr <= '1';
else
if rstTimerCount = commonRSTcount_max then
cr_rst_rr <= '0';
else
cr_rst_rr <= cr_rst_rr;
end if;
end if;
end if;
end process;
--
crFifoFlush: process(clk40)
begin
if rising_edge(clk40) then
if cr_rst_r = '1' then
fifoFLUSH <= '1';
else
if rstTimerCount = fifoFLUSHcount_max then
fifoFLUSH <= '0';
else
fifoFLUSH <= fifoFLUSH;
end if;
end if;
end if;
end process;
--
cr_rst <= cr_rst_rr;
cr_fifo_flush <= fifoFLUSH;
--
end Behavioral;
| gpl-3.0 | a68be4f82156955c0ec67a2285bf14c2 | 0.461764 | 3.955137 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4088/EPROC_OUT2_HDLC.vhd | 1 | 8,426 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 24/01/2016
--! Module Name: EPROC_OUT2_HDLC
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE,work;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
use work.all;
--! HDLC data mode EPROC_OUT2 module
entity EPROC_OUT2_HDLC is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(1 downto 0)
);
end EPROC_OUT2_HDLC;
architecture Behavioral of EPROC_OUT2_HDLC is
----------------------------------
----------------------------------
component hdlc_bist_fifo
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(7 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(7 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
----------------------------------
----------------------------------
signal bit_cnt,bit_cnt_r : std_logic_vector (2 downto 0) := (others=>'1');
signal two_bit_out,EdataOUT_s : std_logic_vector (1 downto 0) := (others=>'1');
signal bit_cnt_ena,ce,ce_r,we,re_r,oe : std_logic := '0';
signal fifo_empty_r,isflag,isflag_r : std_logic := '1';
signal bitOUTclk,rst_fall,restart,bit_stuffing_case,re,ce_1st_clk,fifo_empty,bit_out,bit_out_r : std_logic;
signal byte_out : std_logic_vector (7 downto 0);
signal dataByte,byte_out_r : std_logic_vector (7 downto 0) := (others=>'1');
signal bit_out_sr : std_logic_vector (4 downto 0) := (others=>'1');
signal bit_out_sr_clk0 : std_logic_vector (4 downto 0);
signal send_out_trig : std_logic := '0';
begin
bitOUTclk <= bitCLKx2; -- 2bit output
-------------------------------------------------------------------------------------------
-- restarting data requests after reset fall
-------------------------------------------------------------------------------------------
rst_fall_pulse: entity work.pulse_fall_pw01 port map(bitOUTclk,rst,rst_fall);
restart_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>10,pw=>1) port map(bitOUTclk,rst_fall,restart);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if restart = '1' then
ce <= '1';
end if;
ce_r <= ce;
end if;
end process;
--
ce_1st_clk_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitOUTclk,ce,ce_1st_clk);
--
-------------------------------------------------------------------------------------------
-- input latching @ bitCLKx4
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if edataINrdy = '1' then
if edataIN(9 downto 8) = "11" then -- comma ('error')
dataByte <= (others=>'1');
we <= '0';
elsif edataIN(9 downto 8) = "01" or edataIN(9 downto 8) = "10" then -- eop/sop
dataByte <= HDLC_flag;
we <= '1';
else
dataByte <= edataIN(7 downto 0);
we <= '1';
end if;
else
we <= '0';
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- HDLC bit stuffing FIFO
-------------------------------------------------------------------------------------------
bit_stuffing_FIFO: hdlc_bist_fifo
port map (
rst => rst,
wr_clk => bitCLKx4,
rd_clk => bitOUTclk,
din => dataByte,
wr_en => we,
rd_en => re,
dout => byte_out,
full => open,
empty => fifo_empty
);
-------------------------------------------------------------------------------------------
-- bit counter: counting 8 bit to serialize the out while pausing for zero-bit stuffing
-------------------------------------------------------------------------------------------
bit_stuffing_case <= '1' when (bit_out_sr_clk0 = "11111" and isflag_r = '0') else '0';
bit_cnt_ena <= ce and (not bit_stuffing_case);
re <= '1' when (bit_cnt = "111" and bit_cnt_ena = '1') else '0';
getDataTrig_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitCLKx4,re,getDataTrig);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if ce = '1' then
if bit_cnt_ena = '1' then
bit_cnt <= bit_cnt + 1;
end if;
else
bit_cnt <= (others=>'1');
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- comma selector
-------------------------------------------------------------------------------------------
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
re_r <= re;
fifo_empty_r <= fifo_empty;
end if;
end process;
--
isflag <= '1' when (byte_out = HDLC_flag) else '0';
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if re_r = '1' then
if fifo_empty_r = '1' then
byte_out_r <= (others=>'1'); --error flag, not HDLC_flag!
isflag_r <= '1';
else
byte_out_r <= byte_out;
isflag_r <= isflag; -- no bit stuffing if flag is sent
end if;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- bit selector
-------------------------------------------------------------------------------------------
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
bit_cnt_r <= bit_cnt;
end if;
end process;
--
process(bit_cnt_r,byte_out_r)
begin
case (bit_cnt_r) is
when "000" => bit_out <= byte_out_r(0);
when "001" => bit_out <= byte_out_r(1);
when "010" => bit_out <= byte_out_r(2);
when "011" => bit_out <= byte_out_r(3);
when "100" => bit_out <= byte_out_r(4);
when "101" => bit_out <= byte_out_r(5);
when "110" => bit_out <= byte_out_r(6);
when "111" => bit_out <= byte_out_r(7);
when others =>
end case;
end process;
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
oe <= bit_cnt_ena;
end if;
end process;
--
bit_out_r <= (bit_out and oe) or (not ce_r);
bit_out_sr_clk0 <= bit_out_r & bit_out_sr(4 downto 1);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if rst = '1' then
bit_out_sr <= (others=>'1');
else
bit_out_sr <= bit_out_r & bit_out_sr(4 downto 1);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- sending out 2 bits @ bitCLK
-------------------------------------------------------------------------------------------
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
send_out_trig <= (not send_out_trig) and ce;
end if;
end process;
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if send_out_trig = '1' then
two_bit_out(1) <= bit_out_r;
else
two_bit_out(0) <= bit_out_r;
end if;
end if;
end process;
--
process(bitOUTclk,rst)
begin
if rst = '1' then
EdataOUT_s <= (others=>'1');
elsif bitOUTclk'event and bitOUTclk = '1' then
if send_out_trig = '0' and ce = '1' then
EdataOUT_s <= two_bit_out;
end if;
end if;
end process;
--
EdataOUT <= EdataOUT_s;
--
end Behavioral;
| gpl-3.0 | 6ecd5ac9c4dfeed7380295be7845fbcc | 0.441135 | 3.720088 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/sgmii_10_100_1000/ipcore_dir/temac_10_100_1000/example_design/temac_10_100_1000_block.vhd | 2 | 16,567 | --------------------------------------------------------------------------------
-- File : temac_10_100_1000_block.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the block level VHDL design for the Tri-Mode
-- Ethernet MAC Example Design.
--
-- This block level:
--
-- * instantiates all clock enable logic required to operate the
-- TEMAC and its example design;
--
-- * instantiates appropriate PHY interface module (GMII/MII/RGMII)
-- as required based on the user configuration;
--
-- Please refer to the Datasheet, Getting Started Guide, and
-- the Tri-Mode Ethernet MAC User Gude for further information.
--
--
-- -----------------------------------------|
-- | BLOCK LEVEL WRAPPER |
-- | |
-- | --------------------- |
-- | | ETHERNET MAC | |
-- | | CORE | |
-- | | | |
-- --|--->| Tx Tx |-------------->|
-- | | AXI PHY | |
-- | | I/F I/F | |
-- | | | |
-- | | | |
-- | | | |
-- | | Rx Rx | |
-- | | AXI PHY | |
-- <-|----| I/F I/F |<--------------|
-- | | | |
-- | --------------------- |
-- | |
-- | clock enable logic |
-- | |
-- -----------------------------------------|
--
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- The entity declaration for the block level example design.
--------------------------------------------------------------------------------
entity temac_10_100_1000_block is
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- Transmitter Interface
-------------------------------
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic;
tx_axis_mac_tready : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
clk_enable : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
-- Configuration Vector
-----------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0)
);
end temac_10_100_1000_block;
architecture wrapper of temac_10_100_1000_block is
-----------------------------------------------------------------------------
-- Component Declaration for TEMAC (the Tri-Mode EMAC core).
-----------------------------------------------------------------------------
component temac_10_100_1000
port(
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
gtx_clk : in std_logic;
clk_enable : in std_logic;
-- Receiver Interface
----------------------------
-- rx_axi_clk : in std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- rx_enable : in std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Transmitter Interface
-------------------------------
-- tx_axi_clk : in std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic_vector(0 downto 0);
tx_axis_mac_tready : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
-- tx_enable : in std_logic;
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- Current Speed Indication
---------------------------
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- Physical Interface of the core
--------------------------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
-- Configuration Vector
-----------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the synchronisation flip-flop pair
------------------------------------------------------------------------------
component temac_10_100_1000_sync_block
port (
clk : in std_logic; -- clock to be sync'ed to
data_in : in std_logic; -- Data to be 'synced'
data_out : out std_logic -- synced data
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component temac_10_100_1000_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- internal signals used in this block level wrapper.
------------------------------------------------------------------------------
attribute keep : string;
signal glbl_rst : std_logic;
signal gmii_tx_en_int : std_logic; -- Internal gmii_tx_en signal.
signal gmii_tx_er_int : std_logic; -- Internal gmii_tx_er signal.
signal gmii_txd_int : std_logic_vector(7 downto 0); -- Internal gmii_txd signal.
signal gmii_rx_dv_int : std_logic; -- gmii_rx_dv registered in IOBs.
signal gmii_rx_er_int : std_logic; -- gmii_rx_er registered in IOBs.
signal gmii_rxd_int : std_logic_vector(7 downto 0); -- gmii_rxd registered in IOBs.
signal txspeedis10100 : std_logic; -- MAC speed setting resampled on the transmitter clock
signal rxspeedis10100 : std_logic; -- MAC speed setting resampled on the receiver clock
signal tx_reset_int : std_logic; -- Synchronous reset in the MAC and rgmii Tx domain
signal rx_reset_int : std_logic; -- Synchronous reset in the MAC and rgmii Rx domain
signal rx_statistics_vector_int : std_logic_vector(27 downto 0);
signal rx_statistics_valid_int : std_logic;
signal tx_statistics_vector_int : std_logic_vector(31 downto 0);
signal tx_statistics_valid_int : std_logic;
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_addr : std_logic_vector(31 downto 0);
signal bus2ip_cs : std_logic;
signal bus2ip_rdce : std_logic;
signal bus2ip_wrce : std_logic;
signal bus2ip_data : std_logic_vector(31 downto 0);
signal ip2bus_data : std_logic_vector(31 downto 0);
signal ip2bus_wrack : std_logic;
signal ip2bus_rdack : std_logic;
signal ip2bus_error : std_logic;
signal tx_axis_mac_tuser_int : std_logic_vector(0 downto 0);
begin
-- assign outputs
rx_reset <= rx_reset_int;
tx_reset <= tx_reset_int;
glbl_rst <= not glbl_rstn;
rx_statistics_vector <= rx_statistics_vector_int;
rx_statistics_valid <= rx_statistics_valid_int;
tx_statistics_vector <= tx_statistics_vector_int;
tx_statistics_valid <= tx_statistics_valid_int;
gmii_tx_en <= gmii_tx_en_int;
gmii_tx_er <= gmii_tx_er_int;
gmii_txd <= gmii_txd_int;
gmii_rx_dv_int <= gmii_rx_dv;
gmii_rx_er_int <= gmii_rx_er;
gmii_rxd_int <= gmii_rxd;
-----------------------------------------------------------------------------
-- Instantiate the TEMAC core
-----------------------------------------------------------------------------
trimac_core : temac_10_100_1000
port map (
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
gtx_clk => gtx_clk,
clk_enable => clk_enable,
-- Receiver Interface
-- rx_axi_clk => gtx_clk,
rx_reset => rx_reset_int,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
-- Receiver Statistics
rx_statistics_vector => rx_statistics_vector_int,
rx_statistics_valid => rx_statistics_valid_int,
-- Transmitter Interface
-- tx_axi_clk => gtx_clk,
tx_reset => tx_reset_int,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser_int,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_ifg_delay => tx_ifg_delay,
-- tx_enable => clk_enable,
-- Transmitter Statistics
tx_statistics_vector => tx_statistics_vector_int,
tx_statistics_valid => tx_statistics_valid_int,
-- MAC Control Interface
pause_req => pause_req,
pause_val => pause_val,
-- Current Speed Indication
speedis100 => speedis100,
speedis10100 => speedis10100,
-- Physical Interface of the core
gmii_txd => gmii_txd_int,
gmii_tx_en => gmii_tx_en_int,
gmii_tx_er => gmii_tx_er_int,
gmii_rxd => gmii_rxd_int,
gmii_rx_dv => gmii_rx_dv_int,
gmii_rx_er => gmii_rx_er_int,
-- Configuration Vectors
rx_configuration_vector => rx_configuration_vector,
tx_configuration_vector => tx_configuration_vector);
tx_axis_mac_tuser_int(0) <= tx_axis_mac_tuser;
end wrapper;
| gpl-3.0 | e39b1dd7d4ab218e3682786eb9d42884 | 0.459226 | 4.434422 | false | false | false | false |
HackLinux/ION | src/rtl/cpu/ion_cop0.vhdl | 1 | 11,827 | --------------------------------------------------------------------------------
-- ION_COP0.vhdl -- COP0 for ION CPU.
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ION_COP0 is
generic(
-- Type of memory to be used for register bank in xilinx HW
XILINX_REGBANK : string := "distributed" -- {distributed|block}
);
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
CPU_I : in t_cop0_mosi;
CPU_O : out t_cop0_miso
);
end;
architecture rtl of ION_COP0 is
--------------------------------------------------------------------------------
-- CP0 registers and signals
-- Status register fields.
type t_sr_reg is record
bev : std_logic;
um : std_logic;
erl : std_logic;
exl : std_logic;
ie : std_logic;
im : std_logic_vector(7 downto 0);
end record;
-- Cause register fields.
type t_cause_reg is record
iv : std_logic;
ce : std_logic_vector(1 downto 0);
exc_code : std_logic_vector(4 downto 0);
fdci : std_logic;
bd : std_logic;
end record;
-- CP0[12]: status register implemented flags.
signal sr_reg : t_sr_reg;
-- CP0[13]: cause register implemented flags.
signal cause_reg : t_cause_reg;
signal cp0_status : std_logic_vector(15 downto 0);
signal cp0_we_delayed : std_logic;
signal cp0_index_delayed : std_logic_vector(4 downto 0);
signal cp0_wr_data_delayed: std_logic_vector(31 downto 0);
signal privileged : std_logic;
signal exception_stalled_reg : std_logic;
-- CP0[14]: EPC register (PC value saved at exceptions)
signal epc_reg : t_pc;
-- CP0[13]: 'Cause' register (cause and attributes of exception)
signal cp0_cause : t_word;
signal cause_exc_code : std_logic_vector(4 downto 0);
-- Exception vector or return address, registered for improved timing.
signal vector_reg : t_pc;
signal pc_load_en_reg : std_logic;
signal reset_delayed : std_logic_vector(1 downto 0);
begin
--#### COP0 Registers ##########################################################
-- Handle all registers in the same process: they all operate on the same
-- events anyway.
cp0_registers:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
-- Reset implemented SR flags.
sr_reg.bev <= '1';
sr_reg.um <= '0'; -- Kernel mode
sr_reg.erl <= '1'; -- Error level: Reset
sr_reg.exl <= '0'; -- Exception level: None
sr_reg.ie <= '0'; -- Interrupt Enable: No
sr_reg.im <= (others => '0');
-- Reset implemented CAUSE flags.
cause_reg.iv <= '0';
cause_reg.ce <= "00"; -- FIXME CP* traps merged with unimplemented opcode traps
cause_reg.exc_code <= "00000";
cause_reg.fdci <= '0'; -- FIXME Fast Debug not implemented.
cause_reg.bd <= '0';
-- As per the specs, not all registers have a RESET_I value.
else
if CPU_I.exception='1' then
cause_reg.exc_code <= cause_exc_code;
end if;
-- Everything is stalled if the pipeline is stalled, including
-- exception processing.
if CPU_I.stall='0' then
if (CPU_I.exception='1' or exception_stalled_reg='1') then
-- Exception: do all that needs to be done right here
-- If EXL is not raised already then...
if sr_reg.exl = '0' then
-- Save return address in EPC register...
epc_reg <= CPU_I.pc_restart;
-- ...raise EXL flag...
sr_reg.exl <= '1';
-- ...update cause register...
--cause_reg.exc_code <= cause_exc_code;
else
-- If ERL was already asserted, update no flags.
end if;
-- Update the BD flag for exceptions in delay slots
cause_reg.bd <= CPU_I.in_delay_slot;
elsif CPU_I.eret='1' and privileged='1' then
-- ERET: Return from exception.
-- Handle flags as per {FIXME add reference to vol.3 of the ARM}
if sr_reg.erl='1' then
sr_reg.erl <= '0';
else
sr_reg.exl <= '0';
end if;
elsif cp0_we_delayed='1' then
-- MTC0: load CP0[xx] with Rt.
if cp0_index_delayed = "01100" then
-- MTC0, Status register.
sr_reg.ie <= cp0_wr_data_delayed(0);
sr_reg.exl <= cp0_wr_data_delayed(1);
sr_reg.erl <= cp0_wr_data_delayed(2);
sr_reg.um <= cp0_wr_data_delayed(4);
sr_reg.bev <= cp0_wr_data_delayed(22);
sr_reg.im <= cp0_wr_data_delayed(15 downto 8);
elsif cp0_index_delayed = "01101" then
-- MTC0, Cause register.
cause_reg.iv <= cp0_wr_data_delayed(23);
end if;
end if;
end if;
end if;
end if;
end process cp0_registers;
cp0_registers_delayed_write:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
cp0_wr_data_delayed <= (others => '0');
cp0_we_delayed <= '0';
else
if CPU_I.pipeline_stalled='0' then
if CPU_I.we='1' and privileged='1' then
-- Flag the pending write...
cp0_we_delayed <= '1';
-- ...the write index...
cp0_index_delayed <= CPU_I.index;
-- ...and the write data.
cp0_wr_data_delayed <= CPU_I.data;
else
cp0_we_delayed <= '0';
end if;
end if;
end if;
end if;
end process cp0_registers_delayed_write;
-- FIXME see if this can be replaced with pipeline_stalled
reset_control2:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
exception_stalled_reg <= '0';
else
if CPU_I.exception='1' and CPU_I.stall='1' then
exception_stalled_reg <= '1';
elsif CPU_I.stall='0' then
exception_stalled_reg <= '0';
end if;
end if;
end if;
end process reset_control2;
-- We'll build a signal reset_delayed to keep track of the 2 cycles after
-- RESET_I deassertion; used to control pc_load_en_reg vector_reg.
reset_control:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
reset_delayed <= "11";
else
reset_delayed(1) <= reset_delayed(0);
reset_delayed(0) <= RESET_I;
end if;
end if;
end process reset_control;
vector_register_mux:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
vector_reg <= RESET_VECTOR(31 downto 2);
else
-- Keep the reset vector in the register until cycle 2 after
-- RESET_I deassertion, when it has already been loaded into PC...
if reset_delayed(0)='0' then
-- ...and then replace it with the IRQ vector.
vector_reg <= GENERAL_EXCEPTION_VECTOR(31 downto 2);
end if;
-- FIXME lots of COP0 stuff missing, in case you forget
end if;
end if;
end process vector_register_mux;
pc_load_en_reg <= reset_delayed(1) or CPU_I.exception or CPU_I.eret;
--#### Misc logic ##############################################################
-- Privileged status depends on several flags.
privileged <= not ((not sr_reg.erl) and (not sr_reg.exl) and sr_reg.um);
-- Decode exception cause; will be registered only if actually triggered so the
-- logic need to be valid only in that case.
cause_exc_code <=
"00000" when CPU_I.exception='0' else
"00000" when CPU_I.hw_irq='1' else
"01010" when CPU_I.unknown_opcode='1' else -- bad opcode ('reserved')
-- this triggers for mtc0/mfc0 in user mode too
"01011" when CPU_I.missing_cop='1' else -- CP* unavailable
"01000" when CPU_I.syscall='1' else -- SYSCALL
"01001"; -- BREAK
--#### CPU interface ###########################################################
CPU_O.kernel <= privileged;
CPU_O.pc_load_en <= pc_load_en_reg;
CPU_O.hw_irq_enable_mask <= sr_reg.im(7 downto 2);
CPU_O.global_irq_enable <= sr_reg.ie;
CPU_O.pc_load_value <= vector_reg when CPU_I.eret='0' else epc_reg; -- FIXME @hack5
--#### Read register mux #######################################################
-- Build up the READ registers from the bits and pieces that make them up.
cp0_status <=
sr_reg.im & "000" &
sr_reg.um & '0' & sr_reg.erl & sr_reg.exl & sr_reg.ie;
cp0_cause <= cause_reg.bd & '0' &
cause_reg.ce &
X"0" &
cause_reg.iv & '0' &
cause_reg.fdci & "00000" &
CPU_I.hw_irq_reg & "00" & '0' & -- HW IRQ flags straight from CPU.
cause_reg.exc_code & "00";
-- FIXME the mux should mask to zero for any unused reg index
with CPU_I.index select CPU_O.data <=
X"00" & "0" & sr_reg.bev & "000000" & cp0_status when "01100",
cp0_cause when "01101",
epc_reg & "00" when "01110",
epc_reg & "00" when others;
end architecture rtl;
| lgpl-3.0 | 00f8b7bb922ec3553f23a1065ecda30b | 0.487444 | 4.09664 | false | false | false | false |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/registerBank.vhd | 1 | 1,756 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
entity register_bank is
port(
clk,rst : in std_logic;
data : in std_logic_vector(7 downto 0);
write_addr : in std_logic_vector(3 downto 0);
read_addr1 : in std_logic_vector(3 downto 0);
read_addr2 : in std_logic_vector(3 downto 0);
w_enable : in std_logic;
r_enable : in std_logic;
data_out1 : out std_logic_vector(7 downto 0);
data_out2 : out std_logic_vector(7 downto 0));
end register_bank;
architecture mixed of register_bank is
type mem_type is array(15 downto 0) of std_logic_vector(7 downto 0);
signal mem_data : mem_type;
begin
process(clk, rst)
begin
--if (rst = '1') then
-- mem_data(0) <= X"30";
-- mem_data(1) <= X"40";
-- mem_data(2) <= X"50";
-- mem_data(3) <= X"60";
-- mem_data(4) <= X"70";
--end if;
if (rising_edge(clk) and (w_enable = '1')) then
mem_data(conv_integer(write_addr)) <= data;
report "Registerbank write addr: " & integer'image(conv_integer(write_addr)) & " data: " & integer'image(conv_integer(data));
end if;
if (falling_edge(clk) and (r_enable = '1')) then
data_out1 <= mem_data(conv_integer(read_addr1));
report "Registerbank read addr1: " & integer'image(conv_integer(read_addr1)) & " data: " & integer'image(conv_integer(mem_data(conv_integer(read_addr1))));
data_out2 <= mem_data(conv_integer(read_addr2));
report "Registerbank read addr2: " & integer'image(conv_integer(read_addr2)) & " data: " & integer'image(conv_integer(mem_data(conv_integer(read_addr2))));
end if;
end process;
end mixed;
| unlicense | 31012b3b8c205eabfad64a41622fe891 | 0.621298 | 2.976271 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/icmp_udp_mux.vhd | 1 | 2,771 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 02.04.2017
-- Design Name: ICMP UDP MUX
-- Module Name: icmp_udp_mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions: Vivado 2016.2
-- Description: This module instantiates a multiplexer that selects between data
-- input from UDP_TX or ICMP_TX and forwards the data to the IP layer.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.axi.all;
use work.ipv4_types.all;
entity icmp_udp_mux is
Port(
sel_icmp : in std_logic;
ip_tx_start_icmp : in std_logic;
ip_tx_icmp : in ipv4_tx_type;
ip_tx_start_udp : in std_logic;
ip_tx_udp : in ipv4_tx_type;
ip_tx_start_IP : out std_logic;
ip_tx_IP : out ipv4_tx_type
);
end icmp_udp_mux;
architecture Behavioral of icmp_udp_mux is
begin
ICMPudpMUX_proc: process(sel_icmp, ip_tx_start_icmp, ip_tx_icmp, ip_tx_start_udp, ip_tx_udp)
begin
case sel_icmp is
when '0' =>
ip_tx_start_IP <= ip_tx_start_udp;
ip_tx_IP <= ip_tx_udp;
when '1' =>
ip_tx_start_IP <= ip_tx_start_icmp;
ip_tx_IP <= ip_tx_icmp;
when others =>
ip_tx_start_IP <= '0';
ip_tx_IP.hdr.protocol <= (others => '0');
ip_tx_IP.hdr.data_length <= (others => '0');
ip_tx_IP.hdr.dst_ip_addr <= (others => '0');
ip_tx_IP.data.data_out <= (others => '0');
ip_tx_IP.data.data_out_valid <= '0';
ip_tx_IP.data.data_out_last <= '0';
end case;
end process;
end Behavioral; | gpl-3.0 | 3227bbafca06fcabf919de24efcc94d3 | 0.579935 | 3.425216 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/FIR_Filter/multichannel_fir_filter_imp.vhd | 1 | 1,805 | --------------------------------------------------------------------------------------------------
-- Multichannel FIR Filter Implementation
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
use work.multichannel_fir_filter_pkg.all;
--This module is a top-level for implementing the fir filter
entity multichannel_fir_filter_imp is
port( clk : in std_logic;
clk_2x : in std_logic;
rst : in std_logic;
x1 : in sig;
x2 : in sig;
y1 : out fir_sig;
y2 : out fir_sig);
end multichannel_fir_filter_imp;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture imp of multichannel_fir_filter_imp is
begin
uut : entity work.multichannel_fir_filter(behave)
generic map(h0 => LOW_PASS_41,
h1 => HIGH_PASS_41)
port map( clk => clk,
clk_2x => clk_2x,
rst => rst,
x1 => x1,
x2 => x2,
y1 => y1,
y2 => y2);
end imp;
| mit | 841ae823b1f2c4c2b4198eb2b8dc1cef | 0.309141 | 5.588235 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4088/EPROC_OUT2.vhd | 1 | 4,970 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT2
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee,work;
use ieee.std_logic_1164.all;
use work.all;
--! E-link processor, 2bit output
entity EPROC_OUT2 is
generic (do_generate : boolean := true);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
getDataTrig : out std_logic; -- @ bitCLKx4
ENCODING : in std_logic_vector (3 downto 0);
EDATA_OUT : out std_logic_vector (1 downto 0);
TTCin : in std_logic_vector (1 downto 0);
DATA_IN : in std_logic_vector (9 downto 0);
DATA_RDY : in std_logic
);
end EPROC_OUT2;
architecture Behavioral of EPROC_OUT2 is
constant zeros2bit : std_logic_vector (1 downto 0) := (others=>'0');
signal EdataOUT_ENC8b10b_case, EdataOUT_direct_case, EdataOUT_HDLC_case, EdataOUT_TTC0_case : std_logic_vector (1 downto 0);
signal rst_s, rst_case000, rst_case001, rst_case010, rst_case011 : std_logic;
signal getDataTrig_ENC8b10b_case, getDataTrig_direct_case, getDataTrig_HDLC_case, getDataTrig_TTC_case : std_logic;
begin
gen_enabled: if do_generate = true generate
rst_s <= rst or (not ENA);
-------------------------------------------------------------------------------------------
-- case 0: direct data, no delimeter...
-------------------------------------------------------------------------------------------
rst_case000 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "000")) else '1';
--
direct_case: entity work.EPROC_OUT2_direct
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case000,
getDataTrig => getDataTrig_direct_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_direct_case
);
--
-------------------------------------------------------------------------------------------
-- case 1: DEC8b10b
-------------------------------------------------------------------------------------------
rst_case001 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "001")) else '1';
--
ENC8b10b_case: entity work.EPROC_OUT2_ENC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case001,
getDataTrig => getDataTrig_ENC8b10b_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_ENC8b10b_case
);
--
-------------------------------------------------------------------------------------------
-- case 2: HDLC
-------------------------------------------------------------------------------------------
rst_case010 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "010")) else '1';
--
HDLC_case: entity work.EPROC_OUT2_HDLC
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case010,
getDataTrig => getDataTrig_HDLC_case, -- output, data request
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_HDLC_case
);
--
-------------------------------------------------------------------------------------------
-- case 3: TTC-0
-------------------------------------------------------------------------------------------
rst_case011 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "011")) else '1';
--
getDataTrig_TTC_case <= '0'; --'1' when (ENCODING(2 downto 0) = "011") else '0';
--
ttc_r: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst_case011 = '1' then
EdataOUT_TTC0_case <= zeros2bit;
else
EdataOUT_TTC0_case <= TTCin;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- output data and busy according to the encoding settings
-------------------------------------------------------------------------------------------
dataOUTmux: entity work.MUX4_Nbit
generic map (N=>2)
port map(
data0 => EdataOUT_direct_case,
data1 => EdataOUT_ENC8b10b_case,
data2 => EdataOUT_HDLC_case,
data3 => EdataOUT_TTC0_case,
sel => ENCODING(1 downto 0),
data_out => EDATA_OUT
);
--
getDataTrig <= ENA and (getDataTrig_TTC_case or getDataTrig_HDLC_case or getDataTrig_ENC8b10b_case or getDataTrig_direct_case);
--
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
EDATA_OUT <= (others=>'0');
getDataTrig <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 | a4306b97023b5b74519e322674912dae | 0.465191 | 3.885848 | false | false | false | false |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/hdl/ZynqDesign.vhd | 1 | 117,255 | library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_VG7ZLK is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_VG7ZLK;
architecture STRUCTURE of m00_couplers_imp_VG7ZLK is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(8 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(8 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(8 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(8 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(8 downto 0) <= S_AXI_araddr(8 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(8 downto 0) <= S_AXI_awaddr(8 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_180AW1Y is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_180AW1Y;
architecture STRUCTURE of m01_couplers_imp_180AW1Y is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(5 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(5 downto 0);
M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID;
M_AXI_awaddr(5 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(5 downto 0);
M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY;
M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID;
S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY;
m01_couplers_to_m01_couplers_ARADDR(5 downto 0) <= S_AXI_araddr(5 downto 0);
m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_couplers_AWADDR(5 downto 0) <= S_AXI_awaddr(5 downto 0);
m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready;
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready;
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready;
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_WNEIF9 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_WNEIF9;
architecture STRUCTURE of m02_couplers_imp_WNEIF9 is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(8 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(8 downto 0);
M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
M_AXI_awaddr(8 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(8 downto 0);
M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
m02_couplers_to_m02_couplers_ARADDR(8 downto 0) <= S_AXI_araddr(8 downto 0);
m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
m02_couplers_to_m02_couplers_AWADDR(8 downto 0) <= S_AXI_awaddr(8 downto 0);
m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_156Q4UY is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_156Q4UY;
architecture STRUCTURE of s00_couplers_imp_156Q4UY is
component ZynqDesign_auto_pc_3 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component ZynqDesign_auto_pc_3;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component ZynqDesign_auto_pc_3
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ZynqDesign_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC;
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end ZynqDesign_processing_system7_0_axi_periph_0;
architecture STRUCTURE of ZynqDesign_processing_system7_0_axi_periph_0 is
component ZynqDesign_xbar_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 )
);
end component ZynqDesign_xbar_1;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(8 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARADDR(8 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(8 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWADDR(8 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(5 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARADDR(5 downto 0);
M01_AXI_arvalid <= m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
M01_AXI_awaddr(5 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWADDR(5 downto 0);
M01_AXI_awvalid <= m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
M01_AXI_bready <= m01_couplers_to_processing_system7_0_axi_periph_BREADY;
M01_AXI_rready <= m01_couplers_to_processing_system7_0_axi_periph_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid <= m01_couplers_to_processing_system7_0_axi_periph_WVALID;
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1(0) <= M02_ARESETN(0);
M02_AXI_araddr(8 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_ARADDR(8 downto 0);
M02_AXI_arvalid <= m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
M02_AXI_awaddr(8 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_AWADDR(8 downto 0);
M02_AXI_awvalid <= m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
M02_AXI_bready <= m02_couplers_to_processing_system7_0_axi_periph_BREADY;
M02_AXI_rready <= m02_couplers_to_processing_system7_0_axi_periph_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M02_AXI_wvalid <= m02_couplers_to_processing_system7_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_processing_system7_0_axi_periph_ARREADY <= M01_AXI_arready;
m01_couplers_to_processing_system7_0_axi_periph_AWREADY <= M01_AXI_awready;
m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_BVALID <= M01_AXI_bvalid;
m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RVALID <= M01_AXI_rvalid;
m01_couplers_to_processing_system7_0_axi_periph_WREADY <= M01_AXI_wready;
m02_couplers_to_processing_system7_0_axi_periph_ARREADY <= M02_AXI_arready;
m02_couplers_to_processing_system7_0_axi_periph_AWREADY <= M02_AXI_awready;
m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_BVALID <= M02_AXI_bvalid;
m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RVALID <= M02_AXI_rvalid;
m02_couplers_to_processing_system7_0_axi_periph_WREADY <= M02_AXI_wready;
processing_system7_0_axi_periph_ACLK_net <= ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_VG7ZLK
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(8 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARADDR(8 downto 0),
M_AXI_arready(0) => m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(8 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWADDR(8 downto 0),
M_AXI_awready(0) => m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(8 downto 0) => xbar_to_m00_couplers_ARADDR(8 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(8 downto 0) => xbar_to_m00_couplers_AWADDR(8 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_180AW1Y
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(5 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARADDR(5 downto 0),
M_AXI_arready => m01_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m01_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(5 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWADDR(5 downto 0),
M_AXI_awready => m01_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m01_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m01_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m01_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(5 downto 0) => xbar_to_m01_couplers_ARADDR(37 downto 32),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(5 downto 0) => xbar_to_m01_couplers_AWADDR(37 downto 32),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_WNEIF9
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN(0) => M02_ARESETN_1(0),
M_AXI_araddr(8 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_ARADDR(8 downto 0),
M_AXI_arready => m02_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m02_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(8 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_AWADDR(8 downto 0),
M_AXI_awready => m02_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m02_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m02_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m02_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(8 downto 0) => xbar_to_m02_couplers_ARADDR(72 downto 64),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(8 downto 0) => xbar_to_m02_couplers_AWADDR(72 downto 64),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
s00_couplers: entity work.s00_couplers_imp_156Q4UY
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component ZynqDesign_xbar_1
port map (
aclk => processing_system7_0_axi_periph_ACLK_net,
aresetn => processing_system7_0_axi_periph_ARESETN_net(0),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(8 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(8 downto 0),
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(8 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(8 downto 0),
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ZynqDesign is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
leds_8bits_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
sws_8bits_tri_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of ZynqDesign : entity is "ZynqDesign,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLanguage=VHDL,numBlks=12,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=5,maxHierDepth=0,da_axi4_cnt=3,da_board_cnt=2,da_ps7_cnt=1}";
end ZynqDesign;
architecture STRUCTURE of ZynqDesign is
component ZynqDesign_processing_system7_0_0 is
port (
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component ZynqDesign_processing_system7_0_0;
component ZynqDesign_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component ZynqDesign_axi_gpio_0_0;
component ZynqDesign_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component ZynqDesign_rst_processing_system7_0_100M_0;
component ZynqDesign_zbroji_0_0 is
port (
s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID : in STD_LOGIC;
s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY : out STD_LOGIC;
s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID : in STD_LOGIC;
s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY : out STD_LOGIC;
s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID : out STD_LOGIC;
s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY : in STD_LOGIC;
s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID : in STD_LOGIC;
s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY : out STD_LOGIC;
s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID : out STD_LOGIC;
s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY : in STD_LOGIC;
interrupt : out STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC
);
end component ZynqDesign_zbroji_0_0;
component ZynqDesign_axi_gpio_1_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component ZynqDesign_axi_gpio_1_1;
signal GND_1 : STD_LOGIC;
signal VCC_1 : STD_LOGIC;
signal axi_gpio_0_GPIO_TRI_O : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_gpio_1_GPIO_TRI_I : STD_LOGIC_VECTOR ( 7 downto 0 );
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WVALID : STD_LOGIC;
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_zbroji_0_interrupt_UNCONNECTED : STD_LOGIC;
begin
axi_gpio_1_GPIO_TRI_I(7 downto 0) <= sws_8bits_tri_i(7 downto 0);
leds_8bits_tri_o(7 downto 0) <= axi_gpio_0_GPIO_TRI_O(7 downto 0);
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
VCC: unisim.vcomponents.VCC
port map (
P => VCC_1
);
axi_gpio_0: component ZynqDesign_axi_gpio_0_0
port map (
gpio_io_o(7 downto 0) => axi_gpio_0_GPIO_TRI_O(7 downto 0),
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(8 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
s_axi_bready => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID(0)
);
axi_gpio_1: component ZynqDesign_axi_gpio_1_1
port map (
gpio_io_i(7 downto 0) => axi_gpio_1_GPIO_TRI_I(7 downto 0),
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(8 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(8 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID,
s_axi_bready => processing_system7_0_axi_periph_M02_AXI_BREADY,
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_M02_AXI_RREADY,
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_M02_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID
);
processing_system7_0: component ZynqDesign_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => GND_1,
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.ZynqDesign_processing_system7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(8 downto 0),
M00_AXI_arready(0) => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
M00_AXI_awaddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(8 downto 0),
M00_AXI_awready(0) => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid(0) => processing_system7_0_axi_periph_M00_AXI_WVALID(0),
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(5 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(5 downto 0),
M01_AXI_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID,
M01_AXI_awaddr(5 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(5 downto 0),
M01_AXI_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID,
M01_AXI_bready => processing_system7_0_axi_periph_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => processing_system7_0_axi_periph_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID,
M02_ACLK => processing_system7_0_FCLK_CLK0,
M02_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M02_AXI_araddr(8 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(8 downto 0),
M02_AXI_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID,
M02_AXI_awaddr(8 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(8 downto 0),
M02_AXI_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID,
M02_AXI_bready => processing_system7_0_axi_periph_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => processing_system7_0_axi_periph_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => processing_system7_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_processing_system7_0_100M: component ZynqDesign_rst_processing_system7_0_100M_0
port map (
aux_reset_in => VCC_1,
bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => VCC_1,
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => GND_1,
mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
zbroji_0: component ZynqDesign_zbroji_0_0
port map (
aclk => processing_system7_0_FCLK_CLK0,
aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
interrupt => NLW_zbroji_0_interrupt_UNCONNECTED,
s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR(5 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(5 downto 0),
s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY => processing_system7_0_axi_periph_M01_AXI_ARREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID => processing_system7_0_axi_periph_M01_AXI_ARVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR(5 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(5 downto 0),
s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY => processing_system7_0_axi_periph_M01_AXI_AWREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID => processing_system7_0_axi_periph_M01_AXI_AWVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY => processing_system7_0_axi_periph_M01_AXI_BREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID => processing_system7_0_axi_periph_M01_AXI_BVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY => processing_system7_0_axi_periph_M01_AXI_RREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID => processing_system7_0_axi_periph_M01_AXI_RVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY => processing_system7_0_axi_periph_M01_AXI_WREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID => processing_system7_0_axi_periph_M01_AXI_WVALID
);
end STRUCTURE;
| mit | 82d58cfdd7b96e757932697714ef74da | 0.687382 | 2.820868 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/FIR_Filter/sparse_fir_filter.vhd | 1 | 4,158 | --------------------------------------------------------------------------------------------------
-- Sparse FIR Filter
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package sparse_fir_filter_pkg is
--FIR filter component declaration
component sparse_fir_filter is
generic( h : coefficient_array);
port( clk : in std_logic;
rst : in std_logic;
x : in sig;
y : out fir_sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
use work.sparse_fir_tap_pkg.all;
use work.fir_tap_pkg.all;
entity sparse_fir_filter is
generic( h : coefficient_array);
port( clk : in std_logic;
rst : in std_logic;
x : in sig;
y : out fir_sig);
end sparse_fir_filter;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of sparse_fir_filter is
signal x_chain : sig_array(h'range) := (others => (others => '0'));
signal running_sum : fir_sig_array(h'range) := (others => (others => '0'));
begin
filter_loop : for tap in h'low to h'high generate
begin
if_sparse_tap_gen : if h(tap) = ZERO_COEF generate
sparse_head_tap_gen : if tap = h'low generate
sparse_head_tap : sparse_fir_tap
port map(clk => clk,
rst => rst,
sig_in => x,
sig_out => x_chain(tap),
sum_in => (others => '0'),
sum_out => running_sum(tap));
end generate; --if head tap
sparse_tail_taps_gen : if tap /= h'low generate
sparse_tail_tap : sparse_fir_tap
port map(clk => clk,
rst => rst,
sig_in => x_chain(tap-1),
sig_out => x_chain(tap),
sum_in => running_sum(tap-1),
sum_out => running_sum(tap));
end generate; --if tail taps
end generate;
if_normal_tap_gen : if h(tap) /= ZERO_COEF generate
head_tap_gen : if tap = h'low generate
head_tap : fir_tap
port map(clk => clk,
rst => rst,
coef => h(tap),
sig_in => x,
sig_out => x_chain(tap),
sum_in => (others => '0'),
sum_out => running_sum(tap));
end generate; --if head tap
tail_taps_gen : if tap /= h'low generate
tail_tap : fir_tap
port map(clk => clk,
rst => rst,
coef => h(tap),
sig_in => x_chain(tap-1),
sig_out => x_chain(tap),
sum_in => running_sum(tap-1),
sum_out => running_sum(tap));
end generate; --if tail taps
end generate;
end generate;
--output end of the running sum
y <= running_sum(h'high);
end behave;
| mit | 76e30e41affcf2da110ba6b0725b2dfa | 0.354738 | 4.846154 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/FIR_Filter/lp_fir_filter_imp.vhd | 1 | 1,476 | --------------------------------------------------------------------------------------------------
-- Linear Phase FIR Filter Implementation
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
use work.lp_fir_filter_pkg.all;
--This module is a top-level for implementing the fir filter
entity lp_fir_filter_imp is
port( clk : in std_logic;
rst : in std_logic;
x : in sig;
y : out fir_sig);
end lp_fir_filter_imp;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture imp of lp_fir_filter_imp is
begin
--Instantiate unit under test
uut : entity work.lp_fir_filter(behave)
generic map(h => HIGH_PASS_101)
port map( clk => clk,
rst => rst,
x => x,
y => y);
end imp;
| mit | 29c13dc64698a994c7594bf0baedc450 | 0.313686 | 5.880478 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/centralRouter_package.vhd | 1 | 20,828 | --!-----------------------------------------------------------------------------
--! --
--! Weizmann Institute of Science --
--! Electronics & Data Acquisition Group --
--! --
--!-----------------------------------------------------------------------------
--!
--! unit name: centralRouter package
--!
--! author: [email protected]
--!
--! date: $10/12/2014 $: created
--!
--! version: $Rev 0 $:
--!
--! description: package file for the centralRouter interface
--!
--!-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package centralRouter_package is
-------------------------------------------------------------------
-- general use type definitions
-------------------------------------------------------------------
type array7_std_logic_vector_15 is array (0 to 6) of std_logic_vector(14 downto 0);
type array8_std_logic_vector_15 is array (0 to 7) of std_logic_vector(14 downto 0);
type array8_std_logic_vector_16 is array (0 to 7) of std_logic_vector(15 downto 0);
type array7_std_logic_vector_8 is array (0 to 6) of std_logic_vector(7 downto 0);
type array8_std_logic_vector_8 is array (0 to 7) of std_logic_vector(7 downto 0);
type array15_std_logic_vector_7 is array (0 to 14) of std_logic_vector(6 downto 0);
type array15_std_logic_vector_8 is array (0 to 14) of std_logic_vector(7 downto 0);
type array15_std_logic_vector_6 is array (0 to 14) of std_logic_vector(5 downto 0);
type array15_std_logic_vector_3 is array (0 to 14) of std_logic_vector(2 downto 0);
-------------------------------------------------------------------
-- EPROC internal type definitions
-------------------------------------------------------------------
type isk_2array_type is array (0 to 1) of std_logic_vector(1 downto 0); -- 2 words of 2bit
type word8b_2array_type is array (0 to 1) of std_logic_vector(7 downto 0); -- 2 words of 8bit
type word10b_2array_type is array (0 to 1) of std_logic_vector(9 downto 0); -- 2 words of 10bit
type word10b_2array_4array_type is array (0 to 3) of word10b_2array_type; -- 4 groups of {2 words of 10bit}, one group per alignment
--
type isk_4array_type is array (0 to 3) of std_logic_vector(1 downto 0); -- 4 words of 2bit
type word8b_4array_type is array (0 to 3) of std_logic_vector(7 downto 0); -- 4 words of 8bit
type word10b_4array_type is array (0 to 3) of std_logic_vector(9 downto 0); -- 4 words of 10bit
type word10b_4array_8array_type is array (0 to 7) of word10b_4array_type; -- 8 groups of {4 words of 10bit}, one group per alignment
--
type isk_8array_type is array (0 to 7) of std_logic_vector(1 downto 0); -- 8 words of 2bit
type word8b_8array_type is array (0 to 7) of std_logic_vector(7 downto 0); -- 8 words of 8bit
type word10b_8array_type is array (0 to 7) of std_logic_vector(9 downto 0); -- 8 words of 10bit
type word10b_8array_16array_type is array (0 to 15) of word10b_8array_type; -- 16 groups of {8 words of 10bit}, one group per alignment
-------------------------------------------------------------------
-- 7 and 5 entry arrays of 16 input lines, 16bit line per EGROUP
-------------------------------------------------------------------
type from1GBTdata_array_type is array (0 to 6) of std_logic_vector(15 downto 0);
type to1GBTdata_array_type is array (0 to 4) of std_logic_vector(15 downto 0);
type to1GBTdataNcode_array_type is array (0 to 4) of std_logic_vector(17 downto 0);
-------------------------------------------------------------------
-- N entry array of 16 output lines, 16bit output line per EGROUP
-------------------------------------------------------------------
type GBTdata_array_type is array ( NATURAL RANGE <>) of std_logic_vector(15 downto 0);
-------------------------------------------------------------------
-- GBT_NUM entry arrays
-------------------------------------------------------------------
type ic_data_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type cr_DIN_array_type is array ( NATURAL RANGE <>) of from1GBTdata_array_type;
type cr_DOUT_array_type is array ( NATURAL RANGE <>) of to1GBTdata_array_type;
type cr_8MSbs_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type cr_4bit_array_type is array ( NATURAL RANGE <>) of std_logic_vector(3 downto 0);
type TTCin_array_type is array ( NATURAL RANGE <>) of std_logic_vector(9 downto 0);
type DownFifoFull_mon_array_type is array ( NATURAL RANGE <>) of std_logic_vector(58 downto 0);
type fmch_monitor_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type busyOut_array_type is array ( NATURAL RANGE <>) of std_logic_vector(56 downto 0);
-------------------------------------------------------------------
-- Central Router configuration register arrays
-------------------------------------------------------------------
type crDownstreamConfig_type is array (0 to 7) of std_logic_vector(63 downto 0);
type crUpstreamConfig_type is array (0 to 5) of std_logic_vector(63 downto 0);
-------------------------------------------------------------------
-- 256-bit fifo out, one per GBT
-------------------------------------------------------------------
type d256b_array_type is array (natural range <>) of std_logic_vector(255 downto 0);
type txrx33b_type is array (natural range <>) of std_logic_vector(32 downto 0);
type GBTdm_data_array_type is array ( NATURAL RANGE <>) of std_logic_vector(255 downto 0);
type GBTdm_dsdata_array_type is array ( NATURAL RANGE <>) of std_logic_vector(31 downto 0);
type d32bit_array_type is array (0 to 255) of std_logic_vector(31 downto 0);
type d32bit_array32_type is array (0 to 31) of std_logic_vector(31 downto 0);
-------------------------------------------------------------------
-- 8 entry array of 8bit input
-------------------------------------------------------------------
type EPROC_FIFO_DIN_array_type is array (0 to 7) of std_logic_vector(7 downto 0);
type EPROC_FIFO_DIN_CODE_array_type is array (0 to 7) of std_logic_vector(1 downto 0);
-------------------------------------------------------------------
-- BLOCK size definition [in 16bit words]
-- chunck can span on part of a BLOCK or on several BLOCKs
-------------------------------------------------------------------
constant BLOCK_WORDn : std_logic_vector(9 downto 0) := "1000000000"; -- = 512 (number of 16-bit words in a block)
constant BLOCK_WORD32n : std_logic_vector(8 downto 0) := "100000000"; -- = 256 (number of 32-bit words in a block)
-------------------------------------------------------------------
-- 8b10b encoding / decoding parameters
-------------------------------------------------------------------
constant COMMAp : std_logic_vector (9 downto 0) := "0011111010"; -- +K.28.5
constant COMMAn : std_logic_vector (9 downto 0) := "1100000101"; -- -K.28.5
--- start-of-chunk and end-of-chunk characters
constant EOCp : std_logic_vector (9 downto 0) := "0011110110"; -- +K.28.6
constant EOCn : std_logic_vector (9 downto 0) := "1100001001"; -- -K.28.6
--constant SOCp : std_logic_vector (9 downto 0) := "0011111000"; -- +K.28.7 <---- discontinued
--constant SOCn : std_logic_vector (9 downto 0) := "1100000111"; -- -K.28.7 <---- discontinued
constant SOCp : std_logic_vector (9 downto 0) := "0011111001"; -- +K.28.1
constant SOCn : std_logic_vector (9 downto 0) := "1100000110"; -- -K.28.1
--- start-of-busy and end-of-busy characters
constant SOBp : std_logic_vector (9 downto 0) := "0011110101"; -- +K.28.2
constant SOBn : std_logic_vector (9 downto 0) := "1100001010"; -- -K.28.2
constant EOBp : std_logic_vector (9 downto 0) := "0011110011"; -- +K.28.3
constant EOBn : std_logic_vector (9 downto 0) := "1100001100"; -- -K.28.3
constant Kchar_comma : std_logic_vector (7 downto 0) := "10111100"; -- K28.5
constant Kchar_eop : std_logic_vector (7 downto 0) := "11011100"; -- K28.6
--constant Kchar_sop : std_logic_vector (7 downto 0) := "11111100"; -- K28.7 <---- discontinued
constant Kchar_sop : std_logic_vector (7 downto 0) := "00111100"; -- K28.1
constant Kchar_sob : std_logic_vector (7 downto 0) := "01011100"; -- K28.2
constant Kchar_eob : std_logic_vector (7 downto 0) := "01111100"; -- K28.3
-------------------------------------------------------------------
-- HDLC encoding / decoding parameters
-------------------------------------------------------------------
constant HDLC_flag : std_logic_vector(7 downto 0) := "01111110";
-------------------------------------------------------------------
-- TTC ToHost Data type
-------------------------------------------------------------------
type TTC_ToHost_data_type is record
FMT : std_logic_vector(7 downto 0); --byte0
LEN : std_logic_vector(7 downto 0); --byte1
reserved0 : std_logic_vector(3 downto 0); --byte2
BCID : std_logic_vector(11 downto 0); --byte2,3
XL1ID : std_logic_vector(7 downto 0); --byte4
L1ID : std_logic_vector(23 downto 0); --byte 5,6,7
orbit : std_logic_vector(31 downto 0); --byte 8,9,10,11
trigger_type : std_logic_vector(15 downto 0); --byte 12,13
reserved1 : std_logic_vector(15 downto 0); --byte 14,15
L0ID : std_logic_vector(31 downto 0); --byte 16,17,18,19
data_rdy : std_logic;
end record;
----------------------------------------------------------------------------------
-- 7 EGROUPs configuration parameters:
----------------------------------------------------------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- MATLAB generated parameters, consistent with GBT LINK DATA EMULATOR .coe files
--<< begin
--
-- 1. EPROC_ENA_bits 15 bit vector per EGROUP (15 EPROCs in one EGROUP)
-- [EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN4 EPROC_IN4 EPROC_IN4 EPROC_IN4 EPROC_IN8 EPROC_IN8 EPROC_IN16]
--
type EPROC_ENA_bits_array_type is array (0 to 7) of std_logic_vector(14 downto 0);
constant EPROC_ENA_bits_array : EPROC_ENA_bits_array_type :=(
"111111110000000",
"000000000000110",
"000000000000110",
"000011110000100",
"111111110000000",
"000000000000000",
"000000000000000",
"100000000000000");
--
-- 2. PATH_ENCODING, 16 bit vector per EGROUP (2 bits per PATH, 8 PATHs in one EGROUP)
-- for each of 8 output paths: "00"=non, "01"=8b10b, "10"=HDLC
--
type EPROC_ENCODING_array_type is array (0 to 7) of std_logic_vector(15 downto 0);
constant PATH_ENCODING_array : EPROC_ENCODING_array_type :=(
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"1000000000000000");
--
-- 3. Maximal valid CHUNK length for data truncation
-- per GBT channel, 3MSBs per Eproc type
--
constant MAX_CHUNK_LEN_array : std_logic_vector(11 downto 0) := "000000000000";
--<< end
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- 10 MS bits are used as an Egroup address in serial CR configuration mode (otherwise unused)
constant broadcast17bits : std_logic_vector(16 downto 0) := (16=>'1', 15=>'1', others=>'0');
constant broadcast21bits : std_logic_vector(20 downto 0) := (20=>'1', 19=>'1', others => '0');
-------------------------------------------------------------------
-- initial conf. constants for the case of {TTC_test_mode = false}
--
-- NOT a TTC test, initial configuration is generated using Matlab,
-- according to the selected options in a gui.
-------------------------------------------------------------------
constant CR_TH_EGROUP0_CTRL_C :std_logic_vector(63 downto 0) :=(
broadcast21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(0) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(0)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP1_CTRL_C :std_logic_vector(63 downto 0) :=(
broadcast21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(1) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(1)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP2_CTRL_C :std_logic_vector(63 downto 0) :=(
broadcast21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(2) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(2)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP3_CTRL_C :std_logic_vector(63 downto 0) :=(
broadcast21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(3) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(3)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP4_CTRL_C :std_logic_vector(63 downto 0) :=(
broadcast21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(4) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(4)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP5_CTRL_C :std_logic_vector(63 downto 0) :=(
broadcast21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(5) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(5)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP6_CTRL_C :std_logic_vector(63 downto 0) :=(
broadcast21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(6) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(6)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP7_CTRL_C :std_logic_vector(63 downto 0) :=(
broadcast21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(7) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(7)); -- 15 bit: (14 downto 0)
-------------------------------------------------------------------
-- Initial configuration of the from-host path:
-- matched the initial configuration of the to-host path
-- (and the initial contents of the GBT data emulators)
-- this allows for the loop-back test without reconfiguration
-------------------------------------------------------------------
constant CR_FH_EGROUP0_CTRL_C : std_logic_vector(63 downto 0) := (broadcast17bits &
"00" & PATH_ENCODING_array(0)(15 downto 14) &
"00" & PATH_ENCODING_array(0)(13 downto 12) &
"00" & PATH_ENCODING_array(0)(11 downto 10) &
"00" & PATH_ENCODING_array(0)(9 downto 8) &
"00" & PATH_ENCODING_array(0)(7 downto 6) &
"00" & PATH_ENCODING_array(0)(5 downto 4) &
"00" & PATH_ENCODING_array(0)(3 downto 2) &
"00" & PATH_ENCODING_array(0)(1 downto 0) &
EPROC_ENA_bits_array(0));
constant CR_FH_EGROUP1_CTRL_C : std_logic_vector(63 downto 0) := (broadcast17bits &
"00" & PATH_ENCODING_array(1)(15 downto 14) &
"00" & PATH_ENCODING_array(1)(13 downto 12) &
"00" & PATH_ENCODING_array(1)(11 downto 10) &
"00" & PATH_ENCODING_array(1)(9 downto 8) &
"00" & PATH_ENCODING_array(1)(7 downto 6) &
"00" & PATH_ENCODING_array(1)(5 downto 4) &
"00" & PATH_ENCODING_array(1)(3 downto 2) &
"00" & PATH_ENCODING_array(1)(1 downto 0) &
EPROC_ENA_bits_array(1));
constant CR_FH_EGROUP2_CTRL_C : std_logic_vector(63 downto 0) := (broadcast17bits &
"00" & PATH_ENCODING_array(2)(15 downto 14) &
"00" & PATH_ENCODING_array(2)(13 downto 12) &
"00" & PATH_ENCODING_array(2)(11 downto 10) &
"00" & PATH_ENCODING_array(2)(9 downto 8) &
"00" & PATH_ENCODING_array(2)(7 downto 6) &
"00" & PATH_ENCODING_array(2)(5 downto 4) &
"00" & PATH_ENCODING_array(2)(3 downto 2) &
"00" & PATH_ENCODING_array(2)(1 downto 0) &
EPROC_ENA_bits_array(2));
constant CR_FH_EGROUP3_CTRL_C : std_logic_vector(63 downto 0) := (broadcast17bits &
"00" & PATH_ENCODING_array(3)(15 downto 14) &
"00" & PATH_ENCODING_array(3)(13 downto 12) &
"00" & PATH_ENCODING_array(3)(11 downto 10) &
"00" & PATH_ENCODING_array(3)(9 downto 8) &
"00" & PATH_ENCODING_array(3)(7 downto 6) &
"00" & PATH_ENCODING_array(3)(5 downto 4) &
"00" & PATH_ENCODING_array(3)(3 downto 2) &
"00" & PATH_ENCODING_array(3)(1 downto 0) &
EPROC_ENA_bits_array(3));
constant CR_FH_EGROUP4_CTRL_C : std_logic_vector(63 downto 0) := (broadcast17bits &
"00" & PATH_ENCODING_array(4)(15 downto 14) &
"00" & PATH_ENCODING_array(4)(13 downto 12) &
"00" & PATH_ENCODING_array(4)(11 downto 10) &
"00" & PATH_ENCODING_array(4)(9 downto 8) &
"00" & PATH_ENCODING_array(4)(7 downto 6) &
"00" & PATH_ENCODING_array(4)(5 downto 4) &
"00" & PATH_ENCODING_array(4)(3 downto 2) &
"00" & PATH_ENCODING_array(4)(1 downto 0) &
EPROC_ENA_bits_array(4));
constant CR_FH_EGROUP5_CTRL_C : std_logic_vector(63 downto 0) := (broadcast17bits &
"00" & PATH_ENCODING_array(7)(15 downto 14) &
"00" & PATH_ENCODING_array(7)(13 downto 12) &
"00" & PATH_ENCODING_array(7)(11 downto 10) &
"00" & PATH_ENCODING_array(7)(9 downto 8) &
"00" & PATH_ENCODING_array(7)(7 downto 6) &
"00" & PATH_ENCODING_array(7)(5 downto 4) &
"00" & PATH_ENCODING_array(7)(3 downto 2) &
"00" & PATH_ENCODING_array(7)(1 downto 0) &
EPROC_ENA_bits_array(7));
-------------------------------------------------------------------
-- initial configuration of the from- and to-host paths
-- for the case of {TTC_test_mode = true}
-- TTC test mode, normal GBT mode only!
-- Central Router generic 'wideMode' has to be set false.
-- Congifuration of TTC-from-host matches
-- the direct-to-host congifuration.
-- Trom-Host is TTC, to-Host is direct data.
-------------------------------------------------------------------
--
-- egroup0: 8 x EPROCx2s. direct data: TTC-0 (2bit) [B-chan L1A]
constant CR_FH_EGROUP0_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast17bits & x"33333333" & "111111110000000"; -- TTC-0
constant CR_TH_EGROUP0_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast21bits & "000000000000" & "0000000000000000" & "111111110000000";
-- egroup1: 4 x EPROCx4s. direct data: TTC-1 (4bit) [B-chan ECR BCR L1A]
constant CR_FH_EGROUP1_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast17bits & x"03030303" & "000000001111000"; -- TTC-1
constant CR_TH_EGROUP1_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast21bits & "000000000000" & "0000000000000000" & "000000001111000";
-- egroup2: 4 x EPROCx4s. direct data: TTC-2 (4bit) [Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP2_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast17bits & x"04040404" & "000000001111000"; -- TTC-2
constant CR_TH_EGROUP2_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast21bits & "000000000000" & "0000000000000000" & "000000001111000";
-- egroup3: 2 x EPROCx8s. direct data: TTC-3 (8bit) [B-chan Brcst[5] Brcst[4] Brcst[3] Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP3_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast17bits & x"00300030" & "000000000000110"; -- TTC-3
constant CR_TH_EGROUP3_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast21bits & "000000000000" & "0000000000000000" & "000000000000110";
-- egroup4: 2 x EPROCx8s. direct data: TTC-4 (8bit) [Brcst[6] Brcst[5] Brcst[4] Brcst[3] Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP4_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast17bits & x"00400040" & "000000000000110"; -- TTC-4
constant CR_TH_EGROUP4_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast21bits & "000000000000" & "0000000000000000" & "000000000000110";
-- egroup7: 8 x EPROCx2s. direct data: TTC-0 (2bit) [B-chan L1A]
constant CR_FH_EGROUP5_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast17bits & x"33333333" & "111111110000000"; -- TTC-0
constant CR_TH_EGROUP7_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast21bits & "000000000000" & "0000000000000000" & "000000000000110";
--
--
constant CR_TH_EGROUP5_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := (others=>'0');
constant CR_TH_EGROUP6_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := (others=>'0');
--
--
end package centralRouter_package ;
| gpl-3.0 | 74236e964ee323077826ad294cc374f1 | 0.569714 | 3.40049 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/vmmFrontEnd.vhd | 1 | 127,977 | -------------------------------------------------------------------------------------
-- Company: NTUA - BNL
-- Engineer: Paris Moschovakos, Panagiotis Gkountoumis & Christos Bakalis
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Paris Moschovakos, Panagiotis Gkountoumis & Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 16.03.2016
-- Design Name: VMM boards firmware
-- Module Name: vmmFrontEnd.vhd
-- Project Name: Depends on the board
-- Target Devices: Artix7 xc7a200t-2fbg484 & xc7a200t-3fbg484
-- Tool Versions: Vivado 2017.2
--
-- Changelog:
-- 04.08.2016 Added the XADC Component and multiplexer to share fifo UDP Signals (Reid Pinkham)
-- 11.08.2016 Corrected the fifo resets to go through select_data (Reid Pinkham)
-- 16.09.2016 Added Dynamic IP configuration. (Lev Kurilenko)
-- 16.02.2017 Added new configuration component (udp_data_in_handler) (Christos Bakalis)
-- 27.02.2017 Changed main logic clock to 125MHz (Paris)
-- 10.03.2017 Added configurable CKTP/CKBC module. (Christos Bakalis)
-- 12.03.2017 Changed flow_fsm's primary cktp assertion to comply with cktp_gen
-- module. (Christos Bakalis)
-- 14.03.2017 Added register address/value configuration scheme. (Christos Bakalis)
-- 28.03.2017 Changes to accomodate to MMFE8 VMM3. (Christos Bakalis)
-- 31.03.2017 Added 2 CKBC readout mode (Paris)
-- 30.04.2017 Added vmm_readout_wrapper that contains level-0 readout mode besides
-- the pre-existing continuous mode. (Christos Bakalis)
-- 06.06.2017 Added ART readout handling (Paris)
-- 12.06.2017 Added support for MMFE1 board (Paris)
-- 21.06.2017 Added support for GPVMM board (Paris)
-- 22.06.2017 Added ODDRs for VMM clock forwarding optimization. (Christos Bakalis)
--
----------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity vmmFrontEnd is
port(
-- VMM signals
--------------------------------------
DATA0_1_P, DATA0_1_N : IN std_logic;
DATA0_2_P, DATA0_2_N : IN std_logic;
DATA0_3_P, DATA0_3_N : IN std_logic;
DATA0_4_P, DATA0_4_N : IN std_logic;
DATA0_5_P, DATA0_5_N : IN std_logic;
DATA0_6_P, DATA0_6_N : IN std_logic;
DATA0_7_P, DATA0_7_N : IN std_logic;
DATA0_8_P, DATA0_8_N : IN std_logic;
DATA1_1_P, DATA1_1_N : IN std_logic;
DATA1_2_P, DATA1_2_N : IN std_logic;
DATA1_3_P, DATA1_3_N : IN std_logic;
DATA1_4_P, DATA1_4_N : IN std_logic;
DATA1_5_P, DATA1_5_N : IN std_logic;
DATA1_6_P, DATA1_6_N : IN std_logic;
DATA1_7_P, DATA1_7_N : IN std_logic;
DATA1_8_P, DATA1_8_N : IN std_logic;
ART_1_P, ART_1_N : IN std_logic;
-- ART_2_P, ART_2_N : IN std_logic;
-- ART_3_P, ART_3_N : IN std_logic;
-- ART_4_P, ART_4_N : IN std_logic;
-- ART_5_P, ART_5_N : IN std_logic;
-- ART_6_P, ART_6_N : IN std_logic;
-- ART_7_P, ART_7_N : IN std_logic;
-- ART_8_P, ART_8_N : IN std_logic;
SDO_1 : IN std_logic;
SDO_2 : IN std_logic;
SDO_3 : IN std_logic;
SDO_4 : IN std_logic;
SDO_5 : IN std_logic;
SDO_6 : IN std_logic;
SDO_7 : IN std_logic;
SDO_8 : IN std_logic;
SDI_1 : OUT std_logic;
SDI_2 : OUT std_logic;
SDI_3 : OUT std_logic;
SDI_4 : OUT std_logic;
SDI_5 : OUT std_logic;
SDI_6 : OUT std_logic;
SDI_7 : OUT std_logic;
SDI_8 : OUT std_logic;
SCK_1 : OUT std_logic;
SCK_2 : OUT std_logic;
SCK_3 : OUT std_logic;
SCK_4 : OUT std_logic;
SCK_5 : OUT std_logic;
SCK_6 : OUT std_logic;
SCK_7 : OUT std_logic;
SCK_8 : OUT std_logic;
CS_1 : OUT std_logic;
CS_2 : OUT std_logic;
CS_3 : OUT std_logic;
CS_4 : OUT std_logic;
CS_5 : OUT std_logic;
CS_6 : OUT std_logic;
CS_7 : OUT std_logic;
CS_8 : OUT std_logic;
ENA_1_P, ENA_1_N : OUT std_logic;
ENA_2_P, ENA_2_N : OUT std_logic;
ENA_3_P, ENA_3_N : OUT std_logic;
ENA_4_P, ENA_4_N : OUT std_logic;
ENA_5_P, ENA_5_N : OUT std_logic;
ENA_6_P, ENA_6_N : OUT std_logic;
ENA_7_P, ENA_7_N : OUT std_logic;
ENA_8_P, ENA_8_N : OUT std_logic;
CKTK_1_P, CKTK_1_N : OUT std_logic;
CKTK_2_P, CKTK_2_N : OUT std_logic;
CKTK_3_P, CKTK_3_N : OUT std_logic;
CKTK_4_P, CKTK_4_N : OUT std_logic;
CKTK_5_P, CKTK_5_N : OUT std_logic;
CKTK_6_P, CKTK_6_N : OUT std_logic;
CKTK_7_P, CKTK_7_N : OUT std_logic;
CKTK_8_P, CKTK_8_N : OUT std_logic;
CKTP_1_P, CKTP_1_N : OUT std_logic;
CKTP_2_P, CKTP_2_N : OUT std_logic;
CKTP_3_P, CKTP_3_N : OUT std_logic;
CKTP_4_P, CKTP_4_N : OUT std_logic;
CKTP_5_P, CKTP_5_N : OUT std_logic;
CKTP_6_P, CKTP_6_N : OUT std_logic;
CKTP_7_P, CKTP_7_N : OUT std_logic;
CKTP_8_P, CKTP_8_N : OUT std_logic;
CKBC_1_P, CKBC_1_N : OUT std_logic;
CKBC_2_P, CKBC_2_N : OUT std_logic;
CKBC_3_P, CKBC_3_N : OUT std_logic;
CKBC_4_P, CKBC_4_N : OUT std_logic;
CKBC_5_P, CKBC_5_N : OUT std_logic;
CKBC_6_P, CKBC_6_N : OUT std_logic;
CKBC_7_P, CKBC_7_N : OUT std_logic;
CKBC_8_P, CKBC_8_N : OUT std_logic;
CKDT_1_P, CKDT_1_N : OUT std_logic;
CKDT_2_P, CKDT_2_N : OUT std_logic;
CKDT_3_P, CKDT_3_N : OUT std_logic;
CKDT_4_P, CKDT_4_N : OUT std_logic;
CKDT_5_P, CKDT_5_N : OUT std_logic;
CKDT_6_P, CKDT_6_N : OUT std_logic;
CKDT_7_P, CKDT_7_N : OUT std_logic;
CKDT_8_P, CKDT_8_N : OUT std_logic;
TKI_P, TKI_N : OUT std_logic;
TKO_P, TKO_N : IN std_logic;
CKART_1_P, CKART_1_N : OUT std_logic;
CKART_2_P, CKART_2_N : OUT std_logic;
CKART_3_P, CKART_3_N : OUT std_logic;
CKART_4_P, CKART_4_N : OUT std_logic;
CKART_5_P, CKART_5_N : OUT std_logic;
CKART_6_P, CKART_6_N : OUT std_logic;
CKART_7_P, CKART_7_N : OUT std_logic;
CKART_8_P, CKART_8_N : OUT std_logic;
SETT_P, SETT_N : OUT std_logic;
SETB_P, SETB_N : OUT std_logic;
CK6B_1_P, CK6B_1_N : OUT std_logic;
CK6B_2_P, CK6B_2_N : OUT std_logic;
CK6B_3_P, CK6B_3_N : OUT std_logic;
CK6B_4_P, CK6B_4_N : OUT std_logic;
CK6B_5_P, CK6B_5_N : OUT std_logic;
CK6B_6_P, CK6B_6_N : OUT std_logic;
CK6B_7_P, CK6B_7_N : OUT std_logic;
CK6B_8_P, CK6B_8_N : OUT std_logic;
-- ADDC ART CLK
--------------------------------------
CKART_ADDC_P : OUT std_logic;
CKART_ADDC_N : OUT std_logic;
-- MDT_446/MDT_MU2E Specific Pins
--------------------------------------
TRIGGER_OUT_P : OUT std_logic;
TRIGGER_OUT_N : OUT std_logic;
CH_TRIGGER : IN std_logic;
MO : OUT std_logic;
ART_OUT_P, ART_OUT_N : OUT std_logic;
-- xADC Interface
--------------------------------------
VP_0 : IN std_logic;
VN_0 : IN std_logic;
Vaux0_v_n : IN std_logic;
Vaux0_v_p : IN std_logic;
Vaux1_v_n : IN std_logic;
Vaux1_v_p : IN std_logic;
Vaux2_v_n : IN std_logic;
Vaux2_v_p : IN std_logic;
Vaux3_v_n : IN std_logic;
Vaux3_v_p : IN std_logic;
Vaux8_v_n : IN std_logic;
Vaux8_v_p : IN std_logic;
Vaux9_v_n : IN std_logic;
Vaux9_v_p : IN std_logic;
Vaux10_v_n : IN std_logic;
Vaux10_v_p : IN std_logic;
Vaux11_v_n : IN std_logic;
Vaux11_v_p : IN std_logic;
MuxAddr0 : OUT std_logic;
MuxAddr1 : OUT std_logic;
MuxAddr2 : OUT std_logic;
MuxAddr3_p : OUT std_logic;
MuxAddr3_n : OUT std_logic;
-- 200.0359MHz from bank 14
--------------------------------------
X_2V5_DIFF_CLK_P : IN std_logic;
X_2V5_DIFF_CLK_N : IN std_logic;
-- Tranceiver interface
--------------------------------------
gtrefclk_p : IN std_logic; -- Differential +ve of reference clock for tranceiver: 125MHz, very high quality
gtrefclk_n : IN std_logic; -- Differential -ve of reference clock for tranceiver: 125MHz, very high quality
txp : OUT std_logic; -- Differential +ve of serial transmission from PMA to PMD.
txn : OUT std_logic; -- Differential -ve of serial transmission from PMA to PMD.
rxp : IN std_logic; -- Differential +ve for serial reception from PMD to PMA.
rxn : IN std_logic; -- Differential -ve for serial reception from PMD to PMA.
phy_int : OUT std_logic;
phy_rstn_out : OUT std_logic;
-- AXI4SPI Flash Configuration
---------------------------------------
IO0_IO : INOUT std_logic;
IO1_IO : INOUT std_logic;
SS_IO : INOUT std_logic
);
end vmmFrontEnd;
architecture Behavioral of vmmFrontEnd is
-------------------------------------------------------------------
-- Global Settings
-------------------------------------------------------------------
-- Default IP and MAC address of the board
signal default_IP : std_logic_vector(31 downto 0) := x"c0a80002";
signal default_MAC : std_logic_vector(47 downto 0) := x"002320189223";
signal default_destIP : std_logic_vector(31 downto 0) := x"c0a80010";
-- Set to '1' for MMFE8 or '0' for 1-VMM boards
constant is_mmfe8 : std_logic := '0';
-- Set to '0' for continuous readout mode or '1' for L0 readout mode
constant vmmReadoutMode : std_logic := '1';
-- Set to '1' to enable the ART header
constant artEnabled : std_logic := '1';
-------------------------------------------------------------------
-- Transceiver, TEMAC, UDP_ICMP block
-------------------------------------------------------------------
-- clock generation signals for transceiver
signal gtrefclkp, gtrefclkn : std_logic; -- Route gtrefclk through an IBUFG.
signal txoutclk : std_logic; -- txoutclk from GT transceiver
signal resetdone : std_logic; -- To indicate that the GT transceiver has completed its reset cycle
signal mmcm_locked : std_logic; -- MMCM locked signal.
signal mmcm_reset : std_logic; -- MMCM reset signal.
signal clkfbout : std_logic; -- MMCM feedback clock
signal userclk : std_logic; -- 62.5MHz clock for GT transceiver Tx/Rx user clocks
signal userclk2 : std_logic; -- 125MHz clock for core reference clock.
-- PMA reset generation signals for tranceiver
signal pma_reset_pipe : std_logic_vector(3 downto 0); -- flip-flop pipeline for reset duration stretch
signal pma_reset : std_logic; -- Synchronous transcevier PMA reset
-- An independent clock source used as the reference clock for an
-- IDELAYCTRL (if present) and for the main GT transceiver reset logic.
signal independent_clock_bufg: std_logic;
-- clock generation signals for SGMII clock
signal sgmii_clk_r : std_logic; -- Clock to client MAC (125MHz, 12.5MHz or 1.25MHz) (to rising edge DDR).
signal sgmii_clk_f : std_logic; -- Clock to client MAC (125MHz, 12.5MHz or 1.25MHz) (to falling edge DDR).
-- GMII signals
signal gmii_isolate : std_logic; -- Internal gmii_isolate signal.
signal gmii_txd_int : std_logic_vector(7 downto 0); -- Internal gmii_txd signal (between core and SGMII adaptation module).
signal gmii_tx_en_int : std_logic; -- Internal gmii_tx_en signal (between core and SGMII adaptation module).
signal gmii_tx_er_int : std_logic; -- Internal gmii_tx_er signal (between core and SGMII adaptation module).
signal gmii_rxd_int : std_logic_vector(7 downto 0); -- Internal gmii_rxd signal (between core and SGMII adaptation module).
signal gmii_rx_dv_int : std_logic; -- Internal gmii_rx_dv signal (between core and SGMII adaptation module).
signal gmii_rx_er_int : std_logic; -- Internal gmii_rx_er signal (between core and SGMII adaptation module).
signal phy_rstn : std_logic := '0';
-- Extra registers to ease IOB placement
signal status_vector_int : std_logic_vector(15 downto 0);
signal gmii_txd_emac : std_logic_vector(7 downto 0);
signal gmii_tx_en_emac : std_logic;
signal gmii_tx_er_emac : std_logic;
signal gmii_rxd_emac : std_logic_vector(7 downto 0);
signal gmii_rx_dv_emac : std_logic;
signal gmii_rx_er_emac : std_logic;
signal speed_is_10_100 : std_logic;
signal speed_is_100 : std_logic;
signal tx_axis_mac_tready_int : std_logic;
signal rx_axis_mac_tuser_int : std_logic;
signal rx_axis_mac_tlast_int : std_logic;
signal rx_axis_mac_tdata_int : std_logic_vector(7 downto 0);
signal rx_axis_mac_tvalid_int : std_logic;
signal local_gtx_reset : std_logic;
signal rx_reset : std_logic;
signal tx_reset : std_logic;
signal gtx_pre_resetn : std_logic := '0';
signal tx_axis_mac_tdata_int : std_logic_vector(7 downto 0);
signal tx_axis_mac_tvalid_int : std_logic;
signal tx_axis_mac_tlast_int : std_logic;
signal gtx_resetn : std_logic;
signal glbl_rstn : std_logic := '1';
signal glbl_rst_i : std_logic := '0';
signal gtx_clk_reset_int : std_logic;
signal an_restart_config_int : std_logic;
signal rx_axis_mac_tready_int : std_logic;
signal rx_configuration_vector_int : std_logic_vector(79 downto 0);
signal tx_configuration_vector_int : std_logic_vector(79 downto 0);
signal vector_resetn : std_logic := '0';
signal vector_pre_resetn : std_logic := '0';
signal vector_reset_int : std_logic;
signal clk_enable_int : std_logic;
signal sgmii_clk_int_oddr : std_logic;
signal udp_txi_int : udp_tx_type;
signal control : udp_control_type;
signal udp_rx_int : udp_rx_type;
signal ip_rx_hdr_int : ipv4_rx_header_type;
signal udp_tx_data_out_ready_int : std_logic;
signal udp_tx_start_int : std_logic;
signal icmp_rx_start : std_logic;
signal icmp_rxo : icmp_rx_type;
signal user_data_out_i : std_logic_vector(15 downto 0);
signal end_packet_i : std_logic := '0';
signal we_conf_int : std_logic := '0';
signal packet_length_int : std_logic_vector(11 downto 0);
signal daq_data_out_i : std_logic_vector(15 downto 0);
signal daq_wr_en_i : std_logic := '0';
signal start_conf_proc_int : std_logic := '0';
-------------------------------------------------
-- VMM/FPGA Configuration Signals
-------------------------------------------------
signal vmm_sdo_vec_i : std_logic_vector(8 downto 1) := (others => '0');
signal vmm_cs_all : std_logic := '0';
signal vmm_sck_all : std_logic := '0';
signal vmm_sdi_all : std_logic := '0';
signal vmm_bitmask : std_logic_vector(7 downto 0) := "11111111";
signal vmm_bitmask_1VMM : std_logic_vector(7 downto 0) := "11111111";
signal vmm_bitmask_8VMM : std_logic_vector(7 downto 0) := "11111111";
signal sel_cs : std_logic_vector(1 downto 0) := (others => '0');
signal VMM_CS_i : std_logic := '0';
signal vmm_cs_vec_obuf : std_logic_vector(8 downto 1) := (others => '0');
signal vmm_sck_vec_obuf : std_logic_vector(8 downto 1) := (others => '0');
signal vmm_ena_vec_obuf : std_logic_vector(8 downto 1) := (others => '0');
signal vmm_sdi_vec_obuf : std_logic_vector(8 downto 1) := (others => '0');
signal vmm_ckbc_vec : std_logic_vector(8 downto 1) := (others => '0');
signal vmm_cktp_vec : std_logic_vector(8 downto 1) := (others => '0');
signal ckart_vec : std_logic_vector(9 downto 1) := (others => '0');
signal conf_di_i : std_logic := '0';
signal conf_ena_i : std_logic := '0';
signal conf_wen_i : std_logic := '0';
signal cnt_vmm : integer range 0 to 7 := 0;
signal tko_i : std_logic;
signal MO_i : std_logic := 'Z';
signal end_packet_conf_int: std_logic := '0';
signal end_packet_daq_int : std_logic := '0';
signal is_state : std_logic_vector(3 downto 0) := "1010";
signal latency_conf : std_logic_vector(15 downto 0) := x"0000";
signal art_cnt2 : integer range 0 to 127 := 0;
signal art2 : std_logic := '0';
signal reset_FF : std_logic := '0';
signal wait_cnt : unsigned(7 downto 0) := (others => '0');
signal vmm_id_rdy : std_logic := '0';
signal vmm_conf : std_logic := '0';
signal newIP_rdy : std_logic := '0';
signal xadc_conf_rdy : std_logic := '0';
signal daq_on : std_logic := '0';
signal vmmConf_done : std_logic := '0';
signal flash_busy : std_logic := '0';
signal inhibit_conf : std_logic := '0';
signal conf_state : std_logic_vector(2 downto 0) := b"000";
signal serial_number : std_logic_vector(31 downto 0) := x"00000000";
signal packet_len_conf : std_logic_vector(11 downto 0) := x"000";
signal fpga_rst_i : std_logic := '0';
signal reply_done : std_logic := '0';
signal reply_enable : std_logic := '0';
signal glbl_fifo_init : std_logic := '1'; --synced@200Mhz
signal glbl_fifo_init_s0 : std_logic := '1';
signal glbl_fifo_init_s1 : std_logic := '1'; --synced@125Mhz
-------------------------------------------------
-- VMM Signals
-------------------------------------------------
signal cktk_out_vec : std_logic_vector(8 downto 1);
signal ckdt_out_vec : std_logic_vector(8 downto 1);
signal data0_in_vec : std_logic_vector(8 downto 1);
signal data1_in_vec : std_logic_vector(8 downto 1);
signal art_in_vec : std_logic_vector(8 downto 1) := (others => '0');
signal vmm_tki : std_logic := '0';
signal vmm_cktp_primary : std_logic := '0';
signal CKTP_glbl : std_logic := '0';
signal vmm_ena_all : std_logic := '0';
-------------------------------------------------
-- Readout Signals
-------------------------------------------------
signal daq_enable_i : std_logic := '0';
signal daqFIFO_wr_en_i : std_logic := '0';
signal daqFIFO_din_i : std_logic_vector(15 downto 0);
signal vmmWordReady_i : std_logic := '0';
signal vmmWord_i : std_logic_vector(15 downto 0);
signal vmmEventDone_i : std_logic := '0';
signal daqFIFO_reset : std_logic := '0';
signal daq_vmm_ena_wen_enable : std_logic_vector(8 downto 1) := (others => '0');
signal daq_cktk_out_enable : std_logic_vector(8 downto 1) := (others => '0');
signal linkHealth_bmsk : std_logic_vector(8 downto 1) := (others => '0');
signal UDPDone : std_logic;
signal ckbc_enable : std_logic := '0';
signal cktp_enable : std_logic := '0';
signal dt_state : std_logic_vector(3 downto 0) := b"0000";
signal dt_cntr_st : std_logic_vector(3 downto 0) := b"0000";
signal rst_l0_buff : std_logic := '0';
signal rst_l0_buff_flow : std_logic := '1';
signal rst_l0_pf : std_logic := '0';
signal level_0 : std_logic := '0';
signal daq_on_inhib : std_logic := '1';
signal CKDT_glbl : std_logic := '0';
signal vmm_ckdt_enable : std_logic_vector(8 downto 1) := (others => '0');
-------------------------------------------------
-- Trigger Signals
-------------------------------------------------
signal tren : std_logic := '0';
signal tr_hold : std_logic := '0';
signal trmode : std_logic := '0';
signal ext_trigger_in : std_logic := '0';
signal tr_reset : std_logic := '0';
signal tr_out_i : std_logic;
signal trig_mode_int : std_logic := '0';
signal CH_TRIGGER_i : std_logic := '0';
signal request2ckbc : std_logic := '0';
signal trraw_synced125_i : std_logic := '0';
signal accept_wr : std_logic := '0';
signal vmmArtData : std_logic_vector(5 downto 0) := (others => '0');
signal vmmArtReady : std_logic := '0';
-------------------------------------------------
-- Event Timing & Soft Reset
-------------------------------------------------
signal etr_vmm_wen_vec : std_logic_vector(8 downto 1) := ( others => '0' );
signal etr_vmm_ena_vec : std_logic_vector(8 downto 1) := ( others => '0' );
signal etr_reset_latched: std_logic;
signal glBCID_i : std_logic_vector(11 downto 0) := ( others => '0' );
signal state_rst_etr_i : std_logic_vector(2 downto 0) := ( others => '0' );
signal rst_etr_i : std_logic;
signal rst_done_etr_i : std_logic;
-------------------------------------------------
-- Packet Formation Signals
-------------------------------------------------
signal pf_newCycle : std_logic;
signal pf_packLen : std_logic_vector(11 downto 0);
signal pf_trigVmmRo : std_logic := '0';
signal pf_vmmIdRo : std_logic_vector(2 downto 0) := b"000";
signal pf_rst_flow : std_logic := '0';
signal rst_vmm : std_logic := '0';
signal pf_rst_FIFO : std_logic := '0';
signal pfBusy_i : std_logic := '0';
signal pf_dbg_st : std_logic_vector(4 downto 0) := b"00000";
signal rd_ena_buff : std_logic := '0';
signal pf_rst_final : std_logic := '0';
-------------------------------------------------
-- FIFO2UDP Signals
-------------------------------------------------
signal FIFO2UDP_state : std_logic_vector(3 downto 0) := b"0000";
signal faifouki : std_logic := '0';
------------------------------------------------------------------
-- xADC signals
------------------------------------------------------------------
signal xadc_start : std_logic;
signal vmm_id_xadc : std_logic_vector (15 downto 0) := (others => '0');
signal xadc_sample_size : std_logic_vector (10 downto 0) := "01111111111"; -- 1023 packets
signal xadc_delay : std_logic_vector (17 downto 0) := "011111111111111111"; -- 1023 samples over ~0.7 seconds
signal xadc_end_of_data : std_logic;
signal xadc_fifo_bus : std_logic_vector (15 downto 0);
signal xadc_fifo_enable : std_logic;
signal xadc_packet_len : std_logic_vector (11 downto 0);
signal xadc_busy : std_logic;
signal MuxAddr0_i : std_logic := '0';
signal MuxAddr1_i : std_logic := '0';
signal MuxAddr2_i : std_logic := '0';
signal MuxAddr3_p_i : std_logic := '0';
signal MuxAddr3_n_i : std_logic := '0';
------------------------------------------------------------------
-- Dynamic IP signals
------------------------------------------------------------------
signal myIP_set : std_logic_vector (31 downto 0);
signal myMAC_set : std_logic_vector (47 downto 0);
signal destIP_set : std_logic_vector (31 downto 0);
signal myIP : std_logic_vector (31 downto 0);
signal myMAC : std_logic_vector (47 downto 0);
signal destIP : std_logic_vector (31 downto 0);
signal newIP_start : std_logic;
signal io0_i : std_logic:= '0';
signal io0_o : std_logic:= '0';
signal io0_t : std_logic:= '0';
signal io1_i : std_logic:= '0';
signal io1_o : std_logic:= '0';
signal io1_t : std_logic:= '0';
signal ss_i : std_logic_vector(0 DOWNTO 0):=(others => '0');
signal ss_o : std_logic_vector(0 DOWNTO 0):=(others => '0');
signal ss_t : std_logic:= '0';
------------------------------------------------------------------
-- MMCM + CKBC/CKTP Generator signals
------------------------------------------------------------------
signal clk_160 : std_logic := '0';
signal clk_500 : std_logic := '0';
signal clk_200 : std_logic := '0';
signal clk_40 : std_logic := '0';
signal clk_50 : std_logic := '0';
signal master_locked : std_logic := '0';
signal CKBC_glbl : std_logic := '0';
signal cktp_pulse_width : std_logic_vector(7 downto 0) := x"04"; -- 2 us
signal cktp_period : std_logic_vector(15 downto 0) := x"1388"; -- 1 ms
signal cktp_skew : std_logic_vector(7 downto 0) := (others => '0');
signal ckbc_freq : std_logic_vector(7 downto 0) := x"28"; --40 Mhz
signal cktp_max_num : std_logic_vector(15 downto 0) := x"ffff";
signal cktk_max_num : std_logic_vector(7 downto 0) := x"07";
signal ckbcMode : std_logic := '0';
signal CKTP_raw : std_logic := '0';
signal ckbc_max_num : std_logic_vector(7 downto 0) := x"20";
-------------------------------------------------
-- Flow FSM signals
-------------------------------------------------
type state_t is (IDLE, WAIT_FOR_CONF, CONFIGURE, CONF_DONE, CONFIGURE_DELAY, SEND_CONF_REPLY, DAQ_INIT, FIRST_RESET, TRIG, DAQ, XADC_init, XADC_wait, FLASH_init, FLASH_wait);
signal state : state_t := IDLE;
signal rstFIFO_flow : std_logic := '0';
signal rstFIFO_top : std_logic := '0';
-------------------------------------------------
-- Debugging Signals
-------------------------------------------------
signal overviewProbe : std_logic_vector(63 downto 0);
signal vmmSignalsProbe : std_logic_vector(63 downto 0);
signal triggerETRProbe : std_logic_vector(63 downto 0);
signal configurationProbe : std_logic_vector(63 downto 0);
signal readoutProbe : std_logic_vector(63 downto 0);
signal dataOutProbe : std_logic_vector(63 downto 0);
signal flowProbe : std_logic_vector(63 downto 0);
signal trigger_i : std_logic;
-------------------------------------------------------------------
-- These attribute will stop timing errors being reported in back
-- annotated SDF simulation.
-------------------------------------------------------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of pma_reset_pipe : signal is "TRUE";
attribute ASYNC_REG of glbl_fifo_init_s0 : signal is "TRUE";
attribute ASYNC_REG of glbl_fifo_init_s1 : signal is "TRUE";
-------------------------------------------------------------------
-- Keep signals for ILA
-------------------------------------------------------------------
attribute keep : string;
attribute dont_touch : string;
attribute mark_debug : string;
-------------------------------------------------------------------
-- IOB attribute for VMM pins
-------------------------------------------------------------------
attribute IOB : string;
-- data0
attribute IOB of DATA0_1_P : signal is "TRUE";
attribute IOB of DATA0_1_N : signal is "TRUE";
attribute IOB of DATA0_2_P : signal is "TRUE";
attribute IOB of DATA0_2_N : signal is "TRUE";
attribute IOB of DATA0_3_P : signal is "TRUE";
attribute IOB of DATA0_3_N : signal is "TRUE";
attribute IOB of DATA0_4_P : signal is "TRUE";
attribute IOB of DATA0_4_N : signal is "TRUE";
attribute IOB of DATA0_5_P : signal is "TRUE";
attribute IOB of DATA0_5_N : signal is "TRUE";
attribute IOB of DATA0_6_P : signal is "TRUE";
attribute IOB of DATA0_6_N : signal is "TRUE";
attribute IOB of DATA0_7_P : signal is "TRUE";
attribute IOB of DATA0_7_N : signal is "TRUE";
attribute IOB of DATA0_8_P : signal is "TRUE";
attribute IOB of DATA0_8_N : signal is "TRUE";
-- data1
attribute IOB of DATA1_1_P : signal is "TRUE";
attribute IOB of DATA1_1_N : signal is "TRUE";
attribute IOB of DATA1_2_P : signal is "TRUE";
attribute IOB of DATA1_2_N : signal is "TRUE";
attribute IOB of DATA1_3_P : signal is "TRUE";
attribute IOB of DATA1_3_N : signal is "TRUE";
attribute IOB of DATA1_4_P : signal is "TRUE";
attribute IOB of DATA1_4_N : signal is "TRUE";
attribute IOB of DATA1_5_P : signal is "TRUE";
attribute IOB of DATA1_5_N : signal is "TRUE";
attribute IOB of DATA1_6_P : signal is "TRUE";
attribute IOB of DATA1_6_N : signal is "TRUE";
attribute IOB of DATA1_7_P : signal is "TRUE";
attribute IOB of DATA1_7_N : signal is "TRUE";
attribute IOB of DATA1_8_P : signal is "TRUE";
attribute IOB of DATA1_8_N : signal is "TRUE";
-- cktk
attribute IOB of CKTK_1_P : signal is "TRUE";
attribute IOB of CKTK_1_N : signal is "TRUE";
attribute IOB of CKTK_2_P : signal is "TRUE";
attribute IOB of CKTK_2_N : signal is "TRUE";
attribute IOB of CKTK_3_P : signal is "TRUE";
attribute IOB of CKTK_3_N : signal is "TRUE";
attribute IOB of CKTK_4_P : signal is "TRUE";
attribute IOB of CKTK_4_N : signal is "TRUE";
attribute IOB of CKTK_5_P : signal is "TRUE";
attribute IOB of CKTK_5_N : signal is "TRUE";
attribute IOB of CKTK_6_P : signal is "TRUE";
attribute IOB of CKTK_6_N : signal is "TRUE";
attribute IOB of CKTK_7_P : signal is "TRUE";
attribute IOB of CKTK_7_N : signal is "TRUE";
attribute IOB of CKTK_8_P : signal is "TRUE";
attribute IOB of CKTK_8_N : signal is "TRUE";
-- sdi
attribute IOB of SDI_1 : signal is "TRUE";
attribute IOB of SDI_2 : signal is "TRUE";
attribute IOB of SDI_3 : signal is "TRUE";
attribute IOB of SDI_4 : signal is "TRUE";
attribute IOB of SDI_5 : signal is "TRUE";
attribute IOB of SDI_6 : signal is "TRUE";
attribute IOB of SDI_7 : signal is "TRUE";
attribute IOB of SDI_8 : signal is "TRUE";
-------------------------------------------------------------------
-- Readout Monitoring
-------------------------------------------------------------------
-- attribute keep of vmm_ena : signal is "true";
-- attribute dont_touch of vmm_ena : signal is "true";
-- attribute keep of vmm_wen_vec : signal is "true";
-- attribute dont_touch of vmm_wen_vec : signal is "true";
-- attribute keep of cktk_out_vec : signal is "true";
-- attribute dont_touch of cktk_out_vec : signal is "true";
-- attribute keep of cktk_out_i : signal is "true";
-- attribute keep of ckdt_out_vec : signal is "true";
-- attribute keep of vmm_do_vec_i : signal is "true";
-- attribute keep of daq_vmm_ena_wen_enable: signal is "true";
-- attribute keep of vmm_id_int : signal is "true";
-- attribute keep of data0_in_vec : signal is "true";
-- attribute dont_touch of data0_in_vec : signal is "true";
-- attribute keep of ro_cktk_out_vec : signal is "true";
-- attribute dont_touch of ro_cktk_out_vec : signal is "true";
-------------------------------------------------------------------
-- Trigger
-------------------------------------------------------------------
-- attribute keep of tren : signal is "true";
-- attribute keep of ext_trigger_in : signal is "true";
-- attribute keep of trig_mode_int : signal is "true";
-- attribute keep of tr_hold : signal is "true";
-- attribute dont_touch of tr_hold : signal is "true";
-- attribute mark_debug of tr_hold : signal is "true";
-------------------------------------------------------------------
-- Event Timing & Soft Reset
-------------------------------------------------------------------
-- attribute keep of etr_reset_latched : signal is "true";
-- attribute keep of rst_vmm : signal is "true";
-- attribute keep of etr_vmm_ena_vec : signal is "true";
-- attribute keep of daq_enable_i : signal is "true";
-- attribute keep of glBCID_i : signal is "true";
-- attribute dont_touch of glBCID_i : signal is "true";
-- attribute keep of state_rst_etr_i : signal is "true";
-- attribute dont_touch of state_rst_etr_i : signal is "true";
-- attribute keep of rst_etr_i : signal is "true";
-- attribute dont_touch of rst_etr_i : signal is "true";
-- attribute keep of rst_done_etr_i : signal is "true";
-- attribute dont_touch of rst_done_etr_i : signal is "true";
-------------------------------------------------------------------
-- Packet Formation
-------------------------------------------------------------------
-- attribute keep of pf_newCycle : signal is "true";
-- attribute keep of pfBusy_i : signal is "true";
-- attribute dont_touch of pfBusy_i : signal is "true";
-------------------------------------------------------------------
-- Dynamic IP
-------------------------------------------------------------------
-- attribute keep of io0_i : signal is "TRUE";
-- attribute keep of io0_o : signal is "TRUE";
-- attribute keep of io0_t : signal is "TRUE";
-- attribute keep of io1_i : signal is "TRUE";
-- attribute keep of io1_o : signal is "TRUE";
-- attribute keep of io1_t : signal is "TRUE";
-- attribute keep of ss_i : signal is "TRUE";
-- attribute keep of ss_o : signal is "TRUE";
-- attribute keep of ss_t : signal is "TRUE";
-------------------------------------------------------------------
-- Overview
-------------------------------------------------------------------
-- attribute mark_debug of is_state : signal is "TRUE";
-- attribute mark_debug of pf_dbg_st : signal is "TRUE";
-- attribute mark_debug of FIFO2UDP_state : signal is "TRUE";
-- attribute mark_debug of UDPDone : signal is "TRUE";
-- attribute mark_debug of CKBC_glbl : signal is "TRUE";
-- attribute mark_debug of tr_out_i : signal is "TRUE";
-- attribute mark_debug of conf_state : signal is "TRUE";
-- attribute mark_debug of rd_ena_buff : signal is "TRUE";
-- attribute mark_debug of vmmWord_i : signal is "TRUE";
-- attribute mark_debug of CKTP_glbl : signal is "TRUE";
-- attribute mark_debug of level_0 : signal is "TRUE";
-- attribute mark_debug of rst_l0_pf : signal is "TRUE";
-- attribute mark_debug of vmmWordReady_i : signal is "TRUE";
-- attribute mark_debug of vmmEventDone_i : signal is "TRUE";
-- attribute mark_debug of dt_state : signal is "TRUE";
-- attribute mark_debug of daq_data_out_i : signal is "TRUE";
-- attribute mark_debug of daq_enable_i : signal is "TRUE";
-- attribute mark_debug of pf_trigVmmRo : signal is "TRUE";
-- attribute mark_debug of dt_cntr_st : signal is "TRUE";
-- attribute mark_debug of linkHealth_bmsk : signal is "TRUE";
-------------------------------------------------------------------
-- Other
-------------------------------------------------------------------
-------------------------------------------------------------------
-- COMPONENTS --
-------------------------------------------------------------------
-- 1. clk_wiz_gen
-- 2. event_timing_reset
-- 3. vmm_readout_wrapper
-- 4. FIFO2UDP
-- 5. trigger
-- 6. packet_formation
-- 7. gig_ethernet_pcs_pma_0
-- 8. UDP_Complete_nomac
-- 9. temac_10_100_1000_fifo_block
-- 10. temac_10_100_1000_reset_sync
-- 11. temac_10_100_1000_config_vector_sm
-- 12. i2c_top
-- 13. udp_data_in_handler
-- 14. udp_reply_handler
-- 15. select_data
-- 16. ila_top_level
-- 17. xadc
-- 18. AXI4_SPI
-- 19. VIO_IP
-- 20. clk_gen_wrapper
-- 21. ila_overview
-- 22. art
-- 23. vmm_oddr_wrapper
-------------------------------------------------------------------
-- 1
component clk_wiz_gen
port
( -- Clock in ports
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
-- Clock out ports
clk_out_160 : out std_logic;
clk_out_500 : out std_logic;
clk_out_200 : out std_logic;
clk_out_50 : out std_logic;
clk_out_40 : out std_logic;
-- Status and control signals
reset : in std_logic;
gen_locked : out std_logic
);
end component;
-- 2
component event_timing_reset
port(
hp_clk : in std_logic;
clk : in std_logic;
clk_10_phase45 : in std_logic;
bc_clk : in std_logic;
daqEnable : in std_logic;
pfBusy : in std_logic;
reset : in std_logic;
glBCID : out std_logic_vector(11 downto 0);
prec_cnt : out std_logic_vector(4 downto 0);
state_rst_out : out std_logic_vector(2 downto 0);
rst_o : out std_logic;
rst_done_o : out std_logic;
vmm_ena_vec : out std_logic_vector(8 downto 1);
vmm_wen_vec : out std_logic_vector(8 downto 1);
reset_latched : out std_logic
);
end component;
-- 3
component vmm_readout_wrapper is
generic(is_mmfe8 : std_logic;
vmmReadoutMode : std_logic);
port (
------------------------------------
--- Continuous Readout Interface ---
clkTkProc : in std_logic; -- Used to clock checking for data process
clkDtProc : in std_logic; -- Used to clock word readout process
clk : in std_logic; -- Main clock
--
daq_enable : in std_logic;
trigger_pulse : in std_logic; -- Trigger
cktk_max : in std_logic_vector(7 downto 0); -- Max number of CKTKs
--
dt_state_o : out std_logic_vector(3 downto 0); -- for debugging
dt_cntr_st_o : out std_logic_vector(3 downto 0); -- for debugging
------------------------------------
---- Level-0 Readout Interface -----
clk_ckdt : in std_logic; -- will be forwarded to the VMM
rst_buff : in std_logic; -- reset the level-0 buffer
rst_intf_proc : in std_logic; -- reset the pf interface
--
level_0 : in std_logic; -- level-0 signal
wr_accept : in std_logic; -- buffer acceptance window
--
vmm_conf : in std_logic; -- high during VMM configuration
daq_on_inhib : out std_logic; -- prevent daq_on state before checking link health
------------------------------------
---- Packet Formation Interface ----
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(15 downto 0);
vmmEventDone : out std_logic;
rd_ena_buff : in std_logic; -- read the readout buffer (level0 or continuous)
vmmId : in std_logic_vector(2 downto 0); -- VMM to be readout
linkHealth_bmsk : out std_logic_vector(8 downto 1); -- status of comma alignment links
------------------------------------
---------- VMM3 Interface ----------
vmm_data0_vec : in std_logic_vector(8 downto 1); -- Single-ended data0 from VMM
vmm_data1_vec : in std_logic_vector(8 downto 1); -- Single-ended data1 from VMM
vmm_ckdt_glbl : out std_logic; -- Strobe to VMM CKDT
vmm_ckdt_enable : out std_logic_vector(8 downto 1); -- Enable signal for VMM CKDT
vmm_cktk_vec : out std_logic_vector(8 downto 1) -- Strobe to VMM CKTK
);
end component;
-- 4
component FIFO2UDP
port (
clk_125 : in std_logic;
destinationIP : in std_logic_vector(31 downto 0);
daq_data_in : in std_logic_vector(15 downto 0);
fifo_data_out : out std_logic_vector (7 downto 0);
udp_txi : out udp_tx_type;
udp_tx_start : out std_logic;
re_out : out std_logic;
control : out std_logic;
UDPDone : out std_logic;
udp_tx_data_out_ready : in std_logic;
wr_en : in std_logic;
end_packet : in std_logic;
global_reset : in std_logic;
packet_length_in : in std_logic_vector(11 downto 0);
reset_DAQ_FIFO : in std_logic;
vmmID : in std_logic_vector(2 downto 0);
confReply_packet : in std_logic;
trigger_out : out std_logic;
count_o : out std_logic_vector(3 downto 0);
faifouki : out std_logic
);
end component;
-- 5
component trigger is
generic (vmmReadoutMode : std_logic);
port (
clk : in std_logic;
ckbc : in std_logic;
clk_art : in std_logic;
rst_trig : in std_logic;
ckbcMode : in std_logic;
cktp_enable : in std_logic;
cktp_pulse_width: in std_logic_vector(4 downto 0);
CKTP_raw : in std_logic;
request2ckbc : out std_logic;
accept_wr : out std_logic;
pfBusy : in std_logic;
tren : in std_logic;
tr_hold : in std_logic;
trmode : in std_logic;
trext : in std_logic;
reset : in std_logic;
level_0 : out std_logic;
event_counter : out std_logic_vector(31 DOWNTO 0);
tr_out : out std_logic;
trraw_synced125 : out std_logic;
latency : in std_logic_vector(15 DOWNTO 0)
);
end component;
-- 6
component packet_formation is
generic(is_mmfe8 : std_logic;
vmmReadoutMode : std_logic;
artEnabled : std_logic);
port (
clk : in std_logic;
newCycle : in std_logic;
trigVmmRo : out std_logic;
vmmId : out std_logic_vector(2 downto 0);
vmmWord : in std_logic_vector(15 downto 0);
vmmWordReady : in std_logic;
vmmEventDone : in std_logic;
UDPDone : in std_logic;
pfBusy : out std_logic;
glBCID : in std_logic_vector(11 downto 0);
packLen : out std_logic_vector(11 downto 0);
dataout : out std_logic_vector(15 downto 0);
wrenable : out std_logic;
end_packet : out std_logic;
rd_ena_buff : out std_logic;
rst_l0 : out std_logic;
tr_hold : out std_logic;
reset : in std_logic;
rst_vmm : out std_logic;
linkHealth_bmsk : in std_logic_vector(8 downto 1);
rst_FIFO : out std_logic;
latency : in std_logic_vector(15 downto 0);
dbg_st_o : out std_logic_vector(4 downto 0);
trraw_synced125 : in std_logic;
vmmArtData125 : in std_logic_vector(5 downto 0);
vmmArtReady : in std_logic
);
end component;
-- 7
component gig_ethernet_pcs_pma_0
port(
-- Transceiver Interface
---------------------
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
gtrefclk_out : out std_logic; -- Very high quality clock for GT transceiver.
gtrefclk_bufg_out : out std_logic;
txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD.
txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD.
rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA.
rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA.
resetdone : out std_logic; -- The GT transceiver has completed its reset cycle
userclk_out : out std_logic;
userclk2_out : out std_logic;
rxuserclk_out : out std_logic;
rxuserclk2_out : out std_logic;
pma_reset_out : out std_logic; -- transceiver PMA reset signal
mmcm_locked_out : out std_logic; -- MMCM Locked
independent_clock_bufg : in std_logic;
-- GMII Interface
-----------------
sgmii_clk_r : out std_logic;
sgmii_clk_f : out std_logic;
sgmii_clk_en : out std_logic; -- Clock enable for client MAC
gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC.
gmii_tx_en : in std_logic; -- Transmit control signal from client MAC.
gmii_tx_er : in std_logic; -- Transmit control signal from client MAC.
gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC.
gmii_rx_dv : out std_logic; -- Received control signal to client MAC.
gmii_rx_er : out std_logic; -- Received control signal to client MAC.
gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII.
-- Management: Alternative to MDIO Interface
--------------------------------------------
configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface.
an_interrupt : out std_logic; -- Interrupt to processor to signal that Auto-Negotiation has completed
an_adv_config_vector : in std_logic_vector(15 downto 0); -- Alternate interface to program REG4 (AN ADV)
an_restart_config : in std_logic; -- Alternate signal to modify AN restart bit in REG0
-- Speed Control
----------------
speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds
speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed
-- General IO's
---------------
status_vector : out std_logic_vector(15 downto 0); -- Core status.
reset : in std_logic; -- Asynchronous reset for entire core.
signal_detect : in std_logic; -- Input from PMD to indicate presence of optical input.
gt0_pll0outclk_out : out std_logic;
gt0_pll0outrefclk_out : out std_logic;
gt0_pll1outclk_out : out std_logic;
gt0_pll1outrefclk_out : out std_logic;
gt0_pll0refclklost_out : out std_logic;
gt0_pll0lock_out : out std_logic);
end component;
-- 8
component UDP_ICMP_Complete_nomac
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- ICMP RX signals
icmp_rx_start : out std_logic;
icmp_rxo : out icmp_rx_type;
-- IP RX signals
ip_rx_hdr : out ipv4_rx_header_type;
-- system signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
fifo_init : in std_logic;
our_ip_address : in std_logic_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in udp_control_type;
-- status signals
arp_pkt_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
ip_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic); -- indicates last byte of the trame
end component;
-- 9
component temac_10_100_1000_fifo_block
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_reset : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_axis_fifo_tlast : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_axis_fifo_tlast : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
clk_enable : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- Configuration Vector
-------------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0));
end component;
-- 10
component temac_10_100_1000_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic); -- "Synchronised" reset signal
end component;
-- 11
component temac_10_100_1000_config_vector_sm is
port(
gtx_clk : in std_logic;
gtx_resetn : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
rx_configuration_vector : out std_logic_vector(79 downto 0);
tx_configuration_vector : out std_logic_vector(79 downto 0));
end component;
-- 12
component i2c_top is
port(
clk_in : in std_logic;
phy_rstn_out : out std_logic
);
end component;
-- 13
component udp_data_in_handler
port(
------------------------------------
------- General Interface ----------
clk_125 : in std_logic;
clk_40 : in std_logic;
inhibit_conf : in std_logic;
rst : in std_logic;
rst_fifo_init : in std_logic;
state_o : out std_logic_vector(2 downto 0);
valid_o : out std_logic;
------------------------------------
-------- FPGA Config Interface -----
latency : out std_logic_vector(15 downto 0);
serial_number : out std_logic_vector(31 downto 0);
daq_on : out std_logic;
ext_trigger : out std_logic;
ckbcMode : out std_logic;
fpga_rst : out std_logic;
------------------------------------
-------- UDP Interface -------------
udp_rx : in udp_rx_type;
------------------------------------
---------- AXI4SPI Interface -------
flash_busy : in std_logic;
newIP_rdy : out std_logic;
myIP_set : out std_logic_vector(31 downto 0);
myMAC_set : out std_logic_vector(47 downto 0);
destIP_set : out std_logic_vector(31 downto 0);
------------------------------------
-------- CKTP/CKBC Interface -------
ckbc_freq : out std_logic_vector(7 downto 0);
cktk_max_num : out std_logic_vector(7 downto 0);
cktp_max_num : out std_logic_vector(15 downto 0);
cktp_skew : out std_logic_vector(7 downto 0);
cktp_period : out std_logic_vector(15 downto 0);
cktp_width : out std_logic_vector(7 downto 0);
ckbc_max_num : out std_logic_vector(7 downto 0);
------------------------------------
------ VMM Config Interface --------
vmm_bitmask : out std_logic_vector(7 downto 0);
vmmConf_came : out std_logic;
vmmConf_rdy : out std_logic;
vmmConf_done : out std_logic;
vmm_sck : out std_logic;
vmm_cs : out std_logic;
vmm_cfg_bit : out std_logic;
top_rdy : in std_logic;
------------------------------------
---------- XADC Interface ----------
xadc_busy : in std_logic;
xadc_rdy : out std_logic;
vmm_id_xadc : out std_logic_vector(15 downto 0);
xadc_sample_size : out std_logic_vector(10 downto 0);
xadc_delay : out std_logic_vector(17 downto 0)
);
end component;
-- 14
component udp_reply_handler
port(
------------------------------------
------- General Interface ----------
clk : in std_logic;
enable : in std_logic;
serial_number : in std_logic_vector(31 downto 0);
reply_done : out std_logic;
------------------------------------
---- FIFO Data Select Interface ----
wr_en_conf : out std_logic;
dout_conf : out std_logic_vector(15 downto 0);
packet_len_conf : out std_logic_vector(11 downto 0);
end_conf : out std_logic
);
end component;
-- 15
component select_data
port(
configuring : in std_logic;
data_acq : in std_logic;
xadc : in std_logic;
we_data : in std_logic;
we_conf : in std_logic;
we_xadc : in std_logic;
daq_data_in : in std_logic_vector(15 downto 0);
conf_data_in : in std_logic_vector(15 downto 0);
xadc_data_in : in std_logic_vector(15 downto 0);
data_packet_length : in std_logic_vector(11 downto 0);
xadc_packet_length : in std_logic_vector(11 downto 0);
conf_packet_length : in std_logic_vector(11 downto 0);
end_packet_conf : in std_logic;
end_packet_daq : in std_logic;
end_packet_xadc : in std_logic;
fifo_rst_daq : in std_logic;
fifo_rst_xadc : in std_logic;
rstFIFO_top : in std_logic;
data_out : out std_logic_vector(15 downto 0);
packet_length : out std_logic_vector(11 downto 0);
we : out std_logic;
end_packet : out std_logic;
fifo_rst : out std_logic
);
end component;
-- 16
component ila_top_level
PORT ( clk : in std_logic;
probe0 : in std_logic_vector(63 DOWNTO 0);
probe1 : in std_logic_vector(63 DOWNTO 0);
probe2 : in std_logic_vector(63 DOWNTO 0);
probe3 : in std_logic_vector(63 DOWNTO 0);
probe4 : in std_logic_vector(63 DOWNTO 0);
probe5 : in std_logic_vector(63 DOWNTO 0)
);
end component;
-- 17
component xadcModule
port(
clk125 : in std_logic;
rst : in std_logic;
VP_0 : in std_logic;
VN_0 : in std_logic;
Vaux0_v_n : in std_logic;
Vaux0_v_p : in std_logic;
Vaux1_v_n : in std_logic;
Vaux1_v_p : in std_logic;
Vaux2_v_n : in std_logic;
Vaux2_v_p : in std_logic;
Vaux3_v_n : in std_logic;
Vaux3_v_p : in std_logic;
Vaux8_v_n : in std_logic;
Vaux8_v_p : in std_logic;
Vaux9_v_n : in std_logic;
Vaux9_v_p : in std_logic;
Vaux10_v_n : in std_logic;
Vaux10_v_p : in std_logic;
Vaux11_v_n : in std_logic;
Vaux11_v_p : in std_logic;
data_in_rdy : in std_logic;
vmm_id : in std_logic_vector(15 downto 0);
sample_size : in std_logic_vector(10 downto 0);
delay_in : in std_logic_vector(17 downto 0);
UDPDone : in std_logic;
MuxAddr0 : out std_logic;
MuxAddr1 : out std_logic;
MuxAddr2 : out std_logic;
MuxAddr3_p : out std_logic;
MuxAddr3_n : out std_logic;
end_of_data : out std_logic;
fifo_bus : out std_logic_vector(15 downto 0);
data_fifo_enable : out std_logic;
packet_len : out std_logic_vector(11 downto 0);
xadc_busy : out std_logic
);
end component;
-- 18
component AXI4_SPI
port(
clk_200 : in std_logic;
clk_125 : in std_logic;
clk_50 : in std_logic;
myIP : out std_logic_vector(31 downto 0);
myMAC : out std_logic_vector(47 downto 0);
destIP : out std_logic_vector(31 downto 0);
default_IP : in std_logic_vector(31 downto 0);
default_MAC : in std_logic_vector(47 downto 0);
default_destIP : in std_logic_vector(31 downto 0);
myIP_set : in std_logic_vector(31 downto 0);
myMAC_set : in std_logic_vector(47 downto 0);
destIP_set : in std_logic_vector(31 downto 0);
newip_start : in std_logic;
flash_busy : out std_logic;
io0_i : IN std_logic;
io0_o : OUT std_logic;
io0_t : OUT std_logic;
io1_i : IN std_logic;
io1_o : OUT std_logic;
io1_t : OUT std_logic;
ss_i : IN std_logic_vector(0 DOWNTO 0);
ss_o : OUT std_logic_vector(0 DOWNTO 0);
ss_t : OUT std_logic
);
end component;
-- 19
COMPONENT vio_ip
PORT (
clk : IN std_logic;
probe_out0 : OUT std_logic_VECTOR(31 DOWNTO 0);
probe_out1 : OUT std_logic_VECTOR(47 DOWNTO 0)
);
END COMPONENT;
-- 20
component clk_gen_wrapper
Port(
------------------------------------
------- General Interface ----------
clk_500 : in std_logic;
clk_160 : in std_logic;
clk_125 : in std_logic;
rst : in std_logic;
mmcm_locked : in std_logic;
CKTP_raw : out std_logic;
------------------------------------
----- Configuration Interface ------
cktp_enable : in std_logic;
cktp_primary : in std_logic;
readout_mode : in std_logic;
enable_ro_ckbc : in std_logic;
cktp_pulse_width : in std_logic_vector(4 downto 0);
cktp_max_num : in std_logic_vector(15 downto 0);
cktp_period : in std_logic_vector(15 downto 0);
cktp_skew : in std_logic_vector(4 downto 0);
ckbc_freq : in std_logic_vector(5 downto 0);
ckbc_max_num : in std_logic_vector(7 downto 0);
------------------------------------
---------- VMM Interface -----------
CKTP : out std_logic;
CKBC : out std_logic
);
end component;
-- 21
component ila_overview
Port(
clk : in std_logic;
probe0 : in std_logic_vector(63 downto 0)
);
end component;
-- 22
component artReadout --art_instance
generic( is_mmfe8 : std_logic;
artEnabled : std_logic);
Port(
clk : in std_logic;
clk_art : in std_logic;
trigger : in std_logic;
artData : in std_logic_vector(8 downto 1);
vmmArtData125 : out std_logic_vector(5 downto 0);
vmmArtReady : out std_logic
);
end component;
-- 23
component vmm_oddr_wrapper
Port(
-------------------------------------------------------
ckdt_bufg : in std_logic;
ckdt_enable_vec : in std_logic_vector(8 downto 1);
ckdt_toBuf_vec : out std_logic_vector(8 downto 1);
-------------------------------------------------------
ckbc_bufg : in std_logic;
ckbc_enable : in std_logic;
ckbc_toBuf_vec : out std_logic_vector(8 downto 1);
-------------------------------------------------------
cktp_bufg : in std_logic;
cktp_toBuf_vec : out std_logic_vector(8 downto 1);
-------------------------------------------------------
ckart_bufg : in std_logic;
ckart_toBuf_vec : out std_logic_vector(9 downto 1)
-------------------------------------------------------
);
end component;
begin
gen_vector_reset: process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
if vector_reset_int = '1' then
vector_pre_resetn <= '0';
vector_resetn <= '0';
else
vector_pre_resetn <= '1';
vector_resetn <= vector_pre_resetn;
end if;
end if;
end process gen_vector_reset;
-----------------------------------------------------------------------------
-- Transceiver PMA reset circuitry
-----------------------------------------------------------------------------
core_wrapper: gig_ethernet_pcs_pma_0
port map (
gtrefclk_p => gtrefclk_p,
gtrefclk_n => gtrefclk_n,
txp => txp,
txn => txn,
rxp => rxp,
rxn => rxn,
gtrefclk_out => open,
gtrefclk_bufg_out => txoutclk,
rxuserclk_out => open,
rxuserclk2_out => open,
resetdone => resetdone,
mmcm_locked_out => mmcm_locked,
userclk_out => userclk,
userclk2_out => userclk2,
independent_clock_bufg => clk_200,
pma_reset_out => pma_reset,
sgmii_clk_r => sgmii_clk_r,
sgmii_clk_f => sgmii_clk_f,
sgmii_clk_en => clk_enable_int,
gmii_txd => gmii_txd_int,
gmii_tx_en => gmii_tx_en_int,
gmii_tx_er => gmii_tx_er_int,
gmii_rxd => gmii_rxd_int,
gmii_rx_dv => gmii_rx_dv_int,
gmii_rx_er => gmii_rx_er_int,
gmii_isolate => gmii_isolate,
configuration_vector => "10000", -- configuration_vector,
status_vector => status_vector_int, -- status_vector_int,
reset => '0',
signal_detect => '1', -- signal_detect
speed_is_10_100 => speed_is_10_100,
speed_is_100 => speed_is_100,
an_interrupt => open, -- Interrupt to processor to signal that Auto-Negotiation has completed
an_adv_config_vector => "1111111000000001",-- Alternate interface to program REG4 (AN ADV)
an_restart_config => an_restart_config_int, -- Alternate signal to modify AN restart bit in REG0
gt0_pll0outclk_out => open,
gt0_pll0outrefclk_out => open,
gt0_pll1outclk_out => open,
gt0_pll1outrefclk_out => open,
gt0_pll0refclklost_out => open,
gt0_pll0lock_out => open);
process(userclk2)
begin
if (local_gtx_reset = '1') then
an_restart_config_int <= '1';
else
an_restart_config_int <= '0';
end if;
end process;
tri_fifo: temac_10_100_1000_fifo_block
port map(
gtx_clk => userclk2, --sgmii_clk_int, --userclk2,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => '1',
tx_axi_rstn => '1',
-- Receiver Statistics Interface
-----------------------------------------
rx_reset => rx_reset,
rx_statistics_vector => open,
rx_statistics_valid => open,
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock => userclk2,
rx_fifo_resetn => gtx_resetn,
rx_axis_fifo_tdata => rx_axis_mac_tdata_int,
rx_axis_fifo_tvalid => rx_axis_mac_tvalid_int,
rx_axis_fifo_tready => rx_axis_mac_tready_int,
rx_axis_fifo_tlast => rx_axis_mac_tlast_int,
-- Transmitter Statistics Interface
--------------------------------------------
tx_reset => tx_reset,
tx_ifg_delay => x"00",
tx_statistics_vector => open,
tx_statistics_valid => open,
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock => userclk2,
tx_fifo_resetn => gtx_resetn,
tx_axis_fifo_tdata => tx_axis_mac_tdata_int,
tx_axis_fifo_tvalid => tx_axis_mac_tvalid_int,
tx_axis_fifo_tready => tx_axis_mac_tready_int,
tx_axis_fifo_tlast => tx_axis_mac_tlast_int,
-- MAC Control Interface
--------------------------
pause_req => '0',
pause_val => x"0000",
-- GMII Interface
-------------------
gmii_txd => gmii_txd_emac,
gmii_tx_en => gmii_tx_en_emac,
gmii_tx_er => gmii_tx_er_emac,
gmii_rxd => gmii_rxd_emac,
gmii_rx_dv => gmii_rx_dv_emac,
gmii_rx_er => gmii_rx_er_emac,
clk_enable => clk_enable_int,
speedis100 => speed_is_100,
speedis10100 => speed_is_10_100,
-- Configuration Vector
-------------------------
rx_configuration_vector => rx_configuration_vector_int, -- x"0605_0403_02da_0000_2022",
tx_configuration_vector => tx_configuration_vector_int); -- x"0605_0403_02da_0000_2022"
-- Control vector reset
axi_lite_reset_gen: temac_10_100_1000_reset_sync
port map (
clk => userclk2,
enable => '1',
reset_in => glbl_rst_i,
reset_out => vector_reset_int);
config_vector: temac_10_100_1000_config_vector_sm
port map(
gtx_clk => userclk2, --sgmii_clk_int, --userclk2,
gtx_resetn => vector_resetn,
mac_speed => status_vector_int(11 downto 10), -- "10",
update_speed => '1',
rx_configuration_vector => rx_configuration_vector_int,
tx_configuration_vector => tx_configuration_vector_int);
-----------------------------------------------------------------------------
-- GMII transmitter data logic
-----------------------------------------------------------------------------
-- Drive input GMII signals through IOB input flip-flops (inferred).
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
gmii_txd_int <= gmii_txd_emac;
gmii_tx_en_int <= gmii_tx_en_emac;
gmii_tx_er_int <= gmii_tx_er_emac;
end if;
end process;
gtx_reset_gen: temac_10_100_1000_reset_sync
port map (
clk => userclk2,
enable => '1',
reset_in => local_gtx_reset,
reset_out => gtx_clk_reset_int);
gen_gtx_reset: process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
if gtx_clk_reset_int = '1' then
gtx_pre_resetn <= '0';
gtx_resetn <= '0';
else
gtx_pre_resetn <= '1';
gtx_resetn <= gtx_pre_resetn;
end if;
end if;
end process gen_gtx_reset;
-- Drive input GMII signals through IOB output flip-flops (inferred).
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
gmii_rxd_emac <= gmii_rxd_int;
gmii_rx_dv_emac <= gmii_rx_dv_int;
gmii_rx_er_emac <= gmii_rx_er_int;
end if;
end process;
UDP_ICMP_block: UDP_ICMP_Complete_nomac
Port map(
udp_tx_start => udp_tx_start_int,
udp_txi => udp_txi_int,
udp_tx_result => open,
udp_tx_data_out_ready => udp_tx_data_out_ready_int,
udp_rx_start => open,
udp_rxo => udp_rx_int,
icmp_rx_start => icmp_rx_start,
icmp_rxo => icmp_rxo,
ip_rx_hdr => ip_rx_hdr_int,
rx_clk => userclk2,
tx_clk => userclk2,
reset => glbl_rst_i,
fifo_init => glbl_fifo_init,
our_ip_address => myIP,
our_mac_address => myMAC,
control => control,
arp_pkt_count => open,
ip_pkt_count => open,
mac_tx_tdata => tx_axis_mac_tdata_int,
mac_tx_tvalid => tx_axis_mac_tvalid_int,
mac_tx_tready => tx_axis_mac_tready_int,
mac_tx_tfirst => open,
mac_tx_tlast => tx_axis_mac_tlast_int,
mac_rx_tdata => rx_axis_mac_tdata_int,
mac_rx_tvalid => rx_axis_mac_tvalid_int,
mac_rx_tready => rx_axis_mac_tready_int,
mac_rx_tlast => rx_axis_mac_tlast_int);
i2c_module: i2c_top
port map(
clk_in => clk_200,
phy_rstn_out => phy_rstn
);
udp_din_conf_block: udp_data_in_handler
port map(
------------------------------------
------- General Interface ----------
clk_125 => userclk2,
clk_40 => clk_40,
inhibit_conf => inhibit_conf,
rst => glbl_rst_i,
rst_fifo_init => glbl_fifo_init_s1,
state_o => conf_state,
valid_o => open,
------------------------------------
-------- FPGA Config Interface -----
latency => latency_conf,
serial_number => serial_number,
daq_on => daq_on,
ext_trigger => trig_mode_int,
ckbcMode => ckbcMode,
fpga_rst => glbl_rst_i,
------------------------------------
-------- UDP Interface -------------
udp_rx => udp_rx_int,
------------------------------------
---------- AXI4SPI Interface -------
flash_busy => flash_busy,
newIP_rdy => newIP_rdy,
myIP_set => myIP_set,
myMAC_set => myMAC_set,
destIP_set => destIP_set,
------------------------------------
-------- CKTP/CKBC Interface -------
ckbc_freq => ckbc_freq,
cktk_max_num => cktk_max_num,
cktp_max_num => cktp_max_num,
cktp_skew => cktp_skew,
cktp_period => cktp_period,
cktp_width => cktp_pulse_width,
ckbc_max_num => ckbc_max_num,
------------------------------------
------ VMM Config Interface --------
vmm_bitmask => vmm_bitmask_8VMM,
vmmConf_came => vmm_conf,
vmmConf_rdy => vmm_id_rdy,
vmmConf_done => vmmConf_done,
vmm_sck => vmm_sck_all,
vmm_cs => VMM_CS_i,
vmm_cfg_bit => vmm_sdi_all,
top_rdy => conf_wen_i,
------------------------------------
---------- XADC Interface ----------
xadc_busy => xadc_busy,
xadc_rdy => xadc_conf_rdy,
vmm_id_xadc => vmm_id_xadc,
xadc_sample_size => xadc_sample_size,
xadc_delay => xadc_delay
);
udp_reply_instance: udp_reply_handler
port map(
------------------------------------
------- General Interface ----------
clk => userclk2,
enable => reply_enable,
serial_number => serial_number,
reply_done => reply_done,
------------------------------------
---- FIFO Data Select Interface ----
wr_en_conf => we_conf_int,
dout_conf => user_data_out_i,
packet_len_conf => packet_len_conf,
end_conf => end_packet_conf_int
);
mmcm_master: clk_wiz_gen
port map (
-- Clock in ports
clk_in1_p => X_2V5_DIFF_CLK_P,
clk_in1_n => X_2V5_DIFF_CLK_N,
-- Clock out ports
clk_out_160 => clk_160,
clk_out_500 => clk_500,
clk_out_200 => clk_200,
clk_out_50 => clk_50,
clk_out_40 => clk_40,
-- Status and control signals
reset => '0',
gen_locked => master_locked
);
event_timing_reset_instance: event_timing_reset
port map(
hp_clk => '0', --clk_800
clk => userclk2,
clk_10_phase45 => '0', --clk_10_phase45
bc_clk => '0', --clk_10
daqEnable => daq_enable_i,
pfBusy => pfBusy_i,
reset => rst_vmm,
glBCID => glBCID_i,
prec_cnt => open,
state_rst_out => state_rst_etr_i,
rst_o => rst_etr_i,
rst_done_o => rst_done_etr_i,
vmm_ena_vec => open,
vmm_wen_vec => open,
reset_latched => etr_reset_latched
);
readout_vmm: vmm_readout_wrapper
generic map(is_mmfe8 => is_mmfe8, vmmReadoutMode => vmmReadoutMode)
port map(
------------------------------------
--- Continuous Readout Interface ---
clkTkProc => clk_40,
clkDtProc => clk_50,
clk => userclk2,
--
daq_enable => daq_enable_i,
trigger_pulse => pf_trigVmmRo,
cktk_max => cktk_max_num,
--
dt_state_o => dt_state,
dt_cntr_st_o => dt_cntr_st,
------------------------------------
---- Level-0 Readout Interface -----
clk_ckdt => clk_160,
rst_buff => rst_l0_buff,
rst_intf_proc => rst_l0_pf,
--
level_0 => level_0,
wr_accept => accept_wr,
--
vmm_conf => conf_wen_i,
daq_on_inhib => daq_on_inhib, -- synced to flow_fsm's clock
------------------------------------
---- Packet Formation Interface ----
vmmWordReady => vmmWordReady_i,
vmmWord => vmmWord_i,
rd_ena_buff => rd_ena_buff,
vmmEventDone => vmmEventDone_i,
vmmId => pf_vmmIdRo,
linkHealth_bmsk => linkHealth_bmsk,
------------------------------------
---------- VMM3 Interface ----------
vmm_data0_vec => data0_in_vec,
vmm_data1_vec => data1_in_vec,
vmm_ckdt_glbl => CKDT_glbl,
vmm_ckdt_enable => vmm_ckdt_enable,
vmm_cktk_vec => cktk_out_vec
);
trigger_instance: trigger
generic map(vmmReadoutMode => vmmReadoutMode)
port map(
clk => userclk2,
ckbc => CKBC_glbl,
clk_art => clk_160,
rst_trig => glbl_rst_i,
ckbcMode => ckbcMode,
request2ckbc => request2ckbc,
cktp_enable => cktp_enable,
CKTP_raw => CKTP_raw,
pfBusy => pfBusy_i,
cktp_pulse_width=> cktp_pulse_width(4 downto 0),
tren => tren, -- Trigger module enabled
tr_hold => tr_hold, -- Prevents trigger while high
trmode => trig_mode_int, -- Mode 0: internal / Mode 1: external
trext => CH_TRIGGER_i, -- External trigger is to be driven to this port
level_0 => level_0, -- Level-0 accept signal
accept_wr => accept_wr,
reset => tr_reset,
event_counter => open,
tr_out => tr_out_i,
trraw_synced125 => trraw_synced125_i,
latency => latency_conf
);
FIFO2UDP_instance: FIFO2UDP
Port map(
clk_125 => userclk2,
destinationIP => destIP,
daq_data_in => daqFIFO_din_i,
fifo_data_out => open,
udp_txi => udp_txi_int,
udp_tx_start => udp_tx_start_int,
control => control.ip_controls.arp_controls.clear_cache,
UDPDone => UDPDone,
re_out => open,
udp_tx_data_out_ready => udp_tx_data_out_ready_int,
wr_en => daqFIFO_wr_en_i,
end_packet => end_packet_i,
global_reset => glbl_rst_i,
packet_length_in => packet_length_int,
reset_DAQ_FIFO => daqFIFO_reset,
confReply_packet => start_conf_proc_int,
vmmID => pf_vmmIdRo,
trigger_out => trigger_i,
count_o => FIFO2UDP_state,
faifouki => faifouki
);
packet_formation_instance: packet_formation
generic map(is_mmfe8 => is_mmfe8,
vmmReadoutMode => vmmReadoutMode,
artEnabled => artEnabled)
port map(
clk => userclk2,
newCycle => pf_newCycle,
trigVmmRo => pf_trigVmmRo,
vmmId => pf_vmmIdRo,
vmmWord => vmmWord_i,
vmmWordReady => vmmWordReady_i,
vmmEventDone => vmmEventDone_i,
UDPDone => UDPDone,
pfBusy => pfBusy_i,
glBCID => glBCID_i,
packLen => pf_packLen,
dataout => daq_data_out_i,
wrenable => daq_wr_en_i,
end_packet => end_packet_daq_int,
rd_ena_buff => rd_ena_buff,
rst_l0 => rst_l0_pf,
tr_hold => tr_hold,
reset => pf_rst_final,
rst_vmm => rst_vmm,
linkHealth_bmsk => linkHealth_bmsk,
rst_FIFO => pf_rst_FIFO,
latency => latency_conf,
dbg_st_o => pf_dbg_st,
trraw_synced125 => trraw_synced125_i,
vmmArtData125 => vmmArtData,
vmmArtReady => vmmArtReady
);
data_selection: select_data
port map(
configuring => start_conf_proc_int,
xadc => xadc_busy,
data_acq => daq_enable_i,
we_data => daq_wr_en_i,
we_conf => we_conf_int,
we_xadc => xadc_fifo_enable,
daq_data_in => daq_data_out_i,
conf_data_in => user_data_out_i,
xadc_data_in => xadc_fifo_bus,
data_packet_length => pf_packLen,
xadc_packet_length => xadc_packet_len,
conf_packet_length => packet_len_conf,
end_packet_conf => end_packet_conf_int,
end_packet_daq => end_packet_daq_int,
end_packet_xadc => xadc_end_of_data,
fifo_rst_daq => pf_rst_FIFO,
fifo_rst_xadc => '0',
rstFIFO_top => rstFIFO_top,
data_out => daqFIFO_din_i,
packet_length => packet_length_int,
we => daqFIFO_wr_en_i,
end_packet => end_packet_i,
fifo_rst => daqFIFO_reset
);
xadc_instance: xadcModule
port map(
clk125 => userclk2,
rst => glbl_rst_i,
VP_0 => VP_0,
VN_0 => VN_0,
Vaux0_v_n => Vaux0_v_n,
Vaux0_v_p => Vaux0_v_p,
Vaux1_v_n => Vaux1_v_n,
Vaux1_v_p => Vaux1_v_p,
Vaux2_v_n => Vaux2_v_n,
Vaux2_v_p => Vaux2_v_p,
Vaux3_v_n => Vaux3_v_n,
Vaux3_v_p => Vaux3_v_p,
Vaux8_v_n => Vaux8_v_n,
Vaux8_v_p => Vaux8_v_p,
Vaux9_v_n => Vaux9_v_n,
Vaux9_v_p => Vaux9_v_p,
Vaux10_v_n => Vaux10_v_n,
Vaux10_v_p => Vaux10_v_p,
Vaux11_v_n => Vaux11_v_n,
Vaux11_v_p => Vaux11_v_p,
data_in_rdy => xadc_start,
vmm_id => vmm_id_xadc,
sample_size => xadc_sample_size,
delay_in => xadc_delay,
UDPDone => UDPDone,
MuxAddr0 => MuxAddr0_i,
MuxAddr1 => MuxAddr1_i,
MuxAddr2 => MuxAddr2_i,
MuxAddr3_p => MuxAddr3_p_i,
MuxAddr3_n => MuxAddr3_n_i,
end_of_data => xadc_end_of_data,
fifo_bus => xadc_fifo_bus,
data_fifo_enable => xadc_fifo_enable,
packet_len => xadc_packet_len,
xadc_busy => xadc_busy -- synced to 125 Mhz
);
axi4_spi_instance: AXI4_SPI
port map(
clk_200 => clk_200,
clk_125 => userclk2,
clk_50 => clk_50,
myIP => myIP, -- synced to 125 Mhz
myMAC => myMAC, -- synced to 125 Mhz
destIP => destIP, -- synced to 125 Mhz
default_IP => default_IP,
default_MAC => default_MAC,
default_destIP => default_destIP,
myIP_set => myIP_set, -- synced internally to 50 Mhz
myMAC_set => myMAC_set, -- synced internally to 50 Mhz
destIP_set => destIP_set, -- synced internally to 50 Mhz
newip_start => newIP_start, -- synced internally to 50 Mhz
flash_busy => flash_busy, -- synced to 125 Mhz
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t
--SPI_CLK =>
);
ckbc_cktp_generator: clk_gen_wrapper
port map(
------------------------------------
------- General Interface ----------
clk_500 => clk_500,
clk_160 => clk_160,
clk_125 => userclk2,
rst => glbl_rst_i,
mmcm_locked => master_locked,
CKTP_raw => CKTP_raw,
------------------------------------
----- Configuration Interface ------
cktp_enable => cktp_enable,
cktp_primary => vmm_cktp_primary, -- from flow_fsm
readout_mode => ckbcMode,
enable_ro_ckbc => request2ckbc,
cktp_pulse_width => cktp_pulse_width(4 downto 0),
cktp_max_num => cktp_max_num,
cktp_period => cktp_period,
cktp_skew => cktp_skew(4 downto 0),
ckbc_freq => ckbc_freq(5 downto 0),
ckbc_max_num => ckbc_max_num,
------------------------------------
---------- VMM Interface -----------
CKTP => CKTP_glbl,
CKBC => CKBC_glbl
);
QSPI_IO0_0: IOBUF
port map (
O => io0_i,
IO => IO0_IO,
I => io0_o,
T => io0_t
);
QSPI_IO1_0: IOBUF
port map (
O => io1_i,
IO => IO1_IO,
I => io1_o,
T => io1_t
);
QSPI_SS_0: IOBUF
port map (
O => ss_i(0),
IO => SS_IO,
I => ss_o(0),
T => ss_t
);
art_instance: artReadout
generic map(is_mmfe8 => is_mmfe8,
artEnabled => artEnabled)
port map (
clk => userclk2,
clk_art => clk_160,
trigger => trraw_synced125_i,
artData => art_in_vec,
vmmArtData125 => vmmArtData,
vmmArtReady => vmmArtReady
);
vmm_oddr_inst: vmm_oddr_wrapper
port map(
-------------------------------------------------------
ckdt_bufg => CKDT_glbl,
ckdt_enable_vec => vmm_ckdt_enable,
ckdt_toBuf_vec => ckdt_out_vec,
-------------------------------------------------------
ckbc_bufg => CKBC_glbl,
ckbc_enable => ckbc_enable,
ckbc_toBuf_vec => vmm_ckbc_vec,
-------------------------------------------------------
cktp_bufg => CKTP_glbl,
cktp_toBuf_vec => vmm_cktp_vec,
-------------------------------------------------------
ckart_bufg => clk_160,
ckart_toBuf_vec => ckart_vec
-------------------------------------------------------
);
----------------------------------------------------CS------------------------------------------------------------
cs_obuf_1: OBUF port map (O => CS_1, I => vmm_cs_vec_obuf(1));
cs_obuf_2: OBUF port map (O => CS_2, I => vmm_cs_vec_obuf(2));
cs_obuf_3: OBUF port map (O => CS_3, I => vmm_cs_vec_obuf(3));
cs_obuf_4: OBUF port map (O => CS_4, I => vmm_cs_vec_obuf(4));
cs_obuf_5: OBUF port map (O => CS_5, I => vmm_cs_vec_obuf(5));
cs_obuf_6: OBUF port map (O => CS_6, I => vmm_cs_vec_obuf(6));
cs_obuf_7: OBUF port map (O => CS_7, I => vmm_cs_vec_obuf(7));
cs_obuf_8: OBUF port map (O => CS_8, I => vmm_cs_vec_obuf(8));
----------------------------------------------------SCK------------------------------------------------------------
sck_obuf_1: OBUF port map (O => SCK_1, I => vmm_sck_vec_obuf(1));
sck_obuf_2: OBUF port map (O => SCK_2, I => vmm_sck_vec_obuf(2));
sck_obuf_3: OBUF port map (O => SCK_3, I => vmm_sck_vec_obuf(3));
sck_obuf_4: OBUF port map (O => SCK_4, I => vmm_sck_vec_obuf(4));
sck_obuf_5: OBUF port map (O => SCK_5, I => vmm_sck_vec_obuf(5));
sck_obuf_6: OBUF port map (O => SCK_6, I => vmm_sck_vec_obuf(6));
sck_obuf_7: OBUF port map (O => SCK_7, I => vmm_sck_vec_obuf(7));
sck_obuf_8: OBUF port map (O => SCK_8, I => vmm_sck_vec_obuf(8));
----------------------------------------------------SDI------------------------------------------------------------
sdi_obuf_1: OBUF port map (O => SDI_1, I => vmm_sdi_vec_obuf(1));
sdi_obuf_2: OBUF port map (O => SDI_2, I => vmm_sdi_vec_obuf(2));
sdi_obuf_3: OBUF port map (O => SDI_3, I => vmm_sdi_vec_obuf(3));
sdi_obuf_4: OBUF port map (O => SDI_4, I => vmm_sdi_vec_obuf(4));
sdi_obuf_5: OBUF port map (O => SDI_5, I => vmm_sdi_vec_obuf(5));
sdi_obuf_6: OBUF port map (O => SDI_6, I => vmm_sdi_vec_obuf(6));
sdi_obuf_7: OBUF port map (O => SDI_7, I => vmm_sdi_vec_obuf(7));
sdi_obuf_8: OBUF port map (O => SDI_8, I => vmm_sdi_vec_obuf(8));
---------------------------------------------------SETT/SETB/CK6B--------------------------------------------------
sett_obuf: OBUFDS port map (O => SETT_P, OB => SETT_N, I => '0');
setb_obuf: OBUFDS port map (O => SETB_P, OB => SETB_N, I => '0');
ck6b_obuf_1: OBUFDS port map (O => CK6B_1_P, OB => CK6B_1_N, I => '0');
ck6b_obuf_2: OBUFDS port map (O => CK6B_2_P, OB => CK6B_2_N, I => '0');
ck6b_obuf_3: OBUFDS port map (O => CK6B_3_P, OB => CK6B_3_N, I => '0');
ck6b_obuf_4: OBUFDS port map (O => CK6B_4_P, OB => CK6B_4_N, I => '0');
ck6b_obuf_5: OBUFDS port map (O => CK6B_5_P, OB => CK6B_5_N, I => '0');
ck6b_obuf_6: OBUFDS port map (O => CK6B_6_P, OB => CK6B_6_N, I => '0');
ck6b_obuf_7: OBUFDS port map (O => CK6B_7_P, OB => CK6B_7_N, I => '0');
ck6b_obuf_8: OBUFDS port map (O => CK6B_8_P, OB => CK6B_8_N, I => '0');
----------------------------------------------------SDO------------------------------------------------------------
sdo_ibuf_1: IBUF port map ( O => vmm_sdo_vec_i(1), I => SDO_1);
sdo_ibuf_2: IBUF port map ( O => vmm_sdo_vec_i(2), I => SDO_2);
sdo_ibuf_3: IBUF port map ( O => vmm_sdo_vec_i(3), I => SDO_3);
sdo_ibuf_4: IBUF port map ( O => vmm_sdo_vec_i(4), I => SDO_4);
sdo_ibuf_5: IBUF port map ( O => vmm_sdo_vec_i(5), I => SDO_5);
sdo_ibuf_6: IBUF port map ( O => vmm_sdo_vec_i(6), I => SDO_6);
sdo_ibuf_7: IBUF port map ( O => vmm_sdo_vec_i(7), I => SDO_7);
sdo_ibuf_8: IBUF port map ( O => vmm_sdo_vec_i(8), I => SDO_8);
----------------------------------------------------ENA-----------------------------------------------------------
ena_diff_1: OBUFDS port map ( O => ENA_1_P, OB => ENA_1_N, I => vmm_ena_vec_obuf(1));
ena_diff_2: OBUFDS port map ( O => ENA_2_P, OB => ENA_2_N, I => vmm_ena_vec_obuf(2));
ena_diff_3: OBUFDS port map ( O => ENA_3_P, OB => ENA_3_N, I => vmm_ena_vec_obuf(3));
ena_diff_4: OBUFDS port map ( O => ENA_4_P, OB => ENA_4_N, I => vmm_ena_vec_obuf(4));
ena_diff_5: OBUFDS port map ( O => ENA_5_P, OB => ENA_5_N, I => vmm_ena_vec_obuf(5));
ena_diff_6: OBUFDS port map ( O => ENA_6_P, OB => ENA_6_N, I => vmm_ena_vec_obuf(6));
ena_diff_7: OBUFDS port map ( O => ENA_7_P, OB => ENA_7_N, I => vmm_ena_vec_obuf(7));
ena_diff_8: OBUFDS port map ( O => ENA_8_P, OB => ENA_8_N, I => vmm_ena_vec_obuf(8));
----------------------------------------------------CKBC------------------------------------------------------------
ckbc_diff_1: OBUFDS port map ( O => CKBC_1_P, OB => CKBC_1_N, I => vmm_ckbc_vec(1));
ckbc_diff_2: OBUFDS port map ( O => CKBC_2_P, OB => CKBC_2_N, I => vmm_ckbc_vec(2));
ckbc_diff_3: OBUFDS port map ( O => CKBC_3_P, OB => CKBC_3_N, I => vmm_ckbc_vec(3));
ckbc_diff_4: OBUFDS port map ( O => CKBC_4_P, OB => CKBC_4_N, I => vmm_ckbc_vec(4));
ckbc_diff_5: OBUFDS port map ( O => CKBC_5_P, OB => CKBC_5_N, I => vmm_ckbc_vec(5));
ckbc_diff_6: OBUFDS port map ( O => CKBC_6_P, OB => CKBC_6_N, I => vmm_ckbc_vec(6));
ckbc_diff_7: OBUFDS port map ( O => CKBC_7_P, OB => CKBC_7_N, I => vmm_ckbc_vec(7));
ckbc_diff_8: OBUFDS port map ( O => CKBC_8_P, OB => CKBC_8_N, I => vmm_ckbc_vec(8));
----------------------------------------------------CKTP------------------------------------------------------------
cktp_diff_1: OBUFDS port map ( O => CKTP_1_P, OB => CKTP_1_N, I => vmm_cktp_vec(1));
cktp_diff_2: OBUFDS port map ( O => CKTP_2_P, OB => CKTP_2_N, I => vmm_cktp_vec(2));
cktp_diff_3: OBUFDS port map ( O => CKTP_3_P, OB => CKTP_3_N, I => vmm_cktp_vec(3));
cktp_diff_4: OBUFDS port map ( O => CKTP_4_P, OB => CKTP_4_N, I => vmm_cktp_vec(4));
cktp_diff_5: OBUFDS port map ( O => CKTP_5_P, OB => CKTP_5_N, I => vmm_cktp_vec(5));
cktp_diff_6: OBUFDS port map ( O => CKTP_6_P, OB => CKTP_6_N, I => vmm_cktp_vec(6));
cktp_diff_7: OBUFDS port map ( O => CKTP_7_P, OB => CKTP_7_N, I => vmm_cktp_vec(7));
cktp_diff_8: OBUFDS port map ( O => CKTP_8_P, OB => CKTP_8_N, I => vmm_cktp_vec(8));
----------------------------------------------------CKTK------------------------------------------------------------
cktk_diff_1: OBUFDS port map ( O => CKTK_1_P, OB => CKTK_1_N, I => cktk_out_vec(1));
cktk_diff_2: OBUFDS port map ( O => CKTK_2_P, OB => CKTK_2_N, I => cktk_out_vec(2));
cktk_diff_3: OBUFDS port map ( O => CKTK_3_P, OB => CKTK_3_N, I => cktk_out_vec(3));
cktk_diff_4: OBUFDS port map ( O => CKTK_4_P, OB => CKTK_4_N, I => cktk_out_vec(4));
cktk_diff_5: OBUFDS port map ( O => CKTK_5_P, OB => CKTK_5_N, I => cktk_out_vec(5));
cktk_diff_6: OBUFDS port map ( O => CKTK_6_P, OB => CKTK_6_N, I => cktk_out_vec(6));
cktk_diff_7: OBUFDS port map ( O => CKTK_7_P, OB => CKTK_7_N, I => cktk_out_vec(7));
cktk_diff_8: OBUFDS port map ( O => CKTK_8_P, OB => CKTK_8_N, I => cktk_out_vec(8));
----------------------------------------------------CKDT-------------------------------------------------------------
ckdt_diff_1: OBUFDS port map ( O => ckdt_1_P, OB => ckdt_1_N, I => ckdt_out_vec(1));
ckdt_diff_2: OBUFDS port map ( O => ckdt_2_P, OB => ckdt_2_N, I => ckdt_out_vec(2));
ckdt_diff_3: OBUFDS port map ( O => ckdt_3_P, OB => ckdt_3_N, I => ckdt_out_vec(3));
ckdt_diff_4: OBUFDS port map ( O => ckdt_4_P, OB => ckdt_4_N, I => ckdt_out_vec(4));
ckdt_diff_5: OBUFDS port map ( O => ckdt_5_P, OB => ckdt_5_N, I => ckdt_out_vec(5));
ckdt_diff_6: OBUFDS port map ( O => ckdt_6_P, OB => ckdt_6_N, I => ckdt_out_vec(6));
ckdt_diff_7: OBUFDS port map ( O => ckdt_7_P, OB => ckdt_7_N, I => ckdt_out_vec(7));
ckdt_diff_8: OBUFDS port map ( O => ckdt_8_P, OB => ckdt_8_N, I => ckdt_out_vec(8));
----------------------------------------------------DATA 0-------------------------------------------------------------
data0_diff_1: IBUFDS port map ( O => data0_in_vec(1), I => DATA0_1_P, IB => DATA0_1_N);
data0_diff_2: IBUFDS port map ( O => data0_in_vec(2), I => DATA0_2_P, IB => DATA0_2_N);
data0_diff_3: IBUFDS port map ( O => data0_in_vec(3), I => DATA0_3_P, IB => DATA0_3_N);
data0_diff_4: IBUFDS port map ( O => data0_in_vec(4), I => DATA0_4_P, IB => DATA0_4_N);
data0_diff_5: IBUFDS port map ( O => data0_in_vec(5), I => DATA0_5_P, IB => DATA0_5_N);
data0_diff_6: IBUFDS port map ( O => data0_in_vec(6), I => DATA0_6_P, IB => DATA0_6_N);
data0_diff_7: IBUFDS port map ( O => data0_in_vec(7), I => DATA0_7_P, IB => DATA0_7_N);
data0_diff_8: IBUFDS port map ( O => data0_in_vec(8), I => DATA0_8_P, IB => DATA0_8_N);
----------------------------------------------------DATA 1-------------------------------------------------------------
data1_diff_1: IBUFDS port map ( O => data1_in_vec(1), I => DATA1_1_P, IB => DATA1_1_N);
data1_diff_2: IBUFDS port map ( O => data1_in_vec(2), I => DATA1_2_P, IB => DATA1_2_N);
data1_diff_3: IBUFDS port map ( O => data1_in_vec(3), I => DATA1_3_P, IB => DATA1_3_N);
data1_diff_4: IBUFDS port map ( O => data1_in_vec(4), I => DATA1_4_P, IB => DATA1_4_N);
data1_diff_5: IBUFDS port map ( O => data1_in_vec(5), I => DATA1_5_P, IB => DATA1_5_N);
data1_diff_6: IBUFDS port map ( O => data1_in_vec(6), I => DATA1_6_P, IB => DATA1_6_N);
data1_diff_7: IBUFDS port map ( O => data1_in_vec(7), I => DATA1_7_P, IB => DATA1_7_N);
data1_diff_8: IBUFDS port map ( O => data1_in_vec(8), I => DATA1_8_P, IB => DATA1_8_N);
----------------------------------------------------TKI/TKO-------------------------------------------------------------
TKI_diff_1: OBUFDS port map ( O => TKI_P, OB => TKI_N, I => vmm_tki);
TKO_diff_1: IBUFDS port map ( O => tko_i, I => TKO_P, IB => TKO_N);
---------------------------------------------------CKART----------------------------------------------------------------
ckart_diff_1: OBUFDS port map ( O => CKART_1_P, OB => CKART_1_N, I => ckart_vec(1));
ckart_diff_2: OBUFDS port map ( O => CKART_2_P, OB => CKART_2_N, I => ckart_vec(2));
ckart_diff_3: OBUFDS port map ( O => CKART_3_P, OB => CKART_3_N, I => ckart_vec(3));
ckart_diff_4: OBUFDS port map ( O => CKART_4_P, OB => CKART_4_N, I => ckart_vec(4));
ckart_diff_5: OBUFDS port map ( O => CKART_5_P, OB => CKART_5_N, I => ckart_vec(5));
ckart_diff_6: OBUFDS port map ( O => CKART_6_P, OB => CKART_6_N, I => ckart_vec(6));
ckart_diff_7: OBUFDS port map ( O => CKART_7_P, OB => CKART_7_N, I => ckart_vec(7));
ckart_diff_8: OBUFDS port map ( O => CKART_8_P, OB => CKART_8_N, I => ckart_vec(8));
----------------------------------------------------ART----------------------------------------------------------------
art_diff_1: IBUFDS port map ( O => art_in_vec(1), I => ART_1_P, IB => ART_1_N);
--art_diff_2: IBUFDS port map ( O => art_in_vec(2), I => ART_2_P, IB => ART_2_N);
--art_diff_3: IBUFDS port map ( O => art_in_vec(3), I => ART_3_P, IB => ART_3_N);
--art_diff_4: IBUFDS port map ( O => art_in_vec(4), I => ART_4_P, IB => ART_4_N);
--art_diff_5: IBUFDS port map ( O => art_in_vec(5), I => ART_5_P, IB => ART_5_N);
--art_diff_6: IBUFDS port map ( O => art_in_vec(6), I => ART_6_P, IB => ART_6_N);
--art_diff_7: IBUFDS port map ( O => art_in_vec(7), I => ART_7_P, IB => ART_7_N);
--art_diff_8: IBUFDS port map ( O => art_in_vec(8), I => ART_8_P, IB => ART_8_N);
ckart_addc_buf: OBUFDS port map ( O => CKART_ADDC_P, OB => CKART_ADDC_N, I => ckart_vec(9));
----------------------------------------------------XADC----------------------------------------------------------------
xadc_mux0_obuf: OBUF port map (O => MuxAddr0, I => MuxAddr0_i);
xadc_mux1_obuf: OBUF port map (O => MuxAddr1, I => MuxAddr1_i);
xadc_mux2_obuf: OBUF port map (O => MuxAddr2, I => MuxAddr2_i);
xadc_mux3_obufds: OBUFDS port map (O => MuxAddr3_p, OB => MuxAddr3_n, I => MuxAddr3_p_i);
art_out_diff_1: OBUFDS port map (O => ART_OUT_P, OB => ART_OUT_N, I => art2);
rstn_obuf: OBUF port map (O => phy_rstn_out, I => phy_rstn);
-------------------------------------------------------------------
-- Processes --
-------------------------------------------------------------------
-- 1. synced_to_flowFSM
-- 2. sel_cs
-- 3. flow_fsm
-------------------------------------------------------------------
sync_fifo_init: process(userclk2)
begin
if(rising_edge(userclk2))then
glbl_fifo_init_s0 <= glbl_fifo_init;
glbl_fifo_init_s1 <= glbl_fifo_init_s0;
end if;
end process;
art_process: process(userclk2, art2)
begin
if rising_edge(userclk2) then
if art_cnt2 < 125 and art2 = '1' then
art_cnt2 <= art_cnt2 + 1;
elsif art_cnt2 = 125 then
reset_FF <= '1';
art_cnt2 <= art_cnt2 + 1;
else
art_cnt2 <= 0;
reset_FF <= '0';
end if;
end if;
end process;
FDCE_inst: FDCE
generic map (INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => art2, -- Data output
C => art_in_vec(1), -- Clock input
CE => '1', -- Clock enable input
CLR => reset_FF, -- Asynchronous clear input
D => '1' -- Data input
);
sel_cs_proc: process(sel_cs, vmm_cs_i)
begin
case sel_cs is
when "00" => vmm_cs_all <= '0';
when "01" => vmm_cs_all <= vmm_cs_i;
when "10" => vmm_cs_all <= vmm_cs_i;
when "11" => vmm_cs_all <= '1';
when others => vmm_cs_all <= '0';
end case;
end process;
flow_fsm: process(userclk2)
begin
if rising_edge(userclk2) then
if glbl_rst_i = '1' then
state <= IDLE;
elsif is_state = "0000" then
state <= IDLE;
else
case state is
when IDLE =>
is_state <= "1111";
conf_wen_i <= '0';
conf_ena_i <= '0';
start_conf_proc_int <= '0';
reply_enable <= '0';
cnt_vmm <= 1;
daq_enable_i <= '0';
rst_l0_buff_flow <= '1';
pf_rst_flow <= '0';
rstFIFO_flow <= '0';
tren <= '0';
vmm_ena_all <= '0';
vmm_tki <= '0';
ckbc_enable <= '0';
vmm_cktp_primary <= '0';
daq_vmm_ena_wen_enable <= x"00";
daq_cktk_out_enable <= x"00";
sel_cs <= "11"; -- drive CS high
if(vmm_conf = '1')then
state <= WAIT_FOR_CONF;
elsif(newIP_rdy = '1')then -- start new IP setup
if(wait_cnt = "00000111")then -- wait for safe assertion of multi-bit signal
wait_cnt <= (others => '0');
newIP_start <= '1';
state <= FLASH_init;
else
wait_cnt <= wait_cnt + 1;
newIP_start <= '0';
state <= IDLE;
end if;
elsif(xadc_conf_rdy = '1')then -- start XADC
if(wait_cnt = "00000111")then -- wait for safe assertion of multi-bit signal
wait_cnt <= (others => '0');
xadc_start <= '1';
state <= XADC_init;
else
wait_cnt <= wait_cnt + 1;
xadc_start <= '0';
state <= IDLE;
end if;
elsif(daq_on = '1' and daq_on_inhib = '0')then
state <= DAQ_INIT;
else
state <= IDLE;
wait_cnt <= (others => '0');
end if;
when WAIT_FOR_CONF =>
vmm_ena_all <= '0';
if(vmm_id_rdy = '1')then
if(wait_cnt = "00000111")then -- wait for safe assertion of multi-bit signal
wait_cnt <= (others => '0');
state <= CONFIGURE;
else
wait_cnt <= wait_cnt + 1;
state <= WAIT_FOR_CONF;
end if;
else
wait_cnt <= (others => '0');
state <= WAIT_FOR_CONF;
end if;
when CONFIGURE =>
is_state <= "0001";
sel_cs <= "01"; -- select CS from config
if(vmmConf_done = '1')then
state <= CONF_DONE;
else
state <= CONFIGURE;
end if;
conf_wen_i <= '1';
start_conf_proc_int <= '1';
when CONF_DONE =>
-- sel_cs <= "10"; -- select CS from config
vmm_ena_all <= '1';
is_state <= "0010";
if wait_cnt = "00101000" then
cnt_vmm <= cnt_vmm - 1;
if cnt_vmm = 1 then --VMM conf done
state <= SEND_CONF_REPLY;
else
state <= CONFIGURE_DELAY;
end if;
wait_cnt <= (others => '0');
else
wait_cnt <= wait_cnt + 1;
end if;
conf_wen_i <= '0';
when CONFIGURE_DELAY => -- Waits 100 ns to move to next configuration
is_state <= "1011";
if (wait_cnt >= "00010011") then
wait_cnt <= (others => '0');
vmm_ena_all <= '0';
sel_cs <= "00"; -- drive CS to gnd
state <= CONFIGURE;
else
wait_cnt <= wait_cnt + 1;
end if;
when SEND_CONF_REPLY =>
reply_enable <= '1';
sel_cs <= "00"; -- drive CS to gnd
vmm_ena_all <= '0';
if(reply_done = '1' and UDPDone = '1')then
state <= IDLE;
else
state <= SEND_CONF_REPLY;
end if;
when DAQ_INIT =>
is_state <= "0011";
--for I in 1 to 100 loop
vmm_cktp_primary <= '1';
--end loop;
sel_cs <= "11"; -- drive CS high
vmm_ena_all <= '1';
rst_l0_buff_flow <= '0';
tren <= '0';
daq_vmm_ena_wen_enable <= x"ff";
daq_cktk_out_enable <= x"ff";
daq_enable_i <= '1';
rstFIFO_flow <= '1';
pf_rst_flow <= '1';
if(daq_on = '0')then -- Reset came
daq_vmm_ena_wen_enable <= x"00";
daq_cktk_out_enable <= x"00";
daq_enable_i <= '0';
pf_rst_flow <= '0';
state <= IDLE;
elsif(wait_cnt < "01100100")then
wait_cnt <= wait_cnt + 1;
state <= DAQ_INIT;
elsif(wait_cnt = "01100100")then
wait_cnt <= (others => '0');
state <= TRIG;
end if;
when TRIG =>
is_state <= "0100";
if(vmmReadoutMode = '0')then
vmm_tki <= '1';
else
vmm_tki <= '0';
end if;
vmm_cktp_primary <= '0';
rstFIFO_flow <= '0';
pf_rst_flow <= '0';
tren <= '1';
state <= DAQ;
when DAQ =>
is_state <= "0101";
ckbc_enable <= '1';
if(daq_on = '0')then -- Reset came
daq_enable_i <= '0';
state <= DAQ_INIT;
end if;
when XADC_init =>
is_state <= "0110";
if(xadc_busy = '1')then -- XADC got the message, wait for busy to go low
xadc_start <= '0';
state <= XADC_wait;
else -- XADC didn't get the message, wait and keep high
xadc_start <= '1';
state <= XADC_init;
end if;
when XADC_wait => -- wait for XADC to finish and go to IDLE
if(xadc_busy = '0')then
state <= IDLE;
else
state <= XADC_wait;
end if;
when FLASH_init =>
if(flash_busy = '1')then -- AXI4SPI got the message, wait for busy to go low
newIP_start <= '0';
state <= FLASH_wait;
else -- AXI4SPI didn't get the message, wait and keep high
newIP_start <= '1';
state <= FLASH_init;
end if;
when FLASH_wait => -- wait for AXI4SPI to finish and go to IDLE
if(flash_busy = '0')then
state <= IDLE;
else
state <= FLASH_wait;
end if;
when others =>
state <= IDLE;
is_state <= "0110";
end case;
end if;
end if;
end process;
mmcm_reset <= glbl_rst_i; -- reset;
glbl_rstn <= not glbl_rst_i;
phy_int <= '1';
local_gtx_reset <= glbl_rst_i or rx_reset or tx_reset;
cktp_enable <= '1' when ((state = DAQ and trig_mode_int = '0') or (state = XADC_wait and trig_mode_int = '0')) else '0';
inhibit_conf <= '0' when (state = IDLE) else '1';
vmm_bitmask_1VMM <= "11111111";
vmm_bitmask <= vmm_bitmask_8VMM when (is_mmfe8 = '1') else vmm_bitmask_1VMM;
pf_newCycle <= tr_out_i;
CH_TRIGGER_i <= not CH_TRIGGER;
TRIGGER_OUT_P <= art2;
TRIGGER_OUT_N <= not art2;
MO <= MO_i;
rst_l0_buff <= rst_l0_buff_flow or rst_l0_pf or glbl_rst_i;
pf_rst_final <= pf_rst_flow or glbl_rst_i;
glbl_fifo_init <= not phy_rstn;
rstFIFO_top <= rstFIFO_flow or glbl_fifo_init;
-- configuration assertion
vmm_cs_vec_obuf(1) <= vmm_cs_all;
vmm_cs_vec_obuf(2) <= vmm_cs_all;
vmm_cs_vec_obuf(3) <= vmm_cs_all;
vmm_cs_vec_obuf(4) <= vmm_cs_all;
vmm_cs_vec_obuf(5) <= vmm_cs_all;
vmm_cs_vec_obuf(6) <= vmm_cs_all;
vmm_cs_vec_obuf(7) <= vmm_cs_all;
vmm_cs_vec_obuf(8) <= vmm_cs_all;
vmm_sck_vec_obuf(1) <= vmm_sck_all and vmm_bitmask(0);
vmm_sck_vec_obuf(2) <= vmm_sck_all and vmm_bitmask(1);
vmm_sck_vec_obuf(3) <= vmm_sck_all and vmm_bitmask(2);
vmm_sck_vec_obuf(4) <= vmm_sck_all and vmm_bitmask(3);
vmm_sck_vec_obuf(5) <= vmm_sck_all and vmm_bitmask(4);
vmm_sck_vec_obuf(6) <= vmm_sck_all and vmm_bitmask(5);
vmm_sck_vec_obuf(7) <= vmm_sck_all and vmm_bitmask(6);
vmm_sck_vec_obuf(8) <= vmm_sck_all and vmm_bitmask(7);
vmm_sdi_vec_obuf(1) <= vmm_sdi_all and vmm_bitmask(0);
vmm_sdi_vec_obuf(2) <= vmm_sdi_all and vmm_bitmask(1);
vmm_sdi_vec_obuf(3) <= vmm_sdi_all and vmm_bitmask(2);
vmm_sdi_vec_obuf(4) <= vmm_sdi_all and vmm_bitmask(3);
vmm_sdi_vec_obuf(5) <= vmm_sdi_all and vmm_bitmask(4);
vmm_sdi_vec_obuf(6) <= vmm_sdi_all and vmm_bitmask(5);
vmm_sdi_vec_obuf(7) <= vmm_sdi_all and vmm_bitmask(6);
vmm_sdi_vec_obuf(8) <= vmm_sdi_all and vmm_bitmask(7);
vmm_ena_vec_obuf(1) <= vmm_ena_all;
vmm_ena_vec_obuf(2) <= vmm_ena_all;
vmm_ena_vec_obuf(3) <= vmm_ena_all;
vmm_ena_vec_obuf(4) <= vmm_ena_all;
vmm_ena_vec_obuf(5) <= vmm_ena_all;
vmm_ena_vec_obuf(6) <= vmm_ena_all;
vmm_ena_vec_obuf(7) <= vmm_ena_all;
vmm_ena_vec_obuf(8) <= vmm_ena_all;
--ila_top: ila_top_level
-- port map (
-- clk => userclk2,
-- probe0 => vmmSignalsProbe,
-- probe1 => triggerETRProbe,
-- probe2 => configurationProbe,
-- probe3 => readoutProbe,
-- probe4 => dataOutProbe,
-- probe5 => flowProbe
-- );
--ila_top: ila_overview
-- port map (
-- clk => userclk2,
-- probe0 => overviewProbe
-- );
--VIO_DEFAULT_IP: vio_ip
-- PORT MAP (
-- clk => clk_50,
-- probe_out0 => default_IP,
-- probe_out1 => default_MAC
-- );
-- overviewProbe(3 downto 0) <= is_state;
-- overviewProbe(8 downto 4) <= pf_dbg_st;
-- overviewProbe(9) <= vmmWordReady_i;
-- overviewProbe(10) <= vmmEventDone_i;
-- overviewProbe(11) <= daq_enable_i;
-- overviewProbe(12) <= pf_trigVmmRo;
-- overviewProbe(14 downto 13) <= (others => '0');
-- overviewProbe(15) <= rd_ena_buff;
-- overviewProbe(19 downto 16) <= dt_state;
-- overviewProbe(23 downto 20) <= FIFO2UDP_state;
-- overviewProbe(24) <= CKTP_glbl;
-- overviewProbe(25) <= UDPDone;
-- overviewProbe(26) <= CKBC_glbl;
-- overviewProbe(27) <= tr_out_i;
-- overviewProbe(29 downto 28) <= (others => '0');
-- overviewProbe(30) <= level_0;
-- overviewProbe(31) <= rst_l0_pf;
-- overviewProbe(47 downto 32) <= vmmWord_i;
-- overviewProbe(51 downto 48) <= dt_cntr_st;
-- overviewProbe(59 downto 52) <= linkHealth_bmsk;
-- overviewProbe(63 downto 60) <= (others => '0');
vmmSignalsProbe(7 downto 0) <= (others => '0');
vmmSignalsProbe(15 downto 8) <= cktk_out_vec;
vmmSignalsProbe(23 downto 16) <= ckdt_out_vec;
vmmSignalsProbe(31 downto 24) <= data0_in_vec;
vmmSignalsProbe(32) <= '0';
vmmSignalsProbe(33) <= ckdt_out_vec(1);
vmmSignalsProbe(34) <= data0_in_vec(1);
vmmSignalsProbe(35) <= data1_in_vec(1);
vmmSignalsProbe(36) <= vmm_cs_all;
vmmSignalsProbe(37) <= '0';
vmmSignalsProbe(38) <= vmm_ena_all;
vmmSignalsProbe(39) <= '0';
vmmSignalsProbe(40) <= tko_i;
vmmSignalsProbe(41) <= vmm_ena_all;
vmmSignalsProbe(42) <= art2;
vmmSignalsProbe(43) <= '0';
vmmSignalsProbe(44) <= art_in_vec(1);
vmmSignalsProbe(63 downto 45) <= (others => '0');
triggerETRProbe(0) <= '0';
triggerETRProbe(1) <= tren;
triggerETRProbe(2) <= tr_hold;
triggerETRProbe(3) <= ext_trigger_in;
triggerETRProbe(4) <= trig_mode_int;
triggerETRProbe(7 downto 5) <= state_rst_etr_i;
triggerETRProbe(15 downto 8) <= (others => '0');
triggerETRProbe(23 downto 16) <= (others => '0');
triggerETRProbe(24) <= rst_etr_i;
triggerETRProbe(25) <= etr_reset_latched;
triggerETRProbe(26) <= trigger_i;
triggerETRProbe(38 downto 27) <= glBCID_i;
triggerETRProbe(39) <= CH_TRIGGER_i;
triggerETRProbe(40) <= reset_FF;
triggerETRProbe(63 downto 41) <= (others => '0');
configurationProbe(0) <= start_conf_proc_int;
configurationProbe(1) <= conf_wen_i;
configurationProbe(2) <= conf_di_i;
configurationProbe(18 downto 3) <= (others => '0');
configurationProbe(50 downto 19) <= myIP;
configurationProbe(63 downto 51) <= (others => '0');
readoutProbe(0) <= pf_newCycle;
readoutProbe(1) <= pf_rst_FIFO;
readoutProbe(4 downto 2) <= pf_vmmIdRo;
readoutProbe(5) <= pfBusy_i;
readoutProbe(6) <= rst_vmm;
readoutProbe(7) <= daqFIFO_wr_en_i;
readoutProbe(8) <= daq_wr_en_i;
readoutProbe(24 downto 9) <= vmmWord_i;
readoutProbe(40 downto 25) <= daqFIFO_din_i;
readoutProbe(63 downto 41) <= (others => '0');
dataOutProbe(15 downto 0) <= daq_data_out_i;
dataOutProbe(63 downto 16) <= (others => '0');
flowProbe(3 downto 0) <= is_state;
flowProbe(7 downto 4) <= (others => '0');
flowProbe(11 downto 8) <= (others => '0');
flowProbe(12) <= daq_enable_i;
flowProbe(13) <= xadc_busy;
flowProbe(21 downto 14) <= daq_vmm_ena_wen_enable;
flowProbe(22) <= daqFIFO_reset;
flowProbe(23) <= rstFIFO_top;
flowProbe(24) <= ckbc_enable;
flowProbe(63 downto 25) <= (others => '0');
end Behavioral;
| gpl-3.0 | 176a2b7225b22671d97972f429f03099 | 0.43997 | 3.890351 | false | false | false | false |
atti92/heterogenhomework | project1/solution1/syn/vhdl/fir_hw_coeff_hw_V.vhd | 1 | 5,854 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.2
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fir_hw_coeff_hw_V_rom is
generic(
dwidth : integer := 15;
awidth : integer := 7;
mem_size : integer := 128
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of fir_hw_coeff_hw_V_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 => "000000000011001", 1 => "111111111101010", 2 => "111111111010100",
3 => "111111110101110", 4 => "111111101110100", 5 => "111111100100110",
6 => "111111010111111", 7 => "111111000111101", 8 => "111110110100000",
9 => "111110011100111", 10 => "111110000010100", 11 => "111101100101011",
12 => "111101000110001", 13 => "111100100101101", 14 => "111100000101001",
15 => "111011100110000", 16 => "111011001001100", 17 => "111010110001100",
18 => "111010011111100", 19 => "111010010100110", 20 => "111010010010111",
21 => "111010011010101", 22 => "111010101100110", 23 => "111011001001010",
24 => "111011101111111", 25 => "111100011111110", 26 => "111101010111010",
27 => "111110010100011", 28 => "111111010100110", 29 => "000000010101011",
30 => "000001010011011", 31 => "000010001011101", 32 => "000010111010111",
33 => "000011011110100", 34 => "000011110100011", 35 => "000011111010101",
36 => "000011110000100", 37 => "000011010110001", 38 => "000010101100010",
39 => "000001110101001", 40 => "000000110011011", 41 => "111111101010110",
42 => "111110011111110", 43 => "111101010111000", 44 => "111100010101110",
45 => "111011100000111", 46 => "111010111101001", 47 => "111010101110100",
48 => "111010111000011", 49 => "111011011100110", 50 => "111100011100110",
51 => "111101110111111", 52 => "111111101100001", 53 => "000001110110100",
54 => "000100010010100", 55 => "000110111010100", 56 => "001001101000100",
57 => "001100010101011", 58 => "001110111010001", 59 => "010001010000000",
60 => "010011010000100", 61 => "010100110110010", 62 => "010101111100101",
63 to 64=> "010110100000101", 65 => "010101111100101", 66 => "010100110110010",
67 => "010011010000100", 68 => "010001010000000", 69 => "001110111010001",
70 => "001100010101011", 71 => "001001101000100", 72 => "000110111010100",
73 => "000100010010100", 74 => "000001110110100", 75 => "111111101100001",
76 => "111101110111111", 77 => "111100011100110", 78 => "111011011100110",
79 => "111010111000011", 80 => "111010101110100", 81 => "111010111101001",
82 => "111011100000111", 83 => "111100010101110", 84 => "111101010111000",
85 => "111110011111110", 86 => "111111101010110", 87 => "000000110011011",
88 => "000001110101001", 89 => "000010101100010", 90 => "000011010110001",
91 => "000011110000100", 92 => "000011111010101", 93 => "000011110100011",
94 => "000011011110100", 95 => "000010111010111", 96 => "000010001011101",
97 => "000001010011011", 98 => "000000010101011", 99 => "111111010100110",
100 => "111110010100011", 101 => "111101010111010", 102 => "111100011111110",
103 => "111011101111111", 104 => "111011001001010", 105 => "111010101100110",
106 => "111010011010101", 107 => "111010010010111", 108 => "111010010100110",
109 => "111010011111100", 110 => "111010110001100", 111 => "111011001001100",
112 => "111011100110000", 113 => "111100000101001", 114 => "111100100101101",
115 => "111101000110001", 116 => "111101100101011", 117 => "111110000010100",
118 => "111110011100111", 119 => "111110110100000", 120 => "111111000111101",
121 => "111111010111111", 122 => "111111100100110", 123 => "111111101110100",
124 => "111111110101110", 125 => "111111111010100", 126 => "111111111101010",
127 => "000000000011001" );
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity fir_hw_coeff_hw_V is
generic (
DataWidth : INTEGER := 15;
AddressRange : INTEGER := 128;
AddressWidth : INTEGER := 7);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of fir_hw_coeff_hw_V is
component fir_hw_coeff_hw_V_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
fir_hw_coeff_hw_V_rom_U : component fir_hw_coeff_hw_V_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
| gpl-2.0 | d95c3201f336f03e8ac0a1385893ec2f | 0.598223 | 3.858932 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Multirate/tb_multirate_fir_filter.vhd | 1 | 2,863 | --------------------------------------------------------------------------------------------------
-- Multirate Fir Filter Testbench
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.tb_read_csv_pkg.all;
use work.tb_write_csv_pkg.all;
use work.dsp_pkg.all;
use work.multirate_fir_filter_pkg.all;
--This module is a test-bench for simulating the fir filter
entity tb_multirate_fir_filter is
end tb_multirate_fir_filter;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture sim of tb_multirate_fir_filter is
constant INPUT_FILE : string
:= "X:\Education\Masters Thesis\matlab\multirate\mixedsigs.csv";
constant OUTPUT_FILE : string
:= "X:\Education\Masters Thesis\matlab\multirate\interpolated_filtered_sig.csv";
signal rst : std_logic := '0';
signal clk_10ns : std_logic := '0';
signal clk_20ns : std_logic := '0';
signal sig_in : sig := (others => '0');
signal sig_out : sig := (others => '0');
begin
--Instantiate clock generator
clk1 : tb_clockgen
generic map(PERIOD => 10ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_10ns);
clk2 : tb_clockgen
generic map(PERIOD => 20ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_20ns);
--Instantiate file reader
reader : tb_read_csv
generic map(FILENAME => INPUT_FILE)
port map( clk => clk_10ns,
sig(data) => sig_in);
--Unit under test
uut : multirate_fir_filter
generic map(h => LOW_PASS_41)
port map( clk_low => clk_20ns,
clk_high => clk_10ns,
rst => rst,
x => sig_in,
y => sig_out);
--Instantiate a file writer
writer : tb_write_csv
generic map(FILENAME => OUTPUT_FILE)
port map( clk => clk_10ns,
data => std_logic_vector(sig_out));
--Main Process
--TODO: Add a check for end of file, once reached terminate simulation.
main: process
begin
rst <= '1';
wait for 36ns;
rst <= '0';
wait;
end process;
end sim;
| mit | 42a46ddc13d515bc1785490345e3485a | 0.433461 | 4.537242 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/configuration/cktp_gen.vhd | 1 | 10,146 | ----------------------------------------------------------------------------------------
-- Company: University of Washington
-- Engineer: Lev Kurilenko
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Lev Kurilenko
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 25.10.2016 15:47:35
-- Design Name:
-- Module Name: cktp_gen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: CKTP Generator
--
-- Dependencies:
--
-- Changelog:
-- 20.02.2017 Added dynamic CKBC input frequency and reset circuitry. Changed the input
-- clock frequency to 160 Mhz. (Christos Bakalis)
-- 27.02.2017 Added cktp_primary signal from flow_fsm. (Christos Bakalis)
-- 09.03.2017 Changed input bus widths and introduced integer range for logic and routing
-- optimization. (Christos Bakalis)
-- 14.03.2017 Added a cktp_start delay process. (Christos Bakalis)
--
----------------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cktp_gen is
port(
clk_160 : in std_logic;
cktp_start : in std_logic;
cktp_primary : in std_logic;
vmm_ckbc : in std_logic; -- CKBC clock currently dynamic
ckbc_mode : in std_logic;
ckbc_freq : in std_logic_vector(5 downto 0);
skew : in std_logic_vector(4 downto 0);
pulse_width : in std_logic_vector(11 downto 0);
period : in std_logic_vector(21 downto 0);
CKTP : out std_logic
);
end cktp_gen;
architecture Behavioral of cktp_gen is
--is_state <= "0101";
signal cktp_state : std_logic_vector(3 downto 0) := (others => '0');
signal cktp_cnt : integer range -2 to 2_100_000:= 0;
signal vmm_cktp : std_logic := '0';
signal cktp_start_i : std_logic := '0'; -- Internal connection to 2-Flip-Flop Synchronizer
signal cktp_start_sync : std_logic := '0'; -- Synchronized output from Synchronizer
signal cktp_start_final : std_logic := '0';
signal cktp_primary_i : std_logic := '0';
signal cktp_primary_sync : std_logic := '0';
signal cktp_start_aligned : std_logic := '0'; -- CKTP_start signal aligned to CKBC clock
signal align_cnt : unsigned(7 downto 0) := (others => '0'); -- Used for aligning with the CKBC
signal align_cnt_thresh : unsigned(7 downto 0) := (others => '0');
signal start_align_cnt : std_logic := '0'; --
signal cnt_delay : unsigned(3 downto 0) := (others => '0');
signal ckbc_mode_i : std_logic := '0';
signal ckbc_mode_sync : std_logic := '0';
attribute ASYNC_REG : string;
attribute ASYNC_REG of cktp_start_i : signal is "TRUE";
attribute ASYNC_REG of cktp_start_sync : signal is "TRUE";
attribute ASYNC_REG of cktp_primary_i : signal is "TRUE";
attribute ASYNC_REG of cktp_primary_sync : signal is "TRUE";
attribute ASYNC_REG of ckbc_mode_i : signal is "TRUE";
attribute ASYNC_REG of ckbc_mode_sync : signal is "TRUE";
begin
--period <= x"43200"; -- Hardcode 320,000 cycles at 320 MHz to give a period of 1ms
CKTP <= vmm_cktp;
--testPulse_proc: process(clk_10_phase45) -- 10MHz/#states.
-- begin
-- if rising_edge(clk_10_phase45) then
-- if state = DAQ and trig_mode_int = '0' then
-- case cktp_state is
-- when 0 to 9979 =>
-- cktp_state <= cktp_state + 1;
-- vmm_cktp <= '0';
-- when 9980 to 10000 =>
-- cktp_state <= cktp_state + 1;
-- vmm_cktp <= '1';
-- when others =>
-- cktp_state <= 0;
-- end case;
-- else
-- vmm_cktp <= '0';
-- end if;
-- end if;
--end process;
synchronizer_proc: process(vmm_ckbc, cktp_start_final)
begin
if(cktp_start_final = '0')then
start_align_cnt <= '0';
elsif rising_edge(vmm_ckbc) then
start_align_cnt <= '1';
--if (cktp_start_sync = '1') then
-- cktp_start_aligned <= '1';
-- --if (unsigned(skew) = "00000") then -- Set CKTP signal as soon as rising edge of CKBC arrives if skew = 0
-- -- vmm_cktp <= '1';
-- --end if;
--else
-- cktp_start_aligned <= '0';
--end if;
end if;
end process;
sync160_proc: process(clk_160)
begin
if(rising_edge(clk_160))then
cktp_start_i <= cktp_start;
cktp_start_sync <= cktp_start_i;
cktp_primary_i <= cktp_primary;
cktp_primary_sync <= cktp_primary_i;
ckbc_mode_i <= ckbc_mode;
ckbc_mode_sync <= ckbc_mode_i;
end if;
end process;
-- delay assertion of cktp start
cktpEnableDelayer: process(clk_160)
begin
if(rising_edge(clk_160))then
if(cktp_start_sync = '1')then
if(cnt_delay < "1110")then
cnt_delay <= cnt_delay + 1;
cktp_start_final <= '0';
else
cktp_start_final <= '1';
end if;
else
cnt_delay <= (others => '0');
cktp_start_final <= '0';
end if;
end if;
end process;
testPulse_proc: process(clk_160) -- 160 MHz
begin
if rising_edge(clk_160) then
if(cktp_start_final = '0' and cktp_primary_sync = '0')then
cktp_cnt <= 0;
vmm_cktp <= '0';
cktp_start_aligned <= '0';
align_cnt <= (others => '0');
cktp_state <= (others => '0');
elsif(cktp_primary_sync = '1')then -- from flow_fsm. keep cktp high for readout initialization
vmm_cktp <= '1';
else
if start_align_cnt = '1' or ckbc_mode_sync = '1' then -- Start alignment counter on rising edge of CKBC
if align_cnt < align_cnt_thresh then
align_cnt <= align_cnt + 1;
else
align_cnt <= (others => '0');
end if;
if ckbc_mode_sync = '1' then -- Just send periodic CKTPs if @ ckbc mode
cktp_start_aligned <= '1';
elsif cktp_start_final = '0' then -- Align CKTP generation to rising edge of CKBC if CKTPs are enabled @ top
cktp_start_aligned <= '0';
elsif (align_cnt = align_cnt_thresh) then
cktp_start_aligned <= '1';
if unsigned(skew) = "00000" then -- Set CKTP signal as soon as rising edge of CKBC arrives if skew = 0
vmm_cktp <= '1';
end if;
end if;
end if;
if cktp_start_aligned = '1' then
if (cktp_cnt < (to_integer(unsigned(skew)) - 1 ) and (cktp_cnt /= to_integer(unsigned(skew)))) then
cktp_state <= "0000";
vmm_cktp <= '0';
cktp_cnt <= cktp_cnt + 1;
elsif ( (cktp_cnt >= to_integer((unsigned(skew))) - 1) and (cktp_cnt <= (to_integer(unsigned(skew)) + to_integer(unsigned(pulse_width)) - 2) ) ) then
cktp_state <= "0001";
vmm_cktp <= '1';
cktp_cnt <= cktp_cnt + 1;
-- Uncomment if period needs to be hardcoded
--elsif ( (cktp_cnt > ( unsigned(skew) + unsigned(pulse_width) - 2) ) and (cktp_cnt <= 320000 - 2) ) then
elsif ( (cktp_cnt > ( to_integer(unsigned(skew)) + to_integer(unsigned(pulse_width)) - 2) ) and (cktp_cnt <= to_integer(unsigned(period)) - 2) ) then
cktp_state <= "0010";
vmm_cktp <= '0';
cktp_cnt <= cktp_cnt + 1;
else
cktp_state <= "0011";
cktp_cnt <= 0;
end if;
else
cktp_state <= "1111";
cktp_cnt <= 0;
end if;
end if;
end if;
end process;
ckbc_freq_proc: process(ckbc_freq)
begin
case ckbc_freq is
when "001010" => -- 10 Mhz
align_cnt_thresh <= "00001111"; -- (16 - 1)
when "010100" => -- 20 Mhz
align_cnt_thresh <= "00000111"; -- (8 - 1)
when "101000" => -- 40 Mhz
align_cnt_thresh <= "00000011"; -- (4 - 1)
when others =>
align_cnt_thresh <= "11111111";
end case;
end process;
end Behavioral; | gpl-3.0 | 59ec8ea063ea07711fade56d063bd405 | 0.48768 | 4.029388 | false | false | false | false |
tdotu/ra | testentity.vhd | 1 | 6,943 | LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
--FPGA main entity
ENTITY FirstProject IS
PORT (
SW : IN std_logic_vector(17 downto 0);
KEY : IN std_logic_vector(3 downto 0);
LEDG : OUT std_logic_vector(7 downto 0);
LEDR : OUT std_logic_vector(17 downto 0);
HEX0 : OUT std_logic_vector(6 downto 0);
HEX1 : OUT std_logic_vector(6 downto 0);
HEX2 : OUT std_logic_vector(6 downto 0);
HEX3 : OUT std_logic_vector(6 downto 0);
HEX4 : OUT std_logic_vector(6 downto 0);
HEX5 : OUT std_logic_vector(6 downto 0);
HEX6 : OUT std_logic_vector(6 downto 0);
HEX7 : OUT std_logic_vector(6 downto 0);
clock_50 : IN std_logic
);
END FirstProject ;
ARCHITECTURE behavior OF FirstProject IS
--components
COMPONENT memoryBank IS
GENERIC
(
adressWidth : integer;
memorySize : integer;
wordLength : integer
);
PORT
(
adress : IN std_logic_vector(adressWidth-1 downto 0);
writeBit : IN std_logic; -- if 1 then write input to adressed dword
input : IN std_logic_vector(wordLength-1 downto 0);
output : OUT std_logic_vector(wordLength-1 downto 0) -- value of the selected dword
);
END COMPONENT;
COMPONENT ALU IS
GENERIC
(
size : integer
);
PORT
(
input0 : IN std_logic_vector(size-1 downto 0);
input1 : IN std_logic_vector(size-1 downto 0);
control : IN std_logic_vector(3 downto 0);
clock : IN std_logic;
output : OUT std_logic_vector(size-1 downto 0);
zero : OUT std_logic
);
END COMPONENT;
COMPONENT registerBlock IS
GENERIC
(
regSize : integer
);
PORT
(
regWrite : IN std_logic;
read0 : IN std_logic_vector(4 downto 0);
read1 : IN std_logic_vector(4 downto 0);
write0 : IN std_logic_vector(4 downto 0);
input0 : IN std_logic_vector(regSize-1 downto 0);
output0 : OUT std_logic_vector(regSize-1 downto 0);
output1 : OUT std_logic_vector(regSize-1 downto 0)
);
END COMPONENT;
COMPONENT codeBank IS
PORT
(
adress : IN std_logic_vector(31 downto 0);
output : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT reg IS
GENERIC
(
width : integer
);
PORT
(
clock : IN std_logic;
change : IN std_logic_vector(width-1 downto 0);
state : OUT std_logic_vector(width-1 downto 0)
);
END COMPONENT;
COMPONENT genAdder IS
GENERIC(
value_len : integer
);
PORT(
value0 : IN std_logic_vector(value_len-1 downto 0);
value1 : IN std_logic_vector(value_len-1 downto 0);
output : OUT std_logic_vector(value_len-1 downto 0);
overflow : OUT std_logic
);
END COMPONENT;
COMPONENT increment IS
GENERIC
(
length : integer
);
PORT
(
input : IN std_logic_vector(length-1 downto 0);
output : OUT std_logic_vector(length-1 downto 0);
overflow : OUT std_logic
);
END COMPONENT;
COMPONENT sevenseghex IS
PORT(
nibble : IN std_logic_vector(3 downto 0);
segments : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
COMPONENT control IS
PORT
(
instruction : IN std_logic_vector(5 downto 0);
RegDst : OUT std_logic;
Branch : OUT std_logic_vector(1 downto 0);
MemtoReg : OUT std_logic;
ALUOp : OUT std_logic_vector(3 downto 0);
MemWrite : OUT std_logic;
ALUSrc : OUT std_logic;
RegWrite : OUT std_logic
);
END COMPONENT;
SIGNAL memAdress : std_logic_vector(31 downto 0);
SIGNAL memIn : std_logic_vector(31 downto 0);
SIGNAL memOut : std_logic_vector(31 downto 0);
SIGNAL aluIn0 : std_logic_vector(31 downto 0);
SIGNAL aluIn1 : std_logic_vector(31 downto 0);
SIGNAL aluControl : std_logic_vector(3 downto 0);
SIGNAL aluOut : std_logic_vector(31 downto 0);
SIGNAL aluZero : std_logic;
SIGNAL regW : std_logic;
SIGNAL regRead0 : std_logic_vector(4 downto 0);
SIGNAL regRead1 : std_logic_vector(4 downto 0);
SIGNAL regWrite0 : std_logic_vector(4 downto 0);
SIGNAL regIn0 : std_logic_vector(31 downto 0);
SIGNAL regOut0 : std_logic_vector(31 downto 0);
SIGNAL regOut1 : std_logic_vector(31 downto 0);
SIGNAL RegDst : std_logic;
SIGNAL Branch : std_logic_vector(1 downto 0);
SIGNAL MemToReg : std_logic;
SIGNAL ALUOp : std_logic_vector(3 downto 0);
SIGNAL MemWrite : std_logic;
SIGNAL ALUSrc : std_logic;
SIGNAL RegWrite : std_logic;
SIGNAL codeAdress : std_logic_vector(31 downto 0);
SIGNAL codeOut : std_logic_vector(31 downto 0);
SIGNAL pcChange : std_logic_vector(31 downto 0);
SIGNAL newPC : std_logic_vector(31 downto 0);
SIGNAL nextCmd : std_logic_vector(31 downto 0);
SIGNAL jmpTarget : std_logic_vector(31 downto 0);
SIGNAL altALUIn : std_logic_vector(31 downto 0);
SIGNAL clock : std_logic;
SIGNAL dsp : std_logic_vector(15 downto 0);
BEGIN
mem: memoryBank GENERIC MAP(32, 64, 32) PORT MAP(memAdress, MemWrite, memIn, memOut);
code : codeBank PORT MAP(codeAdress, codeOut);
palu : ALU GENERIC MAP(32) PORT MAP(aluIn0, aluIn1, aluControl, clock, aluOut, aluZero);
regFile : registerBlock GENERIC MAP(32) PORT MAP(regW, regRead0, regRead1, regWrite0, regIn0, regOut0, regOut1);
pc : reg GENERIC MAP(32) PORT MAP(clock, newPC, codeAdress);
cpinc : increment GENERIC MAP(32) PORT MAP(codeAdress, nextCmd, LEDG(0));
jmp : genAdder GENERIC MAP(32) PORT MAP(nextCmd, altALUIn, jmpTarget, LEDG(1));
ctrl : control PORT MAP(codeOut(31 downto 26), RegDst, Branch, MemToReg, ALUOp, MemWrite, ALUSrc, RegWrite);
clock <= NOT KEY(0);
regW <= RegWrite;
memAdress <= aluOut;
memIn <= regOut1;
aluIn0 <= regOut0;
aluControl <= aluOp;
regRead0 <= codeOut(25 downto 21);
regRead1 <= codeOut(20 downto 16);
altALUIn <= (31 downto 16 => codeOut(15)) & codeOut(15 downto 0);
LEDR <= SW;
LEDG(2) <= RegWrite;
hexseg0 : sevenseghex PORT MAP(regIn0(3 downto 0), HEX0);
hexseg1 : sevenseghex PORT MAP(regIn0(7 downto 4), HEX1);
hexseg2 : sevenseghex PORT MAP(regWrite0(3 downto 0), HEX2);
hexseg3 : sevenseghex PORT MAP(dsp(3 downto 0), HEX3);
hexseg4 : sevenseghex PORT MAP(codeAdress(3 downto 0), HEX4);
hexseg5 : sevenseghex PORT MAP(codeAdress(7 downto 4), HEX5);
hexseg6 : sevenseghex PORT MAP(codeAdress(11 downto 8), HEX6);
hexseg7 : sevenseghex PORT MAP(codeAdress(15 downto 12), HEX7);
WITH ALUSrc SELECT
aluIn1 <= regOut1 WHEN '0',
altALUIn WHEN '1',
(OTHERS => '0') WHEN OTHERS;
WITH MemToReg SELECT
regIn0 <= aluOut WHEN '0',
memOut WHEN '1',
(OTHERS => '0') WHEN OTHERS;
WITH RegDst SELECT
regWrite0 <= codeOut(20 downto 16) WHEN '0',
codeOut(15 downto 11) WHEN '1',
(OTHERS => '0') WHEN OTHERS;
WITH memAdress SELECT
dsp <= memIn(15 downto 0) WHEN (OTHERS => '0'),
dsp WHEN OTHERS;
WITH (Branch & aluZero) SELECT
pcChange <= jmpTarget WHEN "100",
jmpTarget WHEN "111",
nextCmd WHEN OTHERS;
WITH KEY(1) SELECT
newPC <= pcChange WHEN '1',
(OTHERS => '0') WHEN OTHERS;
END behavior;
| gpl-3.0 | c881dc8440626cb4e950f9b61e4f8e13 | 0.665706 | 3.065342 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Scrambler/descrambler.vhd | 1 | 3,604 | ----------------------------------------------------------------------------------------------------
-- Data Descrambler
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
----------------------------------------------------------------------------------------------------
-- PACKAGE
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package descrambler_pkg is
component descrambler is
port( clk : in std_logic;
rst : in std_logic;
poly_mask : in std_logic_vector;
seed : in std_logic_vector;
scrambled_datain : in std_logic_vector;
unscrambled_dataout : out std_logic_vector);
end component;
end package;
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.lfsr_pkg.all;
--This entity uses an LFSR to descramble the data. When using a scrambler, ensure the same
--polynomial is used.
entity descrambler is
port( --Process clock. Every clock cycle unscrambled data in is processed through the
--scrambler producing scrambled data out.
clk : in std_logic;
--Asynchronous reset. While high: resets the LFSR to the seed value and sets the
--poly_mask used for the feedback polynomial
rst : in std_logic;
--Place '1's in the bits where the polynomial calls for taps. Read up on LFSR's before
--selecting a polynomial, not all choices will yield "good" random numbers.
--(e.g. X^5 + X^3 + 1 would be poly_mask(4 downto 0) <= "10100";)
poly_mask : in std_logic_vector;
--Must be identical in length to poly_mask. Initial value of the shift register. Is
--only set during rst = '1'. DO NOT SET TO ALL '0's
seed : in std_logic_vector;
--Scrambled data
scrambled_datain : in std_logic_vector;
--Unscrambled data
unscrambled_dataout : out std_logic_vector);
end descrambler;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture behave of descrambler is
signal feedback_to_lfsr : std_logic_vector(scrambled_datain'range);
signal feedback_from_lfsr : std_logic_vector(scrambled_datain'range);
begin
--Use this lfsr to generate random patterns to descramble the data with
descrambling_lfsr : entity work.lfsr(structural)
port map( clk => clk,
rst => rst,
poly_mask => poly_mask,
seed => seed,
feedin => feedback_to_lfsr,
feedout => feedback_from_lfsr);
--Feedback to the LFSR is the scrambled data.
feedback_to_lfsr <= scrambled_datain;
--Descramble the data by xor'ing the data with feedback from the LFSR
unscrambled_dataout <= feedback_from_lfsr xor scrambled_datain;
end behave;
| mit | c99cc9b2e0ff0fe4bca0c174ef232b8d | 0.451165 | 5.347181 | false | false | false | false |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/decode2alu_reg.vhd | 1 | 1,666 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
entity decode2alu_reg is
port(
clk, rst: in std_logic;
noop : in std_logic;
A_in : in std_logic_vector(7 downto 0);
B_in : in std_logic_vector(7 downto 0);
operation_in : in std_logic_vector(4 downto 0);
Raddr1_in : in std_logic_vector(3 downto 0);
Raddr2_in : in std_logic_vector(3 downto 0);
Memaddr_in : in std_logic_vector(7 downto 0);
src_select: in std_logic_vector(1 downto 0);
ALU_result: in std_logic_vector(7 downto 0);
A_out : out std_logic_vector(7 downto 0);
B_out : out std_logic_vector(7 downto 0);
operation_out : out std_logic_vector(4 downto 0);
Raddr1_out : out std_logic_vector(3 downto 0);
Raddr2_out : out std_logic_vector(3 downto 0);
Memaddr_out : out std_logic_vector(7 downto 0)
);
end decode2alu_reg;
architecture mixed of decode2alu_reg is
begin
process(clk,rst)
begin
if (rst = '1') then
A_out <= X"00";
B_out <= X"00";
operation_out <= "00000";
Raddr1_out <= X"0";
Raddr2_out <= X"0";
Memaddr_out <= X"00";
elsif rising_edge(clk) then
if (noop = '1') then
A_out <= X"00";
B_out <= X"00";
operation_out <= "00000";
Raddr1_out <= X"0";
Raddr2_out <= X"0";
Memaddr_out <= X"00";
else
if (src_select(0) = '0') then
A_out <= A_in;
else
A_out <= ALU_result;
end if;
if (src_select(1) = '0') then
B_out <= B_in;
else
B_out <= ALU_result;
end if;
operation_out <= operation_in;
Raddr1_out <= Raddr1_in;
Raddr2_out <= Raddr2_in;
Memaddr_out <= Memaddr_in;
end if;
end if;
end process;
end mixed;
| unlicense | 5475b20954d3a934073b3b1af5ca00bd | 0.623049 | 2.59098 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/FIR_Filter/sparse_fir_tap.vhd | 1 | 3,118 | --------------------------------------------------------------------------------------------------
-- Sparse FIR Tap
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package sparse_fir_tap_pkg is
--FIR tap component declaration
component sparse_fir_tap is
port( clk : in std_logic;
rst : in std_logic;
sig_in : in sig;
sig_out : out sig;
sum_in : in fir_sig;
sum_out : out fir_sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
--This entity represents a the sparse tap in a sparse FIR filter. This tap is only used when the
--coefficient is 0, and is a part of a cascade adder allowing for chaining an indefinite (tho
--definitely finite) number of taps. Because this is a sparse fir tap, the mulitiplication stage
--is skipped if the coefficient is 0, thus saving multiplier resources.
entity sparse_fir_tap is
port( clk : in std_logic;
rst : in std_logic;
sig_in : in sig;
sig_out : out sig;
sum_in : in fir_sig;
sum_out : out fir_sig);
end sparse_fir_tap;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE (behavioral)
--------------------------------------------------------------------------------------------------
architecture behave of sparse_fir_tap is
signal sig_delay : sig_array(1 to 2) := (others => (others => '0'));
signal product : fir_sig := (others => '0');
begin
--delay the input signal
delay_sig : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
sig_delay <= (others => (others => '0'));
else
sig_delay(1) <= sig_in;
sig_delay(2) <= sig_delay(1);
end if;
end if;
end process;
sig_out <= sig_delay(2);
--delay the sum
update_sum : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
sum_out <= (others => '0');
else
sum_out <= sum_in;
end if;
end if;
end process;
end behave;
| mit | 28518482d61062a8fa277d82d11e03aa | 0.377806 | 4.996795 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/USB_TOP.vhd | 1 | 6,814 |
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Wrapper for everything USB
-------------------------------------------------------------------------------------
--Communicates over an USB UART port
--Implements a simple request-response protocol
--The commands from the PC -> response from token
--
--*I -> *IHEJ (ID)
--*W[64 byte] -> *D if successful, *T if timeout, *B if device busy with other task
--*R -> *M[64 byte] if data ready, *B if device busy with other task
--
-------------------------------------------------------------------------------------
entity USB_TOP is
generic ( data_addr_width : integer := 6;
BAUD_RATE : integer := 115200; --baud of 115200
CLOCK_RATE : integer := 100_000_000; --100MHz
OVERSAMPLES : integer := 4);
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
TXD : out STD_LOGIC;
RXD : in STD_LOGIC;
RAM_ADDR : out STD_LOGIC_VECTOR (data_addr_width-1 downto 0);
RAM_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
RAM_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0);
RAM_WE : out STD_LOGIC;
READY_FOR_DATA : in STD_LOGIC;
RSA_DONE : in STD_LOGIC;
DATA_READY : out STD_LOGIC);
end USB_TOP;
architecture Behavioral of USB_TOP is
component FIFO_TXD IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
component TXD_Controller is
Generic (BAUD_RATE : integer := BAUD_RATE; --baud of 115200
CLOCK_RATE : integer := CLOCK_RATE; --100MHz
OVERSAMPLES : integer := OVERSAMPLES);
Port ( CLK : in STD_LOGIC; --Global clock
RESET : in STD_LOGIC; --reset signal (synchronous)
TXD_PIN : out STD_LOGIC; --data pin
FIFO_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); --byte from FIFO
FIFO_READ : out STD_LOGIC; --Read next signal to the FIFO
FIFO_EMPTY : in STD_LOGIC); --Flag from FIFO to signal if the FIFO is empty or not
end component;
component RXD_Controller is
Generic (Baud_Rate : integer := BAUD_RATE; --Baud of 115200
CLOCK_RATE : integer := CLOCK_RATE; --100MHz
OVERSAMPLES : integer := OVERSAMPLES);
Port(
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
RXD_PIN : in STD_LOGIC;
RXD_BYTE : out STD_LOGIC_VECTOR(7 downto 0);
VALID_DATA_IN : out STD_LOGIC);
end component;
component USB_CMD_PARSER is
generic ( data_addr_width : integer := data_addr_width;
Frequency : integer := CLOCK_RATE);
Port ( RXD_BYTE : in STD_LOGIC_VECTOR (7 downto 0); --Input byte from the serial-to-parallell translator
TXD_BYTE : out STD_LOGIC_VECTOR (7 downto 0); --Output byte to the parallell-to-serial translator
RAM_ADDR : out STD_LOGIC_VECTOR (data_addr_width-1 downto 0); --RAM ADDR where the RSA (signed) message is
RAM_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); --DATA from the active RAM cell
RAM_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0); --DATA to be written to active RAM cell if WE is high
VALID_DATA_IN : in STD_LOGIC; --Flag to the parallell-to-serial translator to tell it that there's a new byte on the bus
VALID_DATA_OUT : out STD_LOGIC; --Flag from the serial-to-parallell translator to tell that there's a new byte on the bus
RAM_WE : out STD_LOGIC; --RAM Write Enable flag
RSA_DONE : in STD_LOGIC; --Flag from RSA module that the values in RAM are the signed message
READY_FOR_DATA : in STD_LOGIC; --Flag from RSA module that it is ready to recive a new message to sign
RESET : in STD_LOGIC; --Reset for module. When high all registers and counters resets at next high flank of the clock
CLK : in STD_LOGIC; --Global clock signal
DATA_READY : out STD_LOGIC;
FIFO_EMPTY : in STD_LOGIC);
end component;
signal RXD_BYTE, TXD_BYTE, FIFO_DATA_OUT, FIFO_DATA_IN : STD_LOGIC_VECTOR(7 downto 0);
signal VALID_DATA_IN, VALID_DATA_OUT, FIFO_READ, FIFO_EMPTY : STD_LOGIC;
begin
TXD_CONTRL: TXD_Controller port map(
CLK => CLK,
RESET => RESET,
TXD_PIN => TXD,
FIFO_DATA_IN => FIFO_DATA_OUT, --confusing name. DATA is OUT from FIFO and is IN to TXD
FIFO_READ => FIFO_READ,
FIFO_EMPTY => FIFO_EMPTY
);
RXD_CONTRL: RXD_Controller port map(
CLK => CLK,
RESET => RESET,
RXD_PIN => RXD,
RXD_BYTE => RXD_BYTE,
VALID_DATA_IN => VALID_DATA_IN);
CMD_PARSER: USB_CMD_PARSER port map(
RXD_BYTE => RXD_BYTE,
TXD_BYTE => TXD_BYTE,
RAM_ADDR => RAM_ADDR,
RAM_DATA_IN => RAM_DATA_IN,
RAM_DATA_OUT => RAM_DATA_OUT,
VALID_DATA_IN => VALID_DATA_IN,
VALID_DATA_OUT => VALID_DATA_OUT,
RAM_WE => RAM_WE,
RSA_DONE => RSA_DONE,
READY_FOR_DATA => READY_FOR_DATA,
DATA_READY => DATA_READY,
RESET => RESET,
CLK => CLK,
FIFO_EMPTY => FIFO_EMPTY);
FIFO: FIFO_TXD PORT MAP(
clk => CLK,
rst => RESET,
din => TXD_BYTE,
wr_en => VALID_DATA_OUT,
rd_en => FIFO_READ,
dout => FIFO_DATA_OUT,
full => open,
empty => FIFO_EMPTY
);
end Behavioral;
| bsd-3-clause | 8fd22041ca37f19d07f51685063964df | 0.648077 | 3.622541 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4088/upstreamEpathFifoWrap.vhd | 1 | 6,049 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 23/06/2015
--! Module Name: upstreamEpathFifoWrap
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE,work;
use IEEE.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.all;
--! EPATH FIFO 18 bit wide, 1K deep
entity upstreamEpathFifoWrap is
port (
rst : in std_logic;
fifoFLUSH : in std_logic;
---
wr_clk : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(17 downto 0);
---
rd_clk : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(9 downto 0);
doutRdy : out std_logic;
---
full : out std_logic;
empty : out std_logic;
prog_full : out std_logic
);
end upstreamEpathFifoWrap;
architecture Behavioral of upstreamEpathFifoWrap is
----------------------------------
----------------------------------
component fh_epath_fifo2K_18bit_wide -- IP
port (
wr_clk : in std_logic;
wr_rst : in std_logic;
rd_clk : in std_logic;
rd_rst : in std_logic;
din : in std_logic_vector(17 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(9 downto 0);
prog_full_thresh_negate : in std_logic_vector(9 downto 0);
dout : out std_logic_vector(17 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
prog_full : out std_logic
);
end component;
----------------------------------
----------------------------------
signal rd_en_s, empty_efifo, prog_full_s : std_logic;
signal OE, rst_state, byte_cnt,byte_mux_sel,byte_rdy,rd_en1,rd_en2 : std_logic := '0';
signal dout18bit : std_logic_vector(17 downto 0);
signal byte0, byte1 : std_logic_vector(9 downto 0) := "1100000000";
constant comma_byte : std_logic_vector(9 downto 0) := "1100000000";
signal byte0_code,byte1_code,word16_code : std_logic_vector(1 downto 0);
signal empty_efifo1,empty_efifo2,empty_efifo3 : std_logic;
signal wr_en_r : std_logic := '0';
signal din_r : std_logic_vector(17 downto 0) := "110000000000000000";
begin
-------------------------------------------------------------------------------------------
-- write pipeline
-------------------------------------------------------------------------------------------
process(wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
wr_en_r <= wr_en;
din_r <= din;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- FIFO - ip
-------------------------------------------------------------------------------------------
epathFIFO: fh_epath_fifo2K_18bit_wide
port map(
wr_clk => wr_clk,
wr_rst => fifoFLUSH,
rd_clk => rd_clk,
rd_rst => fifoFLUSH,
din => din_r,
wr_en => wr_en_r,
rd_en => rd_en_s,
dout => dout18bit, --18 bit
full => full,
almost_full => open, --almost_full,
empty => empty_efifo,
prog_full => prog_full_s, -- 1008/960 from 1024
prog_full_thresh_assert => std_logic_vector(to_unsigned(990, 10)),
prog_full_thresh_negate => std_logic_vector(to_unsigned(980, 10))
);
--
-------------------------------------------------------------------------------------------
-- re pulse
-------------------------------------------------------------------------------------------
process(rd_clk,rst)
begin
if rst = '1' then
byte_cnt <= '0';
elsif rd_clk'event and rd_clk = '1' then
if rd_en = '1' then -- 1 clk trigger
byte_cnt <= not byte_cnt;
end if;
end if;
end process;
--
rd_en_s <= rd_en and (not byte_cnt) and (not empty_efifo); -- only when byte_cnt = 0
--
word16_code <= dout18bit(17 downto 16);
--
process(word16_code,empty_efifo1)
begin
if empty_efifo1 = '1' then
byte0_code <= "11";
byte1_code <= "11";
else
if word16_code = "10" then -- start of message
byte0_code <= "11";
byte1_code <= "10";
elsif word16_code = "01" then -- end of message
byte0_code <= "01";
byte1_code <= "11";
else -- "00" data
byte0_code <= empty_efifo1 & empty_efifo1;
byte1_code <= empty_efifo2 & empty_efifo2;
end if;
end if;
end process;
--
byte0 <= byte0_code & dout18bit(15 downto 8);
byte1 <= byte1_code & dout18bit(7 downto 0);
--
process(byte_cnt,byte0,byte1)
begin
if byte_cnt = '1' then
dout <= byte0;
else
dout <= byte1;
end if;
end process;
--
--
process(rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
byte_rdy <= byte_cnt;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- re pulse
-------------------------------------------------------------------------------------------
--
process(rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
doutRdy <= rd_en;
empty_efifo1 <= empty_efifo;
empty_efifo2 <= empty_efifo1;
empty_efifo3 <= empty_efifo2;
end if;
end process;
--
empty <= empty_efifo;-- rd_clk domain
--
process(rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
rst_state <= rst or fifoFLUSH;
OE <= not rst_state;
end if;
end process;
--
prog_full <= prog_full_s and OE;
--
end Behavioral;
| gpl-3.0 | f5a4dc280e72ab0b6479f2aaf33d9b50 | 0.443379 | 3.67051 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/rsa_512/trunk/bench/test_512.vhd | 1 | 10,738 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:40:28 12/13/2009
-- Design Name:
-- Module Name:
-- Project Name: ciosspartan
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: rsa_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity test_rsa_512 is
end test_rsa_512;
architecture behavior of test_rsa_512 is
-- Component Declaration for the Unit Under Test (UUT)
component rsa_top
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
start_in : in std_logic;
x : in std_logic_vector(15 downto 0);
y : in std_logic_vector(15 downto 0);
m : in std_logic_vector(15 downto 0);
r_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector(15 downto 0);
valid_out : out std_logic;
bit_size : in std_logic_vector(15 downto 0)
);
end component;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal valid_in : std_logic := '0';
signal start_in : std_logic;
signal x : std_logic_vector(15 downto 0) := (others => '0');
signal y : std_logic_vector(15 downto 0) := (others => '0');
signal m : std_logic_vector(15 downto 0) := (others => '0');
signal r_c : std_logic_vector(15 downto 0) := (others => '0');
signal n_c : std_logic_vector(15 downto 0) := (others => '0');
signal bit_size : std_logic_vector(15 downto 0) := x"0200";
--Outputs
signal s : std_logic_vector(15 downto 0);
signal valid_out : std_logic;
-- Clock period definitions
constant clk_period : time := 1ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut : rsa_top port map (
clk => clk,
reset => reset,
valid_in => valid_in,
start_in => start_in,
x => x,
y => y,
m => m,
r_c => r_c,
s => s,
valid_out => valid_out,
bit_size => bit_size
);
-- Clock process definitions
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc : process
begin
start_in <= '0';
valid_in <= '0';
-- hold reset state for 100ms.
reset <= '1';
wait for 10ns;
reset <= '0';
wait for clk_period*10;
-- insert stimulus here
--n_c and valid signal and the r_c constant are also required
--n_c <= x"738f";
m <= x"b491";
--Start_in to begin n_c calculation
start_in <= '1';
wait for clk_period;
start_in <= '0';
wait for clk_period*6;
--Start data flow
x <= x"f3ad";
y <= x"42b1";
m <= x"b491";
r_c <= x"f579";
valid_in <= '1';
wait for clk_period;
x <= x"8e40";
y <= x"1ad3";
m <= x"1417";
r_c <= x"6ee9";
wait for clk_period;
x <= x"6af9";
y <= x"a827";
m <= x"b498";
r_c <= x"972d";
wait for clk_period;
x <= x"4e63";
y <= x"0d64";
m <= x"e1b7";
r_c <= x"5052";
wait for clk_period;
x <= x"9600";
y <= x"3f76";
m <= x"e47c";
r_c <= x"1dca";
wait for clk_period;
x <= x"68f4";
y <= x"6670";
m <= x"b186";
r_c <= x"bc81";
wait for clk_period;
x <= x"5a12";
y <= x"5a1c";
m <= x"93f0";
r_c <= x"377e";
wait for clk_period;
x <= x"d62e";
y <= x"4844";
m <= x"b183";
r_c <= x"04ef";
wait for clk_period;
x <= x"8fc1";
y <= x"d5f2";
m <= x"f8f1";
r_c <= x"3a2a";
wait for clk_period;
x <= x"031d";
y <= x"b65a";
m <= x"eed1";
r_c <= x"291b";
wait for clk_period;
x <= x"f496";
y <= x"034f";
m <= x"0083";
r_c <= x"c159";
wait for clk_period;
x <= x"1268";
y <= x"9635";
m <= x"981c";
r_c <= x"9336";
wait for clk_period;
x <= x"2e5a";
y <= x"386e";
m <= x"6441";
r_c <= x"1bd0";
wait for clk_period;
x <= x"c1d6";
y <= x"fb73";
m <= x"fcd8";
r_c <= x"317d";
wait for clk_period;
x <= x"cd8f";
y <= x"5623";
m <= x"cbf0";
r_c <= x"64b4";
wait for clk_period;
x <= x"e4d2";
y <= x"9041";
m <= x"e3ca";
r_c <= x"8793";
wait for clk_period;
x <= x"36c6";
y <= x"99da";
m <= x"41d9";
r_c <= x"85f5";
wait for clk_period;
x <= x"df4a";
y <= x"cd68";
m <= x"b7a0";
r_c <= x"7c8d";
wait for clk_period;
x <= x"8e40";
y <= x"9a94";
m <= x"146e";
r_c <= x"64d9";
wait for clk_period;
x <= x"6af9";
y <= x"ccc8";
m <= x"4776";
r_c <= x"c7f6";
wait for clk_period;
x <= x"4e63";
y <= x"ed49";
m <= x"ec50";
r_c <= x"fba0";
wait for clk_period;
x <= x"9600";
y <= x"4d25";
m <= x"c07c";
r_c <= x"e3e0";
wait for clk_period;
x <= x"68f4";
y <= x"3b8e";
m <= x"e698";
r_c <= x"b567";
wait for clk_period;
x <= x"5a12";
y <= x"36d5";
m <= x"d85f";
r_c <= x"3172";
wait for clk_period;
x <= x"d62e";
y <= x"3a75";
m <= x"729c";
r_c <= x"111a";
wait for clk_period;
x <= x"8fc1";
y <= x"77a3";
m <= x"19b6";
r_c <= x"1971";
wait for clk_period;
x <= x"d2cd";
y <= x"367f";
m <= x"05d3";
r_c <= x"9f9b";
wait for clk_period;
x <= x"c6e4";
y <= x"68de";
m <= x"cacd";
r_c <= x"b574";
wait for clk_period;
x <= x"4a36";
y <= x"59a4";
m <= x"e16f";
r_c <= x"4a50";
wait for clk_period;
x <= x"f6df";
y <= x"9f89";
m <= x"f67b";
r_c <= x"6d56";
wait for clk_period;
x <= x"061c";
y <= x"ed71";
m <= x"7066";
r_c <= x"bdc6";
wait for clk_period;
x <= x"06c8";
y <= x"059f";
m <= x"08de";
r_c <= x"0400";
wait for clk_period;
valid_in <= '0';
--valid_in <='0';
wait for clk_period*200000;
--Now with the public key x"10001";
bit_size <= x"0011";
valid_in <= '1';
x <= x"f3ad";
y <= x"0001";
m <= x"b491";
r_c <= x"f579";
wait for clk_period;
x <= x"8e40";
y <= x"0001";
m <= x"1417";
r_c <= x"6ee9";
wait for clk_period;
x <= x"6af9";
y <= x"0000";
m <= x"b498";
r_c <= x"972d";
wait for clk_period;
x <= x"4e63";
m <= x"e1b7";
r_c <= x"5052";
wait for clk_period;
x <= x"9600";
m <= x"e47c";
r_c <= x"1dca";
wait for clk_period;
x <= x"68f4";
m <= x"b186";
r_c <= x"bc81";
wait for clk_period;
x <= x"5a12";
m <= x"93f0";
r_c <= x"377e";
wait for clk_period;
x <= x"d62e";
m <= x"b183";
r_c <= x"04ef";
wait for clk_period;
x <= x"8fc1";
m <= x"f8f1";
r_c <= x"3a2a";
wait for clk_period;
x <= x"031d";
m <= x"eed1";
r_c <= x"291b";
wait for clk_period;
x <= x"f496";
m <= x"0083";
r_c <= x"c159";
wait for clk_period;
x <= x"1268";
m <= x"981c";
r_c <= x"9336";
wait for clk_period;
x <= x"2e5a";
m <= x"6441";
r_c <= x"1bd0";
wait for clk_period;
x <= x"c1d6";
m <= x"fcd8";
r_c <= x"317d";
wait for clk_period;
x <= x"cd8f";
m <= x"cbf0";
r_c <= x"64b4";
wait for clk_period;
x <= x"e4d2";
m <= x"e3ca";
r_c <= x"8793";
wait for clk_period;
x <= x"36c6";
m <= x"41d9";
r_c <= x"85f5";
wait for clk_period;
x <= x"df4a";
m <= x"b7a0";
r_c <= x"7c8d";
wait for clk_period;
x <= x"8e40";
m <= x"146e";
r_c <= x"64d9";
wait for clk_period;
x <= x"6af9";
m <= x"4776";
r_c <= x"c7f6";
wait for clk_period;
x <= x"4e63";
m <= x"ec50";
r_c <= x"fba0";
wait for clk_period;
x <= x"9600";
m <= x"c07c";
r_c <= x"e3e0";
wait for clk_period;
x <= x"68f4";
m <= x"e698";
r_c <= x"b567";
wait for clk_period;
x <= x"5a12";
m <= x"d85f";
r_c <= x"3172";
wait for clk_period;
x <= x"d62e";
m <= x"729c";
r_c <= x"111a";
wait for clk_period;
x <= x"8fc1";
m <= x"19b6";
r_c <= x"1971";
wait for clk_period;
x <= x"d2cd";
m <= x"05d3";
r_c <= x"9f9b";
wait for clk_period;
x <= x"c6e4";
m <= x"cacd";
r_c <= x"b574";
wait for clk_period;
x <= x"4a36";
m <= x"e16f";
r_c <= x"4a50";
wait for clk_period;
x <= x"f6df";
m <= x"f67b";
r_c <= x"6d56";
wait for clk_period;
x <= x"061c";
m <= x"7066";
r_c <= x"bdc6";
wait for clk_period;
x <= x"06c8";
m <= x"08de";
r_c <= x"0400";
wait for clk_period;
valid_in <= '0';
wait;
end process;
end;
| bsd-3-clause | 9f974ae87ee8a4683a2353582913d290 | 0.414044 | 2.828022 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/elinkInterface_top.vhd | 2 | 11,413 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 17/08/2015
--! Module Name: FIFO2Elink
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
--! Use standard library
library work, ieee, std;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.all;
use work.centralRouter_package.all;
use work.elinkInterface_package.all;
use ieee.std_logic_textio.all;
use std.textio.all;
--! consists of 1 E-path
entity elinkInterface_top is
generic(do_serialize : boolean := true);
port (
clk_200_in_n : in std_logic;
clk_200_in_p : in std_logic;
sys_reset_n : in std_logic;
rst_sw : in std_logic;
locked : out std_logic;
clk40_out : out std_logic;
rst_state : out std_logic;
------
emu_ena : in std_logic;
--
edata_clk : out std_logic;
edata : out std_logic_vector (15 downto 0);
edata_rdy : out std_logic
------
);
end elinkInterface_top;
architecture Behavioral of elinkInterface_top is
----------------------------------
----------------------------------
component CR_CLKs
port
(-- Clock in ports
clk200_in_p : in std_logic;
clk200_in_n : in std_logic;
-- Clock out ports
clk40 : out std_logic;
clk80 : out std_logic;
clk160 : out std_logic;
clk320 : out std_logic;
clk240 : out std_logic;
-- Status and control signals
resetn : in std_logic;
locked : out std_logic
);
end component;
ATTRIBUTE SYN_BLACK_BOX : BOOLEAN;
ATTRIBUTE SYN_BLACK_BOX OF CR_CLKs : COMPONENT IS TRUE;
ATTRIBUTE BLACK_BOX_PAD_PIN : STRING;
ATTRIBUTE BLACK_BOX_PAD_PIN OF CR_CLKs : COMPONENT IS "clk200_in_p,clk200_in_n,clk40,clk80,clk160,clk320,resetn,locked";
----------------------------------
----------------------------------
component emuram_2
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(13 downto 0);
dina : in std_logic_vector(15 downto 0);
douta : out std_logic_vector(15 downto 0);
clkb : in std_logic;
web : in std_logic_vector(0 downto 0);
addrb : in std_logic_vector(13 downto 0);
dinb : in std_logic_vector(15 downto 0);
doutb : out std_logic_vector(15 downto 0)
);
end component emuram_2;
----------------------------------
----------------------------------
constant addr_max : std_logic_vector(13 downto 0) := "11111111111011"; -- 16379 (5 x 3276)
constant zeros14bit : std_logic_vector(13 downto 0) := (others=>'0');
constant zeros16bit : std_logic_vector(15 downto 0) := (others=>'0');
constant block_size : std_logic_vector(8 downto 0) := (others=>'1'); -- block is 1Kbyte
--
signal emuram_rdaddr : std_logic_vector(13 downto 0) := (others=>'0');
signal block_word_count : std_logic_vector(8 downto 0) := (others=>'0');
signal packet_counter : std_logic_vector(7 downto 0) := (others=>'0');
signal count : std_logic_vector(7 downto 0) := (others=>'0');
signal packet_data : std_logic_vector(15 downto 0);
signal clk40, clk80, clk160, clk320, clk240 : std_logic;
signal startup_case : std_logic := '1';
signal efifoRe,send_sop,edata_rdy_r : std_logic := '0';
signal rst,fifo_flush,elinkout1bit,elinkin1bit,efifoWe,efifoPfull,efifoHF,send_eop,emu_ena_s,block_done : std_logic;
signal elinkout2bit,elinkin2bit : std_logic_vector(1 downto 0);
signal elinkout4bit,elinkin4bit : std_logic_vector(3 downto 0);
signal elinkout8bit,elinkin8bit : std_logic_vector(7 downto 0);
signal elinkin16bit : std_logic_vector(15 downto 0);
signal efifoDin : std_logic_vector(17 downto 0) := (others=>'0');
signal efifoDout : std_logic_vector(15 downto 0);
begin
--------------------------------------------------------------------
-- clocks
--------------------------------------------------------------------
clk0: CR_CLKs
port map (
-- Clock in ports
clk200_in_p => clk_200_in_p,
clk200_in_n => clk_200_in_n,
-- Clock out ports
clk40 => clk40,
clk80 => clk80,
clk160 => clk160,
clk320 => clk320,
clk240 => clk240,
-- Status and control signals
resetn => sys_reset_n,
locked => locked
);
--
clk40_out <= clk40;
--
--------------------------------------------------------------------
-- reset and fifo flush sequence
--------------------------------------------------------------------
rst0: entity work.CRresetManager
port map (
clk40 => clk40,
rst_soft => rst_sw,
cr_rst => rst,
cr_fifo_flush => fifo_flush
);
--
rst_state <= rst; -- to output
--
--------------------------------------------------------------------
-- user data source: counter @ clk160
--------------------------------------------------------------------
send_eop <= '1' when (count = packet_size) else '0';
--
process(clk160)
begin
if rising_edge(clk160) then
send_sop <= send_eop; -- nex clock after eop is sent
if emu_ena = '1' then
startup_case <= '0';
end if;
if send_eop = '1' then
packet_counter <= packet_counter + 1;
end if;
end if;
end process;
--
emu_ena_s <= emu_ena and not (send_eop or send_sop or startup_case);
--
process(clk160)
begin
if rising_edge(clk160) then
if efifoPfull = '0' then -- only when not full
if emu_ena_s = '1' then -- when data emulator is enabled in simulation module
count <= count + 1;
else
count <= (others=>'0');
end if;
end if;
end if;
end process;
--
process(clk160)
begin
if rising_edge(clk160) then
if efifoPfull = '1' or emu_ena = '0' then
efifoWe <= '0';
efifoDin <= "11" & x"0000";
else
efifoWe <= '1';
if send_sop = '1' or startup_case = '1' then
efifoDin <= "10" & x"0000";
elsif send_eop = '1' then
efifoDin <= "01" & x"0000";
else
efifoDin <= "00" & packet_data;
end if;
end if;
end if;
end process;
--
--packet_data <= packet_counter & count;
--packet_data <= "11111111" & count;
--packet_data <= (others=>'1');
--packet_data <= x"fc" & x"fd";
--packet_data <= x"7e" & x"f" & count(3 downto 0);
packet_data <= x"fe" & x"f" & count(3 downto 0);
--
--------------------------------------------------------------------
-- elink transmitter
--------------------------------------------------------------------
elink_tx: entity work.FIFO2Elink
generic map (
OutputDataRate => elinkRate,
elinkEncoding => elinkEncoding
)
port map (
clk40 => clk40,
clk80 => clk80,
clk160 => clk160,
clk320 => clk320,
rst => rst,
fifo_flush => fifo_flush,
------
efifoDin => efifoDin, -- [data_code,2bit][data,16bit]
efifoWe => efifoWe,
efifoPfull => efifoPfull,
efifoWclk => clk160,
------
DATA1bitOUT => elinkout1bit,
elink2bit => elinkout2bit,
elink4bit => elinkout4bit,
elink8bit => elinkout8bit
------
);
--------------------------------------------------------------------
-- elink
--------------------------------------------------------------------
-- 1. serialized, 1 bit @ 80/160/320 Mbps
actual_elink_case: if do_serialize = true generate
elinkin1bit <= elinkout1bit;
elinkin2bit <= (others=>'0');
elinkin4bit <= (others=>'0');
elinkin8bit <= (others=>'0');
end generate actual_elink_case;
--
-- 2. not serialized, 2/4/8 bits @ 40 MHz
GBT_frame_case: if do_serialize = false generate
elinkin1bit <= '0';
elinkin2bit <= elinkout2bit;
elinkin4bit <= elinkout4bit;
elinkin8bit <= elinkout8bit;
end generate GBT_frame_case;
--------------------------------------------------------------------
-- test 8b10b-encoded data source for 640Mbps elink
--------------------------------------------------------------------
emulatorRAM_640Mbps_elink: emuram_2
port map (
clka => '0',
wea => "0",
addra => zeros14bit,
dina => zeros16bit,
douta => open,
--
clkb => clk40,
web => "0", -- reading only
addrb => emuram_rdaddr,
dinb => zeros16bit,
doutb => elinkin16bit
);
--
-- address counter
address_counter: process(clk40)
begin
if rising_edge(clk40) then
if emu_ena = '1' and rst = '0' then
if emuram_rdaddr = addr_max then
emuram_rdaddr <= (others => '0');
else
emuram_rdaddr <= emuram_rdaddr + 1;
end if;
else
if emuram_rdaddr >= "00000000000100" then
emuram_rdaddr <= (others => '0');
else
emuram_rdaddr <= emuram_rdaddr + 1;
end if;
end if;
end if;
end process;
--
--------------------------------------------------------------------
-- elink receiver
--------------------------------------------------------------------
elink_rx: entity work.Elink2FIFO
generic map (
InputDataRate => elinkRate,
elinkEncoding => elinkEncoding,
serialized_input => do_serialize
)
port map (
clk40 => clk40,
clk80 => clk80,
clk160 => clk160,
clk320 => clk320,
rst => rst,
fifo_flush => fifo_flush,
------
DATA1bitIN => elinkin1bit,
elink2bit => elinkin2bit,
elink4bit => elinkin4bit,
elink8bit => elinkin8bit,
elink16bit => elinkin16bit,
------
efifoRclk => clk160,
efifoRe => efifoRe,
efifoHF => efifoHF, -- half-full flag: 1 KByte block is ready to be read
efifoDout => efifoDout
------
);
--------------------------------------------------------------------
-- user data acquisition
--------------------------------------------------------------------
block_re_latch: process(clk160)
begin
if rising_edge(clk160) then
if block_done = '1' or rst = '1' then
efifoRe <= '0';
elsif efifoHF = '1' then -- one 1Kbyte block is ready
efifoRe <= '1';
end if;
end if;
end process;
--
block_done <= '1' when (block_word_count = block_size) else '0';
--
block_word_counter: process(clk160)
begin
if rising_edge(clk160) then
if efifoRe = '1' and block_done = '0' then
block_word_count <= block_word_count + 1;
else
block_word_count <= (others=>'0');
end if;
end if;
end process;
--
edata_rdy0: process(clk160)
begin
if rising_edge(clk160) then
edata_rdy_r <= efifoRe;
end if;
end process;
--
edata_clk <= clk160;
edata_rdy <= edata_rdy_r;
edata <= efifoDout;
--
end Behavioral;
| gpl-3.0 | 77e5b8a25b6261df6d4828949fc7fd4f | 0.48471 | 3.706723 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/TXD_Controller.vhd | 1 | 6,556 |
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity TXD_Controller is
Generic (BAUD_RATE : integer; --Baud of this port
CLOCK_RATE : integer; --Frequency of the CLK. Needed to perform correct sampling
OVERSAMPLES : integer := 4);
Port ( CLK : in STD_LOGIC; --Global clock
RESET : in STD_LOGIC; --reset signal (synchronous)
TXD_PIN : out STD_LOGIC; --data pin
FIFO_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); --byte from FIFO
FIFO_READ : out STD_LOGIC; --Read next signal to the FIFO
FIFO_EMPTY : in STD_LOGIC); --Flag from FIFO to signal if the FIFO is empty or not
end TXD_Controller;
--This module handles transmission of bytes (8 bit) from a FIFO to a serial port (UART)
architecture Behavioral of TXD_Controller is
type STATES is (IDLE, START, DATA, STOP);
signal STATE : STATES := IDLE;
signal SAMPLE_COUNTER : integer := 0;
signal SAMPLE_COUNT : integer range 0 to OVERSAMPLES := 1;
signal bit_counter : integer range 0 to 8 := 0;
signal SAMPLE_NOW, BYTE_SENT, over_sampling_done : STD_LOGIC := '0';
begin
oversampler: process (CLK)
constant RATE_OF_SAMPLING : integer := CLOCK_RATE/BAUD_RATE/OVERSAMPLES; --How many cycles beween each sample
variable CURRENT_SAMPLE_COUNTER : integer := 0;
begin
if rising_edge(CLK) then
SAMPLE_NOW <= '0'; --Default is to NOT sample now
over_sampling_done <= '0'; --Default is that the sampling is not done
if RESET = '1' then --If reset signal
SAMPLE_COUNTER <= 0; --reset counter
--If not reset perform standard behaviour
elsif STATE /= IDLE then --We need sampling in every state but IDLE
CURRENT_SAMPLE_COUNTER := SAMPLE_COUNTER;
if CURRENT_SAMPLE_COUNTER < RATE_OF_SAMPLING then --If less than the sampling rate we are just to increase the counter
SAMPLE_COUNTER <= SAMPLE_COUNTER + 1;
else --otherwise we put SAMPLE_NOW to high and reset the counter
SAMPLE_COUNTER <= 0;
SAMPLE_NOW <= '1';
SAMPLE_COUNT <= SAMPLE_COUNT + 1; --count which sample it was
--count the amount of samples done and when the 4th is done
if SAMPLE_COUNT = OVERSAMPLES - 1 then --signal that the oversampling is done
over_sampling_done <= '1';
SAMPLE_COUNT <= 0;
end if;
end if;
end if;
end if;
end process;
State_process: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then --If reset, return to known state
STATE <= IDLE;
FIFO_READ <= '0';
else
FIFO_READ <= '0'; --Do NOT read any more bytes from the FIFO than the absolute first one
case STATE is
when IDLE =>
if FIFO_EMPTY = '0' then --Do nothing until there's a byte in the FIFO to work on
STATE <= START;
FIFO_READ <= '1'; --Read the byte from FIFO. Data will remain on FIFO_DATA_IN
end if;
when START =>
if (over_sampling_done = '1') then --wait for the start signal to be on the pin long enough
STATE <= DATA; --Go to the data transmit state
end if;
when DATA =>
if BYTE_SENT = '1' then --IFF we have sent the ENTIRE byte we can move on to the STOP state, otherwise we have to remain here
state <= STOP;
end if;
when STOP =>
if over_sampling_done = '1' then
if FIFO_EMPTY = '1' then --FIFO empty, return to idle
STATE <= IDLE;
else --FIFO not empty, return to start
STATE <= START;
FIFO_READ <= '1'; --Read the byte from FIFO. Data will remain on FIFO_DATA_IN
end if;
end if;
when others =>
STATE <= IDLE; --Catch all state that returns us to known state
end case;
end if;
end if;
end process;
TXD_process: process(CLK)
begin
if rising_edge(CLK) then
--Standard is that this signals are low
BYTE_SENT <= '0';
if RESET = '1' then
TXD_PIN <= '1'; --Drive pin high if reset as this is the idle state
bit_counter <= 0; --Reset the counters
else
if SAMPLE_NOW = '1' then --If we are to sample now
case STATE is
when IDLE =>
TXD_PIN <= '1'; --Drive the pin high when idle as we have no data now
bit_counter <= 0;
when START =>
TXD_PIN <= '0'; --Drive the pin low to signal that there's data on the way
when DATA =>
TXD_PIN <= FIFO_DATA_IN(bit_counter); --Drive the pin with the correct bit
if over_sampling_done = '1' then
bit_counter <= bit_counter + 1;
end if;
when STOP =>
TXD_PIN <= '1'; --set the pin back to the idle state
bit_counter <= 0;
when others => --assume others = IDLE
TXD_PIN <= '1'; --Drive the pin high when idle as we have no data now
bit_counter <= 0;
end case;
--generate signal for byte transfered and reset the bit counter
if bit_counter = 7 and over_sampling_done = '1' then
bit_counter <= 0;
BYTE_SENT <= '1';
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| bsd-3-clause | 8c4b34c71ba760c18613050179cd3737 | 0.668548 | 3.791787 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/rsa_512/trunk/rtl/n_c.vhd | 1 | 6,437 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Oleg Rasulov
--
-- Create Date: 17:04:24 12/28/2010
-- Design Name:
-- Module Name: n_c - Behavioral
-- Project Name:
-- Target Devices: Spartan-3 xc3s200-4
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
--library UNISIM;
--use UNISIM.VComponents.all;
entity n_c_core is
port (clk : in std_logic;
m_lsw : in std_logic_vector(15 downto 0);
ce : in std_logic;
n_c : out std_logic_vector(15 downto 0);
done : out std_logic
);
end n_c_core;
architecture Behavioral of n_c_core is
type stateNC_type is (stNC_idle, stNC_step1, stNC_step2,
stNC_step3, stNC_step4, stNC_fin);
signal stateNC : stateNC_type;
signal NC_complete : std_logic := '0';
signal NC_start : std_logic := '0';
signal LSW_M : std_logic_vector(15 downto 0);
signal adr_tbl : std_logic_vector(2 downto 0);
signal X0_tbl : std_logic_vector(3 downto 0);
signal Z0_tbl : std_logic_vector(3 downto 0);
signal X1_tbl : std_logic_vector(3 downto 0);
signal V1x9 : std_logic_vector(3 downto 0);
signal TforNC : std_logic_vector(15 downto 0);
signal not_TforNCPl3 : std_logic_vector(15 downto 0);
signal NC : std_logic_vector(15 downto 0);
signal t_NC : std_logic_vector(15 downto 0);
signal t_NC_out : std_logic_vector(15 downto 0);
signal b2equalb1 : std_logic;
-- dummy signals for simulation
signal DUMMY_SIM0 : std_logic_vector(19 downto 0);
signal DUMMY_SIM1 : std_logic_vector(19 downto 0);
--
signal mul1, mul2 : std_logic_vector(35 downto 0);
begin
mul1 <= ("00"&t_NC)*("00"&LSW_M);
TforNC <= mul1(15 downto 0);
mul2 <= ("00"&t_NC)*("00"¬_TforNCPl3);
t_NC_out <= mul2(15 downto 0);
-- TforNC_inst : MULT18X18
-- port map (
-- P(15 downto 0) => TforNC,
-- P(35 downto 16) => DUMMY_SIM0, --only for sim, normally open
-- A(15 downto 0) => t_NC,
-- A(17 downto 16) => "00",
-- B(15 downto 0) => LSW_M,
-- B(17 downto 16) => "00"
-- );
-- NC_inst : MULT18X18
-- port map (
-- P(15 downto 0) => t_NC_out,
-- P(35 downto 16) => DUMMY_SIM1, --only for sim, normally open
-- A(15 downto 0) => t_NC,
-- A(17 downto 16) => "00",
-- B(15 downto 0) => not_TforNCPl3,
-- B(17 downto 16) => "00"
-- );
--------------------------------------------
WRITELSWM_PROCESS : process(clk, NC_complete)
begin
if(NC_complete = '1') then
NC_start <= '0';
elsif rising_edge(clk) then
if(ce = '1') then
LSW_M <= m_lsw;
NC_start <= '1';
end if;
end if;
end process WRITELSWM_PROCESS;
--------------------------------------------
X0_ROM : process(adr_tbl)
begin
case adr_tbl is
when "000" => X0_tbl <= X"F";
when "001" => X0_tbl <= X"5";
when "010" => X0_tbl <= X"3";
when "011" => X0_tbl <= X"9";
when "100" => X0_tbl <= X"7";
when "101" => X0_tbl <= X"D";
when "110" => X0_tbl <= X"B";
when others => X0_tbl <= X"1";
end case;
end process X0_ROM;
-------------------------------------------------------------------------------
Z0_ROM : process(adr_tbl)
begin
case adr_tbl is
when "000" => Z0_tbl <= X"F";
when "001" => Z0_tbl <= X"5";
when "010" => Z0_tbl <= X"3";
when "011" => Z0_tbl <= X"4";
when "100" => Z0_tbl <= X"C";
when "101" => Z0_tbl <= X"5";
when "110" => Z0_tbl <= X"3";
when others => Z0_tbl <= X"1";
end case;
end process Z0_ROM;
-------------------------------------------------------------------------------
X1_ROM : process(b2equalb1, LSW_M, Z0_tbl, V1x9)
begin
if(b2equalb1 = '0') then -- b1==b2
X1_tbl <= LSW_M(7 downto 4) + Z0_tbl;
else -- b1 != b2
X1_tbl <= V1x9 + Z0_tbl;
end if;
end process X1_ROM;
-------------------------------------------------------------------------------
STATE_NC_PROCESS : process(clk)
begin
if rising_edge(clk) then
if(NC_start = '0') then
NC_complete <= '0';
stateNC <= stNC_idle;
done <= '0';
else
case stateNC is
when stNC_idle =>
done <= '0';
stateNC <= stNC_step1;
t_NC <= X"00" & X1_tbl & X0_tbl;
when stNC_step1 =>
t_NC <= t_NC_out;
stateNC <= stNC_step2;
when stNC_step2 =>
t_NC <= t_NC_out;
stateNC <= stNC_step3;
when stNC_step3 =>
t_NC <= t_NC_out;
stateNC <= stNC_step4;
when stNC_step4 =>
t_NC <= t_NC_out;
stateNC <= stNC_fin;
when stNC_fin =>
NC_complete <= '1';
done <= '1';
stateNC <= stNC_idle;
NC <= (not (t_NC(15 downto 1))) & '1';
when others =>
stateNC <= stNC_idle;
end case;
end if;
end if;
end process STATE_NC_PROCESS;
-------------------------------------------------------------------------------
not_TforNCPl3 <= (not TforNC) + 3;
adr_tbl <= LSW_M(3 downto 1);
V1x9 <= (LSW_M(4) & "000") + LSW_M(7 downto 4);
b2equalb1 <= LSW_M(5) xor LSW_M(6);
n_c <= NC;
end Behavioral;
| bsd-3-clause | e04877a6b064baf8cab22d6f2da99cbe | 0.413857 | 3.521335 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_OUT8.vhd | 1 | 5,229 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT8
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee,work;
use ieee.std_logic_1164.all;
use work.all;
--! E-link processor, 8bit output
entity EPROC_OUT8 is
generic (
do_generate : boolean := true;
includeNoEncodingCase : boolean := true
);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
getDataTrig : out std_logic; -- @ bitCLKx4
ENCODING : in std_logic_vector (3 downto 0);
EDATA_OUT : out std_logic_vector (7 downto 0);
TTCin : in std_logic_vector (8 downto 0);
DATA_IN : in std_logic_vector (9 downto 0);
DATA_RDY : in std_logic
);
end EPROC_OUT8;
architecture Behavioral of EPROC_OUT8 is
constant zeros8bit : std_logic_vector (7 downto 0) := (others=>'0');
signal EdataOUT_ENC8b10b_case, EdataOUT_direct_case, EdataOUT_HDLC_case, EdataOUT_TTC3_case, EdataOUT_TTC4_case : std_logic_vector (7 downto 0);
signal rst_s, rst_case000, rst_case001, rst_case010, rst_case011 : std_logic;
signal getDataTrig_ENC8b10b_case, getDataTrig_direct_case, getDataTrig_HDLC_case, getDataTrig_TTC_cases : std_logic;
begin
gen_enabled: if do_generate = true generate
rst_s <= rst or (not ENA);
-------------------------------------------------------------------------------------------
-- case 0: direct data, no delimeter...
-------------------------------------------------------------------------------------------
direct_data_enabled: if includeNoEncodingCase = true generate
rst_case000 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "000")) else '1';
getDataTrig_direct_case <= '1' when (ENCODING(2 downto 0) = "000") else '0';
EdataOUT_direct_case <= DATA_IN(7 downto 0);
end generate direct_data_enabled;
--
direct_data_disabled: if includeNoEncodingCase = false generate
EdataOUT_direct_case <= (others=>'0');
end generate direct_data_disabled;
--
-------------------------------------------------------------------------------------------
-- case 1: DEC8b10b
-------------------------------------------------------------------------------------------
rst_case001 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "001")) else '1';
--
ENC8b10b_case: entity work.EPROC_OUT8_ENC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case001,
getDataTrig => getDataTrig_ENC8b10b_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_ENC8b10b_case
);
--
-------------------------------------------------------------------------------------------
-- case 2: HDLC
-------------------------------------------------------------------------------------------
rst_case010 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "010")) else '1';
--
getDataTrig_HDLC_case <= '0'; --'1' when (ENCODING(2 downto 0) = "010") else '0';
EdataOUT_HDLC_case <= (others=>'0'); --<---TBD
--
-------------------------------------------------------------------------------------------
-- case 3&4: TTC-3 & TTC-4
-------------------------------------------------------------------------------------------
rst_case011 <= '0' when ((rst_s = '0') and ((ENCODING(2 downto 0) = "011") or (ENCODING(2 downto 0) = "100"))) else '1';
--
getDataTrig_TTC_cases <= '0'; --'1' when ((ENCODING(2 downto 0) = "011") or (ENCODING(2 downto 0) = "100")) else '0';
--
ttc_r: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst_case011 = '1' then
EdataOUT_TTC3_case <= zeros8bit;
EdataOUT_TTC4_case <= zeros8bit;
else
EdataOUT_TTC3_case <= TTCin(1) & TTCin(7 downto 2) & TTCin(0);
EdataOUT_TTC4_case <= TTCin(8 downto 2) & TTCin(0);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- output data and busy according to the encoding settings
-------------------------------------------------------------------------------------------
dataOUTmux: entity work.MUX8_Nbit
generic map (N=>8)
port map(
data0 => EdataOUT_direct_case,
data1 => EdataOUT_ENC8b10b_case,
data2 => EdataOUT_HDLC_case,
data3 => EdataOUT_TTC3_case,
data4 => EdataOUT_TTC4_case,
data5 => zeros8bit,
data6 => zeros8bit,
data7 => zeros8bit,
sel => ENCODING(2 downto 0),
data_out => EDATA_OUT
);
--
getDataTrig <= ENA and (getDataTrig_TTC_cases or getDataTrig_HDLC_case or getDataTrig_ENC8b10b_case or getDataTrig_direct_case);
--
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
EDATA_OUT <= (others=>'0');
getDataTrig <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 | 5dee266ce0672aa9d16e2966fd56c8ef | 0.480972 | 3.770007 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/arp_RX.vhd | 2 | 13,223 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_rx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle receipt of arp pkt
-- ignores other types of pkt
--
-- When it receives an ARP pkt that is either addressed to our IP or is a global request,
-- it outputs for a single clock cycle either recv_who_has or recv_I_have along
-- with associated mac or arp entry data.
--
-- Note that if recv who_has and we have it, then we also assert I_have so that we can cache the rev lookup
-- on the expectation that we will want to reply to this host.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created - refactored from arp v0.02 module
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
entity arp_rx is
port (
-- MAC layer RX signals
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- ARP output signals
recv_who_has : out std_logic; -- pulse will be latched
arp_entry_for_who_has : out arp_entry_t; -- target for who_has msg (Iie, who to reply to)
recv_I_have : out std_logic; -- pulse will be latched
arp_entry_for_I_have : out arp_entry_t; -- arp target for I_have msg
-- control and status signals
req_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
-- system signals
our_ip_address : in std_logic_vector (31 downto 0);
rx_clk : in std_logic;
reset : in std_logic
);
end arp_rx;
architecture Behavioral of arp_rx is
type rx_state_t is (IDLE, PARSE, PROCESS_ARP, WAIT_END);
type rx_event_t is (NO_EVENT, DATA);
type count_mode_t is (RST, INCR, HOLD);
type arp_oper_t is (NOP, REQUEST, REPLY);
type tx_state_type is (IDLE, WAIT_MAC, SEND);
-- state variables
signal send_request_needed : std_logic;
signal tx_mac_chn_reqd : std_logic;
signal rx_state : rx_state_t;
signal rx_count : unsigned (7 downto 0);
signal arp_operation : arp_oper_t;
signal arp_req_count : unsigned (7 downto 0);
signal new_arp_entry : arp_entry_t;
-- FIXME - remove these debug state signals
signal arp_err_data : std_logic_vector (7 downto 0);
signal set_err_data : std_logic;
attribute keep : string;
attribute keep of arp_err_data : signal is "true";
-- rx control signals
signal next_rx_state : rx_state_t;
signal set_rx_state : std_logic;
signal rx_event : rx_event_t;
signal rx_count_mode : count_mode_t;
signal set_arp_oper : std_logic;
signal arp_oper_set_val : arp_oper_t;
signal dataval : std_logic_vector (7 downto 0);
signal count_arp_rcvd : std_logic;
signal set_mac5 : std_logic;
signal set_mac4 : std_logic;
signal set_mac3 : std_logic;
signal set_mac2 : std_logic;
signal set_mac1 : std_logic;
signal set_mac0 : std_logic;
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
-- function to determine whether the rx pkt is an arp pkt and whether we want to process it
-- Returns 1 if we should discard
-- The following will make us ignore the frame (all values hexadecimal):
-- PDU type /= 0806
-- Protocol Type /= 0800
-- Hardware Type /= 1
-- Hardware Length /= 6
-- Protocol Length /= 4
-- Operation /= 1 or 2
-- Target IP /= our IP (i.er. message is not meant for us)
--
function not_our_arp(data : std_logic_vector; count : unsigned; our_ip : std_logic_vector) return std_logic is
begin
if
(count = 12 and data /= x"08") or -- PDU type 0806 : ARP
(count = 13 and data /= x"06") or
(count = 14 and data /= x"00") or -- HW type 1 : eth
(count = 15 and data /= x"01") or
(count = 16 and data /= x"08") or -- Protocol 0800 : IP
(count = 17 and data /= x"00") or
(count = 18 and data /= x"06") or -- HW Length 6
(count = 19 and data /= x"04") or -- protocol length 4
(count = 20 and data /= x"00") or -- operation 1 or 2 (req or reply)
(count = 21 and data /= x"01" and data /= x"02") or
(count = 38 and data /= our_ip(31 downto 24)) or -- target IP is ours
(count = 39 and data /= our_ip(23 downto 16)) or
(count = 40 and data /= our_ip(15 downto 8)) or
(count = 41 and data /= our_ip(7 downto 0))
then
return '1';
else
return '0';
end if;
end function not_our_arp;
begin
rx_combinatorial : process (
-- input signals
data_in, data_in_valid, data_in_last, our_ip_address,
-- state variables
rx_state, rx_count, arp_operation, arp_req_count, arp_err_data, new_arp_entry,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode, set_arp_oper, arp_oper_set_val,
dataval, set_mac5, set_mac4, set_mac3, set_mac2, set_mac1, set_mac0, set_ip3, set_ip2, set_ip1, set_ip0, set_err_data,
count_arp_rcvd
)
begin
-- set output followers
req_count <= std_logic_vector(arp_req_count);
-- set defaults for combinatorial outputs
recv_who_has <= '0';
arp_entry_for_who_has.ip <= (others => '0');
arp_entry_for_who_has.mac <= (others => '0');
recv_I_have <= '0';
arp_entry_for_I_have.ip <= (others => '0');
arp_entry_for_I_have.mac <= (others => '0');
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_arp_oper <= '0';
arp_oper_set_val <= NOP;
dataval <= (others => '0');
set_mac5 <= '0';
set_mac4 <= '0';
set_mac3 <= '0';
set_mac2 <= '0';
set_mac1 <= '0';
set_mac0 <= '0';
set_ip3 <= '0';
set_ip2 <= '0';
set_ip1 <= '0';
set_ip0 <= '0';
count_arp_rcvd <= '0';
set_err_data <= '0';
-- determine event (if any)
if data_in_valid = '1' then
rx_event <= DATA;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
next_rx_state <= PARSE;
set_rx_state <= '1';
rx_count_mode <= INCR;
end case;
when PARSE =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
rx_count_mode <= INCR;
-- handle early frame termination
if data_in_last = '1' then
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
--else
end if;
-- check for end of frame. Also, detect and discard if not our frame
if rx_count = 41 then -- TB 2013-01-14 15:09:45 was 42
next_rx_state <= PROCESS_ARP;
set_rx_state <= '1';
elsif not_our_arp(data_in, rx_count, our_ip_address) = '1' then
dataval <= data_in;
set_err_data <= '1';
next_rx_state <= WAIT_END;
set_rx_state <= '1';
elsif rx_count = 21 then
-- capture ARP operation
case data_in is
when x"01" =>
arp_oper_set_val <= REQUEST;
set_arp_oper <= '1';
when x"02" =>
arp_oper_set_val <= REPLY;
set_arp_oper <= '1';
when others => -- ignore other values
end case;
-- capture source mac addr
elsif rx_count = 22 then
set_mac5 <= '1';
dataval <= data_in;
elsif rx_count = 23 then
set_mac4 <= '1';
dataval <= data_in;
elsif rx_count = 24 then
set_mac3 <= '1';
dataval <= data_in;
elsif rx_count = 25 then
set_mac2 <= '1';
dataval <= data_in;
elsif rx_count = 26 then
set_mac1 <= '1';
dataval <= data_in;
elsif rx_count = 27 then
set_mac0 <= '1';
dataval <= data_in;
-- capture source ip addr
elsif rx_count = 28 then
set_ip3 <= '1';
dataval <= data_in;
elsif rx_count = 29 then
set_ip2 <= '1';
dataval <= data_in;
elsif rx_count = 30 then
set_ip1 <= '1';
dataval <= data_in;
elsif rx_count = 31 then
set_ip0 <= '1';
dataval <= data_in;
end if;
-- end if;
end case;
when PROCESS_ARP =>
next_rx_state <= WAIT_END;
set_rx_state <= '1';
arp_oper_set_val <= NOP;
set_arp_oper <= '1';
case arp_operation is
when NOP => -- (nothing to do)
when REQUEST =>
count_arp_rcvd <= '1';
recv_who_has <= '1';
arp_entry_for_who_has <= new_arp_entry;
-- setting I_Have as well allows us to cache the remote node's entry immediately
recv_I_have <= '1';
arp_entry_for_I_have <= new_arp_entry;
when REPLY =>
count_arp_rcvd <= '1';
recv_I_have <= '1';
arp_entry_for_I_have <= new_arp_entry;
end case;
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if data_in_last = '1' then
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
end if;
end case;
end case;
end process;
rx_sequential : process (rx_clk)
begin
if rising_edge(rx_clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"00";
arp_operation <= NOP;
arp_req_count <= x"00";
arp_err_data <= (others => '0');
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST =>
rx_count <= x"00";
when INCR =>
rx_count <= rx_count + 1;
when HOLD =>
rx_count <= rx_count;
end case;
-- err data
if set_err_data = '1' then
arp_err_data <= data_in;
else
arp_err_data <= arp_err_data;
end if;
-- arp operation processing
if set_arp_oper = '1' then
arp_operation <= arp_oper_set_val;
else
arp_operation <= arp_operation;
end if;
-- source mac capture
if (set_mac5 = '1') then new_arp_entry.mac(47 downto 40) <= dataval; end if;
if (set_mac4 = '1') then new_arp_entry.mac(39 downto 32) <= dataval; end if;
if (set_mac3 = '1') then new_arp_entry.mac(31 downto 24) <= dataval; end if;
if (set_mac2 = '1') then new_arp_entry.mac(23 downto 16) <= dataval; end if;
if (set_mac1 = '1') then new_arp_entry.mac(15 downto 8) <= dataval; end if;
if (set_mac0 = '1') then new_arp_entry.mac(7 downto 0) <= dataval; end if;
-- source ip capture
if (set_ip3 = '1') then new_arp_entry.ip(31 downto 24) <= dataval; end if;
if (set_ip2 = '1') then new_arp_entry.ip(23 downto 16) <= dataval; end if;
if (set_ip1 = '1') then new_arp_entry.ip(15 downto 8) <= dataval; end if;
if (set_ip0 = '1') then new_arp_entry.ip(7 downto 0) <= dataval; end if;
-- set arp entry request
if count_arp_rcvd = '1' then
-- count another ARP pkt received
arp_req_count <= arp_req_count + 1;
else
arp_req_count <= arp_req_count;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 3fd3e7b663330923ac7a27b0fdb7874c | 0.494971 | 3.658827 | false | false | false | false |
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