repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
freecores/gpib_controller | vhdl/src/wrapper/InterruptGenerator.vhd | 1 | 3,752 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: InterruptGenerator
-- Date:2011-11-25
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.helperComponents.all;
entity InterruptGenerator is
port (
reset : std_logic;
clk : in std_logic;
interrupt : out std_logic;
-------------------- gpib device ---------------------
-- device is local controlled
isLocal : in std_logic;
-- input buffer ready
in_buf_ready : in std_logic;
-- output buffer ready
out_buf_ready : in std_logic;
-- clear device (DC)
clr : in std_logic;
-- trigger device (DT)
trg : in std_logic;
-- addressed to talk(L or LE)
att : in std_logic;
-- addressed to listen (T or TE)
atl : in std_logic;
-- seriall poll active
spa : in std_logic;
-------------------- gpib controller ---------------------
-- controller write commands
cwrc : in std_logic;
-- controller write data
cwrd : in std_logic;
-- service requested
srq : in std_logic;
-- parallel poll ready
ppr : in std_logic;
-- stb received
stb_received : in std_logic;
REN : in std_logic;
ATN : in std_logic;
IFC : in std_logic
);
end InterruptGenerator;
architecture arch of InterruptGenerator is
constant PULSE_WIDTH : integer := 10;
signal p0, p1, p2, p3, p4, p5, p6, p7 : std_logic;
begin
interrupt <= p0 or p1 or p2 or p3 or p4 or p5 or p6 or p7;
ed0: EdgeDetector generic map (RISING => '1', FALLING => '0',
PULSE_WIDTH => PULSE_WIDTH) port map (
reset => reset, clk => clk, in_data => in_buf_ready, pulse => p0
);
ed1: EdgeDetector generic map (RISING => '1', FALLING => '0',
PULSE_WIDTH => PULSE_WIDTH) port map (
reset => reset, clk => clk, in_data => out_buf_ready, pulse => p1
);
ed2: EdgeDetector generic map (RISING => '1', FALLING => '0',
PULSE_WIDTH => PULSE_WIDTH) port map (
reset => reset, clk => clk, in_data => clr, pulse => p2
);
ed3: EdgeDetector generic map (RISING => '1', FALLING => '0',
PULSE_WIDTH => PULSE_WIDTH) port map (
reset => reset, clk => clk, in_data => trg, pulse => p3
);
ed4: EdgeDetector generic map (RISING => '1', FALLING => '0',
PULSE_WIDTH => PULSE_WIDTH) port map (
reset => reset, clk => clk, in_data => srq, pulse => p4
);
ed5: EdgeDetector generic map (RISING => '1', FALLING => '0',
PULSE_WIDTH => PULSE_WIDTH) port map (
reset => reset, clk => clk, in_data => ppr, pulse => p5
);
ed6: EdgeDetector generic map (RISING => '1', FALLING => '0',
PULSE_WIDTH => PULSE_WIDTH) port map (
reset => reset, clk => clk, in_data => stb_received, pulse => p6
);
ed7: EdgeDetector generic map (RISING => '1', FALLING => '1',
PULSE_WIDTH => PULSE_WIDTH) port map (
reset => reset, clk => clk, in_data => isLocal, pulse => p7
);
end arch;
| gpl-3.0 | 634aaa1024d6cdb655a1a5544a4455f6 | 0.59968 | 3.467652 | false | false | false | false |
Nooxet/embedded_bruteforce | vhdl/string_generator.vhd | 1 | 6,728 | ----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: string_generator - Behavioral
-- Description:
-- A state machine to generate potential passwords
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity string_generator is
port (
clk : in std_logic;
rstn : in std_logic; -- active low reset ofc
i_start : in std_logic;
i_halt : in std_logic;
o_md5_start : out std_logic; -- when we write a string to md5 we also start them
o_done : out std_logic;
o_length : out std_logic_vector(2 downto 0); -- max 6 chars
o_string : out std_logic_vector(47 downto 0) -- 6 char string
);
end string_generator;
architecture Behavioral of string_generator is
type states is (init, c0, c1, c2, c3, c4, c5);
signal state_c, state_n : states;
constant low_chr : unsigned(7 downto 0) := x"61"; -- First character (a)
constant high_chr : unsigned(7 downto 0) := x"7A"; -- Last character generated (z)
signal chr0_c, chr1_c, chr2_c, chr3_c, chr4_c, chr5_c : unsigned(7 downto 0);
signal chr0_n, chr1_n, chr2_n, chr3_n, chr4_n, chr5_n : unsigned(7 downto 0);
signal len_c, len_n : unsigned(2 downto 0);
begin
clk_proc: process(clk)
begin
if rising_edge(clk) then
if rstn = '0' then
state_c <= init;
chr0_c <= (others => '0');
chr1_c <= (others => '0');
chr2_c <= (others => '0');
chr3_c <= (others => '0');
chr4_c <= (others => '0');
chr5_c <= (others => '0');
len_c <= (others => '0');
else
--if i_halt = '0' then -- only update when not halted
state_c <= state_n;
chr0_c <= chr0_n;
chr1_c <= chr1_n;
chr2_c <= chr2_n;
chr3_c <= chr3_n;
chr4_c <= chr4_n;
chr5_c <= chr5_n;
len_c <= len_n;
--end if;
end if;
end if;
end process clk_proc;
fsm_proc: process (i_start, state_c, chr0_c, chr1_c, chr2_c, chr3_c, chr4_c, chr5_c, len_c, i_halt)
begin
-- defaults
state_n <= state_c;
chr0_n <= chr0_c;
chr1_n <= chr1_c;
chr2_n <= chr2_c;
chr3_n <= chr3_c;
chr4_n <= chr4_c;
chr5_n <= chr5_c;
len_n <= len_c;
o_done <= '0';
o_md5_start <= '0';
if i_halt = '0' then
case state_c is
when init =>
chr0_n <= (others => '0');
chr1_n <= (others => '0');
chr2_n <= (others => '0');
chr3_n <= (others => '0');
chr4_n <= (others => '0');
chr5_n <= (others => '0');
len_n <= (others => '0');
o_md5_start <= '0'; -- don't run the md5 in init
if i_start = '1' then
state_n <= c0;
end if;
when c0 =>
chr0_n <= chr0_c + 1;
o_md5_start <= '1'; -- we are not halting so we have to start the next md5
if chr0_c = 0 then
chr0_n <= low_chr; -- set 'a' as the first character
len_n <= len_c + 1; -- string size grows by 1 when we use a new character
end if;
if chr0_c = high_chr then
chr0_n <= low_chr;
state_n <= c1;
end if;
when c1 =>
chr1_n <= chr1_c + 1;
state_n <= c0;
o_md5_start <= '1';
if chr1_c = 0 then
chr1_n <= low_chr;
len_n <= len_c + 1;
end if;
if chr1_c = high_chr then
chr1_n <= low_chr;
state_n <= c2;
end if;
when c2 =>
chr2_n <= chr2_c + 1;
state_n <= c0;
o_md5_start <= '1';
if chr2_c = 0 then
chr2_n <= low_chr;
len_n <= len_c + 1;
end if;
if chr2_c = high_chr then
chr2_n <= low_chr;
state_n <= c3;
end if;
when c3 =>
chr3_n <= chr3_c + 1;
state_n <= c0;
o_md5_start <= '1';
if chr3_c = 0 then
chr3_n <= low_chr;
len_n <= len_c + 1;
end if;
if chr3_c = high_chr then
chr3_n <= low_chr;
state_n <= c4;
end if;
when c4 =>
chr4_n <= chr4_c + 1;
state_n <= c0;
o_md5_start <= '1';
if chr4_c = 0 then
chr4_n <= low_chr;
len_n <= len_c + 1;
end if;
if chr4_c = high_chr then
chr4_n <= low_chr;
state_n <= c5;
end if;
when c5 =>
chr5_n <= chr5_c + 1;
state_n <= c0;
o_md5_start <= '1';
if chr5_c = 0 then
chr5_n <= low_chr;
len_n <= len_c + 1;
end if;
if chr5_c = high_chr then
chr5_n <= low_chr;
state_n <= init;
o_done <= '1'; -- We have now generated all possible passwords
end if;
when others => null;
end case;
end if;
end process;
-- Output logic
o_string <= std_logic_vector(chr5_c & chr4_c & chr3_c & chr2_c & chr1_c & chr0_c);
o_length <= std_logic_vector(len_c);
end Behavioral;
| mit | 3ed9c47bfa5d3c97c51cdfca6057bfc4 | 0.352259 | 3.969322 | false | false | false | false |
tsotnep/vhdl_soc_audio_mixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/filter_v1_00_a/hdl/vhdl/user_logic.vhd | 3 | 34,463 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Tue Apr 14 17:57:17 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 15;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
CLK_48 : in std_logic;
RST : in std_logic;
HP_BTN : in std_logic;
BP_BTN : in std_logic;
LP_BTN : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
signal reset, IIR_LP_Done_R, IIR_LP_Done_L, IIR_BP_Done_R, IIR_BP_Done_L, IIR_HP_Done_R, IIR_HP_Done_L: std_logic;
signal AUDIO_OUT_TRUNC_L, AUDIO_OUT_TRUNC_R, IIR_LP_Y_Out_R, IIR_LP_Y_Out_L, IIR_BP_Y_Out_R, IIR_BP_Y_Out_L, IIR_HP_Y_Out_R, IIR_HP_Y_Out_L: std_logic_vector(15 downto 0);
component IIR_Biquad_II is
Generic(
Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b0 ~ +0.0010232
Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0010_0001_1000_0111_0011_1001"; -- b1 ~ +0.0020464
Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b2 ~ +0.0010232
Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0101_1110_1011_0111_1110_0110_1000"; -- a1 ~ -1.9075016
Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_0101_0111_1001_0000_0111_0101"
);
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR (15 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
function Three_ASR ( val: signed (15 downto 0) ) return signed is begin
return val(15) & val(15) & val(15) & val(15 downto 3) ;
end Three_ASR;
function Two_ASR ( val: signed (15 downto 0) ) return signed is begin
return val(15) & val(15) & val(15 downto 2) ;
end Two_ASR;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg2 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg3 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg4 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg5 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg6 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg7 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg8 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg9 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg10 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg11 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg12 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg13 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg14 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
-- signal slv_reg15 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
-- signal slv_reg16 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
-- signal slv_reg17 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
-- signal slv_reg18 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
-- signal slv_reg19 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
-- signal slv_reg20 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
-- signal slv_reg21 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
-- signal slv_reg22 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
-- signal slv_reg23 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
-- signal slv_reg24 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
-- signal slv_reg25 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
-- signal slv_reg26 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
-- signal slv_reg27 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
-- signal slv_reg28 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
-- signal slv_reg29 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
-- signal slv_reg_write_sel : std_logic_vector(29 downto 0);
-- signal slv_reg_read_sel : std_logic_vector(29 downto 0);
signal slv_reg_write_sel : std_logic_vector(14 downto 0);
signal slv_reg_read_sel : std_logic_vector(14 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
---- connect all the "filter done" with an AND gate to the user_logic top level entity.
FILTER_DONE <= IIR_LP_Done_R and IIR_LP_Done_L and IIR_BP_Done_R and IIR_BP_Done_L and IIR_HP_Done_R and IIR_HP_Done_L;
-----Pad the Audio output with 8 zeros to make it up to 24 bit,
AUDIO_OUT_L <= AUDIO_OUT_TRUNC_L & X"00";
AUDIO_OUT_R <= AUDIO_OUT_TRUNC_R & X"00";
---this process controls each individual filter and the final output of the filter.
process (HP_BTN,BP_BTN, LP_BTN)
variable val: std_logic_vector(2 downto 0):= HP_BTN & BP_BTN & LP_BTN;
begin
case VAL is
when "000" =>
AUDIO_OUT_TRUNC_L <= (others => '0');--IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0');--IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
when "001" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R;
when "010" =>
AUDIO_OUT_TRUNC_L <= IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_BP_Y_Out_R;
when "011" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_BP_Y_Out_R;
when "100" =>
AUDIO_OUT_TRUNC_L <= IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_HP_Y_Out_R;
when "101" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_HP_Y_Out_R;
when "110" =>
AUDIO_OUT_TRUNC_L <= IIR_HP_Y_Out_L + IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_HP_Y_Out_R + IIR_BP_Y_Out_R;
when "111" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
when others =>
AUDIO_OUT_TRUNC_L <= (others => '0');--IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0');--IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
end case;
end process;
IIR_LP_R: IIR_Biquad_II
Generic Map
(
Coef_b0 => B"00_00_0000_0001_0000_1100_0011_1001_1100", -- b0 ~ +0.0010232
Coef_b1 => B"00_00_0000_0010_0001_1000_0111_0011_1001", -- b1 ~ +0.0020464
Coef_b2 => B"00_00_0000_0001_0000_1100_0011_1001_1100", -- b2 ~ +0.0010232
Coef_a1 => B"10_00_0101_1110_1011_0111_1110_0110_1000", -- a1 ~ -1.9075016
Coef_a2 => B"00_11_1010_0101_0111_1001_0000_0111_0101" -- a2 ~ +0.9115945
)
Port map (
clk => CLK_48,
rst => reset,
sample_trig => '1',--Sample_IIR,
X_in => AUDIO_IN_R(23 downto 8),
filter_done => IIR_LP_Done_R,
Y_out => IIR_LP_Y_Out_R
);
IIR_LP_L: IIR_Biquad_II
Generic Map
(
Coef_b0 => B"00_00_0000_0001_0000_1100_0011_1001_1100", -- b0 ~ +0.0010232
Coef_b1 => B"00_00_0000_0010_0001_1000_0111_0011_1001", -- b1 ~ +0.0020464
Coef_b2 => B"00_00_0000_0001_0000_1100_0011_1001_1100", -- b2 ~ +0.0010232
Coef_a1 => B"10_00_0101_1110_1011_0111_1110_0110_1000", -- a1 ~ -1.9075016
Coef_a2 => B"00_11_1010_0101_0111_1001_0000_0111_0101" -- a2 ~ +0.9115945
)
Port map (
clk => CLK_48,
rst => reset,
sample_trig => '1',--Sample_IIR,
X_in => AUDIO_IN_L(23 downto 8),--X_in_truncated_L,
filter_done => IIR_LP_Done_L,
Y_out => IIR_LP_Y_Out_L
);
IIR_BP_R: IIR_Biquad_II --(20 - 20000)
Generic Map
(
Coef_b0 => B"00_00_1101_1001_0100_1010_0010_0011_0000",-- b0 ~ +0.212196872
Coef_b1 => B"11_10_0101_0001_1010_0101_0110_1110_1000",-- b1 ~ -0.420267366
Coef_b2 => B"00_00_1101_1001_0100_1010_0010_0011_0000",-- b2 ~ +0.212196872
Coef_a1 => B"11_10_0101_0001_1010_0101_0110_1110_1000",-- a1 ~ -0.575606257
Coef_a2 => B"11_01_1011_0010_1001_0100_0100_0110_0000" -- a2 ~ +0.986994963
)
Port map (
clk => CLK_48,
rst => reset,
sample_trig => '1',--Sample_IIR,
X_in => AUDIO_IN_R(23 downto 8),--X_in_truncated_R,
filter_done => IIR_BP_Done_R,
Y_out => IIR_BP_Y_Out_R
);
IIR_BP_L: IIR_Biquad_II--(20 - 20000)
Generic Map
(
Coef_b0 => B"00_00_1101_1001_0100_1010_0010_0011_0000",-- b0 ~ +0.212196872
Coef_b1 => B"11_10_0101_0001_1010_0101_0110_1110_1000",-- b1 ~ -0.420267366
Coef_b2 => B"00_00_1101_1001_0100_1010_0010_0011_0000",-- b2 ~ +0.212196872
Coef_a1 => B"11_10_0101_0001_1010_0101_0110_1110_1000",-- a1 ~ -0.575606257
Coef_a2 => B"11_01_1011_0010_1001_0100_0100_0110_0000" -- a2 ~ +0.986994963
)
Port map (
clk => CLK_48,
rst => reset,
sample_trig => '1',--Sample_IIR,
X_in => AUDIO_IN_L(23 downto 8),--X_in_truncated_L,
filter_done => IIR_BP_Done_L,
Y_out => IIR_BP_Y_Out_L
);
IIR_HP_R: IIR_Biquad_II
Generic Map
(
Coef_b0 => B"00_00_0000_0000_1010_1011_0111_0101_1110",-- b0 ~ +0.00065407
Coef_b1 => B"00_00_0000_0000_0000_0000_0000_0000_0000",-- b1 ~ 0.0
Coef_b2 => B"11_11_1111_1111_0101_0100_1000_1010_0010",-- b2 ~ -0.00065407
Coef_a1 => B"10_00_0000_0001_0110_0100_0110_0011_0100",-- a1 ~ -1.998640489
Coef_a2 => B"00_11_1111_1110_1010_1001_0001_0100_0010" -- a2 ~ +0.998691859
)
Port map (
clk => CLK_48,
rst => reset,
sample_trig => '1',--Sample_IIR,
X_in => AUDIO_IN_R(23 downto 8),--X_in_truncated_R,
filter_done => IIR_HP_Done_R,
Y_out => IIR_HP_Y_Out_R
);
IIR_HP_L: IIR_Biquad_II
Generic Map
(
Coef_b0 => B"00_00_0000_0000_1010_1011_0111_0101_1110",-- b0 ~ +0.00065407
Coef_b1 => B"00_00_0000_0000_0000_0000_0000_0000_0000",-- b1 ~ 0.0
Coef_b2 => B"11_11_1111_1111_0101_0100_1000_1010_0010",-- b2 ~ -0.00065407
Coef_a1 => B"10_00_0000_0001_0110_0100_0110_0011_0100",-- a1 ~ -1.998640489
Coef_a2 => B"00_11_1111_1110_1010_1001_0001_0100_0010" -- a2 ~ +0.998691859
)
Port map (
clk => CLK_48,
rst => reset,
sample_trig => '1',--Sample_IIR,
X_in => AUDIO_IN_L(23 downto 8),--X_in_truncated_L,
filter_done => IIR_HP_Done_L,
Y_out => IIR_HP_Y_Out_L
);
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
-- slv_reg_write_sel <= Bus2IP_WrCE(29 downto 0);
-- slv_reg_read_sel <= Bus2IP_RdCE(29 downto 0);
slv_reg_write_sel <= Bus2IP_WrCE(14 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(14 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12) or Bus2IP_RdCE(13) or Bus2IP_RdCE(14) or Bus2IP_RdCE(15) or Bus2IP_RdCE(16) or Bus2IP_RdCE(17) or Bus2IP_RdCE(18) or Bus2IP_RdCE(19) or Bus2IP_RdCE(20) or Bus2IP_RdCE(21) or Bus2IP_RdCE(22) or Bus2IP_RdCE(23) or Bus2IP_RdCE(24) or Bus2IP_RdCE(25) or Bus2IP_RdCE(26) or Bus2IP_RdCE(27) or Bus2IP_RdCE(28) or Bus2IP_RdCE(29);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
-- slv_reg15 <= (others => '0');
-- slv_reg16 <= (others => '0');
-- slv_reg17 <= (others => '0');
-- slv_reg18 <= (others => '0');
-- slv_reg19 <= (others => '0');
-- slv_reg20 <= (others => '0');
-- slv_reg21 <= (others => '0');
-- slv_reg22 <= (others => '0');
-- slv_reg23 <= (others => '0');
-- slv_reg24 <= (others => '0');
-- slv_reg25 <= (others => '0');
-- slv_reg26 <= (others => '0');
-- slv_reg27 <= (others => '0');
-- slv_reg28 <= (others => '0');
-- slv_reg29 <= (others => '0');
else
case slv_reg_write_sel is
when "100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg8(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg9(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg10(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg11(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg12(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg13(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg14(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- when "000000000000000100000000000000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg15(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "000000000000000010000000000000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg16(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "000000000000000001000000000000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg17(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "000000000000000000100000000000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg18(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "000000000000000000010000000000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg19(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "000000000000000000001000000000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg20(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "000000000000000000000100000000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg21(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "000000000000000000000010000000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg22(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "000000000000000000000001000000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg23(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "000000000000000000000000100000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg24(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "000000000000000000000000010000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg25(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "000000000000000000000000001000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg26(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "000000000000000000000000000100" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg27(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "000000000000000000000000000010" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg28(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "000000000000000000000000000001" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg29(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14) is --, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29 ) is
begin
case slv_reg_read_sel is
when "100000000000000" => slv_ip2bus_data <= slv_reg0;
when "010000000000000" => slv_ip2bus_data <= slv_reg1;
when "001000000000000" => slv_ip2bus_data <= slv_reg2;
when "000100000000000" => slv_ip2bus_data <= slv_reg3;
when "000010000000000" => slv_ip2bus_data <= slv_reg4;
when "000001000000000" => slv_ip2bus_data <= slv_reg5;
when "000000100000000" => slv_ip2bus_data <= slv_reg6;
when "000000010000000" => slv_ip2bus_data <= slv_reg7;
when "000000001000000" => slv_ip2bus_data <= slv_reg8;
when "000000000100000" => slv_ip2bus_data <= slv_reg9;
when "000000000010000" => slv_ip2bus_data <= slv_reg10;
when "000000000001000" => slv_ip2bus_data <= slv_reg11;
when "000000000000100" => slv_ip2bus_data <= slv_reg12;
when "000000000000010" => slv_ip2bus_data <= slv_reg13;
when "000000000000001" => slv_ip2bus_data <= slv_reg14;
-- when "000000000000000100000000000000" => slv_ip2bus_data <= slv_reg15;
-- when "000000000000000010000000000000" => slv_ip2bus_data <= slv_reg16;
-- when "000000000000000001000000000000" => slv_ip2bus_data <= slv_reg17;
-- when "000000000000000000100000000000" => slv_ip2bus_data <= slv_reg18;
-- when "000000000000000000010000000000" => slv_ip2bus_data <= slv_reg19;
-- when "000000000000000000001000000000" => slv_ip2bus_data <= slv_reg20;
-- when "000000000000000000000100000000" => slv_ip2bus_data <= slv_reg21;
-- when "000000000000000000000010000000" => slv_ip2bus_data <= slv_reg22;
-- when "000000000000000000000001000000" => slv_ip2bus_data <= slv_reg23;
-- when "000000000000000000000000100000" => slv_ip2bus_data <= slv_reg24;
-- when "000000000000000000000000010000" => slv_ip2bus_data <= slv_reg25;
-- when "000000000000000000000000001000" => slv_ip2bus_data <= slv_reg26;
-- when "000000000000000000000000000100" => slv_ip2bus_data <= slv_reg27;
-- when "000000000000000000000000000010" => slv_ip2bus_data <= slv_reg28;
-- when "000000000000000000000000000001" => slv_ip2bus_data <= slv_reg29;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| mit | 025da11c23043e37dbac0a9915dd862f | 0.528712 | 3.105614 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib_helper/gpibReader.vhd | 1 | 4,311 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: gpibReader
-- Date: 2011-10-30
-- Author: Andrzej Paluch
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.utilPkg.all;
entity gpibReader is
port (
-- clock
clk : in std_logic;
-- reset
reset : std_logic;
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
-- input data
data_in : in std_logic_vector (7 downto 0);
-- data valid
dvd : in std_logic;
-- listener active
lac : in std_logic;
-- last byte
lsb : in std_logic;
-- ready to next byte
rdy : out std_logic;
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
-- is LE function active
isLE : in std_logic;
-- current secondary address
secAddr : in std_logic_vector (4 downto 0);
-- secondary address of data
dataSecAddr : out std_logic_vector (4 downto 0);
-- buffer ready interrupt
buf_interrupt : out std_logic;
-- indicates end of stream
end_of_stream : out std_logic;
-- resets reader
reset_reader : in std_logic;
------------------ fifo --------------------------------------
-- indicates fifo full
fifo_full : in std_logic;
-- indicates fifo ready to write
fifo_ready_to_write : in std_logic;
-- indicates at least one byte in fifo
at_least_one_byte_in_fifo : in std_logic;
-- output data
data_out : out std_logic_vector (7 downto 0);
-- fifo strobe
fifo_strobe : out std_logic
);
end gpibReader;
architecture arch of gpibReader is
-- reader states
type READER_STATE is (
ST_IDLE,
ST_WAIT_DVD_1,
ST_WAIT_DVD_0
);
signal current_state : READER_STATE;
signal buf_ready_to_write : boolean;
begin
buf_interrupt <= not to_stdl(buf_ready_to_write);
process (clk, reset, reset_reader) begin
if reset = '1' then
current_state <= ST_IDLE;
rdy <= '1';
buf_ready_to_write <= TRUE;
end_of_stream <= '0';
fifo_strobe <= '0';
dataSecAddr <= "00000";
elsif reset_reader='1' then
buf_ready_to_write <= TRUE;
end_of_stream <= '0';
fifo_strobe <= '0';
dataSecAddr <= "00000";
elsif rising_edge(clk) then
case current_state is
when ST_IDLE =>
if lac='1' and buf_ready_to_write then
if isLE = '1' then
dataSecAddr <= secAddr;
end if;
rdy <= '1';
current_state <= ST_WAIT_DVD_1;
elsif lac='0' and at_least_one_byte_in_fifo='1' then
buf_ready_to_write <= FALSE;
end if;
when ST_WAIT_DVD_1 =>
if dvd='1' and fifo_ready_to_write='1' then
fifo_strobe <= '1';
data_out <= data_in;
if lsb='1'or fifo_full='1' then
buf_ready_to_write <= FALSE;
end_of_stream <= lsb;
end if;
rdy <= '0';
current_state <= ST_WAIT_DVD_0;
elsif lac='0' then
current_state <= ST_IDLE;
end if;
when ST_WAIT_DVD_0 =>
if dvd='0' then
fifo_strobe <= '0';
current_state <= ST_IDLE;
end if;
when others =>
current_state <= ST_IDLE;
end case;
end if;
end process;
end arch;
| gpl-3.0 | 48e5408084c0500f5f3c16987752033a | 0.533519 | 3.672061 | false | false | false | false |
freecores/gpib_controller | vhdl/src/comm/Uart.vhd | 1 | 4,894 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: Uart
-- Date:2011-11-26
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Uart is
port (
reset : in std_logic;
clk : in std_logic;
---------- UART ---------------
RX : in std_logic;
TX : out std_logic;
---------- gpib ---------------
data_out : out std_logic_vector(7 downto 0);
data_out_ready : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_in_ready : in std_logic;
ready_to_send : out std_logic
);
end Uart;
architecture arch of Uart is
constant BIT_TIME : integer :=
-- 115200
--572
-- 921600
72
;
constant HALF_BIT_TIME : integer := BIT_TIME / 2;
type RX_STATES is (
ST_RX_IDLE,
ST_RX_HALF_START,
ST_RX_RECEIVE_BITS,
ST_RX_RECEIVE_STOP_BIT
);
type TX_STATES is (
ST_TX_IDLE,
ST_TX_SEND_BITS,
ST_TX_SEND_STOP_BIT
);
signal syncRX : std_logic;
signal rxState : RX_STATES;
signal lastRx : std_logic;
signal rxTimeCounter : integer range 0 to BIT_TIME;
signal rxBitCounter : integer range 0 to 7;
signal innerBuf : std_logic_vector(6 downto 0);
signal txState : TX_STATES;
signal lastData_in_ready : std_logic;
signal txTimeCounter : integer range 0 to BIT_TIME;
signal txBitCounter : integer range 0 to 8;
begin
-- RX synchronizer
process(clk, RX) begin
if rising_edge(clk) then
syncRX <= RX;
end if;
end process;
-- RX
process(reset, clk, syncRX) begin
if reset = '1' then
rxState <= ST_RX_IDLE;
lastRx <= syncRX;
data_out_ready <= '0';
elsif rising_edge(clk) then
lastRx <= syncRX;
if rxTimeCounter < BIT_TIME then
rxTimeCounter <= rxTimeCounter + 1;
end if;
case rxState is
when ST_RX_IDLE =>
if lastRx /= syncRX and syncRX = '0' then
rxTimeCounter <= 1;
rxState <= ST_RX_HALF_START;
end if;
when ST_RX_HALF_START =>
if rxTimeCounter >= HALF_BIT_TIME then
rxBitCounter <= 0;
rxTimeCounter <= 1;
rxState <= ST_RX_RECEIVE_BITS;
end if;
when ST_RX_RECEIVE_BITS =>
if rxTimeCounter >= BIT_TIME then
if rxBitCounter < 7 then
innerBuf(rxBitCounter) <= syncRX;
rxBitCounter <= rxBitCounter + 1;
rxTimeCounter <= 1;
elsif rxBitCounter = 7 then
data_out(7) <= syncRX;
data_out(6 downto 0) <= innerBuf;
data_out_ready <= '0';
rxTimeCounter <= 1;
rxState <= ST_RX_RECEIVE_STOP_BIT;
end if;
end if;
when ST_RX_RECEIVE_STOP_BIT =>
if rxTimeCounter >= BIT_TIME then
data_out_ready <= '1';
rxState <= ST_RX_IDLE;
end if;
when others =>
rxState <= ST_RX_IDLE;
end case;
end if;
end process;
-- TX
process(reset, clk, data_in_ready) begin
if reset = '1' then
TX <= '1';
ready_to_send <= '1';
txState <= ST_TX_IDLE;
elsif rising_edge(clk) then
lastData_in_ready <= data_in_ready;
if txTimeCounter < BIT_TIME then
txTimeCounter <= txTimeCounter + 1;
end if;
case txState is
when ST_TX_IDLE =>
if lastData_in_ready /= data_in_ready and
data_in_ready = '1' then
TX <= '0';
txTimeCounter <= 1;
txBitCounter <= 0;
ready_to_send <= '0';
txState <= ST_TX_SEND_BITS;
end if;
when ST_TX_SEND_BITS =>
if txTimeCounter >= BIT_TIME then
if txBitCounter < 8 then
TX <= data_in(txBitCounter);
txBitCounter <= txBitCounter + 1;
txTimeCounter <= 1;
elsif txBitCounter = 8 then
TX <= '1';
txTimeCounter <= 1;
txState <= ST_TX_SEND_STOP_BIT;
end if;
end if;
when ST_TX_SEND_STOP_BIT =>
if txTimeCounter >= BIT_TIME then
ready_to_send <= '1';
txState <= ST_TX_IDLE;
end if;
when others =>
txState <= ST_TX_IDLE;
end case;
end if;
end process;
end arch;
| gpl-3.0 | c5b58dd7672eb77477c09b5b72782be5 | 0.580915 | 3.34976 | false | false | false | false |
whitef0x0/EECE353-Lab4 | lab4.vhd | 1 | 3,935 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lab4 is
port(CLOCK_50 : in std_logic;
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(17 downto 0);
LEDG : out std_logic_vector(7 downto 0);
VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0); -- The outs go to VGA controller
VGA_HS : out std_logic;
VGA_VS : out std_logic;
VGA_BLANK : out std_logic;
VGA_SYNC : out std_logic;
VGA_CLK : out std_logic);
end lab4;
architecture rtl of lab4 is
-- Component from the Verilog file: vga_adapter.v
component vga_adapter
generic(RESOLUTION : string);
port (
resetn : in std_logic;
clock : in std_logic;
colour : in std_logic_vector(2 downto 0);
x : in std_logic_vector(7 downto 0);
y : in std_logic_vector(6 downto 0);
plot : in std_logic;
VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0);
VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK : out std_logic);
end component;
component fsm is
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
xdone, ydone, ldone : IN STD_LOGIC;
sw : IN STD_LOGIC_VECTOR(17 downto 0);
draw : IN STD_LOGIC;
resetx, resety, incr_y, incr_x, plot, initl, drawl : OUT STD_LOGIC;
colour : OUT STD_LOGIC_VECTOR(2 downto 0);
x : OUT STD_LOGIC_VECTOR(7 downto 0);
y : OUT STD_LOGIC_VECTOR(6 downto 0);
ledg : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component datapath is
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
resetx, resety, incr_y, incr_x, initl, drawl : IN STD_LOGIC;
x : OUT STD_LOGIC_VECTOR(7 downto 0);
y : OUT STD_LOGIC_VECTOR(6 downto 0);
xin : IN STD_LOGIC_VECTOR(7 downto 0); -- x1
yin : IN STD_LOGIC_VECTOR(6 downto 0); -- y1
xdone, ydone, ldone : OUT STD_LOGIC
);
end component;
signal s_x : std_logic_vector(7 downto 0) := "00000000";
signal s_y : std_logic_vector(6 downto 0) := "0000000";
signal colour : std_logic_vector(2 downto 0);
signal plot : std_logic;
signal resety, resetx, initl : std_logic;
signal xdone, ydone, ldone : std_logic;
signal incr_y, incr_x, drawl : std_logic;
signal x_int : std_logic_vector(7 downto 0);
signal y_int : std_logic_vector(6 downto 0);
begin
vga_u0 : vga_adapter
generic map(RESOLUTION => "160x120")
port map(resetn => KEY(3),
clock => CLOCK_50,
colour => colour,
x => s_x,
y => s_y,
plot => plot,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_HS => VGA_HS,
VGA_VS => VGA_VS,
VGA_BLANK => VGA_BLANK,
VGA_SYNC => VGA_SYNC,
VGA_CLK => VGA_CLK
);
fsm0 : fsm PORT MAP(
clock => CLOCK_50,
resetb => KEY(3),
xdone => xdone,
ydone => ydone,
ldone => ldone,
sw => SW,
draw => KEY(0),
resetx => resetx,
resety => resety,
incr_y => incr_y,
incr_x => incr_x,
plot => plot,
initl => initl,
drawl => drawl,
colour => colour,
x => x_int,
y => y_int,
ledg => LEDG
);
datapath0 : datapath PORT MAP(
clock => CLOCK_50,
resetb => KEY(3),
resetx => resetx,
resety => resety,
initl => initl,
drawl => drawl,
x => s_x,
y => s_y,
xin => x_int,
yin => y_int,
xdone => xdone,
ydone => ydone,
ldone => ldone,
incr_y => incr_y,
incr_x => incr_x
);
end rtl;
| mit | 57282ed2b39e71f635d1d345ebefa3cb | 0.505718 | 3.093553 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib/if_func_C.vhd | 1 | 12,435 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: if_func_C
-- Date: 23:00:30 10/04/2011
-- Author: Andrzej Paluch
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.utilPkg.all;
entity if_func_C is
port(
-- device inputs
clk : in std_logic; -- clock
pon : in std_logic; -- power on
gts : in std_logic; -- go to standby
rpp : in std_logic; -- request parallel poll
tcs : in std_logic; -- take control synchronously
tca : in std_logic; -- take control asynchronously
sic : in std_logic; -- send interface clear
rsc : in std_logic; -- request system control
sre : in std_logic; -- send remote enable
-- state inputs
TADS : in std_logic; -- talker addressed state (T or TE)
ACDS : in std_logic; -- accept data state (AH)
ANRS : in std_logic; -- acceptor not ready state (AH)
STRS : in std_logic; -- source transfer state (SH)
SDYS : in std_logic; -- source delay state (SH)
-- command inputs
ATN_in : in std_logic; -- attention
IFC_in : in std_logic; -- interface clear
TCT_in : in std_logic; -- take control
SRQ_in : in std_logic; -- service request
-- command outputs
ATN_out : out std_logic; -- attention
IFC_out : out std_logic; -- interface clear
TCT_out : out std_logic; -- take control
IDY_out : out std_logic; -- identify
REN_out : out std_logic; -- remote enable
-- reported states
CACS : out std_logic; -- controller active state
CTRS : out std_logic; -- controller transfer state
CSBS : out std_logic; -- controller standby state
CPPS : out std_logic; -- controller parallel poll state
CSRS : out std_logic; -- controller service requested state
SACS : out std_logic -- system control active state
);
end if_func_C;
architecture Behavioral of if_func_C is
-- states
type C_STATE_1 is (
-- controller idle state
ST_CIDS,
-- controller addressed state
ST_CADS,
-- controller transfer state
ST_CTRS,
-- controller active state
ST_CACS,
-- controller standby state
ST_CSBS,
-- controllet synchronous wait state
ST_CSWS,
-- controller active wait state
ST_CAWS,
-- controller parallel poll wait state
ST_CPWS,
-- controller parallel poll wait state
ST_CPPS
);
-- states
type C_STATE_2 is (
-- controller service not requested state
ST_CSNS,
-- controller service requested state
ST_CSRS
);
-- states
type C_STATE_3 is (
-- system control interface clear idle state
ST_SIIS,
-- system control interface clear active state
ST_SIAS,
-- system control interface clear not active state
ST_SINS
);
-- states
type C_STATE_4 is (
-- system control remote enable idle state
ST_SRIS,
-- system control remote enable active state
ST_SRAS,
-- system control remote enable not active state
ST_SRNS
);
-- states
type C_STATE_5 is (
-- system control not active state
ST_SNAS,
-- system control active state
ST_SACS
);
-- current state
signal current_state_1 : C_STATE_1;
signal current_state_2 : C_STATE_2;
signal current_state_3 : C_STATE_3;
signal current_state_4 : C_STATE_4;
signal current_state_5 : C_STATE_5;
-- events
signal event1_1, event1_2, event1_3, event1_4, event1_5,
event1_6, event1_7, event1_8, event1_9, event1_10,
event1_11, event1_12 : boolean;
signal event2_1, event2_2 : boolean;
signal event3_1, event3_2, event3_3, event3_4, event3_5 : boolean;
signal event4_1, event4_2, event4_3, event4_4, event4_5 : boolean;
signal event5_1, event5_2 : boolean;
-- timers
constant TIMER_T6_TIMEOUT : integer := 110;
constant TIMER_T7_TIMEOUT : integer := 25;
constant TIMER_T9_TIMEOUT : integer := 75;
constant TIMER_A_MAX : integer := 128;
signal timer_a : integer range 0 to TIMER_A_MAX;
signal timer_T6Expired : boolean;
signal timer_T7Expired : boolean;
signal timer_T9Expired : boolean;
constant TIMER_T8_TIMEOUT : integer := 5000;
constant TIMER_B_MAX : integer := 5004;
signal timer_b : integer range 0 to TIMER_B_MAX;
signal timer_b_1 : integer range 0 to TIMER_B_MAX;
signal timer_T8Expired : boolean;
signal timer_T8_1Expired : boolean;
begin
-- state machine process - C_STATE_1
process(pon, clk) begin
-- async reset
if pon='1' then
current_state_1 <= ST_CIDS;
elsif rising_edge(clk) then
-- timer
if timer_a < TIMER_A_MAX then
timer_a <= timer_a + 1;
end if;
-- state machine
case current_state_1 is
------------------
when ST_CIDS =>
if event1_1 then
-- no state change
elsif event1_2 then
current_state_1 <= ST_CADS;
end if;
------------------
when ST_CADS =>
if event1_1 then
current_state_1 <= ST_CIDS;
elsif event1_4 then
current_state_1 <= ST_CACS;
end if;
------------------
when ST_CACS =>
if event1_1 then
current_state_1 <= ST_CIDS;
elsif event1_5 then
current_state_1 <= ST_CTRS;
elsif event1_6 then
current_state_1 <= ST_CSBS;
elsif event1_7 then
timer_a <= 0;
current_state_1 <= ST_CPWS;
end if;
------------------
when ST_CTRS =>
if event1_1 then
current_state_1 <= ST_CIDS;
elsif event1_3 or event1_1 then
current_state_1 <= ST_CIDS;
end if;
------------------
when ST_CSBS =>
if event1_1 then
current_state_1 <= ST_CIDS;
elsif event1_9 then
timer_a <= 0;
current_state_1 <= ST_CSWS;
end if;
------------------
when ST_CSWS =>
if event1_1 then
current_state_1 <= ST_CIDS;
elsif event1_10 then
timer_a <= 0;
current_state_1 <= ST_CAWS;
end if;
------------------
when ST_CAWS =>
if event1_1 then
current_state_1 <= ST_CIDS;
elsif event1_8 then
current_state_1 <= ST_CACS;
elsif event1_7 then
timer_a <= 0;
current_state_1 <= ST_CPWS;
end if;
------------------
when ST_CPWS =>
if event1_1 then
current_state_1 <= ST_CIDS;
elsif event1_11 then
current_state_1 <= ST_CPPS;
end if;
------------------
when ST_CPPS =>
if event1_1 then
current_state_1 <= ST_CIDS;
elsif event1_12 then
current_state_1 <= ST_CAWS;
end if;
------------------
when others =>
current_state_1 <= ST_CIDS;
end case;
end if;
end process;
-- state machine process - C_STATE_2
process(pon, clk) begin
-- async reset
if pon='1' then
current_state_2 <= ST_CSNS;
elsif rising_edge(clk) then
-- state machine
case current_state_2 is
------------------
when ST_CSNS =>
if event2_1 then
current_state_2 <= ST_CSRS;
end if;
------------------
when ST_CSRS =>
if event2_2 then
current_state_2 <= ST_CSNS;
end if;
------------------
when others =>
current_state_2 <= ST_CSNS;
end case;
end if;
end process;
-- state machine process - C_STATE_3
process(pon, clk) begin
-- async reset
if pon='1' then
current_state_3 <= ST_SIIS;
elsif rising_edge(clk) then
-- timer
if timer_b < TIMER_B_MAX then
timer_b <= timer_b + 1;
end if;
-- state machine
case current_state_3 is
------------------
when ST_SIIS =>
if event3_1 then
-- no state change
elsif event3_2 then
timer_b <= 0;
current_state_3 <= ST_SIAS;
elsif event3_3 then
current_state_3 <= ST_SINS;
end if;
------------------
when ST_SIAS =>
if event3_1 then
current_state_3 <= ST_SIIS;
elsif event3_5 then
current_state_3 <= ST_SINS;
end if;
------------------
when ST_SINS =>
if event3_1 then
current_state_3 <= ST_SIIS;
elsif event3_4 then
current_state_3 <= ST_SIAS;
end if;
------------------
when others =>
current_state_3 <= ST_SIIS;
end case;
end if;
end process;
-- state machine process - C_STATE_4
process(pon, clk) begin
-- async reset
if pon='1' then
timer_b_1 <= 0;
current_state_4 <= ST_SRIS;
elsif rising_edge(clk) then
-- timer
if timer_b_1 < TIMER_B_MAX then
timer_b_1 <= timer_b_1 + 1;
end if;
-- state machine
case current_state_4 is
------------------
when ST_SRIS =>
if event4_1 then
-- no state change
elsif event4_2 then
timer_b_1 <= 0;
current_state_4 <= ST_SRAS;
elsif event4_3 then
current_state_4 <= ST_SRNS;
end if;
------------------
when ST_SRAS =>
if event4_1 then
current_state_4 <= ST_SRIS;
elsif event4_5 then
current_state_4 <= ST_SRNS;
end if;
------------------
when ST_SRNS =>
if event4_1 then
current_state_4 <= ST_SRIS;
elsif event4_4 then
timer_b_1 <= 0;
current_state_4 <= ST_SRAS;
end if;
------------------
when others =>
current_state_4 <= ST_SRIS;
end case;
end if;
end process;
-- state machine process - C_STATE_5
process(pon, clk) begin
-- async reset
if pon='1' then
current_state_5 <= ST_SNAS;
elsif rising_edge(clk) then
-- state machine
case current_state_5 is
------------------
when ST_SNAS =>
if event5_1 then
current_state_5 <= ST_SACS;
end if;
------------------
when ST_SACS =>
if event5_2 then
current_state_5 <= ST_SNAS;
end if;
------------------
when others =>
current_state_5 <= ST_SNAS;
end case;
end if;
end process;
-- events
event1_1 <= IFC_in='1' and current_state_5/=ST_SACS;
event1_2 <= (TCT_in='1' and TADS='1' and ACDS='1') or current_state_3=ST_SIAS;
event1_3 <= STRS='0';
event1_4 <= ATN_in='0';
event1_5 <= TCT_in='1' and TADS='0' and ACDS='1';
event1_6 <= SDYS='0' and STRS='0' and gts='1';
event1_7 <= rpp='1';
event1_8 <= timer_T9Expired and rpp='0';
event1_9 <= (tcs='1' and ANRS='1') or tca='1';
event1_10 <= timer_T7Expired;
event1_11 <= timer_T6Expired;
event1_12 <= rpp='0';
event2_1 <= SRQ_in='1';
event2_2 <= SRQ_in='0';
event3_1 <= current_state_5/=ST_SACS;
event3_2 <= current_state_5=ST_SACS and sic='1';
event3_3 <= current_state_5=ST_SACS and sic='0';
event3_4 <= sic='1';
event3_5 <= sic='0' and timer_T8Expired;
event4_1 <= current_state_5/=ST_SACS;
event4_2 <= current_state_5=ST_SACS and sre='1';
event4_3 <= current_state_5=ST_SACS and sre='0';
event4_4 <= sre='1';
event4_5 <= sre='0' and timer_T8_1Expired;
event5_1 <= rsc='1';
event5_2 <= rsc='0';
-- timers
timer_T6Expired <= timer_a >= TIMER_T6_TIMEOUT;
timer_T7Expired <= timer_a >= TIMER_T7_TIMEOUT;
timer_T9Expired <= timer_a >= TIMER_T9_TIMEOUT;
timer_T8Expired <= timer_b >= TIMER_T8_TIMEOUT;
timer_T8_1Expired <= timer_b_1 >= TIMER_T8_TIMEOUT;
CPPS <= to_stdl(current_state_1 = ST_CPPS);
CSRS <= to_stdl(current_state_2 = ST_CSRS);
CSBS <= to_stdl(current_state_1 = ST_CSBS);
CACS <= to_stdl(current_state_1 = ST_CACS);
SACS <= to_stdl(current_state_5 = ST_SACS);
-- CTRS
with current_state_1 select
CTRS <=
'1' when ST_CTRS,
'0' when others;
-- ATN
with current_state_1 select
ATN_out <=
'0' when ST_CIDS,
'0' when ST_CADS,
'0' when ST_CSBS,
'1' when others;
-- IDY_out
with current_state_1 select
IDY_out <=
'1' when ST_CPWS,
'1' when ST_CPPS,
'0' when others;
-- TCT
with current_state_1 select
TCT_out <=
'1' when ST_CTRS,
'0' when others;
-- IFC
with current_state_3 select
IFC_out <=
'1' when ST_SIAS,
'0' when others;
-- REN
with current_state_4 select
REN_out <=
'1' when ST_SRAS,
'0' when others;
end Behavioral;
| gpl-3.0 | 8d34714b2f952dbe0b5c38784012b146 | 0.588098 | 2.962831 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/pcores/bajsd_v1_00_a - Copy/hdl/vhdl/tb_hash_ctrl.vhd | 1 | 3,568 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:29:11 09/18/2014
-- Design Name:
-- Module Name: H:/embedded_labs/hash_ctrl/tb_hash_ctrl.vhd
-- Project Name: hash_ctrl
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: hash_ctrl
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_hash_ctrl IS
END tb_hash_ctrl;
ARCHITECTURE behavior OF tb_hash_ctrl IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT hash_ctrl
GENERIC( N : integer := 3);
PORT(
clk : IN std_logic;
rstn : IN std_logic;
i_string_done : IN std_logic;
i_md5_done : IN std_logic;
i_hash : IN std_logic_vector(127 downto 0);
i_start : IN std_logic;
o_md5_select : OUT std_logic_vector(2 downto 0);
o_start : OUT std_logic;
o_string_halt : OUT std_logic;
o_cmp_hash : OUT std_logic_vector(127 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rstn : std_logic := '0';
signal i_string_done : std_logic := '0';
signal i_md5_done : std_logic := '0';
signal i_hash : std_logic_vector(127 downto 0) := (others => '0');
signal i_start : std_logic := '0';
--Outputs
signal o_md5_select : std_logic_vector(2 downto 0);
signal o_start : std_logic;
signal o_string_halt : std_logic;
signal o_cmp_hash : std_logic_vector(127 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: hash_ctrl PORT MAP (
clk => clk,
rstn => rstn,
i_string_done => i_string_done,
i_md5_done => i_md5_done,
i_hash => i_hash,
i_start => i_start,
o_md5_select => o_md5_select,
o_start => o_start,
o_string_halt => o_string_halt,
o_cmp_hash => o_cmp_hash
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period;
rstn <= '0';
wait for clk_period;
rstn <= '1';
i_hash <= x"10203040102030401020304010203040";
wait for clk_period;
i_start <= '1';
wait for clk_period;
i_start <= '0';
--assert o_start = '1' report "ctrl is started but not the other components";
--assert o_cmp_hash = x"10203040102030401020304010203040" report "the cmp_hash was not forwarded";
wait for clk_period*3;
--assert o_string_halt = '1' report "not halting while in counting";
i_md5_done <= '1';
wait for clk_period;
i_md5_done <= '0';
wait for clk_period*4;
i_string_done <= '1';
wait;
end process;
END;
| mit | 91107f58b39c249050f015e73b9a34a3 | 0.589406 | 3.398095 | false | false | false | false |
esar/hdmilight-v2 | fpga/flashdma.vhd | 1 | 6,011 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2014 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity flashDMAController is
Port (
clk : in std_logic;
flashStartAddr : in std_logic_vector(23 downto 0);
sramStartAddr : in std_logic_vector(15 downto 0);
copySize : in std_logic_vector(15 downto 0);
write : in std_logic;
start : in std_logic;
busy : out std_logic;
we : out std_logic;
addr : out std_logic_vector(15 downto 0);
din : in std_logic_vector( 7 downto 0);
dout : out std_logic_vector( 7 downto 0);
spiClk : out std_logic;
spiCs : out std_logic;
spiSi : out std_logic;
spiSo : in std_logic
);
end flashDMAController;
architecture Behavioral of flashDMAController is
type StateType is (
STATE_IDLE,
STATE_READ_INIT, STATE_READ_CMD, STATE_READ_ADDR1, STATE_READ_ADDR2, STATE_READ_ADDR3, STATE_READ_ADDR4, STATE_READ_DATA,
STATE_WRITE_INIT
);
signal state : StateType;
signal nextState : StateType;
signal shiftOut : std_logic_vector(7 downto 0);
signal shiftIn : std_logic_vector(7 downto 0);
signal count : std_logic_vector(2 downto 0);
signal flashAddr : std_logic_vector(23 downto 0);
signal bytesLeft : std_logic_vector(15 downto 0);
signal intAddr : std_logic_vector(15 downto 0);
signal intWe : std_logic;
signal intSpiCs : std_logic;
begin
process(clk)
begin
if(rising_edge(clk)) then
state <= nextState;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
intWe <= '0';
shiftOut <= shiftOut(6 downto 0) & '0';
shiftIn <= shiftIn(6 downto 0) & spiSo;
count <= std_logic_vector(unsigned(count) + 1);
if(start = '1') then
intAddr <= sramStartAddr;
flashAddr <= flashStartAddr;
bytesLeft <= copySize;
count <= (others => '0');
if(write = '1') then
nextState <= STATE_WRITE_INIT;
else
nextState <= STATE_READ_INIT;
end if;
else
case state is
when STATE_IDLE =>
intSpiCs <= '1';
when STATE_READ_INIT =>
if(nextState = STATE_READ_CMD) then
intSpiCs <= '0';
end if;
shiftOut <= x"0B";
count <= "000";
nextState <= STATE_READ_CMD;
when STATE_READ_CMD =>
if(count = "111") then
shiftOut <= flashAddr(23 downto 16);
nextState <= STATE_READ_ADDR1;
end if;
when STATE_READ_ADDR1 =>
if(count = "111") then
shiftOut <= flashAddr(15 downto 8);
nextState <= STATE_READ_ADDR2;
end if;
when STATE_READ_ADDR2 =>
if(count = "111") then
shiftOut <= flashAddr(7 downto 0);
nextState <= STATE_READ_ADDR3;
end if;
when STATE_READ_ADDR3 =>
if(count = "111") then
shiftOut <= x"00";
nextState <= STATE_READ_ADDR4;
end if;
when STATE_READ_ADDR4 =>
if(count = "111") then
nextState <= STATE_READ_DATA;
end if;
when STATE_READ_DATA =>
if(count = "000") then
dout <= shiftIn;
intWe <= '1';
if(bytesLeft = x"0001") then
nextState <= STATE_IDLE;
end if;
bytesLeft <= std_logic_vector(unsigned(bytesLeft) - 1);
end if;
if(intWe = '1') then
intAddr <= std_logic_vector(unsigned(intAddr) + 1);
end if;
when STATE_WRITE_INIT =>
nextState <= STATE_IDLE;
--when STATE_WRITE_INIT =>
-- intSpiCs <= '0';
-- shiftOut <= x"0B";
-- count <= (others => '0');
-- nextState <= STATE_WRITE_ENABLE_CMD;
--when STATE_WRITE_ENABLE_CMD =>
-- if(count = "111") then
-- intSpiCs <= '1';
-- nextState <= STATE_WRITE_ERASE_INIT;
-- end if;
--when STATE_WRITE_ERASE_INIT =>
-- intSpiCs <= '0';
-- shiftOut <= x"0E";
-- nextState <= STATE_WRITE_ERASE_CMD;
--when STATE_WRITE_ERASE_CMD =>
-- if(count = "111") then
-- shiftOut <= flashAddr(23 downto 0);
-- nextState <= STATE_WRITE_ERASE_ADDR1;
-- end if;
--when STATE_WRITE_ERASE_ADDR1 =>
-- if(count = "111") then
-- shiftOut <= flashAddr(16 downto 8);
-- nextState <= STATE_WRITE_ERASE_ADDR2;
-- end if;
--when STATE_WRITE_ERASE_ADDR2 =>
-- if(count = "111") then
-- shiftOut <= flashAddr( 7 downto 0);
-- nextState <= STATE_WRITE_ERASE_ADDR3;
-- end if;
--when STATE_WRITE_ERASE_ADDR3 =>
-- if(count = "111") then
-- intSpiCs <= '1';
-- nextState <= STATE_WRITE_PROG_INIT;
-- end if;
--when STATE_WRITE_PROG_INIT =>
-- intSpiCs <= '0';
-- shiftOut <= x"13";
-- nextState <= STATE_WRITE_PROG_CMD;
--when STATE_WRITE_PROG_CMD =>
-- if(count = "111") then
end case;
end if;
end if;
end process;
clk_fwd : ODDR2
generic map
(
DDR_ALIGNMENT => "NONE",
INIT => '1',
SRTYPE => "SYNC"
)
port map
(
Q => spiClk,
C0 => clk,
C1 => not clk,
D0 => '1',
D1 => '0',
S => intSpiCs
);
busy <= not intSpiCs;
we <= intWe;
addr <= intAddr;
spiCs <= intSpiCs;
spiSi <= shiftOut(7);
end Behavioral;
| gpl-2.0 | 6d643a1d3ca246417d01f1751cdce652 | 0.584429 | 3.098454 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib_helper/MemoryBlock.vhd | 1 | 10,664 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: MemoryBlock
-- Date:2011-11-14
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
use work.utilPkg.all;
use work.helperComponents.all;
entity MemoryBlock is
port (
reset : in std_logic;
clk : in std_logic;
-------------------------------------------------
p1_addr : in std_logic_vector(10 downto 0);
p1_data_in : in std_logic_vector(7 downto 0);
p1_strobe : in std_logic;
p1_data_out : out std_logic_vector(7 downto 0);
-------------------------------------------------
p2_addr : in std_logic_vector(10 downto 0);
p2_data_in : in std_logic_vector(7 downto 0);
p2_strobe : in std_logic;
p2_data_out : out std_logic_vector(7 downto 0)
);
end MemoryBlock;
architecture arch of MemoryBlock is
constant ADDR_WIDTH : integer := 11;
constant DATA_WIDTH : integer := 8;
signal m_p1_parity_in, m_p1_parity_out : std_logic_vector(0 downto 0);
signal m_p1_data_in, m_p1_data_out :
std_logic_vector((DATA_WIDTH-1) downto 0);
signal m_p1_addr : std_logic_vector((ADDR_WIDTH-1) downto 0);
signal m_p1_clk, m_p1_en, m_p1_ssr, m_p1_we : std_logic;
signal m_p2_parity_in, m_p2_parity_out : std_logic_vector(0 downto 0);
signal m_p2_data_in, m_p2_data_out :
std_logic_vector((DATA_WIDTH-1) downto 0);
signal m_p2_addr : std_logic_vector((ADDR_WIDTH-1) downto 0);
signal m_p2_clk, m_p2_en, m_p2_ssr, m_p2_we : std_logic;
begin
m_p1_en <= '1';
m_p2_en <= '1';
m_p1_ssr <= reset;
m_p2_ssr <= reset;
m_p1_addr <= p1_addr;
m_p2_addr <= p2_addr;
p1_data_out <= m_p1_data_out;
p2_data_out <= m_p2_data_out;
m_p1_data_in <= p1_data_in;
m_p2_data_in <= p2_data_in;
m_p1_clk <= clk;
m_p2_clk <= clk;
m_p1_we <= p1_strobe;
m_p2_we <= p2_strobe;
-- RAMB16_S9_S9: Virtex-II/II-Pro, Spartan-3/3E 2k x 8 + 1 Parity bit Dual-Port RAM
-- Xilinx HDL Language Template, version 9.1i
RAMB16_S9_S9_inst : RAMB16_S9_S9
generic map (
INIT_A => X"000", -- Value of output RAM registers on Port A at startup
INIT_B => X"000", -- Value of output RAM registers on Port B at startup
SRVAL_A => X"000", -- Port A ouput value upon SSR assertion
SRVAL_B => X"000", -- Port B ouput value upon SSR assertion
WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
-- The following INIT_xx declarations specify the initial contents of the RAM
-- Address 0 to 511
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 1023
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1024 to 1535
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1536 to 2047
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INITP_xx are for the parity bits
-- Address 0 to 511
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 1023
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1024 to 1535
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1536 to 2047
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DOA => m_p1_data_out, -- Port A 8-bit Data Output
DOB => m_p2_data_out, -- Port B 8-bit Data Output
DOPA => m_p1_parity_out, -- Port A 1-bit Parity Output
DOPB => m_p2_parity_out, -- Port B 1-bit Parity Output
ADDRA => m_p1_addr, -- Port A 11-bit Address Input
ADDRB => m_p2_addr, -- Port B 11-bit Address Input
CLKA => m_p1_clk, -- Port A Clock
CLKB => m_p2_clk, -- Port B Clock
DIA => m_p1_data_in, -- Port A 8-bit Data Input
DIB => m_p2_data_in, -- Port B 8-bit Data Input
DIPA => m_p1_parity_in, -- Port A 1-bit parity Input
DIPB => m_p2_parity_in, -- Port-B 1-bit parity Input
ENA => m_p1_en, -- Port A RAM Enable Input
ENB => m_p2_en, -- PortB RAM Enable Input
SSRA => m_p1_ssr, -- Port A Synchronous Set/Reset Input
SSRB => m_p2_ssr, -- Port B Synchronous Set/Reset Input
WEA => m_p1_we, -- Port A Write Enable Input
WEB => m_p2_we -- Port B Write Enable Input
);
end arch;
| gpl-3.0 | 77a6eda6399b3ea5b7f4c31c1c93c3fe | 0.755533 | 4.469405 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/rawUVCfifo/simulation/rawUVCfifo_tb.vhd | 3 | 6,361 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rawUVCfifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.rawUVCfifo_pkg.ALL;
ENTITY rawUVCfifo_tb IS
END ENTITY;
ARCHITECTURE rawUVCfifo_arch OF rawUVCfifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
CONSTANT rd_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 400 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from rawUVCfifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of rawUVCfifo_synth
rawUVCfifo_synth_inst:rawUVCfifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 92
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| bsd-2-clause | a99068411660ec2476845280eec1ba33 | 0.613583 | 4.187623 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/system_brutus_0_wrapper.vhd | 1 | 1,823 | -------------------------------------------------------------------------------
-- system_brutus_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library brutus_v1_00_a;
use brutus_v1_00_a.all;
entity system_brutus_0_wrapper is
port (
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
);
end system_brutus_0_wrapper;
architecture STRUCTURE of system_brutus_0_wrapper is
component brutus is
port (
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
);
end component;
begin
brutus_0 : brutus
port map (
FSL_Clk => FSL_Clk,
FSL_Rst => FSL_Rst,
FSL_S_Clk => FSL_S_Clk,
FSL_S_Read => FSL_S_Read,
FSL_S_Data => FSL_S_Data,
FSL_S_Control => FSL_S_Control,
FSL_S_Exists => FSL_S_Exists,
FSL_M_Clk => FSL_M_Clk,
FSL_M_Write => FSL_M_Write,
FSL_M_Data => FSL_M_Data,
FSL_M_Control => FSL_M_Control,
FSL_M_Full => FSL_M_Full
);
end architecture STRUCTURE;
| mit | bbc95695b514ef4489943d29d8b23701 | 0.546901 | 3.084602 | false | false | false | false |
whitef0x0/EECE353-Lab4 | vga_demo.vhd | 1 | 2,227 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity vga_demo is
port(
CLOCK_50 : in std_logic;
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(17 downto 0);
VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0);
VGA_HS : out std_logic;
VGA_VS : out std_logic;
VGA_BLANK : out std_logic;
VGA_SYNC : out std_logic;
VGA_CLK : out std_logic
);
end vga_demo;
architecture rtl of vga_demo is
component vga_adapter ---- Component from the Verilog file: vga_adapter.v
generic(
RESOLUTION : string
);
port (
resetn : in std_logic;
clock : in std_logic;
colour : in std_logic_vector(2 downto 0);
x : in std_logic_vector(7 downto 0);
y : in std_logic_vector(6 downto 0);
plot : in std_logic;
VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0);
VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK : out std_logic
);
end component;
signal resetn : std_logic;
signal x : std_logic_vector(7 downto 0);
signal y : std_logic_vector(6 downto 0);
signal colour : std_logic_vector(2 downto 0);
signal plot : std_logic;
begin
resetn <= KEY(3);
x <= SW(7 downto 0);
y <= SW(14 downto 8);
colour <= SW(17 downto 15);
plot <= not KEY(0);
vga_u0 : vga_adapter
generic map(
RESOLUTION => "160x120"
) ---- Sets the resolution of display (as per vga_adapter.v description)
port map(
resetn => resetn,
clock => CLOCK_50,
colour => colour,
x => x,
y => y,
plot => plot,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_HS => VGA_HS,
VGA_VS => VGA_VS,
VGA_BLANK => VGA_BLANK,
VGA_SYNC => VGA_SYNC,
VGA_CLK => VGA_CLK
);
end rtl;
| mit | 7a0a93d2a91829f7256129a17d9420b7 | 0.458464 | 3.687086 | false | false | false | false |
mithro/HDMI2USB | hdl/misc/controller.vhd | 1 | 13,424 | -- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--
-- Adds
-- U = usb/uvc
-- J = jpeg encoder
-- S = source selector
-- H = Hdmi
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity controller is
port
(
status : out std_logic_vector(4 downto 0);
usb_cmd : out std_logic_vector(2 downto 0); -- UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2)
jpeg_encoder_cmd : out std_logic_vector(1 downto 0); -- encodingQuality(1 downto 0)
selector_cmd : out std_logic_vector(12 downto 0); -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
HB_on : out std_logic;
uart_rd : out std_logic;
uart_rx_empty : in std_logic;
uart_din : in std_logic_vector(7 downto 0);
uart_clk : in std_logic;
usb_or_uart : in std_logic;
hdmi_cmd : out std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
hdmi_dvi : in std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
rdy_H : in std_logic_vector(1 downto 0);
btnu : in std_logic;
btnd : in std_logic;
btnl : in std_logic;
btnr : in std_logic;
uvc_rst : out std_logic;
cmd_byte : in std_logic_vector(7 downto 0);
cmd_en : in std_logic;
rst : in std_logic;
ifclk : in std_logic;
clk : in std_logic
);
end entity;
ARCHITECTURE rtl OF controller is
COMPONENT cmdfifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
signal usb_cmd_i : std_logic_vector(2 downto 0); -- UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2)
signal jpeg_encoder_cmd_i : std_logic_vector(1 downto 0); -- encodingQuality(1 downto 0)
signal selector_cmd_i : std_logic_vector(12 downto 0); -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
signal HB_on_i : std_logic;
signal hdmi_cmd_i : std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
signal hdmi_dvi_q : std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
signal counter : std_logic_vector(7 downto 0);
signal cmd : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal add : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal rd_en : STD_LOGIC;
signal dout : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal full : STD_LOGIC;
signal almost_full : STD_LOGIC;
signal empty : STD_LOGIC;
signal almost_empty : STD_LOGIC;
signal valid : STD_LOGIC;
signal uvc_rst_i : STD_LOGIC;
signal vsync_q : STD_LOGIC;
signal vsync_rising_edge : STD_LOGIC;
signal pressed : STD_LOGIC;
signal toggle : STD_LOGIC;
signal uart_rd_s : STD_LOGIC;
signal empty_s : STD_LOGIC;
signal fifo_din : STD_LOGIC_VECTOR(7 downto 0);
signal fifo_clk : STD_LOGIC;
signal fifo_wr : STD_LOGIC;
begin
-- comb logic
usb_cmd <= usb_cmd_i;
jpeg_encoder_cmd <= jpeg_encoder_cmd_i;
selector_cmd <= selector_cmd_i;
hdmi_cmd <= hdmi_cmd_i;
HB_on <= HB_on_i;
-- CMD Decoder
process(rst,clk)
begin
if rst = '1' then
usb_cmd_i <= "001"; -- uvc on/off(2) raw/jpeg(1) UVCpayloadheader(0)
jpeg_encoder_cmd_i <= "00"; -- encodingQuality(1 downto 0)
selector_cmd_i(3 downto 0) <= "0111"; -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted)
selector_cmd_i(12 downto 4) <= "111000000"; --(4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
HB_on_i <= '1';
hdmi_cmd_i <= "11"; -- if 1 then dvi else hdmi
uvc_rst_i <= '1';
pressed <= '0';
hdmi_dvi_q <= "00";
status <= (others => '0');
toggle <= '0';
counter <= (others => '0');
elsif rising_edge(clk) then
if uvc_rst_i = '1' then
uvc_rst <= '1';
counter <= (others => '0');
toggle <= '1';
else
counter <= counter+1;
end if;
if counter = (counter'range => '1') and toggle = '1' then
uvc_rst <= '0';
toggle <= '0';
end if;
uvc_rst_i <= '0';
status <= (others => '0');
rd_en <= '0';
hdmi_dvi_q <= hdmi_dvi;
if (hdmi_dvi_q(0) xor hdmi_dvi(0)) = '1' then
hdmi_cmd_i(0) <= hdmi_dvi(0);
end if;
if (hdmi_dvi_q(1) xor hdmi_dvi(1)) = '1' then
hdmi_cmd_i(1) <= hdmi_dvi(1);
end if;
if btnd = '1' and pressed = '0' then
uvc_rst_i <= '1';
selector_cmd_i(1 downto 0) <= "11";
pressed <= '1';
else
pressed <= '0';
end if;
if btnl = '1' and pressed = '0' and rdy_H(1) = '1' then
uvc_rst_i <= '1';
selector_cmd_i(1 downto 0) <= "01";
pressed <= '1';
else
pressed <= '0';
end if;
if btnu = '1' and pressed = '0' and rdy_H(0) = '1' then
uvc_rst_i <= '1';
selector_cmd_i(1 downto 0) <= "00";
pressed <= '1';
else
pressed <= '0';
end if;
if empty = '0' and rd_en = '0' then
rd_en <= '1';
case add is
when X"55" | X"75" => -- U UVC/USB / UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2)
case cmd is
when X"4a" | X"6a" => -- J j
usb_cmd_i(1) <= '1';
uvc_rst_i <= '1';
when X"52" | X"72" => -- Rr
usb_cmd_i(1) <= '0';
uvc_rst_i <= '1';
when X"4e" | X"6e" => -- N n (on)
usb_cmd_i(2) <= '1';
uvc_rst_i <= '1';
when X"46" | X"66" => -- Ff (off)
usb_cmd_i(2) <= '0';
uvc_rst_i <= '1';
when X"56" | X"76" => -- V v (video) header on
usb_cmd_i(0) <= '1';
uvc_rst_i <= '1';
when X"49" | X"69" => -- I i (image) header off
usb_cmd_i(0) <= '0';
uvc_rst_i <= '1';
when X"53" | X"73" => -- Status
status(0) <= '1';
when X"48" | X"68" => -- H
uvc_rst_i <= '1';
if (selector_cmd_i(1 downto 0) = "00") then -- hdmi 0
hdmi_cmd_i(0) <= '0'; -- HDMI
elsif (selector_cmd_i(1 downto 0) = "01") then -- hdmi 1
hdmi_cmd_i(1) <= '0'; -- HDMI
end if;
when X"44" | X"64" => -- D
uvc_rst_i <= '1';
if (selector_cmd_i(1 downto 0) = "00") then -- hdmi 0
hdmi_cmd_i(0) <= '1'; -- DVI
elsif (selector_cmd_i(1 downto 0) = "01") then -- hdmi 1
hdmi_cmd_i(1) <= '1'; -- DVI
end if;
when others =>
end case;
when X"4a" | X"6a" => -- J Jpeg
case cmd is
when X"53" | X"73" => -- Status
status(1) <= '1';
when X"30" => -- quality 100 %
jpeg_encoder_cmd_i(1 downto 0) <= "00";
when X"31" => -- quality 85%
jpeg_encoder_cmd_i(1 downto 0) <= "01";
when X"32" => -- quality 75%
jpeg_encoder_cmd_i(1 downto 0) <= "10";
when X"33" => -- quality 50%
jpeg_encoder_cmd_i(1 downto 0) <= "11";
when others =>
end case;
when X"48" | X"68" => -- H Hdmi
case cmd is
when X"53" | X"73" => -- Status
status(3) <= '1';
when X"30" => -- Force HDMI 0 to 720p
hdmi_cmd_i(0) <= '0';
uvc_rst_i <= '1';
when X"31" => -- Force HDMI 0 to 1024
hdmi_cmd_i(0) <= '1';
uvc_rst_i <= '1';
when X"32" => -- Force HDMI 1 to 720p
hdmi_cmd_i(1) <= '0';
uvc_rst_i <= '1';
when X"33" => -- Force HDMI 1 to 1024
hdmi_cmd_i(0) <= '1';
uvc_rst_i <= '1';
when others =>
end case;
when X"53" | X"73" => -- S Source Selector
case cmd is -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
when X"53" | X"73" => -- Status
status(2) <= '1';
when X"55" | X"75" => -- U button force source to HDMI0
if rdy_H(0) = '1' then
selector_cmd_i(1 downto 0) <= "00";
uvc_rst_i <= '1';
end if;
when X"4c" | X"6c" => -- L button force source to HDMI1
if rdy_H(1) = '1' then
selector_cmd_i(1 downto 0) <= "01";
uvc_rst_i <= '1';
end if;
when X"52" | X"72" => -- V button force source to VGA
-- selector_cmd_i(1 downto 0) <= "10";
when X"44" | X"64" => -- D button force source to test pattern
selector_cmd_i(1 downto 0) <= "11";
uvc_rst_i <= '1';
when X"47" | X"67" => -- Froce Gray
selector_cmd_i(2) <= '0';
when X"43" | X"63" => -- Froce Color
selector_cmd_i(2) <= '1';
when X"49" | X"69" => -- Invert Color
selector_cmd_i(3) <= not selector_cmd_i(3);
when X"48" | X"68" => -- Heart Beat On/Off
HB_on_i <= not HB_on_i;
when others =>
end case;
-- RGB (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
when X"52" | X"72" => -- Red
case cmd is
when X"4e" | X"6e" => -- N n (on)
selector_cmd_i(12) <= '1';
when X"46" | X"66" => -- Ff (off)
selector_cmd_i(12) <= '0';
when X"30" =>
selector_cmd_i(9 downto 8) <= "00";
when X"31" =>
selector_cmd_i(9 downto 8) <= "01";
when X"32" =>
selector_cmd_i(9 downto 8) <= "10";
when X"33" =>
selector_cmd_i(9 downto 8) <= "11";
when others =>
end case;
when X"47" | X"67" => -- Green (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
case cmd is
when X"4e" | X"6e" => -- N n (on)
selector_cmd_i(11) <= '1';
when X"46" | X"66" => -- Ff (off)
selector_cmd_i(11) <= '0';
when X"30" =>
selector_cmd_i(7 downto 6) <= "00";
when X"31" =>
selector_cmd_i(7 downto 6) <= "01";
when X"32" =>
selector_cmd_i(7 downto 6) <= "10";
when X"33" =>
selector_cmd_i(7 downto 6) <= "11";
when others =>
end case;
when X"42" | X"62" => -- Blue
case cmd is
when X"4e" | X"6e" => -- N n (on)
selector_cmd_i(10) <= '1';
when X"46" | X"66" => -- Ff (off)
selector_cmd_i(10) <= '0';
when X"30" =>
selector_cmd_i(5 downto 4) <= "00";
when X"31" =>
selector_cmd_i(5 downto 4) <= "01";
when X"32" =>
selector_cmd_i(5 downto 4) <= "10";
when X"33" =>
selector_cmd_i(5 downto 4) <= "11";
when others =>
end case;
when X"44" | X"64" => --Debug
case cmd is
when X"53" | X"73" => --Status
status(4) <= '1';
when others =>
end case;
when others =>
end case; -- case add
end if; -- cmd_en
end if; -- clk
end process;
uart_rd <= uart_rd_s;
uart_ctrl : process(uart_clk, uart_rx_empty, empty_s)
begin
if rst = '1' then
uart_rd_s <= '0';
elsif rising_edge(uart_clk) then
empty_s <= uart_rx_empty;
end if;
if empty_s = '1' and uart_rx_empty = '0' then
uart_rd_s <= '1';
end if;
if empty_s = uart_rx_empty then
uart_rd_s <= '0';
end if;
end process;
fifo_mux: process(usb_or_uart, uart_rd_s, cmd_en, uart_din, cmd_byte, uart_clk, ifclk)
begin
if usb_or_uart = '0' then
fifo_din <= cmd_byte;
fifo_wr <= cmd_en;
fifo_clk <= ifclk;
else
fifo_din <= uart_din;
fifo_wr <= uart_rd_s;
fifo_clk <= uart_clk;
end if;
end process;
cmd <= dout(7 downto 0);
add <= dout(15 downto 8);
cmdfifo_comp : cmdfifo
PORT MAP (
rst => rst,
wr_clk => fifo_clk,
rd_clk => clk,
din => fifo_din,
wr_en => fifo_wr,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty,
valid => valid
);
END ARCHITECTURE;
| bsd-2-clause | e5a69d17df480d26c106879a6f31b88e | 0.544324 | 2.717959 | false | false | false | false |
esar/hdmilight-v2 | fpga/avr/reg_16.vhd | 3 | 2,023 | -------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: Register - Behavioral
-- Create Date: 12:37:55 10/28/2009
-- Description: a register pair of a CPU.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg_16 is
port ( I_CLK : in std_logic;
I_D : in std_logic_vector (15 downto 0);
I_WE : in std_logic_vector ( 1 downto 0);
Q : out std_logic_vector (15 downto 0));
end reg_16;
architecture Behavioral of reg_16 is
signal L : std_logic_vector (15 downto 0) := X"7777";
begin
process(I_CLK)
begin
if (rising_edge(I_CLK)) then
if (I_WE(1) = '1') then
L(15 downto 8) <= I_D(15 downto 8);
end if;
if (I_WE(0) = '1') then
L( 7 downto 0) <= I_D( 7 downto 0);
end if;
end if;
end process;
Q <= L;
end Behavioral;
| gpl-2.0 | 411cc866a211be3620c60b84ae17963a | 0.508156 | 4.078629 | false | false | false | false |
UdayanSinha/Code_Blocks | VHDL/Projects/work/data_bus.vhd | 1 | 1,185 | LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY data_bus IS
PORT(data_in: IN STD_LOGIC_VECTOR(3 DOWNTO 0); --data bus
data_out: OUT STD_LOGIC_VECTOR(3 DOWNTO 0):="ZZZZ";
en0, en1, rd_wr0, rd_wr1, clk, rst: IN STD_LOGIC); --register read-write select, clock, register select
END data_bus;
ARCHITECTURE behave of data_bus IS
COMPONENT register_generic IS
GENERIC(size: INTEGER);
PORT(d: IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0));
END COMPONENT;
SIGNAL d0, d1, q0, q1: STD_LOGIC_VECTOR(3 DOWNTO 0); --register internal outputs and inputs
BEGIN
R0: register_generic GENERIC MAP(4) PORT MAP (d0, clk, rst, q0);
R1: register_generic GENERIC MAP(4) PORT MAP (d1, clk, rst, q1);
data_out<=q0 WHEN en0='1' AND rd_wr0='0' else others=>'Z';
data_out<=q1 WHEN en1='1' AND rd_wr1='0' else others=>'Z';
d0<=data_in WHEN en0='1' AND rd_wr0='1';
d1<=data_in WHEN en1='1' AND rd_wr1='1';
END behave; | mit | f24c73f09352b28623d834d61509e3ad | 0.669198 | 2.9625 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/system_microblaze_0_i_bram_ctrl_wrapper.vhd | 1 | 18,546 | -------------------------------------------------------------------------------
-- system_microblaze_0_i_bram_ctrl_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_10_a;
use lmb_bram_if_cntlr_v3_10_a.all;
entity system_microblaze_0_i_bram_ctrl_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_microblaze_0_i_bram_ctrl_wrapper : entity is "lmb_bram_if_cntlr_v3_10_a";
end system_microblaze_0_i_bram_ctrl_wrapper;
architecture STRUCTURE of system_microblaze_0_i_bram_ctrl_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_FAMILY : string;
C_MASK : std_logic_vector(0 to 31);
C_MASK1 : std_logic_vector(0 to 31);
C_MASK2 : std_logic_vector(0 to 31);
C_MASK3 : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_ECC : integer;
C_INTERCONNECT : integer;
C_FAULT_INJECT : integer;
C_CE_FAILING_REGISTERS : integer;
C_UE_FAILING_REGISTERS : integer;
C_ECC_STATUS_REGISTERS : integer;
C_ECC_ONOFF_REGISTER : integer;
C_ECC_ONOFF_RESET_VALUE : integer;
C_CE_COUNTER_WIDTH : integer;
C_WRITE_ACCESS : integer;
C_NUM_LMB : integer;
C_SPLB_CTRL_BASEADDR : std_logic_vector;
C_SPLB_CTRL_HIGHADDR : std_logic_vector;
C_SPLB_CTRL_AWIDTH : INTEGER;
C_SPLB_CTRL_DWIDTH : INTEGER;
C_SPLB_CTRL_P2P : INTEGER;
C_SPLB_CTRL_MID_WIDTH : INTEGER;
C_SPLB_CTRL_NUM_MASTERS : INTEGER;
C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER;
C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER;
C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1));
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1));
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
begin
microblaze_0_i_bram_ctrl : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00007fff",
C_FAMILY => "spartan6",
C_MASK => X"40000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_NUM_LMB => 1,
C_SPLB_CTRL_BASEADDR => X"FFFFFFFF",
C_SPLB_CTRL_HIGHADDR => X"00000000",
C_SPLB_CTRL_AWIDTH => 32,
C_SPLB_CTRL_DWIDTH => 32,
C_SPLB_CTRL_P2P => 0,
C_SPLB_CTRL_MID_WIDTH => 1,
C_SPLB_CTRL_NUM_MASTERS => 1,
C_SPLB_CTRL_SUPPORT_BURSTS => 0,
C_SPLB_CTRL_NATIVE_DWIDTH => 32,
C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF",
C_S_AXI_CTRL_HIGHADDR => X"00000000",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
Interrupt => Interrupt,
UE => UE,
CE => CE,
SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus,
SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid,
SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID,
SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW,
SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE,
SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size,
SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type,
SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus,
SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck,
SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize,
SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait,
SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate,
SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck,
SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp,
SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus,
SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck,
SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp,
SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy,
SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr,
SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr,
SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus,
SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid,
SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim,
SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim,
SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort,
SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock,
SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize,
SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr,
SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst,
SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst,
SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq,
SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq,
SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri,
SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri,
SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri,
SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute,
SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm,
SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr,
SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm,
SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ,
S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY
);
end architecture STRUCTURE;
| mit | c311405d3f7955236ab3ab9126d04f27 | 0.616575 | 2.929395 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib/if_func_T_TE.vhd | 1 | 7,415 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: if_func_T_TE
-- Date: 01:04:57 10/01/2011
-- Author: Andrzej Paluch
--------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use work.utilPkg.all;
entity if_func_T_TE is
port(
-- clock
clk : in std_logic; -- clock
-- function settings
isTE : in std_logic;
-- local instruction inputs
pon : in std_logic; -- power on
ton : in std_logic; -- talk only
endOf : in std_logic; -- end of byte string
-- state inputs
ACDS : in std_logic; -- accept data state (AH)
APRS : in std_logic; -- affirmative poll response
LPAS : in std_logic; -- listener primary state (LE)
-- remote instruction inputs
ATN : in std_logic; -- attention
IFC : in std_logic; -- interface clear
SPE : in std_logic; -- serial poll enable
SPD : in std_logic; -- serial poll disable
MTA : in std_logic; -- my talk address
OTA : in std_logic; -- other talk address
MLA : in std_logic; -- my listen address
OSA : in std_logic; -- other secondary address
MSA : in std_logic; -- my secondary address
PCG : in std_logic; -- primary command group
-- remote instruction outputs
END_OF : out std_logic; -- end of data
RQS : out std_logic; -- data accepted
DAB : out std_logic; -- data byte
EOS : out std_logic; -- end of string
STB : out std_logic; -- status byte
-- local instruction outputs
tac : out std_logic; -- talker active
-- reported states
SPAS : out std_logic; -- serial poll active state
TPAS : out std_logic; -- transmitter active state
TADS : out std_logic; -- talker addressed state
TACS : out std_logic -- talker active state
);
end if_func_T_TE;
architecture Behavioral of if_func_T_TE is
-- states
type T_STATE_1 is (
-- talker idle state
ST_TIDS,
-- talker addressed state
ST_TADS,
-- talker active state
ST_TACS,
-- serial poll active state
ST_SPAS
);
type T_STATE_2 is (
-- serial poll idle state
ST_SPIS,
-- seriall poll mode state
ST_SPMS
);
type T_STATE_3 is (
-- talker primary idle state
ST_TPIS,
-- talker primary addressed state
ST_TPAS
);
-- current state
signal current_state_1 : T_STATE_1;
signal current_state_2 : T_STATE_2;
signal current_state_3 : T_STATE_3;
-- events
signal event1_1, event1_2, event1_3, event1_4, event1_5, event1_6 : boolean;
signal event2_1, event2_2, event2_3 : boolean;
signal event3_1, event3_2, event3_3 : boolean;
begin
-- state machine process - T_STATE_1
process(pon, clk) begin
if pon = '1' then
current_state_1 <= ST_TIDS;
elsif rising_edge(clk) then
case current_state_1 is
------------------
when ST_TIDS =>
if event1_6 then
-- no state change
elsif event1_1 then
current_state_1 <= ST_TADS;
end if;
------------------
when ST_TADS =>
if event1_6 then
current_state_1 <= ST_TIDS;
elsif event1_2 then
current_state_1 <= ST_SPAS;
elsif event1_3 then
current_state_1 <= ST_TIDS;
elsif event1_4 then
current_state_1 <= ST_TACS;
end if;
------------------
when ST_SPAS =>
if event1_6 then
current_state_1 <= ST_TIDS;
elsif event1_5 then
current_state_1 <= ST_TADS;
end if;
------------------
when ST_TACS =>
if event1_6 then
current_state_1 <= ST_TIDS;
elsif event1_5 then
current_state_1 <= ST_TADS;
end if;
------------------
when others =>
current_state_1 <= ST_TIDS;
end case;
end if;
end process;
-- state machine process - T_STATE_2
process(pon, clk) begin
if pon = '1' then
current_state_2 <= ST_SPIS;
elsif rising_edge(clk) then
case current_state_2 is
------------------
when ST_SPIS =>
if event2_3 then
-- no state change
elsif event2_1 then
current_state_2 <= ST_SPMS;
end if;
------------------
when ST_SPMS =>
if event2_3 then
current_state_2 <= ST_SPIS;
elsif event2_2 then
current_state_2 <= ST_SPIS;
end if;
------------------
when others =>
current_state_2 <= ST_SPIS;
end case;
end if;
end process;
-- state machine process - T_STATE_3
process(pon, clk) begin
if pon = '1' then
current_state_3 <= ST_TPIS;
elsif rising_edge(clk) then
case current_state_3 is
------------------
when ST_TPIS =>
if event3_3 then
-- no state change
elsif event3_1 then
current_state_3 <= ST_TPAS;
end if;
------------------
when ST_TPAS =>
if event3_3 then
current_state_3 <= ST_TPIS;
elsif event3_2 then
current_state_3 <= ST_TPIS;
end if;
------------------
when others =>
current_state_3 <= ST_TPIS;
end case;
end if;
end process;
-- events
event1_1 <= is_1(
-- TE
(isTE and
(ton or (MSA and ACDS and to_stdl(current_state_3=ST_TPAS)))) or
-- T
(not isTE and
(ton or (MTA and ACDS)))
);
event1_2 <= ATN='0' and current_state_2=ST_SPMS;
event1_3 <=
-- TE
(isTE='1' and ((OTA='1' and ACDS='1') or
(OSA='1' and current_state_3=ST_TPAS and ACDS='1') or
(MSA='1' and LPAS='1' and ACDS='1'))) or
-- T
(isTE='0' and ((OTA='1' and ACDS='1') or (MLA='1' and ACDS='1')));
event1_4 <= ATN='0' and current_state_2/=ST_SPMS;
event1_5 <= ATN='1';
event1_6 <= IFC='1';
event2_1 <= SPE='1' and ACDS='1';
event2_2 <= SPD='1' and ACDS='1';
event2_3 <= IFC='1';
event3_1 <= MTA='1' and ACDS='1';
event3_2 <= PCG='1' and MTA='0' and ACDS='1';
event3_3 <= IFC='1';
-- TADS generator
with current_state_1 select
TADS <=
'1' when ST_TADS,
'0' when others;
-- TACS generator
with current_state_1 select
TACS <=
'1' when ST_TACS,
'0' when others;
-- DAB generator
with current_state_1 select
DAB <=
'1' when ST_TACS,
'0' when others;
-- EOS is kind of DAB
with current_state_1 select
EOS <=
'1' when ST_TACS,
'0' when others;
-- STB generator
with current_state_1 select
STB <=
'1' when ST_SPAS,
'0' when others;
-- SPAS generator
with current_state_1 select
SPAS <=
'1' when ST_SPAS,
'0' when others;
-- TPAS generator
with current_state_3 select
TPAS <=
'1' when ST_TPAS,
'0' when others;
-- tac generator
with current_state_1 select
tac <=
'1' when ST_TACS,
'0' when others;
-- END_OF generator
with current_state_1 select
END_OF <=
endOf when ST_TACS,
endOf when ST_SPAS,
'0' when others;
-- RQS generator
RQS <= APRS when current_state_1=ST_SPAS else '0';
end Behavioral;
| gpl-3.0 | 177162ccd4f7d031f7c2d78ae94b662d | 0.587862 | 3.06405 | false | false | false | false |
autosub-team/autosub | src/tests/testTasksVHDL/testsubmissions/pwm/pwm_beh.vhdl | 2 | 646 | library IEEE;
use IEEE.std_logic_1164.all;
architecture behavior of pwm is
signal clk_cnt: natural := 0;
constant period :integer := 2500;
constant duty : integer := 1400;
begin
clk_count : process(CLK)
begin
if(rising_edge(CLK)) then
if(clk_cnt = period) then
clk_cnt <= 1;
else
clk_cnt <= clk_cnt + 1;
end if;
end if;
end process;
siggen: process(clk_cnt)
begin
if(clk_cnt = duty) then
O <= '0';
elsif(clk_cnt = period) then
O <= '1';
end if;
end process;
end behavior;
| gpl-2.0 | e17a135a59aaa41bc8cc57c52831d99f | 0.50774 | 3.734104 | false | false | false | false |
esar/hdmilight-v2 | fpga/resultDistributor.vhd | 1 | 5,300 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2014 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity resultDistributor is
PORT (
clk : in std_logic;
start : in std_logic;
driverReadyVect : in std_logic_vector(7 downto 0);
driverStartVect : out std_logic_vector(7 downto 0);
driverData : out std_logic_vector(23 downto 0);
outputMapAddr : out std_logic_vector(11 downto 0);
outputMapData : in std_logic_vector(15 downto 0);
areaResultAddr : out std_logic_vector(7 downto 0);
areaResultR : in std_logic_vector(7 downto 0);
areaResultG : in std_logic_vector(7 downto 0);
arearesultB : in std_logic_vector(7 downto 0);
colourCoefAddr : out std_logic_vector(8 downto 0);
colourCoefData : in std_logic_vector(63 downto 0);
gammaTableRAddr : out std_logic_vector(10 downto 0);
gammaTableRData : in std_logic_vector(7 downto 0);
gammaTableGAddr : out std_logic_vector(10 downto 0);
gammaTableGData : in std_logic_vector(7 downto 0);
gammaTableBAddr : out std_logic_vector(10 downto 0);
gammaTableBData : in std_logic_vector(7 downto 0)
);
end resultDistributor;
architecture Behavioral of resultDistributor is
signal laststart : std_logic;
signal count : std_logic_vector(11 downto 0);
signal lightIndex : std_logic_vector(8 downto 0);
signal driverIndex : std_logic_vector(2 downto 0);
signal firstLight : std_logic;
signal enabled : std_logic;
signal skip : std_logic;
signal startOne : std_logic;
signal startOne_1 : std_logic;
signal resultReady : std_logic;
signal driverReady : std_logic;
signal driverStart : std_logic;
signal colourCoefIndex : std_logic_vector(3 downto 0);
signal colourTransformStart : std_logic;
signal colourTransformDone : std_logic;
signal transformedR : std_logic_vector(7 downto 0);
signal transformedG : std_logic_vector(7 downto 0);
signal transformedB : std_logic_vector(7 downto 0);
begin
colourTransformer : entity work.colourTransformer port map (
clk, colourTransformStart, colourTransformDone,
colourCoefIndex, colourCoefAddr, colourCoefData,
areaResultR, areaResultG, areaResultB,
transformedR, transformedG, transformedB
);
lightIndex <= count(11 downto 3);
driverIndex <= count(2 downto 0);
driverReady <= driverReadyVect(to_integer(unsigned(driverIndex)));
driverStartVect(0) <= driverStart when driverIndex = "000" else '0';
driverStartVect(1) <= driverStart when driverIndex = "001" else '0';
driverStartVect(2) <= driverStart when driverIndex = "010" else '0';
driverStartVect(3) <= driverStart when driverIndex = "011" else '0';
driverStartVect(4) <= driverStart when driverIndex = "100" else '0';
driverStartVect(5) <= driverStart when driverIndex = "101" else '0';
driverStartVect(6) <= driverStart when driverIndex = "110" else '0';
driverStartVect(7) <= driverStart when driverIndex = "111" else '0';
process(clk)
begin
if(rising_edge(clk)) then
startOne <= '0';
if(start = '1' and laststart = '0') then
count <= (others => '0');
startOne <= '1';
elsif((skip = '1' or driverStart = '1') and count /= "111111111111") then
count <= std_logic_vector(unsigned(count) + 1);
startOne <= '1';
end if;
laststart <= start;
end if;
end process;
-- signal colour transformer start two clocks after startOne
-- to wait for output map RAM read, and then area result RAM read
process(clk)
begin
if(rising_edge(clk)) then
skip <= '0';
colourTransformStart <= '0';
startOne_1 <= startOne;
if(enabled = '1') then
colourTransformStart <= startOne_1;
else
skip <= startOne_1;
end if;
end if;
end process;
process(clk, startOne)
begin
if(startOne = '1') then
resultReady <= '0';
elsif(rising_edge(clk)) then
if(colourTransformDone = '1') then
resultReady <= '1';
end if;
end if;
end process;
firstLight <= '1' when lightIndex = "000000000" else '0';
driverStart <= (driverReady or firstLight) and resultReady;
outputMapAddr <= driverIndex & lightIndex;
areaResultAddr <= outputMapData(7 downto 0);
gammaTableRAddr <= outputMapData(10 downto 8) & transformedR;
gammaTableGAddr <= outputMapData(10 downto 8) & transformedG;
gammaTableBAddr <= outputMapData(10 downto 8) & transformedB;
colourCoefIndex <= outputMapData(14 downto 11);
enabled <= outputMapData(15);
driverData <= gammaTableGData & gammaTableRData & gammaTableBData;
end Behavioral;
| gpl-2.0 | cb79dc5168bda60ab613774b49b686f7 | 0.692453 | 3.602991 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib/if_func_SR.vhd | 1 | 3,140 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 01:04:57 10/01/2011
-- Design Name:
-- Module Name: if_func_SR - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity if_func_SR is
port(
-- device inputs
clk : in std_logic; -- clock
pon : in std_logic; -- power on
rsv : in std_logic; -- service request
-- state inputs
SPAS : in std_logic; -- serial poll active state (T or TE)
-- output instructions
SRQ : out std_logic; -- service request
-- reported states
APRS : out std_logic -- affirmative poll response state
);
end if_func_SR;
architecture Behavioral of if_func_SR is
-- states
type SR_STATE is (
-- negative poll response state
ST_NPRS,
-- service request state
ST_SRQS,
-- affirmative poll response state
ST_APRS
);
-- current state
signal current_state : SR_STATE;
-- predicates
signal pred1 : boolean;
signal pred2 : boolean;
begin
-- state machine process
process(pon, clk) begin
if pon = '1' then
current_state <= ST_NPRS;
elsif rising_edge(clk) then
case current_state is
------------------
when ST_NPRS =>
if pred1 then
current_state <= ST_SRQS;
end if;
------------------
when ST_SRQS =>
if pred2 then
current_state <= ST_NPRS;
elsif SPAS='1' then
current_state <= ST_APRS;
end if;
------------------
when ST_APRS =>
if pred2 then
current_state <= ST_NPRS;
end if;
------------------
when others =>
current_state <= ST_NPRS;
end case;
end if;
end process;
-- predicates
pred1 <= rsv='1' and SPAS='0';
pred2 <= rsv='0' and SPAS='0';
-- APRS generator
with current_state select
APRS <=
'1' when ST_APRS,
'0' when others;
-- SRQ generator
with current_state select
SRQ <=
'1' when ST_SRQS,
'0' when others;
end Behavioral;
| gpl-3.0 | 04d74cf8686a57477a894ba2ad3a770f | 0.595541 | 3.81068 | false | false | false | false |
freecores/gpib_controller | vhdl/test/RegsGpibFasade_communication_test.vhd | 1 | 10,174 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 16:22:23 02/04/2012
-- Design Name:
-- Module Name: RegsGpibFasade_test.vhd
-- Project Name: proto1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: RegsGpibFasade
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
use work.wrapperComponents.ALL;
ENTITY RegsGpibFasade_communication_test IS
END RegsGpibFasade_communication_test;
ARCHITECTURE behavior OF RegsGpibFasade_communication_test IS
component gpibCableEmulator is port (
-- interface signals
DIO_1 : in std_logic_vector (7 downto 0);
output_valid_1 : in std_logic;
DIO_2 : in std_logic_vector (7 downto 0);
output_valid_2 : in std_logic;
DIO : out std_logic_vector (7 downto 0);
-- attention
ATN_1 : in std_logic;
ATN_2 : in std_logic;
ATN : out std_logic;
-- data valid
DAV_1 : in std_logic;
DAV_2 : in std_logic;
DAV : out std_logic;
-- not ready for data
NRFD_1 : in std_logic;
NRFD_2 : in std_logic;
NRFD : out std_logic;
-- no data accepted
NDAC_1 : in std_logic;
NDAC_2 : in std_logic;
NDAC : out std_logic;
-- end or identify
EOI_1 : in std_logic;
EOI_2 : in std_logic;
EOI : out std_logic;
-- service request
SRQ_1 : in std_logic;
SRQ_2 : in std_logic;
SRQ : out std_logic;
-- interface clear
IFC_1 : in std_logic;
IFC_2 : in std_logic;
IFC : out std_logic;
-- remote enable
REN_1 : in std_logic;
REN_2 : in std_logic;
REN : out std_logic
);
end component;
--Inputs
signal reset : std_logic := '0';
signal clk : std_logic := '0';
signal DI : std_logic_vector(7 downto 0) := (others => '0');
signal ATN_in : std_logic := '0';
signal DAV_in : std_logic := '0';
signal NRFD_in : std_logic := '0';
signal NDAC_in : std_logic := '0';
signal EOI_in : std_logic := '0';
signal SRQ_in : std_logic := '0';
signal IFC_in : std_logic := '0';
signal REN_in : std_logic := '0';
signal data_in : std_logic_vector(15 downto 0) := (others => '0');
signal reg_addr : std_logic_vector(14 downto 0) := (others => '0');
signal strobe_read : std_logic := '0';
signal strobe_write : std_logic := '0';
--Outputs
signal DO : std_logic_vector(7 downto 0);
signal output_valid : std_logic;
signal ATN_out : std_logic;
signal DAV_out : std_logic;
signal NRFD_out : std_logic;
signal NDAC_out : std_logic;
signal EOI_out : std_logic;
signal SRQ_out : std_logic;
signal IFC_out : std_logic;
signal REN_out : std_logic;
signal data_out : std_logic_vector(15 downto 0);
signal interrupt_line : std_logic;
signal debug1 : std_logic;
--Inputs
signal data_in_1 : std_logic_vector(15 downto 0) := (others => '0');
signal reg_addr_1 : std_logic_vector(14 downto 0) := (others => '0');
signal strobe_read_1 : std_logic := '0';
signal strobe_write_1 : std_logic := '0';
--Outputs
signal DO_1 : std_logic_vector(7 downto 0);
signal output_valid_1 : std_logic;
signal ATN_out_1 : std_logic;
signal DAV_out_1 : std_logic;
signal NRFD_out_1 : std_logic;
signal NDAC_out_1 : std_logic;
signal EOI_out_1 : std_logic;
signal SRQ_out_1 : std_logic;
signal IFC_out_1 : std_logic;
signal REN_out_1 : std_logic;
signal data_out_1 : std_logic_vector(15 downto 0);
signal interrupt_line_1 : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RegsGpibFasade PORT MAP (
reset => reset,
clk => clk,
DI => DI,
DO => DO,
output_valid => output_valid,
ATN_in => ATN_in,
ATN_out => ATN_out,
DAV_in => DAV_in,
DAV_out => DAV_out,
NRFD_in => NRFD_in,
NRFD_out => NRFD_out,
NDAC_in => NDAC_in,
NDAC_out => NDAC_out,
EOI_in => EOI_in,
EOI_out => EOI_out,
SRQ_in => SRQ_in,
SRQ_out => SRQ_out,
IFC_in => IFC_in,
IFC_out => IFC_out,
REN_in => REN_in,
REN_out => REN_out,
data_in => data_in,
data_out => data_out,
reg_addr => reg_addr,
strobe_read => strobe_read,
strobe_write => strobe_write,
interrupt_line => interrupt_line,
debug1 => debug1
);
-- Instantiate the Unit Under Test (UUT)
uut_1: RegsGpibFasade PORT MAP (
reset => reset,
clk => clk,
DI => DI,
DO => DO_1,
output_valid => output_valid_1,
ATN_in => ATN_in,
ATN_out => ATN_out_1,
DAV_in => DAV_in,
DAV_out => DAV_out_1,
NRFD_in => NRFD_in,
NRFD_out => NRFD_out_1,
NDAC_in => NDAC_in,
NDAC_out => NDAC_out_1,
EOI_in => EOI_in,
EOI_out => EOI_out_1,
SRQ_in => SRQ_in,
SRQ_out => SRQ_out_1,
IFC_in => IFC_in,
IFC_out => IFC_out_1,
REN_in => REN_in,
REN_out => REN_out_1,
data_in => data_in_1,
data_out => data_out_1,
reg_addr => reg_addr_1,
strobe_read => strobe_read_1,
strobe_write => strobe_write_1,
interrupt_line => interrupt_line_1,
debug1 => open
);
gce: gpibCableEmulator port map (
-- interface signals
DIO_1 => DO,
output_valid_1 => output_valid,
DIO_2 => DO_1,
output_valid_2 => output_valid_1,
DIO => DI,
-- attention
ATN_1 => ATN_out,
ATN_2 => ATN_out_1,
ATN => ATN_in,
-- data valid
DAV_1 => DAV_out,
DAV_2 => DAV_out_1,
DAV => DAV_in,
-- not ready for data
NRFD_1 => NRFD_out,
NRFD_2 => NRFD_out_1,
NRFD => NRFD_in,
-- no data accepted
NDAC_1 => NDAC_out,
NDAC_2 => NDAC_out_1,
NDAC => NDAC_in,
-- end or identify
EOI_1 => EOI_out,
EOI_2 => EOI_out_1,
EOI => EOI_in,
-- service request
SRQ_1 => SRQ_out,
SRQ_2 => SRQ_out_1,
SRQ => SRQ_in,
-- interface clear
IFC_1 => IFC_out,
IFC_2 => IFC_out_1,
IFC => IFC_in,
-- remote enable
REN_1 => REN_out,
REN_2 => REN_out_1,
REN => REN_in
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process begin
-- hold reset state for 10 clock cycles
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*10;
-- set address of GPIB1
reg_addr_1 <= "000000000000001";
data_in_1 <= X"0002";
wait for clk_period*2;
strobe_write_1 <= '1';
wait for clk_period*2;
strobe_write_1 <= '0';
wait for clk_period*2;
-- set rsc
reg_addr <= "000000000000111";
data_in <= X"0040";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
wait for clk_period*20;
-- set sic
reg_addr <= "000000000000111";
data_in <= X"00c0";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
wait for clk_period*20;
-- reset sic
reg_addr <= "000000000000111";
data_in <= X"0040";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
wait until IFC_in = '0';
-- address GPIB1 to listen
reg_addr <= "000000000001101";
data_in <= X"0022";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
wait for clk_period*5;
-- address GPIB0 to talk
reg_addr <= "000000000001101";
data_in <= X"0041";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
wait for clk_period*5;
-- go to standby
reg_addr <= "000000000000111";
data_in <= X"0240";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
wait until ATN_in = '0';
reg_addr <= "000000000000111";
data_in <= X"0040";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
wait for clk_period*5;
-- set eof
reg_addr <= "000000000001010";
data_in <= X"0006";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
wait for clk_period*5;
-- writes data to GPIB1
reg_addr <= "000000000001101";
data_in <= X"0007";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
wait for clk_period*15;
-- take control
reg_addr <= "000000000000111";
data_in <= X"0840";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
wait for clk_period*150;
-- reset buffer
reg_addr <= "000000000001010";
data_in <= X"000a";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
wait for clk_period*10;
-- address GPIB0 to listen
reg_addr <= "000000000001101";
data_in <= X"0021";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
wait for clk_period*5;
wait;
end process;
END;
| gpl-3.0 | a2d9a078db6e5a7f65d8a7d4e97506b3 | 0.61205 | 2.908519 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/source/vhdl/compute_distance.vhd | 1 | 5,253 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: compute_distance_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
use ieee.math_real.all;
use work.lloyds_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity compute_distance_top is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
point_1 : in data_type;
point_2 : in data_type;
distance : out coord_type_ext;
point_1_out : out data_type;
point_2_out : out data_type;
rdy : out std_logic
);
end compute_distance_top;
architecture Behavioral of compute_distance_top is
constant LAT_DOT_PRODUCT : integer := MUL_CORE_LATENCY+2*integer(ceil(log2(real(D))));
constant LAT_SUB : integer := 2;
constant LATENCY : integer := LAT_DOT_PRODUCT+LAT_SUB;
type data_delay_type is array(0 to LATENCY-1) of data_type;
component addorsub
generic (
USE_DSP : boolean := true;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
component dot_product
generic (
SCALE_MUL_RESULT : integer := 0
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
point_1 : in data_type;
point_2 : in data_type;
result : out coord_type_ext;
rdy : out std_logic
);
end component;
signal tmp_diff : data_type;
signal tmp_sub_rdy : std_logic;
signal tmp_dot_product_rdy : std_logic;
signal tmp_dot_product_result : coord_type_ext;
signal data_delay_1 : data_delay_type;
signal data_delay_2 : data_delay_type;
begin
G1: for I in 0 to D-1 generate
G_FIRST: if I = 0 generate
addorsub_inst : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => COORD_BITWIDTH,
B_BITWIDTH => COORD_BITWIDTH,
RES_BITWIDTH => COORD_BITWIDTH
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
sub => '1',
a => point_1(I),
b => point_2(I),
res => tmp_diff(I),
rdy => tmp_sub_rdy
);
end generate G_FIRST;
G_OTHER: if I > 0 generate
addorsub_inst : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => COORD_BITWIDTH,
B_BITWIDTH => COORD_BITWIDTH,
RES_BITWIDTH => COORD_BITWIDTH
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
sub => '1',
a => point_1(I),
b => point_2(I),
res => tmp_diff(I),
rdy => open
);
end generate G_OTHER;
end generate G1;
dot_product_inst : dot_product
generic map (
SCALE_MUL_RESULT => MUL_FRACTIONAL_BITS
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_sub_rdy,
point_1 => tmp_diff,
point_2 => tmp_diff,
result => tmp_dot_product_result,
rdy => tmp_dot_product_rdy
);
-- feed point_2 from input of this unit to output
data_delay_proc : process(clk)
begin
if rising_edge(clk) then
data_delay_1(0) <= point_1;
data_delay_1(1 to LATENCY-1) <= data_delay_1(0 to LATENCY-2);
data_delay_2(0) <= point_2;
data_delay_2(1 to LATENCY-1) <= data_delay_2(0 to LATENCY-2);
end if;
end process data_delay_proc;
rdy <= tmp_dot_product_rdy;
distance <= tmp_dot_product_result;
point_1_out <= data_delay_1(LATENCY-1);
point_2_out <= data_delay_2(LATENCY-1);
end Behavioral;
| bsd-3-clause | 50ccf3857e00887d75c6b2e8676fb097 | 0.474776 | 4.253441 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-2/instr_reg.vhd | 1 | 864 | library IEEE;
use ieee.std_logic_1164.all;
entity instr_reg is
port(
input : in std_logic_vector(31 downto 0);
IRw : in std_logic;
instr31_26, instr5_0 : out std_logic_vector(5 downto 0);
instr25_21, instr20_16, instr15_11 : out std_logic_vector(4 downto 0);
instr15_0 : out std_logic_vector(15 downto 0);
instr25_0 : out std_logic_vector(25 downto 0)
);
end instr_reg;
architecture behav of instr_reg is
signal Rr1, Rr2, Wr1, Wr2, Opc, FC : std_logic_vector(5 downto 0);
signal Se16 : std_logic_vector(15 downto 0);
signal Se26 : std_logic_vector(25 downto 0);
begin
instr31_26 <= input(31 downto 26);
instr25_21 <= input(25 downto 21);
instr25_0 <= input(25 downto 0);
instr20_16 <= input(20 downto 16);
instr15_11 <= input(15 downto 11);
instr15_0 <= input(15 downto 0);
instr5_0 <= input(5 downto 0);
end behav;
| gpl-3.0 | 868b54de4a322da073a5a8e2cbf3e3e2 | 0.672454 | 2.62614 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/system_microblaze_0_wrapper.vhd | 1 | 88,130 | -------------------------------------------------------------------------------
-- system_microblaze_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library microblaze_v8_40_a;
use microblaze_v8_40_a.all;
entity system_microblaze_0_wrapper is
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to 3);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to 31);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to 31);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to 3);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to 31);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to 31);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector(0 downto 0);
M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector(0 downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector(0 downto 0);
M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector(0 downto 0);
M_AXI_IP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector(0 downto 0);
M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector(0 downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector(0 downto 0);
M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector(0 downto 0);
M_AXI_DP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector(0 downto 0);
M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_IC_BID : in std_logic_vector(0 downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_ARID : out std_logic_vector(0 downto 0);
M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_RID : in std_logic_vector(0 downto 0);
M_AXI_IC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_AWID : out std_logic_vector(0 downto 0);
M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_DC_BID : in std_logic_vector(0 downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_ARID : out std_logic_vector(0 downto 0);
M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_RID : in std_logic_vector(0 downto 0);
M_AXI_DC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector(0 downto 0);
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to 31);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to 31);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to 31);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to 31);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to 31);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to 31);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to 31);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to 31);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to 31);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to 31);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to 31);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to 31);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to 31);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to 31);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to 31);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to 31);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to 31);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to 31);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to 31);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to 31);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to 31);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to 31);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to 31);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to 31);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to 31);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to 31);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to 31);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to 31);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to 31);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to 31);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to 31);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to 31);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(31 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(31 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(31 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(31 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(31 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(31 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(31 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(31 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(31 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(31 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(31 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(31 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(31 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(31 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(31 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(31 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(31 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(31 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(31 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(31 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(31 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(31 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(31 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(31 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(31 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(31 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(31 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(31 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(31 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(31 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(31 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(31 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_microblaze_0_wrapper : entity is "microblaze_v8_40_a";
end system_microblaze_0_wrapper;
architecture STRUCTURE of system_microblaze_0_wrapper is
component microblaze is
generic (
C_SCO : integer;
C_FREQ : integer;
C_DATA_SIZE : integer;
C_DYNAMIC_BUS_SIZING : integer;
C_FAMILY : string;
C_INSTANCE : string;
C_AVOID_PRIMITIVES : integer;
C_FAULT_TOLERANT : integer;
C_ECC_USE_CE_EXCEPTION : integer;
C_LOCKSTEP_SLAVE : integer;
C_ENDIANNESS : integer;
C_AREA_OPTIMIZED : integer;
C_OPTIMIZATION : integer;
C_INTERCONNECT : integer;
C_STREAM_INTERCONNECT : integer;
C_DPLB_DWIDTH : integer;
C_DPLB_NATIVE_DWIDTH : integer;
C_DPLB_BURST_EN : integer;
C_DPLB_P2P : integer;
C_IPLB_DWIDTH : integer;
C_IPLB_NATIVE_DWIDTH : integer;
C_IPLB_BURST_EN : integer;
C_IPLB_P2P : integer;
C_M_AXI_DP_THREAD_ID_WIDTH : integer;
C_M_AXI_DP_DATA_WIDTH : integer;
C_M_AXI_DP_ADDR_WIDTH : integer;
C_M_AXI_DP_EXCLUSIVE_ACCESS : integer;
C_M_AXI_IP_THREAD_ID_WIDTH : integer;
C_M_AXI_IP_DATA_WIDTH : integer;
C_M_AXI_IP_ADDR_WIDTH : integer;
C_D_AXI : integer;
C_D_PLB : integer;
C_D_LMB : integer;
C_I_AXI : integer;
C_I_PLB : integer;
C_I_LMB : integer;
C_USE_MSR_INSTR : integer;
C_USE_PCMP_INSTR : integer;
C_USE_BARREL : integer;
C_USE_DIV : integer;
C_USE_HW_MUL : integer;
C_USE_FPU : integer;
C_USE_REORDER_INSTR : integer;
C_UNALIGNED_EXCEPTIONS : integer;
C_ILL_OPCODE_EXCEPTION : integer;
C_M_AXI_I_BUS_EXCEPTION : integer;
C_M_AXI_D_BUS_EXCEPTION : integer;
C_IPLB_BUS_EXCEPTION : integer;
C_DPLB_BUS_EXCEPTION : integer;
C_DIV_ZERO_EXCEPTION : integer;
C_FPU_EXCEPTION : integer;
C_FSL_EXCEPTION : integer;
C_USE_STACK_PROTECTION : integer;
C_PVR : integer;
C_PVR_USER1 : std_logic_vector(0 to 7);
C_PVR_USER2 : std_logic_vector(0 to 31);
C_DEBUG_ENABLED : integer;
C_NUMBER_OF_PC_BRK : integer;
C_NUMBER_OF_RD_ADDR_BRK : integer;
C_NUMBER_OF_WR_ADDR_BRK : integer;
C_INTERRUPT_IS_EDGE : integer;
C_EDGE_IS_POSITIVE : integer;
C_RESET_MSR : std_logic_vector;
C_OPCODE_0x0_ILLEGAL : integer;
C_FSL_LINKS : integer;
C_FSL_DATA_SIZE : integer;
C_USE_EXTENDED_FSL_INSTR : integer;
C_M0_AXIS_DATA_WIDTH : integer;
C_S0_AXIS_DATA_WIDTH : integer;
C_M1_AXIS_DATA_WIDTH : integer;
C_S1_AXIS_DATA_WIDTH : integer;
C_M2_AXIS_DATA_WIDTH : integer;
C_S2_AXIS_DATA_WIDTH : integer;
C_M3_AXIS_DATA_WIDTH : integer;
C_S3_AXIS_DATA_WIDTH : integer;
C_M4_AXIS_DATA_WIDTH : integer;
C_S4_AXIS_DATA_WIDTH : integer;
C_M5_AXIS_DATA_WIDTH : integer;
C_S5_AXIS_DATA_WIDTH : integer;
C_M6_AXIS_DATA_WIDTH : integer;
C_S6_AXIS_DATA_WIDTH : integer;
C_M7_AXIS_DATA_WIDTH : integer;
C_S7_AXIS_DATA_WIDTH : integer;
C_M8_AXIS_DATA_WIDTH : integer;
C_S8_AXIS_DATA_WIDTH : integer;
C_M9_AXIS_DATA_WIDTH : integer;
C_S9_AXIS_DATA_WIDTH : integer;
C_M10_AXIS_DATA_WIDTH : integer;
C_S10_AXIS_DATA_WIDTH : integer;
C_M11_AXIS_DATA_WIDTH : integer;
C_S11_AXIS_DATA_WIDTH : integer;
C_M12_AXIS_DATA_WIDTH : integer;
C_S12_AXIS_DATA_WIDTH : integer;
C_M13_AXIS_DATA_WIDTH : integer;
C_S13_AXIS_DATA_WIDTH : integer;
C_M14_AXIS_DATA_WIDTH : integer;
C_S14_AXIS_DATA_WIDTH : integer;
C_M15_AXIS_DATA_WIDTH : integer;
C_S15_AXIS_DATA_WIDTH : integer;
C_ICACHE_BASEADDR : std_logic_vector;
C_ICACHE_HIGHADDR : std_logic_vector;
C_USE_ICACHE : integer;
C_ALLOW_ICACHE_WR : integer;
C_ADDR_TAG_BITS : integer;
C_CACHE_BYTE_SIZE : integer;
C_ICACHE_USE_FSL : integer;
C_ICACHE_LINE_LEN : integer;
C_ICACHE_ALWAYS_USED : integer;
C_ICACHE_INTERFACE : integer;
C_ICACHE_VICTIMS : integer;
C_ICACHE_STREAMS : integer;
C_ICACHE_FORCE_TAG_LUTRAM : integer;
C_ICACHE_DATA_WIDTH : integer;
C_M_AXI_IC_THREAD_ID_WIDTH : integer;
C_M_AXI_IC_DATA_WIDTH : integer;
C_M_AXI_IC_ADDR_WIDTH : integer;
C_M_AXI_IC_USER_VALUE : integer;
C_M_AXI_IC_AWUSER_WIDTH : integer;
C_M_AXI_IC_ARUSER_WIDTH : integer;
C_M_AXI_IC_WUSER_WIDTH : integer;
C_M_AXI_IC_RUSER_WIDTH : integer;
C_M_AXI_IC_BUSER_WIDTH : integer;
C_DCACHE_BASEADDR : std_logic_vector;
C_DCACHE_HIGHADDR : std_logic_vector;
C_USE_DCACHE : integer;
C_ALLOW_DCACHE_WR : integer;
C_DCACHE_ADDR_TAG : integer;
C_DCACHE_BYTE_SIZE : integer;
C_DCACHE_USE_FSL : integer;
C_DCACHE_LINE_LEN : integer;
C_DCACHE_ALWAYS_USED : integer;
C_DCACHE_INTERFACE : integer;
C_DCACHE_USE_WRITEBACK : integer;
C_DCACHE_VICTIMS : integer;
C_DCACHE_FORCE_TAG_LUTRAM : integer;
C_DCACHE_DATA_WIDTH : integer;
C_M_AXI_DC_THREAD_ID_WIDTH : integer;
C_M_AXI_DC_DATA_WIDTH : integer;
C_M_AXI_DC_ADDR_WIDTH : integer;
C_M_AXI_DC_EXCLUSIVE_ACCESS : integer;
C_M_AXI_DC_USER_VALUE : integer;
C_M_AXI_DC_AWUSER_WIDTH : integer;
C_M_AXI_DC_ARUSER_WIDTH : integer;
C_M_AXI_DC_WUSER_WIDTH : integer;
C_M_AXI_DC_RUSER_WIDTH : integer;
C_M_AXI_DC_BUSER_WIDTH : integer;
C_USE_MMU : integer;
C_MMU_DTLB_SIZE : integer;
C_MMU_ITLB_SIZE : integer;
C_MMU_TLB_ACCESS : integer;
C_MMU_ZONES : integer;
C_MMU_PRIVILEGED_INSTR : integer;
C_USE_INTERRUPT : integer;
C_USE_EXT_BRK : integer;
C_USE_EXT_NM_BRK : integer;
C_USE_BRANCH_TARGET_CACHE : integer;
C_BRANCH_TARGET_CACHE_SIZE : integer;
C_PC_WIDTH : integer
);
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to (C_IPLB_DWIDTH-1)/8);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to (C_DPLB_DWIDTH-1)/8);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_AWADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(((C_M_AXI_IP_DATA_WIDTH/8)-1) downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_ARADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_RDATA : in std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_AWADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(((C_M_AXI_DP_DATA_WIDTH/8)-1) downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_ARADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_RDATA : in std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_AWADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector((C_M_AXI_IC_AWUSER_WIDTH-1) downto 0);
M_AXI_IC_WDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(((C_M_AXI_IC_DATA_WIDTH/8)-1) downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector((C_M_AXI_IC_WUSER_WIDTH-1) downto 0);
M_AXI_IC_BID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector((C_M_AXI_IC_BUSER_WIDTH-1) downto 0);
M_AXI_IC_ARID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_ARADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector((C_M_AXI_IC_ARUSER_WIDTH-1) downto 0);
M_AXI_IC_RID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_RDATA : in std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector((C_M_AXI_IC_RUSER_WIDTH-1) downto 0);
M_AXI_DC_AWID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_AWADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector((C_M_AXI_DC_AWUSER_WIDTH-1) downto 0);
M_AXI_DC_WDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(((C_M_AXI_DC_DATA_WIDTH/8)-1) downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector((C_M_AXI_DC_WUSER_WIDTH-1) downto 0);
M_AXI_DC_BID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector((C_M_AXI_DC_BUSER_WIDTH-1) downto 0);
M_AXI_DC_ARID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_ARADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector((C_M_AXI_DC_ARUSER_WIDTH-1) downto 0);
M_AXI_DC_RID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_RDATA : in std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector((C_M_AXI_DC_RUSER_WIDTH-1) downto 0);
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(C_M0_AXIS_DATA_WIDTH-1 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(C_S0_AXIS_DATA_WIDTH-1 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(C_M1_AXIS_DATA_WIDTH-1 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(C_S1_AXIS_DATA_WIDTH-1 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(C_M2_AXIS_DATA_WIDTH-1 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(C_S2_AXIS_DATA_WIDTH-1 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(C_M3_AXIS_DATA_WIDTH-1 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(C_S3_AXIS_DATA_WIDTH-1 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(C_M4_AXIS_DATA_WIDTH-1 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(C_S4_AXIS_DATA_WIDTH-1 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(C_M5_AXIS_DATA_WIDTH-1 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(C_S5_AXIS_DATA_WIDTH-1 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(C_M6_AXIS_DATA_WIDTH-1 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(C_S6_AXIS_DATA_WIDTH-1 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(C_M7_AXIS_DATA_WIDTH-1 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(C_S7_AXIS_DATA_WIDTH-1 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(C_M8_AXIS_DATA_WIDTH-1 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(C_S8_AXIS_DATA_WIDTH-1 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(C_M9_AXIS_DATA_WIDTH-1 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(C_S9_AXIS_DATA_WIDTH-1 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(C_M10_AXIS_DATA_WIDTH-1 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(C_S10_AXIS_DATA_WIDTH-1 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(C_M11_AXIS_DATA_WIDTH-1 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(C_S11_AXIS_DATA_WIDTH-1 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(C_M12_AXIS_DATA_WIDTH-1 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(C_S12_AXIS_DATA_WIDTH-1 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(C_M13_AXIS_DATA_WIDTH-1 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(C_S13_AXIS_DATA_WIDTH-1 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(C_M14_AXIS_DATA_WIDTH-1 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(C_S14_AXIS_DATA_WIDTH-1 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(C_M15_AXIS_DATA_WIDTH-1 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(C_S15_AXIS_DATA_WIDTH-1 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
end component;
begin
microblaze_0 : microblaze
generic map (
C_SCO => 0,
C_FREQ => 50000000,
C_DATA_SIZE => 32,
C_DYNAMIC_BUS_SIZING => 1,
C_FAMILY => "spartan6",
C_INSTANCE => "microblaze_0",
C_AVOID_PRIMITIVES => 0,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_ENDIANNESS => 1,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 2,
C_STREAM_INTERCONNECT => 0,
C_DPLB_DWIDTH => 32,
C_DPLB_NATIVE_DWIDTH => 32,
C_DPLB_BURST_EN => 0,
C_DPLB_P2P => 0,
C_IPLB_DWIDTH => 32,
C_IPLB_NATIVE_DWIDTH => 32,
C_IPLB_BURST_EN => 0,
C_IPLB_P2P => 0,
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_D_AXI => 1,
C_D_PLB => 0,
C_D_LMB => 1,
C_I_AXI => 0,
C_I_PLB => 0,
C_I_LMB => 1,
C_USE_MSR_INSTR => 1,
C_USE_PCMP_INSTR => 1,
C_USE_BARREL => 1,
C_USE_DIV => 0,
C_USE_HW_MUL => 1,
C_USE_FPU => 0,
C_USE_REORDER_INSTR => 1,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_IPLB_BUS_EXCEPTION => 0,
C_DPLB_BUS_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DEBUG_ENABLED => 1,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_FSL_LINKS => 1,
C_FSL_DATA_SIZE => 32,
C_USE_EXTENDED_FSL_INSTR => 0,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"00000000",
C_ICACHE_HIGHADDR => X"3FFFFFFF",
C_USE_ICACHE => 0,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 0,
C_CACHE_BYTE_SIZE => 8192,
C_ICACHE_USE_FSL => 0,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 0,
C_ICACHE_INTERFACE => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_STREAMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 2#11111#,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"00000000",
C_DCACHE_HIGHADDR => X"3FFFFFFF",
C_USE_DCACHE => 0,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 0,
C_DCACHE_BYTE_SIZE => 8192,
C_DCACHE_USE_FSL => 0,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 0,
C_DCACHE_INTERFACE => 0,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 2#11111#,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_INTERRUPT => 0,
C_USE_EXT_BRK => 1,
C_USE_EXT_NM_BRK => 1,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0,
C_PC_WIDTH => 32
)
port map (
CLK => CLK,
RESET => RESET,
MB_RESET => MB_RESET,
INTERRUPT => INTERRUPT,
INTERRUPT_ADDRESS => INTERRUPT_ADDRESS,
INTERRUPT_ACK => INTERRUPT_ACK,
EXT_BRK => EXT_BRK,
EXT_NM_BRK => EXT_NM_BRK,
DBG_STOP => DBG_STOP,
MB_Halted => MB_Halted,
MB_Error => MB_Error,
WAKEUP => WAKEUP,
SLEEP => SLEEP,
DBG_WAKEUP => DBG_WAKEUP,
LOCKSTEP_MASTER_OUT => LOCKSTEP_MASTER_OUT,
LOCKSTEP_SLAVE_IN => LOCKSTEP_SLAVE_IN,
LOCKSTEP_OUT => LOCKSTEP_OUT,
INSTR => INSTR,
IREADY => IREADY,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
INSTR_ADDR => INSTR_ADDR,
IFETCH => IFETCH,
I_AS => I_AS,
IPLB_M_ABort => IPLB_M_ABort,
IPLB_M_ABus => IPLB_M_ABus,
IPLB_M_UABus => IPLB_M_UABus,
IPLB_M_BE => IPLB_M_BE,
IPLB_M_busLock => IPLB_M_busLock,
IPLB_M_lockErr => IPLB_M_lockErr,
IPLB_M_MSize => IPLB_M_MSize,
IPLB_M_priority => IPLB_M_priority,
IPLB_M_rdBurst => IPLB_M_rdBurst,
IPLB_M_request => IPLB_M_request,
IPLB_M_RNW => IPLB_M_RNW,
IPLB_M_size => IPLB_M_size,
IPLB_M_TAttribute => IPLB_M_TAttribute,
IPLB_M_type => IPLB_M_type,
IPLB_M_wrBurst => IPLB_M_wrBurst,
IPLB_M_wrDBus => IPLB_M_wrDBus,
IPLB_MBusy => IPLB_MBusy,
IPLB_MRdErr => IPLB_MRdErr,
IPLB_MWrErr => IPLB_MWrErr,
IPLB_MIRQ => IPLB_MIRQ,
IPLB_MWrBTerm => IPLB_MWrBTerm,
IPLB_MWrDAck => IPLB_MWrDAck,
IPLB_MAddrAck => IPLB_MAddrAck,
IPLB_MRdBTerm => IPLB_MRdBTerm,
IPLB_MRdDAck => IPLB_MRdDAck,
IPLB_MRdDBus => IPLB_MRdDBus,
IPLB_MRdWdAddr => IPLB_MRdWdAddr,
IPLB_MRearbitrate => IPLB_MRearbitrate,
IPLB_MSSize => IPLB_MSSize,
IPLB_MTimeout => IPLB_MTimeout,
DATA_READ => DATA_READ,
DREADY => DREADY,
DWAIT => DWAIT,
DCE => DCE,
DUE => DUE,
DATA_WRITE => DATA_WRITE,
DATA_ADDR => DATA_ADDR,
D_AS => D_AS,
READ_STROBE => READ_STROBE,
WRITE_STROBE => WRITE_STROBE,
BYTE_ENABLE => BYTE_ENABLE,
DPLB_M_ABort => DPLB_M_ABort,
DPLB_M_ABus => DPLB_M_ABus,
DPLB_M_UABus => DPLB_M_UABus,
DPLB_M_BE => DPLB_M_BE,
DPLB_M_busLock => DPLB_M_busLock,
DPLB_M_lockErr => DPLB_M_lockErr,
DPLB_M_MSize => DPLB_M_MSize,
DPLB_M_priority => DPLB_M_priority,
DPLB_M_rdBurst => DPLB_M_rdBurst,
DPLB_M_request => DPLB_M_request,
DPLB_M_RNW => DPLB_M_RNW,
DPLB_M_size => DPLB_M_size,
DPLB_M_TAttribute => DPLB_M_TAttribute,
DPLB_M_type => DPLB_M_type,
DPLB_M_wrBurst => DPLB_M_wrBurst,
DPLB_M_wrDBus => DPLB_M_wrDBus,
DPLB_MBusy => DPLB_MBusy,
DPLB_MRdErr => DPLB_MRdErr,
DPLB_MWrErr => DPLB_MWrErr,
DPLB_MIRQ => DPLB_MIRQ,
DPLB_MWrBTerm => DPLB_MWrBTerm,
DPLB_MWrDAck => DPLB_MWrDAck,
DPLB_MAddrAck => DPLB_MAddrAck,
DPLB_MRdBTerm => DPLB_MRdBTerm,
DPLB_MRdDAck => DPLB_MRdDAck,
DPLB_MRdDBus => DPLB_MRdDBus,
DPLB_MRdWdAddr => DPLB_MRdWdAddr,
DPLB_MRearbitrate => DPLB_MRearbitrate,
DPLB_MSSize => DPLB_MSSize,
DPLB_MTimeout => DPLB_MTimeout,
M_AXI_IP_AWID => M_AXI_IP_AWID,
M_AXI_IP_AWADDR => M_AXI_IP_AWADDR,
M_AXI_IP_AWLEN => M_AXI_IP_AWLEN,
M_AXI_IP_AWSIZE => M_AXI_IP_AWSIZE,
M_AXI_IP_AWBURST => M_AXI_IP_AWBURST,
M_AXI_IP_AWLOCK => M_AXI_IP_AWLOCK,
M_AXI_IP_AWCACHE => M_AXI_IP_AWCACHE,
M_AXI_IP_AWPROT => M_AXI_IP_AWPROT,
M_AXI_IP_AWQOS => M_AXI_IP_AWQOS,
M_AXI_IP_AWVALID => M_AXI_IP_AWVALID,
M_AXI_IP_AWREADY => M_AXI_IP_AWREADY,
M_AXI_IP_WDATA => M_AXI_IP_WDATA,
M_AXI_IP_WSTRB => M_AXI_IP_WSTRB,
M_AXI_IP_WLAST => M_AXI_IP_WLAST,
M_AXI_IP_WVALID => M_AXI_IP_WVALID,
M_AXI_IP_WREADY => M_AXI_IP_WREADY,
M_AXI_IP_BID => M_AXI_IP_BID,
M_AXI_IP_BRESP => M_AXI_IP_BRESP,
M_AXI_IP_BVALID => M_AXI_IP_BVALID,
M_AXI_IP_BREADY => M_AXI_IP_BREADY,
M_AXI_IP_ARID => M_AXI_IP_ARID,
M_AXI_IP_ARADDR => M_AXI_IP_ARADDR,
M_AXI_IP_ARLEN => M_AXI_IP_ARLEN,
M_AXI_IP_ARSIZE => M_AXI_IP_ARSIZE,
M_AXI_IP_ARBURST => M_AXI_IP_ARBURST,
M_AXI_IP_ARLOCK => M_AXI_IP_ARLOCK,
M_AXI_IP_ARCACHE => M_AXI_IP_ARCACHE,
M_AXI_IP_ARPROT => M_AXI_IP_ARPROT,
M_AXI_IP_ARQOS => M_AXI_IP_ARQOS,
M_AXI_IP_ARVALID => M_AXI_IP_ARVALID,
M_AXI_IP_ARREADY => M_AXI_IP_ARREADY,
M_AXI_IP_RID => M_AXI_IP_RID,
M_AXI_IP_RDATA => M_AXI_IP_RDATA,
M_AXI_IP_RRESP => M_AXI_IP_RRESP,
M_AXI_IP_RLAST => M_AXI_IP_RLAST,
M_AXI_IP_RVALID => M_AXI_IP_RVALID,
M_AXI_IP_RREADY => M_AXI_IP_RREADY,
M_AXI_DP_AWID => M_AXI_DP_AWID,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWLEN => M_AXI_DP_AWLEN,
M_AXI_DP_AWSIZE => M_AXI_DP_AWSIZE,
M_AXI_DP_AWBURST => M_AXI_DP_AWBURST,
M_AXI_DP_AWLOCK => M_AXI_DP_AWLOCK,
M_AXI_DP_AWCACHE => M_AXI_DP_AWCACHE,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWQOS => M_AXI_DP_AWQOS,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WLAST => M_AXI_DP_WLAST,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => M_AXI_DP_BID,
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARID => M_AXI_DP_ARID,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARLEN => M_AXI_DP_ARLEN,
M_AXI_DP_ARSIZE => M_AXI_DP_ARSIZE,
M_AXI_DP_ARBURST => M_AXI_DP_ARBURST,
M_AXI_DP_ARLOCK => M_AXI_DP_ARLOCK,
M_AXI_DP_ARCACHE => M_AXI_DP_ARCACHE,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARQOS => M_AXI_DP_ARQOS,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => M_AXI_DP_RID,
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => M_AXI_DP_RLAST,
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_AWUSER => M_AXI_IC_AWUSER,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_WUSER => M_AXI_IC_WUSER,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => M_AXI_IC_BUSER,
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_ARUSER => M_AXI_IC_ARUSER,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => M_AXI_IC_RUSER,
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_AWUSER => M_AXI_DC_AWUSER,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_WUSER => M_AXI_DC_WUSER,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => M_AXI_DC_BUSER,
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_ARUSER => M_AXI_DC_ARUSER,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => M_AXI_DC_RUSER,
DBG_CLK => DBG_CLK,
DBG_TDI => DBG_TDI,
DBG_TDO => DBG_TDO,
DBG_REG_EN => DBG_REG_EN,
DBG_SHIFT => DBG_SHIFT,
DBG_CAPTURE => DBG_CAPTURE,
DBG_UPDATE => DBG_UPDATE,
DEBUG_RST => DEBUG_RST,
Trace_Instruction => Trace_Instruction,
Trace_Valid_Instr => Trace_Valid_Instr,
Trace_PC => Trace_PC,
Trace_Reg_Write => Trace_Reg_Write,
Trace_Reg_Addr => Trace_Reg_Addr,
Trace_MSR_Reg => Trace_MSR_Reg,
Trace_PID_Reg => Trace_PID_Reg,
Trace_New_Reg_Value => Trace_New_Reg_Value,
Trace_Exception_Taken => Trace_Exception_Taken,
Trace_Exception_Kind => Trace_Exception_Kind,
Trace_Jump_Taken => Trace_Jump_Taken,
Trace_Delay_Slot => Trace_Delay_Slot,
Trace_Data_Address => Trace_Data_Address,
Trace_Data_Access => Trace_Data_Access,
Trace_Data_Read => Trace_Data_Read,
Trace_Data_Write => Trace_Data_Write,
Trace_Data_Write_Value => Trace_Data_Write_Value,
Trace_Data_Byte_Enable => Trace_Data_Byte_Enable,
Trace_DCache_Req => Trace_DCache_Req,
Trace_DCache_Hit => Trace_DCache_Hit,
Trace_DCache_Rdy => Trace_DCache_Rdy,
Trace_DCache_Read => Trace_DCache_Read,
Trace_ICache_Req => Trace_ICache_Req,
Trace_ICache_Hit => Trace_ICache_Hit,
Trace_ICache_Rdy => Trace_ICache_Rdy,
Trace_OF_PipeRun => Trace_OF_PipeRun,
Trace_EX_PipeRun => Trace_EX_PipeRun,
Trace_MEM_PipeRun => Trace_MEM_PipeRun,
Trace_MB_Halted => Trace_MB_Halted,
Trace_Jump_Hit => Trace_Jump_Hit,
FSL0_S_CLK => FSL0_S_CLK,
FSL0_S_READ => FSL0_S_READ,
FSL0_S_DATA => FSL0_S_DATA,
FSL0_S_CONTROL => FSL0_S_CONTROL,
FSL0_S_EXISTS => FSL0_S_EXISTS,
FSL0_M_CLK => FSL0_M_CLK,
FSL0_M_WRITE => FSL0_M_WRITE,
FSL0_M_DATA => FSL0_M_DATA,
FSL0_M_CONTROL => FSL0_M_CONTROL,
FSL0_M_FULL => FSL0_M_FULL,
FSL1_S_CLK => FSL1_S_CLK,
FSL1_S_READ => FSL1_S_READ,
FSL1_S_DATA => FSL1_S_DATA,
FSL1_S_CONTROL => FSL1_S_CONTROL,
FSL1_S_EXISTS => FSL1_S_EXISTS,
FSL1_M_CLK => FSL1_M_CLK,
FSL1_M_WRITE => FSL1_M_WRITE,
FSL1_M_DATA => FSL1_M_DATA,
FSL1_M_CONTROL => FSL1_M_CONTROL,
FSL1_M_FULL => FSL1_M_FULL,
FSL2_S_CLK => FSL2_S_CLK,
FSL2_S_READ => FSL2_S_READ,
FSL2_S_DATA => FSL2_S_DATA,
FSL2_S_CONTROL => FSL2_S_CONTROL,
FSL2_S_EXISTS => FSL2_S_EXISTS,
FSL2_M_CLK => FSL2_M_CLK,
FSL2_M_WRITE => FSL2_M_WRITE,
FSL2_M_DATA => FSL2_M_DATA,
FSL2_M_CONTROL => FSL2_M_CONTROL,
FSL2_M_FULL => FSL2_M_FULL,
FSL3_S_CLK => FSL3_S_CLK,
FSL3_S_READ => FSL3_S_READ,
FSL3_S_DATA => FSL3_S_DATA,
FSL3_S_CONTROL => FSL3_S_CONTROL,
FSL3_S_EXISTS => FSL3_S_EXISTS,
FSL3_M_CLK => FSL3_M_CLK,
FSL3_M_WRITE => FSL3_M_WRITE,
FSL3_M_DATA => FSL3_M_DATA,
FSL3_M_CONTROL => FSL3_M_CONTROL,
FSL3_M_FULL => FSL3_M_FULL,
FSL4_S_CLK => FSL4_S_CLK,
FSL4_S_READ => FSL4_S_READ,
FSL4_S_DATA => FSL4_S_DATA,
FSL4_S_CONTROL => FSL4_S_CONTROL,
FSL4_S_EXISTS => FSL4_S_EXISTS,
FSL4_M_CLK => FSL4_M_CLK,
FSL4_M_WRITE => FSL4_M_WRITE,
FSL4_M_DATA => FSL4_M_DATA,
FSL4_M_CONTROL => FSL4_M_CONTROL,
FSL4_M_FULL => FSL4_M_FULL,
FSL5_S_CLK => FSL5_S_CLK,
FSL5_S_READ => FSL5_S_READ,
FSL5_S_DATA => FSL5_S_DATA,
FSL5_S_CONTROL => FSL5_S_CONTROL,
FSL5_S_EXISTS => FSL5_S_EXISTS,
FSL5_M_CLK => FSL5_M_CLK,
FSL5_M_WRITE => FSL5_M_WRITE,
FSL5_M_DATA => FSL5_M_DATA,
FSL5_M_CONTROL => FSL5_M_CONTROL,
FSL5_M_FULL => FSL5_M_FULL,
FSL6_S_CLK => FSL6_S_CLK,
FSL6_S_READ => FSL6_S_READ,
FSL6_S_DATA => FSL6_S_DATA,
FSL6_S_CONTROL => FSL6_S_CONTROL,
FSL6_S_EXISTS => FSL6_S_EXISTS,
FSL6_M_CLK => FSL6_M_CLK,
FSL6_M_WRITE => FSL6_M_WRITE,
FSL6_M_DATA => FSL6_M_DATA,
FSL6_M_CONTROL => FSL6_M_CONTROL,
FSL6_M_FULL => FSL6_M_FULL,
FSL7_S_CLK => FSL7_S_CLK,
FSL7_S_READ => FSL7_S_READ,
FSL7_S_DATA => FSL7_S_DATA,
FSL7_S_CONTROL => FSL7_S_CONTROL,
FSL7_S_EXISTS => FSL7_S_EXISTS,
FSL7_M_CLK => FSL7_M_CLK,
FSL7_M_WRITE => FSL7_M_WRITE,
FSL7_M_DATA => FSL7_M_DATA,
FSL7_M_CONTROL => FSL7_M_CONTROL,
FSL7_M_FULL => FSL7_M_FULL,
FSL8_S_CLK => FSL8_S_CLK,
FSL8_S_READ => FSL8_S_READ,
FSL8_S_DATA => FSL8_S_DATA,
FSL8_S_CONTROL => FSL8_S_CONTROL,
FSL8_S_EXISTS => FSL8_S_EXISTS,
FSL8_M_CLK => FSL8_M_CLK,
FSL8_M_WRITE => FSL8_M_WRITE,
FSL8_M_DATA => FSL8_M_DATA,
FSL8_M_CONTROL => FSL8_M_CONTROL,
FSL8_M_FULL => FSL8_M_FULL,
FSL9_S_CLK => FSL9_S_CLK,
FSL9_S_READ => FSL9_S_READ,
FSL9_S_DATA => FSL9_S_DATA,
FSL9_S_CONTROL => FSL9_S_CONTROL,
FSL9_S_EXISTS => FSL9_S_EXISTS,
FSL9_M_CLK => FSL9_M_CLK,
FSL9_M_WRITE => FSL9_M_WRITE,
FSL9_M_DATA => FSL9_M_DATA,
FSL9_M_CONTROL => FSL9_M_CONTROL,
FSL9_M_FULL => FSL9_M_FULL,
FSL10_S_CLK => FSL10_S_CLK,
FSL10_S_READ => FSL10_S_READ,
FSL10_S_DATA => FSL10_S_DATA,
FSL10_S_CONTROL => FSL10_S_CONTROL,
FSL10_S_EXISTS => FSL10_S_EXISTS,
FSL10_M_CLK => FSL10_M_CLK,
FSL10_M_WRITE => FSL10_M_WRITE,
FSL10_M_DATA => FSL10_M_DATA,
FSL10_M_CONTROL => FSL10_M_CONTROL,
FSL10_M_FULL => FSL10_M_FULL,
FSL11_S_CLK => FSL11_S_CLK,
FSL11_S_READ => FSL11_S_READ,
FSL11_S_DATA => FSL11_S_DATA,
FSL11_S_CONTROL => FSL11_S_CONTROL,
FSL11_S_EXISTS => FSL11_S_EXISTS,
FSL11_M_CLK => FSL11_M_CLK,
FSL11_M_WRITE => FSL11_M_WRITE,
FSL11_M_DATA => FSL11_M_DATA,
FSL11_M_CONTROL => FSL11_M_CONTROL,
FSL11_M_FULL => FSL11_M_FULL,
FSL12_S_CLK => FSL12_S_CLK,
FSL12_S_READ => FSL12_S_READ,
FSL12_S_DATA => FSL12_S_DATA,
FSL12_S_CONTROL => FSL12_S_CONTROL,
FSL12_S_EXISTS => FSL12_S_EXISTS,
FSL12_M_CLK => FSL12_M_CLK,
FSL12_M_WRITE => FSL12_M_WRITE,
FSL12_M_DATA => FSL12_M_DATA,
FSL12_M_CONTROL => FSL12_M_CONTROL,
FSL12_M_FULL => FSL12_M_FULL,
FSL13_S_CLK => FSL13_S_CLK,
FSL13_S_READ => FSL13_S_READ,
FSL13_S_DATA => FSL13_S_DATA,
FSL13_S_CONTROL => FSL13_S_CONTROL,
FSL13_S_EXISTS => FSL13_S_EXISTS,
FSL13_M_CLK => FSL13_M_CLK,
FSL13_M_WRITE => FSL13_M_WRITE,
FSL13_M_DATA => FSL13_M_DATA,
FSL13_M_CONTROL => FSL13_M_CONTROL,
FSL13_M_FULL => FSL13_M_FULL,
FSL14_S_CLK => FSL14_S_CLK,
FSL14_S_READ => FSL14_S_READ,
FSL14_S_DATA => FSL14_S_DATA,
FSL14_S_CONTROL => FSL14_S_CONTROL,
FSL14_S_EXISTS => FSL14_S_EXISTS,
FSL14_M_CLK => FSL14_M_CLK,
FSL14_M_WRITE => FSL14_M_WRITE,
FSL14_M_DATA => FSL14_M_DATA,
FSL14_M_CONTROL => FSL14_M_CONTROL,
FSL14_M_FULL => FSL14_M_FULL,
FSL15_S_CLK => FSL15_S_CLK,
FSL15_S_READ => FSL15_S_READ,
FSL15_S_DATA => FSL15_S_DATA,
FSL15_S_CONTROL => FSL15_S_CONTROL,
FSL15_S_EXISTS => FSL15_S_EXISTS,
FSL15_M_CLK => FSL15_M_CLK,
FSL15_M_WRITE => FSL15_M_WRITE,
FSL15_M_DATA => FSL15_M_DATA,
FSL15_M_CONTROL => FSL15_M_CONTROL,
FSL15_M_FULL => FSL15_M_FULL,
M0_AXIS_TLAST => M0_AXIS_TLAST,
M0_AXIS_TDATA => M0_AXIS_TDATA,
M0_AXIS_TVALID => M0_AXIS_TVALID,
M0_AXIS_TREADY => M0_AXIS_TREADY,
S0_AXIS_TLAST => S0_AXIS_TLAST,
S0_AXIS_TDATA => S0_AXIS_TDATA,
S0_AXIS_TVALID => S0_AXIS_TVALID,
S0_AXIS_TREADY => S0_AXIS_TREADY,
M1_AXIS_TLAST => M1_AXIS_TLAST,
M1_AXIS_TDATA => M1_AXIS_TDATA,
M1_AXIS_TVALID => M1_AXIS_TVALID,
M1_AXIS_TREADY => M1_AXIS_TREADY,
S1_AXIS_TLAST => S1_AXIS_TLAST,
S1_AXIS_TDATA => S1_AXIS_TDATA,
S1_AXIS_TVALID => S1_AXIS_TVALID,
S1_AXIS_TREADY => S1_AXIS_TREADY,
M2_AXIS_TLAST => M2_AXIS_TLAST,
M2_AXIS_TDATA => M2_AXIS_TDATA,
M2_AXIS_TVALID => M2_AXIS_TVALID,
M2_AXIS_TREADY => M2_AXIS_TREADY,
S2_AXIS_TLAST => S2_AXIS_TLAST,
S2_AXIS_TDATA => S2_AXIS_TDATA,
S2_AXIS_TVALID => S2_AXIS_TVALID,
S2_AXIS_TREADY => S2_AXIS_TREADY,
M3_AXIS_TLAST => M3_AXIS_TLAST,
M3_AXIS_TDATA => M3_AXIS_TDATA,
M3_AXIS_TVALID => M3_AXIS_TVALID,
M3_AXIS_TREADY => M3_AXIS_TREADY,
S3_AXIS_TLAST => S3_AXIS_TLAST,
S3_AXIS_TDATA => S3_AXIS_TDATA,
S3_AXIS_TVALID => S3_AXIS_TVALID,
S3_AXIS_TREADY => S3_AXIS_TREADY,
M4_AXIS_TLAST => M4_AXIS_TLAST,
M4_AXIS_TDATA => M4_AXIS_TDATA,
M4_AXIS_TVALID => M4_AXIS_TVALID,
M4_AXIS_TREADY => M4_AXIS_TREADY,
S4_AXIS_TLAST => S4_AXIS_TLAST,
S4_AXIS_TDATA => S4_AXIS_TDATA,
S4_AXIS_TVALID => S4_AXIS_TVALID,
S4_AXIS_TREADY => S4_AXIS_TREADY,
M5_AXIS_TLAST => M5_AXIS_TLAST,
M5_AXIS_TDATA => M5_AXIS_TDATA,
M5_AXIS_TVALID => M5_AXIS_TVALID,
M5_AXIS_TREADY => M5_AXIS_TREADY,
S5_AXIS_TLAST => S5_AXIS_TLAST,
S5_AXIS_TDATA => S5_AXIS_TDATA,
S5_AXIS_TVALID => S5_AXIS_TVALID,
S5_AXIS_TREADY => S5_AXIS_TREADY,
M6_AXIS_TLAST => M6_AXIS_TLAST,
M6_AXIS_TDATA => M6_AXIS_TDATA,
M6_AXIS_TVALID => M6_AXIS_TVALID,
M6_AXIS_TREADY => M6_AXIS_TREADY,
S6_AXIS_TLAST => S6_AXIS_TLAST,
S6_AXIS_TDATA => S6_AXIS_TDATA,
S6_AXIS_TVALID => S6_AXIS_TVALID,
S6_AXIS_TREADY => S6_AXIS_TREADY,
M7_AXIS_TLAST => M7_AXIS_TLAST,
M7_AXIS_TDATA => M7_AXIS_TDATA,
M7_AXIS_TVALID => M7_AXIS_TVALID,
M7_AXIS_TREADY => M7_AXIS_TREADY,
S7_AXIS_TLAST => S7_AXIS_TLAST,
S7_AXIS_TDATA => S7_AXIS_TDATA,
S7_AXIS_TVALID => S7_AXIS_TVALID,
S7_AXIS_TREADY => S7_AXIS_TREADY,
M8_AXIS_TLAST => M8_AXIS_TLAST,
M8_AXIS_TDATA => M8_AXIS_TDATA,
M8_AXIS_TVALID => M8_AXIS_TVALID,
M8_AXIS_TREADY => M8_AXIS_TREADY,
S8_AXIS_TLAST => S8_AXIS_TLAST,
S8_AXIS_TDATA => S8_AXIS_TDATA,
S8_AXIS_TVALID => S8_AXIS_TVALID,
S8_AXIS_TREADY => S8_AXIS_TREADY,
M9_AXIS_TLAST => M9_AXIS_TLAST,
M9_AXIS_TDATA => M9_AXIS_TDATA,
M9_AXIS_TVALID => M9_AXIS_TVALID,
M9_AXIS_TREADY => M9_AXIS_TREADY,
S9_AXIS_TLAST => S9_AXIS_TLAST,
S9_AXIS_TDATA => S9_AXIS_TDATA,
S9_AXIS_TVALID => S9_AXIS_TVALID,
S9_AXIS_TREADY => S9_AXIS_TREADY,
M10_AXIS_TLAST => M10_AXIS_TLAST,
M10_AXIS_TDATA => M10_AXIS_TDATA,
M10_AXIS_TVALID => M10_AXIS_TVALID,
M10_AXIS_TREADY => M10_AXIS_TREADY,
S10_AXIS_TLAST => S10_AXIS_TLAST,
S10_AXIS_TDATA => S10_AXIS_TDATA,
S10_AXIS_TVALID => S10_AXIS_TVALID,
S10_AXIS_TREADY => S10_AXIS_TREADY,
M11_AXIS_TLAST => M11_AXIS_TLAST,
M11_AXIS_TDATA => M11_AXIS_TDATA,
M11_AXIS_TVALID => M11_AXIS_TVALID,
M11_AXIS_TREADY => M11_AXIS_TREADY,
S11_AXIS_TLAST => S11_AXIS_TLAST,
S11_AXIS_TDATA => S11_AXIS_TDATA,
S11_AXIS_TVALID => S11_AXIS_TVALID,
S11_AXIS_TREADY => S11_AXIS_TREADY,
M12_AXIS_TLAST => M12_AXIS_TLAST,
M12_AXIS_TDATA => M12_AXIS_TDATA,
M12_AXIS_TVALID => M12_AXIS_TVALID,
M12_AXIS_TREADY => M12_AXIS_TREADY,
S12_AXIS_TLAST => S12_AXIS_TLAST,
S12_AXIS_TDATA => S12_AXIS_TDATA,
S12_AXIS_TVALID => S12_AXIS_TVALID,
S12_AXIS_TREADY => S12_AXIS_TREADY,
M13_AXIS_TLAST => M13_AXIS_TLAST,
M13_AXIS_TDATA => M13_AXIS_TDATA,
M13_AXIS_TVALID => M13_AXIS_TVALID,
M13_AXIS_TREADY => M13_AXIS_TREADY,
S13_AXIS_TLAST => S13_AXIS_TLAST,
S13_AXIS_TDATA => S13_AXIS_TDATA,
S13_AXIS_TVALID => S13_AXIS_TVALID,
S13_AXIS_TREADY => S13_AXIS_TREADY,
M14_AXIS_TLAST => M14_AXIS_TLAST,
M14_AXIS_TDATA => M14_AXIS_TDATA,
M14_AXIS_TVALID => M14_AXIS_TVALID,
M14_AXIS_TREADY => M14_AXIS_TREADY,
S14_AXIS_TLAST => S14_AXIS_TLAST,
S14_AXIS_TDATA => S14_AXIS_TDATA,
S14_AXIS_TVALID => S14_AXIS_TVALID,
S14_AXIS_TREADY => S14_AXIS_TREADY,
M15_AXIS_TLAST => M15_AXIS_TLAST,
M15_AXIS_TDATA => M15_AXIS_TDATA,
M15_AXIS_TVALID => M15_AXIS_TVALID,
M15_AXIS_TREADY => M15_AXIS_TREADY,
S15_AXIS_TLAST => S15_AXIS_TLAST,
S15_AXIS_TDATA => S15_AXIS_TDATA,
S15_AXIS_TVALID => S15_AXIS_TVALID,
S15_AXIS_TREADY => S15_AXIS_TREADY,
ICACHE_FSL_IN_CLK => ICACHE_FSL_IN_CLK,
ICACHE_FSL_IN_READ => ICACHE_FSL_IN_READ,
ICACHE_FSL_IN_DATA => ICACHE_FSL_IN_DATA,
ICACHE_FSL_IN_CONTROL => ICACHE_FSL_IN_CONTROL,
ICACHE_FSL_IN_EXISTS => ICACHE_FSL_IN_EXISTS,
ICACHE_FSL_OUT_CLK => ICACHE_FSL_OUT_CLK,
ICACHE_FSL_OUT_WRITE => ICACHE_FSL_OUT_WRITE,
ICACHE_FSL_OUT_DATA => ICACHE_FSL_OUT_DATA,
ICACHE_FSL_OUT_CONTROL => ICACHE_FSL_OUT_CONTROL,
ICACHE_FSL_OUT_FULL => ICACHE_FSL_OUT_FULL,
DCACHE_FSL_IN_CLK => DCACHE_FSL_IN_CLK,
DCACHE_FSL_IN_READ => DCACHE_FSL_IN_READ,
DCACHE_FSL_IN_DATA => DCACHE_FSL_IN_DATA,
DCACHE_FSL_IN_CONTROL => DCACHE_FSL_IN_CONTROL,
DCACHE_FSL_IN_EXISTS => DCACHE_FSL_IN_EXISTS,
DCACHE_FSL_OUT_CLK => DCACHE_FSL_OUT_CLK,
DCACHE_FSL_OUT_WRITE => DCACHE_FSL_OUT_WRITE,
DCACHE_FSL_OUT_DATA => DCACHE_FSL_OUT_DATA,
DCACHE_FSL_OUT_CONTROL => DCACHE_FSL_OUT_CONTROL,
DCACHE_FSL_OUT_FULL => DCACHE_FSL_OUT_FULL
);
end architecture STRUCTURE;
| mit | b031606f67b5f36fc43a98f9ddc7ae2c | 0.605957 | 2.754063 | false | false | false | false |
mithro/HDMI2USB | hdl/DEBUG/counter_top.vhd | 3 | 8,252 | -- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2014, Ajit Mathew <[email protected]>
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--The debug module collects counters from the system for debugging.
--The following counters will be supported:
-- - Device State
-- - Resolution
-- - in frame rate
-- - frame rate
-- - frame rate write time
-- - processing time
-- - frame drop count
-- - frame size
-- Use the dubugging program to access the counters
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity debug_top is
port(
clk : in std_logic;
clk_50Mhz : out std_logic;
rst : in std_logic;
vsync : in std_logic;
no_frame_read : in std_logic;
pktend : in std_logic;
jpg_busy : in std_logic;
write_img : in std_logic;
sw : in std_logic_vector(7 downto 0);
uart_en : out std_logic;
frame_size : in std_logic_vector(23 downto 0);
de_H0 : in std_logic; --Data enable for HDMI0
vsync_H0 : in std_logic;
hsync_H0 : in std_logic;
de_H1 : in std_logic; --Data enable for HDMI1
vsync_H1 : in std_logic;
hsync_H1 : in std_logic;
jpgORraw : in std_logic;
input_source : in std_logic_vector(1 downto 0);
encoding_Q : in std_logic_vector(1 downto 0);
resX : in std_logic_vector(15 downto 0);
resY : in std_logic_vector(15 downto 0);
eof_jpg : in std_logic;
debug_byte : out std_logic_vector(7 downto 0);
debug_index : in integer range 0 to 15;
uart_byte : out std_logic_vector(7 downto 0)
);
end debug_top;
architecture Behavioral of debug_top is
component counters
port(
clk : in std_logic;
clk_ms : in std_logic;
clk_1hz : in std_logic;
rst : in std_logic;
vsync : in std_logic;
no_frame_read : in std_logic;
write_img : in std_logic;
pktend : in std_logic;
jpg_busy : in std_logic;
proc_time : out std_logic_vector(7 downto 0);
frame_write_time : out std_logic_vector(7 downto 0);
frame_rate : out std_logic_vector(7 downto 0);
in_frame_rate : out std_logic_vector(7 downto 0);
frame_drop_cnt : out std_logic_vector(7 downto 0)
);
end component;
signal prescaler : integer range 0 to 50000000;
signal prescaler1 : integer range 0 to 50000;
signal clk_ms : std_logic;
signal clk_1hz : std_logic;
signal proc_time : std_logic_vector(7 downto 0);
signal frame_write_time : std_logic_vector(7 downto 0);
signal frame_rate : std_logic_vector(7 downto 0);
signal in_frame_rate : std_logic_vector(7 downto 0);
signal frame_drop_cnt : std_logic_vector(7 downto 0);
signal switch_case : std_logic_vector(2 downto 0);
signal send, send_q : std_logic;
signal clk_50Mhz_s : std_logic;
signal jpg_busy_s : std_logic;
signal cnt : integer range 0 to 32;
signal f_data : std_logic_vector(7 downto 0);
type f_send_states is (wait_send_edge, send_byte1, send_byte2);
signal f_send_state : f_send_states;
signal uart_en_f : std_logic;
signal uart_en1 : std_logic;
signal device_state : std_logic_vector(7 downto 0);
type send_array is array(0 to 15) of std_logic_vector(7 downto 0);
signal uart_send_array : send_array;
signal byte_cnt : integer range 0 to 15;
signal debug_byte_q : std_logic_vector(7 downto 0);
constant N_BYTES : integer := 14;
begin
clk_50Mhz <= clk_50Mhz_s;
process(clk, rst)
begin
if rst = '1' then
clk_50Mhz_s <= '0';
elsif rising_edge(clk) then
clk_50Mhz_s <= not clk_50Mhz_s;
end if;
end process;
clk_gen : process(clk, rst)
begin
if rst = '1' then
clk_1hz <= '0';
prescaler <= 0;
prescaler1 <= 0;
elsif rising_edge(clk) then
if prescaler = 50000000-1 then
prescaler <= 0;
clk_1hz <= not clk_1hz;
else
prescaler <= prescaler + 1;
end if;
if prescaler1 = 50000 then
prescaler1 <= 0;
clk_ms <= not clk_ms;
else
prescaler1 <= prescaler1 + 1;
end if;
end if;
end process clk_gen;
send <= clk_1hz;
device_state <= "0" & (de_H0 or vsync_H0 or hsync_H0) &
(de_H1 or vsync_H1 or hsync_H1) &
jpgORraw & input_source & encoding_Q;
uart_send_array(0) <= X"AA";
uart_send_array(1) <= device_state;
uart_send_array(2) <= resX(15 downto 8);
uart_send_array(3) <= resX(7 downto 0);
uart_send_array(4) <= resY(15 downto 8);
uart_send_array(5) <= resY(7 downto 0);
uart_send_array(6) <= in_frame_rate;
uart_send_array(7) <= frame_rate;
uart_send_array(8) <= frame_write_time;
uart_send_array(9) <= proc_time;
uart_send_array(10) <= frame_drop_cnt;
uart_send_array(11) <= frame_size(23 downto 16);
uart_send_array(12) <= frame_size(15 downto 8);
uart_send_array(13) <= frame_size(7 downto 0);
debug_byte <= uart_send_array(debug_index);
array_send : process(clk_50Mhz_s, rst)
begin
if rst = '1' then
uart_en <= '0';
uart_byte <= uart_send_array(0);
byte_cnt <= 0;
elsif rising_edge(clk_50Mhz_s) then
send_q <= send;
case byte_cnt is
when 0 =>
uart_en <= '0';
if send_q = '0' and send = '1' then
uart_en <= '1';
uart_byte <= uart_send_array(0);
byte_cnt <= byte_cnt+1;
end if;
when N_BYTES-1 =>
uart_en <= '1';
uart_byte <= uart_send_array(13);
byte_cnt <= 0;
when others =>
uart_en <= '1';
uart_byte <= uart_send_array(byte_cnt);
byte_cnt <= byte_cnt+1;
end case;
end if;
end process;
Inst_counters : counters port map(
clk => clk,
clk_ms => clk_ms,
clk_1hz => clk_1hz,
rst => rst,
vsync => vsync,
no_frame_read => no_frame_read,
write_img => write_img,
pktend => eof_jpg,
jpg_busy => jpg_busy,
proc_time => proc_time,
frame_write_time => frame_write_time,
frame_rate => frame_rate,
in_frame_rate => in_frame_rate,
frame_drop_cnt => frame_drop_cnt
);
end Behavioral;
| bsd-2-clause | 80932f4033f48e4d65624fb98d0a7378 | 0.569438 | 3.436901 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/resync_search_results.vhd | 1 | 10,537 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: resync_search_results - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity resync_search_results is
generic (
RESYNC_NODE_DATA : boolean := true;
RESYNC_CNTR_IDX : boolean := true
);
port (
clk : in std_logic;
sclr : in std_logic;
point_list_nd : in std_logic;
point_list_d : in data_type;
point_list_idx : in centre_index_type;
closest_n_first_nd : in std_logic;
max_idx : in centre_index_type;
min_point : in data_type;
min_index : in centre_index_type;
u_in : in node_data_type;
min_point_out : out data_type;
min_index_out : out centre_index_type;
point_list_d_out : out data_type;
point_list_idx_out : out centre_index_type;
u_out : out node_data_type;
rdy : out std_logic;
rdy_last_cycle : out std_logic
);
end resync_search_results;
architecture Behavioral of resync_search_results is
type state_type is (idle, readout);
component centre_positions_fifo
port (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(D*COORD_BITWIDTH-1 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(D*COORD_BITWIDTH-1 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
end component;
component centre_index_fifo
port (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
end component;
component ctrl_fifo
port (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(2*INDEX_BITWIDTH+D*COORD_BITWIDTH-1 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(2*INDEX_BITWIDTH+D*COORD_BITWIDTH-1 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
end component;
component ctrl_fifo_u
port (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
end component;
signal state : state_type;
signal counter : centre_index_type;
signal counter_done : std_logic;
signal tmp_fifo1_din : std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
signal tmp_fifo1_dout : std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
signal tmp_fifo1_dout_conv : data_type;
signal tmp_fifo1_rd_en : std_logic;
signal tmp_fifo1_emp : std_logic;
signal tmp_fifo1_valid : std_logic;
signal tmp_fifo1_idx_din : std_logic_vector(INDEX_BITWIDTH-1 downto 0);
signal tmp_fifo1_idx_dout : std_logic_vector(INDEX_BITWIDTH-1 downto 0);
signal tmp_fifo2_din : std_logic_vector(2*INDEX_BITWIDTH+D*COORD_BITWIDTH-1 downto 0);
signal tmp_fifo2_dout : std_logic_vector(2*INDEX_BITWIDTH+D*COORD_BITWIDTH-1 downto 0);
signal tmp_fifo2_rd_en : std_logic;
signal tmp_fifo2_emp : std_logic;
signal tmp_fifo2_valid : std_logic;
signal tmp_fifo2_minpoint_conv : data_type;
signal tmp_fifo2_u_din : std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0);
signal tmp_fifo2_u_dout : std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0);
signal tmp_fifo2_u_dout_conv : node_data_type;
signal reg_point_list_d_out : data_type;
signal min_point_reg : data_type;
signal min_index_reg : centre_index_type;
signal u_reg : node_data_type;
--signal fifo1_valid_reg : std_logic;
signal last_cycle_reg : std_logic;
begin
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
state <= idle;
elsif state = idle AND tmp_fifo2_rd_en='1' then
state <= readout;
elsif state = readout AND counter = 0 then
state <= idle;
end if;
end if;
end process fsm_proc;
counter_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
counter <= (others => '1');
else
if state = idle then
counter <= unsigned(tmp_fifo2_dout(INDEX_BITWIDTH-1 downto 0));
elsif state = readout then
counter <= counter-1;
end if;
end if;
end if;
end process counter_proc;
counter_done <= '1' WHEN state = readout AND counter = 0 ELSE '0';
-- buffer the centres in a fifo until minsearch is done
G1: for I in 0 to D-1 generate
tmp_fifo1_din((I+1)*COORD_BITWIDTH-1 downto I*COORD_BITWIDTH) <= point_list_d(I);
end generate G1;
tmp_fifo1_rd_en <= '1' WHEN state = readout ELSE '0';
fifo1_inst : centre_positions_fifo
port map (
clk => clk,
srst => sclr,
din => tmp_fifo1_din,
wr_en => point_list_nd,
rd_en => tmp_fifo1_rd_en,
dout => tmp_fifo1_dout,
full => open,
empty => tmp_fifo1_emp,
valid => tmp_fifo1_valid
);
G2: for I in 0 to D-1 generate
tmp_fifo1_dout_conv(I) <= tmp_fifo1_dout((I+1)*COORD_BITWIDTH-1 downto I*COORD_BITWIDTH);
end generate G2;
G_RSNC_CNTR_IDX : if RESYNC_CNTR_IDX = true generate
tmp_fifo1_idx_din <= std_logic_vector(point_list_idx);
fifo1_idx_inst : centre_index_fifo
port map (
clk => clk,
srst => sclr,
din => tmp_fifo1_idx_din,
wr_en => point_list_nd,
rd_en => tmp_fifo1_rd_en,
dout => tmp_fifo1_idx_dout,
full => open,
empty => open,
valid => open
);
end generate G_RSNC_CNTR_IDX;
G_NRSNC_CNTR_IDX : if RESYNC_CNTR_IDX = false generate
tmp_fifo1_idx_dout <= (others => '0');
end generate G_NRSNC_CNTR_IDX;
tmp_fifo2_din(INDEX_BITWIDTH-1 downto 0) <= std_logic_vector(max_idx);
tmp_fifo2_din(2*INDEX_BITWIDTH-1 downto 1*INDEX_BITWIDTH) <= std_logic_vector(min_index);
G3: for I in 0 to D-1 generate
tmp_fifo2_din((I+1)*COORD_BITWIDTH+2*INDEX_BITWIDTH-1 downto I*COORD_BITWIDTH+2*INDEX_BITWIDTH) <= min_point(I);
end generate G3;
tmp_fifo2_rd_en <= '1' WHEN state = idle AND tmp_fifo2_emp = '0' ELSE '0';
fifo2_inst : ctrl_fifo
port map (
clk => clk,
srst => sclr,
din => tmp_fifo2_din,
wr_en => closest_n_first_nd,
rd_en => tmp_fifo2_rd_en,
dout => tmp_fifo2_dout,
full => open,
empty => tmp_fifo2_emp,
valid => tmp_fifo2_valid
);
G5: for I in 0 to D-1 generate
tmp_fifo2_minpoint_conv(I) <= tmp_fifo2_dout((I+1)*COORD_BITWIDTH+2*INDEX_BITWIDTH-1 downto I*COORD_BITWIDTH+2*INDEX_BITWIDTH);
end generate G5;
G_RSNC_U : if RESYNC_NODE_DATA = true generate
tmp_fifo2_u_din <= nodedata_2_stdlogic(u_in);
fifo2_u_inst : ctrl_fifo_u
port map (
clk => clk,
srst => sclr,
din => tmp_fifo2_u_din,
wr_en => closest_n_first_nd,
rd_en => tmp_fifo2_rd_en,
dout => tmp_fifo2_u_dout,
full => open,
empty => open,
valid => open
);
tmp_fifo2_u_dout_conv <= stdlogic_2_nodedata(tmp_fifo2_u_dout);
end generate G_RSNC_U;
G_NRSNC_U : if RESYNC_NODE_DATA = false generate
tmp_fifo2_u_dout <= (others => '0');
tmp_fifo2_u_dout_conv <= stdlogic_2_nodedata(tmp_fifo2_u_dout);
end generate G_NRSNC_U;
output_reg_proc : process(clk)
begin
if rising_edge(clk) then
if state = idle then
min_point_reg <= tmp_fifo2_minpoint_conv;
min_index_reg <= unsigned(tmp_fifo2_dout(2*INDEX_BITWIDTH-1 downto 1*INDEX_BITWIDTH));
u_reg <= tmp_fifo2_u_dout_conv;
end if;
if sclr = '1' then
last_cycle_reg <= '0';
else
last_cycle_reg <= counter_done;
end if;
end if;
end process output_reg_proc;
rdy_last_cycle <= last_cycle_reg; -- be careful if changing latency of fifo1
rdy <= tmp_fifo1_valid;
point_list_d_out <= tmp_fifo1_dout_conv;--reg_point_list_d_out;
point_list_idx_out <= unsigned(tmp_fifo1_idx_dout);
min_point_out <= min_point_reg;
min_index_out <= min_index_reg;
u_out <= u_reg;
end Behavioral;
| bsd-3-clause | c77c815475a3b2e805e0bc77dec1a1d9 | 0.538389 | 3.633448 | false | false | false | false |
freecores/gpib_controller | vhdl/test/gpibWriterReaderTest.vhd | 1 | 14,175 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 23:21:05 10/21/2011
-- Design Name:
-- Module Name: /windows/h/projekty/elektronika/USB_to_HPIB/usbToHpib/test_scr//gpibInterfaceTest.vhd
-- Project Name: usbToHpib
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: gpibInterface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.gpibComponents.all;
use work.helperComponents.all;
ENTITY gpibWriterReaderTest IS
END gpibWriterReaderTest;
ARCHITECTURE behavior OF gpibWriterReaderTest IS
-- Component Declaration for the Unit Under Test (UUT)
component gpibCableEmulator is port (
-- interface signals
DIO_1 : in std_logic_vector (7 downto 0);
output_valid_1 : in std_logic;
DIO_2 : in std_logic_vector (7 downto 0);
output_valid_2 : in std_logic;
DIO : out std_logic_vector (7 downto 0);
-- attention
ATN_1 : in std_logic;
ATN_2 : in std_logic;
ATN : out std_logic;
-- data valid
DAV_1 : in std_logic;
DAV_2 : in std_logic;
DAV : out std_logic;
-- not ready for data
NRFD_1 : in std_logic;
NRFD_2 : in std_logic;
NRFD : out std_logic;
-- no data accepted
NDAC_1 : in std_logic;
NDAC_2 : in std_logic;
NDAC : out std_logic;
-- end or identify
EOI_1 : in std_logic;
EOI_2 : in std_logic;
EOI : out std_logic;
-- service request
SRQ_1 : in std_logic;
SRQ_2 : in std_logic;
SRQ : out std_logic;
-- interface clear
IFC_1 : in std_logic;
IFC_2 : in std_logic;
IFC : out std_logic;
-- remote enable
REN_1 : in std_logic;
REN_2 : in std_logic;
REN : out std_logic
);
end component;
-- inputs common
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal T1 : std_logic_vector(7 downto 0) := "00000100";
-- inputs 1
signal data_1 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_1 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_1 : std_logic := '0';
signal nba_1 : std_logic := '0';
signal ltn_1 : std_logic := '0';
signal lun_1 : std_logic := '0';
signal lon_1 : std_logic := '0';
signal ton_1 : std_logic := '0';
signal endOf_1 : std_logic := '0';
signal gts_1 : std_logic := '0';
signal rpp_1 : std_logic := '0';
signal tcs_1 : std_logic := '0';
signal tca_1 : std_logic := '0';
signal sic_1 : std_logic := '0';
signal rsc_1 : std_logic := '0';
signal sre_1 : std_logic := '0';
signal rtl_1 : std_logic := '0';
signal rsv_1 : std_logic := '0';
signal ist_1 : std_logic := '0';
signal lpe_1 : std_logic := '0';
-- inputs 2
signal data_2 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_2 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_2 : std_logic := '0';
signal nba_2 : std_logic := '0';
signal ltn_2 : std_logic := '0';
signal lun_2 : std_logic := '0';
signal lon_2 : std_logic := '0';
signal ton_2 : std_logic := '0';
signal endOf_2 : std_logic := '0';
signal gts_2 : std_logic := '0';
signal rpp_2 : std_logic := '0';
signal tcs_2 : std_logic := '0';
signal tca_2 : std_logic := '0';
signal sic_2 : std_logic := '0';
signal rsc_2 : std_logic := '0';
signal sre_2 : std_logic := '0';
signal rtl_2 : std_logic := '0';
signal rsv_2 : std_logic := '0';
signal ist_2 : std_logic := '0';
signal lpe_2 : std_logic := '0';
-- outputs 1
signal dvd_1 : std_logic;
signal wnc_1 : std_logic;
signal tac_1 : std_logic;
signal lac_1 : std_logic;
signal cwrc_1 : std_logic;
signal cwrd_1 : std_logic;
signal clr_1 : std_logic;
signal trg_1 : std_logic;
signal atl_1 : std_logic;
signal att_1 : std_logic;
signal mla_1 : std_logic;
signal lsb_1 : std_logic;
signal spa_1 : std_logic;
signal ppr_1 : std_logic;
signal sreq_1 : std_logic;
signal isLocal_1 : std_logic;
signal currentSecAddr_1 : std_logic_vector (4 downto 0);
-- outputs 2
signal dvd_2 : std_logic;
signal wnc_2 : std_logic;
signal tac_2 : std_logic;
signal lac_2 : std_logic;
signal cwrc_2 : std_logic;
signal cwrd_2 : std_logic;
signal clr_2 : std_logic;
signal trg_2 : std_logic;
signal atl_2 : std_logic;
signal att_2 : std_logic;
signal mla_2 : std_logic;
signal lsb_2 : std_logic;
signal spa_2 : std_logic;
signal ppr_2 : std_logic;
signal sreq_2 : std_logic;
signal isLocal_2 : std_logic;
signal currentSecAddr_2 : std_logic_vector (4 downto 0);
-- common
signal DO : std_logic_vector (7 downto 0);
signal DI_1 : std_logic_vector (7 downto 0);
signal output_valid_1 : std_logic;
signal DI_2 : std_logic_vector (7 downto 0);
signal output_valid_2 : std_logic;
signal ATN_1, ATN_2, ATN : std_logic;
signal DAV_1, DAV_2, DAV : std_logic;
signal NRFD_1, NRFD_2, NRFD : std_logic;
signal NDAC_1, NDAC_2, NDAC : std_logic;
signal EOI_1, EOI_2, EOI : std_logic;
signal SRQ_1, SRQ_2, SRQ : std_logic;
signal IFC_1, IFC_2, IFC : std_logic;
signal REN_1, REN_2, REN : std_logic;
type WR_BUF_TYPE is
array (0 to 15) of std_logic_vector (7 downto 0);
-- gpib reader
signal buf_interrupt : std_logic;
signal data_available : std_logic;
signal last_byte_addr : std_logic_vector (3 downto 0);
signal end_of_stream : std_logic;
signal byte_addr : std_logic_vector (3 downto 0);
signal data_out : std_logic_vector (7 downto 0);
signal reset_buffer : std_logic := '0';
signal dataSecAddr : std_logic_vector (4 downto 0);
signal buf_strobe : std_logic;
signal buffer_byte_mode : std_logic;
signal read_buffer : WR_BUF_TYPE;
-- gpib writer
signal w_last_byte_addr : std_logic_vector (3 downto 0)
:= (others => '0');
signal w_end_of_stream : std_logic := '0';
signal w_data_available : std_logic := '0';
signal w_buf_interrupt : std_logic;
signal w_data_in : std_logic_vector (7 downto 0);
signal w_byte_addr : std_logic_vector (3 downto 0);
signal w_reset_buffer : std_logic := '0';
signal w_buffer_byte_mode : std_logic;
signal w_write_buffer : WR_BUF_TYPE;
-- Clock period definitions
constant clk_period : time := 2ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
gpib1: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00001",
myTalkAddr => "00001",
secAddrMask => (others => '0'),
data => data_1,
status_byte => status_byte_1,
T1 => T1,
rdy => rdy_1,
nba => nba_1,
ltn => ltn_1,
lun => lun_1,
lon => lon_1,
ton => ton_1,
endOf => endOf_1,
gts => gts_1,
rpp => rpp_1,
tcs => tcs_1,
tca => tca_1,
sic => sic_1,
rsc => rsc_1,
sre => sre_1,
rtl => rtl_1,
rsv => rsv_1,
ist => ist_1,
lpe => lpe_1,
dvd => dvd_1,
wnc => wnc_1,
tac => tac_1,
lac => lac_1,
cwrc => cwrc_1,
cwrd => cwrd_1,
clr => clr_1,
trg => trg_1,
atl => atl_1,
att => att_1,
mla => mla_1,
lsb => lsb_1,
spa => spa_1,
ppr => ppr_1,
sreq => sreq_1,
isLocal => isLocal_1,
currentSecAddr => currentSecAddr_1,
DI => DO,
DO => DI_1,
output_valid => output_valid_1,
ATN_in => ATN,
ATN_out => ATN_1,
DAV_in => DAV,
DAV_out => DAV_1,
NRFD_in => NRFD,
NRFD_out => NRFD_1,
NDAC_in => NDAC,
NDAC_out => NDAC_1,
EOI_in => EOI,
EOI_out => EOI_1,
SRQ_in => SRQ,
SRQ_out => SRQ_1,
IFC_in => IFC,
IFC_out => IFC_1,
REN_in => REN,
REN_out => REN_1
);
-- Instantiate the Unit Under Test (UUT)
gpib2: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00010",
myTalkAddr => "00010",
secAddrMask => (others => '0'),
data => data_2,
status_byte => status_byte_2,
T1 => T1,
rdy => rdy_2,
nba => nba_2,
ltn => ltn_2,
lun => lun_2,
lon => lon_2,
ton => ton_2,
endOf => endOf_2,
gts => gts_2,
rpp => rpp_2,
tcs => tcs_2,
tca => tca_2,
sic => sic_2,
rsc => rsc_2,
sre => sre_2,
rtl => rtl_2,
rsv => rsv_2,
ist => ist_2,
lpe => lpe_2,
dvd => dvd_2,
wnc => wnc_2,
tac => tac_2,
lac => lac_2,
cwrc => cwrc_2,
cwrd => cwrd_2,
clr => clr_2,
trg => trg_2,
atl => atl_2,
att => att_2,
mla => mla_2,
lsb => lsb_2,
spa => spa_2,
ppr => ppr_2,
sreq => sreq_2,
isLocal => isLocal_2,
currentSecAddr => currentSecAddr_2,
DI => DO,
DO => DI_2,
output_valid => output_valid_2,
ATN_in => ATN,
ATN_out => ATN_2,
DAV_in => DAV,
DAV_out => DAV_2,
NRFD_in => NRFD,
NRFD_out => NRFD_2,
NDAC_in => NDAC,
NDAC_out => NDAC_2,
EOI_in => EOI,
EOI_out => EOI_2,
SRQ_in => SRQ,
SRQ_out => SRQ_2,
IFC_in => IFC,
IFC_out => IFC_2,
REN_in => REN,
REN_out => REN_2
);
ce: gpibCableEmulator port map (
-- interface signals
DIO_1 => DI_1,
output_valid_1 => output_valid_1,
DIO_2 => DI_2,
output_valid_2 => output_valid_2,
DIO => DO,
-- attention
ATN_1 => ATN_1, ATN_2 => ATN_2, ATN => ATN,
DAV_1 => DAV_1, DAV_2 => DAV_2, DAV => DAV,
NRFD_1 => NRFD_1, NRFD_2 => NRFD_2, NRFD => NRFD,
NDAC_1 => NDAC_1, NDAC_2 => NDAC_2, NDAC => NDAC,
EOI_1 => EOI_1, EOI_2 => EOI_2, EOI => EOI,
SRQ_1 => SRQ_1, SRQ_2 => SRQ_2, SRQ => SRQ,
IFC_1 => IFC_1, IFC_2 => IFC_2, IFC => IFC,
REN_1 => REN_1, REN_2 => REN_2, REN => REN
);
process (buf_strobe) begin
if rising_edge(buf_strobe) then
read_buffer(conv_integer(w_byte_addr)) <= data_out;
end if;
end process;
gr: gpibReader generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_in => DO, dvd => dvd_2, lac => lac_2, lsb => lsb_2, rdy => rdy_2,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isLE => '0', secAddr => (others => '0'), dataSecAddr => dataSecAddr,
buf_interrupt => buf_interrupt, data_available => data_available,
last_byte_addr => last_byte_addr, end_of_stream => end_of_stream,
byte_addr => byte_addr, data_out => data_out,
buf_strobe => buf_strobe, buffer_byte_mode => buffer_byte_mode,
reset_buffer => reset_buffer
);
w_data_in <= w_write_buffer(conv_integer(w_byte_addr));
gw: gpibWriter generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_out => data_1, wnc => wnc_1, spa => spa_1, nba => nba_1,
endOf => endOf_1, tac => tac_1, cwrc => cwrc_1,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isTE => '0', secAddr => (others => '0'), dataSecAddr => (others => '0'),
last_byte_addr => w_last_byte_addr, end_of_stream => w_end_of_stream,
data_available => w_data_available, buf_interrupt => w_buf_interrupt,
data_in => w_data_in, byte_addr => w_byte_addr,
buffer_byte_mode => w_buffer_byte_mode,
reset_buffer => w_reset_buffer
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 10 clock periods.
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*10;
-- requests system control
rsc_1 <= '1';
-- interface clear
sic_1 <= '1';
wait until IFC_1 = '1';
sic_1 <= '0';
wait until IFC_1 = '0';
-- gpib2 to listen
w_write_buffer(0) <= "00100010";
-- gpib1 to talk
w_write_buffer(1) <= "01000001";
w_last_byte_addr <= "0001";
w_end_of_stream <= '1';
w_data_available <= '1';
wait until w_buf_interrupt='1';
gts_1 <= '1';
wait until ATN='0';
w_reset_buffer <= '1';
wait for clk_period*2;
w_reset_buffer <= '0';
wait for clk_period*1;
w_write_buffer(0) <= "10101010";
w_write_buffer(1) <= "01010101";
w_write_buffer(2) <= "11111111";
w_last_byte_addr <= "0010";
w_data_available <= '1';
wait until buf_interrupt='1';
wait for clk_period*1;
assert read_buffer(0) = "10101010";
wait for clk_period*1;
assert read_buffer(1) = "01010101";
wait for clk_period*1;
assert read_buffer(2) = "11111111";
report "$$$ END OF TEST - write read $$$";
wait;
end process;
END;
| gpl-3.0 | 9ee95917887942f87281e51bb8f63027 | 0.567831 | 2.887553 | false | false | false | false |
RickvanLoo/Synthesizer | phaseaccum_entity.vhd | 1 | 1,022 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
entity phaseaccum_entity is
GENERIC(max_length : integer := 2147483647;
lut_bit_width : integer := 8;
pa_bit_width : integer := 32
);
PORT (a_clk : IN std_logic;
reset : IN std_logic;
PA_word : IN unsigned(pa_bit_width-1 downto 0);
phase_out : OUT unsigned(lut_bit_width-1 downto 0)
);
END phaseaccum_entity;
architecture behav of phaseaccum_entity is
signal phase_reg : unsigned(pa_bit_width-1 downto 0) := (others => '0');
begin
process(a_clk,reset)
begin
if reset = '0' then
phase_reg <= (others => '0');
phase_out <= (others => '0');
elsif falling_edge(a_clk) then
if PA_word = x"00000000" then
phase_reg <= (others => '0');
phase_out <= (others => '0');
else
phase_reg <= phase_reg + PA_word;
phase_out <= phase_reg(pa_bit_width-1 downto pa_bit_width-lut_bit_width); -- 24-31
end if;
end if;
end process;
end behav; | mit | bd0c80fb257315030f40c241425d4b7c | 0.597847 | 2.979592 | false | false | false | false |
tsotnep/vhdl_soc_audio_mixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/superip.vhd | 2 | 17,403 | ------------------------------------------------------------------------------
-- superip.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: superip.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue May 5 20:44:19 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library superip_v1_00_a;
use superip_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity superip is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic; -- get rid of this
Audio_Left_in : in std_logic_vector(23 downto 0);
Audio_Right_in : in std_logic_vector(23 downto 0);
Mux3_BalanceORMux2_Left_out : out std_logic_vector(23 downto 0);
Mux3_BalanceORMux2_Right_out : out std_logic_vector(23 downto 0);
SAMPLE_TRIG : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity superip;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of superip is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity superip_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
CLK_48_in => CLK_48_in,
CLK_100M_in => CLK_100M_in,
Audio_Left_in => Audio_Left_in,
Audio_Right_in => Audio_Right_in,
Mux3_BalanceORMux2_Left_out => Mux3_BalanceORMux2_Left_out,
Mux3_BalanceORMux2_Right_out => Mux3_BalanceORMux2_Right_out,
SAMPLE_TRIG => SAMPLE_TRIG,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
| mit | 9e88e95a500eef25d1610d6e66552790 | 0.461127 | 4.138644 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/pcores/bajsd_v1_00_a/hdl/vhdl/bajsd.vhd | 2 | 4,824 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bajsd is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
attribute SIGIS of FSL_S_Clk : signal is "Clk";
attribute SIGIS of FSL_M_Clk : signal is "Clk";
end bajsd;
architecture EXAMPLE of bajsd is
-- Total number of input data.
constant NUMBER_OF_INPUT_WORDS : natural := 4;
-- Total number of output data
constant NUMBER_OF_OUTPUT_WORDS : natural := 2;
type STATE_TYPE is (Idle, Read_Inputs, cracking, Write_Outputs);
signal state : STATE_TYPE;
-- Accumulator to hold sum of inputs read at any point in time
--signal sum : std_logic_vector(0 to 31);
-- Counters to store the number inputs read & outputs written
signal nr_of_reads : natural range 0 to NUMBER_OF_INPUT_WORDS - 1;
signal nr_of_writes : natural range 0 to NUMBER_OF_OUTPUT_WORDS - 1;
signal s_fsl_data_recv : std_logic;
signal s_fsl_hash : std_logic_vector(127 downto 0);
signal s_pw_found : std_logic;
signal s_passwd : std_logic_vector(47 downto 0);
signal tmp_passwd : std_logic_vector(47 downto 0);
signal s_rstn : std_logic;
component brutus_top is
generic (
M : integer := 1
);
port (
clk : in std_logic;
rstn : in std_logic;
i_fsl_data_recv : in std_logic;
i_fsl_hash : in std_logic_vector(127 downto 0);
o_pw_found : out std_logic;
o_passwd : out std_logic_vector(47 downto 0)
);
end component brutus_top;
begin
s_rstn <= not FSL_Rst; -- for brutus inverted reset
-- Brutus instantiation --
brutus_inst: brutus_top
port map (
clk => FSL_Clk,
rstn => s_rstn, -- active low
i_fsl_data_recv => s_fsl_data_recv,
i_fsl_hash => s_fsl_hash,
o_pw_found => s_pw_found,
o_passwd => s_passwd
);
FSL_S_Read <= FSL_S_Exists when state = Read_Inputs else '0';
FSL_M_Write <= not FSL_M_Full when state = Write_Outputs else '0';
FSL_M_Data <= tmp_passwd(31 downto 0); --s_passwd(31 downto 0);
The_SW_accelerator : process (FSL_Clk) is
begin -- process The_SW_accelerator
if FSL_Clk'event and FSL_Clk = '1' then -- Rising clock edge
if FSL_Rst = '1' then -- Synchronous reset (active high)
-- CAUTION: make sure your reset polarity is consistent with the
-- system reset polarity
state <= Idle;
nr_of_reads <= 0;
nr_of_writes <= 0;
--sum <= (others => '0');
s_fsl_data_recv <= '0'; -- fsl to brutus, signal for data available
s_fsl_hash <= (others => '0'); -- fsl to brutus, the has(c)h
tmp_passwd <= (others => '0');
else
case state is
when Idle =>
if (FSL_S_Exists = '1') then
state <= Read_Inputs;
nr_of_reads <= NUMBER_OF_INPUT_WORDS - 1;
s_fsl_hash <= (others => '0');
--sum <= (others => '0');
end if;
when Read_Inputs =>
if (FSL_S_Exists = '1') then
-- Coprocessor function (Adding) happens here
--sum <= x"12345678"; --std_logic_vector(unsigned(sum) + unsigned(FSL_S_Data));
s_fsl_hash <= s_fsl_hash(95 downto 0) & FSL_S_Data; -- shift in the hash 4 times
if (nr_of_reads = 0) then
state <= cracking; -- change this to cracking later
s_fsl_data_recv <= '1'; -- let brutus know it's time to crack
nr_of_writes <= NUMBER_OF_OUTPUT_WORDS - 1;
else
nr_of_reads <= nr_of_reads - 1;
end if;
end if;
when cracking =>
if s_pw_found = '1' then
state <= Write_Outputs;
tmp_passwd <= s_passwd;
end if;
when Write_Outputs =>
if (nr_of_writes = 0) then
state <= Idle;
else
if (FSL_M_Full = '0') then
tmp_passwd <= x"00000000" & tmp_passwd(47 downto 32);
nr_of_writes <= nr_of_writes - 1;
end if;
end if;
when others => null;
end case;
end if;
end if;
end process The_SW_accelerator;
end architecture EXAMPLE;
| mit | 7b5302ba3c17ffc0967e487794f2c86c | 0.560738 | 3.315464 | false | false | false | false |
esar/hdmilight-v2 | fpga/avg4.vhd | 1 | 5,156 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hscale4 is
Port ( CLK : in STD_LOGIC;
D_HSYNC : in STD_LOGIC;
D_VSYNC : in STD_LOGIC;
D_DATAENABLE : in STD_LOGIC;
D_R : in STD_LOGIC_VECTOR (7 downto 0);
D_G : in STD_LOGIC_VECTOR (7 downto 0);
D_B : in STD_LOGIC_VECTOR (7 downto 0);
Q_HSYNC : out STD_LOGIC;
Q_VSYNC : out STD_LOGIC;
Q_DATAENABLE : out STD_LOGIC;
CE2 : out STD_LOGIC;
CE4 : out STD_LOGIC;
Q_R : out STD_LOGIC_VECTOR (7 downto 0);
Q_G : out STD_LOGIC_VECTOR (7 downto 0);
Q_B : out STD_LOGIC_VECTOR (7 downto 0));
end hscale4;
architecture Behavioral of hscale4 is
signal COUNT : std_logic_vector(1 downto 0);
signal DATAENABLE_LAST : std_logic;
signal R1 : std_logic_vector(7 downto 0);
signal R2 : std_logic_vector(7 downto 0);
signal R3 : std_logic_vector(7 downto 0);
signal RSUM1 : std_logic_vector(8 downto 0);
signal RSUM2 : std_logic_vector(8 downto 0);
signal RSUM3 : std_logic_vector(8 downto 0);
signal RAVG : std_logic_vector(7 downto 0);
signal G1 : std_logic_vector(7 downto 0);
signal G2 : std_logic_vector(7 downto 0);
signal G3 : std_logic_vector(7 downto 0);
signal GSUM1 : std_logic_vector(8 downto 0);
signal GSUM2 : std_logic_vector(8 downto 0);
signal GSUM3 : std_logic_vector(8 downto 0);
signal GAVG : std_logic_vector(7 downto 0);
signal B1 : std_logic_vector(7 downto 0);
signal B2 : std_logic_vector(7 downto 0);
signal B3 : std_logic_vector(7 downto 0);
signal BSUM1 : std_logic_vector(8 downto 0);
signal BSUM2 : std_logic_vector(8 downto 0);
signal BSUM3 : std_logic_vector(8 downto 0);
signal BAVG : std_logic_vector(7 downto 0);
signal HSYNC : std_logic_vector(6 downto 0);
signal VSYNC : std_logic_vector(6 downto 0);
signal DATAENABLE : std_logic_vector(6 downto 0);
begin
process(CLK)
begin
if(rising_edge(CLK)) then
if(D_DATAENABLE = '1' and DATAENABLE_LAST = '0') then
COUNT <= (others => '0');
else
COUNT <= std_logic_vector(unsigned(COUNT) + 1);
end if;
DATAENABLE_LAST <= D_DATAENABLE;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
R3 <= R2;
R2 <= R1;
R1 <= D_R;
RSUM1 <= std_logic_vector(unsigned('0' & D_R) + unsigned('0' & R1));
RSUM2 <= std_logic_vector(unsigned('0' & R2) + unsigned('0' & R3));
RSUM3 <= std_logic_vector(unsigned('0' & RSUM1(8 downto 1)) + unsigned('0' & RSUM2(8 downto 1)));
if(COUNT(1 downto 0) = "01") then
RAVG <= RSUM3(8 downto 1);
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
G3 <= G2;
G2 <= G1;
G1 <= D_G;
GSUM1 <= std_logic_vector(unsigned('0' & D_G) + unsigned('0' & G1));
GSUM2 <= std_logic_vector(unsigned('0' & G2) + unsigned('0' & G3));
GSUM3 <= std_logic_vector(unsigned('0' & GSUM1(8 downto 1)) + unsigned('0' & GSUM2(8 downto 1)));
if(COUNT(1 downto 0) = "11") then
GAVG <= GSUM3(8 downto 1);
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
B3 <= B2;
B2 <= B1;
B1 <= D_B;
BSUM1 <= std_logic_vector(unsigned('0' & D_B) + unsigned('0' & B1));
BSUM2 <= std_logic_vector(unsigned('0' & B2) + unsigned('0' & B3));
BSUM3 <= std_logic_vector(unsigned('0' & BSUM1(8 downto 1)) + unsigned('0' & BSUM2(8 downto 1)));
if(COUNT(1 downto 0) = "11") then
BAVG <= BSUM3(8 downto 1);
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
HSYNC <= HSYNC(5 downto 0) & D_HSYNC;
VSYNC <= VSYNC(5 downto 0) & D_VSYNC;
DATAENABLE <= DATAENABLE(5 downto 0) & D_DATAENABLE;
end if;
end process;
Q_HSYNC <= HSYNC(6);
Q_VSYNC <= VSYNC(6);
Q_DATAENABLE <= DATAENABLE(6);
Q_R <= RAVG;
Q_G <= GAVG;
Q_B <= BAVG;
CE2 <= COUNT(0);
CE4 <= COUNT(1);
end Behavioral;
| gpl-2.0 | dd48022a8bcf8bcef3a24cf286de1e47 | 0.617339 | 2.994193 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib/if_func_DC.vhd | 1 | 2,784 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- author: Andrzej Paluch
--
-- Create Date: 01:04:57 10/03/2011
-- Design Name:
-- Module Name: if_func_DC - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity if_func_DC is
port(
-- device inputs
clk : in std_logic; -- clock
-- state inputs
LADS : in std_logic; -- listener addressed state (L or LE)
ACDS : in std_logic; -- accept data state (AH)
-- instructions
DCL : in std_logic; -- my listen address
SDC : in std_logic; -- unlisten
-- local instructions
clr : out std_logic -- clear device
);
end if_func_DC;
architecture Behavioral of if_func_DC is
-- states
type DC_STATE is (
-- device clear idle state
ST_DCIS,
-- device clear active state
ST_DCAS
);
-- current state
signal current_state : DC_STATE;
-- predicates
signal pred1 : boolean;
signal pred2 : boolean;
begin
-- state machine process
process(clk) begin
if rising_edge(clk) then
case current_state is
------------------
when ST_DCIS =>
if pred1 then
current_state <= ST_DCAS;
end if;
------------------
when ST_DCAS =>
if pred2 then
current_state <= ST_DCIS;
end if;
------------------
when others =>
current_state <= ST_DCIS;
end case;
end if;
end process;
-- predicates
pred1 <= (DCL='1' or (SDC='1' and LADS='1')) and ACDS='1';
pred2 <= not pred1;
-- clr generator
with current_state select
clr <=
'1' when ST_DCAS,
'0' when others;
end Behavioral;
| gpl-3.0 | c8be694e9946b6e22ca35033453392a3 | 0.595546 | 3.893706 | false | false | false | false |
kb3gtn/mojo_modulator | vhdl/src/databus_master.vhd | 3 | 6,897 | -----------------------------------------------------------------------------
-- databus_master.vhd
-- This file provides a simple data bus master design that can
-- interface with an 8 bit command bus.
--
-- Command Formats:
--
-- The commands are 8 bits in length.
--
-- In general this is the read/write command format for the databus.
--
-- Bit 7 Bit 0
-- R/!W A7 A6 A5 A4 A3 A2 A1 A0
--
-- There are 2 exceptions:
-- 0xFF and 0x7F are idle commands (they do nothing)
--
-- this means there are 0 -> 126 address in the databus master.
-- each address addresses 8 bits of memory.
--
-- Peter Fetterer <[email protected]>
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity databus_master is
Generic (
slave_latency_max : integer := 3 -- latency from read/write strb to when the
-- operation is complete in number of i_clk cycles.
-- 3 would give a slave 3 clock cycles to perform
-- the needed operation.
);
Port (
-- clock and resets
i_clk : in std_logic; -- input system clock
i_srst : in std_logic; -- sync reset to system clock
-- db master cmd interface
i_db_cmd_in : in std_logic_vector( 7 downto 0); -- input cmd byte
i_db_cmd_wstrb : in std_logic; -- write strobe for cmd byte
o_db_cmd_rdy : out std_logic; -- '1' rdy to process next cmd, '0' busy
i_db_cmd_data_in : in std_logic_vector( 7 downto 0); -- input byte if cmd is a write (with wstrb)
o_db_cmd_data_out : out std_logic_vector( 7 downto 0); -- output byte if cmd was a read
-- data bus interface
o_db_addr : out std_logic_vector( 6 downto 0); -- 6 -> 0 bit address bus (7 bits)
o_db_write_data : out std_logic_vector( 7 downto 0); -- write data
i_db_read_data : in std_logic_vector( 7 downto 0); -- read data
o_db_read_strb : out std_logic; -- db_read_strobe
o_db_write_strb : out std_logic -- db_write_strobe
);
end entity;
architecture b of databus_master is
---------------------------------------------
-- Signals
---------------------------------------------
signal db_state : integer;
signal slv_latency_cntr : integer;
signal db_data_read : std_logic_vector( 7 downto 0);
signal db_data_write : std_logic_vector( 7 downto 0);
signal db_addr : std_logic_vector( 6 downto 0);
signal db_wr_active : std_logic;
signal db_rd_active : std_logic;
begin
o_db_addr <= db_addr;
o_db_write_data <= db_data_write;
o_db_write_strb <= db_wr_active;
o_db_cmd_data_out <= db_data_read;
db_state_machine : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' ) then
-- in reset
db_state <= 0;
o_db_cmd_rdy <= '0';
db_addr <= (others=>'0');
db_data_write <= (others=>'0');
o_db_read_strb <= '0';
db_wr_active <= '0';
slv_latency_cntr <= 0;
else
-- state mux
case db_state is
when 0 =>
-- start of cycle
-- signal ready for a new command
o_db_cmd_rdy <= '1';
db_wr_active <= '0';
o_db_read_strb <= '0';
db_state <= 1;
when 1 =>
-- wait for a command
if ( i_db_cmd_wstrb = '1' ) then
-- we have a command to process
if ( i_db_cmd_in = x"FF" ) or ( i_db_cmd_in = x"7F" ) then
-- idle command.. ignore
db_state <= 1; -- stay here, wait for next cmd
else
-- this is a real command
db_addr <= i_db_cmd_in(6 downto 0); -- get address for cmd..
-- Is it a read or a write....
if ( i_db_cmd_in(7) = '1' ) then
-- this is a read register command
-- issue read request on address
o_db_read_strb <= '1';
o_db_cmd_rdy <= '0'; -- busy
db_state <= 2;
else
-- this is a write register command
-- issue write request
db_data_write <= i_db_cmd_data_in;
db_wr_active <= '1';
o_db_cmd_rdy <= '0'; -- busy
db_state <= 4;
end if;
end if;
end if;
when 2 =>
-- read command started...
-- need to wait for slave_latency_max clock cycles
if ( slv_latency_cntr = slave_latency_max ) then
-- slave latency counter expired..
-- push down read strobe when timer expires
o_db_read_strb <= '0';
db_data_read <= i_db_read_data; -- sample read bus into local register.
slv_latency_cntr <= 0;
db_state <= 0;
else
slv_latency_cntr <= slv_latency_cntr + 1;
end if;
-- state 3 removed..
when 4 =>
-- write request wait period.
db_wr_active <= '0';
-- need to wait for slave_latency_max clock cycles
if ( slv_latency_cntr = slave_latency_max ) then
-- slave latency counter expired..
slv_latency_cntr <= 0;
-- write should be complete now..
db_state <= 0;
else
slv_latency_cntr <= slv_latency_cntr + 1;
end if;
when others =>
db_state <= 0;
end case;
end if;
end if;
end process;
end architecture;
| apache-2.0 | 53a5a3fdd4763ecab8b518cb440465ee | 0.408003 | 4.555482 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/source/vhdl/lloyds_algorithm_core.vhd | 1 | 17,282 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: lloyds_algorithm_core - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.lloyds_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lloyds_algorithm_core is
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
-- initial parameters
n : in node_index_type;
k : in centre_index_type;
-- init node and centre memory
wr_init_node : in std_logic;
wr_node_address_init : in node_address_type;
wr_node_data_init : in node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
-- access centre buffer
rdo_centre_buffer : in std_logic;
centre_buffer_addr : in centre_index_type;
valid : out std_logic;
wgtCent_out : out data_type_ext;
sum_sq_out : out coord_type_ext;
count_out : out coord_type;
-- processing done
rdy : out std_logic
);
end lloyds_algorithm_core;
architecture Behavioral of lloyds_algorithm_core is
type state_type is (idle, init, processing_phase, done);
type schedule_state_type is (free, busy, wait_cycle);
type par_element_type_ext is array(0 to D-1) of std_logic_vector(PARALLEL_UNITS*COORD_BITWIDTH_EXT-1 downto 0);
type par_element_type_ext_sum is array(0 to D-1) of std_logic_vector(COORD_BITWIDTH_EXT+integer(ceil(log2(real(PARALLEL_UNITS))))-1 downto 0);
component memory_mgmt
port (
clk : in std_logic;
sclr : in std_logic;
rd : in std_logic;
rd_node_addr : in node_address_type;
k : in centre_index_type;
wr_init_node : in std_logic;
wr_node_address_init : in node_address_type;
wr_node_data_init : in node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
valid : out std_logic_vector(0 to PARALLEL_UNITS-1);
rd_node_data : out par_node_data_type;
rd_centre_list_pos_data : out par_data_type
);
end component;
component process_node is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
u_in : in node_data_type;
centre_positions_in : in data_type;
rdy : out std_logic;
final_index_out : out centre_index_type;
sum_sq_out : out coord_type_ext;
u_out : out node_data_type
);
end component;
component centre_buffer_mgmt
port (
clk : in std_logic;
sclr : in std_logic;
init : in std_logic;
addr_in_init : in centre_index_type;
nd : in std_logic;
request_rdo : in std_logic;
addr_in : in centre_index_type;
wgtCent_in : in data_type_ext;
sum_sq_in : in coord_type_ext;
count_in : in coord_type;
valid : out std_logic;
wgtCent_out : out data_type_ext;
sum_sq_out : out coord_type_ext;
count_out : out coord_type
);
end component;
component adder_tree
generic (
USE_DSP_FOR_ADD : boolean := true;
NUMBER_OF_INPUTS : integer := 4;
INPUT_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
input_string : in std_logic_vector(NUMBER_OF_INPUTS*INPUT_BITWIDTH-1 downto 0);
rdy : out std_logic;
output : out std_logic_vector(INPUT_BITWIDTH+integer(ceil(log2(real(NUMBER_OF_INPUTS))))-1 downto 0)
);
end component;
-- fsm
signal state : state_type;
signal start_processing : std_logic;
signal first_output : std_logic;
signal processing_done_counter : node_index_type;
signal processing_done : std_logic;
signal processing_done_reg : std_logic;
-- scheduler
signal schedule_state : schedule_state_type;
signal schedule_counter : centre_index_type;
signal schedule_node_counter : node_index_type;
signal schedule_node_counter_reg : node_index_type;
signal schedule_counter_done : std_logic;
signal schedule_first : std_logic;
signal schedule_next : std_logic;
signal schedule_par_not_yet_matched : std_logic;
-- memory mgmt
signal memory_mgmt_rd : std_logic;
signal memory_data_valid : std_logic_vector(0 to PARALLEL_UNITS-1);
signal rd_node_addr : node_address_type;
signal rd_k : centre_index_type;
signal rd_node_data : par_node_data_type;
signal rd_centre_positions : par_data_type;
-- process_node
signal pn_final_index_out : par_centre_index_type;
signal pn_sum_sq_out : par_coord_type_ext;
signal pn_rdy : std_logic_vector(0 to PARALLEL_UNITS-1);
signal pn_u_out : par_node_data_type;
-- centre buffer mgmt
signal tmp_addr : par_centre_index_type;
signal centre_buffer_valid : std_logic_vector(0 to PARALLEL_UNITS-1);
signal centre_buffer_wgtCent : par_data_type_ext;
signal centre_buffer_sum_sq : par_coord_type_ext;
signal centre_buffer_count : par_coord_type;
-- adder tree
signal at_input_string_count : std_logic_vector(PARALLEL_UNITS*COORD_BITWIDTH-1 downto 0);
signal at_count_rdy : std_logic;
signal at_count_out : std_logic_vector(COORD_BITWIDTH+integer(ceil(log2(real(PARALLEL_UNITS))))-1 downto 0);
signal at_input_string_wgtCent : par_element_type_ext;
signal at_wgtCent_rdy : std_logic;
signal at_wgtCent_out : par_element_type_ext_sum;
signal at_input_string_sum_sq : std_logic_vector(PARALLEL_UNITS*COORD_BITWIDTH_EXT-1 downto 0);
signal at_sum_sq_rdy : std_logic;
signal at_sum_sq_out : std_logic_vector(COORD_BITWIDTH_EXT+integer(ceil(log2(real(PARALLEL_UNITS))))-1 downto 0);
-- output
signal tmp_valid : std_logic;
signal tmp_count_out : coord_type;
signal tmp_wgtCent_out : data_type_ext;
signal tmp_sum_sq_out : coord_type_ext;
-- stats not synthesised
signal cycle_count_enable : std_logic;
signal first_start : std_logic := '0';
signal cycle_count : unsigned(31 downto 0);
begin
G0_SYNTH : if SYNTHESIS = false generate
-- some statistics
stats_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
cycle_count_enable <= '0';
elsif state = processing_phase AND processing_done_counter /= n then
cycle_count_enable <= '1';
elsif processing_done_counter = n then
cycle_count_enable <= '0';
end if;
if start = '1' then
first_start <= '1'; -- latch the first start assertion
end if;
if first_start = '0' then
cycle_count <= (others => '0');
else -- count cycles for all iterations
cycle_count <= cycle_count+1;
end if;
end if;
end process stats_proc;
end generate G0_SYNTH;
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
-- state <= idle;
-- elsif state = idle AND wr_init_node = '1' then
state <= init;
elsif state = init AND start = '1' then
state <= processing_phase;
elsif state = processing_phase AND processing_done_reg = '1' AND schedule_next = '1' then
state <= done;
elsif state = done then
state <= init;
end if;
end if;
end process fsm_proc;
start_processing <= '1' WHEN state = init AND start = '1' ELSE '0';
-- scheduler (get next node from node memory)
scheduler_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
schedule_state <= free;
elsif schedule_state = free AND schedule_first = '1' then
schedule_state <= busy;
elsif schedule_state = busy AND schedule_counter_done = '1' then
schedule_state <= free;
end if;
if sclr = '1' OR schedule_state = free then
schedule_counter <= to_unsigned(0,INDEX_BITWIDTH);
elsif schedule_state = busy then
schedule_counter <= schedule_counter+1;
end if;
if sclr = '1' then
schedule_node_counter <= (others => '0');
processing_done_reg <= '0';
else
if schedule_next = '1' then
schedule_node_counter <= schedule_node_counter+1;
end if;
if processing_done = '1' then
processing_done_reg <= '1';
end if;
end if;
end if;
end process scheduler_proc;
schedule_first <= '1' WHEN schedule_state = free AND state = processing_phase ELSE '0';
schedule_next <= '1' WHEN schedule_state = busy AND schedule_par_not_yet_matched = '1' ELSE '0';
schedule_counter_done <= '1' WHEN schedule_counter = k ELSE '0';
schedule_par_not_yet_matched <= '1' WHEN schedule_counter < to_unsigned(PARALLEL_UNITS,INDEX_BITWIDTH) ELSE '0';
processing_done <= '1' WHEN schedule_node_counter = n AND state = processing_phase ELSE '0';
memory_mgmt_rd <= schedule_next;
rd_node_addr <= std_logic_vector(schedule_node_counter);
rd_k <= k;
memory_mgmt_inst : memory_mgmt
port map (
clk => clk,
sclr => sclr,
rd => memory_mgmt_rd,
rd_node_addr => rd_node_addr,
k => rd_k,
wr_init_node => wr_init_node,
wr_node_address_init => wr_node_address_init,
wr_node_data_init => wr_node_data_init,
wr_init_pos => wr_init_pos,
wr_centre_list_pos_address_init => wr_centre_list_pos_address_init,
wr_centre_list_pos_data_init => wr_centre_list_pos_data_init,
valid => memory_data_valid,
rd_node_data => rd_node_data,
rd_centre_list_pos_data => rd_centre_positions
);
G_PAR_1 : for I in 0 to PARALLEL_UNITS-1 generate
process_node_inst : process_node
port map(
clk => clk,
sclr => sclr,
nd => memory_data_valid(I),
u_in => rd_node_data(I),
centre_positions_in => rd_centre_positions(I),
rdy => pn_rdy(I),
final_index_out => pn_final_index_out(I),
sum_sq_out => pn_sum_sq_out(I),
u_out => pn_u_out(I)
);
end generate G_PAR_1;
G_PAR_2 : for I in 0 to PARALLEL_UNITS-1 generate
tmp_addr(I) <= pn_final_index_out(I) WHEN rdo_centre_buffer = '0' ELSE centre_buffer_addr;
centre_buffer_mgmt_inst : centre_buffer_mgmt
port map (
clk => clk,
sclr => sclr,
nd => pn_rdy(I),
init => wr_init_pos,
addr_in_init => wr_centre_list_pos_address_init,
request_rdo => rdo_centre_buffer,
addr_in => tmp_addr(I),
wgtCent_in => conv_normal_2_ext(pn_u_out(I).position),
sum_sq_in => pn_sum_sq_out(I),
count_in => std_logic_vector(to_unsigned(1,COORD_BITWIDTH)),
valid => centre_buffer_valid(I),
wgtCent_out => centre_buffer_wgtCent(I),
sum_sq_out => centre_buffer_sum_sq(I),
count_out => centre_buffer_count(I)
);
at_input_string_count((I+1)*COORD_BITWIDTH-1 downto I*COORD_BITWIDTH) <= centre_buffer_count(I);
at_input_string_sum_sq((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT) <= centre_buffer_sum_sq(I);
G_PAR_2_1 : for J in 0 to D-1 generate
at_input_string_wgtCent(J)((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT) <= centre_buffer_wgtCent(I)(J);
end generate G_PAR_2_1;
end generate G_PAR_2;
G_PAR_3 : if PARALLEL_UNITS > 1 generate
adder_tree_inst_count : adder_tree
generic map (
USE_DSP_FOR_ADD => USE_DSP_FOR_ADD,
NUMBER_OF_INPUTS => PARALLEL_UNITS,
INPUT_BITWIDTH => COORD_BITWIDTH
)
port map(
clk => clk,
sclr => sclr,
nd => centre_buffer_valid(0),
sub => '0',
input_string => at_input_string_count,
rdy => at_count_rdy,
output => at_count_out
);
G_PAR_3_1 : for J in 0 to D-1 generate
adder_tree_inst_wgtCent : adder_tree
generic map (
USE_DSP_FOR_ADD => USE_DSP_FOR_ADD,
NUMBER_OF_INPUTS => PARALLEL_UNITS,
INPUT_BITWIDTH => COORD_BITWIDTH_EXT
)
port map(
clk => clk,
sclr => sclr,
nd => centre_buffer_valid(0),
sub => '0',
input_string => at_input_string_wgtCent(J),
rdy => at_wgtCent_rdy,
output => at_wgtCent_out(J)
);
tmp_wgtCent_out(J) <= at_wgtCent_out(J)(COORD_BITWIDTH_EXT-1 downto 0);
end generate G_PAR_3_1;
adder_tree_inst_sum_sq : adder_tree
generic map (
USE_DSP_FOR_ADD => USE_DSP_FOR_ADD,
NUMBER_OF_INPUTS => PARALLEL_UNITS,
INPUT_BITWIDTH => COORD_BITWIDTH_EXT
)
port map(
clk => clk,
sclr => sclr,
nd => centre_buffer_valid(0),
sub => '0',
input_string => at_input_string_sum_sq,
rdy => at_sum_sq_rdy,
output => at_sum_sq_out
);
tmp_valid <= at_count_rdy;
tmp_count_out <= at_count_out(COORD_BITWIDTH-1 downto 0);
tmp_sum_sq_out <= at_sum_sq_out(COORD_BITWIDTH_EXT-1 downto 0);
end generate G_PAR_3;
G_PAR_4 : if PARALLEL_UNITS = 1 generate
tmp_valid <= centre_buffer_valid(0);
tmp_count_out <= centre_buffer_count(0);
tmp_wgtCent_out <= centre_buffer_wgtCent(0);
tmp_sum_sq_out <= centre_buffer_sum_sq(0);
end generate G_PAR_4;
processing_done_counter_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
first_output <= '0';
processing_done_counter <= to_unsigned(PARALLEL_UNITS-1,NODE_POINTER_BITWIDTH);
elsif pn_rdy(PARALLEL_UNITS-1) = '1' then
first_output <= '1';
if first_output = '1' then
processing_done_counter <= processing_done_counter+to_unsigned(PARALLEL_UNITS,NODE_POINTER_BITWIDTH);
end if;
end if;
end if;
end process processing_done_counter_proc;
valid <= tmp_valid;
wgtCent_out <= tmp_wgtCent_out;
sum_sq_out <= tmp_sum_sq_out;
count_out <= tmp_count_out;
rdy <= '1' WHEN processing_done_counter >= n ELSE '0';
end Behavioral;
| bsd-3-clause | 7729eb2ddc9fbc923b6a7f687a513526 | 0.513887 | 4.021876 | false | false | false | false |
UdayanSinha/Code_Blocks | VHDL/Projects/work/adder_subtractor_generic.vhd | 1 | 1,463 | -- A-B=A+B'+1
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
--define entity for adder-subtractor
ENTITY add_subb IS
GENERIC(size: INTEGER);
PORT(a, b: IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); --std_logic_vector defines array of 8 elements with indexed from 0 to 7; can use bit_vector as well
add_sub: IN STD_LOGIC;
cout: OUT STD_LOGIC;
sum: OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0));
END add_subb;
--define architecture for adder-subtractor
ARCHITECTURE structural OF add_subb IS
COMPONENT full_adder --use a single full adder to build a bigger 8-bit adder-subtractor
PORT(a, b, carry_in: IN STD_LOGIC;
carry_out, sum: OUT STD_LOGIC);
END COMPONENT;
SIGNAL carry: STD_LOGIC_VECTOR(size DOWNTO 0); --for connecting carry-out pins internally among adders
SIGNAL b_bar: STD_LOGIC_VECTOR(size-1 DOWNTO 0);
BEGIN
carry(0)<=add_sub;
cout<=add_sub XOR carry(size);
G0: FOR i IN size-1 DOWNTO 0 GENERATE --create the complete circuit
b_bar(i)<=b(i) XOR carry(0);
adder_subtractor_array: full_adder PORT MAP(a=>a(i), b=>b_bar(i), carry_in=>carry(i), carry_out=>carry(i+1), sum=>sum(i));
END GENERATE G0;
END structural; | mit | 1ef36fe2716ce06d1010adf34d4cb818 | 0.639781 | 3.6575 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/madd.vhd | 1 | 5,821 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: madd - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
-- calculates a*b+c
entity madd is -- latency = mul core latency + 1 if add incl
generic (
MUL_LATENCY : integer := 3;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
INCLUDE_ADD : boolean := false;
C_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
c : in std_logic_vector(C_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end madd;
architecture Behavioral of madd is
constant INT_BITWIDTH : integer := A_BITWIDTH+B_BITWIDTH+1;
type data_delay_type is array(0 to MUL_LATENCY-1) of std_logic_vector(C_BITWIDTH-1 downto 0);
function sext(val : std_logic_vector; length : integer) return std_logic_vector is
variable val_msb : std_logic;
variable result : std_logic_vector(length-1 downto 0);
begin
val_msb := val(val'length-1);
result(val'length-1 downto 0) := val;
result(length-1 downto val'length) := (others => val_msb);
return result;
end sext;
component mul
port (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(A_BITWIDTH-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(B_BITWIDTH DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(A_BITWIDTH+B_BITWIDTH-1 DOWNTO 0)
);
end component;
component addorsub is
generic (
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
signal tmp_pout : std_logic_vector(A_BITWIDTH+B_BITWIDTH-1 downto 0);
signal pout : std_logic_vector(INT_BITWIDTH-1 downto 0);
signal summand_1 : signed(INT_BITWIDTH-1 downto 0);
signal summand_2 : signed(INT_BITWIDTH-1 downto 0);
signal sum_reg : signed(INT_BITWIDTH-1 downto 0);
signal delay_line : std_logic_vector(0 to MUL_LATENCY+1-1);
signal data_delay_line : data_delay_type;
begin
-- compensate mul latency
delay_line_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
delay_line <= (others => '0');
else
delay_line(0) <= nd;
delay_line(1 to MUL_LATENCY+1-1) <= delay_line(0 to MUL_LATENCY+1-2);
end if;
end if;
end process delay_line_proc;
G_N_ADD : if INCLUDE_ADD = false generate
mul_inst : mul
port map (
clk => clk,
a => a,
b => b,
p => tmp_pout
);
pout <= sext(tmp_pout,INT_BITWIDTH);
res <= pout(INT_BITWIDTH-1 downto INT_BITWIDTH-RES_BITWIDTH);
rdy <= delay_line(MUL_LATENCY-1);
end generate G_N_ADD;
G_ADD : if INCLUDE_ADD = true generate
mul_inst : mul
port map (
clk => clk,
a => a,
b => b,
p => tmp_pout
);
data_delay_proc : process(clk)
begin
if rising_edge(clk) then
data_delay_line(0) <= c;
data_delay_line(1 to MUL_LATENCY-1) <= data_delay_line(0 to MUL_LATENCY-2);
end if;
end process data_delay_proc;
summand_1 <= signed(sext(data_delay_line(MUL_LATENCY-1),INT_BITWIDTH));
summand_2 <= signed(sext(tmp_pout,INT_BITWIDTH));
sum_reg_proc : process(clk)
begin
if rising_edge(clk) then
sum_reg <= summand_1 + summand_2;
end if;
end process sum_reg_proc;
-- addorsub_inst : addorsub
-- generic map(
-- A_BITWIDTH => A_BITWIDTH+B_BITWIDTH,
-- B_BITWIDTH => C_BITWIDTH,
-- RES_BITWIDTH => INT_BITWIDTH
-- )
-- port map (
-- clk => clk,
-- sclr => sclr,
-- nd => delay_line(MUL_LATENCY-1),
-- sub => '0',
-- a => tmp_pout,
-- b => data_delay_line(MUL_LATENCY-1),
-- res => pout,
-- rdy => rdy
-- );
--
res <= std_logic_vector(sum_reg(INT_BITWIDTH-1 downto INT_BITWIDTH-RES_BITWIDTH));
rdy <= delay_line(MUL_LATENCY+1-1);
end generate G_ADD;
end Behavioral;
| bsd-3-clause | 09d960c5159f48bead43d16912a50f06 | 0.507301 | 3.976093 | false | false | false | false |
kb3gtn/mojo_modulator | vhdl/src/mojo_top.vhd | 1 | 11,849 | -------------------------------------------------------------------------------
-- Mojo_Top.vhd
--
-- This file is the top level of heirarchy for the mojo_modulator design.
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity mojo_top is
port (
i_clk50m : in std_logic; -- 50 MHZ XO on board
i_rst_n : in std_logic; -- Reset line on board
---------------------------------------
-- RS232 TTL lines comming from a USB <-> TTL SERIAL converter
o_serial_tx : out STD_LOGIC; -- 3rd pin up from uC outside.
i_serial_rx : in STD_LOGIC; -- 4th pin up from uC outside.
-- LEDS -------------------------------
o_led : out STD_LOGIC_VECTOR(7 downto 0 );
---------------------------------------
-- DAC Interface
-- Dac Interface
o_dac_pin_mode : out STD_LOGIC; -- select between pin mode and spi mode
o_dac_sleep : out STD_LOGIC; -- places dac in to sleep when '1'
o_dac_mode : out STD_LOGIC; -- 2's comp samples or offset binary
o_dac_cmode : out STD_LOGIC; -- clock mode (diff vs single ended)
o_dac_clk_p : out STD_LOGIC; -- differential clock (cmos)
o_dac_clk_n : out STD_LOGIC; -- inverted version of clk_p
o_dac_DB : out signed( 11 downto 0 ) -- sample data bits (12b dac)
);
end entity mojo_top;
architecture system of mojo_top is
----------------------------------
-- Components used in this level
----------------------------------
-- command interface
component command_interface is
port (
i_clk : in std_logic; -- databus clock
i_srst : in std_logic; -- sync reset to clock provided
-- Serial Interface ------------------------------------------
i_rx_serial_stream : in std_logic; -- received TTL rs232 stream
o_tx_serial_stream : out std_logic; -- transmit TTL rs232 stream
-- data bus interface to slave devices -----------------------
o_db_addr : out std_logic_vector( 6 downto 0); -- address bus (7 bits)
o_db_wdata : out std_logic_vector( 7 downto 0); -- write data
i_db_rdata : in std_logic_vector( 7 downto 0); -- read data
o_db_rstrb : out std_logic; -- db_read_strobe
o_db_wstrb : out std_logic -- db_write_strobe
);
end component command_interface;
-- component that allows us to set the LEDs from a the databus
component led_display is
generic (
led_reg_addr : integer := 0 -- address for the led display module to use
);
port (
i_clk : in std_logic;
i_srst : in std_logic;
-- Databus signals ------------------
i_db_addr : in std_logic_vector(6 downto 0);
i_db_wdata : in std_logic_vector(7 downto 0);
o_db_rdata : out std_logic_vector(7 downto 0);
i_db_rstrb : in std_logic;
i_db_wstrb : in std_logic;
-- LED output -----------------------
o_led : out std_logic_vector(7 downto 0)
);
end component;
-- Dynamic clock management title
-- use to generate a 100 MHz clock from the 50 MHz XO
-- 100 MHz clock is used for the DAC DSP.
component dcm_core
port (
-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
component mojo_modulator is
generic (
ftw_reg0_addr : integer := 8; -- address in memory of this register
ftw_reg1_addr : integer := 9; -- "
ftw_reg2_addr : integer := 10; -- "
ftw_reg3_addr : integer := 11 -- "
);
port (
-- Databus Clock & reset ---------------------------------
i_clk_db : in std_logic; -- data bus clock
i_srst_db : in std_logic; -- reset for databus clk
-- Databus signals ---------------------------------------
i_db_addr : in std_logic_vector(6 downto 0);
i_db_wdata : in std_logic_vector(7 downto 0);
o_db_rdata : out std_logic_vector(7 downto 0);
i_db_rstrb : in std_logic;
i_db_wstrb : in std_logic;
-- DSP Sample Clocks & Reset -----------------------------
i_clk_dsp : in std_logic; -- dsp sample rate clock (>= db_clk)
i_srst_dsp : in std_logic; -- reset
---DSP Samples Out ---------------------------------------
o_dac_samples : out signed(15 downto 0)
);
end component mojo_modulator;
----------------------------------
-- Signal for this level
----------------------------------
signal db_addr : std_logic_vector(6 downto 0);
signal db_wdata : std_logic_vector(7 downto 0);
signal db_rdata : std_logic_vector(7 downto 0);
signal db_rstrb : std_logic;
signal db_wstrb : std_logic;
-- reset timer
signal reset_timer : unsigned( 15 downto 0 );
signal clk_50 : std_logic; -- input 50 MHz clock after clock buffer
signal srst_50 : std_logic; -- 50 MHz sync reset, active high..
-- DCM clock signals
signal clk_120m : std_logic; -- 100 Mhz clock before global buffer.
signal clk_120 : std_logic; -- 100 MHz clock
signal clk_120n : std_logic; -- inverted clock
signal dac_clk : std_logic;
signal clk_120_locked : std_logic; -- clock 100 is locked. (for srst_120)
signal clk_120_dcm_rst : std_logic; -- reset for dcm
signal srst_120 : std_logic; -- sync reset for 100 MHz clock domain (active high)
-- dac samples (from modulator)
signal dac_sample : signed(15 downto 0); -- gets scaled to 12 bits ..
begin
clk_120n <= not clk_120;
-- IO Interface and clocking stuff here.....
-- IBUFG: Single-ended global clock input buffer for 50 MHz clk
-- Spartan-6
IBUFG_inst : IBUFG
generic map (
IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => clk_50, -- Clock buffer output
I => i_clk50m -- Clock buffer input (connect directly to top-level port)
);
-- End of IBUFG_inst instantiation
-- clocking for dac
-- single ended to differental IO driver block.. (Xilinx)
OBUF_inst : OBUF
generic map (
DRIVE => 4,
IOSTANDARD => "DEFAULT",
SLEW => "FAST"
)
port map (
O => o_dac_clk_p, -- P clk pin
I => clk_120n -- input clock
);
-- generate synchronious reset signal for
-- synchronious blocks
rst_sync : process( clk_50 )
begin
if ( rising_edge(clk_50) ) then
if ( i_rst_n = '0' ) then
-- reset active
srst_50 <= '1'; -- 50 MHz clk domain in reset
srst_120 <= '1'; -- 100 MHZ clk domain in reset
clk_120_dcm_rst <= '1'; -- dcm in reset at startup
-- timer to hold design in reset untill clocks are good.
-- for simulation hot wire this to 0xFFFF to by pass timer.
reset_timer <= x"FFFF";
-- normal case.
--reset_timer <= (others=>'0');
else
-- reset timer expires
if ( reset_timer = x"FFFF" ) then
srst_50 <= '0'; -- 50 MHZ reset will now de-assert..
clk_120_dcm_rst <= '0'; -- start PLL, XO is stable..
-- wait for PLL lock before releasing 100 MHz reset.
if ( clk_120_locked = '1' ) then
srst_120 <= '0'; -- start design up
end if;
else
-- reset time is not expired..
reset_timer <= reset_timer + 1;
end if;
end if;
end if;
end process;
-- DCM PLL for 100 MHz clock generation
u_clk_pll : dcm_core
port map (
-- Clock in ports
CLK_IN1 => clk_50,
-- Clock out ports
CLK_OUT1 => clk_120,
-- Status and control signals
RESET => clk_120_dcm_rst,
LOCKED => clk_120_locked
);
-- high level system blocks here...............
-- command interface
u_ci : command_interface
port map (
i_clk => clk_50, -- clock used for uart and databus transactions
i_srst => srst_50, -- reset sync to this clock
-- Serial Interface ------------------------------------------
i_rx_serial_stream => i_serial_rx,
o_tx_serial_stream => o_serial_tx,
-- data bus interface to slave devices -----------------------
o_db_addr => db_addr,
o_db_wdata => db_wdata,
i_db_rdata => db_rdata,
o_db_rstrb => db_rstrb,
o_db_wstrb => db_wstrb
);
-- block that controls the LED on the board
-- great for testing memory map control..
u_led_display : led_display
port map (
i_clk => clk_50,
i_srst => srst_50,
-- Databus signals ------------------
i_db_addr => db_addr,
i_db_wdata => db_wdata,
o_db_rdata => db_rdata,
i_db_rstrb => db_rstrb,
i_db_wstrb => db_wstrb,
-- LED output -----------------------
o_led => o_led
);
u_mojo_modulator : mojo_modulator
generic map(
ftw_reg0_addr => 8, -- address in memory of this register
ftw_reg1_addr => 9, -- "
ftw_reg2_addr => 10, -- "
ftw_reg3_addr => 11 -- "
)
port map (
-- Databus Clock & reset ---------------------------------
i_clk_db => clk_50,
i_srst_db => srst_50,
-- Databus signals ---------------------------------------
i_db_addr => db_addr,
i_db_wdata => db_wdata,
o_db_rdata => db_rdata,
i_db_rstrb => db_rstrb,
i_db_wstrb => db_wstrb,
-- DSP Sample Clocks & Reset -----------------------------
i_clk_dsp => clk_120,
i_srst_dsp => srst_120,
---DSP Samples Out ---------------------------------------
o_dac_samples => dac_sample
);
-- dac setup
o_dac_pin_mode <= '1'; -- place dac in pin mode..
o_dac_sleep <= '0'; -- dac not sleeping
o_dac_mode <= '1'; -- 2's complement samples
o_dac_cmode <= '0'; -- use single ended clocking
--o_dac_clk_p <= '0';
o_dac_clk_n <= '0'; -- not used, tie low.
o_dac_DB <= dac_sample(15 downto 4); -- scale down to top most 12 bits.
end architecture system;
| apache-2.0 | 7b115e0488630077686e05dfe39775e4 | 0.454638 | 4.204755 | false | false | false | false |
RickvanLoo/Synthesizer | note_2_pa.vhd | 1 | 2,102 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY NOTE_2_PA IS
GENERIC(lut_bit_width : integer := 8;
pa_bit_width : integer := 32
);
PORT ( CLK : in std_logic;
RESET : in std_logic;
ENABLE : in std_logic;
NOTE_ON : in std_logic_vector(7 downto 0); --Note ON/OFF 0x80(off), 0xFF(on);
PA_word : OUT unsigned(pa_bit_width-1 downto 0)
);
END NOTE_2_PA;
architecture behav of NOTE_2_PA is
type pa_lut is array (0 to 127) of integer;
constant pa_index:pa_lut:=(0,1209463,1281381,1357576,1438302,1523828,1614439,1710439,1812147,1919903,2034066,2155018,2283162,2418926,2562762,2715152,2876604,3047655,3228878,3420877,3624293,3839805,4068132,4310035,4566323,4837851,5125525,5430304,5753207,6095311,6457757,6841755,7248587,7679610,8136263,8620071,9132647,9675702,10251050,10860609,11506414,12190621,12915513,13683509,14497173,15359220,16272527,17240142,18265294,19351405,20502099,21721217,23012828,24381242,25831026,27367019,28994347,30718440,32545054,34480283,36530588,38702809,41004198,43442435,46025656,48762484,51662052,54734038,57988693,61436880,65090107,68960566,73061175,77405619,82008396,86884869,92051312,97524968,103324105,109468076,115977386,122873760,130180214,137921133,146122350,154811237,164016792,173769738,184102625,195049936,206648209,218936151,231954772,245747521,260360429,275842266,292244700,309622474,328033585,347539477,368205249,390099873,413296419,437872302,463909545,491495042,520720858,551684531,584489400,619244949,656067170,695078954,736410499,780199746,826592837,875744605,927819089,982990083,1041441715,1103369062,1168978801,1238489898,1312134339,1390157907,1472820998,1560399492,1653185674,1751489210);
begin
PROCESS(clk,reset)
variable lutindex : integer;
BEGIN
if reset = '0' then
PA_word <= (others => '0');
elsif rising_edge(clk) then
if enable = '1' then
lutindex := to_integer(unsigned(NOTE_ON));
PA_word <= to_unsigned(pa_index(lutindex), pa_bit_width);
else
PA_word <= to_unsigned(pa_index(0), pa_bit_width);
end if;
end if;
END PROCESS;
end behav; | mit | 39ba76cd92516cd99bd335a8a0fd6f31 | 0.772122 | 2.591862 | false | false | false | false |
kb3gtn/mojo_modulator | vhdl/src/led_display.vhd | 1 | 2,565 | -------------------------------------------------------------------------------
-- LED Display
--
-- This module is a simple module that has 1 register
-- that defines the state of the 8 leds on the board.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity led_display is
generic (
led_reg_addr : integer := 0 -- address for the led display module to use
);
port (
i_clk : in std_logic;
i_srst : in std_logic;
-- Databus signals ------------------
i_db_addr : in std_logic_vector(6 downto 0);
i_db_wdata : in std_logic_vector(7 downto 0);
o_db_rdata : out std_logic_vector(7 downto 0);
i_db_rstrb : in std_logic;
i_db_wstrb : in std_logic;
-- LED output -----------------------
o_led : out std_logic_vector(7 downto 0)
);
end entity led_display;
architecture system of led_display is
-- signals
signal led_reg : std_logic_vector(7 downto 0);
signal led_reg_addr_stl : std_logic_vector( 6 downto 0);
begin
-- output tie to local signal register.
o_led <= led_reg;
led_reg_addr_stl <= std_logic_vector(to_unsigned(led_reg_addr, 7));
-- update led_reg depending on databus activity.
u_db_slave : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' ) then
-- reset state
led_reg <= (others=>'0');
else
-- write have priority over reads here..
if ( i_db_wstrb = '1' ) then
if ( i_db_addr = led_reg_addr_stl ) then
led_reg <= i_db_wdata;
end if;
else
if ( i_db_rstrb = '1' ) then
if ( i_db_addr = led_reg_addr_stl ) then
o_db_rdata <= led_reg;
else
o_db_rdata <= (others=>'Z'); -- we are not address, don't drive bus..
end if;
else
-- do not drive shared rdata line if we are not addressed to output anything
o_db_rdata <= (others=>'Z');
end if; -- end db_rstrb
end if; -- end db_wstrb
end if; -- end not in reset
end if;
end process;
end architecture;
| apache-2.0 | 1670b2d995294df60b319dd66583cbdf | 0.444834 | 4.170732 | false | false | false | false |
esar/hdmilight-v2 | fpga/formatDetector.vhd | 1 | 11,298 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2014 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity formatDetector is
Port (
clk : in std_logic;
ce2 : in std_logic;
hblank : in std_logic;
vblank : in std_logic;
dataenable : in std_logic;
r : in std_logic_vector(7 downto 0);
g : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
cfgclk : in std_logic;
threshold : in std_logic_vector(7 downto 0);
xSize : out std_logic_vector(11 downto 0);
xPreActive : out std_logic_vector(11 downto 0);
xPostActive : out std_logic_vector(11 downto 0);
ySize : out std_logic_vector(10 downto 0);
yPreActive : out std_logic_vector(10 downto 0);
yPostActive : out std_logic_vector(10 downto 0);
formatChanged : out std_logic
);
end formatDetector;
architecture Behavioral of formatDetector is
signal xSizeReg : std_logic_vector(11 downto 0);
signal xPreActiveReg : std_logic_vector(11 downto 0);
signal xPostActiveReg : std_logic_vector(11 downto 0);
signal ySizeReg : std_logic_vector(10 downto 0);
signal yPreActiveReg : std_logic_vector(10 downto 0);
signal yPostActiveReg : std_logic_vector(10 downto 0);
signal xCount : std_logic_vector(11 downto 0);
signal xPreActiveCount : std_logic_vector(11 downto 0);
signal xPostActiveCount : std_logic_vector(11 downto 0);
signal xTotalPreActiveCount : std_logic_vector(11 downto 0);
signal xTotalPostActiveCount : std_logic_vector(11 downto 0);
signal yCount : std_logic_vector(10 downto 0);
signal yPreActiveCount : std_logic_vector(10 downto 0);
signal yPostActiveCount : std_logic_vector(10 downto 0);
signal xStepCount : std_logic_vector(5 downto 0);
signal xTotalR : std_logic_vector(17 downto 0);
signal xTotalG : std_logic_vector(17 downto 0);
signal xTotalB : std_logic_vector(17 downto 0);
signal xTotal : std_logic_vector(19 downto 0);
signal yStepCount : std_logic_vector(4 downto 0);
signal lastvblank : std_logic;
signal lasthblank : std_logic;
signal lastdataenable : std_logic;
signal startOfFrame : std_logic;
signal endOfFrame : std_logic;
signal startOfLine : std_logic;
signal endOfLine : std_logic;
signal vblankCfgClk : std_logic_vector(1 downto 0);
signal lastvblankCfgClk : std_logic;
signal endOfFrameCfgClk : std_logic;
signal xSizeCfgClk : std_logic_vector(11 downto 0);
signal xPreActiveCfgClk : std_logic_vector(11 downto 0);
signal xPostActiveCfgClk : std_logic_vector(11 downto 0);
signal ySizeCfgClk : std_logic_vector(10 downto 0);
signal yPreActiveCfgClk : std_logic_vector(10 downto 0);
signal yPostActiveCfgClk : std_logic_vector(10 downto 0);
signal xSizeCfgClkPrev : std_logic_vector(11 downto 0);
signal xPreActiveCfgClkPrev : std_logic_vector(11 downto 0);
signal xPostActiveCfgClkPrev : std_logic_vector(11 downto 0);
signal ySizeCfgClkPrev : std_logic_vector(10 downto 0);
signal yPreActiveCfgClkPrev : std_logic_vector(10 downto 0);
signal yPostActiveCfgClkPrev : std_logic_vector(10 downto 0);
signal gotFirstActiveColumn : std_logic;
signal gotFirstActiveLine : std_logic;
signal pixelIsBelowThreshold : std_logic;
signal lineIsBelowThreshold : std_logic;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(ce2 = '1' and vblank = '0') then
startOfLine <= '0';
endOfLine <= '0';
if(dataenable = '1' and lastdataenable = '0') then
startOfLine <= '1';
elsif(dataenable = '0' and lastdataenable = '1') then
endOfLine <= '1';
end if;
lastdataenable <= dataenable;
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
if(ce2 = '1') then
startOfFrame <= '0';
endOfFrame <= '0';
if(vblank = '0' and lastvblank = '1') then
startOfFrame <= '1';
elsif(vblank = '1' and lastvblank = '0') then
endOfFrame <= '1';
end if;
lastvblank <= vblank;
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
if(ce2 = '1') then
if(startOfLine = '1') then
xPreActiveCount <= (others => '0');
gotFirstActiveColumn <= '0';
elsif(pixelIsBelowThreshold = '0') then
gotFirstActiveColumn <= '1';
elsif(gotFirstActiveColumn = '0') then
xPreActiveCount <= std_logic_vector(unsigned(xPreActiveCount) + 1);
end if;
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
if(ce2 = '1') then
if(startOfLine = '1' or pixelIsBelowThreshold = '0') then
xPostActiveCount <= (others => '0');
else
xPostActiveCount <= std_logic_vector(unsigned(xPostActiveCount) + 1);
end if;
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
if(ce2 = '1') then
if(startOfFrame = '1') then
xTotalPreActiveCount <= (others => '1');
elsif(endOfLine = '1' and
unsigned(xPreActiveCount) < unsigned(xTotalPreActiveCount) and
unsigned(yCount) > unsigned(ySizeReg(10 downto 2))) then
xTotalPreActiveCount <= xPreActiveCount;
end if;
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
if(ce2 = '1') then
if(startOfFrame = '1') then
xTotalPostActiveCount <= (others => '1');
elsif(endOfLine = '1' and
unsigned(xPostActiveCount) < unsigned(xTotalPostActiveCount) and
unsigned(yCount) < unsigned(ySizeReg(10 downto 2))) then
xTotalPostActiveCount <= xPostActiveCount;
end if;
end if;
end if;
end process;
-- counter to for 1/64th of the horizontal resolution
process(clk)
begin
if(rising_edge(clk)) then
if(ce2 = '1') then
if(startOfLine = '1' or unsigned(xStepCount) = 0) then
xStepCount <= xSizeReg(11 downto 6);
else
xStepCount <= std_logic_vector(unsigned(xStepCount) - 1);
end if;
end if;
end if;
end process;
-- sum together 64 pixels spread evenly across the line
process(clk)
begin
if(rising_edge(clk)) then
if(ce2 = '1') then
if(startOfLine = '1') then
xTotalR <= (others => '0');
xTotalG <= (others => '0');
xTotalB <= (others => '0');
elsif(unsigned(xStepCount) = 0) then
xTotalR <= std_logic_vector(unsigned(xTotalR) + unsigned(r));
xTotalG <= std_logic_vector(unsigned(xTotalG) + unsigned(g));
xTotalB <= std_logic_vector(unsigned(xTotalB) + unsigned(b));
end if;
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
if(ce2 = '1') then
-- note: 2 times G so we can average with a divide by 4
xTotal <= std_logic_vector(unsigned("00" & xTotalR) + unsigned("0" & xTotalG & "0") + unsigned("00" & xTotalB));
end if;
end if;
end process;
-- at the end of the line, increment the bar height if the average of the
-- 64 samples are below the threshold
process(clk)
begin
if(rising_edge(clk)) then
if(ce2 = '1') then
if(startOfFrame = '1') then
yPreActiveCount <= (others => '0');
gotFirstActiveLine <= '0';
elsif(endOfLine = '1') then
if(lineIsBelowThreshold = '0') then
gotFirstActiveLine <= '1';
elsif(gotFirstActiveLine = '0') then
yPreActiveCount <= std_logic_vector(unsigned(yPreActiveCount) + 1);
end if;
end if;
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
if(ce2 = '1') then
if(startOfFrame = '1') then
yPostActiveCount <= (others => '0');
elsif(endOfLine = '1') then
if(lineIsBelowThreshold = '0') then
yPostActiveCount <= (others => '0');
else
yPostActiveCount <= std_logic_vector(unsigned(yPostActiveCount) + 1);
end if;
end if;
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
if(ce2 = '1') then
if(startOfLine = '1') then
xCount <= (others => '0');
elsif(dataenable = '1') then
xCount <= std_logic_vector(unsigned(xCount) + 1);
end if;
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
if(ce2 = '1') then
if(startOfFrame = '1') then
yCount <= (others => '0');
elsif(endOfLine = '1') then
yCount <= std_logic_vector(unsigned(yCount) + 1);
end if;
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
if(ce2 = '1') then
if(endOfFrame = '1') then
xSizeReg <= xCount;
xPreActiveReg <= xTotalPreActiveCount;
xPostActiveReg <= xTotalPostActiveCount;
ySizeReg <= yCount;
yPreActiveReg <= yPreActiveCount;
yPostActiveReg <= yPostActiveCount;
end if;
end if;
end if;
end process;
process(cfgclk)
begin
if(rising_edge(cfgclk)) then
vblankCfgClk <= vblankCfgClk(0) & vblank;
end if;
end process;
process(cfgclk)
begin
if(rising_edge(cfgclk)) then
endOfFrameCfgClk <= '0';
if(vblankCfgClk(1) = '1' and lastvblankCfgClk = '0') then
endOfFrameCfgClk <= '1';
end if;
lastvblankCfgClk <= vblankCfgClk(1);
end if;
end process;
process(cfgclk)
begin
if(rising_edge(cfgclk)) then
formatChanged <= '0';
if(endOfFrameCfgClk = '1') then
xSizeCfgClkPrev <= xSizeCfgClk;
xPreActiveCfgClkPrev <= xPreActiveCfgClk;
xPostActiveCfgClkPrev <= xPostActiveCfgClk;
ySizeCfgClkPrev <= ySizeCfgClk;
yPreActiveCfgClkPrev <= yPreActiveCfgClk;
yPostActiveCfgClkPrev <= yPostActiveCfgClk;
xSizeCfgClk <= xSizeReg;
xPreActiveCfgClk <= xPreActiveReg;
xPostActiveCfgClk <= xPostActiveReg;
ySizeCfgClk <= ySizeReg;
yPreActiveCfgClk <= yPreActiveReg;
yPostActiveCfgClk <= yPostActiveReg;
if(xSizeCfgClkPrev /= xSizeCfgClk or
xPreActiveCfgClkPrev /= xPreActiveCfgClk or
xPostActiveCfgClkPrev /= xPostActiveCfgClk or
ySizeCfgClkPrev /= ySizeCfgClk or
yPreActiveCfgClkPrev /= yPreActiveCfgClk or
yPostActiveCfgClkPrev /= yPostActiveCfgClk) then
formatChanged <= '1';
end if;
end if;
end if;
end process;
xSize <= xSizeCfgClk(10 downto 0) & "0";
xPreActive <= xPreActiveCfgClk(10 downto 0) & "0";
xPostActive <= xPostActiveCfgClk(10 downto 0) & "0";
ySize <= ySizeCfgClk;
yPreActive <= yPreActiveCfgClk;
yPostActive <= yPostActiveCfgClk;
pixelIsBelowThreshold <= '1' when (unsigned(r) < unsigned(threshold)) and
(unsigned(g) < unsigned(threshold)) and
(unsigned(b) < unsigned(threshold)) else '0';
lineIsBelowthreshold <= '1' when unsigned(xTotal(19 downto 6)) < unsigned(threshold) else '0';
end Behavioral;
| gpl-2.0 | 5787868aae84d4fabf670477f0c8ba41 | 0.663657 | 3.296761 | false | false | false | false |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/soc_system_inst.vhd | 1 | 20,813 | component soc_system is
port (
adc_ltc2308_0_conduit_end_adc_convst : out std_logic; -- adc_convst
adc_ltc2308_0_conduit_end_adc_sck : out std_logic; -- adc_sck
adc_ltc2308_0_conduit_end_adc_sdi : out std_logic; -- adc_sdi
adc_ltc2308_0_conduit_end_adc_sdo : in std_logic := 'X'; -- adc_sdo
clk_clk : in std_logic := 'X'; -- clk
hps_0_f2h_cold_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_f2h_debug_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_f2h_stm_hw_events_stm_hwevents : in std_logic_vector(27 downto 0) := (others => 'X'); -- stm_hwevents
hps_0_f2h_warm_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_h2f_reset_reset_n : out std_logic; -- reset_n
hps_0_hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_0_hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_0_hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_0_hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_0_hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_0_hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_0_hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_0_hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_0_hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_0_hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_0_hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_0_hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_0_hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_0_hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_0_hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_0_hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_0_hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_0_hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_0_hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_0_hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_0_hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_0_hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_0_hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_0_hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_0_hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_0_hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_0_hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_0_hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_0_hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_0_hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_0_hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_0_hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_0_hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_0_hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_0_hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_0_hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_0_hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA
hps_0_hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL
hps_0_hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_0_hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
hps_0_hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09
hps_0_hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35
hps_0_hps_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40
hps_0_hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_0_hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hps_0_hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61
leds_pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
pll_0_locked_export : out std_logic; -- export
pll_0_outclk2_clk : out std_logic; -- clk
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component soc_system;
u0 : component soc_system
port map (
adc_ltc2308_0_conduit_end_adc_convst => CONNECTED_TO_adc_ltc2308_0_conduit_end_adc_convst, -- adc_ltc2308_0_conduit_end.adc_convst
adc_ltc2308_0_conduit_end_adc_sck => CONNECTED_TO_adc_ltc2308_0_conduit_end_adc_sck, -- .adc_sck
adc_ltc2308_0_conduit_end_adc_sdi => CONNECTED_TO_adc_ltc2308_0_conduit_end_adc_sdi, -- .adc_sdi
adc_ltc2308_0_conduit_end_adc_sdo => CONNECTED_TO_adc_ltc2308_0_conduit_end_adc_sdo, -- .adc_sdo
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
hps_0_f2h_cold_reset_req_reset_n => CONNECTED_TO_hps_0_f2h_cold_reset_req_reset_n, -- hps_0_f2h_cold_reset_req.reset_n
hps_0_f2h_debug_reset_req_reset_n => CONNECTED_TO_hps_0_f2h_debug_reset_req_reset_n, -- hps_0_f2h_debug_reset_req.reset_n
hps_0_f2h_stm_hw_events_stm_hwevents => CONNECTED_TO_hps_0_f2h_stm_hw_events_stm_hwevents, -- hps_0_f2h_stm_hw_events.stm_hwevents
hps_0_f2h_warm_reset_req_reset_n => CONNECTED_TO_hps_0_f2h_warm_reset_req_reset_n, -- hps_0_f2h_warm_reset_req.reset_n
hps_0_h2f_reset_reset_n => CONNECTED_TO_hps_0_h2f_reset_reset_n, -- hps_0_h2f_reset.reset_n
hps_0_hps_io_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TX_CLK, -- hps_0_hps_io.hps_io_emac1_inst_TX_CLK
hps_0_hps_io_hps_io_emac1_inst_TXD0 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
hps_0_hps_io_hps_io_emac1_inst_TXD1 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
hps_0_hps_io_hps_io_emac1_inst_TXD2 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
hps_0_hps_io_hps_io_emac1_inst_TXD3 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
hps_0_hps_io_hps_io_emac1_inst_RXD0 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
hps_0_hps_io_hps_io_emac1_inst_MDIO => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
hps_0_hps_io_hps_io_emac1_inst_MDC => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
hps_0_hps_io_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
hps_0_hps_io_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
hps_0_hps_io_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_0_hps_io_hps_io_emac1_inst_RXD1 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
hps_0_hps_io_hps_io_emac1_inst_RXD2 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
hps_0_hps_io_hps_io_emac1_inst_RXD3 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
hps_0_hps_io_hps_io_sdio_inst_CMD => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
hps_0_hps_io_hps_io_sdio_inst_D0 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
hps_0_hps_io_hps_io_sdio_inst_D1 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
hps_0_hps_io_hps_io_sdio_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
hps_0_hps_io_hps_io_sdio_inst_D2 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
hps_0_hps_io_hps_io_sdio_inst_D3 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D0 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
hps_0_hps_io_hps_io_usb1_inst_D1 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
hps_0_hps_io_hps_io_usb1_inst_D2 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
hps_0_hps_io_hps_io_usb1_inst_D3 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D4 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
hps_0_hps_io_hps_io_usb1_inst_D5 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
hps_0_hps_io_hps_io_usb1_inst_D6 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
hps_0_hps_io_hps_io_usb1_inst_D7 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
hps_0_hps_io_hps_io_usb1_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
hps_0_hps_io_hps_io_usb1_inst_STP => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
hps_0_hps_io_hps_io_usb1_inst_DIR => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
hps_0_hps_io_hps_io_usb1_inst_NXT => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
hps_0_hps_io_hps_io_spim1_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_CLK, -- .hps_io_spim1_inst_CLK
hps_0_hps_io_hps_io_spim1_inst_MOSI => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_MOSI, -- .hps_io_spim1_inst_MOSI
hps_0_hps_io_hps_io_spim1_inst_MISO => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_MISO, -- .hps_io_spim1_inst_MISO
hps_0_hps_io_hps_io_spim1_inst_SS0 => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_SS0, -- .hps_io_spim1_inst_SS0
hps_0_hps_io_hps_io_uart0_inst_RX => CONNECTED_TO_hps_0_hps_io_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
hps_0_hps_io_hps_io_uart0_inst_TX => CONNECTED_TO_hps_0_hps_io_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
hps_0_hps_io_hps_io_i2c0_inst_SDA => CONNECTED_TO_hps_0_hps_io_hps_io_i2c0_inst_SDA, -- .hps_io_i2c0_inst_SDA
hps_0_hps_io_hps_io_i2c0_inst_SCL => CONNECTED_TO_hps_0_hps_io_hps_io_i2c0_inst_SCL, -- .hps_io_i2c0_inst_SCL
hps_0_hps_io_hps_io_i2c1_inst_SDA => CONNECTED_TO_hps_0_hps_io_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
hps_0_hps_io_hps_io_i2c1_inst_SCL => CONNECTED_TO_hps_0_hps_io_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
hps_0_hps_io_hps_io_gpio_inst_GPIO09 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO09, -- .hps_io_gpio_inst_GPIO09
hps_0_hps_io_hps_io_gpio_inst_GPIO35 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO35, -- .hps_io_gpio_inst_GPIO35
hps_0_hps_io_hps_io_gpio_inst_GPIO40 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO40, -- .hps_io_gpio_inst_GPIO40
hps_0_hps_io_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53
hps_0_hps_io_hps_io_gpio_inst_GPIO54 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO54, -- .hps_io_gpio_inst_GPIO54
hps_0_hps_io_hps_io_gpio_inst_GPIO61 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO61, -- .hps_io_gpio_inst_GPIO61
leds_pio_0_external_connection_export => CONNECTED_TO_leds_pio_0_external_connection_export, -- leds_pio_0_external_connection.export
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
pll_0_locked_export => CONNECTED_TO_pll_0_locked_export, -- pll_0_locked.export
pll_0_outclk2_clk => CONNECTED_TO_pll_0_outclk2_clk, -- pll_0_outclk2.clk
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
);
| gpl-3.0 | ef212b4176e0d401afe920cdb1ff48fd | 0.452938 | 2.980951 | false | false | false | false |
esar/hdmilight-v2 | fpga/colourTransformer.vhd | 1 | 4,406 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2014 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity colourTransformer is
Port (
clk : in std_logic;
start : in std_logic;
done : out std_logic;
coefIndex : in std_logic_vector(3 downto 0);
coefAddr : out std_logic_vector(8 downto 0);
coefData : in std_logic_vector(63 downto 0);
Rin : in std_logic_vector(7 downto 0);
Gin : in std_logic_vector(7 downto 0);
Bin : in std_logic_vector(7 downto 0);
Rout : out std_logic_vector(7 downto 0);
Gout : out std_logic_vector(7 downto 0);
Bout : out std_logic_vector(7 downto 0)
);
end colourTransformer;
architecture Behavioral of colourTransformer is
signal count : std_logic_vector(1 downto 0);
signal Xin : std_logic_vector(7 downto 0);
signal Rcoef : std_logic_vector(17 downto 0);
signal Gcoef : std_logic_vector(17 downto 0);
signal Bcoef : std_logic_vector(17 downto 0);
signal Radd : std_logic_vector(35 downto 0);
signal Gadd : std_logic_vector(35 downto 0);
signal Badd : std_logic_vector(35 downto 0);
signal Rprod : std_logic_vector(35 downto 0);
signal Gprod : std_logic_vector(35 downto 0);
signal Bprod : std_logic_vector(35 downto 0);
signal Sshift : std_logic_vector(5 downto 0);
begin
-- create done signal by delaying the start signal by 6 clocks
process(clk)
begin
if(rising_edge(clk)) then
Sshift <= Sshift(4 Downto 0) & start;
done <= Sshift(5);
end if;
end process;
-- counter to control matrix multiply stages
process(clk)
begin
if(rising_edge(clk)) then
if(start = '1') then
count <= "00";
else
count <= std_logic_vector(unsigned(count) + 1);
end if;
end if;
end process;
-- select multiply input for each stage: R, G, B, Constant
process(clk)
begin
if(rising_edge(clk)) then
case count is
when "00" => Xin <= Rin;
when "01" => Xin <= Gin;
when "10" => Xin <= Bin;
when "11" => Xin <= "00000001";
when others => Xin <= "00000000";
end case;
end if;
end process;
-- select adder input: zero for first stage, accumulate for remaining stages
Radd <= (others => '0') when count = "01" else Rprod;
Gadd <= (others => '0') when count = "01" else Gprod;
Badd <= (others => '0') when count = "01" else Bprod;
-- get the coefficients
--
-- Rr Gr Br
-- Rg Gg Bg
-- Rb Gb Bb
-- Rx Gx Bx
coefAddr <= "000" & coefIndex & count;
Rcoef <= coefData(17 downto 0);
Gcoef <= coefData(35 downto 18);
Bcoef <= coefData(53 downto 36);
-- multiply/accumulate
process(clk)
begin
if(rising_edge(clk)) then
Rprod <= std_logic_vector(signed("0" & Xin & "000000000") * signed(Rcoef) + signed(Radd));
Gprod <= std_logic_vector(signed("0" & Xin & "000000000") * signed(Gcoef) + signed(Gadd));
Bprod <= std_logic_vector(signed("0" & Xin & "000000000") * signed(Bcoef) + signed(Badd));
end if;
end process;
-- clamp and deliver
process(clk)
begin
if(rising_edge(clk)) then
if(count = "01") then
if(Rprod(35 downto 26) = "0000000000") then
Rout <= Rprod(25 downto 18);
elsif(Rprod(35) = '1') then
Rout <= (others => '0');
else
Rout <= (others => '1');
end if;
if(Gprod(35 downto 26) = "0000000000") then
Gout <= Gprod(25 downto 18);
elsif(Rprod(35) = '1') then
Gout <= (others => '0');
else
Gout <= (others => '1');
end if;
if(Bprod(35 downto 26) = "0000000000") then
Bout <= Bprod(25 downto 18);
elsif(Bprod(35) = '1') then
Bout <= (others => '0');
else
Bout <= (others => '1');
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 5d03e7ec52b0a4dec7b45457216aba27 | 0.635497 | 3.12704 | false | false | false | false |
tsotnep/vhdl_soc_audio_mixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/adau1761_audio_v1_00_a/hdl/vhdl/ClkDividerN.vhd | 3 | 739 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ClkDividerN is
generic(divFactor : positive);
port(reset : in std_logic;
clkIn : in std_logic;
clkOut : out std_logic);
end ClkDividerN;
architecture Behavioral of ClkDividerN is
signal s_divCounter : natural;
begin
process(reset, clkIn)
begin
if (reset = '1') then
clkOut <= '0';
s_divCounter <= 0;
elsif (rising_edge(clkIn)) then
if (s_divCounter = divFactor - 1) then
clkOut <= '0';
s_divCounter <= 0;
else
if (s_divCounter = (divFactor / 2 - 1)) then
clkOut <= '1';
end if;
s_divCounter <= s_divCounter + 1;
end if;
end if;
end process;
end Behavioral;
| mit | 1c2de65bb89e1945b01de682be3aea12 | 0.608931 | 3.105042 | false | false | false | false |
tsotnep/vhdl_soc_audio_mixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/user_logic.vhd | 3 | 17,875 | ------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Copyright 2011(c) Analog Devices, Inc.
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- [email protected] (c) Analog Devices Inc.
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library axi_spdif_tx_v1_00_a;
use axi_spdif_tx_v1_00_a.tx_package.all;
entity user_logic is
generic
(
C_NUM_REG : integer := 8;
C_SLV_DWIDTH : integer := 32
);
port
(
--SPDIF interface
spdif_data_clk : in std_logic;
spdif_tx_o : out std_logic;
spdif_tx_int_o : out std_logic;
--AXI Lite interface
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
--AXI streaming interface
S_AXIS_ACLK : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of S_AXIS_ACLK : signal is "CLK";
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg2 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg3 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg4 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg5 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg6 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg7 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(7 downto 0);
signal slv_reg_read_sel : std_logic_vector(7 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
------------------------------------------
-- SPDIF signals
------------------------------------------
constant USER_DATA_BUF : integer := 0;
constant CH_STAT_BUF : integer := 0;
constant RAM_ADDR_WIDTH : integer := 7;
signal config_reg : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal chstatus_reg : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal chstat_freq : std_logic_vector(1 downto 0);
signal chstat_gstat, chstat_preem, chstat_copy, chstat_audio : std_logic;
signal mem_rd, mem_rd_d1, ch_status_wr, user_data_wr : std_logic;
signal sample_data: std_logic_vector(15 downto 0);
signal conf_mode : std_logic_vector(3 downto 0);
signal conf_ratio : std_logic_vector(7 downto 0);
signal conf_udaten, conf_chsten : std_logic_vector(1 downto 0);
signal conf_tinten, conf_txdata, conf_txen : std_logic;
signal user_data_a, user_data_b : std_logic_vector(191 downto 0);
signal ch_stat_a, ch_stat_b : std_logic_vector(191 downto 0);
signal channel : std_logic;
------------------------------------------
-- Audio samples FIFO
------------------------------------------
type RAM_TYPE is array (0 to (2**RAM_ADDR_WIDTH - 1)) of std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal audio_fifo : RAM_TYPE;
signal audio_fifo_wr_addr : std_logic_vector(RAM_ADDR_WIDTH - 1 downto 0);
signal audio_fifo_rd_addr : std_logic_vector(RAM_ADDR_WIDTH - 1 downto 0);
signal audio_fifo_full : std_logic;
begin
-- Audio samples FIFO management
S_AXIS_TREADY <= '1' when audio_fifo_full = '0' else '0';
AUDIO_FIFO_PROCESS : process (S_AXIS_ACLK) is
variable audio_fifo_free_cnt : integer range 0 to 2**RAM_ADDR_WIDTH;
begin
if S_AXIS_ACLK'event and S_AXIS_ACLK = '1' then
if Bus2IP_Resetn = '0' or conf_txdata = '0' then
audio_fifo_wr_addr <= (others => '0');
audio_fifo_rd_addr <= (others => '0');
audio_fifo_free_cnt := 2**RAM_ADDR_WIDTH;
audio_fifo_full <= '0';
mem_rd_d1 <= '0';
else
mem_rd_d1 <= mem_rd;
if ((S_AXIS_TVALID = '1') and (audio_fifo_free_cnt > 0)) then
audio_fifo(conv_integer(audio_fifo_wr_addr)) <= S_AXIS_TDATA;
audio_fifo_wr_addr <= audio_fifo_wr_addr + '1';
audio_fifo_free_cnt := audio_fifo_free_cnt - 1;
end if;
if((channel = '1') and (mem_rd_d1 = '1' and mem_rd = '0') and (audio_fifo_free_cnt < (2**RAM_ADDR_WIDTH)))then
audio_fifo_rd_addr <= audio_fifo_rd_addr + '1';
audio_fifo_free_cnt := audio_fifo_free_cnt + 1;
end if;
if(audio_fifo_free_cnt = 0)then
audio_fifo_full <= '1';
else
audio_fifo_full <= '0';
end if;
if(channel = '1') then
sample_data(15 downto 0) <= audio_fifo(conv_integer(audio_fifo_rd_addr))(31 downto 16);
else
sample_data(15 downto 0) <= audio_fifo(conv_integer(audio_fifo_rd_addr))(15 downto 0);
end if;
end if;
end if;
end process AUDIO_FIFO_PROCESS;
-- SPDIF registers update
config_reg <= slv_reg0;
chstatus_reg <= slv_reg1;
-- Configuration signals update
conf_mode(3 downto 0) <= config_reg(23 downto 20);
conf_ratio(7 downto 0) <= config_reg(15 downto 8);
UD: if USER_DATA_BUF = 1 generate
conf_udaten(1 downto 0) <= config_reg(7 downto 6);
end generate UD;
NUD: if USER_DATA_BUF = 0 generate
conf_udaten(1 downto 0) <= "00";
end generate NUD;
CS: if CH_STAT_BUF = 1 generate
conf_chsten(1 downto 0) <= config_reg(5 downto 4);
end generate CS;
NCS: if CH_STAT_BUF = 0 generate
conf_chsten(1 downto 0) <= "00";
end generate NCS;
conf_tinten <= config_reg(2);
conf_txdata <= config_reg(1);
conf_txen <= config_reg(0);
-- Channel status signals update
chstat_freq(1 downto 0) <= chstatus_reg(7 downto 6);
chstat_gstat <= chstatus_reg(3);
chstat_preem <= chstatus_reg(2);
chstat_copy <= chstatus_reg(1);
chstat_audio <= chstatus_reg(0);
-- User data/ch. status register write strobes
user_data_wr <= '0';--'1' when Bus2IP_WrCE(0) = '1' and
--conv_integer(Bus2IP_Addr(14 downto 10)) > 31 and
--conv_integer(Bus2IP_Addr(14 downto 10)) < 56 else '0';
ch_status_wr <= '0'; --'1' when Bus2IP_WrCE(0) = '1' and
--conv_integer(Bus2IP_Addr(14 downto 10)) > 63 and
--conv_integer(Bus2IP_Addr(14 downto 10)) < 88 else '0';
-- UserData - byte buffer
UDB: tx_bitbuf
generic map (ENABLE_BUFFER => USER_DATA_BUF)
port map (
up_clk => Bus2IP_Clk,
up_rstn => Bus2IP_Resetn,
buf_wr => user_data_wr,
up_addr => Bus2IP_Data(20 downto 16),
up_wdata => Bus2IP_Data(15 downto 0),
buf_data_a => user_data_a,
buf_data_b => user_data_b);
-- ChStat - byte buffer
CSB: tx_bitbuf
generic map (ENABLE_BUFFER => CH_STAT_BUF)
port map (
up_clk => Bus2IP_Clk,
up_rstn => Bus2IP_Resetn,
buf_wr => ch_status_wr,
up_addr => Bus2IP_Data(20 downto 16),
up_wdata => Bus2IP_Data(15 downto 0),
buf_data_a => ch_stat_a,
buf_data_b => ch_stat_b);
-- Transmit encoder
TENC: tx_encoder
generic map (DATA_WIDTH => 16)
port map (
up_clk => Bus2IP_Clk,
data_clk => spdif_data_clk, -- data clock
resetn => Bus2IP_Resetn, -- resetn
conf_mode => conf_mode, -- sample format
conf_ratio => conf_ratio, -- clock divider
conf_udaten => conf_udaten, -- user data control
conf_chsten => conf_chsten, -- ch. status control
conf_txdata => conf_txdata, -- sample data enable
conf_txen => conf_txen, -- spdif signal enable
user_data_a => user_data_a, -- ch. a user data
user_data_b => user_data_b, -- ch. b user data
ch_stat_a => ch_stat_a, -- ch. a status
ch_stat_b => ch_stat_b, -- ch. b status
chstat_freq => chstat_freq, -- sample freq.
chstat_gstat => chstat_gstat, -- generation status
chstat_preem => chstat_preem, -- preemphasis status
chstat_copy => chstat_copy, -- copyright bit
chstat_audio => chstat_audio, -- data format
sample_data => sample_data, -- audio data
mem_rd => mem_rd, -- sample buffer read
channel => channel, -- which channel should be read
spdif_tx_o => spdif_tx_o); -- SPDIF output signal
-- Interrupt generation
spdif_tx_int_o <= '0';
-- internal registers access logic
slv_reg_write_sel <= Bus2IP_WrCE(7 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(7 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
case slv_reg_write_sel is
when "10000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7 ) is
begin
case slv_reg_read_sel is
when "10000000" => slv_ip2bus_data <= slv_reg0;
when "01000000" => slv_ip2bus_data <= slv_reg1;
when "00100000" => slv_ip2bus_data <= slv_reg2;
when "00010000" => slv_ip2bus_data <= slv_reg3;
when "00001000" => slv_ip2bus_data <= slv_reg4;
when "00000100" => slv_ip2bus_data <= slv_reg5;
when "00000010" => slv_ip2bus_data <= slv_reg6;
when "00000001" => slv_ip2bus_data <= slv_reg7;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| mit | 638c624e43c9966f85dc5b386ecbb05d | 0.526266 | 3.636826 | false | false | false | false |
whitef0x0/EECE353-Lab4 | datapath_challenge.vhd | 1 | 3,333 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.ALL;
ENTITY datapath_challenge IS
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
initx, inity, loady, loadx, initl, drawl : IN STD_LOGIC;
x : OUT STD_LOGIC_VECTOR(7 downto 0); -- x0
y : OUT STD_LOGIC_VECTOR(6 downto 0);
xin : IN STD_LOGIC_VECTOR(7 downto 0); -- x1
yin : IN STD_LOGIC_VECTOR(6 downto 0);
initLoad: IN STD_LOGIC;
ledr: OUT STD_LOGIC_VECTOR(17 downto 0);
xdone, ydone, ldone : OUT STD_LOGIC
);
END entity;
ARCHITECTURE mixed OF datapath_challenge IS
SIGNAL x_old : unsigned(7 downto 0);
SIGNAL y_old : unsigned(6 downto 0);
BEGIN
PROCESS(clock, resetb)
VARIABLE x_tmp : unsigned(7 downto 0) := "00000000";
VARIABLE y_tmp : unsigned(6 downto 0) := "0000000";
VARIABLE dx : signed(8 downto 0);
VARIABLE dy : signed(7 downto 0);
VARIABLE x0 : unsigned(7 downto 0) := "01010000"; -- 80
VARIABLE y0 : unsigned(6 downto 0) := "0111100"; -- 60
VARIABLE x1 : unsigned(7 downto 0) := "01010000";
VARIABLE y1 : unsigned(6 downto 0) := "0111100";
VARIABLE sx : signed(1 downto 0);
VARIABLE sy : signed(1 downto 0);
VARIABLE err : signed(8 downto 0);
VARIABLE e2 : signed(9 downto 0);
BEGIN
IF (resetb = '0') THEN
y_tmp := "0000000";
x_tmp := "00000000";
x0 := "01010000"; -- 80
y0 := "0111100"; -- 60
x1 := "01010000"; -- 80
y1 := "0111100"; -- 60
ELSIF rising_edge(clock) THEN
--initialize line if flag is set
IF (initl = '1') THEN
if(initLoad = '1') THEN
x0 := x1; -- 80
y0 := y1; -- 60
ELSE
x0 := x_old;
y0 := y_old;
LEDR(17 downto 11) <= std_logic_vector(y_old);
END IF;
x1 := unsigned(xin); -- destination point
x_old <= x1;
y1 := unsigned(yin); -- destination point
y_old <= y1;
LEDR(9 downto 3) <= std_logic_vector(y1);
dx := to_signed(abs(to_integer(x1) - to_integer(x0)), 9);
dy := to_signed(abs(to_integer(y1) - to_integer(y0)), 8);
IF (x0 < x1) THEN
sx := to_signed(1, 2);
ELSE
sx := to_signed(-1, 2);
END IF;
IF (y0 < y1) THEN
sy := to_signed(1, 2);
ELSE
sy := to_signed(-1, 2);
END IF;
err := to_signed(to_integer(dx) - to_integer(dy), 9);
ldone <= '0';
--Draw line if flag is set
ELSIF (drawl = '1') THEN
X <= STD_LOGIC_VECTOR(x0);
Y <= STD_LOGIC_VECTOR(y0);
IF ((x0 = x1) and (y0 = y1)) THEN
ldone <= '1';
ELSE
e2 := signed(2*err)(9 downto 0);
IF (e2 > -dy) THEN
err := err - dy;
x0 := unsigned(signed(x0) + sx);
END IF;
IF (e2 < dx) THEN
err := err + dx;
y0 := unsigned(signed(y0) + sy);
END IF;
END IF;
-- Screen clearing logic
ELSE
IF (INITY = '1') THEN
y_tmp := "0000000";
ELSIF (LOADY = '1') THEN
y_tmp := y_tmp + 1;
END IF;
IF (y_tmp = 119) THEN
YDONE <= '1';
ELSE
YDONE <= '0';
END IF;
Y <= std_logic_vector(y_tmp);
IF (INITX = '1') THEN
x_tmp := "00000000";
ELSIF (LOADX = '1') THEN
x_tmp := x_tmp + 1;
END IF;
IF (x_tmp = 159) THEN
XDONE <= '1';
ELSE
XDONE <= '0';
END IF;
X <= std_logic_vector(x_tmp);
END IF;
END IF;
END PROCESS;
END mixed;
| mit | 695c945ac90a10343a91f6b92c481219 | 0.547855 | 2.770574 | false | false | false | false |
Nooxet/embedded_bruteforce | vhdl/md5_mux.vhd | 3 | 1,870 | ----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: md5_mux - Behavioral
-- Description:
-- A mux to select which hash to compare
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- include the hash_array type --
use work.hash_array_pkg.all;
entity md5_mux is
generic (
N : integer
);
port (
clk : in std_logic;
rstn : in std_logic;
i_hash_0 : in unsigned(127 downto 0); --hash_array(N-1 downto 0);
i_hash_1 : in unsigned(127 downto 0); --hash_array(N-1 downto 0);
i_select : in unsigned(N-1 downto 0); -- should be ceil(log2(N-1))
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end md5_mux;
architecture Behavioral of md5_mux is
begin
clk_proc : process(clk)
begin
if rising_edge(clk) then
if rstn = '0' then
o_hash_0 <= (others => '0');
o_hash_1 <= (others => '0');
o_hash_2 <= (others => '0');
o_hash_3 <= (others => '0');
else
o_hash_0 <= (others => '0');
o_hash_1 <= (others => '0');
o_hash_2 <= (others => '0');
o_hash_3 <= (others => '0');
--o_hash <= i_hash(to_integer(unsigned(i_select)));
if i_select = "00" then
o_hash_0 <= i_hash_0(127 downto 96);
o_hash_1 <= i_hash_0(95 downto 64);
o_hash_2 <= i_hash_0(63 downto 32);
o_hash_3 <= i_hash_0(31 downto 0);
elsif i_select = "01" then
o_hash_0 <= i_hash_1(127 downto 96);
o_hash_1 <= i_hash_1(95 downto 64);
o_hash_2 <= i_hash_1(63 downto 32);
o_hash_3 <= i_hash_1(31 downto 0);
end if;
end if;
end if;
end process;
end Behavioral;
| mit | f8899d3fa826a7d5726160193572a628 | 0.513904 | 2.921875 | false | false | false | false |
esar/hdmilight-v2 | fpga/uart_rx.vhd | 2 | 3,895 | library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------------------
-- UART Receiver ------------------------------------------------------------
entity uart_rx is
generic (
fullbit : integer );
port (
clk : in std_logic;
reset : in std_logic;
--
dout : out std_logic_vector(7 downto 0);
avail : out std_logic;
error : out std_logic;
clear : in std_logic;
--
rxd : in std_logic );
end uart_rx;
-----------------------------------------------------------------------------
-- Implemenattion -----------------------------------------------------------
architecture rtl of uart_rx is
constant halfbit : integer := fullbit / 2;
-- Signals
signal bitcount : integer range 0 to 10;
signal count : integer range 0 to FULLBIT;
signal shiftreg : std_logic_vector(7 downto 0);
signal rxd2 : std_logic;
begin
proc: process(clk, reset) is
begin
if reset='1' then
bitcount <= 0;
count <= 0;
error <= '0';
avail <= '0';
elsif clk'event and clk='1' then
if clear='1' then
error <= '0';
avail <= '0';
end if;
if count/=0 then
count <= count - 1;
else
if bitcount=0 then -- wait for startbit
if rxd2='0' then -- FOUND
count <= HALFBIT;
bitcount <= bitcount + 1;
end if;
elsif bitcount=1 then -- sample mid of startbit
if rxd2='0' then -- OK
count <= FULLBIT;
bitcount <= bitcount + 1;
shiftreg <= "00000000";
else -- ERROR
error <= '1';
bitcount <= 0;
end if;
elsif bitcount=10 then -- stopbit
if rxd2='1' then -- OK
count <= 0;
bitcount <= 0;
dout <= shiftreg;
avail <= '1';
else -- ERROR
count <= FULLBIT;
bitcount <= 0;
error <= '1';
end if;
else
shiftreg(6 downto 0) <= shiftreg(7 downto 1);
shiftreg(7) <= rxd2;
count <= FULLBIT;
bitcount <= bitcount + 1;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Sync incoming RXD (anti metastable) --------------------------------------
syncproc: process(reset, clk) is
begin
if reset='1' then
rxd2 <= '1';
elsif clk'event and clk='1' then
rxd2 <= rxd;
end if;
end process;
end rtl; | gpl-2.0 | 8d18804d3a56da8f2c6726d05739ed2c | 0.282927 | 6.282258 | false | false | false | false |
autosub-team/autosub | src/tests/testTasksVHDL/testsubmissions/crc/fsr_beh.vhdl | 2 | 879 | library IEEE;
use IEEE.std_logic_1164.all;
architecture behavior of fsr is
constant gen_degree : integer := 8;
begin
process(EN,RST,CLK)
constant top_bit: integer := gen_degree-1;
variable content: std_logic_vector(gen_degree-1 downto 0);
variable do_inv: std_logic;
begin
if(EN='1') then
if(RST='1') then
content:= (others=>'0');
elsif(rising_edge(CLK)) then
do_inv:= content(top_bit) xor DATA_IN;
content(7) := content(6);
content(6) := content(5) xor do_inv;
content(5) := content(4);
content(4) := content(3);
content(3) := content(2);
content(2) := content(1);
content(1) := content(0) xor do_inv;
content(0) := do_inv;
end if;
DATA <= content;
end if;
end process;
end behavior;
| gpl-2.0 | 2d58c7f5517ccb42993673fa6f1abd8d | 0.538111 | 3.474308 | false | false | false | false |
UdayanSinha/Code_Blocks | VHDL/Projects/work/tb_adder_subtractor_generic.vhd | 1 | 1,421 | -- A-B=A+B'+1
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY tb_add_subb IS END tb_add_subb;
ARCHITECTURE test OF tb_add_subb IS
CONSTANT size : INTEGER:=4; --4-bit adder subtractor
COMPONENT add_subb
GENERIC(size: INTEGER);
PORT(a, b: IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); --std_logic_vector defines array of 8 elements with indexed from 0 to 7; can use bit_vector as well
add_sub: IN STD_LOGIC;
cout: OUT STD_LOGIC;
sum: OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0));
END COMPONENT;
SIGNAL a, b, sum: STD_LOGIC_VECTOR(size-1 DOWNTO 0);
SIGNAL add_sub, cout: STD_LOGIC;
BEGIN
T1:add_subb GENERIC MAP (size) PORT MAP (a, b, add_sub, cout, sum);
a <="0000",
"1111" AFTER 10 ns,
"1001" AFTER 20 ns,
"1010" AFTER 30 ns,
"1011" AFTER 40 ns,
"1100" AFTER 50 ns,
"1101" AFTER 60 ns,
"1110" AFTER 70 ns,
"0001" AFTER 80 ns;
b <="0000",
"0111" AFTER 10 ns,
"0001" AFTER 20 ns,
"0010" AFTER 30 ns,
"0011" AFTER 40 ns,
"0100" AFTER 50 ns,
"0101" AFTER 60 ns,
"0110" AFTER 70 ns,
"0111" AFTER 80 ns;
add_sub <= '0',
'1' AFTER 50 ns;
END test; | mit | 779ae0ae98c7355dacbc5c18e019c65f | 0.585503 | 3.399522 | false | false | false | false |
freecores/gpib_controller | vhdl/test/gpib_PP_Test.vhd | 1 | 13,797 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 23:21:05 10/21/2011
-- Design Name:
-- Module Name: /windows/h/projekty/elektronika/USB_to_HPIB/usbToHpib/test_scr//gpibInterfaceTest.vhd
-- Project Name: usbToHpib
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: gpibInterface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.gpibComponents.all;
use work.helperComponents.all;
ENTITY gpib_PP_Test IS
END gpib_PP_Test;
ARCHITECTURE behavior OF gpib_PP_Test IS
-- Component Declaration for the Unit Under Test (UUT)
component gpibCableEmulator is port (
-- interface signals
DIO_1 : in std_logic_vector (7 downto 0);
output_valid_1 : in std_logic;
DIO_2 : in std_logic_vector (7 downto 0);
output_valid_2 : in std_logic;
DIO : out std_logic_vector (7 downto 0);
-- attention
ATN_1 : in std_logic;
ATN_2 : in std_logic;
ATN : out std_logic;
-- data valid
DAV_1 : in std_logic;
DAV_2 : in std_logic;
DAV : out std_logic;
-- not ready for data
NRFD_1 : in std_logic;
NRFD_2 : in std_logic;
NRFD : out std_logic;
-- no data accepted
NDAC_1 : in std_logic;
NDAC_2 : in std_logic;
NDAC : out std_logic;
-- end or identify
EOI_1 : in std_logic;
EOI_2 : in std_logic;
EOI : out std_logic;
-- service request
SRQ_1 : in std_logic;
SRQ_2 : in std_logic;
SRQ : out std_logic;
-- interface clear
IFC_1 : in std_logic;
IFC_2 : in std_logic;
IFC : out std_logic;
-- remote enable
REN_1 : in std_logic;
REN_2 : in std_logic;
REN : out std_logic
);
end component;
-- inputs common
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal T1 : std_logic_vector(7 downto 0) := "00000100";
-- inputs 1
signal data_1 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_1 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_1 : std_logic := '0';
signal nba_1 : std_logic := '0';
signal ltn_1 : std_logic := '0';
signal lun_1 : std_logic := '0';
signal lon_1 : std_logic := '0';
signal ton_1 : std_logic := '0';
signal endOf_1 : std_logic := '0';
signal gts_1 : std_logic := '0';
signal rpp_1 : std_logic := '0';
signal tcs_1 : std_logic := '0';
signal tca_1 : std_logic := '0';
signal sic_1 : std_logic := '0';
signal rsc_1 : std_logic := '0';
signal sre_1 : std_logic := '0';
signal rtl_1 : std_logic := '0';
signal rsv_1 : std_logic := '0';
signal ist_1 : std_logic := '0';
signal lpe_1 : std_logic := '0';
-- inputs 2
signal lpeUsed_2 : std_logic := '0';
signal data_2 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_2 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_2 : std_logic := '0';
signal nba_2 : std_logic := '0';
signal ltn_2 : std_logic := '0';
signal lun_2 : std_logic := '0';
signal lon_2 : std_logic := '0';
signal ton_2 : std_logic := '0';
signal endOf_2 : std_logic := '0';
signal gts_2 : std_logic := '0';
signal rpp_2 : std_logic := '0';
signal tcs_2 : std_logic := '0';
signal tca_2 : std_logic := '0';
signal sic_2 : std_logic := '0';
signal rsc_2 : std_logic := '0';
signal sre_2 : std_logic := '0';
signal rtl_2 : std_logic := '0';
signal rsv_2 : std_logic := '0';
signal ist_2 : std_logic := '0';
signal lpe_2 : std_logic := '0';
-- outputs 1
signal dvd_1 : std_logic;
signal wnc_1 : std_logic;
signal tac_1 : std_logic;
signal cwrc_1 : std_logic;
signal cwrd_1 : std_logic;
signal clr_1 : std_logic;
signal trg_1 : std_logic;
signal atl_1 : std_logic;
signal att_1 : std_logic;
signal mla_1 : std_logic;
signal lsb_1 : std_logic;
signal spa_1 : std_logic;
signal ppr_1 : std_logic;
signal sreq_1 : std_logic;
signal isLocal_1 : std_logic;
signal currentSecAddr_1 : std_logic_vector (4 downto 0);
-- outputs 2
signal dvd_2 : std_logic;
signal wnc_2 : std_logic;
signal tac_2 : std_logic;
signal cwrc_2 : std_logic;
signal cwrd_2 : std_logic;
signal clr_2 : std_logic;
signal trg_2 : std_logic;
signal atl_2 : std_logic;
signal att_2 : std_logic;
signal mla_2 : std_logic;
signal lsb_2 : std_logic;
signal spa_2 : std_logic;
signal ppr_2 : std_logic;
signal sreq_2 : std_logic;
signal isLocal_2 : std_logic;
signal currentSecAddr_2 : std_logic_vector (4 downto 0);
-- common
signal DO : std_logic_vector (7 downto 0);
signal DI_1 : std_logic_vector (7 downto 0);
signal output_valid_1 : std_logic;
signal DI_2 : std_logic_vector (7 downto 0);
signal output_valid_2 : std_logic;
signal ATN_1, ATN_2, ATN : std_logic;
signal DAV_1, DAV_2, DAV : std_logic;
signal NRFD_1, NRFD_2, NRFD : std_logic;
signal NDAC_1, NDAC_2, NDAC : std_logic;
signal EOI_1, EOI_2, EOI : std_logic;
signal SRQ_1, SRQ_2, SRQ : std_logic;
signal IFC_1, IFC_2, IFC : std_logic;
signal REN_1, REN_2, REN : std_logic;
-- gpib reader
signal buf_interrupt : std_logic;
signal data_available : std_logic;
signal last_byte_addr : std_logic_vector (3 downto 0);
signal end_of_stream : std_logic;
signal byte_addr : std_logic_vector (3 downto 0);
signal data_out : std_logic_vector (7 downto 0);
signal reset_buffer : std_logic := '0';
signal dataSecAddr : std_logic_vector (4 downto 0);
-- gpib writer
signal w_last_byte_addr : std_logic_vector (3 downto 0)
:= (others => '0');
signal w_end_of_stream : std_logic := '0';
signal w_data_available : std_logic := '0';
signal w_buf_interrupt : std_logic;
signal w_data_in : std_logic_vector (7 downto 0);
signal w_byte_addr : std_logic_vector (3 downto 0);
signal w_reset_buffer : std_logic := '0';
type WR_BUF_TYPE is
array (0 to 15) of std_logic_vector (7 downto 0);
signal w_write_buffer : WR_BUF_TYPE;
-- Clock period definitions
constant clk_period : time := 2ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
gpib1: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00001",
myTalkAddr => "00001",
secAddrMask => (others => '0'),
data => data_1,
status_byte => status_byte_1,
T1 => T1,
rdy => rdy_1,
nba => nba_1,
ltn => ltn_1,
lun => lun_1,
lon => lon_1,
ton => ton_1,
endOf => endOf_1,
gts => gts_1,
rpp => rpp_1,
tcs => tcs_1,
tca => tca_1,
sic => sic_1,
rsc => rsc_1,
sre => sre_1,
rtl => rtl_1,
rsv => rsv_1,
ist => ist_1,
lpe => lpe_1,
dvd => dvd_1,
wnc => wnc_1,
tac => tac_1,
cwrc => cwrc_1,
cwrd => cwrd_1,
clr => clr_1,
trg => trg_1,
atl => atl_1,
att => att_1,
mla => mla_1,
lsb => lsb_1,
spa => spa_1,
ppr => ppr_1,
sreq => sreq_1,
isLocal => isLocal_1,
currentSecAddr => currentSecAddr_1,
DI => DO,
DO => DI_1,
output_valid => output_valid_1,
ATN_in => ATN,
ATN_out => ATN_1,
DAV_in => DAV,
DAV_out => DAV_1,
NRFD_in => NRFD,
NRFD_out => NRFD_1,
NDAC_in => NDAC,
NDAC_out => NDAC_1,
EOI_in => EOI,
EOI_out => EOI_1,
SRQ_in => SRQ,
SRQ_out => SRQ_1,
IFC_in => IFC,
IFC_out => IFC_1,
REN_in => REN,
REN_out => REN_1
);
-- Instantiate the Unit Under Test (UUT)
gpib2: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => lpeUsed_2,
fixedPpLine => "001",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00010",
myTalkAddr => "00010",
secAddrMask => (others => '0'),
data => data_2,
status_byte => status_byte_2,
T1 => T1,
rdy => rdy_2,
nba => nba_2,
ltn => ltn_2,
lun => lun_2,
lon => lon_2,
ton => ton_2,
endOf => endOf_2,
gts => gts_2,
rpp => rpp_2,
tcs => tcs_2,
tca => tca_2,
sic => sic_2,
rsc => rsc_2,
sre => sre_2,
rtl => rtl_2,
rsv => rsv_2,
ist => ist_2,
lpe => lpe_2,
dvd => dvd_2,
wnc => wnc_2,
tac => tac_2,
cwrc => cwrc_2,
cwrd => cwrd_2,
clr => clr_2,
trg => trg_2,
atl => atl_2,
att => att_2,
mla => mla_2,
lsb => lsb_2,
spa => spa_2,
ppr => ppr_2,
sreq => sreq_2,
isLocal => isLocal_2,
currentSecAddr => currentSecAddr_2,
DI => DO,
DO => DI_2,
output_valid => output_valid_2,
ATN_in => ATN,
ATN_out => ATN_2,
DAV_in => DAV,
DAV_out => DAV_2,
NRFD_in => NRFD,
NRFD_out => NRFD_2,
NDAC_in => NDAC,
NDAC_out => NDAC_2,
EOI_in => EOI,
EOI_out => EOI_2,
SRQ_in => SRQ,
SRQ_out => SRQ_2,
IFC_in => IFC,
IFC_out => IFC_2,
REN_in => REN,
REN_out => REN_2
);
ce: gpibCableEmulator port map (
-- interface signals
DIO_1 => DI_1,
output_valid_1 => output_valid_1,
DIO_2 => DI_2,
output_valid_2 => output_valid_2,
DIO => DO,
-- attention
ATN_1 => ATN_1, ATN_2 => ATN_2, ATN => ATN,
DAV_1 => DAV_1, DAV_2 => DAV_2, DAV => DAV,
NRFD_1 => NRFD_1, NRFD_2 => NRFD_2, NRFD => NRFD,
NDAC_1 => NDAC_1, NDAC_2 => NDAC_2, NDAC => NDAC,
EOI_1 => EOI_1, EOI_2 => EOI_2, EOI => EOI,
SRQ_1 => SRQ_1, SRQ_2 => SRQ_2, SRQ => SRQ,
IFC_1 => IFC_1, IFC_2 => IFC_2, IFC => IFC,
REN_1 => REN_1, REN_2 => REN_2, REN => REN
);
gr: gpibReader generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_in => DO, dvd => dvd_2, atl => atl_2, lsb => lsb_2, rdy => rdy_2,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isLE => '0', secAddr => (others => '0'), dataSecAddr => dataSecAddr,
buf_interrupt => buf_interrupt, data_available => data_available,
last_byte_addr => last_byte_addr, end_of_stream => end_of_stream,
byte_addr => byte_addr, data_out => data_out,
reset_buffer => reset_buffer
);
w_data_in <= w_write_buffer(conv_integer(w_byte_addr));
gw: gpibWriter generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_out => data_1, wnc => wnc_1, spa => spa_1, nba => nba_1,
endOf => endOf_1, att => att_1, cwrc => cwrc_1,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isTE => '0', secAddr => (others => '0'), dataSecAddr => (others => '0'),
last_byte_addr => w_last_byte_addr, end_of_stream => w_end_of_stream,
data_available => w_data_available, buf_interrupt => w_buf_interrupt,
data_in => w_data_in, byte_addr => w_byte_addr,
reset_buffer => w_reset_buffer
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 10 clock periods.
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*10;
-- requests system control
rsc_1 <= '1';
-- interface clear
sic_1 <= '1';
wait until IFC_1 = '1';
sic_1 <= '0';
wait until IFC_1 = '0';
-- gpib2 to listen
w_write_buffer(0) <= "00100010";
-- gpib1 to talk
w_write_buffer(1) <= "01000001";
-- PP configure
w_write_buffer(2) <= "00000101";
-- PP enable line no. 3
w_write_buffer(3) <= "01101011";
w_last_byte_addr <= "0011";
w_end_of_stream <= '1';
w_data_available <= '1';
wait until w_buf_interrupt = '1';
ist_2 <= '1';
rpp_1 <= '1';
wait until ppr_1 = '1';
assert DO = "00001000";
rpp_1 <= '0';
wait until cwrc_1 = '1';
w_reset_buffer <= '1';
wait for clk_period*1;
w_reset_buffer <= '0';
wait for clk_period*1;
-- PP disable
w_write_buffer(0) <= "01110000";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt = '1';
lpeUsed_2 <= '1';
lpe_2 <= '1';
rpp_1 <= '1';
wait until ppr_1 = '1';
assert DO = "00000010";
report "$$$ END OF TEST - parallel poll $$$";
wait;
end process;
END;
| gpl-3.0 | 9e2f2545f47367cf14bd1f95cb27276e | 0.559904 | 2.880376 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/ISE/controller_sg_pp_md_comp/tb_brutus_dual.vhd | 1 | 2,837 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:48:46 10/15/2014
-- Design Name:
-- Module Name: C:/Users/ael10jso/Xilinx/embedded_bruteforce/brutus_system/ISE/controller_sg_pp_md_comp/tb_brutus_dual.vhd
-- Project Name: controller_sg_pp_md_comp
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: brutus_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_brutus_dual IS
END tb_brutus_dual;
ARCHITECTURE behavior OF tb_brutus_dual IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT brutus_top
PORT(
clk : IN std_logic;
rstn : IN std_logic;
i_fsl_data_recv : IN std_logic;
i_fsl_hash : IN std_logic_vector(127 downto 0);
o_pw_found : OUT std_logic;
o_passwd : OUT std_logic_vector(47 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rstn : std_logic := '0';
signal i_fsl_data_recv : std_logic := '0';
signal i_fsl_hash : std_logic_vector(127 downto 0) := (others => '0');
--Outputs
signal o_pw_found : std_logic;
signal o_passwd : std_logic_vector(47 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: brutus_top PORT MAP (
clk => clk,
rstn => rstn,
i_fsl_data_recv => i_fsl_data_recv,
i_fsl_hash => i_fsl_hash,
o_pw_found => o_pw_found,
o_passwd => o_passwd
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
rstn <= '0';
wait for clk_period*10;
rstn <= '1';
i_fsl_hash <= x"07159c47ee1b19ae4fb9c40d480856c4"; -- "ba"
i_fsl_data_recv <= '1';
wait for clk_period;
i_fsl_data_recv <= '0';
wait;
end process;
END;
| mit | 256898eecd46e60d6894512b75ca1bda | 0.58865 | 3.54625 | false | true | false | false |
kb3gtn/mojo_modulator | vhdl/src/spi_master.vhd | 2 | 11,077 | -----------------------------------------------------------------------------
-- SPI_MASTER.vhd
--
-- This block is a SPI Master uart that is designed to interface with
-- a simple databus master address/data bus inteface.
--
-- This register exposes 3 registers
--
-- A status Register, and a data registers, Clock Rate Register
--
-- Conf register:
--
-- Bit0 - Chip Select 0 line value.. '1' -- asserted, '0' -- de-asserted
-- Bit1 - Chip Select 1 line value.. '1' -- asserted, '0' -- de-asserted
-- Bit2 - Chip Select 2 line value.. '1' -- asserted, '0' -- de-asserted
-- Bit3 - Chip Select 4 line value.. '1' -- asserted, '0' -- de-asserted
-- Bit4 - Clk Edge for data change.. '1' -- falling, '0' -- rising (clk polarity)
-- Bit5 - Data Polarity.. '1' -- Inverted, '0' -- Normal
-- Bit6 - Bit Order.. '1' -- msb first, '0' -- lsb first
-- Bit7 - Reset.. '1' asserted, '0' de-asserted ( running )
--
-- Chip selects are basically GPIO..
-- Can have multiple chip select asserted if you so desire..
--
-- Data register:
-- Bit(7 - 0) -- data byte to transmit
--
--
-- Clock Rate Register
-- This register takes a value that defines the clock rate used in SPI operations
--
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity spi_master is
generic (
-- default address for this module to use..
data_reg_addr : std_logic_vector( 6 downto 0) := "000000"; -- address 0
conf_reg_addr : std_logic_vector( 6 downto 0) := "000001"; -- address 1
baud_reg_addr : std_logic_vector( 6 downto 0) := "000010" -- address 2
);
port (
i_clk : in std_logic; -- input system clock (50 MHz)
i_srst : in std_logic; -- input sync reset to i_clk
-- spi interface
o_spi_sclk : out std_logic; -- spi clock signal
o_spi_mosi : out std_logic; -- spi master data output
i_spi_miso : in std_logic; -- spi master data input
o_spi_cs_n : out std_logic_vector( 3 downto 0); -- chip select signals. (active low)
-- data bus interface
i_db_addr : in std_logic_vector( 6 downto 0);
i_db_wr_strb : in std_logic;
i_db_rd_strb : in std_logic;
i_db_wr_data : in std_logic_vector( 7 downto 0 );
o_db_rd_data : out std_logic_vector( 7 downto 0 )
);
end entity;
architecture b of spi_master is
--##########################################
--# SIGNALS
--##########################################
signal app_rst : std_logic;
signal spi_sclk_strb : std_logic; -- clock enable strobe for sclk state change. (2 time clock period)
signal spi_bit_strb : std_logic; -- bit shift should occur..
signal spi_sclk : std_logic; -- clock normal (data change on rising edge)
signal spi_sclk_n : std_logic; -- clock inverted (data change on falling edge)
signal spi_mosi : std_logic; -- mosi normal
signal spi_mosi_n : std_logic; -- mosi inverted
signal spi_miso : std_logic; -- miso normal
signal spi_miso_n : std_logic; -- miso inverted
signal db_rd_data : std_logic_vector( 7 downto 0);
signal spi_register : std_logic_vector( 7 downto 0 ); -- spi shift register
signal chip_selects : std_logic_vector( 3 downto 0 ); -- chip select outputs (gpio)
signal spi_active : std_logic; -- spi transaction in progress
signal spi_start_strb : std_logic; -- start spi transaction strobe/flag/clock enable
signal spi_bit_cntr : integer; -- number of bits sent
signal baud_cntr : unsigned( 11 downto 0 );
signal baud_val : unsigned( 11 downto 0 );
-- memory map regsiters
signal baud_reg : std_logic_vector( 7 downto 0 );
signal conf_reg : std_logic_vector( 7 downto 0 );
signal spi_data_reg : std_logic_vector( 7 downto 0 );
begin
-- internal register to output bus
o_db_rd_data <= db_rd_data;
-- chip select outputs
o_spi_cs_n <= conf_reg( 3 downto 0 );
-- databus interface
db_slave : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' ) then
app_rst <= '0';
baud_reg <= (others=>'0');
conf_reg <= (others=>'0');
db_rd_data <= (others=>'Z');
else
-- writes over reads
if ( i_db_wr_strb = '1' ) then
-- we have a write on the bus
-- mux based on address
if ( i_db_addr = data_reg_addr ) then
spi_data_reg <= i_db_wr_data;
spi_start_strb <= '1'; -- signal we have a new byte to send..
end if;
if ( i_db_addr = baud_reg_addr ) then
baud_reg <= i_db_wr_data;
end if;
if ( i_db_addr = conf_reg_addr ) then
conf_reg <= i_db_wr_data;
end if;
-- in all cases, we are not performing a read..
-- high Z our drive on the read bus
db_rd_data <= (others=>'Z');
else
spi_start_strb <= '0';
if ( i_db_rd_strb = '1' ) then
if( i_db_addr = data_reg_addr ) then
db_rd_data <= spi_register;
end if;
if ( i_db_addr = baud_reg_addr ) then
db_rd_data <= baud_reg;
end if;
if ( i_db_addr = conf_reg_addr ) then
db_rd_data <= conf_reg;
end if;
else
db_rd_data <= (others=>'Z'); -- high Z bus
end if;
end if;
end if;
end if;
end process;
-- power of 2 scaling factor to baud value from memory mapped register
-- to internal counter limit..
baud_val <= unsigned( "00" & baud_reg & "00" ); -- multiply by 4
-- simple clock divider to get
-- bit rate for spi uart.
baud_gen : process( i_clk )
begin
if ( rising_edge(i_clk) ) then
if ( i_srst = '1' or app_rst = '1' ) then
baud_cntr <= (others=>'0');
spi_sclk_strb <= '0';
else
if ( baud_cntr = baud_val ) then
spi_sclk_strb <= '1'; -- next bit period strobe..
baud_cntr <= (others=>'0');
else
spi_sclk_strb <= '0';
baud_cntr <= baud_cntr + 1;
end if;
end if;
end if;
end process;
-- generate inverted/normal sclk as needed
o_spi_sclk <= conf_reg(4) xor spi_sclk; -- if conf_reg = '1', clock will be inverted.
-- update spi_sclk when we get a strobe.
clk_gen : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' or app_rst = '1' ) then
spi_sclk <= '0';
spi_bit_strb <= '0';
else
-- spi_active is cleared by the spi_shiftreg when it has shifted out..
-- spi_active gets set when a spi_start_strb is recevied in spi_shiftreg
-- spi_sclk_strb indicates 1/2 clock periods..
if ( spi_sclk_strb = '1' and spi_active = '1' ) then
if ( spi_sclk = '1' ) then
spi_sclk <= '0';
spi_bit_strb <= '0';
else
if ( spi_bit_cntr = 8 ) then
spi_sclk <= '0'; -- dribble clock skip..
else
spi_sclk <= '1';
end if;
spi_bit_strb <= '1'; -- next bit in shift register..
end if;
end if;
if ( spi_active = '0' ) then
spi_sclk <= '0';
end if;
if ( spi_sclk_strb = '0' ) then
spi_bit_strb <= '0';
end if;
end if;
end if;
end process;
-- SPI shift register
spi_shiftreg : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' or app_rst = '1' ) then
spi_register <= (others=>'0');
spi_bit_cntr <= 0;
spi_active <= '0';
spi_mosi <= '0';
else
if ( spi_active = '0' and spi_start_strb = '1' ) then
spi_active <= '1';
spi_register <= spi_data_reg; -- load in new contents to send
spi_bit_cntr <= 0;
else
if ( spi_bit_strb = '1' and spi_active = '1' ) then
if ( spi_bit_cntr = 8) then
spi_bit_cntr <= 0;
spi_active <= '0';
else
spi_bit_cntr <= spi_bit_cntr + 1;
if ( conf_reg(6) = '1' ) then
-- send MSB first
spi_mosi <= spi_register(7);
spi_register <= spi_register( 6 downto 0 ) & spi_miso;
else
-- send LSB first
spi_mosi <= spi_register(0);
spi_register <= spi_miso & spi_register( 7 downto 1 );
end if;
end if;
end if;
if ( spi_active = '0' ) then
spi_mosi <= '0';
end if;
end if;
end if;
end if;
end process;
-- data polarity selector
-- also performs sampling of input data line to i_clk domain
spi_pol_select : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' or app_rst = '1' ) then
o_spi_mosi <= '0';
spi_miso <= '0';
else
if ( conf_reg(5) = '1' ) then
-- use inverted data
o_spi_mosi <= not spi_mosi;
spi_miso <= not i_spi_miso;
else
-- use normal data
o_spi_mosi <= spi_mosi;
spi_miso <= i_spi_miso;
end if;
end if;
end if;
end process;
end architecture;
| apache-2.0 | c465e3f01ee6e32e35580b33bcd64b15 | 0.43983 | 4.131667 | false | false | false | false |
tsotnep/vhdl_soc_audio_mixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/Balance.vhd | 2 | 5,209 | ----------------------------------------------------------------------------------
-- Company: TTU_SoCDesign
-- Engineer: Mohamed Behery
--
-- Create Date: 16:51:21 04/29/2015
-- Design Name: Panning unit
-- Module Name: Balance - Behavioral
-- Project Name: Audio mixer
-- Target Devices: ZedBoard (Zynq7000)
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Balance is
generic(INTBIT_WIDTH : positive ;
FRACBIT_WIDTH : positive ;
N : positive ;
Attenuation_Const : positive ); -- This constant is for attenuating the input signals so that the signal is not chopped if amplified
Port(CLK_BAL : in std_logic;
RESET_BAL : in std_logic;
POINTER : in integer;
CH_L_IN, CH_R_IN : in signed(INTBIT_WIDTH - 1 downto 0);
CH_L_OUT : out signed(INTBIT_WIDTH - 1 downto 0) := x"000000";
CH_R_OUT : out signed(INTBIT_WIDTH - 1 downto 0) := x"000000";
READY_BAL : out std_logic := '0'
);
end Balance;
Architecture Behavioral of Balance is
type Coeff_Array is array (0 to N / 2) of signed((INTBIT_WIDTH + FRACBIT_WIDTH) - 1 downto 0);
-- Coeffecients calculated via the Matlab m-file (check the Matlab code in the last code section)
-- constant Amp_Coeff : Coeff_Array := (500,667,767,867,909,923,937,951,962,967,972,977,982,986,991,995,1000); --The second half of the balance graph has it's amplification values placed in Amp_Coeff array
-- constant Att_Coeff : Coeff_Array := (500,333,233,133,91,77,63,49,38,33,28,23,18,14,9,5,0); --The second half of the balance graph has it's attenuation values placed in Att_Coeff array
constant Amp_Coeff : Coeff_Array := (x"0001F400", x"00029B00", x"0002FF00", x"00036300", x"00038D00", x"00039B00", x"0003A900", x"0003B700", x"0003C200", x"0003C700", x"0003CC00", x"0003D100", x"0003D600", x"0003DA00", x"0003DF00", x"0003E300", x"0003E800");
constant Att_Coeff : Coeff_Array := (x"0001F400", x"00014D00", x"0000E900", x"00008500", x"00005B00", x"00004D00", x"00003F00", x"00003100", x"00002600", x"00002100", x"00001C00", x"00001700", x"00001200", x"00000E00", x"00000900", x"00000500", x"00000000");
signal Coeff_Left : signed((INTBIT_WIDTH + FRACBIT_WIDTH) - 1 downto 0);
signal Coeff_Right : signed((INTBIT_WIDTH + FRACBIT_WIDTH) - 1 downto 0);
signal ready_signal_right : STD_LOGIC;
signal ready_signal_left : STD_LOGIC;
signal CH_R_IN_signal : signed(INTBIT_WIDTH - 1 downto 0);
signal CH_L_IN_signal : signed(INTBIT_WIDTH - 1 downto 0);
signal CH_L_OUT_signal : signed(INTBIT_WIDTH - 1 downto 0);
signal CH_R_OUT_signal : signed(INTBIT_WIDTH - 1 downto 0);
component AmplifierFP
Port(
CLK : in std_logic;
RESET : in std_logic;
IN_SIG : in signed((INTBIT_WIDTH - 1) downto 0); --amplifier input signal
IN_COEF : in signed((INTBIT_WIDTH + FRACBIT_WIDTH - 1) downto 0) := (others => '0'); --amplifying coefficient
OUT_AMP : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); --amplifier output
OUT_RDY : out std_logic
);
end component;
begin
Mult_Left : AmplifierFP port map(
CLK => CLK_BAL,
RESET => RESET_BAL,
IN_SIG => CH_L_IN_signal,
IN_COEF => Coeff_Left,
OUT_AMP => CH_L_OUT_signal,
OUT_RDY => ready_signal_left
);
Mult_Right : AmplifierFP port map(
CLK => CLK_BAL,
RESET => RESET_BAL,
IN_SIG => CH_R_IN_signal,
IN_COEF => Coeff_right,
OUT_AMP => CH_R_OUT_signal,
OUT_RDY => ready_signal_right
);
READY_BAL <= (ready_signal_right and ready_signal_left);
CH_L_IN_signal <= shift_right(CH_L_IN, Attenuation_Const); -- Attenuating the incoming data from the outside by 6dB
CH_R_IN_signal <= shift_right(CH_R_IN, Attenuation_Const); -- Attenuating the incoming data from the outside by 6dB
Combinational : process(POINTER) -- Here according to the value of the POINTER the coefficient graph "half" is either kept as it is or it's inverted
begin
if (POINTER > N / 2) then -- Case 1: Amplify Right and Attenuate Left
Coeff_Right <= Amp_Coeff(POINTER - N / 2); -- If the POINTER is above 50% the graph is kept as it is
Coeff_Left <= Att_Coeff(POINTER - N / 2);
elsif (POINTER < N / 2) then -- Case 2: Amplify Left and Attenuate Right
Coeff_Right <= Att_Coeff(N / 2 - POINTER); -- If the POINTER is below 50% the graph is inverted
Coeff_Left <= Amp_Coeff(N / 2 - POINTER);
else
Coeff_Right <= Att_Coeff(0); -- else: the POINTER = 50%, give the coefficients the 0th value in the array
Coeff_Left <= Amp_Coeff(0);
end if;
end process Combinational;
Sequential : process(CLK_BAL)
begin
if (CLK_BAL'event and CLK_BAL = '1') then
CH_L_OUT <= CH_L_OUT_signal;
CH_R_OUT <= CH_R_OUT_signal;
end if;
end process Sequential;
end Behavioral; | mit | 607ad5ec5a79a8067336ee41381d7a29 | 0.617009 | 3.203567 | false | false | false | false |
whitef0x0/EECE353-Lab4 | lab4-challenge.vhd | 1 | 4,278 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lab4_challenge is
port(CLOCK_50 : in std_logic;
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(17 downto 0);
LEDG : out std_logic_vector(7 downto 0);
VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0); -- The outs go to VGA controller
VGA_HS : out std_logic;
VGA_VS : out std_logic;
VGA_BLANK : out std_logic;
VGA_SYNC : out std_logic;
VGA_CLK : out std_logic);
end lab4_challenge;
architecture rtl of lab4_challenge is
-- Component from the Verilog file: vga_adapter.v
component vga_adapter
generic(RESOLUTION : string);
port (
resetn : in std_logic;
clock : in std_logic;
colour : in std_logic_vector(2 downto 0);
x : in std_logic_vector(7 downto 0);
y : in std_logic_vector(6 downto 0);
plot : in std_logic;
VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0);
VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK : out std_logic);
end component;
component fsm_challenge is
PORT (
clk : IN STD_LOGIC;
resetb : IN STD_LOGIC;
xdone, ydone, ldone : IN STD_LOGIC;
sw : IN STD_LOGIC_VECTOR(17 downto 0);
draw : IN STD_LOGIC;
initx, inity, loady, loadx, plot, initl, drawl : OUT STD_LOGIC;
colour : OUT STD_LOGIC_VECTOR(2 downto 0);
x : OUT STD_LOGIC_VECTOR(7 downto 0);
y : OUT STD_LOGIC_VECTOR(6 downto 0);
initLoad: STD_LOGIC;
ledg : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component datapath_challenge is
PORT (
clk : IN STD_LOGIC;
resetb : IN STD_LOGIC;
initx, inity, loady, loadx, initl, drawl : IN STD_LOGIC;
x : OUT STD_LOGIC_VECTOR(7 downto 0);
y : OUT STD_LOGIC_VECTOR(6 downto 0);
xin : IN STD_LOGIC_VECTOR(7 downto 0); -- x1
yin : IN STD_LOGIC_VECTOR(6 downto 0); -- y1
initLoad: STD_LOGIC;
xdone, ydone, ldone : OUT STD_LOGIC
);
end component;
signal x : std_logic_vector(7 downto 0) := "00000000";
signal y : std_logic_vector(6 downto 0) := "0000000";
signal colour : std_logic_vector(2 downto 0);
signal plot : std_logic;
signal inity, initx, initl : std_logic;
signal xdone, ydone, ldone : std_logic;
signal loady, loadx, drawl : std_logic;
signal s_initLoad : std_logic;
signal xmid : std_logic_vector(7 downto 0);
signal ymid : std_logic_vector(6 downto 0);
signal slow : std_logic_vector(23 downto 0) := (others=>'0');
begin
PROCESS(CLOCK_50)
BEGIN
IF (rising_edge(CLOCK_50)) THEN
slow <= std_logic_vector(unsigned(slow) + 1);
END IF;
END PROCESS;
vga_u0 : vga_adapter
generic map(RESOLUTION => "160x120")
port map(resetn => KEY(3),
clock => CLOCK_50,
colour => colour,
x => x,
y => y,
plot => plot,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_HS => VGA_HS,
VGA_VS => VGA_VS,
VGA_BLANK => VGA_BLANK,
VGA_SYNC => VGA_SYNC,
VGA_CLK => VGA_CLK
);
sm : fsm_challenge PORT MAP(
clk => CLOCK_50,
resetb => KEY(3),
xdone => xdone,
ydone => ydone,
ldone => ldone,
sw => SW,
draw => KEY(0),
initx => initx,
inity => inity,
loady => loady,
loadx => loadx,
plot => plot,
initl => initl,
drawl => drawl,
colour => colour,
x => xmid,
y => ymid,
initLoad => s_initLoad,
ledg => LEDG
);
dp : datapath_challenge PORT MAP(
clk => CLOCK_50,
resetb => KEY(3),
initx => initx,
inity => inity,
initl => initl,
drawl => drawl,
x => x,
y => y,
xin => xmid,
yin => ymid,
xdone => xdone,
ydone => ydone,
ldone => ldone,
loady => loady,
initLoad => s_initLoad,
loadx => loadx
);
end rtl;
| mit | 99ca8f2f08dc2b737d83ade131689ebb | 0.521973 | 3.150221 | false | false | false | false |
tsotnep/vhdl_soc_audio_mixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/Tester.vhd | 3 | 3,051 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Tester is
port(
Audio_Left_in : in std_logic_vector(23 downto 0);
Audio_Right_in : in std_logic_vector(23 downto 0);
VolCtrl_Left_out_in : in std_logic_vector(23 downto 0);
VolCtrl_Right_out_in : in std_logic_vector(23 downto 0);
Mux1_VolCtrlORAudio_Left_out : out std_logic_vector(23 downto 0);
Mux1_VolCtrlORAudio_Right_out : out std_logic_vector(23 downto 0);
Filter_Left_out_in : in std_logic_vector(23 downto 0);
Filter_Right_out_in : in std_logic_vector(23 downto 0);
Mux2_FilterORMux1_Left_out : out std_logic_vector(23 downto 0);
Mux2_FilterORMux1_Right_out : out std_logic_vector(23 downto 0);
Balance_Left_out_in : in std_logic_vector(23 downto 0);
Balance_Right_out_in : in std_logic_vector(23 downto 0);
Mux3_BalanceORMux2_Left_out : out std_logic_vector(23 downto 0);
Mux3_BalanceORMux2_Right_out : out std_logic_vector(23 downto 0);
Mux_Select_in : in std_logic_vector(2 downto 0));
end Tester;
architecture Behavioral of Tester is
signal Mux1_VolCtrlORAudio_Left_out_T : std_logic_vector(23 downto 0);
signal Mux1_VolCtrlORAudio_Right_out_T : std_logic_vector(23 downto 0);
signal Mux2_FilterORMux1_Left_out_T : std_logic_vector(23 downto 0);
signal Mux2_FilterORMux1_Right_out_T : std_logic_vector(23 downto 0);
begin
Mux1_VolCtrlORAudio_Left_out <= Mux1_VolCtrlORAudio_Left_out_T;
Mux1_VolCtrlORAudio_Right_out <= Mux1_VolCtrlORAudio_Right_out_T;
Mux2_FilterORMux1_Left_out <= Mux2_FilterORMux1_Left_out_T;
Mux2_FilterORMux1_Right_out <= Mux2_FilterORMux1_Right_out_T;
MUX1 : process(Audio_Left_in, Audio_Right_in, Mux_Select_in(0), VolCtrl_Left_out_in, VolCtrl_Right_out_in)
begin
if Mux_Select_in(0) = '0' then
Mux1_VolCtrlORAudio_Left_out_T <= VolCtrl_Left_out_in;
Mux1_VolCtrlORAudio_Right_out_T <= VolCtrl_Right_out_in;
else
Mux1_VolCtrlORAudio_Left_out_T <= Audio_Left_in;
Mux1_VolCtrlORAudio_Right_out_T <= Audio_Right_in;
end if;
end process;
MUX2 : process(Filter_Left_out_in, Filter_Right_out_in, Mux_Select_in(1), Mux1_VolCtrlORAudio_Left_out_T, Mux1_VolCtrlORAudio_Right_out_T)
begin
if Mux_Select_in(1) = '0' then
Mux2_FilterORMux1_Left_out_T <= Filter_Left_out_in;
Mux2_FilterORMux1_Right_out_T <= Filter_Right_out_in;
else
Mux2_FilterORMux1_Left_out_T <= Mux1_VolCtrlORAudio_Left_out_T;
Mux2_FilterORMux1_Right_out_T <= Mux1_VolCtrlORAudio_Right_out_T;
end if;
end process;
MUX3 : process (Balance_Left_out_in, Balance_Right_out_in, Mux2_FilterORMux1_Left_out_T, Mux2_FilterORMux1_Right_out_T, Mux_Select_in(2))
begin
if Mux_Select_in(2) = '0' then
Mux3_BalanceORMux2_Left_out <= Balance_Left_out_in;
Mux3_BalanceORMux2_Right_out <= Balance_Right_out_in;
else
Mux3_BalanceORMux2_Left_out <= Mux2_FilterORMux1_Left_out_T;
Mux3_BalanceORMux2_Right_out <= Mux2_FilterORMux1_Right_out_T;
end if;
end process;
end Behavioral;
| mit | b63634f26ecb350d37316ab3a00adb47 | 0.698132 | 2.783759 | false | false | false | false |
esar/hdmilight-v2 | fpga/test_flashdma.vhd | 1 | 3,875 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:08:12 11/08/2014
-- Design Name:
-- Module Name: /home/stephen/projects/hardware/hdmilight/fpga/test_flashdma.vhd
-- Project Name: hdmilight
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: flashDMAController
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_flashdma IS
END test_flashdma;
ARCHITECTURE behavior OF test_flashdma IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT flashDMAController
PORT(
clk : IN std_logic;
flashStartAddr : IN std_logic_vector(23 downto 0);
sramStartAddr : IN std_logic_vector(15 downto 0);
copySize : IN std_logic_vector(15 downto 0);
write : IN std_logic;
start : IN std_logic;
busy : OUT std_logic;
sramWe : OUT std_logic;
sramAddr : OUT std_logic_vector(15 downto 0);
sramDin : OUT std_logic_vector(7 downto 0);
sramDout : IN std_logic_vector(7 downto 0);
spiClk : OUT std_logic;
spiCs : OUT std_logic;
spiDo : OUT std_logic;
spiDi : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal flashStartAddr : std_logic_vector(23 downto 0) := (others => '0');
signal sramStartAddr : std_logic_vector(15 downto 0) := (others => '0');
signal copySize : std_logic_vector(15 downto 0) := (others => '0');
signal write : std_logic := '0';
signal start : std_logic := '0';
signal sramDout : std_logic_vector(7 downto 0) := (others => '0');
signal spiDi : std_logic := '0';
--Outputs
signal busy : std_logic;
signal sramWe : std_logic;
signal sramAddr : std_logic_vector(15 downto 0);
signal sramDin : std_logic_vector(7 downto 0);
signal spiClk : std_logic;
signal spiCs : std_logic;
signal spiDo : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant spiClk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: flashDMAController PORT MAP (
clk => clk,
flashStartAddr => flashStartAddr,
sramStartAddr => sramStartAddr,
copySize => copySize,
write => write,
start => start,
busy => busy,
sramWe => sramWe,
sramAddr => sramAddr,
sramDin => sramDin,
sramDout => sramDout,
spiClk => spiClk,
spiCs => spiCs,
spiDo => spiDo,
spiDi => spiDi
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
flashStartAddr <= x"F00F0F";
write <= '0';
copySize <= x"0100";
start <= '1';
wait for clk_period;
start <= '0';
wait;
end process;
END;
| gpl-2.0 | c2b833b56b05fd865c352c181f1d3e77 | 0.585548 | 3.871129 | false | true | false | false |
dhmeves/ece-485 | ece-485-project-2/sign_extend.vhd | 1 | 3,179 | library IEEE;
use ieee.std_logic_1164.all;
entity sign_extend is
port(
instr15_0 : in std_logic_vector(15 downto 0);
clk, rst, pre, ce : in std_logic;
output : out std_logic_vector(31 downto 0)
);
end sign_extend;
architecture behav of sign_extend is
signal output_buf, output_buf0 : std_logic;
begin
DFF1 : entity work.d_flip_flop(behav) port map(clk, instr15_0(0), rst, pre, ce, output(0));
DFF2 : entity work.d_flip_flop(behav) port map(clk, instr15_0(1), rst, pre, ce, output(1));
DFF3 : entity work.d_flip_flop(behav) port map(clk, instr15_0(2), rst, pre, ce, output(2));
DFF4 : entity work.d_flip_flop(behav) port map(clk, instr15_0(3), rst, pre, ce, output(3));
DFF5 : entity work.d_flip_flop(behav) port map(clk, instr15_0(4), rst, pre, ce, output(4));
DFF6 : entity work.d_flip_flop(behav) port map(clk, instr15_0(5), rst, pre, ce, output(5));
DFF7 : entity work.d_flip_flop(behav) port map(clk, instr15_0(6), rst, pre, ce, output(6));
DFF8 : entity work.d_flip_flop(behav) port map(clk, instr15_0(7), rst, pre, ce, output(7));
DFF9 : entity work.d_flip_flop(behav) port map(clk, instr15_0(8), rst, pre, ce, output(8));
DFF10 : entity work.d_flip_flop(behav) port map(clk, instr15_0(9), rst, pre, ce, output(9));
DFF11 : entity work.d_flip_flop(behav) port map(clk, instr15_0(10), rst, pre, ce, output(10));
DFF12 : entity work.d_flip_flop(behav) port map(clk, instr15_0(11), rst, pre, ce, output(11));
DFF13 : entity work.d_flip_flop(behav) port map(clk, instr15_0(12), rst, pre, ce, output(12));
DFF14 : entity work.d_flip_flop(behav) port map(clk, instr15_0(13), rst, pre, ce, output(13));
DFF15 : entity work.d_flip_flop(behav) port map(clk, instr15_0(14), rst, pre, ce, output(14));
DFF16 : entity work.d_flip_flop(behav) port map(clk, instr15_0(15), rst, pre, ce, output(15));
output_buf0 <= instr15_0(15) when rst = '0' else '0' when rst = '1';
output_buf <= output_buf0 when pre = '0' else '1' when pre = '1';
output(16) <= '0' when output_buf = '0' else '1' when output_buf = '1';
output(17) <= '0' when output_buf = '0' else '1' when output_buf = '1';
output(18) <= '0' when output_buf = '0' else '1' when output_buf = '1';
output(19) <= '0' when output_buf = '0' else '1' when output_buf = '1';
output(20) <= '0' when output_buf = '0' else '1' when output_buf = '1';
output(21) <= '0' when output_buf = '0' else '1' when output_buf = '1';
output(22) <= '0' when output_buf = '0' else '1' when output_buf = '1';
output(23) <= '0' when output_buf = '0' else '1' when output_buf = '1';
output(24) <= '0' when output_buf = '0' else '1' when output_buf = '1';
output(25) <= '0' when output_buf = '0' else '1' when output_buf = '1';
output(26) <= '0' when output_buf = '0' else '1' when output_buf = '1';
output(27) <= '0' when output_buf = '0' else '1' when output_buf = '1';
output(28) <= '0' when output_buf = '0' else '1' when output_buf = '1';
output(29) <= '0' when output_buf = '0' else '1' when output_buf = '1';
output(30) <= '0' when output_buf = '0' else '1' when output_buf = '1';
output(31) <= '0' when output_buf = '0' else '1' when output_buf = '1';
end behav; | gpl-3.0 | 4e4d15fdfbace36f373f4086559e99cc | 0.627556 | 2.52502 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-1/encoder_struct.vhd | 1 | 4,154 | library ieee;
use ieee.std_logic_1164.all;
entity encoder_struct is
port(
input : in std_logic_vector(5 downto 0);
output : out std_logic_vector(2 downto 0)
);
end encoder_struct;
architecture struct of encoder_struct is
begin
output(0) <= ((input(1) and not (((input(0) or input(2)) or (input(3) or input(4))) or input(5))) or (input(3) and not (((input(0) or input(1)) or (input(2) or input(4))) or input(5))) or (input(5) and not (((input(0) or input(1)) or (input(2) or input(3))) or input(4))));
output(1) <= ((input(2) and not (((input(0) or input(1)) or (input(3) or input(4))) or input(5))) or (input(3) and not (((input(0) or input(1)) or (input(2) or input(4))) or input(5))));
output(2) <= ((input(4) and not (((input(0) or input(1)) or (input(2) or input(3))) or input(5))) or (input(5) and not (((input(0) or input(1)) or (input(2) or input(3))) or input(4))));
end struct;
library ieee;
use ieee.std_logic_1164.all;
entity encoder_struct_test_bench is
end encoder_struct_test_bench;
architecture behavior of encoder_struct_test_bench is
-- Component Declaration for the Encoder Structural Model Test Bench
component encoder_struct
port(
input : in std_logic_vector(5 downto 0);
output : out std_logic_vector(2 downto 0)
);
end component;
-- inputs
signal input : std_logic_vector(5 downto 0) := (others => '0');
-- outputs
signal output : std_logic_vector(2 downto 0);
begin
-- Instantiate the Encoder Test Bench
test_bench: encoder_struct port map (
input => input,
output => output
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 50 ns.
wait for 50 ns;
input <= "000000";
wait for 50 ns;
input <= "000001";
wait for 50 ns;
input <= "000010";
wait for 50 ns;
input <= "000011";
wait for 50 ns;
input <= "000100";
wait for 50 ns;
input <= "000101";
wait for 50 ns;
input <= "000110";
wait for 50 ns;
input <= "000111";
wait for 50 ns;
input <= "001000";
wait for 50 ns;
input <= "001001";
wait for 50 ns;
input <= "001010";
wait for 50 ns;
input <= "001011";
wait for 50 ns;
input <= "001100";
wait for 50 ns;
input <= "001101";
wait for 50 ns;
input <= "001110";
wait for 50 ns;
input <= "001111";
wait for 50 ns;
input <= "010000";
wait for 50 ns;
input <= "010001";
wait for 50 ns;
input <= "010010";
wait for 50 ns;
input <= "010011";
wait for 50 ns;
input <= "010100";
wait for 50 ns;
input <= "010101";
wait for 50 ns;
input <= "010110";
wait for 50 ns;
input <= "010111";
wait for 50 ns;
input <= "011000";
wait for 50 ns;
input <= "011001";
wait for 50 ns;
input <= "011010";
wait for 50 ns;
input <= "011011";
wait for 50 ns;
input <= "011100";
wait for 50 ns;
input <= "011101";
wait for 50 ns;
input <= "011110";
wait for 50 ns;
input <= "011111";
wait for 50 ns;
input <= "100000";
wait for 50 ns;
input <= "100001";
wait for 50 ns;
input <= "100010";
wait for 50 ns;
input <= "100011";
wait for 50 ns;
input <= "100100";
wait for 50 ns;
input <= "100101";
wait for 50 ns;
input <= "100110";
wait for 50 ns;
input <= "100111";
wait for 50 ns;
input <= "101000";
wait for 50 ns;
input <= "101001";
wait for 50 ns;
input <= "101010";
wait for 50 ns;
input <= "101011";
wait for 50 ns;
input <= "101100";
wait for 50 ns;
input <= "101101";
wait for 50 ns;
input <= "101110";
wait for 50 ns;
input <= "101111";
wait for 50 ns;
input <= "110000";
wait for 50 ns;
input <= "110001";
wait for 50 ns;
input <= "110010";
wait for 50 ns;
input <= "110011";
wait for 50 ns;
input <= "110100";
wait for 50 ns;
input <= "110101";
wait for 50 ns;
input <= "110110";
wait for 50 ns;
input <= "110111";
wait for 50 ns;
input <= "111000";
wait for 50 ns;
input <= "111001";
wait for 50 ns;
input <= "111010";
wait for 50 ns;
input <= "111011";
wait for 50 ns;
input <= "111100";
wait for 50 ns;
input <= "111101";
wait for 50 ns;
input <= "111110";
wait for 50 ns;
input <= "111111";
wait;
end process;
end; | gpl-3.0 | e554b7af281561350417c135e3e8bcee | 0.603033 | 2.841313 | false | false | false | false |
tsotnep/vhdl_soc_audio_mixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/Volctrl.vhd | 2 | 2,921 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity VolCtrl is
generic(INTBIT_WIDTH : positive; -- := 24;
FRACBIT_WIDTH : positive --:= 8
);
port(
OUT_VOLCTRL_L : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); -- 24 bit signed output
OUT_VOLCTRL_R : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); -- 24 bit signed output
OUT_RDY_L : out STD_LOGIC;
OUT_RDY_R : out STD_LOGIC;
IN_SIG_L : in signed((INTBIT_WIDTH - 1) downto 0); --amplifier input signal 24-bit
IN_SIG_R : in signed((INTBIT_WIDTH - 1) downto 0); --amplifier input signal 24-bit
IN_COEF_L : in signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); -- 32 bit COEF from a register. Last 8 bits are fractional for volume control 0<-->1
IN_COEF_R : in signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); -- 32 bit COEF from a register. Last 8 bits are fractional for volume control 0<-->1
RESET : in STD_LOGIC;
CLK_48 : in STD_LOGIC;
CLK_100M : in STD_LOGIC
);
end VolCtrl;
architecture Behavioral of VolCtrl is
COMPONENT AmplifierFP
PORT(
CLK : in std_logic;
RESET : in std_logic;
IN_SIG : in signed((INTBIT_WIDTH - 1) downto 0); --amplifier input signal 24-bit
IN_COEF : in signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); -- 32 bit COEF from a register. Last 8 bits are fractional for volume control 0<-->1
OUT_AMP : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); --amplifier output
OUT_RDY : out std_logic
);
END COMPONENT;
signal SIG_VOLCTRL_L, SIG_VOLCTRL_R : signed((INTBIT_WIDTH - 1) downto 0) := (others => '0');
signal AMP_OUT_L, AMP_OUT_R : signed((INTBIT_WIDTH - 1) downto 0) := (others => '0');
signal VOLCTRL_L, VOLCTRL_R : signed((INTBIT_WIDTH - 1) downto 0) := (others => '0');
signal volctrl_ready_l : std_logic := '0';
signal volctrl_ready_r : std_logic := '0';
begin
AmplifierFP_L : AmplifierFP PORT MAP(
CLK => CLK_48,
RESET => RESET,
IN_SIG => IN_SIG_L,
IN_COEF => IN_COEF_L,
OUT_AMP => AMP_OUT_L,
OUT_RDY => volctrl_ready_l
);
AmplifierFP_R : AmplifierFP PORT MAP(
CLK => CLK_48,
RESET => RESET,
IN_SIG => IN_SIG_R,
IN_COEF => IN_COEF_R,
OUT_AMP => AMP_OUT_R,
OUT_RDY => volctrl_ready_r
);
seq_proc : process(CLK_48)
begin
if (CLK_48'event and CLK_48 = '1') then
-- update the ready signal when new values gets written to the buffer
if (volctrl_ready_l = '1') then
VOLCTRL_L <= AMP_OUT_L;
end if;
if (volctrl_ready_r = '1') then
VOLCTRL_R <= AMP_OUT_R;
end if;
end if;
end process;
OUT_RDY_L <= volctrl_ready_l;
OUT_RDY_R <= volctrl_ready_r;
OUT_VOLCTRL_L <= VOLCTRL_L;
OUT_VOLCTRL_R <= VOLCTRL_R;
end Behavioral; | mit | 538ddecc16662a562e50b879a6854a89 | 0.600137 | 2.962475 | false | false | false | false |
UdayanSinha/Code_Blocks | VHDL/Projects/work/data_bus_4bit.vhd | 1 | 900 | LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY data_bus_4bit IS
PORT(data_bus: INOUT STD_LOGIC_VECTOR(3 DOWNTO 0):=(others=>'Z'); --data bus
rd_wr, clk, addr: IN STD_LOGIC); --register read-write select, clock, register select
END data_bus_4bit;
ARCHITECTURE behave of data_bus_4bit IS
SIGNAL d0, d1, q0, q1: STD_LOGIC_VECTOR(3 DOWNTO 0); --register internal outputs and inputs
BEGIN
PROCESS(clk)
BEGIN
IF rising_edge(clk) THEN
q1<=d1;
q0<=d0;
END IF;
END PROCESS;
data_bus<=q0 WHEN addr='0' AND rd_wr='0' ELSE "ZZZZ";
data_bus<=q1 WHEN addr='1' AND rd_wr='0' ELSE "ZZZZ";
d0<=data_bus WHEN addr='0' AND rd_wr='1';
d1<=data_bus WHEN addr='1' AND rd_wr='1';
END behave; | mit | ddd3078f42ee9f2361227100f80e836d | 0.663333 | 3.010033 | false | false | false | false |
kb3gtn/mojo_modulator | vhdl/src/mojo_modulator.vhd | 1 | 8,945 | ---------------------------------------------------------------------------
-- mojo_modulator.vhd
--
-- This is a simple modulator design top level component
--
-- In this case the design is just a CW generator to test out
-- the NCO design.
--
-- Peter Fetterer
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mojo_modulator is
generic (
ftw_reg0_addr : integer := 8; -- address in memory of this register
ftw_reg1_addr : integer := 9; -- "
ftw_reg2_addr : integer := 10; -- "
ftw_reg3_addr : integer := 11 -- "
);
port (
-- Databus Clock & reset ---------------------------------
i_clk_db : in std_logic; -- data bus clock
i_srst_db : in std_logic; -- reset for databus clk
-- Databus signals ---------------------------------------
i_db_addr : in std_logic_vector(6 downto 0);
i_db_wdata : in std_logic_vector(7 downto 0);
o_db_rdata : out std_logic_vector(7 downto 0);
i_db_rstrb : in std_logic;
i_db_wstrb : in std_logic;
-- DSP Sample Clocks & Reset -----------------------------
i_clk_dsp : in std_logic; -- dsp sample rate clock (>= db_clk)
i_srst_dsp : in std_logic; -- reset
---DSP Samples Out ---------------------------------------
o_dac_samples : out signed(15 downto 0)
);
end entity mojo_modulator;
architecture system of mojo_modulator is
------------------------
-- Components
------------------------
component cos_nco is
generic (
constant phase_acc_size : integer := 32; -- 32bit freq resultion
constant sample_depth : integer := 16; -- number of bits in output samples
constant phase_depth : integer := 12 -- resolution of the phase generation
);
port (
i_clk : in std_logic; -- sample rate clock
i_srst : in std_logic; -- sync reset to provided clock
----------------------------------------
i_phase_offset : in unsigned( phase_depth-1 downto 0 ); -- phase shift input
i_freq_word : in unsigned( phase_acc_size-1 downto 0); -- frequency input
o_sample : out signed( sample_depth-1 downto 0) -- output samples, every clock
);
end component cos_nco;
-------------------------
-- Signals
-------------------------
signal ftw_reg_working : unsigned( 31 downto 0 ); -- data bus working copy
signal ftw_reg : unsigned( 31 downto 0 ); -- register used to drive nco
signal ftw_reg_state : bit_vector( 3 downto 0 ); -- track if all registers have been updated.
signal ftw_update_ff : std_logic; -- flip flop to cross clock domain
signal ftw_update_ff_set : std_logic; -- set by data bus (slow clock)
signal ftw_update_ff_clr : std_logic; -- cleared by dsp domain
-- register address as std_logic_vectors
constant ftw_reg0_addr_stl : std_logic_vector := std_logic_vector( to_unsigned(ftw_reg0_addr, 7));
constant ftw_reg1_addr_stl : std_logic_vector := std_logic_vector( to_unsigned(ftw_reg1_addr, 7));
constant ftw_reg2_addr_stl : std_logic_vector := std_logic_vector( to_unsigned(ftw_reg2_addr, 7));
constant ftw_reg3_addr_stl : std_logic_vector := std_logic_vector( to_unsigned(ftw_reg3_addr, 7));
signal phase_offset : unsigned( 11 downto 0);
begin
-- static phase offset for NCO (not changing)
phase_offset <= (others=>'0');
-- ff to signal dsp clock domain that ftw_reg_working is ready to latch into ftw_reg
u_ftw_update_ff : process( i_clk_dsp )
begin
if ( rising_edge( i_clk_dsp ) ) then
if ( i_srst_dsp = '1' ) then
ftw_update_ff <= '0';
else
-- clear has priority over set. (faster clock domain)
if ( ftw_update_ff_clr = '1' ) then
ftw_update_ff <= '0';
else
if ( ftw_update_ff_set = '1' ) then
ftw_update_ff <= '1';
end if;
end if;
end if;
end if;
end process;
-- data bus slave module
u_db_slave : process( i_clk_db )
begin
if ( rising_edge( i_clk_db ) ) then
if ( i_srst_db = '1' ) then
ftw_reg_working <= (others=>'0');
ftw_reg_state <= "0000";
ftw_update_ff_set <= '0';
else
if ( ftw_reg_state = "1111" ) then
ftw_update_ff_set <= '1'; -- only up for 1 clk_db cycle
ftw_reg_state <= "0000"; -- reset state
else
ftw_update_ff_set <= '0'; -- always 0 unless signaling.
end if;
-- write have priority over reads
if ( i_db_wstrb = '1' ) then
if ( i_db_addr = ftw_reg0_addr_stl ) then
ftw_reg_working(7 downto 0) <= unsigned(i_db_wdata);
ftw_reg_state(0) <= '1';
end if;
if ( i_db_addr = ftw_reg1_addr_stl ) then
ftw_reg_working(15 downto 8) <= unsigned(i_db_wdata);
ftw_reg_state(1) <= '1';
end if;
if ( i_db_addr = ftw_reg2_addr_stl ) then
ftw_reg_working(23 downto 16) <= unsigned(i_db_wdata);
ftw_reg_state(2) <= '1';
end if;
if ( i_db_addr = ftw_reg3_addr_stl ) then
ftw_reg_working(31 downto 24) <= unsigned(i_db_wdata);
ftw_reg_state(3) <= '1';
end if;
else
-- data bus read..
if ( i_db_rstrb = '1' ) then
if ( i_db_addr = ftw_reg0_addr_stl ) then
o_db_rdata <= std_logic_vector( ftw_reg_working(7 downto 0));
end if;
if ( i_db_addr = ftw_reg1_addr_stl ) then
o_db_rdata <= std_logic_vector( ftw_reg_working(15 downto 8));
end if;
if ( i_db_addr = ftw_reg2_addr_stl ) then
o_db_rdata <= std_logic_vector( ftw_reg_working(23 downto 16));
end if;
if ( i_db_addr = ftw_reg3_addr_stl ) then
o_db_rdata <= std_logic_vector( ftw_reg_working(31 downto 24));
end if;
-- if none of our register are being addressed.
if ( i_db_addr /= ftw_reg0_addr_stl ) and
( i_db_addr /= ftw_reg1_addr_stl ) and
( i_db_addr /= ftw_reg2_addr_stl ) and
( i_db_addr /= ftw_reg3_addr_stl ) then
-- not addressing us, output 'Z' (high Z drive to shared bus)
o_db_rdata <= (others=>'Z');
end if;
else
-- not in read strobe, don't drive bus
o_db_rdata <= (others=>'Z');
end if;
end if;
end if;
end if;
end process;
-- update ftw register into dsp clock domain.
u_ftw_reg_update : process( i_clk_dsp )
begin
if (rising_edge(i_clk_dsp) ) then
if ( i_srst_dsp = '1' ) then
ftw_reg <= (others=>'0');
else
if ( ftw_update_ff = '1' ) then
-- latch in new ftw reg value from databus domain
ftw_reg <= ftw_reg_working;
-- signal we have handled it.
ftw_update_ff_clr <= '1';
else
ftw_update_ff_clr <= '0';
end if;
end if;
end if;
end process;
-- nco component
u_cos_nco_1 : cos_nco
generic map (
phase_acc_size => 32, -- 32bit freq resultion
sample_depth => 16, -- number of bits in output samples
phase_depth => 12 -- resolution of the phase generation
)
port map (
i_clk => i_clk_dsp,
i_srst => i_srst_dsp,
----------------------------------------
i_phase_offset => phase_offset,
i_freq_word => ftw_reg,
o_sample => o_dac_samples
);
end architecture system;
| apache-2.0 | 55cec8ab6745c4afd591a5e3429d30b1 | 0.445724 | 4.13546 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/source/vhdl/centre_buffer_mgmt.vhd | 1 | 6,398 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: centre_buffer_mgmt - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.lloyds_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity centre_buffer_mgmt is
port (
clk : in std_logic;
sclr : in std_logic;
init : in std_logic;
addr_in_init : in centre_index_type;
nd : in std_logic;
request_rdo : in std_logic;
addr_in : in centre_index_type;
wgtCent_in : in data_type_ext;
sum_sq_in : in coord_type_ext;
count_in : in coord_type;
valid : out std_logic;
wgtCent_out : out data_type_ext;
sum_sq_out : out coord_type_ext;
count_out : out coord_type
);
end centre_buffer_mgmt;
architecture Behavioral of centre_buffer_mgmt is
constant DIM : integer := D;
constant LAT : integer := 2;
type state_type is (read, write);
component centre_buffer_dist
port (
a : IN STD_LOGIC_VECTOR(integer(ceil(log2(real(K_MAX))))-1 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(integer(ceil(log2(real(K_MAX))))-1 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DIM*COORD_BITWIDTH_EXT-1 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
qdpo : OUT STD_LOGIC_VECTOR(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DIM*COORD_BITWIDTH_EXT-1 DOWNTO 0)
);
end component;
signal state : state_type;
signal tmp_we : std_logic;
signal we_reg : std_logic;
signal rdo_delay : std_logic_vector(0 to LAT-1);
signal wr_addr_in_reg : centre_index_type;
signal rd_addr_in_reg : centre_index_type;
signal wgtCent_reg : data_type_ext;
signal sum_sq_reg : coord_type_ext;
signal count_reg : coord_type;
signal tmp_dina : std_logic_vector(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DIM*COORD_BITWIDTH_EXT-1 downto 0);
signal tmp_doutb : std_logic_vector(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DIM*COORD_BITWIDTH_EXT-1 downto 0);
signal tmp_wgtCent_int : data_type_ext;
signal tmp_sum_sq_int : coord_type_ext;
signal tmp_count_int : coord_type;
signal tmp_wgtCent_int_sum : data_type_ext;
signal tmp_sum_sq_int_sum : coord_type_ext;
signal tmp_count_int_sum : coord_type;
begin
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
state <= read;
elsif state = read AND nd = '1' then
state <= write;
elsif state = write then
state <= read;
end if;
end if;
end process fsm_proc;
tmp_we <= '1' WHEN state = write ELSE '0';
reg_proc : process(clk)
begin
if rising_edge(clk) then
if init = '1' then
wr_addr_in_reg <= addr_in_init;
rd_addr_in_reg <= addr_in;
for I in 0 to D-1 loop
wgtCent_reg(I) <= (others => '0');
end loop;
sum_sq_reg <= (others => '0');
count_reg <= (others => '0');
elsif nd = '1' OR request_rdo='1' then
wr_addr_in_reg <= addr_in;
rd_addr_in_reg <= addr_in;
--addr_in_reg <= addr_in;
wgtCent_reg <= wgtCent_in;
sum_sq_reg <= sum_sq_in;
count_reg <= count_in;
end if;
end if;
end process reg_proc;
reg_proc2 : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
we_reg <= '0';
rdo_delay <= (others => '0');
else
we_reg <= tmp_we OR init;
rdo_delay(0) <= request_rdo;
rdo_delay(1 to LAT-1) <= rdo_delay(0 to LAT-2);
end if;
end if;
end process reg_proc2;
centre_buffer_dist_inst : centre_buffer_dist
port map (
a => std_logic_vector(wr_addr_in_reg(integer(ceil(log2(real(K_MAX))))-1 downto 0)),
dpra => std_logic_vector(rd_addr_in_reg(integer(ceil(log2(real(K_MAX))))-1 downto 0)),
d => tmp_dina,
clk => clk,
we => we_reg,
qdpo_srst => init,
qdpo => tmp_doutb
);
G1: for I in 0 to D-1 generate
tmp_wgtCent_int(I) <= tmp_doutb((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT);
end generate G1;
tmp_sum_sq_int <= tmp_doutb(1*COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT-1 downto 0*COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT);
tmp_count_int <= tmp_doutb(COORD_BITWIDTH+COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT-1 downto 0+COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT);
G2: for I in 0 to D-1 generate
tmp_wgtCent_int_sum(I) <= std_logic_vector(signed(tmp_wgtCent_int(I)) + signed(wgtCent_reg(I)));
tmp_dina((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT) <= (tmp_wgtCent_int_sum(I));
end generate G2;
tmp_sum_sq_int_sum <= std_logic_vector(signed(tmp_sum_sq_int) + signed(sum_sq_reg));
tmp_dina(1*COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT-1 downto 0*COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT) <= tmp_sum_sq_int_sum;
tmp_count_int_sum <= std_logic_vector(signed(tmp_count_int) + signed(count_reg));
tmp_dina(COORD_BITWIDTH+COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT-1 downto 0+COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT) <= tmp_count_int_sum;
valid <= rdo_delay(LAT-1);
wgtCent_out <= tmp_wgtCent_int;
sum_sq_out <= tmp_sum_sq_int;
count_out <= tmp_count_int;
end Behavioral;
| bsd-3-clause | 58d417a9155c3d2ca30ae8e9bc65333c | 0.554236 | 3.558398 | false | false | false | false |
esar/hdmilight-v2 | fpga/test_configRam.vhd | 1 | 3,373 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:18:15 10/30/2014
-- Design Name:
-- Module Name: /home/stephen/projects/hardware/hdmilight/fpga/test_configRam.vhd
-- Project Name: hdmilight
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: lightConfigRam
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY test_configRam IS
END test_configRam;
ARCHITECTURE behavior OF test_configRam IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT lightConfigRam
PORT(
a_clk : IN std_logic;
a_wr : IN std_logic;
a_addr : IN std_logic_vector(11 downto 0);
a_din : IN std_logic_vector(7 downto 0);
a_dout : OUT std_logic_vector(7 downto 0);
b_clk : IN std_logic;
b_addr : IN std_logic_vector(8 downto 0);
b_dout : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal a_clk : std_logic := '0';
signal a_wr : std_logic := '0';
signal a_addr : std_logic_vector(11 downto 0) := (others => '0');
signal a_din : std_logic_vector(7 downto 0) := (others => '0');
signal b_clk : std_logic := '0';
signal b_addr : std_logic_vector(8 downto 0) := (others => '0');
--Outputs
signal a_dout : std_logic_vector(7 downto 0);
signal b_dout : std_logic_vector(31 downto 0);
-- Clock period definitions
constant a_clk_period : time := 10 ns;
constant b_clk_period : time := 10 ns;
signal count : std_logic_vector(7 downto 0) := "00000000";
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: lightConfigRam PORT MAP (
a_clk => a_clk,
a_wr => a_wr,
a_addr => a_addr,
a_din => a_din,
a_dout => a_dout,
b_clk => b_clk,
b_addr => b_addr,
b_dout => b_dout
);
-- Clock process definitions
a_clk_process :process
begin
a_clk <= '0';
wait for a_clk_period/2;
a_clk <= '1';
wait for a_clk_period/2;
end process;
b_clk_process :process
begin
b_clk <= '0';
wait for b_clk_period/2;
b_clk <= '1';
wait for b_clk_period/2;
end process;
process(a_clk)
begin
if(rising_edge(a_clk)) then
count <= std_logic_vector(unsigned(count) + 1);
end if;
end process;
a_din <= count;
a_addr <= "0000" & count;
a_wr <= '1' when unsigned(count) < 64 else '0';
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for a_clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| gpl-2.0 | 2e779a757b785fdbe62b196d79356f7c | 0.584643 | 3.434827 | false | true | false | false |
freecores/gpib_controller | vhdl/src/gpib_helper/SinglePulseGenerator.vhd | 1 | 1,909 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: SinglePulseGenerator
-- Date:2011-11-10
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.utilPkg.all;
entity SinglePulseGenerator is
generic (
WIDTH : integer := 3
);
port (
reset : in std_logic;
clk : in std_logic;
t_in: in std_logic;
t_out : out std_logic;
pulse : out std_logic
);
end SinglePulseGenerator;
architecture arch of SinglePulseGenerator is
signal rcount : integer range 0 to WIDTH;
signal i_t_out : std_logic;
begin
pulse <= to_stdl(t_in /= i_t_out);
t_out <= i_t_out;
-- buffer reset generator
process (reset, clk, t_in) begin
if reset = '1' then
i_t_out <= t_in;
rcount <= 0;
elsif rising_edge(clk) then
if t_in /= i_t_out then
rcount <= rcount + 1;
if rcount = WIDTH then
rcount <= 0;
i_t_out <= t_in;
end if;
end if;
end if;
end process;
end arch;
| gpl-3.0 | bc1ef13b3dde4782da657245ab6b9d2b | 0.59979 | 3.721248 | false | false | false | false |
mithro/HDMI2USB | hdl/jpeg_encoder/design/ROMR.vhd | 5 | 7,225 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : ROMR
-- Design : EV_JPEG_ENC
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROMR.VHD
-- Created : Wed Mar 19 21:09 2009
--
--------------------------------------------------------------------------------
--
-- Description : Reciprocal of 1/X where X is 1..255
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity ROMR is
generic
(
ROMADDR_W : INTEGER := 8;
ROMDATA_W : INTEGER := 16
);
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROMR;
architecture RTL of ROMR is
constant CK : integer := 256*256;
type ROMQ_TYPE is array (0 to 2**ROMADDR_W-1)
of INTEGER range 0 to 2**ROMDATA_W-1;
constant rom : ROMQ_TYPE :=
(
0,
65535,
32768,
21845,
16384,
13107,
10923,
9362,
8192,
7282,
6554,
5958,
5461,
5041,
4681,
4369,
4096,
3855,
3641,
3449,
3277,
3121,
2979,
2849,
2731,
2621,
2521,
2427,
2341,
2260,
2185,
2114,
2048,
1986,
1928,
1872,
1820,
1771,
1725,
1680,
1638,
1598,
1560,
1524,
1489,
1456,
1425,
1394,
1365,
1337,
1311,
1285,
1260,
1237,
1214,
1192,
1170,
1150,
1130,
1111,
1092,
1074,
1057,
1040,
1024,
1008,
993,
978,
964,
950,
936,
923,
910,
898,
886,
874,
862,
851,
840,
830,
819,
809,
799,
790,
780,
771,
762,
753,
745,
736,
728,
720,
712,
705,
697,
690,
683,
676,
669,
662,
655,
649,
643,
636,
630,
624,
618,
612,
607,
601,
596,
590,
585,
580,
575,
570,
565,
560,
555,
551,
546,
542,
537,
533,
529,
524,
520,
516,
512,
508,
504,
500,
496,
493,
489,
485,
482,
478,
475,
471,
468,
465,
462,
458,
455,
452,
449,
446,
443,
440,
437,
434,
431,
428,
426,
423,
420,
417,
415,
412,
410,
407,
405,
402,
400,
397,
395,
392,
390,
388,
386,
383,
381,
379,
377,
374,
372,
370,
368,
366,
364,
362,
360,
358,
356,
354,
352,
350,
349,
347,
345,
343,
341,
340,
338,
336,
334,
333,
331,
329,
328,
326,
324,
323,
321,
320,
318,
317,
315,
314,
312,
311,
309,
308,
306,
305,
303,
302,
301,
299,
298,
297,
295,
294,
293,
291,
290,
289,
287,
286,
285,
284,
282,
281,
280,
279,
278,
277,
275,
274,
273,
272,
271,
270,
269,
267,
266,
265,
264,
263,
262,
261,
260,
259,
258,
257
);
signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
begin
datao <= STD_LOGIC_VECTOR(TO_UNSIGNED( rom( TO_INTEGER(UNSIGNED(addr_reg)) ), ROMDATA_W));
process(clk)
begin
if clk = '1' and clk'event then
addr_reg <= addr;
end if;
end process;
end RTL;
| bsd-2-clause | e8f6747b19ff5b8626b555da6ab93188 | 0.359308 | 4.598982 | false | false | false | false |
esar/hdmilight-v2 | fpga/ws2811Driver.vhd | 1 | 3,085 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ws2811Driver is
Port ( clk : in STD_LOGIC;
idle : out STD_LOGIC;
load : in STD_LOGIC;
datain : in STD_LOGIC_VECTOR (23 downto 0);
dataout : out STD_LOGIC);
end ws2811Driver;
architecture Behavioral of ws2811Driver is
signal bitcount : std_logic_vector(4 downto 0);
signal subbitcount : std_logic_vector(4 downto 0);
signal countEnable : std_logic;
signal shiftData : std_logic_vector(23 downto 0);
signal shiftEnable : std_logic;
signal shiftOutput : std_logic;
signal nextOutput : std_logic;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(load = '1') then
bitcount <= (others => '0');
subbitcount <= (others => '0');
elsif(countEnable = '1') then
subbitcount <= std_logic_vector(unsigned(subbitcount) + 1);
if(subbitcount = "10011") then
bitcount <= std_logic_vector(unsigned(bitcount) + 1);
subbitcount <= (others => '0');
end if;
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
if(load = '1') then
shiftData <= datain;
elsif(shiftEnable = '1') then
shiftData <= shiftData(22 downto 0) & "0";
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
dataout <= nextOutput;
end if;
end process;
-- freeze counter when it reaches 24 bytes (24*4 clocks)
countEnable <= '0' when bitcount = "10111" and subbitcount = "10011" else '1';
idle <= not countEnable;
-- enable shift every 4 clocks
shiftEnable <= '1' when subbitcount = "10011" else '0';
shiftOutput <= shiftData(23);
-- over a 4 clock period:
-- for a 1 output 1 1 1 0
-- for a 0 output 1 0 0 0
nextOutput <= '1' when subbitcount(4 downto 2) = "000" else
'0' when subbitcount(4 downto 2) = "100" else
shiftOutput;
end Behavioral;
| gpl-2.0 | 2c8f9f3fe289f4cb8039997cd3a642f9 | 0.649271 | 3.616647 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/pcores/ready4hood_v1_00_a/hdl/vhdl/comp.vhd | 2 | 2,964 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Gabbe
--
-- Create Date: 09:40:15 09/17/2014
-- Design Name:
-- Module Name: comp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity comp is
port(
clk : in std_logic;
rstn : in std_logic; -- active low
i_hash_0, i_hash_1, i_hash_2, i_hash_3 : in unsigned(31 downto 0); -- hash from md5
i_cmp_hash : in std_logic_vector(127 downto 0); -- hash we are going to crack
i_start : in std_logic; -- 1 when we should read i_cmp_hash
o_equal : out std_logic -- 1 if we found the matching hash, else 0
);
end comp;
architecture Behavioral of comp is
-- the register signals --
signal cmp_hash_c, cmp_hash_n : std_logic_vector(127 downto 0);
-- for delaying equal signal, to controller --
signal eq_c, eq_n : std_logic;
begin
-- the only signals which are clocked in this block are the register signals --
clk_proc: process(clk)
begin
if rising_edge(clk) then
if rstn = '0' then
cmp_hash_c <= (others => '0');
eq_c <= '0';
else
cmp_hash_c <= cmp_hash_n;
eq_c <= eq_n;
end if;
end if;
end process;
-- data path --
data_proc: process(i_start, i_cmp_hash, i_hash_0, i_hash_1, i_hash_2, i_hash_3, cmp_hash_c, eq_c)
-- the i_hash_1-3 have to be converted to little endian --
variable little_endian_0, little_endian_1, little_endian_2, little_endian_3 : unsigned(31 downto 0);
begin
-- defaults --
eq_n <= eq_c;
-- converts the md5-hashes to little endian --
little_endian_0 := i_hash_0(7 downto 0) & i_hash_0(15 downto 8) & i_hash_0(23 downto 16) & i_hash_0(31 downto 24);
little_endian_1 := i_hash_1(7 downto 0) & i_hash_1(15 downto 8) & i_hash_1(23 downto 16) & i_hash_1(31 downto 24);
little_endian_2 := i_hash_2(7 downto 0) & i_hash_2(15 downto 8) & i_hash_2(23 downto 16) & i_hash_2(31 downto 24);
little_endian_3 := i_hash_3(7 downto 0) & i_hash_3(15 downto 8) & i_hash_3(23 downto 16) & i_hash_3(31 downto 24);
-- sets the register value --
if i_start = '1' then
cmp_hash_n <= i_cmp_hash;
else
cmp_hash_n <= cmp_hash_c;
end if;
-- have we found a matching hash or not? --
if (little_endian_0 & little_endian_1 & little_endian_2 & little_endian_3) = unsigned(cmp_hash_c) then
eq_n <= '1';
else
eq_n <= '0';
end if;
end process;
o_equal <= eq_c;
end Behavioral;
| mit | 69ff4debfb32193b83b39c2ad307b37a | 0.607287 | 2.943396 | false | false | false | false |
UdayanSinha/Code_Blocks | VHDL/Projects/work/test.vhd | 1 | 2,792 | ------------------------------------------------------
-- Four Bit Up-Down Counter
-- File Name : counter_sig.vhd
-- Data Type : std_logic_vector
-- Reset : Asynchronous
-- Active : Low
------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_signed.ALL;
entity counter_sig is
port ( UP, CLK, RESET : in std_logic;
OUT1 : out std_logic;
OUT2 : out std_logic_vector(3 downto 0)
);
end counter_sig;
architecture Arch_counter_sig of counter_sig is
signal COUNT : std_logic_vector(3 downto 0);
begin
-----------------------------------------------------
process (CLK, RESET)
begin
if RESET = '0' then
COUNT <= (others=>'0');
elsif clk'event AND clk='1' then
case UP is
when '1' => COUNT<=COUNT+1;
when others => COUNT<=COUNT-1;
end case;
end if;
end process;
-----------------------------------------------------
OUT1 <= '1' when (UP='1' and COUNT=15) or
(UP='0' and COUNT=0)
else '0';
OUT2 <= COUNT;
-----------------------------------------------------
end; -- Arch_counter_sig
---------------------------------------------------------
---
-- File Name: counter_sig2.vhd
---------------------------------------------------------
---
architecture Arch_counter_sig2 of counter_sig is
signal COUNT : std_logic_vector(3 downto 0);
begin
process (CLK, RESET)
begin
if RESET = '0' then
COUNT <= (others=>'0');
OUT1 <= '0';
OUT2 <= (others=>'0');
elsif clk'event AND clk='1' then
case UP is
when '1' => COUNT<=COUNT+1;
when others => COUNT<=COUNT-1;
end case;
if (UP='1' and COUNT=15) or (UP='0' and COUNT=0) then
OUT1 <= '1';
else
OUT1 <= '0';
end if;
OUT2 <= COUNT;
end if;
end process;
end; -- Arch_counter_sig2
------------------------------------------------------
-- File Name : counter_var.vhd
------------------------------------------------------
architecture Arch_counter_var of counter_sig is
begin
-----------------------------------------------------
process (CLK, RESET)
variable COUNT : std_logic_vector(3 downto 0);
begin
if RESET = '0' then
COUNT := (others=>'0');
OUT1 <= '0';
OUT2 <= (others=>'0');
elsif clk'event AND clk='1' then
case UP is
when '1' => COUNT:=COUNT+1;
when others=> COUNT:=COUNT-1;
end case;
if (UP='1' and COUNT=15) or (UP='0' and COUNT=0) then
OUT1 <= '1';
else
OUT1 <= '0';
end if;
OUT2 <= COUNT;
end if;
end process;
-----------------------------------------------------
end; -- Arch_counter_var
| mit | 0fbcea04d254798aef719e4c14c86ce8 | 0.424785 | 3.949081 | false | false | false | false |
freecores/gpib_controller | prototype_1/fpga/xilinx_prj/src/main.vhd | 1 | 14,280 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 22:17:28 01/24/2012
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.communication.ALL;
use work.wrapperComponents.ALL;
use work.helperComponents.ALL;
entity main is
port(
--reset : in std_logic;
clk : in std_logic;
------ UART ---------
RX : in std_logic;
TX : out std_logic;
------ GPIB ---------
DI : in std_logic_vector (7 downto 0);
DO : out std_logic_vector (7 downto 0);
ATN_in : in std_logic;
ATN_out : out std_logic;
DAV_in : in std_logic;
DAV_out : out std_logic;
NRFD_in : in std_logic;
NRFD_out : out std_logic;
NDAC_in : in std_logic;
NDAC_out : out std_logic;
EOI_in : in std_logic;
EOI_out : out std_logic;
SRQ_in : in std_logic;
SRQ_out : out std_logic;
IFC_in : in std_logic;
IFC_out : out std_logic;
REN_in : in std_logic;
REN_out : out std_logic;
------ LEDS ---------
led1 : out std_logic;
led2 : out std_logic
------ DEBUG --------
;debug1 : out std_logic
;debug2 : out std_logic
);
end main;
architecture Behavioral of main is
constant BUF_LEN_MAX_BIT_NUM : integer := 11;
type UART_REC_STATES is (
ST_UART_REC_READ_ADDR,
ST_UART_REC_READ_B1,
ST_UART_REC_READ_B2,
ST_UART_REC_READ_BURST_W_LEN_B1,
ST_UART_REC_READ_BURST_W_LEN_B2,
ST_UART_REC_BURST_READ
);
type UART_TR_STATES is (
ST_UART_TR_IDLE,
ST_UART_TR_WAIT_NOT_READY_TO_SEND_1,
ST_UART_TR_WRITE_B1,
ST_UART_TR_WAIT_NOT_READY_TO_SEND_2,
ST_UART_TR_WRITE_B2,
ST_UART_TR_WRITE_BURST,
ST_UART_TR_WAIT_BURST_NOT_READY_TO_SEND,
ST_UART_TR_WAIT_BURST_READY_TO_SEND
);
---------- global -------------
signal reset : std_logic;
signal reset_timer : integer range 0 to 50000000;
---------- UART ---------------
signal uart_reset, uart_clk, uart_RX, uart_TX, uart_data_out_ready,
uart_data_in_ready, uart_ready_to_send : std_logic;
signal uart_data_out, uart_data_in : std_logic_vector(7 downto 0);
---------- GPIB ------------------------
signal gpib_reset, gpib_clk : std_logic;
---------- GPIB interface signals ------
signal gpib_DI, gpib_DO : std_logic_vector (7 downto 0);
signal gpib_output_valid : std_logic;
signal gpib_ATN_in, gpib_ATN_out, gpib_DAV_in, gpib_DAV_out, gpib_NRFD_in,
gpib_NRFD_out, gpib_NDAC_in, gpib_NDAC_out, gpib_EOI_in, gpib_EOI_out,
gpib_SRQ_in, gpib_SRQ_out, gpib_IFC_in, gpib_IFC_out, gpib_REN_in,
gpib_REN_out : std_logic;
---------- registers access -------------
signal gpib_data_in, gpib_data_out : std_logic_vector(15 downto 0);
signal gpib_reg_addr : std_logic_vector(14 downto 0);
signal gpib_strobe_read, gpib_strobe_write : std_logic;
----------- writer strobe pulse generator
signal t_in_strobe_write, t_out_strobe_write : std_logic;
----------- reader strobe pulse generator
signal t_in_strobe_read, t_out_strobe_read : std_logic;
---------- interrupt line ---------------
signal gpib_interrupt_line : std_logic;
---------- UART transceiver -------------
signal uart_rec_state : UART_REC_STATES;
signal uart_strobe_write_s1, uart_strobe_write_s2 : std_logic;
signal uart_tr_state : UART_TR_STATES;
signal burstLen : std_logic_vector (BUF_LEN_MAX_BIT_NUM downto 0);
signal isBurstRead : std_logic;
signal subscribeBurstRead_1, subscribeBurstRead_2 : std_logic;
signal currentBurstReadLen : integer range 0 to 2**BUF_LEN_MAX_BIT_NUM;
-- GPIB synchronizer
signal gSync_clk : std_logic;
signal gSync_DI : std_logic_vector(7 downto 0);
signal gSync_DO : std_logic_vector(7 downto 0);
signal gSync_ATN_in : std_logic;
signal gSync_ATN_Out : std_logic;
signal gSync_DAV_in : std_logic;
signal gSync_DAV_out : std_logic;
signal gSync_NRFD_in : std_logic;
signal gSync_NRFD_out : std_logic;
signal gSync_NDAC_in : std_logic;
signal gSync_NDAC_out : std_logic;
signal gSync_EOI_in : std_logic;
signal gSync_EOI_out : std_logic;
signal gSync_SRQ_in : std_logic;
signal gSync_SRQ_out : std_logic;
signal gSync_IFC_in : std_logic;
signal gSync_IFC_out : std_logic;
signal gSync_REN_in : std_logic;
signal gSync_REN_out : std_logic;
begin
-- UART
uart_reset <= reset;
uart_clk <= clk;
uart_RX <= RX;
TX <= uart_TX;
-- GPIB sync
gSync_clk <= clk;
gSync_DI <= DI;
gSync_ATN_in <= ATN_in;
gSync_DAV_in <= DAV_in;
gSync_NRFD_in <= NRFD_in;
gSync_NDAC_in <= NDAC_in;
gSync_EOI_in <= EOI_in;
gSync_SRQ_in <= SRQ_in;
gSync_IFC_in <= IFC_in;
gSync_REN_in <= REN_in;
-- GPIB
gpib_reset <= reset;
gpib_clk <= clk;
gpib_DI <= not gSync_DO;
DO <= gpib_DO when gpib_output_valid = '1' else "00000000";
gpib_ATN_in <= not gSync_ATN_Out;
ATN_out <= gpib_ATN_out;
gpib_DAV_in <= not gSync_DAV_out;
DAV_out <= gpib_DAV_out;
gpib_NRFD_in <= not gSync_NRFD_out;
NRFD_out <= gpib_NRFD_out;
gpib_NDAC_in <= not gSync_NDAC_out;
NDAC_out <= gpib_NDAC_out;
gpib_EOI_in <= not gSync_EOI_out;
EOI_out <= gpib_EOI_out;
gpib_SRQ_in <= not gSync_SRQ_out;
SRQ_out <= gpib_SRQ_out;
gpib_IFC_in <= not gSync_IFC_out;
IFC_out <= gpib_IFC_out;
gpib_REN_in <= not gSync_REN_out;
REN_out <= gpib_REN_out;
-- DEBUG
--led1 <= reset;
led2 <= uart_data_out_ready;
--debug1 <= gpib_output_valid;
---------- receive from UART -----------
process (reset, uart_data_out_ready, uart_strobe_write_s2) begin
if reset = '1' then
uart_strobe_write_s1 <= uart_strobe_write_s2;
t_in_strobe_write <= '0';
subscribeBurstRead_1 <= '0';
uart_rec_state <= ST_UART_REC_READ_ADDR;
elsif rising_edge(uart_data_out_ready) then
case uart_rec_state is
when ST_UART_REC_READ_ADDR =>
gpib_reg_addr(14 downto 6) <= "000000000";
gpib_reg_addr(5 downto 0) <= uart_data_out(5 downto 0);
if uart_data_out(7) = '1' then
if uart_data_out(6) = '1' then
isBurstRead <= '1';
uart_rec_state <= ST_UART_REC_READ_BURST_W_LEN_B1;
else
uart_strobe_write_s1 <= not uart_strobe_write_s2;
uart_rec_state <= ST_UART_REC_READ_ADDR;
end if;
else
if uart_data_out(6) = '1' then
isBurstRead <= '0';
uart_rec_state <= ST_UART_REC_READ_BURST_W_LEN_B1;
else
uart_rec_state <= ST_UART_REC_READ_B1;
end if;
end if;
when ST_UART_REC_READ_B1 =>
gpib_data_in(7 downto 0) <= uart_data_out;
uart_rec_state <= ST_UART_REC_READ_B2;
when ST_UART_REC_READ_B2 =>
gpib_data_in(15 downto 8) <= uart_data_out;
t_in_strobe_write <= not t_out_strobe_write;
uart_rec_state <= ST_UART_REC_READ_ADDR;
-- burst length
when ST_UART_REC_READ_BURST_W_LEN_B1 =>
burstLen(7 downto 0) <= uart_data_out;
uart_rec_state <= ST_UART_REC_READ_BURST_W_LEN_B2;
when ST_UART_REC_READ_BURST_W_LEN_B2 =>
burstLen(11 downto 8) <= uart_data_out(3 downto 0);
if isBurstRead = '1' then
subscribeBurstRead_1 <= not subscribeBurstRead_2;
uart_rec_state <= ST_UART_REC_READ_ADDR;
else
uart_rec_state <= ST_UART_REC_BURST_READ;
end if;
when ST_UART_REC_BURST_READ =>
gpib_data_in(7 downto 0) <= uart_data_out;
t_in_strobe_write <= not t_out_strobe_write;
burstLen <= burstLen - 1;
if burstLen = "000000000001" then
uart_rec_state <= ST_UART_REC_READ_ADDR;
end if;
when others =>
uart_rec_state <= ST_UART_REC_READ_ADDR;
end case;
end if;
end process;
---------- write to UART ---------------------
process (reset, clk, uart_strobe_write_s1) begin
if reset = '1' then
uart_strobe_write_s2 <= uart_strobe_write_s1;
uart_data_in_ready <= '0';
t_in_strobe_read <= '0';
subscribeBurstRead_2 <= '0';
led1 <= '0';
uart_tr_state <= ST_UART_TR_IDLE;
elsif rising_edge(clk) then
case uart_tr_state is
when ST_UART_TR_IDLE =>
if uart_strobe_write_s2 /= uart_strobe_write_s1 and
uart_ready_to_send = '1' then
uart_strobe_write_s2 <= uart_strobe_write_s1;
uart_data_in <= gpib_data_out(7 downto 0);
uart_data_in_ready <= '1';
uart_tr_state <= ST_UART_TR_WAIT_NOT_READY_TO_SEND_1;
elsif subscribeBurstRead_1 /= subscribeBurstRead_2 and
uart_ready_to_send = '1' then
subscribeBurstRead_2 <= subscribeBurstRead_1;
currentBurstReadLen <= conv_integer(UNSIGNED(burstLen));
uart_tr_state <= ST_UART_TR_WRITE_BURST;
end if;
when ST_UART_TR_WAIT_NOT_READY_TO_SEND_1 =>
if uart_ready_to_send = '0' then
uart_data_in_ready <= '0';
uart_tr_state <= ST_UART_TR_WRITE_B1;
end if;
when ST_UART_TR_WRITE_B1 =>
if uart_ready_to_send = '1' then
uart_data_in <= gpib_data_out(15 downto 8);
uart_data_in_ready <= '1';
uart_tr_state <= ST_UART_TR_WAIT_NOT_READY_TO_SEND_2;
end if;
when ST_UART_TR_WAIT_NOT_READY_TO_SEND_2 =>
if uart_ready_to_send = '0' then
uart_data_in_ready <= '0';
uart_tr_state <= ST_UART_TR_WRITE_B2;
end if;
when ST_UART_TR_WRITE_B2 =>
if uart_ready_to_send = '1' then
t_in_strobe_read <= not t_out_strobe_read;
uart_tr_state <= ST_UART_TR_IDLE;
end if;
-- burst read
when ST_UART_TR_WRITE_BURST =>
if uart_ready_to_send = '1' then
uart_data_in <= gpib_data_out(7 downto 0);
uart_data_in_ready <= '1';
currentBurstReadLen <= currentBurstReadLen - 1;
led1 <= '1';
uart_tr_state <= ST_UART_TR_WAIT_BURST_NOT_READY_TO_SEND;
end if;
when ST_UART_TR_WAIT_BURST_NOT_READY_TO_SEND =>
if uart_ready_to_send = '0' then
uart_data_in_ready <= '0';
t_in_strobe_read <= not t_out_strobe_read;
uart_tr_state <= ST_UART_TR_WAIT_BURST_READY_TO_SEND;
end if;
when ST_UART_TR_WAIT_BURST_READY_TO_SEND =>
if uart_ready_to_send = '1' then
if currentBurstReadLen > 0 then
uart_tr_state <= ST_UART_TR_WRITE_BURST;
else
led1 <= '0';
uart_tr_state <= ST_UART_TR_IDLE;
end if;
end if;
when others =>
uart_tr_state <= ST_UART_TR_IDLE;
end case;
end if;
end process;
process (clk) begin
if rising_edge(clk) then
if reset_timer < 50000000 then
reset_timer <= reset_timer + 1;
reset <= '1';
else
reset <= '0';
end if;
end if;
end process;
uart0: Uart port map(
reset => uart_reset, clk => uart_clk, RX => uart_RX, TX => uart_TX,
data_out => uart_data_out, data_out_ready => uart_data_out_ready,
data_in => uart_data_in, data_in_ready => uart_data_in_ready,
ready_to_send => uart_ready_to_send
);
spg_strobe_write: SinglePulseGenerator generic map (WIDTH => 1) port map(
reset => reset, clk => clk,
t_in => t_in_strobe_write, t_out => t_out_strobe_write,
pulse => gpib_strobe_write
);
spg_strobe_read: SinglePulseGenerator generic map (WIDTH => 1) port map(
reset => reset, clk => clk,
t_in => t_in_strobe_read, t_out => t_out_strobe_read,
pulse => gpib_strobe_read
);
gpibSync: GpibSynchronizer port map (
clk => gSync_clk,
DI => gSync_DI,
DO => gSync_DO,
ATN_in => gSync_ATN_in,
ATN_out => gSync_ATN_Out,
DAV_in => gSync_DAV_in,
DAV_out => gSync_DAV_out,
NRFD_in => gSync_NRFD_in,
NRFD_out => gSync_NRFD_out,
NDAC_in => gSync_NDAC_in,
NDAC_out => gSync_NDAC_out,
EOI_in => gSync_EOI_in,
EOI_out => gSync_EOI_out,
SRQ_in => gSync_SRQ_in,
SRQ_out => gSync_SRQ_out,
IFC_in => gSync_IFC_in,
IFC_out => gSync_IFC_out,
REN_in => gSync_REN_in,
REN_out => gSync_REN_out
);
gpib0: RegsGpibFasade port map(
reset => gpib_reset, clk => gpib_clk,
DI => gpib_DI, DO => gpib_DO, output_valid => gpib_output_valid,
ATN_in => gpib_ATN_in, ATN_out => gpib_ATN_out,
DAV_in => gpib_DAV_in, DAV_out => gpib_DAV_out,
NRFD_in => gpib_NRFD_in, NRFD_out => gpib_NRFD_out,
NDAC_in => gpib_NDAC_in, NDAC_out => gpib_NDAC_out,
EOI_in => gpib_EOI_in, EOI_out => gpib_EOI_out,
SRQ_in => gpib_SRQ_in, SRQ_out => gpib_SRQ_out,
IFC_in => gpib_IFC_in, IFC_out => gpib_IFC_out,
REN_in => gpib_REN_in, REN_out => gpib_REN_out,
data_in => gpib_data_in, data_out => gpib_data_out,
reg_addr => gpib_reg_addr,
strobe_read => gpib_strobe_read,
strobe_write => gpib_strobe_write,
interrupt_line => gpib_interrupt_line,
debug1 => debug1, debug2 => debug2
);
end Behavioral;
| gpl-3.0 | 930ea1dcb214decb82835dbfa1e6032d | 0.593978 | 2.897139 | false | false | false | false |
Nooxet/embedded_bruteforce | vhdl/tb_controller.vhd | 2 | 3,646 | --------------------------------------------------------------------------------
-- Company:
-- Engineer: Noxet && Niklas
--
-- Create Date: 16:17:39 09/22/2014
-- Design Name:
-- Module Name: C:/Users/ael10jso/Xilinx/embedded_bruteforce/vhdl/tb_controller.vhd
-- Project Name: test_sg_top
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: controller
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_controller IS
END tb_controller;
ARCHITECTURE behavior OF tb_controller IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT controller
PORT(
clk : IN std_logic;
rstn : IN std_logic;
i_fsl_data_recv : IN std_logic;
i_fsl_hash : IN std_logic_vector(127 downto 0);
i_comp_eq : IN std_logic;
i_sg_done : IN std_logic;
i_sg_string : IN std_logic_vector(47 downto 0);
i_md5_done : IN std_logic;
o_passwd_hash : OUT std_logic_vector(127 downto 0);
o_pw_found : OUT std_logic;
o_passwd : OUT std_logic_vector(47 downto 0);
o_start_sg_comp : OUT std_logic;
o_start_md5 : OUT std_logic;
o_halt_sg : OUT std_logic;
o_demux_sel : OUT std_logic_vector(0 downto 0);
o_mux_sel : OUT std_logic_vector(0 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rstn : std_logic := '0';
signal i_fsl_data_recv : std_logic := '0';
signal i_fsl_hash : std_logic_vector(127 downto 0) := (others => '0');
signal i_comp_eq : std_logic := '0';
signal i_sg_done : std_logic := '0';
signal i_sg_string : std_logic_vector(47 downto 0) := (others => '0');
signal i_md5_done : std_logic := '0';
--Outputs
signal o_passwd_hash : std_logic_vector(127 downto 0);
signal o_pw_found : std_logic;
signal o_passwd : std_logic_vector(47 downto 0);
signal o_start_sg_comp : std_logic;
signal o_start_md5 : std_logic;
signal o_halt_sg : std_logic;
signal o_demux_sel : std_logic_vector(0 downto 0);
signal o_mux_sel : std_logic_vector(0 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: controller PORT MAP (
clk => clk,
rstn => rstn,
i_fsl_data_recv => i_fsl_data_recv,
i_fsl_hash => i_fsl_hash,
i_comp_eq => i_comp_eq,
i_sg_done => i_sg_done,
i_sg_string => i_sg_string,
i_md5_done => i_md5_done,
o_passwd_hash => o_passwd_hash,
o_pw_found => o_pw_found,
o_passwd => o_passwd,
o_start_sg_comp => o_start_sg_comp,
o_start_md5 => o_start_md5,
o_halt_sg => o_halt_sg,
o_demux_sel => o_demux_sel,
o_mux_sel => o_mux_sel
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 10 ns.
wait for 10 ns;
rstn <= '0';
wait for clk_period*10;
rstn <= '1';
i_fsl_hash <= x"e2fc714c4727ee9395f324cd2e7f331f";
i_fsl_data_recv <= '1'; -- catch the data!
wait for clk_period;
--i_sg_string <=
wait;
end process;
END;
| mit | 034cab5e275436eb9073a2fdaba196d3 | 0.558694 | 3.246661 | false | false | false | false |
kb3gtn/mojo_modulator | vhdl/src/cos_phase_table.vhd | 1 | 5,287 | -----------------------------------------------------------
-- cos_phase_table.vhd
--
-- Lookup 16bit value from a cos(x) table.
-- Table resolution is 12 bits (4096 entries)
--
-- y = cos(x) -- where x is digital phase Q
--
-- Q = (radian/2*pi)*((2^phase_depth))
-- or if you talk degrees
-- Q = ( degrees/360)*((2^phase_depth))
--
--
-- Peter Fetterer (KB3GTN)
-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
entity cos_phase_table is
generic (
constant sample_depth : integer := 16; -- number of bits in output sample (1->N)
constant phase_depth : integer := 12 -- number of bits for phase input value (1->N)
);
port (
i_clk : in std_logic; -- input DSP clock
i_srst : in std_logic; -- input sync reset to dsp clock
---------------------------------------------------------
x : in unsigned( phase_depth-1 downto 0 ); -- digital normalized phase input (0->2*pi)
y : out signed( sample_depth-1 downto 0 ) -- output value signed 16b
);
end entity cos_phase_table;
architecture system of cos_phase_table is
----------------------------------
-- lookup table
-- pre-compute at compile time..
----------------------------------
constant memory_depth : integer := 2**phase_depth; -- how many memory entries do we need.
constant SCALE : real := real((2**(real(sample_depth)-1.0))-1.0); -- cos is normal 1.0 we want 2^(N-1)-1 (will all be positive values)
constant STEP : real := 1.0/(real(2**phase_depth)); -- phase increment per table entry (0->90 degrees)
-- memory table is 1/4 cos period, 1024 phase enteries of 16 bit samples
-- taking advantage of cos symmetry for the other 3/4 of the period.
type cos_table_mem is array ( 0 to memory_depth ) of signed( sample_depth-1 downto 0);
-- function to fill in cos_table_mem
function init_lookuptable return cos_table_mem is
variable tmp_mem : cos_table_mem;
begin
-- phase table is only 0.25 + 1 sample of the total period. (0 -> 1024, 1025 entries)
for i in 0 to integer((2**real(phase_depth))) loop
tmp_mem(i) := to_signed( integer( round( cos(real(MATH_2_PI*(real(i)*STEP)))*SCALE)), 16 );
end loop;
return tmp_mem;
end;
-- This is the lookup table, should synth into 1 blockram on Xilinx parts.
constant cos_lookup : cos_table_mem := init_lookuptable;
----------------------------
-- Design Signals
----------------------------
signal ref_phase : unsigned(9 downto 0); -- lower 10 bits of X
signal base_phase : unsigned(10 downto 0); -- base phase 0 -> 90 degrees
signal inv_sample_out : std_logic; -- output sample needs to be inverted.
signal quadrant : unsigned(1 downto 0); -- phase quadrant requested
begin
quadrant <= x(11 downto 10); -- upper 2 bits of phase give's us quadrant
ref_phase <= x(9 downto 0); -- phase within quadrant
compute_base_phase : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' ) then
base_phase <= (others=>'0');
inv_sample_out <= '0';
else
case quadrant is
when "00" =>
-- requested direct entry in table.
-- 0 -> >90 degrees
base_phase <= ("0" & ref_phase);
inv_sample_out <= '0';
when "01" =>
-- request second quadrante
-- 90 -> >180 degrees
-- map 2nd quad phase to 1st quad phase
base_phase <= "10000000000" - ("0" & ref_phase); -- 180 degrees - ref_phase => phase in quad 1.
inv_sample_out <= '1'; -- invert the base_base from quad1 to get quad2's value.
when "10" =>
-- request third quad
-- 180 -> >270
-- map 3rd quad phase to 1st quad phase
base_phase <= ("1" & ref_phase) - "10000000000"; -- just subtract 180 degrees
inv_sample_out <= '1'; -- invert magnatude
when "11" =>
-- request forth quad
-- 270 -> >360 (360 is zero)
-- map 4th quad to 1st quad phase
base_phase <= "10000000000" - ( "0" & ref_phase);
inv_sample_out <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
generate_sample : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( inv_sample_out = '1' ) then
-- invert sample before outputing ( invert and add 1 )
y <= not cos_lookup( to_integer(base_phase) ) + 1;
else
-- normal output
y <= cos_lookup( to_integer(base_phase) );
end if;
end if;
end process;
end architecture system;
| apache-2.0 | 5092570ee15b2cbb76a6fe3608aa26a7 | 0.49442 | 4.179447 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/pcores/bajsd_v1_00_a/hdl/vhdl/md5_working.vhd | 1 | 14,788 | --library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
--entity MD5 is
-- Port( Clk : in std_logic;
-- Reset : in std_logic;
-- Run : in std_logic;
-- FirstRun : in std_logic;
-- w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15 : in std_logic_vector(31 downto 0);
-- Done : out std_logic;
-- Hash_1, Hash_2, Hash_3, Hash_4 : out std_logic_vector(31 downto 0));
--end MD5;
--
--architecture Behavioral of MD5 is
--
----Initial Constants for Words A, B, C, and D
--constant aa : std_logic_vector(31 downto 0) := x"67452301";
--constant bb : std_logic_vector(31 downto 0) := x"EFCDAB89";
--constant cc : std_logic_vector(31 downto 0) := x"98BADCFE";
--constant dd : std_logic_vector(31 downto 0) := x"10325476";
--
--subtype arr8 is STD_LOGIC_VECTOR (7 downto 0);
--subtype arr32 is STD_LOGIC_VECTOR (31 downto 0);
--
----R[64] is used to determine the amount of left rotation
--type Rarray is array (63 downto 0) of arr8;
--constant R : Rarray :=( x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06",
-- x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04",
-- x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05",
-- x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07");
--
--
----K[64] = floor(abs(sin(i)) * 2^32)
--type Karray is array (63 downto 0) of arr32;
--constant K : Karray :=( x"eb86d391", x"2ad7d2bb", x"bd3af235", x"f7537e82", x"4e0811a1", x"a3014314", x"fe2ce6e0", x"6fa87e4f", x"85845dd1",
-- x"ffeff47d", x"8f0ccc92", x"655b59c3", x"fc93a039", x"ab9423a7", x"432aff97", x"f4292244", x"c4ac5665", x"1fa27cf8",
-- x"e6db99e5", x"d9d4d039", x"04881d05", x"d4ef3085", x"eaa127fa", x"289b7ec6", x"bebfbc70", x"f6bb4b60", x"4bdecfa9",
-- x"a4beea44", x"fde5380c", x"6d9d6122", x"8771f681", x"fffa3942", x"8d2a4c8a", x"676f02d9", x"fcefa3f8", x"a9e3e905",
-- x"455a14ed", x"f4d50d87", x"c33707d6", x"21e1cde6", x"e7d3fbc8", x"d8a1e681", x"02441453", x"d62f105d", x"e9b6c7aa",
-- x"265e5a51", x"c040b340", x"f61e2562", x"49b40821", x"a679438e", x"fd987193", x"6b901122", x"895cd7be", x"ffff5bb1",
-- x"8b44f7af", x"698098d8", x"fd469501", x"a8304613", x"4787c62a", x"f57c0faf", x"c1bdceee", x"242070db", x"e8c7b756",
-- x"d76aa478");
--
--type Warray is array (15 downto 0) of arr32;
--signal W : Warray;
--signal a, b, c, d, f : std_logic_vector(31 downto 0);
--signal g : integer range 0 to 15;
--signal i : integer range 0 to 64;
--
--type ctrl_state is (Halt, Process_1, Process_2, Process_3, Process_4, Waiting, Finished);
--signal State, Next_state : ctrl_state;
--
--begin
-- Assign_Next_State : process (Clk, Reset)
-- begin
-- if (Reset = '1') then
-- State <= Halt;
-- elsif (rising_edge(clk)) then
-- State <= Next_State;
-- end if;
-- end process;
--
-- Get_Next_State : process (State, Run, FirstRun, i)
-- begin
-- case State is
-- when Halt =>
-- if (FirstRun = '0') then
-- Next_state <= Halt;
-- else
-- Next_state <= Process_1;
-- end if;
-- when Process_1 => --Each Process is one of the four stages in the MD5 Algorithm
-- if(i = 15) then
-- Next_state <= Process_2;
-- else
-- Next_state <= Process_1;
-- end if;
-- when Process_2 =>
-- if(i = 31) then
-- Next_state <= Process_3;
-- else
-- Next_state <= Process_2;
-- end if;
-- when Process_3 =>
-- if(i = 47) then
-- Next_state <= Process_4;
-- else
-- Next_state <= Process_3;
-- end if;
-- when Process_4 =>
-- if(i = 63) then
-- Next_state <= Finished;
-- else
-- Next_state <= Process_4;
-- end if;
-- when Finished =>
-- Next_state <= Waiting;
-- when Waiting =>
-- if (Run = '0') then
-- Next_state <= Waiting;
-- else
-- Next_state <= Process_1;
-- end if;
-- when others =>
-- Next_state <= Halt;
-- end case;
-- end process;
--
-- Control_States : process (state, a, b, c, d, i)
-- begin
-- Done <= '0';
-- Hash_1 <= x"00000000";
-- Hash_2 <= x"00000000";
-- Hash_3 <= x"00000000";
-- Hash_4 <= x"00000000";
--
-- f <= x"00000000";
-- g <= 0;
-- case State is
-- when Process_1 =>
-- f <= (b and c) or ((not b) and d);
-- g <= i;
-- when Process_2 =>
-- f <= (d and b) or ((not d) and c);
-- g <= (((5*i) + 1) mod 16);
-- when Process_3 =>
-- f <= b xor c xor d;
-- g <= ((3*i) + 5) mod 16;
-- when Process_4 =>
-- f <= c xor (b or (not d));
-- g <= (7*i) mod 16;
-- when Finished =>
-- Done <= '1';
-- Hash_1 <= aa + a;
-- Hash_2 <= bb + b;
-- Hash_3 <= cc + c;
-- Hash_4 <= dd + d;
-- when others =>
-- NULL;
-- end case;
-- end process;
-- Process_MD5 : process (state, a, b, c, d, i, W, clk)
-- begin
-- if (rising_edge(clk)) then
-- case State is
-- when Halt =>
-- i <= 0;
-- a <= aa;
-- b <= bb;
-- c <= cc;
-- d <= dd;
--
-- W(0) <= w0;
-- W(1) <= w1;
-- W(2) <= w2;
-- W(3) <= w3;
-- W(4) <= w4;
-- W(5) <= w5;
-- W(6) <= w6;
-- W(7) <= w7;
-- W(8) <= w8;
-- W(9) <= w9;
-- W(10) <= w10;
-- W(11) <= w11;
-- W(12) <= w12;
-- W(13) <= w13;
-- W(14) <= w14;
-- W(15) <= w15;
-- when Process_1 =>
-- d <= c;
-- c <= b;
-- --Shift Left OR'ed with the Equivalent Shift Right is the same as Left Rotation
-- b <= b + (SHL((a + f + K(i) + W(g)), R(i)) or SHR((a + f + K(i) + W(g)), ("00100000" - R(i))));
-- a <= d;
-- i <= i + 1;
-- when Process_2 =>
-- d <= c;
-- c <= b;
-- --Shift Left OR'ed with the Equivalent Shift Right is the same as Left Rotation
-- b <= b + (SHL((a + f + K(i) + W(g)), R(i)) or SHR((a + f + K(i) + W(g)), ("00100000" - R(i))));
-- a <= d;
-- i <= i + 1;
-- when Process_3 =>
-- d <= c;
-- c <= b;
-- b <= b + (SHL((a + f + K(i) + W(g)), R(i)) or SHR((a + f + K(i) + W(g)), ("00100000" - R(i))));
-- a <= d;
-- i <= i + 1;
-- when Process_4 =>
-- d <= c;
-- c <= b;
-- b <= b + (SHL((a + f + K(i) + W(g)), R(i)) or SHR((a + f + K(i) + W(g)), ("00100000" - R(i))));
-- a <= d;
-- i <= i + 1;
-- when Waiting =>
-- i <= 0;
-- a <= aa;
-- b <= bb;
-- c <= cc;
-- d <= dd;
--
-- W(0) <= w0;
-- W(1) <= w1;
-- W(2) <= w2;
-- W(3) <= w3;
-- W(4) <= w4;
-- W(5) <= w5;
-- W(6) <= w6;
-- W(7) <= w7;
-- W(8) <= w8;
-- W(9) <= w9;
-- W(10) <= w10;
-- W(11) <= w11;
-- W(12) <= w12;
-- W(13) <= w13;
-- W(14) <= w14;
-- W(15) <= w15;
-- when others =>
-- NULL;
-- end case;
-- end if;
-- end process;
--end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--use ieee.numeric_bit.all;
entity MD5 is
port (
clk : in std_logic;
rstn : in std_logic;
i_start : in std_logic;
--i_data : in unsigned(71 downto 0); -- 8 chars + 1 appended bit
i_data_0 : in unsigned(31 downto 0); -- first 4 chars
i_data_1 : in unsigned(31 downto 0); -- next 4 chars
i_length : in std_logic_vector(7 downto 0); -- nbr of chars
o_done : out std_logic;
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end MD5;
architecture Behavioral of MD5 is
-- the initialization values of the loop variables --
constant a_init : unsigned(31 downto 0) := x"67452301";
constant b_init : unsigned(31 downto 0) := x"EFCDAB89";
constant c_init : unsigned(31 downto 0) := x"98BADCFE";
constant d_init : unsigned(31 downto 0) := x"10325476";
-- the array with the init values --
type w_array is array(15 downto 0) of unsigned(31 downto 0);
signal w_c, w_n : w_array; --w_n
-- loop signals --
signal a_c, a_n, b_c, b_n, c_c, c_n, d_c, d_n, f : unsigned(31 downto 0);
signal i_c, i_n : integer range 0 to 63;
signal g : integer range 0 to 15;
-- the states for the main loop --
type state is (stage_1, stage_2, stage_3, stage_4, waiting, finished, set_output);
signal state_c, state_n : state;
-- Specifies the amount to shift in the main loop, use rotate_left() --
type s_array is array(63 downto 0) of unsigned(7 downto 0);
constant s : s_array :=( x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06",
x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04",
x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05",
x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07");
-- 15 0f 0a 06 17 10 0b 04 14 0e 09 05 16 11 0c 07
-- fixed amount to add during the rotation --
type k_array is array(63 downto 0) of unsigned(31 downto 0);
constant k : k_array :=( x"eb86d391", x"2ad7d2bb", x"bd3af235", x"f7537e82", x"4e0811a1", x"a3014314", x"fe2ce6e0", x"6fa87e4f", x"85845dd1",
x"ffeff47d", x"8f0ccc92", x"655b59c3", x"fc93a039", x"ab9423a7", x"432aff97", x"f4292244", x"c4ac5665", x"1fa27cf8",
x"e6db99e5", x"d9d4d039", x"04881d05", x"d4ef3085", x"eaa127fa", x"289b7ec6", x"bebfbc70", x"f6bb4b60", x"4bdecfa9",
x"a4beea44", x"fde5380c", x"6d9d6122", x"8771f681", x"fffa3942", x"8d2a4c8a", x"676f02d9", x"fcefa3f8", x"a9e3e905",
x"455a14ed", x"f4d50d87", x"c33707d6", x"21e1cde6", x"e7d3fbc8", x"d8a1e681", x"02441453", x"d62f105d", x"e9b6c7aa",
x"265e5a51", x"c040b340", x"f61e2562", x"49b40821", x"a679438e", x"fd987193", x"6b901122", x"895cd7be", x"ffff5bb1",
x"8b44f7af", x"698098d8", x"fd469501", x"a8304613", x"4787c62a", x"f57c0faf", x"c1bdceee", x"242070db", x"e8c7b756",
x"d76aa478");
-- begin the Behavioral --
begin
-- the clock process --
clk_proc: process(clk)
begin
if rising_edge(clk) then
if rstn = '0' then
state_c <= waiting;
-- reset the main loop signals --
i_c <= 0;
a_c <= a_init;
b_c <= b_init;
c_c <= c_init;
d_c <= d_init;
w_c <= (others => (others => '0'));
else
state_c <= state_n;
i_c <= i_n;
a_c <= a_n;
b_c <= b_n;
c_c <= c_n;
d_c <= d_n;
w_c <= w_n;
end if;
end if;
end process;
-- the state control --
FSM: process(state_c, i_start, i_c)
begin
-- defaults --
state_n <= state_c;
case state_c is
when waiting =>
if i_start = '0' then
state_n <= waiting;
else
state_n <= stage_1;
end if;
when stage_1 =>
if i_c = 15 then -- state change depending on the counter
state_n <= stage_2;
else
state_n <= stage_1;
end if;
when stage_2 =>
if i_c = 31 then
state_n <= stage_3;
else
state_n <= stage_2;
end if;
when stage_3 =>
if i_c = 47 then
state_n <= stage_4;
else
state_n <= stage_3;
end if;
when stage_4 =>
if i_c = 63 then
state_n <= finished;
else
state_n <= stage_4;
end if;
when finished =>
state_n <= waiting;
when others =>
null;
end case;
end process;
-- set the outputs and update f & g --
data_path: process(a_c, b_c, c_c, d_c, f, g, i_c, w_c, state_c, i_data_0, i_data_1, i_length)
begin
-- set standard values --
o_done <= '0';
o_hash_0 <= (others => '0');
o_hash_1 <= (others => '0');
o_hash_2 <= (others => '0');
o_hash_3 <= (others => '0');
f <= (others => '0');
g <= 0;
w_n <= w_c;
-- set init vector-data values --
-- --w(0) <= i_data_0;
-- --w(1) <= i_data_1;
-- w_n(0) <= (others => '0');
-- w_n(1) <= (others => '0');
-- w_n(2) <= (others => '0');
-- w_n(3) <= (others => '0');
-- w_n(4) <= (others => '0');
-- w_n(5) <= (others => '0');
-- w_n(6) <= (others => '0');
-- w_n(7) <= (others => '0');
-- w_n(8) <= (others => '0');
-- w_n(9) <= (others => '0');
-- w_n(10) <= (others => '0');
-- w_n(11) <= (others => '0');
-- w_n(12) <= (others => '0');
-- w_n(13) <= (others => '0');
-- w_n(14) <= (others => '0');
-- --w_n(14) <= unsigned(x"000000" & i_length);
-- w_n(15) <= (others => '0');
-- main loop signals calc set as standard values --
d_n <= c_c;
c_n <= b_c;
b_n <= b_c + rotate_left(a_c + k(i_c) + w_c(g) + f, to_integer(s(i_c)));
a_n <= d_c;
if i_c < 63 then
i_n <= i_c + 1;
else
i_n <= i_c;
end if;
case state_c is
when waiting =>
i_n <= 0;
a_n <= a_init;
b_n <= b_init;
c_n <= c_init;
d_n <= d_init;
w_n(0) <= i_data_0;
w_n(1) <= i_data_1;
w_n(14) <= unsigned(x"000000" & i_length);
when stage_1 =>
f <= (b_c and c_c) or ((not b_c) and d_c);
g <= i_c;-- mod 16; CHECK THIS!!
when stage_2 =>
f <= (d_c and b_c) or ((not d_c) and c_c);
g <= ((5 * i_c) + 1) mod 16;
when stage_3 =>
f <= b_c xor c_c xor d_c;
g <= ((3 * i_c) + 5) mod 16;
when stage_4 =>
f <= c_c xor (b_c or (not d_c));
g <= (7 * i_c) mod 16;
when finished =>
o_done <= '1';
o_hash_0 <= (a_init + a_c);
o_hash_1 <= (b_init + b_c);
o_hash_2 <= (c_init + c_c);
o_hash_3 <= (d_init + d_c);
when others => null;
end case;
end process;
end Behavioral;
| mit | fe37685d2e2178c2f4e6f6c25a7f982b | 0.467744 | 2.41792 | false | false | false | false |
esar/hdmilight-v2 | fpga/avr/prog_mem.vhd | 1 | 15,778 | -------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: prog_mem - Behavioral
-- Create Date: 14:09:04 10/30/2009
-- Description: the program memory of a CPU.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
entity prog_mem is
port ( I_CLK : in std_logic;
I_CE : in std_logic;
I_WAIT : in std_logic;
I_PC : in std_logic_vector(15 downto 0); -- word address
I_PM_ADR : in std_logic_vector(15 downto 0); -- byte address
Q_OPC : out std_logic_vector(31 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_PM_DOUT : out std_logic_vector( 7 downto 0));
end prog_mem;
architecture Behavioral of prog_mem is
constant zero_256 : bit_vector := X"00000000000000000000000000000000"
& X"00000000000000000000000000000000";
signal M_OPC_E1 : std_logic_vector(15 downto 0);
signal M_OPC_E2 : std_logic_vector(15 downto 0);
signal M_OPC_E3 : std_logic_vector(15 downto 0);
signal M_OPC_E4 : std_logic_vector(15 downto 0);
signal M_OPC_E5 : std_logic_vector(15 downto 0);
signal M_OPC_E6 : std_logic_vector(15 downto 0);
signal M_OPC_O1 : std_logic_vector(15 downto 0);
signal M_OPC_O2 : std_logic_vector(15 downto 0);
signal M_OPC_O3 : std_logic_vector(15 downto 0);
signal M_OPC_O4 : std_logic_vector(15 downto 0);
signal M_OPC_O5 : std_logic_vector(15 downto 0);
signal M_OPC_O6 : std_logic_vector(15 downto 0);
signal M_PMD_E1 : std_logic_vector(15 downto 0);
signal M_PMD_E2 : std_logic_vector(15 downto 0);
signal M_PMD_E3 : std_logic_vector(15 downto 0);
signal M_PMD_E4 : std_logic_vector(15 downto 0);
signal M_PMD_E5 : std_logic_vector(15 downto 0);
signal M_PMD_E6 : std_logic_vector(15 downto 0);
signal M_PMD_O1 : std_logic_vector(15 downto 0);
signal M_PMD_O2 : std_logic_vector(15 downto 0);
signal M_PMD_O3 : std_logic_vector(15 downto 0);
signal M_PMD_O4 : std_logic_vector(15 downto 0);
signal M_PMD_O5 : std_logic_vector(15 downto 0);
signal M_PMD_O6 : std_logic_vector(15 downto 0);
signal L_WAIT_N : std_logic;
signal L_PC_0 : std_logic;
signal L_PC_13_11 : std_logic_vector( 2 downto 0);
signal L_PC_E : std_logic_vector(10 downto 1);
signal L_PC_O : std_logic_vector(10 downto 1);
signal L_PMD : std_logic_vector(15 downto 0);
signal L_PM_ADR_1_0 : std_logic_vector( 1 downto 0);
signal L_PM_ADR_14_12 : std_logic_vector( 2 downto 0);
begin
pe1 : RAMB16_S18_S18
generic map(INIT_00 => X"00000000000000000000000000000000000000000000000095082411940c940e")
port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_E1, DOB => M_PMD_E1,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
pe2 : RAMB16_S18_S18
port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_E2, DOB => M_PMD_E2,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
pe3 : RAMB16_S18_S18
port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_E3, DOB => M_PMD_E3,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
pe4 : RAMB16_S18_S18
port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_E4, DOB => M_PMD_E4,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
pe5 : RAMB16_S18_S18
port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_E5, DOB => M_PMD_E5,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
pe6 : RAMB16_S18_S18
port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_E6, DOB => M_PMD_E6,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
po1 : RAMB16_S18_S18
generic map(INIT_00 => X"0000000000000000000000000000000000000000000000000000be1300000004")
port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_O1, DOB => M_PMD_O1,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
po2 : RAMB16_S18_S18
port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_O2, DOB => M_PMD_O2,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
po3 : RAMB16_S18_S18
port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_O3, DOB => M_PMD_O3,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
po4 : RAMB16_S18_S18
port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_O4, DOB => M_PMD_O4,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
po5 : RAMB16_S18_S18
port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_O5, DOB => M_PMD_O5,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
po6 : RAMB16_S18_S18
port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_O6, DOB => M_PMD_O6,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
-- remember I_PC0 and I_PM_ADR for the output mux.
--
pc0: process(I_CLK)
begin
if (I_CE = '1' and rising_edge(I_CLK)) then
Q_PC <= I_PC;
L_PM_ADR_1_0 <= I_PM_ADR(1 downto 0);
L_PM_ADR_14_12 <= I_PM_ADR(14 downto 12);
if ((I_WAIT = '0')) then
L_PC_0 <= I_PC(0);
L_PC_13_11 <= I_PC(13 downto 11);
end if;
end if;
end process;
L_WAIT_N <= I_CE and (not I_WAIT);
-- we use two memory blocks _E and _O (even and odd).
-- This gives us a quad-port memory so that we can access
-- I_PC, I_PC + 1, and PM simultaneously.
--
-- I_PC and I_PC + 1 are handled by port A of the memory while PM
-- is handled by port B.
--
-- Q_OPC(15 ... 0) shall contain the word addressed by I_PC, while
-- Q_OPC(31 ... 16) shall contain the word addressed by I_PC + 1.
--
-- There are two cases:
--
-- case A: I_PC is even, thus I_PC + 1 is odd
-- case B: I_PC + 1 is odd , thus I_PC is even
--
L_PC_O <= I_PC(10 downto 1);
L_PC_E <= I_PC(10 downto 1) + ("000000000" & I_PC(0));
Q_OPC(15 downto 0) <= M_OPC_E1 when L_PC_13_11 = "000" and L_PC_0 = '0' else
M_OPC_E2 when L_PC_13_11 = "001" and L_PC_0 = '0' else
M_OPC_E3 when L_PC_13_11 = "010" and L_PC_0 = '0' else
M_OPC_E4 when L_PC_13_11 = "011" and L_PC_0 = '0' else
M_OPC_E5 when L_PC_13_11 = "100" and L_PC_0 = '0' else
M_OPC_E6 when L_PC_13_11 = "101" and L_PC_0 = '0' else
M_OPC_O1 when L_PC_13_11 = "000" and L_PC_0 = '1' else
M_OPC_O2 when L_PC_13_11 = "001" and L_PC_0 = '1' else
M_OPC_O3 when L_PC_13_11 = "010" and L_PC_0 = '1' else
M_OPC_O4 when L_PC_13_11 = "011" and L_PC_0 = '1' else
M_OPC_O5 when L_PC_13_11 = "100" and L_PC_0 = '1' else
M_OPC_O6;
Q_OPC(31 downto 16) <= M_OPC_E1 when L_PC_13_11 = "000" and L_PC_0 = '1' else
M_OPC_E2 when L_PC_13_11 = "001" and L_PC_0 = '1' else
M_OPC_E3 when L_PC_13_11 = "010" and L_PC_0 = '1' else
M_OPC_E4 when L_PC_13_11 = "011" and L_PC_0 = '1' else
M_OPC_E5 when L_PC_13_11 = "100" and L_PC_0 = '1' else
M_OPC_E6 when L_PC_13_11 = "101" and L_PC_0 = '1' else
M_OPC_O1 when L_PC_13_11 = "000" and L_PC_0 = '0' else
M_OPC_O2 when L_PC_13_11 = "001" and L_PC_0 = '0' else
M_OPC_O3 when L_PC_13_11 = "010" and L_PC_0 = '0' else
M_OPC_O4 when L_PC_13_11 = "011" and L_PC_0 = '0' else
M_OPC_O5 when L_PC_13_11 = "100" and L_PC_0 = '0' else
M_OPC_O6;
--Q_OPC(15 downto 0) <= M_OPC_E when L_PC_0 = '0' else M_OPC_O;
--Q_OPC(31 downto 16) <= M_OPC_E when L_PC_0 = '1' else M_OPC_O;
L_PMD <= M_PMD_E1 when L_PM_ADR_14_12 = "000" and L_PM_ADR_1_0(1) = '0' else
M_PMD_O1 when L_PM_ADR_14_12 = "000" and L_PM_ADR_1_0(1) = '1' else
M_PMD_E2 when L_PM_ADR_14_12 = "001" and L_PM_ADR_1_0(1) = '0' else
M_PMD_O2 when L_PM_ADR_14_12 = "001" and L_PM_ADR_1_0(1) = '1' else
M_PMD_E3 when L_PM_ADR_14_12 = "010" and L_PM_ADR_1_0(1) = '0' else
M_PMD_O3 when L_PM_ADR_14_12 = "010" and L_PM_ADR_1_0(1) = '1' else
M_PMD_E4 when L_PM_ADR_14_12 = "011" and L_PM_ADR_1_0(1) = '0' else
M_PMD_O4 when L_PM_ADR_14_12 = "011" and L_PM_ADR_1_0(1) = '1' else
M_PMD_E5 when L_PM_ADR_14_12 = "100" and L_PM_ADR_1_0(1) = '0' else
M_PMD_O5 when L_PM_ADR_14_12 = "100" and L_PM_ADR_1_0(1) = '1' else
M_PMD_E6 when L_PM_ADR_14_12 = "101" and L_PM_ADR_1_0(1) = '0' else
M_PMD_O6;
--L_PMD <= M_PMD_E when (L_PM_ADR_1_0(1) = '0') else M_PMD_O;
Q_PM_DOUT <= L_PMD(7 downto 0) when (L_PM_ADR_1_0(0) = '0')
else L_PMD(15 downto 8);
end Behavioral;
| gpl-2.0 | 0372522f264756439fef82753905df0d | 0.410952 | 3.3308 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib/if_func_AH.vhd | 1 | 4,455 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 01:04:57 10/01/2011
-- Design Name:
-- Module Name: if_func_AH - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.utilPkg.all;
entity if_func_AH is
port(
-- device inputs
clk : in std_logic; -- clock
pon : in std_logic; -- power on
rdy : in std_logic; -- ready for next message
tcs : in std_logic; -- take control synchronously
-- state inputs
LACS : in std_logic; -- listener active state
LADS : in std_logic; -- listener addressed state
-- interface inputs
ATN : in std_logic; -- attention
DAV : in std_logic; -- data accepted
-- interface outputs
RFD : out std_logic; -- ready for data
DAC : out std_logic; -- data accepted
-- reported state
ANRS : out std_logic; -- acceptor not ready state
ACDS : out std_logic -- accept data state
);
end if_func_AH;
architecture Behavioral of if_func_AH is
-- states
type AH_STATE is (
-- acceptor idle state
ST_AIDS,
-- acceptor not ready state
ST_ANRS,
-- acceptor ready state
ST_ACRS,
-- acceptor wait for new cycle state
ST_AWNS,
-- accept data state
ST_ACDS
);
-- current state
signal current_state : AH_STATE;
-- events
signal event1, event2, event3, event4, event5, event6, event7 : boolean;
-- timers
constant TIMER_T3_MAX : integer := 3;
constant TIMER_T3_TIMEOUT : integer := 2;
signal timerT3 : integer range 0 to TIMER_T3_MAX;
signal timerT3Expired : boolean;
begin
-- state machine process
process(pon, clk) begin
if pon = '1' then
current_state <= ST_AIDS;
elsif rising_edge(clk) then
case current_state is
------------------
when ST_AIDS =>
if event2 then
-- no state change
elsif event1 then
current_state <= ST_ANRS;
end if;
------------------
when ST_ANRS =>
if event2 then
current_state <= ST_AIDS;
elsif event4 then
current_state <= ST_ACRS;
end if;
------------------
when ST_ACRS =>
if event2 then
current_state <= ST_AIDS;
elsif event5 then
current_state <= ST_ANRS;
elsif event6 then
timerT3 <= 0;
current_state <= ST_ACDS;
end if;
------------------
when ST_ACDS =>
if event2 then
current_state <= ST_AIDS;
elsif event3 then
current_state <= ST_AWNS;
end if;
if timerT3 < TIMER_T3_MAX then
timerT3 <= timerT3 + 1;
end if;
------------------
when ST_AWNS =>
if event2 then
current_state <= ST_AIDS;
elsif event7 then
current_state <= ST_ANRS;
end if;
------------------
when others =>
current_state <= ST_AIDS;
end case;
end if;
end process;
-- events
event1 <= ATN='1' or LACS='1' or LADS='1';
event2 <= not(ATN='1' or LACS='1' or LADS='1');
event3 <= (rdy='0' and ATN='0') or (timerT3Expired and ATN='1');
event4 <= (ATN='1' or rdy='1') and tcs='0';
event5 <= not (ATN='1' or rdy='1');
event6 <= DAV = '1';
event7 <= DAV = '0';
-- timers
timerT3Expired <= timerT3 >= TIMER_T3_TIMEOUT;
RFD <= to_stdl(
current_state = ST_AIDS or
current_state = ST_ACRS
);
DAC <= to_stdl(
current_state = ST_AIDS or
current_state = ST_AWNS
);
ACDS <= to_stdl(current_state = ST_ACDS);
ANRS <= to_stdl(current_state = ST_ANRS);
end Behavioral;
| gpl-3.0 | e044772eeabaab3626a0ce3297391b13 | 0.58743 | 3.375 | false | false | false | false |
alonho/game_of_life_vhdl | board.vhdl | 2 | 6,304 |
package matrix_pkg is
constant X: integer := 4;
constant Y: integer := 4;
type matrix is array(0 to X, 0 to Y) of integer range 0 to 1;
end package matrix_pkg;
use work.matrix_pkg.all;
entity board is
generic (
init_state : matrix
);
port (
mat: inout matrix;
clock: in integer range 0 to 1
);
end board;
architecture arch of board is
component cell
generic (
start_alive : integer range 0 to 1
);
port (
clock,
upper_left, upper, upper_right,
left, right,
lower_left, lower, lower_right : in integer range 0 to 1;
alive : inout integer range 0 to 1
);
end component;
begin
outer:
for i in 0 to X generate
begin
inner:
for j in 0 to Y generate
begin
upper_left:
if (i = 0 and j = 0) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => 0,
upper => 0,
upper_right => 0,
left => 0,
right => mat(i + 1, j),
lower_left => 0,
lower => mat(i, j + 1),
lower_right => mat(i + 1, j + 1),
alive => mat(i, j));
end generate upper_left;
upper:
if (i > 0 and i < X and j = 0) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => 0,
upper => 0,
upper_right => 0,
left => mat(i - 1, j),
right => mat(i + 1, j),
lower_left => mat(i - 1, j + 1),
lower => mat(i, j + 1),
lower_right => mat(i + 1, j + 1),
alive => mat(i, j));
end generate upper;
upper_right:
if (i = X and j = 0) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => 0,
upper => 0,
upper_right => 0,
left => mat(i - 1, j),
right => 0,
lower_left => mat(i - 1, j + 1),
lower => mat(i, j + 1),
lower_right => 0,
alive => mat(i, j));
end generate upper_right;
left:
if (i = 0 and j > 0 and j < Y) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => 0,
upper => mat(i, j - 1),
upper_right => mat(i + 1, j - 1),
left => 0,
right => mat(i + 1, j),
lower_left => 0,
lower => mat(i, j + 1),
lower_right => mat(i + 1, j + 1),
alive => mat(i, j));
end generate left;
middle:
if (i > 0 and i < X and j > 0 and j < Y) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => mat(i - 1, j - 1),
upper => mat(i, j - 1),
upper_right => mat(i + 1, j - 1),
left => mat(i - 1, j),
right => mat(i + 1, j),
lower_left => mat(i - 1, j + 1),
lower => mat(i, j + 1),
lower_right => mat(i + 1, j + 1),
alive => mat(i, j));
end generate middle;
right:
if (i = X and j > 0 and j < Y) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => mat(i - 1, j - 1),
upper => mat(i, j - 1),
upper_right => 0,
left => mat(i - 1, j),
right => 0,
lower_left => mat(i - 1, j + 1),
lower => mat(i, j + 1),
lower_right => 0,
alive => mat(i, j));
end generate right;
lower_left:
if (i = 0 and j = Y) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => 0,
upper => mat(i, j - 1),
upper_right => mat(i + 1, j - 1),
left => 0,
right => mat(i + 1, j),
lower_left => 0,
lower => 0,
lower_right => 0,
alive => mat(i, j));
end generate lower_left;
lower:
if (i > 0 and i < X and j = Y) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => mat(i - 1, j - 1),
upper => mat(i, j - 1),
upper_right => mat(i + 1, j - 1),
left => mat(i - 1, j),
right => mat(i + 1, j),
lower_left => 0,
lower => 0,
lower_right => 0,
alive => mat(i, j));
end generate lower;
lower_right:
if (i = X and j = Y) generate
cell: entity work.cell
generic map
(start_alive => init_state(i, j))
port map
(clock => clock,
upper_left => mat(i - 1, j - 1),
upper => mat(i, j - 1),
upper_right => 0,
left => mat(i - 1, j),
right => 0,
lower_left => 0,
lower => 0,
lower_right => 0,
alive => mat(i, j));
end generate lower_right;
end generate inner;
end generate outer;
end arch;
| bsd-3-clause | 456bd9f95736b3ece623db3bdaa595b1 | 0.381187 | 4.120261 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/cmdfifo/simulation/cmdfifo_tb.vhd | 3 | 6,334 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cmdfifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.cmdfifo_pkg.ALL;
ENTITY cmdfifo_tb IS
END ENTITY;
ARCHITECTURE cmdfifo_arch OF cmdfifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from cmdfifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of cmdfifo_synth
cmdfifo_synth_inst:cmdfifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 20
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| bsd-2-clause | 92b83f05353a861539cec4fd2f8955fe | 0.611936 | 4.169849 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/system_stub.vhd | 1 | 1,520 | -------------------------------------------------------------------------------
-- system_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_stub is
port (
RS232_Uart_1_sout : out std_logic;
RS232_Uart_1_sin : in std_logic;
RESET : in std_logic;
Push_Buttons_4Bits_TRI_I : in std_logic_vector(0 to 3);
LEDs_8Bits_TRI_O : out std_logic_vector(7 downto 0);
GCLK : in std_logic;
DIP_Switches_8Bits_TRI_I : in std_logic_vector(7 downto 0)
);
end system_stub;
architecture STRUCTURE of system_stub is
component system is
port (
RS232_Uart_1_sout : out std_logic;
RS232_Uart_1_sin : in std_logic;
RESET : in std_logic;
Push_Buttons_4Bits_TRI_I : in std_logic_vector(0 to 3);
LEDs_8Bits_TRI_O : out std_logic_vector(7 downto 0);
GCLK : in std_logic;
DIP_Switches_8Bits_TRI_I : in std_logic_vector(7 downto 0)
);
end component;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system : component is "user_black_box";
begin
system_i : system
port map (
RS232_Uart_1_sout => RS232_Uart_1_sout,
RS232_Uart_1_sin => RS232_Uart_1_sin,
RESET => RESET,
Push_Buttons_4Bits_TRI_I => Push_Buttons_4Bits_TRI_I,
LEDs_8Bits_TRI_O => LEDs_8Bits_TRI_O,
GCLK => GCLK,
DIP_Switches_8Bits_TRI_I => DIP_Switches_8Bits_TRI_I
);
end architecture STRUCTURE;
| mit | 96e0926a2ef421b67510c96e8d275f7f | 0.578289 | 3.275862 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_HLS/rtl/source/lloyds_algorithm_wrapper.vhd | 1 | 7,440 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- lloyds_algorithm_wrapper - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity lloyds_algorithm_wrapper is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
data_value_V_dout : IN STD_LOGIC_VECTOR (47 downto 0);
data_value_V_empty_n : IN STD_LOGIC;
data_value_V_read : OUT STD_LOGIC;
cntr_pos_init_value_V_dout : IN STD_LOGIC_VECTOR (47 downto 0);
cntr_pos_init_value_V_empty_n : IN STD_LOGIC;
cntr_pos_init_value_V_read : OUT STD_LOGIC;
n_V : IN STD_LOGIC_VECTOR (14 downto 0);
k_V : IN STD_LOGIC_VECTOR (7 downto 0);
distortion_out_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
distortion_out_V_full_n : IN STD_LOGIC;
distortion_out_V_write : OUT STD_LOGIC;
clusters_out_value_V_din : OUT STD_LOGIC_VECTOR (47 downto 0);
clusters_out_value_V_full_n : IN STD_LOGIC;
clusters_out_value_V_write : OUT STD_LOGIC
);
end lloyds_algorithm_wrapper;
architecture Behavioral of lloyds_algorithm_wrapper is
component lloyds_algorithm_top is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
data_value_V_dout : IN STD_LOGIC_VECTOR (47 downto 0);
data_value_V_empty_n : IN STD_LOGIC;
data_value_V_read : OUT STD_LOGIC;
cntr_pos_init_value_V_dout : IN STD_LOGIC_VECTOR (47 downto 0);
cntr_pos_init_value_V_empty_n : IN STD_LOGIC;
cntr_pos_init_value_V_read : OUT STD_LOGIC;
n_V : IN STD_LOGIC_VECTOR (14 downto 0);
k_V : IN STD_LOGIC_VECTOR (7 downto 0);
distortion_out_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
distortion_out_V_full_n : IN STD_LOGIC;
distortion_out_V_write : OUT STD_LOGIC;
clusters_out_value_V_din : OUT STD_LOGIC_VECTOR (47 downto 0);
clusters_out_value_V_full_n : IN STD_LOGIC;
clusters_out_value_V_write : OUT STD_LOGIC
);
end component;
signal tmp_clk : std_logic;
signal ap_rst_reg : std_logic;
signal ap_start_reg : std_logic;
signal ap_done_tmp : std_logic;
signal ap_done_reg : std_logic;
signal ap_idle_tmp : std_logic;
signal ap_idle_reg : std_logic;
signal data_value_V_dout_reg : std_logic_vector (47 downto 0);
signal data_value_V_empty_n_reg : std_logic;
signal data_value_V_read_tmp : std_logic;
signal data_value_V_read_reg : std_logic;
signal cntr_pos_init_value_V_dout_reg : std_logic_vector (47 downto 0);
signal cntr_pos_init_value_V_empty_n_reg : std_logic;
signal cntr_pos_init_value_V_read_tmp : std_logic;
signal cntr_pos_init_value_V_read_reg : std_logic;
signal n_V_reg : std_logic_vector (14 downto 0);
signal k_V_reg : std_logic_vector (7 downto 0);
signal root_V_reg : std_logic_vector (14 downto 0);
signal distortion_out_V_din_tmp : std_logic_vector (31 downto 0);
signal distortion_out_V_din_reg : std_logic_vector (31 downto 0);
signal distortion_out_V_full_n_reg : std_logic;
signal distortion_out_V_write_tmp : std_logic;
signal distortion_out_V_write_reg : std_logic;
signal clusters_out_value_V_din_tmp : std_logic_vector (47 downto 0);
signal clusters_out_value_V_din_reg : std_logic_vector (47 downto 0);
signal clusters_out_value_V_full_n_reg : std_logic;
signal clusters_out_value_V_write_tmp : std_logic;
signal clusters_out_value_V_write_reg : std_logic;
begin
ClkBuffer: IBUFG
port map (
I => ap_clk,
O => tmp_clk
);
input_reg : process(tmp_clk)
begin
if rising_edge(tmp_clk) then
ap_rst_reg <= ap_rst;
ap_start_reg <= ap_start;
data_value_V_dout_reg <= data_value_V_dout;
data_value_V_empty_n_reg <= data_value_V_empty_n;
cntr_pos_init_value_V_dout_reg <= cntr_pos_init_value_V_dout;
cntr_pos_init_value_V_empty_n_reg <= cntr_pos_init_value_V_empty_n;
n_V_reg <= n_V;
k_V_reg <= k_V;
distortion_out_V_full_n_reg <= distortion_out_V_full_n;
clusters_out_value_V_full_n_reg <= clusters_out_value_V_full_n;
end if;
end process input_reg;
lloyds_alogrithm_top_inst : lloyds_algorithm_top
port map(
ap_clk => tmp_clk,
ap_rst => ap_rst_reg,
ap_start => ap_start_reg,
ap_done => ap_done_tmp,
ap_idle => ap_idle_tmp,
data_value_V_dout => data_value_V_dout_reg,
data_value_V_empty_n => data_value_V_empty_n_reg,
data_value_V_read => data_value_V_read_tmp,
cntr_pos_init_value_V_dout => cntr_pos_init_value_V_dout_reg,
cntr_pos_init_value_V_empty_n => cntr_pos_init_value_V_empty_n_reg,
cntr_pos_init_value_V_read => cntr_pos_init_value_V_read_tmp,
n_V => n_V_reg,
k_V => k_V_reg,
distortion_out_V_din => distortion_out_V_din_tmp,
distortion_out_V_full_n => distortion_out_V_full_n_reg,
distortion_out_V_write => distortion_out_V_write_tmp,
clusters_out_value_V_din => clusters_out_value_V_din_tmp,
clusters_out_value_V_full_n => clusters_out_value_V_full_n_reg,
clusters_out_value_V_write => clusters_out_value_V_write_tmp
);
output_reg : process(tmp_clk)
begin
if rising_edge(tmp_clk) then
ap_done_reg <= ap_done_tmp;
ap_idle_reg <= ap_idle_tmp;
data_value_V_read_reg <= data_value_V_read_tmp;
cntr_pos_init_value_V_read_reg <= cntr_pos_init_value_V_read_tmp;
distortion_out_V_din_reg <= distortion_out_V_din_tmp;
distortion_out_V_write_reg <= distortion_out_V_write_tmp;
clusters_out_value_V_din_reg <= clusters_out_value_V_din_tmp;
clusters_out_value_V_write_reg <= clusters_out_value_V_write_tmp;
end if;
end process output_reg;
ap_done <= ap_done_reg;
ap_idle <= ap_idle_reg;
data_value_V_read <= data_value_V_read_reg;
cntr_pos_init_value_V_read <= cntr_pos_init_value_V_read_reg;
distortion_out_V_din <= distortion_out_V_din_reg;
distortion_out_V_write <= distortion_out_V_write_reg;
clusters_out_value_V_din <= clusters_out_value_V_din_reg;
clusters_out_value_V_write <= clusters_out_value_V_write_reg;
end Behavioral;
| bsd-3-clause | aba37bf0cc9d5d0499a5bd6e3e61f0f7 | 0.572446 | 3.297872 | false | false | false | false |
esar/hdmilight-v2 | fpga/uart_tx.vhd | 2 | 2,644 | library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------------------
-- UART Transmitter ---------------------------------------------------------
entity uart_tx is
generic (
fullbit : integer );
port (
clk : in std_logic;
reset : in std_logic;
--
din : in std_logic_vector(7 downto 0);
wr : in std_logic;
busy : out std_logic;
--
txd : out std_logic );
end uart_tx;
-----------------------------------------------------------------------------
-- Implemenattion -----------------------------------------------------------
architecture rtl of uart_tx is
constant halfbit : integer := fullbit / 2;
-- Signals
signal bitcount : integer range 0 to 10;
signal count : integer range 0 to fullbit;
signal shiftreg : std_logic_vector(7 downto 0);
begin
proc: process(clk, reset)
begin
if reset='1' then
count <= 0;
bitcount <= 0;
busy <= '0';
txd <= '1';
elsif clk'event and clk='1' then
if count/=0 then
count <= count - 1;
else
if bitcount=0 then
busy <= '0';
if wr='1' then -- START BIT
shiftreg <= din;
busy <= '1';
txd <= '0';
bitcount <= bitcount + 1;
count <= fullbit;
end if;
elsif bitcount=9 then -- STOP BIT
txd <= '1';
bitcount <= 0;
count <= fullbit;
else -- DATA BIT
shiftreg(6 downto 0) <= shiftreg(7 downto 1);
txd <= shiftreg(0);
bitcount <= bitcount + 1;
count <= fullbit;
end if;
end if;
end if;
end process;
end rtl; | gpl-2.0 | ffaef6d7bcb91bcdd0c9fcb91ed66a85 | 0.279879 | 6.221176 | false | false | false | false |
mithro/HDMI2USB | hdl/jpeg_encoder/design/CtrlSM.vhd | 5 | 12,699 | -------------------------------------------------------------------------------
-- File Name : CtrlSM.vhd
--
-- Project : JPEG_ENC
--
-- Module : CtrlSM
--
-- Content : CtrlSM
--
-- Description : CtrlSM core
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity CtrlSM is
port
(
CLK : in std_logic;
RST : in std_logic;
-- output IF
outif_almost_full : in std_logic;
-- HOST IF
sof : in std_logic;
img_size_x : in std_logic_vector(15 downto 0);
img_size_y : in std_logic_vector(15 downto 0);
jpeg_ready : out std_logic;
jpeg_busy : out std_logic;
-- FDCT
fdct_start : out std_logic;
fdct_ready : in std_logic;
fdct_sm_settings : out T_SM_SETTINGS;
-- ZIGZAG
zig_start : out std_logic;
zig_ready : in std_logic;
zig_sm_settings : out T_SM_SETTINGS;
-- Quantizer
qua_start : out std_logic;
qua_ready : in std_logic;
qua_sm_settings : out T_SM_SETTINGS;
-- RLE
rle_start : out std_logic;
rle_ready : in std_logic;
rle_sm_settings : out T_SM_SETTINGS;
-- Huffman
huf_start : out std_logic;
huf_ready : in std_logic;
huf_sm_settings : out T_SM_SETTINGS;
-- ByteStuffdr
bs_start : out std_logic;
bs_ready : in std_logic;
bs_sm_settings : out T_SM_SETTINGS;
-- JFIF GEN
jfif_start : out std_logic;
jfif_ready : in std_logic;
jfif_eoi : out std_logic;
-- OUT MUX
out_mux_ctrl : out std_logic
);
end entity CtrlSM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of CtrlSM is
constant NUM_STAGES : integer := 6;
constant CMP_MAX : std_logic_vector(2 downto 0) := "100";
type T_STATE is (IDLES, JFIF, HORIZ, COMP, VERT, EOI);
type ARR_FSM is array(NUM_STAGES downto 1) of std_logic_vector(1 downto 0);
type T_ARR_SM_SETTINGS is array(NUM_STAGES+1 downto 1) of T_SM_SETTINGS;
signal Reg : T_ARR_SM_SETTINGS;
signal main_state : T_STATE;
signal start : std_logic_vector(NUM_STAGES+1 downto 1);
signal idle : std_logic_vector(NUM_STAGES+1 downto 1);
signal start_PB : std_logic_vector(NUM_STAGES downto 1);
signal ready_PB : std_logic_vector(NUM_STAGES downto 1);
signal fsm : ARR_FSM;
signal start1_d : std_logic;
signal RSM : T_SM_SETTINGS;
signal out_mux_ctrl_s : std_logic;
signal out_mux_ctrl_s2 : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fdct_sm_settings <= Reg(1);
zig_sm_settings <= Reg(2);
qua_sm_settings <= Reg(3);
rle_sm_settings <= Reg(4);
huf_sm_settings <= Reg(5);
bs_sm_settings <= Reg(6);
fdct_start <= start_PB(1);
ready_PB(1) <= fdct_ready;
zig_start <= start_PB(2);
ready_PB(2) <= zig_ready;
qua_start <= start_PB(3);
ready_PB(3) <= qua_ready;
rle_start <= start_PB(4);
ready_PB(4) <= rle_ready;
huf_start <= start_PB(5);
ready_PB(5) <= huf_ready;
bs_start <= start_PB(6);
ready_PB(6) <= bs_ready;
-----------------------------------------------------------------------------
-- CTRLSM 1..NUM_STAGES
-----------------------------------------------------------------------------
G_S_CTRL_SM : for i in 1 to NUM_STAGES generate
-- CTRLSM 1..NUM_STAGES
U_S_CTRL_SM : entity work.SingleSM
port map
(
CLK => CLK,
RST => RST,
-- from/to SM(m)
start_i => start(i),
idle_o => idle(i),
-- from/to SM(m+1)
idle_i => idle(i+1),
start_o => start(i+1),
-- from/to processing block
pb_rdy_i => ready_PB(i),
pb_start_o => start_PB(i),
-- state out
fsm_o => fsm(i)
);
end generate G_S_CTRL_SM;
idle(NUM_STAGES+1) <= not outif_almost_full;
-------------------------------------------------------------------
-- Regs
-------------------------------------------------------------------
G_REG_SM : for i in 1 to NUM_STAGES generate
p_reg1 : process(CLK, RST)
begin
if RST = '1' then
Reg(i) <= C_SM_SETTINGS;
elsif CLK'event and CLK = '1' then
if start(i) = '1' then
if i = 1 then
Reg(i).x_cnt <= RSM.x_cnt;
Reg(i).y_cnt <= RSM.y_cnt;
Reg(i).cmp_idx <= RSM.cmp_idx;
else
Reg(i) <= Reg(i-1);
end if;
end if;
end if;
end process;
end generate G_REG_SM;
-------------------------------------------------------------------
-- Main_SM
-------------------------------------------------------------------
p_main_sm : process(CLK, RST)
begin
if RST = '1' then
main_state <= IDLES;
start(1) <= '0';
start1_d <= '0';
jpeg_ready <= '0';
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= (others => '0');
jpeg_busy <= '0';
RSM.cmp_idx <= (others => '0');
out_mux_ctrl_s <= '0';
out_mux_ctrl_s2 <= '0';
jfif_eoi <= '0';
out_mux_ctrl <= '0';
jfif_start <= '0';
elsif CLK'event and CLK = '1' then
start(1) <= '0';
start1_d <= start(1);
jpeg_ready <= '0';
jfif_start <= '0';
out_mux_ctrl_s2 <= out_mux_ctrl_s;
out_mux_ctrl <= out_mux_ctrl_s2;
case main_state is
-------------------------------
-- IDLE
-------------------------------
when IDLES =>
if sof = '1' then
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= (others => '0');
jfif_start <= '1';
out_mux_ctrl_s <= '0';
jfif_eoi <= '0';
main_state <= JFIF;
end if;
-------------------------------
-- JFIF
-------------------------------
when JFIF =>
if jfif_ready = '1' then
out_mux_ctrl_s <= '1';
main_state <= HORIZ;
end if;
-------------------------------
-- HORIZ
-------------------------------
when HORIZ =>
if RSM.x_cnt < unsigned(img_size_x) then
main_state <= COMP;
else
RSM.x_cnt <= (others => '0');
main_state <= VERT;
end if;
-------------------------------
-- COMP
-------------------------------
when COMP =>
if idle(1) = '1' and start(1) = '0' then
if RSM.cmp_idx < unsigned(CMP_MAX) then
start(1) <= '1';
else
RSM.cmp_idx <= (others => '0');
RSM.x_cnt <= RSM.x_cnt + 16;
main_state <= HORIZ;
end if;
end if;
-------------------------------
-- VERT
-------------------------------
when VERT =>
if RSM.y_cnt < unsigned(img_size_y)-8 then
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= RSM.y_cnt + 8;
main_state <= HORIZ;
else
if idle(NUM_STAGES+1 downto 1) = (NUM_STAGES+1 downto 1 => '1') then
main_state <= EOI;
jfif_eoi <= '1';
out_mux_ctrl_s <= '0';
jfif_start <= '1';
end if;
end if;
-------------------------------
-- VERT
-------------------------------
when EOI =>
if jfif_ready = '1' then
jpeg_ready <= '1';
main_state <= IDLES;
end if;
-------------------------------
-- others
-------------------------------
when others =>
main_state <= IDLES;
end case;
if start1_d = '1' then
RSM.cmp_idx <= RSM.cmp_idx + 1;
end if;
if main_state = IDLES then
jpeg_busy <= '0';
else
jpeg_busy <= '1';
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | bsd-2-clause | 0ad832a1718babdf8f6c818076e7e994 | 0.365462 | 4.619498 | false | false | false | false |
Nooxet/embedded_bruteforce | vhdl/controller.vhd | 2 | 5,645 | ----------------------------------------------------------------------------------
-- Engineer: Noxet && Niklas
--
-- Create Date: 14:56:58 09/22/2014
-- Module Name: controller - Behavioral
-- Description:
-- The Brutus system controller
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity controller is
generic (
N : integer := 1
);
port (
clk : in std_logic;
rstn : in std_logic;
i_fsl_data_recv : in std_logic;
i_fsl_hash : in std_logic_vector(127 downto 0);
i_comp_eq : in std_logic; -- check if password was found
i_sg_done : in std_logic; -- string generator done signal
i_sg_string : in std_logic_vector(47 downto 0); -- current potential password
i_md5_done : in std_logic; -- done signal from the main MD5 core
o_passwd_hash : out std_logic_vector(127 downto 0); -- hash from FSL
o_pw_found : out std_logic; -- flag to indicate password found
-- o_pw_nfound : out ---
o_passwd : out std_logic_vector(47 downto 0); -- password string, send to user
o_start_sg_comp : out std_logic; -- start signals to sg and comp
o_start_md5 : out std_logic; -- start signal to MD5 cores
o_halt_sg : out std_logic; -- halt signal to sg
o_demux_sel : out unsigned(N-1 downto 0); --
o_mux_sel : out unsigned(N-1 downto 0) -- select signals to DEMUX/MUX
);
end controller;
architecture Behavioral of controller is
type states is (wait_fsl, calc_md5, wait_md5, comp_md5, send_fsl);
signal state_c, state_n : states;
signal dm_count_c, dm_count_n : unsigned(N-1 downto 0); -- DEMUX selector counter
signal m_count_c, m_count_n : unsigned(N-1 downto 0); -- MUX selector counter
type pw_buff_array is array(N-1 downto 0) of std_logic_vector(47 downto 0);
signal pw_buff_c, pw_buff_n : pw_buff_array;
signal jaevla_raeknare_c, jaevla_raeknare_n : unsigned(1 downto 0);
begin
clk_proc: process(clk)
begin
if rising_edge(clk) then
if rstn = '0' then
state_c <= wait_fsl;
dm_count_c <= (others => '0');
m_count_c <= (others => '0');
pw_buff_c <= (others => (others => '0'));
jaevla_raeknare_c <= (others => '0');
else
state_c <= state_n;
dm_count_c <= dm_count_n;
m_count_c <= m_count_n;
pw_buff_c <= pw_buff_n;
jaevla_raeknare_c <= jaevla_raeknare_n;
end if;
end if;
end process;
fsm_proc: process(state_c, i_fsl_data_recv, i_comp_eq, i_sg_done, i_md5_done, i_sg_string, pw_buff_c, m_count_c, dm_count_c, jaevla_raeknare_c)
begin
-- defaults --
o_start_sg_comp <= '0';
o_start_md5 <= '0';
o_halt_sg <= '0';
dm_count_n <= dm_count_c;
m_count_n <= m_count_c;
o_passwd <= (others => '0');
o_pw_found <= '0';
pw_buff_n <= pw_buff_c;
state_n <= state_c;
jaevla_raeknare_n <= jaevla_raeknare_c;
case state_c is
-- KOLLA IFALL SG ÄR FÄRDIG, ISÅFALL HOPPA TILL /DEV/NULL --
when wait_fsl =>
dm_count_n <= (others => '0');
m_count_n <= (others => '0');
if i_fsl_data_recv = '1' then
state_n <= calc_md5;
o_start_sg_comp <= '1';
end if;
when calc_md5 =>
o_start_md5 <= '1'; -- start MD5 cores
dm_count_n <= dm_count_c + 1;
pw_buff_n(to_integer(dm_count_c)) <= i_sg_string; -- buffer the sg passwords
if dm_count_c = N-1 then -- should be N-1? CHECK THIS, we now
-- halt everything...
dm_count_n <= (others => '0');
o_halt_sg <= '1'; -- halt the sg while crunching MD5 hashes
state_n <= wait_md5;
end if;
-- wait for the main MD5 core to be finished
when wait_md5 =>
o_halt_sg <= '1'; -- halt until done
if i_md5_done = '1' then
state_n <= comp_md5;
m_count_n <= m_count_c + 1;
end if;
when comp_md5 => -- rename to a better name
o_halt_sg <= '1'; -- TEST
m_count_n <= m_count_c + 1;
if i_comp_eq = '1' then
o_passwd <= pw_buff_c(to_integer(m_count_c));
o_pw_found <= '1';
state_n <= wait_fsl; -- back to init state
elsif m_count_c = N-1 then
m_count_n <= m_count_c;
if jaevla_raeknare_c = 1 then
m_count_n <= (others => '0');
jaevla_raeknare_n <= (others => '0');
state_n <= calc_md5; -- if pwd not found, calculate next hash
o_halt_sg <= '0';
else
jaevla_raeknare_n <= jaevla_raeknare_c + 1;
end if;
end if;
when others => null;
end case;
end process;
-- pass through signal --
o_passwd_hash <= i_fsl_hash;
o_demux_sel <= dm_count_c;
o_mux_sel <= m_count_c;
end Behavioral;
| mit | ed75f4723f0967998021ad8bd04ef706 | 0.466253 | 3.550314 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/ISE/fuck_vga/test.vhd | 1 | 1,220 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:50:45 10/15/2014
-- Design Name:
-- Module Name: test - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test is
port (
clk : in std_logic;
rst : in std_logic;
o : out std_logic_vector(9 downto 0)
);
end test;
architecture Behavioral of test is
signal c, n : unsigned(9 downto 0);
begin
clk_proc: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
c <= (others => '0');
else
c <= n;
end if;
end if;
end process;
n <= c + 1;
o <= std_logic_vector(c);
end Behavioral;
| mit | 0d9dfc1c6fc4a02cb7040a16e518e1a4 | 0.568852 | 3.536232 | false | true | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/source/vhdl/divider_top.vhd | 1 | 6,177 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: divider_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.lloyds_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity divider_top is
generic (
ROUND : boolean := false
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
dividend : in data_type_ext;
divisor : in coord_type;
rdy : out std_logic;
quotient : out data_type;
divide_by_zero : out std_logic
);
end divider_top;
architecture Behavioral of divider_top is
constant QUOTIENT_BITWIDTH : integer := COORD_BITWIDTH_EXT;
constant FRACTIONAL_BITWIDTH : integer := COORD_BITWIDTH_EXT-COORD_BITWIDTH;
type divider_result_type is array(0 to D-1) of std_logic_vector(QUOTIENT_BITWIDTH+FRACTIONAL_BITWIDTH-1 downto 0);
type quotient_type is array(0 to D-1) of std_logic_vector(QUOTIENT_BITWIDTH-1 downto 0);
component divider
port (
aclk : IN std_logic;
s_axis_divisor_tvalid : IN std_logic;
--s_axis_divisor_tready : OUT std_logic;
s_axis_divisor_tdata : IN std_logic_vector(COORD_BITWIDTH-1 DOWNTO 0);
s_axis_dividend_tvalid : IN std_logic;
--s_axis_dividend_tready : OUT std_logic;
s_axis_dividend_tdata : IN std_logic_vector(COORD_BITWIDTH_EXT-1 DOWNTO 0);
m_axis_dout_tvalid : OUT std_logic;
m_axis_dout_tdata : OUT std_logic_vector(QUOTIENT_BITWIDTH+FRACTIONAL_BITWIDTH-1 DOWNTO 0)
--m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
end component;
component divider_v3_0
port (
clk : IN std_logic;
sclr : IN std_logic;
s_axis_divisor_tvalid : IN std_logic;
divisor : IN std_logic_vector(COORD_BITWIDTH-1 DOWNTO 0);
dividend : IN std_logic_vector(COORD_BITWIDTH_EXT-1 DOWNTO 0);
quotient: OUT std_logic_vector(QUOTIENT_BITWIDTH-1 DOWNTO 0);
fractional : OUT std_logic_vector(FRACTIONAL_BITWIDTH-1 downto 0)
);
end component;
component dsp_round
generic (
BITWIDTH_IN : integer := 32;
BITWIDTH_OUT : integer := 32
);
port (
sclr : in std_logic;
nd : in std_logic;
AB_IN : in std_logic_vector (BITWIDTH_IN-1 downto 0);
CARRYIN_IN : in std_logic;
CLK_IN : in std_logic;
C_IN : in std_logic_vector (BITWIDTH_IN-1 downto 0);
P_OUT : out std_logic_vector (BITWIDTH_OUT-1 downto 0);
rdy : out std_logic
);
end component;
signal tmp_divisor : coord_type;
signal divider_result : divider_result_type;
signal tmp_quotient : quotient_type;
signal divider_valid : std_logic_vector(0 to D-1);
signal tmp_divide_by_zero : std_logic_vector(0 to D-1);
signal round_valid : std_logic_vector(0 to D-1);
signal c_in_const : std_logic_vector(COORD_BITWIDTH_EXT-1 downto 0);
begin
c_in_const(QUOTIENT_BITWIDTH-1 downto QUOTIENT_BITWIDTH-FRACTIONAL_BITWIDTH-1) <= (others => '0');
c_in_const(QUOTIENT_BITWIDTH-FRACTIONAL_BITWIDTH-2 downto 0) <= (others => '1');
tmp_divisor <= std_logic_vector(to_unsigned(1,COORD_BITWIDTH)) WHEN divisor = std_logic_vector(to_unsigned(0,COORD_BITWIDTH)) ELSE divisor;
G_DIV : for I in 0 to D-1 generate
divider_inst : divider
port map (
aclk => clk,
s_axis_divisor_tvalid => nd,
--s_axis_divisor_tready => open,
s_axis_divisor_tdata => tmp_divisor,
s_axis_dividend_tvalid => nd,
--s_axis_dividend_tready => open,
s_axis_dividend_tdata => dividend(I),
m_axis_dout_tvalid => divider_valid(I),
m_axis_dout_tdata => divider_result(I)
--m_axis_dout_tuser(0) => tmp_divide_by_zero(I)
);
tmp_quotient(I) <= divider_result(I)(QUOTIENT_BITWIDTH+FRACTIONAL_BITWIDTH-1 downto FRACTIONAL_BITWIDTH);
G_ROUND : if ROUND = true generate
dsp_round_inst : dsp_round
generic map (
BITWIDTH_IN => COORD_BITWIDTH_EXT,
BITWIDTH_OUT => COORD_BITWIDTH
)
port map (
sclr => sclr,
nd => divider_valid(I),
AB_IN => divider_result(I)(COORD_BITWIDTH_EXT-1 downto 0),
CARRYIN_IN => divider_result(I)(COORD_BITWIDTH_EXT-1), -- round towards zero
CLK_IN => clk,
C_IN => c_in_const,
P_OUT => quotient(I),
rdy => round_valid(I)
);
end generate G_ROUND;
G_NO_ROUND : if ROUND = false generate
quotient(I) <= divider_result(I)(QUOTIENT_BITWIDTH-1 downto FRACTIONAL_BITWIDTH);
end generate G_NO_ROUND;
end generate G_DIV;
G_NO_ROUND_1 : if ROUND = false generate
rdy <= divider_valid(0);
end generate G_NO_ROUND_1;
G_ROUND_1 : if ROUND = true generate
rdy <= round_valid(0);
end generate G_ROUND_1;
divide_by_zero <= '0';--tmp_divide_by_zero(0);
end Behavioral;
| bsd-3-clause | a008246d998537ffe66b7327f9833e0c | 0.546706 | 4.055811 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib_helper/SerialPollCoordinator.vhd | 1 | 2,702 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: SerialPollCoordinator
-- Date:2011-11-03
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SerialPollCoordinator is
port (
-- clock
clk : in std_logic;
-- reset
reset : in std_logic;
-- data accepted
DAC : in std_logic;
-- receive status byte
rec_stb : in std_logic;
-- attention in
ATN_in : in std_logic;
-- attention out
ATN_out : out std_logic;
-- output valid in
output_valid_in : in std_logic;
-- output valid out
output_valid_out : out std_logic;
-- stb received
stb_received : out std_logic
);
end SerialPollCoordinator;
architecture arch of SerialPollCoordinator is
-- serial poll coordinator states
type SPC_STATE is (
ST_IDLE,
ST_WAIT_DAC,
ST_WAIT_REC_STB_0
);
signal current_state : SPC_STATE;
begin
ATN_out <= '0' when current_state = ST_WAIT_DAC else ATN_in;
output_valid_out <= '0' when current_state = ST_WAIT_DAC else output_valid_in;
stb_received <= '1' when current_state = ST_WAIT_REC_STB_0 else '0';
process (clk, reset) begin
if reset = '1' then
current_state <= ST_IDLE;
elsif rising_edge(clk) then
case current_state is
when ST_IDLE =>
if rec_stb='1' then
current_state <= ST_WAIT_DAC;
end if;
when ST_WAIT_DAC =>
if DAC='1' then
current_state <= ST_WAIT_REC_STB_0;
elsif rec_stb='0' then
current_state <= ST_IDLE;
end if;
when ST_WAIT_REC_STB_0 =>
if rec_stb='0' then
current_state <= ST_IDLE;
end if;
when others =>
current_state <= ST_IDLE;
end case;
end if;
end process;
end arch;
| gpl-3.0 | 938226b357e0dcf2eff5a6b1d6059e2d | 0.618431 | 3.428934 | false | false | false | false |
tomoasleep/vhdl_test_script | examples/register_file.vhd | 1 | 1,077 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity register_file is
generic( value : std_logic_vector(2 downto 0) );
port (
input : in std_logic_vector(2 downto 0);
update : in std_logic;
output : out std_logic_vector(2 downto 0);
reg : out std_logic_vector(2 downto 0);
calc_result: out std_logic_vector(2 downto 0);
genericv : out std_logic_vector(2 downto 0);
clk : in std_logic
);
end register_file;
architecture behave of register_file is
component calculator port(
input : in std_logic_vector(2 downto 0);
output : out std_logic_vector(2 downto 0));
end component;
signal data : std_logic_vector(2 downto 0);
signal clout : std_logic_vector(2 downto 0);
begin -- behave
cl :calculator port map (
input => input,
output => clout);
main: process(clk) begin
if rising_edge(clk) then
if update = '1' then
data <= input;
calc_result <= clout;
end if;
end if;
end process;
output <= input;
reg <= data;
genericv <= value;
end behave;
| mit | beebb1fb80482dd20c9cb702075dd942 | 0.641597 | 3.34472 | false | false | false | false |
freecores/gpib_controller | vhdl/src/wrapper/GpibStatusReg.vhd | 1 | 2,114 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: SettingsReg0
-- Date:2011-11-09
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity GpibStatusReg is
port (
data_out : out std_logic_vector (15 downto 0);
-- gpib
currentSecAddr : in std_logic_vector (4 downto 0); -- current sec addr
att : in std_logic; -- addressed to talk(L or LE)
tac : in std_logic; -- talker active (T, TE)
atl : in std_logic; -- addressed to listen (T or TE)
lac : in std_logic; -- listener active (L, LE)
cwrc : in std_logic; -- controller write commands
cwrd : in std_logic; -- controller write data
spa : in std_logic; -- seriall poll active
isLocal : in std_logic -- device is local controlled
);
end GpibStatusReg;
architecture arch of GpibStatusReg is
begin
data_out(4 downto 0) <= currentSecAddr;
data_out(5) <= att;
data_out(6) <= tac;
data_out(7) <= atl;
data_out(8) <= lac;
data_out(9) <= cwrc;
data_out(10) <= cwrd;
data_out(11) <= spa;
data_out(12) <= isLocal;
data_out(15 downto 13) <= "000";
end arch;
| gpl-3.0 | 4deca9b558e182d876101eb0d49348a2 | 0.620624 | 3.670139 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/source/vhdl/addorsub.vhd | 2 | 8,323 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: addorsub - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
-- computes a+b or a-b
entity addorsub is
generic (
USE_DSP : boolean := true;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end addorsub;
architecture Behavioral of addorsub is
function my_max(v1 : integer; v2 : integer) return integer is
variable result : integer;
begin
if v1 < v2 then
result := v2;
else
result := v1;
end if;
return result;
end my_max;
function sext(val : std_logic_vector; length : integer) return std_logic_vector is
variable val_msb : std_logic;
variable result : std_logic_vector(length-1 downto 0);
begin
val_msb := val(val'length-1);
result(val'length-1 downto 0) := val;
result(length-1 downto val'length) := (others => val_msb);
return result;
end sext;
constant INT_BITWIDTH : integer := A_BITWIDTH+1;
constant LATENCY : integer := 2;
signal GND_ALUMODE : std_logic;
signal GND_BUS_3 : std_logic_vector (2 downto 0);
signal GND_BUS_18 : std_logic_vector (17 downto 0);
signal GND_BUS_30 : std_logic_vector (29 downto 0);
signal GND_BUS_48 : std_logic_vector (47 downto 0);
signal GND_OPMODE : std_logic;
signal VCC_OPMODE : std_logic;
signal AB_IN : std_logic_vector(47 downto 0);
signal C_IN : std_logic_vector(47 downto 0);
signal P_OUT : std_logic_vector(47 downto 0);
signal delay_line : std_logic_vector(0 to LATENCY-1);
signal a_reg : std_logic_vector(A_BITWIDTH-1 downto 0);
signal b_reg : std_logic_vector(B_BITWIDTH-1 downto 0);
signal p_reg : std_logic_vector(47 downto 0);
signal tmp_sum : signed(INT_BITWIDTH-1 downto 0);
begin
G_DSP : if USE_DSP = true generate
GND_ALUMODE <= '0';
GND_BUS_3(2 downto 0) <= "000";
GND_BUS_18(17 downto 0) <= "000000000000000000";
GND_BUS_30(29 downto 0) <= "000000000000000000000000000000";
GND_BUS_48(47 downto 0) <=
"000000000000000000000000000000000000000000000000";
GND_OPMODE <= '0';
VCC_OPMODE <= '1';
C_IN(47 downto A_BITWIDTH) <= (others=> a(A_BITWIDTH-1));
C_IN(A_BITWIDTH-1 downto 0) <= a;
AB_IN(47 downto B_BITWIDTH) <= (others=> b(B_BITWIDTH-1));
AB_IN(B_BITWIDTH-1 downto 0) <= b;
DSP48E_INST : DSP48E
generic map( ACASCREG => 1,
ALUMODEREG => 0,
AREG => 1,
AUTORESET_PATTERN_DETECT => FALSE,
AUTORESET_PATTERN_DETECT_OPTINV => "MATCH",
A_INPUT => "DIRECT",
BCASCREG => 1,
BREG => 1,
B_INPUT => "DIRECT",
CARRYINREG => 1,
CARRYINSELREG => 0,
CREG => 1,
MASK => x"3FFFFFFFFFFF",
MREG => 1,
MULTCARRYINREG => 1,
OPMODEREG => 0,
PATTERN => x"000000000000", -- pattern to all zeros
PREG => 1,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
SEL_ROUNDING_MASK => "MODE1", -- set to MODE1 instead of SEL_MASK to overrule SEL_MASK
USE_MULT => "NONE",
USE_PATTERN_DETECT => "PATDET", -- enable pattern detect
USE_SIMD => "ONE48")
port map (A(29 downto 0)=>AB_IN(47 downto 18),
ACIN(29 downto 0)=>GND_BUS_30(29 downto 0),
ALUMODE(3)=>GND_ALUMODE,
ALUMODE(2)=>GND_ALUMODE,
ALUMODE(1)=>sub,
ALUMODE(0)=>sub,
B(17 downto 0)=>AB_IN(17 downto 0),
BCIN(17 downto 0)=>GND_BUS_18(17 downto 0),
C(47 downto 0)=>C_IN(47 downto 0),
CARRYCASCIN=>GND_ALUMODE,
CARRYIN=>GND_ALUMODE,
CARRYINSEL(2 downto 0)=>GND_BUS_3(2 downto 0),
CEALUMODE=>VCC_OPMODE,
CEA1=>nd,
CEA2=>VCC_OPMODE,
CEB1=>nd,
CEB2=>VCC_OPMODE,
CEC=>nd,
CECARRYIN=>VCC_OPMODE,
CECTRL=>VCC_OPMODE,
CEM=>VCC_OPMODE,
CEMULTCARRYIN=>VCC_OPMODE,
CEP=>VCC_OPMODE,
CLK=>clk,
MULTSIGNIN=>GND_ALUMODE,
OPMODE(6)=>GND_OPMODE,
OPMODE(5)=>VCC_OPMODE,
OPMODE(4)=>VCC_OPMODE,
OPMODE(3)=>GND_OPMODE,
OPMODE(2)=>GND_OPMODE,
OPMODE(1)=>VCC_OPMODE,
OPMODE(0)=>VCC_OPMODE,
PCIN(47 downto 0)=>GND_BUS_48(47 downto 0),
RSTA=>GND_ALUMODE,
RSTALLCARRYIN=>GND_ALUMODE,
RSTALUMODE=>GND_ALUMODE,
RSTB=>GND_ALUMODE,
RSTC=>GND_ALUMODE,
RSTCTRL=>GND_ALUMODE,
RSTM=>GND_ALUMODE,
RSTP=>GND_ALUMODE,
ACOUT=>open,
BCOUT=>open,
CARRYCASCOUT=>open,
CARRYOUT=>open,
MULTSIGNOUT=>open,
OVERFLOW=>open,
P(47 downto 0)=>P_OUT(47 downto 0),
PATTERNBDETECT=>open,
PATTERNDETECT=>open,
PCOUT=>open,
UNDERFLOW=>open);
-- trunc LSB (safe)
--res <= P_OUT(INT_BITWIDTH-1 downto INT_BITWIDTH-RES_BITWIDTH);
-- trunc MSB (unsafe)
res <= P_OUT(RES_BITWIDTH-1 downto 0);
end generate G_DSP;
G_NODSP : if USE_DSP = false generate
reg_proc : process(clk)
begin
if rising_edge(clk) then
a_reg <= a;
b_reg <= b;
p_reg <= sext(std_logic_vector(tmp_sum),48);
end if;
end process reg_proc;
add_sub : process(a_reg,b_reg,sub)
begin
if sub ='0' then
tmp_sum <= signed(sext(a_reg,INT_BITWIDTH))+signed(sext(b_reg,INT_BITWIDTH));
else
tmp_sum <= signed(sext(a_reg,INT_BITWIDTH))-signed(sext(b_reg,INT_BITWIDTH));
end if;
end process add_sub;
res <= p_reg(RES_BITWIDTH-1 downto 0);
end generate G_NODSP;
-- compensate for downconverter latency
delay_line_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
delay_line <= (others => '0');
else
delay_line(0) <= nd;
delay_line(1 to LATENCY-1) <= delay_line(0 to LATENCY-2);
end if;
end if;
end process delay_line_proc;
rdy <= delay_line(LATENCY-1);
end Behavioral;
| bsd-3-clause | 9d25864aa67c7e6cc6069a06b088cc7c | 0.479635 | 4.307971 | false | false | false | false |
freecores/gpib_controller | vhdl/src/wrapper/RegMultiplexer.vhd | 1 | 5,280 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: RegMultiplexer
-- Date:2011-11-14
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity RegMultiplexer is
generic (
ADDR_WIDTH : integer := 15
);
port (
strobe_read : in std_logic;
strobe_write : in std_logic;
data_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
--------------------------------------------------------
reg_addr : in std_logic_vector((ADDR_WIDTH-1) downto 0);
--------------------------------------------------------
reg_strobe_0 : out std_logic;
reg_in_0 : out std_logic_vector (15 downto 0);
reg_out_0 : in std_logic_vector (15 downto 0);
reg_strobe_1 : out std_logic;
reg_in_1 : out std_logic_vector (15 downto 0);
reg_out_1 : in std_logic_vector (15 downto 0);
reg_strobe_2 : out std_logic;
reg_in_2 : out std_logic_vector (15 downto 0);
reg_out_2 : in std_logic_vector (15 downto 0);
reg_strobe_3 : out std_logic;
reg_in_3 : out std_logic_vector (15 downto 0);
reg_out_3 : in std_logic_vector (15 downto 0);
reg_strobe_4 : out std_logic;
reg_in_4 : out std_logic_vector (15 downto 0);
reg_out_4 : in std_logic_vector (15 downto 0);
reg_strobe_5 : out std_logic;
reg_in_5 : out std_logic_vector (15 downto 0);
reg_out_5 : in std_logic_vector (15 downto 0);
reg_strobe_6 : out std_logic;
reg_in_6 : out std_logic_vector (15 downto 0);
reg_out_6 : in std_logic_vector (15 downto 0);
reg_strobe_7 : out std_logic;
reg_in_7 : out std_logic_vector (15 downto 0);
reg_out_7 : in std_logic_vector (15 downto 0);
reg_strobe_8 : out std_logic;
reg_in_8 : out std_logic_vector (15 downto 0);
reg_out_8 : in std_logic_vector (15 downto 0);
reg_strobe_9 : out std_logic;
reg_in_9 : out std_logic_vector (15 downto 0);
reg_out_9 : in std_logic_vector (15 downto 0);
reg_strobe_10 : out std_logic;
reg_in_10 : out std_logic_vector (15 downto 0);
reg_out_10 : in std_logic_vector (15 downto 0);
reg_strobe_11 : out std_logic;
reg_in_11 : out std_logic_vector (15 downto 0);
reg_out_11 : in std_logic_vector (15 downto 0);
reg_strobe_other0 : out std_logic;
reg_in_other0 : out std_logic_vector (15 downto 0);
reg_out_other0 : in std_logic_vector (15 downto 0);
reg_strobe_other1 : out std_logic;
reg_in_other1 : out std_logic_vector (15 downto 0);
reg_out_other1 : in std_logic_vector (15 downto 0)
);
end RegMultiplexer;
architecture arch of RegMultiplexer is
constant REG_COUNT : integer := 14;
constant MAX_ADDR : integer := (2**ADDR_WIDTH - 1);
type SIGNAL_VECTOR is array ((REG_COUNT-1) downto 0) of std_logic;
type BUS_VECTOR is array ((REG_COUNT-1) downto 0) of
std_logic_vector (15 downto 0);
signal cur_reg_num : integer range 0 to 13;
signal dec_addr : integer range MAX_ADDR downto 0;
signal inputs : BUS_VECTOR;
signal outputs : BUS_VECTOR;
signal strobes : SIGNAL_VECTOR;
begin
(reg_strobe_other1, reg_strobe_other0, reg_strobe_11, reg_strobe_10,
reg_strobe_9, reg_strobe_8, reg_strobe_7, reg_strobe_6, reg_strobe_5,
reg_strobe_4, reg_strobe_3, reg_strobe_2, reg_strobe_1,
reg_strobe_0) <= strobes;
(reg_in_other1, reg_in_other0, reg_in_11, reg_in_10, reg_in_9, reg_in_8,
reg_in_7, reg_in_6, reg_in_5, reg_in_4, reg_in_3, reg_in_2, reg_in_1,
reg_in_0) <= inputs;
outputs <= (reg_out_other1, reg_out_other0, reg_out_11, reg_out_10,
reg_out_9, reg_out_8, reg_out_7, reg_out_6, reg_out_5, reg_out_4,
reg_out_3, reg_out_2, reg_out_1, reg_out_0);
dec_addr <= conv_integer(reg_addr);
process (dec_addr) begin
if dec_addr >= 0 and dec_addr < (REG_COUNT-2) then
cur_reg_num <= dec_addr;
elsif dec_addr = (REG_COUNT-2) then
cur_reg_num <= 12;
else
cur_reg_num <= 13;
end if;
end process;
process (strobe_read, strobe_write, data_in, outputs, cur_reg_num) begin
strobes <= (others => '0');
inputs <= (others => (others => '0'));
data_out <= (others => '0');
if cur_reg_num < REG_COUNT then
if cur_reg_num = 12 then
strobes(cur_reg_num) <= strobe_read;
else
strobes(cur_reg_num) <= strobe_write;
end if;
inputs(cur_reg_num) <= data_in;
data_out <= outputs(cur_reg_num);
end if;
end process;
end arch;
| gpl-3.0 | 6a0e1103144d1aa7c6263e37b7d78030 | 0.62178 | 2.946429 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/source/vhdl/min_search.vhd | 1 | 4,025 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: min_search - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.lloyds_algorithm_pkg.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity min_search is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
metric_in : in coord_type_ext;
u_in : in node_data_type;
point_in : in data_type;
min_point : out data_type;
min_index : out centre_index_type;
min_metric : out coord_type_ext;
u_out : out node_data_type;
rdy : out std_logic
);
end min_search;
architecture Behavioral of min_search is
type state_type is (idle, processing, delaying, done);
signal state : state_type;
signal metric_in_reg : coord_type_ext;
signal point_in_reg : data_type;
signal current_smallest : std_logic;
signal tmp_min_metric : coord_type_ext;
signal tmp_min_index : centre_index_type;
signal tmp_min_point : data_type;
signal tmp_u_in : node_data_type;
signal counter : centre_index_type;
signal rdy_reg : std_logic;
signal rdy_sig : std_logic;
begin
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
state <= idle;
elsif state = idle AND nd='1' then
state <= processing;
tmp_u_in <= u_in; -- save the u_in input (a bit dirty)
elsif state = processing AND nd='0' then -- assume continuous streaming
state <= idle;
elsif state = done then
state <= idle;
end if;
end if;
end process fsm_proc;
-- need to delay by one cycle due to state machine
input_reg_proc : process(clk)
begin
if rising_edge(clk) then
metric_in_reg <= metric_in;
point_in_reg <= point_in;
end if;
end process input_reg_proc;
current_smallest <= '1' WHEN state = processing AND unsigned(metric_in_reg) < unsigned(tmp_min_metric) ELSE '0';
min_distance_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' OR state = idle OR state = done then
tmp_min_metric(COORD_BITWIDTH_EXT-1 downto 0) <= (others => '1'); --largest possible value (assume unsigned metrics)
tmp_min_index <= (others => '0');
else
if current_smallest = '1' then
tmp_min_metric <= metric_in_reg;
tmp_min_index <= counter;
tmp_min_point <= point_in_reg;
end if;
end if;
end if;
end process min_distance_proc;
counter_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' OR state = idle OR state = done then
counter <= (others => '0');
else
counter <= counter+1;
end if;
end if;
end process counter_proc;
rdy_sig <= '1' WHEN state = processing AND nd='0' ELSE '0';
rdy_proc : process(clk)
begin
if rising_edge(clk) then
if sclr ='1' then
rdy_reg <= '0';
else
rdy_reg <= rdy_sig;
end if;
end if;
end process rdy_proc;
min_point <= tmp_min_point;
min_index <= tmp_min_index;
min_metric <= tmp_min_metric;
rdy <= rdy_reg;
u_out <= tmp_u_in;
end Behavioral;
| bsd-3-clause | 8b625cfc65529d738af5e1d54cdcee77 | 0.523975 | 4.016966 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/centre_stack_mgmt.vhd | 1 | 6,178 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: centre_stack_mgmt - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity centre_stack_mgmt is
port (
clk : in STD_LOGIC;
sclr : in STD_LOGIC;
push : in std_logic;
pop : in std_logic;
cntr_addr_in : in centre_list_address_type;
k_in : in centre_index_type;
cntr_addr_out : out centre_list_address_type;
k_out : out centre_index_type;
empty : out std_logic;
valid : out std_logic
);
end centre_stack_mgmt;
architecture Behavioral of centre_stack_mgmt is
constant MEM_LAT : integer := 2;
constant STACK_POINTER_BITWIDTH : integer := integer(ceil(log2(real(STACK_SIZE))));
type stack_pointer_delay_line_type is array(0 to MEM_LAT-1) of unsigned(STACK_POINTER_BITWIDTH-1 downto 0);
component centre_stack_memory
port (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(STACK_POINTER_BITWIDTH-1 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(STACK_POINTER_BITWIDTH-1 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO 0)
);
end component;
signal stack_pointer : unsigned(STACK_POINTER_BITWIDTH-1 downto 0);
signal pop_reg : std_logic;
signal push_reg : std_logic;
signal tmp_stack_addr_rd : unsigned(STACK_POINTER_BITWIDTH-1 downto 0);
signal stack_addr_rd_reg : unsigned(STACK_POINTER_BITWIDTH-1 downto 0);
signal tmp_addr_item : std_logic_vector(CNTR_POINTER_BITWIDTH-1 downto 0);
signal rec_stack_pointer : std_logic_vector(CNTR_POINTER_BITWIDTH-1 downto 0);
signal tmp_cntr_stack_din : std_logic_vector(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 downto 0);
signal tmp_empty : std_logic;
signal tmp_cntr_stack_dout : std_logic_vector(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 downto 0);
signal rdy_delay_line : std_logic_vector(0 to MEM_LAT-1);
signal emp_delay_line : std_logic_vector(0 to MEM_LAT-1);
signal stack_pointer_delay_line : stack_pointer_delay_line_type;
begin
update_stack_ptr_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
stack_pointer <= to_unsigned(0,STACK_POINTER_BITWIDTH);--(others => '0');
else
if push = '1' AND pop = '0' then
stack_pointer <= stack_pointer+1;
elsif push = '0' AND pop = '1' then
stack_pointer <= stack_pointer-1;
elsif push = '1' AND pop = '1' then
stack_pointer <= stack_pointer; -- add 1, remove 1
end if;
end if;
end if;
end process update_stack_ptr_proc;
tmp_stack_addr_rd <= stack_pointer-1;
tmp_empty <= '1' WHEN stack_pointer = 0 ELSE '0';
input_reg_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
pop_reg <= '0';
--push_reg <= '0';
else
pop_reg <= pop;
stack_addr_rd_reg <= tmp_stack_addr_rd;
--push_reg <= push;
--rec_stack_pointer <= std_logic_vector(stack_pointer);
end if;
end if;
end process input_reg_proc;
--tmp_addr_item <= rec_stack_pointer(CNTR_POINTER_BITWIDTH-1 downto 1) & '0' WHEN push='1' AND push_reg='1' ELSE std_logic_vector(stack_pointer(CNTR_POINTER_BITWIDTH-1 downto 1)) & '0';
tmp_cntr_stack_din(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 downto INDEX_BITWIDTH) <= std_logic_vector(cntr_addr_in);
tmp_cntr_stack_din(INDEX_BITWIDTH-1 downto 0) <= std_logic_vector(k_in);
centre_stack_memory_inst_1 : centre_stack_memory
port map (
clka => clk,
wea(0) => push,
addra => std_logic_vector(stack_pointer),
dina => tmp_cntr_stack_din,
clkb => clk,
addrb => std_logic_vector(tmp_stack_addr_rd),--std_logic_vector(stack_addr_rd_reg),
doutb => tmp_cntr_stack_dout
);
delay_line_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
rdy_delay_line <= (others => '0');
emp_delay_line <= (others => '0');
else
rdy_delay_line(0) <= pop;--pop_reg;
rdy_delay_line(1 to MEM_LAT-1) <= rdy_delay_line(0 to MEM_LAT-2);
stack_pointer_delay_line(0) <= tmp_stack_addr_rd;--stack_pointer;
stack_pointer_delay_line(1 to MEM_LAT-1) <= stack_pointer_delay_line(0 to MEM_LAT-2);
end if;
end if;
end process delay_line_proc;
cntr_addr_out <= tmp_cntr_stack_dout(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 downto INDEX_BITWIDTH);
k_out <= unsigned(tmp_cntr_stack_dout(INDEX_BITWIDTH-1 downto 0));
valid <= rdy_delay_line(MEM_LAT-1); -- AND NOT(emp_delay_line(MEM_LAT-1));
empty <= tmp_empty;--emp_delay_line(MEM_LAT-1);
end Behavioral;
| bsd-3-clause | ca2b0f0d8f9b92f5ed3785da72fdaf57 | 0.558271 | 3.839652 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/source/vhdl/dot_product.vhd | 1 | 7,771 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: dot_product - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
use ieee.math_real.all;
use work.lloyds_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dot_product is
generic (
SCALE_MUL_RESULT : integer := 0
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
point_1 : in data_type;
point_2 : in data_type;
result : out coord_type_ext;
rdy : out std_logic
);
end dot_product;
architecture Behavioral of dot_product is
constant LAYERS_TREE_ADDER : integer := integer(ceil(log2(real(D))));
type mul_res_array_type is array(0 to D-1) of std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1-1 downto 0);
--type tree_adder_res_array_type is array(0 to LAYERS_TREE_ADDER-1, 0 to D/2-1) of std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
component addorsub
generic (
USE_DSP : boolean := true;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
component madd
generic (
MUL_LATENCY : integer := 3;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
INCLUDE_ADD : boolean := false;
C_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
c : in std_logic_vector(C_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
component adder_tree
generic (
USE_DSP_FOR_ADD : boolean := true;
NUMBER_OF_INPUTS : integer := 4;
INPUT_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
input_string : in std_logic_vector(NUMBER_OF_INPUTS*INPUT_BITWIDTH-1 downto 0);
rdy : out std_logic;
output : out std_logic_vector(INPUT_BITWIDTH+integer(ceil(log2(real(NUMBER_OF_INPUTS))))-1 downto 0)
);
end component;
signal tmp_mul_res : mul_res_array_type;
signal tmp_tree_adder_input_string : std_logic_vector(D*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)-1 downto 0);
--signal tmp_tree_adder_res : tree_adder_res_array_type;
signal tmp_tree_adder_res : std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
signal const_0 : std_logic_vector(MUL_BITWIDTH-1 downto 0);
signal tmp_mul_rdy : std_logic;
signal delay_line_tree_adder : std_logic_vector(0 to 2*LAYERS_TREE_ADDER-1);
signal tmp_final_res : coord_type_ext;
begin
const_0 <= (others => '0');
G1: for I in 0 to D-1 generate
G_FIRST: if I = 0 generate
madd_inst : madd
generic map(
MUL_LATENCY => MUL_CORE_LATENCY,
A_BITWIDTH => MUL_BITWIDTH,
B_BITWIDTH => MUL_BITWIDTH,
INCLUDE_ADD => false,
C_BITWIDTH => MUL_BITWIDTH,
RES_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
a => saturate(point_1(I)),
b => saturate(point_2(I)),
c => const_0,
res => tmp_mul_res(I),
rdy => tmp_mul_rdy
);
end generate G_FIRST;
G_OTHER: if I > 0 generate
madd_inst : madd
generic map(
A_BITWIDTH => MUL_BITWIDTH,
B_BITWIDTH => MUL_BITWIDTH,
C_BITWIDTH => MUL_BITWIDTH,
RES_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
a => saturate(point_1(I)),
b => saturate(point_2(I)),
c => const_0,
res => tmp_mul_res(I),
rdy => open
);
end generate G_OTHER;
end generate G1;
G2 : for I in 0 to D-1 generate
tmp_tree_adder_input_string((I+1)*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)-1 downto I*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)) <= tmp_mul_res(I);
end generate G2;
adder_tree_inst : adder_tree
generic map (
USE_DSP_FOR_ADD => USE_DSP_FOR_ADD,
NUMBER_OF_INPUTS => D,
INPUT_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_mul_rdy,
sub => '0',
input_string => tmp_tree_adder_input_string,
rdy => rdy,
output => tmp_tree_adder_res
);
G3: if COORD_BITWIDTH_EXT <= 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER generate
--tmp_final_res <= tmp_tree_adder_res(LAYERS_TREE_ADDER-1,0)(COORD_BITWIDTH_EXT-1 downto 0);
tmp_final_res <= tmp_tree_adder_res(COORD_BITWIDTH_EXT-1 downto 0);
end generate G3;
G4: if COORD_BITWIDTH_EXT > 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER generate
--tmp_final_res(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0) <= tmp_tree_adder_res(LAYERS_TREE_ADDER-1,0)(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
--tmp_final_res(COORD_BITWIDTH_EXT-1 downto 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER) <= (others => tmp_tree_adder_res(LAYERS_TREE_ADDER-1,0)(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1));
tmp_final_res(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0) <= tmp_tree_adder_res(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
tmp_final_res(COORD_BITWIDTH_EXT-1 downto 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER) <= (others => tmp_tree_adder_res(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1));
end generate G4;
--rdy <= delay_line_tree_adder(2*LAYERS_TREE_ADDER-1);
result <= tmp_final_res;
end Behavioral;
| bsd-3-clause | 8df85285de605ca65ede0cd1377e0261 | 0.526316 | 3.801859 | false | false | false | false |
esar/hdmilight-v2 | fpga/avr/opc_deco.vhd | 1 | 29,610 | -------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: opc_deco - Behavioral
-- Create Date: 16:05:16 10/29/2009
-- Description: the opcode decoder of a CPU.
--
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.common.ALL;
entity opc_deco is
port ( I_CLK : in std_logic;
I_CE : in std_logic;
I_OPC : in std_logic_vector(31 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_T0 : in std_logic;
Q_ALU_OP : out std_logic_vector( 4 downto 0);
Q_AMOD : out std_logic_vector( 5 downto 0);
Q_BIT : out std_logic_vector( 3 downto 0);
Q_DDDDD : out std_logic_vector( 4 downto 0);
Q_IMM : out std_logic_vector(15 downto 0);
Q_JADR : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector(15 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_PC_OP : out std_logic_vector( 2 downto 0);
Q_PMS : out std_logic; -- program memory select
Q_RD_M : out std_logic;
Q_RRRRR : out std_logic_vector( 4 downto 0);
Q_RSEL : out std_logic_vector( 1 downto 0);
Q_WE_01 : out std_logic;
Q_WE_D : out std_logic_vector( 1 downto 0);
Q_WE_F : out std_logic;
Q_WE_M : out std_logic_vector( 1 downto 0);
Q_WE_XYZS : out std_logic);
end opc_deco;
architecture Behavioral of opc_deco is
begin
process(I_CE, I_CLK)
begin
if (I_CE = '1' and rising_edge(I_CLK)) then
--
-- set the most common settings as default.
--
Q_ALU_OP <= ALU_D_MV_Q;
Q_AMOD <= AMOD_ABS;
Q_BIT <= I_OPC(10) & I_OPC(2 downto 0);
Q_DDDDD <= I_OPC(8 downto 4);
Q_IMM <= X"0000";
Q_JADR <= I_OPC(31 downto 16);
Q_OPC <= I_OPC(15 downto 0);
Q_PC <= I_PC;
Q_PC_OP <= PC_NEXT;
Q_PMS <= '0';
Q_RD_M <= '0';
Q_RRRRR <= I_OPC(9) & I_OPC(3 downto 0);
Q_RSEL <= RS_REG;
Q_WE_D <= "00";
Q_WE_01 <= '0';
Q_WE_F <= '0';
Q_WE_M <= "00";
Q_WE_XYZS <= '0';
case I_OPC(15 downto 10) is
when "000000" => -- 0000 00xx xxxx xxxx
case I_OPC(9 downto 8) is
when "00" =>
--
-- 0000 0000 0000 0000 - NOP
-- 0000 0000 001v vvvv - INTERRUPT
--
if (I_OPC(5)) = '1' then -- interrupt
Q_ALU_OP <= ALU_INTR;
Q_AMOD <= AMOD_SPdd;
Q_JADR <= "0000000000" & I_OPC(4 downto 0) & "0";
Q_PC_OP <= PC_LD_I;
Q_WE_F <= '1'; -- clear I-flag
Q_WE_M <= "11"; -- write return address
Q_WE_XYZS <= '1'; -- write new SP
end if;
when "01" =>
--
-- 0000 0001 dddd rrrr - MOVW
--
Q_DDDDD <= I_OPC(7 downto 4) & "0";
Q_RRRRR <= I_OPC(3 downto 0) & "0";
Q_ALU_OP <= ALU_MV_16;
Q_WE_D <= "11";
when "10" =>
--
-- 0000 0010 dddd rrrr - MULS
--
Q_DDDDD <= "1" & I_OPC(7 downto 4);
Q_RRRRR <= "1" & I_OPC(3 downto 0);
Q_ALU_OP <= ALU_MULT;
Q_IMM(7 downto 5) <= MULT_SS;
Q_WE_01 <= '1';
Q_WE_F <= '1';
when others =>
--
-- 0000 0011 0ddd 0rrr - _MULSU SU "010"
-- 0000 0011 0ddd 1rrr - FMUL UU "100"
-- 0000 0011 1ddd 0rrr - FMULS SS "111"
-- 0000 0011 1ddd 1rrr - FMULSU SU "110"
--
Q_DDDDD(4 downto 3) <= "10"; -- regs 16 to 23
Q_RRRRR(4 downto 3) <= "10"; -- regs 16 to 23
Q_ALU_OP <= ALU_MULT;
if I_OPC(7) = '0' then
if I_OPC(3) = '0' then
Q_IMM(7 downto 5) <= MULT_SU;
else
Q_IMM(7 downto 5) <= MULT_FUU;
end if;
else
if I_OPC(3) = '0' then
Q_IMM(7 downto 5) <= MULT_FSS;
else
Q_IMM(7 downto 5) <= MULT_FSU;
end if;
end if;
Q_WE_01 <= '1';
Q_WE_F <= '1';
end case;
when "000001" | "000010" =>
--
-- 0000 01rd dddd rrrr - CPC = SBC without Q_WE_D
-- 0000 10rd dddd rrrr - SBC
--
Q_ALU_OP <= ALU_SBC;
Q_WE_D <= '0' & I_OPC(11); -- write Rd if SBC.
Q_WE_F <= '1';
when "000011" => -- 0000 11xx xxxx xxxx
--
-- 0000 11rd dddd rrrr - ADD
--
Q_ALU_OP <= ALU_ADD;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "000100" => -- 0001 00xx xxxx xxxx
--
-- 0001 00rd dddd rrrr - CPSE
--
Q_ALU_OP <= ALU_SUB;
if (I_T0 = '0') then -- second cycle.
Q_PC_OP <= PC_SKIP_Z;
end if;
when "000101" | "000110" =>
--
-- 0001 01rd dddd rrrr - CP = SUB without Q_WE_D
-- 0000 10rd dddd rrrr - SUB
--
Q_ALU_OP <= ALU_SUB;
Q_WE_D <= '0' & I_OPC(11); -- write Rd if SUB.
Q_WE_F <= '1';
when "000111" => -- 0001 11xx xxxx xxxx
--
-- 0001 11rd dddd rrrr - ADC
--
Q_ALU_OP <= ALU_ADC;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "001000" => -- 0010 00xx xxxx xxxx
--
-- 0010 00rd dddd rrrr - AND
--
Q_ALU_OP <= ALU_AND;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "001001" => -- 0010 01xx xxxx xxxx
--
-- 0010 01rd dddd rrrr - EOR
--
Q_ALU_OP <= ALU_EOR;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "001010" => -- 0010 10xx xxxx xxxx
--
-- 0010 10rd dddd rrrr - OR
--
Q_ALU_OP <= ALU_OR;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "001011" => -- 0010 11xx xxxx xxxx
--
-- 0010 11rd dddd rrrr - MOV
--
Q_ALU_OP <= ALU_R_MV_Q;
Q_WE_D <= "01";
when "001100" | "001101" | "001110" | "001111"
| "010100" | "010101" | "010110" | "010111" =>
--
-- 0011 KKKK dddd KKKK - CPI
-- 0101 KKKK dddd KKKK - SUBI
--
Q_ALU_OP <= ALU_SUB;
Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
Q_RSEL <= RS_IMM;
Q_DDDDD(4) <= '1'; -- Rd = 16...31
Q_WE_D <= '0' & I_OPC(14);
Q_WE_F <= '1';
when "010000" | "010001" | "010010" | "010011" =>
--
-- 0100 KKKK dddd KKKK - SBCI
--
Q_ALU_OP <= ALU_SBC;
Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
Q_RSEL <= RS_IMM;
Q_DDDDD(4) <= '1'; -- Rd = 16...31
Q_WE_D <= "01";
Q_WE_F <= '1';
when "011000" | "011001" | "011010" | "011011" =>
--
-- 0110 KKKK dddd KKKK - ORI
--
Q_ALU_OP <= ALU_OR;
Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
Q_RSEL <= RS_IMM;
Q_DDDDD(4) <= '1'; -- Rd = 16...31
Q_WE_D <= "01";
Q_WE_F <= '1';
when "011100" | "011101" | "011110" | "011111" =>
--
-- 0111 KKKK dddd KKKK - ANDI
--
Q_ALU_OP <= ALU_AND;
Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
Q_RSEL <= RS_IMM;
Q_DDDDD(4) <= '1'; -- Rd = 16...31
Q_WE_D <= "01";
Q_WE_F <= '1';
when "100000" | "100001" | "100010" | "100011"
| "101000" | "101001" | "101010" | "101011" =>
--
-- LDD (Y + q) == LD (y) if q == 0
--
-- 10q0 qq0d dddd 1qqq LDD (Y + q)
-- 10q0 qq0d dddd 0qqq LDD (Z + q)
-- 10q0 qq1d dddd 1qqq SDD (Y + q)
-- 10q0 qq1d dddd 0qqq SDD (Z + q)
-- L/ Z/
-- S Y
--
Q_IMM(5) <= I_OPC(13);
Q_IMM(4 downto 3) <= I_OPC(11 downto 10);
Q_IMM(2 downto 0) <= I_OPC( 2 downto 0);
if (I_OPC(3) = '0') then Q_AMOD <= AMOD_Zq;
else Q_AMOD <= AMOD_Yq;
end if;
if (I_OPC(9) = '0') then -- LDD
Q_RSEL <= RS_DIN;
Q_RD_M <= I_T0;
Q_WE_D <= '0' & not I_T0;
else -- STD
Q_WE_M <= '0' & I_OPC(9);
end if;
when "100100" => -- 1001 00xx xxxx xxxx
Q_IMM <= I_OPC(31 downto 16); -- absolute address for LDS/STS
if (I_OPC(9) = '0') then -- LDD / POP
--
-- 1001 00-0d dddd 0000 - LDS
-- 1001 00-0d dddd 0001 - LD Rd, Z+
-- 1001 00-0d dddd 0010 - LD Rd, -Z
-- 1001 00-0d dddd 0100 - LPM Rd, (Z) (ii)
-- 1001 00-0d dddd 0101 - LPM Rd, (Z+) (iii)
-- 1001 00-0d dddd 0110 - ELPM Z --- not mega8
-- 1001 00-0d dddd 0111 - ELPM Z+ --- not mega8
-- 1001 00-0d dddd 1001 - LD Rd, Y+
-- 1001 00-0d dddd 1010 - LD Rd, -Y
-- 1001 00-0d dddd 1100 - LD Rd, X
-- 1001 00-0d dddd 1101 - LD Rd, X+
-- 1001 00-0d dddd 1110 - LD Rd, -X
-- 1001 00-0d dddd 1111 - POP Rd
--
Q_RSEL <= RS_DIN;
Q_RD_M <= I_T0;
Q_WE_D <= '0' & not I_T0;
Q_WE_XYZS <= not I_T0;
Q_PMS <= (not I_OPC(3)) and I_OPC(2) and (not I_OPC(1));
case I_OPC(3 downto 0) is
when "0000" => Q_AMOD <= AMOD_ABS; Q_WE_XYZS <= '0';
when "0001" => Q_AMOD <= AMOD_Zi;
when "0100" => Q_AMOD <= AMOD_Z; Q_WE_XYZS <= '0';
when "0101" => Q_AMOD <= AMOD_Zi;
when "1001" => Q_AMOD <= AMOD_Yi;
when "1010" => Q_AMOD <= AMOD_dY;
when "1100" => Q_AMOD <= AMOD_X; Q_WE_XYZS <= '0';
when "1101" => Q_AMOD <= AMOD_Xi;
when "1110" => Q_AMOD <= AMOD_dX;
when "1111" => Q_AMOD <= AMOD_iSP;
when others => Q_WE_XYZS <= '0';
end case;
else -- STD / PUSH
--
-- 1001 00-1r rrrr 0000 - STS
-- 1001 00-1r rrrr 0001 - ST Z+. Rr
-- 1001 00-1r rrrr 0010 - ST -Z. Rr
-- 1001 00-1r rrrr 1000 - ST Y. Rr
-- 1001 00-1r rrrr 1001 - ST Y+. Rr
-- 1001 00-1r rrrr 1010 - ST -Y. Rr
-- 1001 00-1r rrrr 1100 - ST X. Rr
-- 1001 00-1r rrrr 1101 - ST X+. Rr
-- 1001 00-1r rrrr 1110 - ST -X. Rr
-- 1001 00-1r rrrr 1111 - PUSH Rr
--
Q_ALU_OP <= ALU_D_MV_Q;
Q_WE_M <= "01";
Q_WE_XYZS <= '1';
case I_OPC(3 downto 0) is
when "0000" => Q_AMOD <= AMOD_ABS; Q_WE_XYZS <= '0';
when "0001" => Q_AMOD <= AMOD_Zi;
when "0010" => Q_AMOD <= AMOD_dZ;
when "1001" => Q_AMOD <= AMOD_Yi;
when "1010" => Q_AMOD <= AMOD_dY;
when "1100" => Q_AMOD <= AMOD_X; Q_WE_XYZS <= '0';
when "1101" => Q_AMOD <= AMOD_Xi;
when "1110" => Q_AMOD <= AMOD_dX;
when "1111" => Q_AMOD <= AMOD_SPd;
when others =>
end case;
end if;
when "100101" => -- 1001 01xx xxxx xxxx
if (I_OPC(9) = '0') then -- 1001 010
case I_OPC(3 downto 0) is
when "0000" =>
--
-- 1001 010d dddd 0000 - COM Rd
--
Q_ALU_OP <= ALU_COM;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0001" =>
--
-- 1001 010d dddd 0001 - NEG Rd
--
Q_ALU_OP <= ALU_NEG;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0010" =>
--
-- 1001 010d dddd 0010 - SWAP Rd
--
Q_ALU_OP <= ALU_SWAP;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0011" =>
--
-- 1001 010d dddd 0011 - INC Rd
--
Q_ALU_OP <= ALU_INC;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0101" =>
--
-- 1001 010d dddd 0101 - ASR Rd
--
Q_ALU_OP <= ALU_ASR;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0110" =>
--
-- 1001 010d dddd 0110 - LSR Rd
--
Q_ALU_OP <= ALU_LSR;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0111" =>
--
-- 1001 010d dddd 0111 - ROR Rd
--
Q_ALU_OP <= ALU_ROR;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "1000" => -- 1001 010x xxxx 1000
if I_OPC(8) = '0' then -- 1001 0100 xxxx 1000
--
-- 1001 0100 0sss 1000 - BSET
-- 1001 0100 1sss 1000 - BCLR
--
Q_BIT(3 downto 0) <= I_OPC(7 downto 4);
Q_ALU_OP <= ALU_SREG;
Q_WE_F <= '1';
else -- 1001 0101 xxxx 1000
--
-- 1001 0101 0000 1000 - RET
-- 1001 0101 0001 1000 - RETI
-- 1001 0101 1000 1000 - SLEEP
-- 1001 0101 1001 1000 - BREAK
-- 1001 0101 1100 1000 - LPM [ R0,(Z) ]
-- 1001 0101 1101 1000 - ELPM not mega8
-- 1001 0101 1110 1000 - SPM
-- 1001 0101 1111 1000 - SPM #2
-- 1001 0101 1010 1000 - WDR
--
case I_OPC(7 downto 4) is
when "0000" => -- RET
Q_AMOD <= AMOD_iiSP;
Q_RD_M <= I_T0;
Q_WE_XYZS <= not I_T0;
if (I_T0 = '0') then
Q_PC_OP <= PC_LD_S;
end if;
when "0001" => -- RETI
Q_ALU_OP <= ALU_INTR;
Q_IMM(6) <= '1';
Q_AMOD <= AMOD_iiSP;
Q_RD_M <= I_T0;
Q_WE_F <= not I_T0; -- I flag
Q_WE_XYZS <= not I_T0;
if (I_T0 = '0') then
Q_PC_OP <= PC_LD_S;
end if;
when "1100" => -- (i) LPM R0, (Z)
Q_DDDDD <= "00000";
Q_AMOD <= AMOD_Z;
Q_PMS <= '1';
Q_WE_D <= '0' & not I_T0;
when "1110" => -- SPM
Q_ALU_OP <= ALU_D_MV_Q;
Q_DDDDD <= "00000";
Q_AMOD <= AMOD_Z;
Q_PMS <= '1';
Q_WE_M <= "01";
when "1111" => -- SPM #2
-- page write: not supported
when others =>
end case;
end if;
when "1001" => -- 1001 010x xxxx 1001
--
-- 1001 0100 0000 1001 IJMP
-- 1001 0100 0001 1001 EIJMP -- not mega8
-- 1001 0101 0000 1001 ICALL
-- 1001 0101 0001 1001 EICALL -- not mega8
--
Q_PC_OP <= PC_LD_Z;
if (I_OPC(8) = '1') then -- ICALL
Q_ALU_OP <= ALU_PC_1;
Q_AMOD <= AMOD_SPdd;
Q_WE_M <= "11";
Q_WE_XYZS <= '1';
end if;
when "1010" => -- 1001 010x xxxx 1010
--
-- 1001 010d dddd 1010 - DEC Rd
--
Q_ALU_OP <= ALU_DEC;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "1011" => -- 1001 010x xxxx 1011
--
-- 1001 0100 KKKK 1011 - DES -- not mega8
--
when "1100" | "1101" =>
--
-- 1001 010k kkkk 110k - JMP (k = 0 for 16 bit)
-- kkkk kkkk kkkk kkkk
--
Q_PC_OP <= PC_LD_I;
when "1110" | "1111" => -- 1001 010x xxxx 111x
--
-- 1001 010k kkkk 111k - CALL (k = 0)
-- kkkk kkkk kkkk kkkk
--
Q_ALU_OP <= ALU_PC_2;
Q_AMOD <= AMOD_SPdd;
Q_PC_OP <= PC_LD_I;
Q_WE_M <= "11"; -- both PC bytes
Q_WE_XYZS <= '1';
when others =>
end case;
else -- 1001 011
--
-- 1001 0110 KKdd KKKK - ADIW
-- 1001 0111 KKdd KKKK - SBIW
--
if (I_OPC(8) = '0') then Q_ALU_OP <= ALU_ADIW;
else Q_ALU_OP <= ALU_SBIW;
end if;
Q_IMM(5 downto 4) <= I_OPC(7 downto 6);
Q_IMM(3 downto 0) <= I_OPC(3 downto 0);
Q_RSEL <= RS_IMM;
Q_DDDDD <= "11" & I_OPC(5 downto 4) & "0";
Q_WE_D <= "11";
Q_WE_F <= '1';
end if; -- I_OPC(9) = 0/1
when "100110" => -- 1001 10xx xxxx xxxx
--
-- 1001 1000 AAAA Abbb - CBI
-- 1001 1001 AAAA Abbb - SBIC
-- 1001 1010 AAAA Abbb - SBI
-- 1001 1011 AAAA Abbb - SBIS
--
Q_ALU_OP <= ALU_BIT_CS;
Q_AMOD <= AMOD_ABS;
Q_BIT(3) <= I_OPC(9); -- set/clear
-- IMM = AAAAAA + 0x20
--
Q_IMM(4 downto 0) <= I_OPC(7 downto 3);
Q_IMM(6 downto 5) <= "01";
Q_RD_M <= I_T0;
if ((I_OPC(8) = '0') ) then -- CBI or SBI
Q_WE_M(0) <= '1';
else -- SBIC or SBIS
if (I_T0 = '0') then -- second cycle.
Q_PC_OP <= PC_SKIP_T;
end if;
end if;
when "100111" => -- 1001 11xx xxxx xxxx
--
-- 1001 11rd dddd rrrr - MUL
--
Q_ALU_OP <= ALU_MULT;
Q_IMM(7 downto 5) <= "000"; -- -MUL UU;
Q_WE_01 <= '1';
Q_WE_F <= '1';
when "101100" | "101101" => -- 1011 0xxx xxxx xxxx
--
-- 1011 0AAd dddd AAAA - IN
--
Q_RSEL <= RS_DIN;
Q_AMOD <= AMOD_ABS;
-- IMM = AAAAAA
-- + 010000 (0x20)
Q_IMM(3 downto 0) <= I_OPC(3 downto 0);
Q_IMM(4) <= I_OPC(9);
Q_IMM(6 downto 5) <= "01" + ('0' & I_OPC(10 downto 10));
Q_RD_M <= '1';
Q_WE_D <= "01";
when "101110" | "101111" => -- 1011 1xxx xxxx xxxx
--
-- 1011 1AAr rrrr AAAA - OUT
--
Q_ALU_OP <= ALU_D_MV_Q;
Q_AMOD <= AMOD_ABS;
-- IMM = AAAAAA
-- + 010000 (0x20)
--
Q_IMM(3 downto 0) <= I_OPC(3 downto 0);
Q_IMM(4) <= I_OPC(9);
Q_IMM(6 downto 5) <= "01" + ('0' & I_OPC(10 downto 10));
Q_WE_M <= "01";
when "110000" | "110001" | "110010" | "110011" =>
--
-- 1100 kkkk kkkk kkkk - RJMP
--
Q_JADR <= I_PC + (I_OPC(11) & I_OPC(11) & I_OPC(11) & I_OPC(11)
& I_OPC(11 downto 0)) + X"0001";
Q_PC_OP <= PC_LD_I;
when "110100" | "110101" | "110110" | "110111" =>
--
-- 1101 kkkk kkkk kkkk - RCALL
--
Q_JADR <= I_PC + (I_OPC(11) & I_OPC(11) & I_OPC(11) & I_OPC(11)
& I_OPC(11 downto 0)) + X"0001";
Q_ALU_OP <= ALU_PC_1;
Q_AMOD <= AMOD_SPdd;
Q_PC_OP <= PC_LD_I;
Q_WE_M <= "11"; -- both PC bytes
Q_WE_XYZS <= '1';
when "111000" | "111001" | "111010" | "111011" => -- LDI
--
-- 1110 KKKK dddd KKKK - LDI Rd, K
--
Q_ALU_OP <= ALU_R_MV_Q;
Q_RSEL <= RS_IMM;
Q_DDDDD <= '1' & I_OPC(7 downto 4); -- 16..31
Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
Q_WE_D <= "01";
when "111100" | "111101" => -- 1111 0xxx xxxx xxxx
--
-- 1111 00kk kkkk kbbb - BRBS
-- 1111 01kk kkkk kbbb - BRBC
-- v
-- bbb: status register bit
-- v: value (set/cleared) of status register bit
--
Q_JADR <= I_PC + (I_OPC(9) & I_OPC(9) & I_OPC(9) & I_OPC(9)
& I_OPC(9) & I_OPC(9) & I_OPC(9) & I_OPC(9)
& I_OPC(9) & I_OPC(9 downto 3)) + X"0001";
Q_PC_OP <= PC_BCC;
when "111110" => -- 1111 10xx xxxx xxxx
--
-- 1111 100d dddd 0bbb - BLD
-- 1111 101d dddd 0bbb - BST
--
if I_OPC(9) = '0' then -- BLD: T flag to register
Q_ALU_OP <= ALU_BLD;
Q_WE_D <= "01";
else -- BST: register to T flag
Q_AMOD <= AMOD_ABS;
Q_BIT(3) <= '1';
Q_IMM(4 downto 0) <= I_OPC(8 downto 4);
Q_ALU_OP <= ALU_BIT_CS;
Q_WE_F <= '1';
end if;
when "111111" => -- 1111 11xx xxxx xxxx
--
-- 1111 110r rrrr 0bbb - SBRC
-- 1111 111r rrrr 0bbb - SBRS
--
-- like SBIC, but and general purpose regs instead of I/O regs.
--
Q_ALU_OP <= ALU_BIT_CS;
Q_AMOD <= AMOD_ABS;
Q_BIT(3) <= I_OPC(9); -- set/clear bit
Q_IMM(4 downto 0) <= I_OPC(8 downto 4);
if (I_T0 = '0') then
Q_PC_OP <= PC_SKIP_T;
end if;
when others =>
end case;
end if;
end process;
end Behavioral;
| gpl-2.0 | f9cb7139e749bf4106602646709e0a92 | 0.299088 | 4.32958 | false | false | false | false |
autosub-team/autosub | src/tests/testTasksVHDL/testsubmissions/gates/desc/IEEE_1164_Gates_beh.vhdl | 2 | 2,305 | library ieee;
use ieee.std_logic_1164.all;
--##########################
--######## AND GATES #######
--##########################
architecture behavior of AND2 is
begin
O<= I1 and I2;
end architecture behavior;
architecture behavior of AND3 is
begin
O<= I1 and I2 and I3;
end architecture behavior;
architecture behavior of AND4 is
begin
O<= I1 and I2 and I3 and I4;
end architecture behavior;
--##########################
--######## NAND GATES ######
--##########################
architecture behavior of NAND2 is
begin
O<= not(I1 and I2);
end architecture behavior;
architecture behavior of NAND3 is
begin
O<= not(I1 and I2 and I3);
end architecture behavior;
architecture behavior of NAND4 is
begin
O<= not(I1 and I2 and I3 and I4);
end architecture behavior;
--##########################
--######## OR GATES ########
--##########################
architecture behavior of OR2 is
begin
O<= I1 or I2;
end architecture behavior;
architecture behavior of OR3 is
begin
O<= I1 or I2 or I3;
end architecture behavior;
architecture behavior of OR4 is
begin
O<= I1 or I2 or I3 or I4;
end architecture behavior;
--##########################
--######## NOR GATES #######
--##########################
architecture behavior of NOR2 is
begin
O<= not(I1 or I2);
end architecture behavior;
architecture behavior of NOR3 is
begin
O<= not(I1 or I2 or I3);
end architecture behavior;
architecture behavior of NOR4 is
begin
O<= not(I1 or I2 or I3 or I4);
end architecture behavior;
--##########################
--######## XOR GATES #######
--##########################
architecture behavior of XOR2 is
begin
O<= I1 xor I2;
end architecture behavior;
architecture behavior of XOR3 is
begin
O<= I1 xor I2 xor I3;
end architecture behavior;
architecture behavior of XOR4 is
begin
O<= I1 xor I2 xor I3 xor I4;
end architecture behavior;
--##########################
--######## XNOR GATES ######
--##########################
architecture behavior of XNOR2 is
begin
O<= not(I1 xor I2);
end architecture behavior;
architecture behavior of XNOR3 is
begin
O<= not(I1 xor I2 xor I3);
end architecture behavior;
architecture behavior of XNOR4 is
begin
O<= not(I1 xor I2 xor I3 xor I4);
end architecture behavior;
| gpl-2.0 | 1502164eec42382c9950c6fb3b1a12f2 | 0.582213 | 3.854515 | false | false | false | false |
tsotnep/vhdl_soc_audio_mixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/filter_v1_00_a/hdl/vhdl/IIR_Biquad_1.vhd | 3 | 27,481 | --////////////////////// IIR_Biquad_I //////////////////////////////////--
-- ***********************************************************************
-- FileName: IIR_Biquad_1.vhd
-- FPGA: Xilinx Spartan 6
-- IDE: Xilinx ISE 13.1
--
-- HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
-- DIGI-KEY ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
-- INFRINGEMENT.
--
-- Version History
-- Version 1.0 7/31/2012 Tony Storey
-- Initial Public Releaselibrary ieee;
-- This biquad is set up for 18 bit input words with 32 bit coefficients
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity IIR_Biquad is
Port (
clk : in STD_LOGIC;
n_reset : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR (23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR (23 downto 0)
);
end IIR_Biquad;
architecture arch of IIR_Biquad is
-- -- Used Bilinear Z Transform
-- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
--------------------------------------------------------------------------
--
-- b0 + b1*Z^-1 + b2*Z^-2
-- H[z] = -------------------------
-- 1 + a1*Z^-1 + a2*Z^-2
--
--------------------------------------------------------------------------
-- define biquad coefficients WORKED WITH HIGH SOUND
constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_1110_0011_1110_0101_0110_0111_1100"; -- b0 ~ +0.2225548
constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_01_1100_0111_1100_1010_1100_1000_1110"; -- b1 ~ +0.4451095
constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_1110_0011_1110_0101_0110_0111_1100"; -- b2 ~ +0.2225548
constant Coef_a1 : std_logic_vector(31 downto 0) := B"11_10_1010_0110_1001_1101_0101_0001_1011"; -- a1 ~ -0.3372905
constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_01_0011_1000_0011_1100_1110_1100_0001"; -- a2 ~ +0.3049199
-- Pre Generated Example IIR filters
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- -- band pass 2nd order butterworth f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- define biquad coefficients -- DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0000_1111"; -- b0 ~ +0.061511769
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1111_0001"; -- b0 ~ -0.061511769
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0101_0111"; -- a1 ~ -1.816910185
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0001_1110_0010"; -- a2 ~ +0.876976463
-- -- low pass 2nd order butt fl = 500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients WORKED BUT VERY LOW SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b0 ~ +0.0010232
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0010_0001_1000_0111_0011_1001"; -- b1 ~ +0.0020464
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b2 ~ +0.0010232
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0101_1110_1011_0111_1110_0110_1000"; -- a1 ~ -1.9075016
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_0101_0111_1001_0000_0111_0101"; -- a2 ~ +0.9115945
---- -- stop band 2nd order cheb f0 = 2828.47, Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
---- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
---- --------------------------------------------------------------------------
----
---- define biquad coefficients -- WORKED WITH AVERAGE SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- -- band pass 2nd order elliptical fl= 2000Hz, fu = 2500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0100_1001_0001_0011_0101_0100_0111"; -- b0 ~ +0.0713628
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ +0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1011_0110_1110_1100_1010_1011_1000"; -- b2 ~ -0.0713628
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1110_0011_0001_0001_1010_1011_1111"; -- a1 ~ -1.7782529**
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0110_1101_1101_1001_0101_0111_0001"; -- a2 ~ +0.8572744
-- -- Used Bilinear Z Transform
-- -- low pass 2nd order butterworth fc = 12000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients WORKED WITH HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b0 ~ +0.292893219
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_10_0101_0111_1101_1000_0110_0110_0110"; -- b1 ~ +0.585786438
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b2 ~ +0.292893219
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- a1 ~ 0.0
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0101_0111_1101_1000"; -- a2 ~ +0.171572875***
-- -- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b0 ~ +0.9993459
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- b1 ~ -1.9986306
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b2 ~ +0.9993459
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- a1 ~
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_1110_1010_1001_0001_0110_1110"; -- a2 ~ +0.9986919
--
-- -- stop band 2nd order ellip fl = 500Hz, fu = 2000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients WORKED BUT WITH LOW SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b0 ~ +0.9597323
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- b1 ~ -1.9029905
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b2 ~ +0.9597323
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- a1 ~ -1.9029905
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_1101_1000_1000_0010_0111_1000"; -- a2 ~ +0.9194647
-- -- low pass 2nd order cheb fc = 10000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients WORKED WITH HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_01_1100_0010_1111_0101_0111_0000_0101"; -- b1 ~ 0.4403894
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"11_10_1100_0101_0000_1101_0101_0000_0100"; -- a1 ~ -0.3075664
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_1100_0000_1101_1101_1001_0000_0110"; -- a2 ~ +0.1883452
-- -- band pass 2nd order cheb f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0011_0000"; -- b0 ~ +0.0615118
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1100_1111"; -- b0 ~ -0.0615118**
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0100_1000"; -- a1 ~ -1.8169102
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0010_0000_1011"; -- a2 ~ +0.8769765
-- define each pre gain sample flip flop
signal ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2 : std_logic_vector(23 downto 0) := (others => '0');
-- define each post gain 64 bit sample
signal pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad : std_logic_vector( 55 downto 0) := (others => '0');
-- define each post gain 32 but truncated sample
signal pgZFF_X0, pgZFF_X1, pgZFF_X2, pgZFF_Y1, pgZFF_Y2 : std_logic_vector(23 downto 0) := (others => '0');
-- define output double reg
signal Y_out_double : std_logic_vector( 23 downto 0) := (others => '0');
-- state machine signals
type state_type is (idle, run);
signal state_reg, state_next : state_type;
-- counter signals
signal q_reg, q_next : unsigned(2 downto 0);
signal q_reset, q_add : std_logic;
-- data path flags
signal mul_coefs, trunc_prods, sum_stg_a, trunc_out : std_logic;
begin
-- process to shift samples
process(clk, n_reset, Y_out_double, sample_trig)
begin
if(n_reset = '1') then
ZFF_X0 <= (others => '0');
ZFF_X1 <= (others => '0');
ZFF_X2 <= (others => '0');
ZFF_Y1 <= (others => '0');
ZFF_Y2 <= (others => '0');
elsif(rising_edge(clk)) then
if(sample_trig = '1' and state_reg = idle)
then
ZFF_X0 <= X_in(23) & X_in(23 downto 1);
ZFF_X1 <= ZFF_X0;
ZFF_X2 <= ZFF_X1;
ZFF_Y1 <= Y_out_double;
ZFF_Y2 <= ZFF_Y1;
end if;
end if;
end process;
-- STATE UPDATE AND TIMING
process(clk, n_reset)
begin
if(n_reset = '1') then
state_reg <= idle;
q_reg <= (others => '0'); -- reset counter
elsif (rising_edge(clk)) then
state_reg <= state_next; -- update the state
q_reg <= q_next;
end if;
end process;
-- COUNTER FOR TIMING
q_next <= (others => '0') when q_reset = '1' else -- resets the counter
q_reg + 1 when q_add = '1' else -- increment count if commanded
q_reg;
-- process for control of data path flags
process( q_reg, state_reg, sample_trig)
begin
-- defaults
q_reset <= '0';
q_add <= '0';
mul_coefs <= '0';
trunc_prods <= '0';
sum_stg_a <= '0';
trunc_out <= '0';
filter_done <= '0';
case state_reg is
when idle =>
if(sample_trig = '1') then
state_next <= run;
else
state_next <= idle;
end if;
when run =>
if( q_reg < "001") then
q_add <= '1';
state_next <= run;
elsif( q_reg < "011") then
mul_coefs <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "100") then
trunc_prods <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "101") then
sum_stg_a <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "110") then
trunc_out <= '1';
q_add <= '1';
state_next <= run;
else
q_reset <= '1';
filter_done <= '1';
state_next <= idle;
end if;
end case;
end process;
-- add gain factors to numerator of biquad (feed forward path)
pgZFF_X0_quad <= std_logic_vector( signed(Coef_b0) * signed(ZFF_X0)) when mul_coefs = '1';
pgZFF_X1_quad <= std_logic_vector( signed(Coef_b1) * signed(ZFF_X1)) when mul_coefs = '1';
pgZFF_X2_quad <= std_logic_vector( signed(Coef_b2) * signed(ZFF_X2)) when mul_coefs = '1';
-- add gain factors to denominator of biquad (feed back path)
pgZFF_Y1_quad <= std_logic_vector( signed(Coef_a1) * signed(ZFF_Y1)) when mul_coefs = '1';
pgZFF_Y2_quad <= std_logic_vector( signed(Coef_a2) * signed(ZFF_Y2)) when mul_coefs = '1';
-- truncate the output to summation block
process(clk, trunc_prods, pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad)
begin
if rising_edge(clk) then
if (trunc_prods = '1') then
pgZFF_X0 <= pgZFF_X0_quad(55 downto 32);
pgZFF_X2 <= pgZFF_X2_quad(55 downto 32);
pgZFF_X1 <= pgZFF_X1_quad(55 downto 32);
pgZFF_Y1 <= pgZFF_Y1_quad(55 downto 32);
pgZFF_Y2 <= pgZFF_Y2_quad(55 downto 32);
end if;
end if;
end process;
-- sum all post gain feedback and feedfoward paths
-- Y[z] = X[z]*bo + X[z]*b1*Z^-1 + X[z]*b2*Z^-2 - Y[z]*a1*z^-1 + Y[z]*a2*z^-2
process(clk, sum_stg_a)
begin
if(rising_edge(clk)) then
if(sum_stg_a = '1') then
Y_out_double <= std_logic_vector(signed(pgZFF_X0) + signed(pgZFF_X1) + signed(pgZFF_X2) - signed(pgZFF_Y1) - signed(pgZFF_Y2)); --std_logic_vector((pgZFF_X0));--
end if;
end if;
end process;
-- output truncation block
process(clk, trunc_out)
begin
if rising_edge(clk) then
if (trunc_out = '1') then
Y_out <= Y_out_double( 23 downto 0);
end if;
end if;
end process;
end arch;
-- Pre Generated Example IIR filters
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- -- band pass 2nd order butterworth f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0000_1111"; -- b0 ~ +0.061511769
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1111_0001"; -- b0 ~ -0.061511769
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0101_0111"; -- a1 ~ -1.816910185
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0001_1110_0010"; -- a2 ~ +0.876976463
-- -- low pass 2nd order butt fl = 500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b0 ~ +0.0010232
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0010_0001_1000_0111_0011_1001"; -- b1 ~ +0.0020464
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b2 ~ +0.0010232
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0101_1110_1011_0111_1110_0110_1000"; -- a1 ~ -1.9075016
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_0101_0111_1001_0000_0111_0101"; -- a2 ~ +0.9115945
---- -- stop band 2nd order cheb f0 = 2828.47, Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
---- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
---- --------------------------------------------------------------------------
----
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- -- band pass 2nd order elliptical fl= 2000Hz, fu = 2500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0100_1001_0001_0011_0101_0100_0111"; -- b0 ~ +0.0713628
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ +0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1011_0110_1110_1100_1010_1011_1000"; -- b2 ~ -0.0713628
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1110_0011_0001_0001_1010_1011_1111"; -- a1 ~ -1.7782529
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0110_1101_1101_1001_0101_0111_0001"; -- a2 ~ +0.8572744
-- -- Used Bilinear Z Transform
-- -- low pass 2nd order butterworth fc = 12000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b0 ~ +0.292893219
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_10_0101_0111_1101_1000_0110_0110_0110"; -- b1 ~ +0.585786438
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b2 ~ +0.292893219
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- a1 ~ 0.0
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0101_0111_1101_1000"; -- a2 ~ +0.171572875
-- -- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b0 ~ +0.9993459
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- b1 ~ -1.9986306
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b2 ~ +0.9993459
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- a1 ~ -1.9986306
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_1110_1010_1001_0001_0110_1110"; -- a2 ~ +0.9986919
--
-- -- stop band 2nd order ellip fl = 500Hz, fu = 2000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b0 ~ +0.9597323
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- b1 ~ -1.9029905
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b2 ~ +0.9597323
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- a1 ~ -1.9029905
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_1101_1000_1000_0010_0111_1000"; -- a2 ~ +0.9194647
--
-- -- low pass 2nd order cheb fc = 10000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_01_1100_0010_1111_0101_0111_0000_0101"; -- b1 ~ 0.4403894
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"11_10_1100_0101_0000_1101_0101_0000_0100"; -- a1 ~ -0.3075664
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_1100_0000_1101_1101_1001_0000_0110"; -- a2 ~ +0.1883452
-- -- band pass 2nd order cheb f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0011_0000"; -- b0 ~ +0.0615118
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1100_1111"; -- b0 ~ -0.0615118
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0100_1000"; -- a1 ~ -1.8169102
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0010_0000_1011"; -- a2 ~ +0.8769765
| mit | f9a4caea3de66b04bdfc8d39cdcdf3af | 0.495324 | 2.789949 | false | false | false | false |
kb3gtn/mojo_modulator | vhdl/testbench/top_level_tb/mojo_top_tb.vhd | 1 | 6,247 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:38:40 07/06/2014
-- Design Name:
-- Module Name: /home/kb3gtn/sandbox/mojo_modulator/vhdl/testbench/top_level_tb/mojo_top_tb.vhd
-- Project Name: mojo_modulator
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: mojo_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY mojo_top_tb IS
END mojo_top_tb;
ARCHITECTURE behavior OF mojo_top_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mojo_top
PORT(
i_clk50m : IN std_logic;
i_rst_n : IN std_logic;
o_serial_tx : OUT std_logic;
i_serial_rx : IN std_logic;
o_led : OUT std_logic_vector(7 downto 0);
o_dac_pin_mode : OUT std_logic;
o_dac_sleep : OUT std_logic;
o_dac_mode : OUT std_logic;
o_dac_cmode : OUT std_logic;
o_dac_clk_p : OUT std_logic;
o_dac_clk_n : OUT std_logic;
o_dac_DB : OUT signed(11 downto 0)
);
END COMPONENT;
--Inputs
signal i_clk50m : std_logic := '0';
signal i_rst_n : std_logic := '0';
signal i_serial_rx : std_logic := '0';
--Outputs
signal o_serial_tx : std_logic;
signal o_led : std_logic_vector(7 downto 0);
signal o_dac_pin_mode : std_logic;
signal o_dac_sleep : std_logic;
signal o_dac_mode : std_logic;
signal o_dac_cmode : std_logic;
signal o_dac_clk_p : std_logic;
signal o_dac_clk_n : std_logic;
signal o_dac_DB : signed(11 downto 0);
constant clk50_period : time := 10 ns; -- 1/2 period on 50 MHz clk
constant tx_bit_period : time := 4.34 us; -- 1/2 period of 115200 bit period
signal serial_ce : std_logic; -- clock enable for serial generation procedure
-- procedure to send a byte of data as a rs232 serial stream
procedure serial_send (
constant input_byte : in std_logic_vector(7 downto 0);
signal tx_out : out std_logic
) is
begin
tx_out <= '1'; -- idle state;
wait until rising_edge( serial_ce );
tx_out <= '0'; -- tx start bit.
wait until rising_edge( serial_ce );
tx_out <= input_byte(0);
wait until rising_edge( serial_ce );
tx_out <= input_byte(1);
wait until rising_edge( serial_ce );
tx_out <= input_byte(2);
wait until rising_edge( serial_ce );
tx_out <= input_byte(3);
wait until rising_edge( serial_ce );
tx_out <= input_byte(4);
wait until rising_edge( serial_ce );
tx_out <= input_byte(5);
wait until rising_edge( serial_ce );
tx_out <= input_byte(6);
wait until rising_edge( serial_ce );
tx_out <= input_byte(7);
wait until rising_edge( serial_ce );
tx_out <= '0'; -- stop bit
wait until rising_edge( serial_ce );
tx_out <= '1'; -- back to idle
wait until rising_edge( serial_ce );
wait until rising_edge( serial_ce );
wait until rising_edge( serial_ce );
wait until rising_edge( serial_ce );
wait until rising_edge( serial_ce );
wait until rising_edge( serial_ce );
end procedure;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mojo_top PORT MAP (
i_clk50m => i_clk50m,
i_rst_n => i_rst_n,
o_serial_tx => o_serial_tx,
i_serial_rx => i_serial_rx,
o_led => o_led,
o_dac_pin_mode => o_dac_pin_mode,
o_dac_sleep => o_dac_sleep,
o_dac_mode => o_dac_mode,
o_dac_cmode => o_dac_cmode,
o_dac_clk_p => o_dac_clk_p,
o_dac_clk_n => o_dac_clk_n,
o_dac_DB => o_dac_DB
);
-- Clock process definitions
clk_50_process :process
begin
i_clk50m <= '0';
wait for clk50_period/2;
i_clk50m <= '1';
wait for clk50_period/2;
end process;
-- serial_ce_gen
serial_ce_gen : process
begin
serial_ce <= '0';
wait for tx_bit_period/2;
serial_ce <= '1';
wait for tx_bit_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
i_serial_rx <= '1'; -- idle is high
i_rst_n <= '0'; -- reset asserted board level
wait for 30 ns;
i_rst_n <= '1'; -- reset deasserted on board level
-- wait for 700 us; -- wait for reset and DCM to lock in simulation.
--
-- turn LEDs on ( address 0x03 )
serial_send( x"00", i_serial_rx );
wait for 40 us;
serial_send( x"55", i_serial_rx );
wait for 40 us;
serial_send( x"00", i_serial_rx );
wait for 40 us;
serial_send( x"AA", i_serial_rx );
wait for 40 us;
--
-- read back value from led register
serial_send( x"80", i_serial_rx );
wait for 40 us;
--
-- load nco with a value
serial_send( x"08", i_serial_rx );
wait for 40 us;
serial_send( x"33", i_serial_rx );
wait for 40 us;
--
serial_send( x"09", i_serial_rx );
wait for 40 us;
serial_send( x"33", i_serial_rx );
wait for 40 us;
--
serial_send( x"0A", i_serial_rx );
wait for 40 us;
serial_send( x"33", i_serial_rx );
wait for 40 us;
--
serial_send( x"0B", i_serial_rx );
wait for 40 us;
serial_send( x"03", i_serial_rx );
wait for 40 us;
--
--
-- let nco run..
wait for 100 us;
--
--
wait;
end process;
END;
| apache-2.0 | 2dc65b2e1355ff8d5a9e3e0489eaa212 | 0.5417 | 3.391422 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/dsp_round.vhd | 1 | 5,627 | ----------------------------------------------------------------------------------
-- Company: ESA
-- Engineer: Felix Winterstein
--
-- Create Date: 06.04.2013 21:02:35
-- Design Name:
-- Module Name: dsp_round - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity dsp_round is
generic (
BITWIDTH_IN : integer := 32;
BITWIDTH_OUT : integer := 32
);
port (
sclr : in std_logic;
nd : in std_logic;
AB_IN : in std_logic_vector (BITWIDTH_IN-1 downto 0);
CARRYIN_IN : in std_logic;
CLK_IN : in std_logic;
C_IN : in std_logic_vector (BITWIDTH_IN-1 downto 0);
P_OUT : out std_logic_vector (BITWIDTH_OUT-1 downto 0);
rdy : out std_logic
);
end dsp_round;
architecture BEHAVIORAL of dsp_round is
constant LAT : integer := 2;
signal GND_ALUMODE : std_logic;
signal GND_BUS_3 : std_logic_vector (2 downto 0);
signal GND_BUS_18 : std_logic_vector (17 downto 0);
signal GND_BUS_30 : std_logic_vector (29 downto 0);
signal GND_BUS_48 : std_logic_vector (47 downto 0);
signal GND_OPMODE : std_logic;
signal VCC_OPMODE : std_logic;
signal ab_in_ext : std_logic_vector(47 downto 0);
signal c_in_ext : std_logic_vector(47 downto 0);
signal p_out_ext : std_logic_vector(47 downto 0);
signal delay_line : std_logic_vector(0 to LAT-1);
begin
GND_ALUMODE <= '0';
GND_BUS_3(2 downto 0) <= "000";
GND_BUS_18(17 downto 0) <= "000000000000000000";
GND_BUS_30(29 downto 0) <= "000000000000000000000000000000";
GND_BUS_48(47 downto 0) <=
"000000000000000000000000000000000000000000000000";
GND_OPMODE <= '0';
VCC_OPMODE <= '1';
ab_in_ext(47 downto BITWIDTH_IN) <= (others => AB_IN(BITWIDTH_IN-1));
ab_in_ext(BITWIDTH_IN-1 downto 0) <= AB_IN;
c_in_ext(47 downto BITWIDTH_IN) <= (others => C_IN(BITWIDTH_IN-1));
c_in_ext(BITWIDTH_IN-1 downto 0) <= C_IN;
DSP48E_INST : DSP48E
generic map( ACASCREG => 1,
ALUMODEREG => 0,
AREG => 1,
AUTORESET_PATTERN_DETECT => FALSE,
AUTORESET_PATTERN_DETECT_OPTINV => "MATCH",
A_INPUT => "DIRECT",
BCASCREG => 1,
BREG => 1,
B_INPUT => "DIRECT",
CARRYINREG => 1,
CARRYINSELREG => 0,
CREG => 1,
MASK => x"3FFFFFFFFFFF",
MREG => 1,
MULTCARRYINREG => 1,
OPMODEREG => 0,
PATTERN => x"000000000000",
PREG => 1,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
SEL_ROUNDING_MASK => "SEL_MASK",
USE_MULT => "NONE",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48")
port map (A(29 downto 0)=>ab_in_ext(47 downto 18),
ACIN(29 downto 0)=>GND_BUS_30(29 downto 0),
ALUMODE(3)=>GND_ALUMODE,
ALUMODE(2)=>GND_ALUMODE,
ALUMODE(1)=>GND_ALUMODE,
ALUMODE(0)=>GND_ALUMODE,
B(17 downto 0)=>ab_in_ext(17 downto 0),
BCIN(17 downto 0)=>GND_BUS_18(17 downto 0),
C(47 downto 0)=>c_in_ext(47 downto 0),
CARRYCASCIN=>GND_ALUMODE,
CARRYIN=>CARRYIN_IN,
CARRYINSEL(2 downto 0)=>GND_BUS_3(2 downto 0),
CEALUMODE=>VCC_OPMODE,
CEA1=>VCC_OPMODE,
CEA2=>VCC_OPMODE,
CEB1=>VCC_OPMODE,
CEB2=>VCC_OPMODE,
CEC=>VCC_OPMODE,
CECARRYIN=>VCC_OPMODE,
CECTRL=>VCC_OPMODE,
CEM=>VCC_OPMODE,
CEMULTCARRYIN=>VCC_OPMODE,
CEP=>VCC_OPMODE,
CLK=>CLK_IN,
MULTSIGNIN=>GND_ALUMODE,
OPMODE(6)=>GND_OPMODE,
OPMODE(5)=>VCC_OPMODE,
OPMODE(4)=>VCC_OPMODE,
OPMODE(3)=>GND_OPMODE,
OPMODE(2)=>GND_OPMODE,
OPMODE(1)=>VCC_OPMODE,
OPMODE(0)=>VCC_OPMODE,
PCIN(47 downto 0)=>GND_BUS_48(47 downto 0),
RSTA=>GND_ALUMODE,
RSTALLCARRYIN=>GND_ALUMODE,
RSTALUMODE=>GND_ALUMODE,
RSTB=>GND_ALUMODE,
RSTC=>GND_ALUMODE,
RSTCTRL=>GND_ALUMODE,
RSTM=>GND_ALUMODE,
RSTP=>GND_ALUMODE,
ACOUT=>open,
BCOUT=>open,
CARRYCASCOUT=>open,
CARRYOUT=>open,
MULTSIGNOUT=>open,
OVERFLOW=>open,
P(47 downto 0)=>p_out_ext(47 downto 0),
PATTERNBDETECT=>open,
PATTERNDETECT=>open,
PCOUT=>open,
UNDERFLOW=>open);
P_OUT <= p_out_ext(BITWIDTH_IN-1 downto BITWIDTH_IN-BITWIDTH_OUT);
delay_line_proc : process(CLK_IN)
begin
if rising_edge(CLK_IN) then
if sclr = '1' then
delay_line <= (others => '0');
else
delay_line(0) <= nd;
delay_line(1 to LAT-1) <= delay_line(0 to LAT-2);
end if;
end if;
end process delay_line_proc;
rdy <= delay_line(LAT-1);
end BEHAVIORAL;
| bsd-3-clause | ad2ee34daebdd4438e53fef958a85b07 | 0.498667 | 3.862045 | false | false | false | false |
mithro/HDMI2USB | hdl/jpeg_encoder/design/FIFO.vhd | 5 | 8,669 | -- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity RAMF is
generic (
RAMD_W : INTEGER := 12;
RAMA_W : INTEGER := 6
);
port (
d : in STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMD_W-1 downto 0)
);
end RAMF;
architecture RTL of RAMF is
type mem_type is array ((2**RAMA_W)-1 downto 0) of
STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
signal mem : mem_type;
signal read_addr : STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
begin
-------------------------------------------------------------------------------
q_sg:
-------------------------------------------------------------------------------
q <= mem(TO_INTEGER(UNSIGNED(read_addr)));
-------------------------------------------------------------------------------
read_proc: -- register read address
-------------------------------------------------------------------------------
process (clk)
begin
if clk = '1' and clk'event then
read_addr <= raddr;
end if;
end process;
-------------------------------------------------------------------------------
write_proc: --write access
-------------------------------------------------------------------------------
process (clk) begin
if clk = '1' and clk'event then
if we = '1' then
mem(TO_INTEGER(UNSIGNED(waddr))) <= d;
end if;
end if;
end process;
end RTL;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
library WORK;
entity FIFO is
generic (
DATA_WIDTH : INTEGER := 12;
ADDR_WIDTH : INTEGER := 2
);
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
rinc : in STD_LOGIC;
winc : in STD_LOGIC;
datai : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
datao : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
fullo : out STD_LOGIC;
emptyo : out STD_LOGIC;
count : out STD_LOGIC_VECTOR (ADDR_WIDTH downto 0)
);
end FIFO;
architecture RTL of FIFO is
signal raddr_reg : unsigned(ADDR_WIDTH-1 downto 0);
signal waddr_reg : unsigned(ADDR_WIDTH-1 downto 0);
signal count_reg : unsigned(ADDR_WIDTH downto 0);
signal rd_en_reg : STD_LOGIC;
signal wr_en_reg : STD_LOGIC;
signal empty_reg : STD_LOGIC;
signal full_reg : STD_LOGIC;
signal ramq : STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
signal ramd : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal ramwaddr : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
signal ramenw : STD_LOGIC;
signal ramraddr : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
signal ramenr : STD_LOGIC;
constant ZEROS_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '0');
constant ONES_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
component RAMF
generic (
RAMD_W : INTEGER := 12;
RAMA_W : INTEGER := 6
);
port (
d : in STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMD_W-1 downto 0)
);
end component;
begin
U_RAMF : RAMF
generic map (
RAMD_W => DATA_WIDTH,
RAMA_W => ADDR_WIDTH
)
port map (
d => ramd,
waddr => ramwaddr,
raddr => ramraddr,
we => ramenw,
clk => clk,
q => ramq
);
ramd <= datai;
ramwaddr <= std_logic_vector(waddr_reg);
ramenw <= wr_en_reg;
ramraddr <= std_logic_vector(raddr_reg);
ramenr <= '1';
datao <= ramq;
emptyo <= empty_reg;
fullo <= full_reg;
rd_en_reg <= (rinc and not empty_reg);
wr_en_reg <= (winc and not full_reg);
count <= std_logic_vector(count_reg);
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
empty_reg <= '1';
else
if count_reg = unsigned(ZEROS_C) or
(count_reg = 1 and rd_en_reg = '1' and wr_en_reg = '0') then
empty_reg <= '1';
else
empty_reg <= '0';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
full_reg <= '0';
else
if count_reg = 2**ADDR_WIDTH or
(count_reg = 2**ADDR_WIDTH-1 and wr_en_reg = '1' and rd_en_reg = '0') then
full_reg <= '1';
else
full_reg <= '0';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
raddr_reg <= (others => '0');
else
if rd_en_reg = '1' then
raddr_reg <= raddr_reg + to_unsigned(1, raddr_reg'length);
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
waddr_reg <= (others => '0');
else
if wr_en_reg = '1' then
waddr_reg <= waddr_reg + to_unsigned(1, waddr_reg'length);
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
count_reg <= (others => '0');
else
if (rd_en_reg = '1' and wr_en_reg = '0') or (rd_en_reg = '0' and wr_en_reg = '1') then
if rd_en_reg = '1' then
count_reg <= count_reg - to_unsigned(1, count_reg'length);
else
count_reg <= count_reg + to_unsigned(1, count_reg'length);
end if;
end if;
end if;
end if;
end process;
end RTL;
| bsd-2-clause | c432cfdfa8845bcf7b8e9e55f98a1921 | 0.465567 | 4.069953 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-2/thirty_two_bit_alu.vhd | 1 | 5,396 | library IEEE;
use ieee.std_logic_1164.all;
entity thirty_two_bit_alu is
port(
a, bout : in std_logic_vector(31 downto 0);
less, ainvert, binvert, cin, clk, rst, pre, ce : in std_logic;
ALUOp : in std_logic_vector(1 downto 0);
result : out std_logic_vector(31 downto 0);
cout, set, overflow, zero, bne : out std_logic);
end thirty_two_bit_alu;
architecture behav of thirty_two_bit_alu is
signal c : std_logic_vector(30 downto 0) := (others => '0');
signal add : std_logic_vector(31 downto 0);
signal zeroOut : std_logic;
begin
--Instances
ADD1 : entity work.alu(behav) port map(a(0), bout(0), less, ainvert, binvert, cin, ALUOp, c(0), add(0), set, overflow);
ADD2 : entity work.alu(behav) port map(a(1), bout(1), less, ainvert, binvert, c(0), ALUOp, c(1), add(1), set, overflow);
ADD3 : entity work.alu(behav) port map(a(2), bout(2), less, ainvert, binvert, c(1), ALUOp, c(2), add(2), set, overflow);
ADD4 : entity work.alu(behav) port map(a(3), bout(3), less, ainvert, binvert, c(2), ALUOp, c(3), add(3), set, overflow);
ADD5 : entity work.alu(behav) port map(a(4), bout(4), less, ainvert, binvert, c(3), ALUOp, c(4), add(4), set, overflow);
ADD6 : entity work.alu(behav) port map(a(5), bout(5), less, ainvert, binvert, c(4), ALUOp, c(5), add(5), set, overflow);
ADD7 : entity work.alu(behav) port map(a(6), bout(6), less, ainvert, binvert, c(5), ALUOp, c(6), add(6), set, overflow);
ADD8 : entity work.alu(behav) port map(a(7), bout(7), less, ainvert, binvert, c(6), ALUOp, c(7), add(7), set, overflow);
ADD9 : entity work.alu(behav) port map(a(8), bout(8), less, ainvert, binvert, c(7), ALUOp, c(8), add(8), set, overflow);
ADD10 : entity work.alu(behav) port map(a(9), bout(9), less, ainvert, binvert, c(8), ALUOp, c(9), add(9), set, overflow);
ADD11 : entity work.alu(behav) port map(a(10), bout(10), less, ainvert, binvert, c(9), ALUOp, c(10), add(10), set, overflow);
ADD12 : entity work.alu(behav) port map(a(11), bout(11), less, ainvert, binvert, c(10), ALUOp, c(11), add(11), set, overflow);
ADD13 : entity work.alu(behav) port map(a(12), bout(12), less, ainvert, binvert, c(11), ALUOp, c(12), add(12), set, overflow);
ADD14 : entity work.alu(behav) port map(a(13), bout(13), less, ainvert, binvert, c(12), ALUOp, c(13), add(13), set, overflow);
ADD15 : entity work.alu(behav) port map(a(14), bout(14), less, ainvert, binvert, c(13), ALUOp, c(14), add(14), set, overflow);
ADD16 : entity work.alu(behav) port map(a(15), bout(15), less, ainvert, binvert, c(14), ALUOp, c(15), add(15), set, overflow);
ADD17 : entity work.alu(behav) port map(a(16), bout(16), less, ainvert, binvert, c(15), ALUOp, c(16), add(16), set, overflow);
ADD18 : entity work.alu(behav) port map(a(17), bout(17), less, ainvert, binvert, c(16), ALUOp, c(17), add(17), set, overflow);
ADD19 : entity work.alu(behav) port map(a(18), bout(18), less, ainvert, binvert, c(17), ALUOp, c(18), add(18), set, overflow);
ADD20 : entity work.alu(behav) port map(a(19), bout(19), less, ainvert, binvert, c(18), ALUOp, c(19), add(19), set, overflow);
ADD21 : entity work.alu(behav) port map(a(20), bout(20), less, ainvert, binvert, c(19), ALUOp, c(20), add(20), set, overflow);
ADD22 : entity work.alu(behav) port map(a(21), bout(21), less, ainvert, binvert, c(20), ALUOp, c(21), add(21), set, overflow);
ADD23 : entity work.alu(behav) port map(a(22), bout(22), less, ainvert, binvert, c(21), ALUOp, c(22), add(22), set, overflow);
ADD24 : entity work.alu(behav) port map(a(23), bout(23), less, ainvert, binvert, c(22), ALUOp, c(23), add(23), set, overflow);
ADD25 : entity work.alu(behav) port map(a(24), bout(24), less, ainvert, binvert, c(23), ALUOp, c(24), add(24), set, overflow);
ADD26 : entity work.alu(behav) port map(a(25), bout(25), less, ainvert, binvert, c(24), ALUOp, c(25), add(25), set, overflow);
ADD27 : entity work.alu(behav) port map(a(26), bout(26), less, ainvert, binvert, c(25), ALUOp, c(26), add(26), set, overflow);
ADD28 : entity work.alu(behav) port map(a(27), bout(27), less, ainvert, binvert, c(26), ALUOp, c(27), add(27), set, overflow);
ADD29 : entity work.alu(behav) port map(a(28), bout(28), less, ainvert, binvert, c(27), ALUOp, c(28), add(28), set, overflow);
ADD30 : entity work.alu(behav) port map(a(29), bout(29), less, ainvert, binvert, c(28), ALUOp, c(29), add(29), set, overflow);
ADD31 : entity work.alu(behav) port map(a(30), bout(30), less, ainvert, binvert, c(29), ALUOp, c(30), add(30), set, overflow);
ADD32 : entity work.alu(behav) port map(a(31), bout(31), less, ainvert, binvert, c(30), ALUOp, cout, add(31), set, overflow);
result <= add;
zero <= zeroOut;
--zero <= '1' when (add = "00000000000000000000000000000000");
zeroOut <= '0' when ((add(0) = '1') or (add(2) = '1') or (add(3) = '1') or (add(4) = '1') or (add(5) = '1') or (add(6) = '1') or (add(7) = '1') or (add(8) = '1') or (add(9) = '1') or (add(10) = '1') or (add(11) = '1') or (add(12) = '1') or (add(13) = '1') or (add(14) = '1') or (add(15) = '1') or (add(16) = '1') or (add(17) = '1') or (add(18) = '1') or (add(19) = '1') or (add(20) = '1') or (add(21) = '1') or (add(22) = '1') or (add(23) = '1') or (add(24) = '1') or (add(25) = '1') or (add(26) = '1') or (add(27) = '1') or (add(28) = '1') or (add(29) = '1') or (add(30) = '1') or (add(31) = '1')) else '1';
bne <= '0' when (zeroOut = '1') else '1';
end behav; | gpl-3.0 | aeca7b4ee6b8980bbed3e21ca8c3a245 | 0.622869 | 2.610547 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/simulation/testbench.vhd | 1 | 13,260 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: testbench - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.all;
use ieee.math_real.all;
use STD.textio.all;
use work.filtering_algorithm_pkg.all;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
constant MY_N : integer := 2*128-1; -- 2*N_POINTS-1
constant MY_K : integer := 4;
-- input data
file my_input_tree : TEXT open READ_MODE is "../../simulation/tree_data_N128_K4_D3_s0.75.mat";
file my_input_cntr : TEXT open READ_MODE is "../../simulation/initial_centres_N128_K4_D3_s0.75_1.mat";
--file my_input_tree : TEXT open READ_MODE is "../../simulation/tree_data_N16384_K128_D3_s0.20.mat";
--file my_input_cntr : TEXT open READ_MODE is "../../simulation/initial_centres_N16384_K128_D3_s0.20_1.mat";
--file my_input_tree : TEXT open READ_MODE is "../../simulation/tree_data_N16384_K128_D3_s0.00.mat";
--file my_input_cntr : TEXT open READ_MODE is "../../simulation/initial_centres_N16384_K128_D3_s0.00_1.mat";
--file my_input_tree : TEXT open READ_MODE is "../../simulation/tree_data_N16384_K128_D3_s0.20_p4_4.mat";
--file my_input_cntr : TEXT open READ_MODE is "../../simulation/initial_centres_N16384_K128_D3_s0.20_1.mat";
-- Clock period definitions
constant CLK_PERIOD : time := 10 ns;
constant RESET_CYCLES : integer := 20;
constant INIT_CYCLES : integer := MY_N;
constant NUM_COLS : integer := 5+4*D;
type state_type is (readfile, reset, init, processing, processing_done);
type file_tree_data_array_type is array(0 to NUM_COLS-1, 0 to MY_N-1) of integer;
type file_cntr_data_array_type is array(0 to D-1, 0 to MY_K-1) of integer;
-- Component Declaration for the Unit Under Test (UUT)
component filtering_alogrithm_top
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
-- initial parameters
k : in centre_index_type;
root_address : in par_node_address_type;
-- init node and centre memory
wr_init_cent : in std_logic;
wr_centre_list_address_init : in centre_list_address_type;
wr_centre_list_data_init : in centre_index_type;
wr_init_node : in std_logic_vector(0 to PARALLEL_UNITS-1);
wr_node_address_init : in par_node_address_type;
wr_node_data_init : in par_node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
-- outputs
valid : out std_logic;
clusters_out : out data_type;
distortion_out : out coord_type_ext;
-- processing done
rdy : out std_logic
);
end component;
--Inputs
signal clk : std_logic;
signal sclr : std_logic := '1';
signal start : std_logic := '0';
-- initial parameters
signal k : centre_index_type;
signal root_address : node_address_type;
-- init node and centre memory
signal wr_init_cent : std_logic := '0';
signal wr_centre_list_address_init : centre_list_address_type;
signal wr_centre_list_data_init : centre_index_type;
signal wr_init_node : std_logic := '0';
signal wr_node_address_init : node_address_type;
signal wr_node_data_init : node_data_type;
signal wr_init_pos : std_logic := '0';
signal wr_centre_list_pos_address_init : centre_index_type;
signal wr_centre_list_pos_data_init : data_type;
-- Outputs
signal valid : std_logic;
signal clusters_out : data_type;
signal distortion_out : coord_type_ext;
signal rdy : std_logic;
-- file io
signal file_tree_data_array : file_tree_data_array_type;
signal file_cntr_data_array : file_cntr_data_array_type;
signal read_file_done : std_logic := '0';
-- Operation
signal state : state_type := readfile;
signal reset_counter : integer := 0;
signal init_counter : integer := 0;
signal reset_counter_done : std_logic := '0';
signal init_counter_done : std_logic := '0';
BEGIN
-- PARALLEL_UNITS == 1 always in testbench!!!
-- Instantiate the Unit Under Test (UUT)
uut : filtering_alogrithm_top
port map (
clk => clk,
sclr => sclr,
start => start ,
-- initial parameters
k => k,
root_address(0) => root_address,
-- init node and centre memory
wr_init_cent => wr_init_cent,
wr_centre_list_address_init => wr_centre_list_address_init,
wr_centre_list_data_init => wr_centre_list_data_init,
wr_init_node(0) => wr_init_node,
wr_node_address_init(0) => wr_node_address_init,
wr_node_data_init(0) => wr_node_data_init,
wr_init_pos => wr_init_pos,
wr_centre_list_pos_address_init => wr_centre_list_pos_address_init,
wr_centre_list_pos_data_init => wr_centre_list_pos_data_init,
-- outputs
valid => valid,
clusters_out => clusters_out,
distortion_out => distortion_out,
-- final result available
rdy => rdy
);
-- Clock process definitions
clk_process : process
begin
clk <= '1';
wait for CLK_PERIOD/2;
clk <= '0';
wait for CLK_PERIOD/2;
end process;
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if state = readfile AND read_file_done = '1' then
state <= reset;
elsif state = reset AND reset_counter_done = '1' then
state <= init;
elsif state = init AND init_counter_done = '1' then
state <= processing;
elsif state = processing AND rdy = '1' then
state <= processing_done;
end if;
end if;
end process fsm_proc;
counter_proc : process(clk)
begin
if rising_edge(clk) then
if state = reset then
reset_counter <= reset_counter+1;
end if;
if state = init then
init_counter <= init_counter+1;
end if;
end if;
end process counter_proc;
reset_counter_done <= '1' WHEN reset_counter = RESET_CYCLES-1 ELSE '0';
init_counter_done <= '1' WHEN init_counter = INIT_CYCLES-1 ELSE '0';
reset_proc : process(state)
begin
if state = reset then
sclr <= '1';
else
sclr <= '0';
end if;
end process reset_proc;
init_proc : process(state, init_counter)
variable centre_idx : centre_index_type;
variable centre_pos : data_type;
variable node : node_data_type;
begin
if state = init then
-- centre_index_memory
if init_counter < MY_K then
centre_idx := to_unsigned(init_counter,INDEX_BITWIDTH);
wr_init_cent <= '1';
wr_centre_list_address_init <= std_logic_vector(to_unsigned(0,CNTR_POINTER_BITWIDTH));--std_logic_vector(to_unsigned(file_tree_data_array(0,0),CNTR_POINTER_BITWIDTH));
wr_centre_list_data_init <= centre_idx;
else
wr_init_cent <= '0';
end if;
-- centre_positions_memory
if init_counter < MY_K then
for I in 0 to D-1 loop
centre_pos(I) := std_logic_vector(to_signed(file_cntr_data_array(I,init_counter),COORD_BITWIDTH));
end loop;
wr_init_pos <= '1';
wr_centre_list_pos_address_init <= to_unsigned(init_counter,INDEX_BITWIDTH);
wr_centre_list_pos_data_init <= centre_pos;
else
wr_init_pos <= '0';
end if;
-- tree_node_memory
if init_counter < MY_N then
for I in 0 to D-1 loop
node.bnd_lo(I) := std_logic_vector(to_signed(file_tree_data_array(5+0*D+I,init_counter),COORD_BITWIDTH));
node.bnd_hi(I) := std_logic_vector(to_signed(file_tree_data_array(5+1*D+I,init_counter),COORD_BITWIDTH));
node.midPoint(I) := std_logic_vector(to_signed(file_tree_data_array(5+2*D+I,init_counter),COORD_BITWIDTH));
node.wgtCent(I) := std_logic_vector(to_signed(file_tree_data_array(5+3*D+I,init_counter),COORD_BITWIDTH_EXT));
end loop;
node.sum_sq := std_logic_vector(to_signed(file_tree_data_array(4,init_counter),COORD_BITWIDTH_EXT));
node.count := std_logic_vector(to_signed(file_tree_data_array(3,init_counter),COORD_BITWIDTH));
node.left := std_logic_vector(to_unsigned(file_tree_data_array(1,init_counter),NODE_POINTER_BITWIDTH));
node.right := std_logic_vector(to_unsigned(file_tree_data_array(2,init_counter),NODE_POINTER_BITWIDTH));
wr_init_node <= '1';
wr_node_address_init <= std_logic_vector(to_unsigned(file_tree_data_array(0,init_counter),NODE_POINTER_BITWIDTH));
wr_node_data_init <= node;
else
wr_init_node <= '0';
end if;
else
wr_init_cent <= '0';
wr_init_node <= '0';
wr_init_pos <= '0';
end if;
end process init_proc;
processing_proc : process(state, init_counter_done)
variable centre_idx : centre_index_type;
variable centre_pos : data_type;
variable node : node_data_type;
begin
if state = init AND init_counter_done = '1' then
start <= '1';
k <= to_unsigned(MY_K-1,INDEX_BITWIDTH);
root_address <= std_logic_vector(to_unsigned(file_tree_data_array(0,0),NODE_POINTER_BITWIDTH));
else
start <= '0';
end if;
end process processing_proc;
-- read tree data and initial centres from file
read_file : process
variable my_line : LINE;
variable my_input_line : LINE;
variable tmp_line_counter_tree : integer;
variable tmp_line_counter_cntr : integer;
variable tmp_file_line_counter_cntr : integer;
variable tmp_d : integer;
variable tmp_file_data_tree : file_tree_data_array_type;
variable tmp_file_data_cntr : file_cntr_data_array_type;
begin
write(my_line, string'("reading input files"));
writeline(output, my_line);
tmp_line_counter_tree := 0;
loop
exit when endfile(my_input_tree) OR tmp_line_counter_tree = MY_N;
readline(my_input_tree, my_input_line);
for I in 0 to NUM_COLS-1 loop -- NUM_COLS columns
read(my_input_line,tmp_file_data_tree(I,tmp_line_counter_tree));
end loop;
tmp_line_counter_tree := tmp_line_counter_tree+1;
end loop;
file_tree_data_array <= tmp_file_data_tree;
write(my_line, string'("Number of lines:"));
writeline(output, my_line);
write(my_line, tmp_line_counter_tree);
writeline(output, my_line);
-- reading centres now
tmp_line_counter_cntr := 0;
tmp_file_line_counter_cntr := 0;
tmp_d := 0;
loop
exit when endfile(my_input_cntr) OR tmp_line_counter_cntr = D*MY_K;
readline(my_input_cntr, my_input_line);
read(my_input_line,tmp_file_data_cntr(tmp_d,tmp_file_line_counter_cntr));
-- if tmp_line_counter_cntr < MY_K then
-- read(my_input_line,tmp_file_data_cntr(0,tmp_line_counter_cntr));
-- else
-- read(my_input_line,tmp_file_data_cntr(1,tmp_line_counter_cntr-MY_K));
-- end if;
tmp_line_counter_cntr := tmp_line_counter_cntr+1;
tmp_file_line_counter_cntr := tmp_file_line_counter_cntr+1;
if tmp_file_line_counter_cntr = MY_K then
tmp_d := tmp_d +1;
tmp_file_line_counter_cntr := 0;
end if;
end loop;
file_cntr_data_array <= tmp_file_data_cntr;
write(my_line, string'("Number of lines:"));
writeline(output, my_line);
write(my_line, tmp_line_counter_cntr);
writeline(output, my_line);
read_file_done <= '1';
wait; -- one shot at time zero,
end process read_file;
END;
| bsd-3-clause | 6465d15298136a746f709f1a0a93f9c0 | 0.548341 | 3.680266 | false | false | false | false |
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