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Nooxet/embedded_bruteforce | vhdl/md5_demux.vhd | 3 | 1,412 | ----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: md5_demux - Behavioral
-- Description:
-- A demux to select which md5 to use for hashing
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- include the hash_array type --
use work.hash_array_pkg.all;
entity md5_demux is
generic (
N : integer
);
port (
i_md5_indata : in md5_indata_t;
i_select : in unsigned(N-1 downto 0); -- should be ceil(log2(N-1))
o_md5_indata_0 : out md5_indata_t; --_array(N-1 downto 0)
o_md5_indata_1 : out md5_indata_t --_array(N-1 downto 0)
);
end md5_demux;
architecture Behavioral of md5_demux is
begin
comb_proc : process(i_select, i_md5_indata)
begin
o_md5_indata_0.data_0 <= (others => '0');
o_md5_indata_0.data_1 <= (others => '0');
o_md5_indata_0.start <= '0';
o_md5_indata_0.len <= (others => '0');
o_md5_indata_1.data_0 <= (others => '0');
o_md5_indata_1.data_1 <= (others => '0');
o_md5_indata_1.start <= '0';
o_md5_indata_1.len <= (others => '0');
--o_md5_indata(to_integer(unsigned(i_select))) <= i_md5_indata;
if i_select = 0 then
o_md5_indata_0 <= i_md5_indata;
elsif i_select = 1 then
o_md5_indata_1 <= i_md5_indata;
end if;
end process;
end Behavioral;
| mit | dcb5e0a9cb06f0ce87e0b15a8466da65 | 0.541076 | 2.779528 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib/commandDecoder.vhd | 1 | 8,375 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: commandDecoder
-- Date:2011-10-07
-- Author: Andrzej Paluch
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.utilPkg.all;
entity commandDecoder is
port (
-------------------------------------------
-- data lines -----------------------------
-------------------------------------------
DI : in std_logic_vector (7 downto 0);
-------------------------------------------
-- control lines --------------------------
-------------------------------------------
-- DAV line
DAV_line : in std_logic;
-- NRFD line
NRFD_line : in std_logic;
-- NDAC line
NDAC_line : in std_logic;
-- ATN line
ATN_line : in std_logic;
-- EOI line
EOI_line : in std_logic;
-- SRQ line
SRQ_line : in std_logic;
-- IFC line
IFC_line : in std_logic;
-- REN line
REN_line : in std_logic;
-------------------------------------------
-- internal settiongs ---------------------
-------------------------------------------
-- eos mark
eosMark : in std_logic_vector (7 downto 0);
-- eos used
eosUsed : in std_logic;
-- my listen address
myListAddr : in std_logic_vector (4 downto 0);
-- my talk address
myTalkAddr : in std_logic_vector (4 downto 0);
-- secondary address detected
secAddrDetected : in std_logic;
-------------------------------------------
-- internal states ------------------------
-------------------------------------------
-- serial poll active state (T or TE)
SPAS : in std_logic;
-------------------------------------------
-- single line commands -------------------
-------------------------------------------
-- attention
ATN : out std_logic;
-- data accepted
DAC : out std_logic;
-- data valid
DAV : out std_logic;
-- end
END_c : out std_logic;
-- identify
IDY : out std_logic;
-- interface clear
IFC : out std_logic;
-- remote enable
REN : out std_logic;
-- ready for data
RFD : out std_logic;
-- service request
SRQ : out std_logic;
-------------------------------------------
-- multi line commands --------------------
-------------------------------------------
-- addressed command group
ACG : out std_logic;
-- data byte
DAB : out std_logic;
-- device clear
DCL : out std_logic;
-- end of string
EOS : out std_logic;
-- group execute trigger
GET : out std_logic;
-- go to local
GTL : out std_logic;
-- listen address group
LAG : out std_logic;
-- local lockout
LLO : out std_logic;
-- my listen address
MLA : out std_logic;
-- my talk address
MTA : out std_logic;
-- my secondary address
MSA : out std_logic;
-- null byte
NUL : out std_logic;
-- other secondary address
OSA : out std_logic;
-- other talk address
OTA : out std_logic;
-- primary command group
PCG : out std_logic;
-- parallel poll configure
PPC : out std_logic;
-- parallel poll enable
PPE : out std_logic;
-- parallel poll disable
PPD : out std_logic;
-- parallel poll response
PPR : out std_logic;
-- parallel poll unconfigure
PPU : out std_logic;
-- request service
RQS : out std_logic;
-- secondary command group
SCG : out std_logic;
-- selected device clear
SDC : out std_logic;
-- serial poll disable
SPD : out std_logic;
-- serial poll enable
SPE : out std_logic;
-- status byte
STB : out std_logic;
-- talk address group
TAG : out std_logic;
-- take control
TCT : out std_logic;
-- universal command group
UCG : out std_logic;
-- unlisten
UNL : out std_logic;
-- untalk
UNT : out std_logic
);
end commandDecoder;
architecture arch of commandDecoder is
signal ATN_int, IDY_int : std_logic;
signal SCG_int, MSA_int, TAG_int, MTA_int, ACG_int, UCG_int,
LAG_int, STB_int : std_logic;
begin
--------------------------------------
-- single line
--------------------------------------
ATN_int <= ATN_line;
ATN <= ATN_int;
----------------------
DAC <= not NDAC_line;
----------------------
DAV <= DAV_line;
----------------------
END_c <= not ATN_line and EOI_line;
----------------------
IDY_int <= ATN_line and EOI_line;
IDY <= IDY_int;
----------------------
IFC <= IFC_line;
----------------------
REN <= REN_line;
----------------------
RFD <= not NRFD_line;
----------------------
SRQ <= SRQ_line;
---------------------------------------
-- multiple line
---------------------------------------
ACG_int <= ATN_int and to_stdl(DI(6 downto 4) = "000");
ACG <= ACG_int;
---------------------------------------
DAB <= not ATN_int and ((eosUsed and to_stdl(DI /= eosMark)) or not eosUsed);
---------------------------------------
DCL <= ATN_int and to_stdl(DI(6 downto 0) = "0010100");
---------------------------------------
EOS <= not ATN_int and eosUsed and to_stdl(DI = eosMark);
---------------------------------------
GET <= ATN_int and to_stdl(DI(6 downto 0) = "0001000");
---------------------------------------
GTL <= ATN_int and to_stdl(DI(6 downto 0) = "0000001");
---------------------------------------
LAG_int <= ATN_int and to_stdl(DI(6 downto 5) = "01");
LAG <= LAG_int;
---------------------------------------
LLO <= ATN_int and to_stdl(DI(6 downto 0) = "0010001");
---------------------------------------
MLA <= LAG_int and to_stdl(DI(4 downto 0) = myListAddr);
---------------------------------------
MTA_int <= TAG_int and to_stdl(DI(4 downto 0) = myTalkAddr);
MTA <= MTA_int;
---------------------------------------
MSA_int <= SCG_int and secAddrDetected;
MSA <= MSA_int;
---------------------------------------
NUL <= ATN_int and to_stdl(DI = "00000000");
---------------------------------------
OSA <= SCG_int and not MSA_int;
---------------------------------------
OTA <= TAG_int and not MTA_int;
---------------------------------------
PCG <= ACG_int or UCG_int or LAG_int or TAG_int;
---------------------------------------
PPC <= ATN_int and to_stdl(DI(6 downto 0) = "0000101");
---------------------------------------
PPE <= ATN_int and to_stdl(DI(6 downto 4) = "110");
---------------------------------------
PPD <= ATN_int and to_stdl(DI(6 downto 4) = "111"); -- "-1110000" ?
---------------------------------------
PPR <= ATN_int and IDY_int;
---------------------------------------
PPU <= ATN_int and to_stdl(DI(6 downto 0) = "0010101");
---------------------------------------
RQS <= STB_int and to_stdl(DI(6) = '1');
---------------------------------------
SCG_int <= ATN_int and to_stdl(DI(6 downto 5) = "11");
SCG <= SCG_int;
---------------------------------------
SDC <= ATN_int and to_stdl(DI(6 downto 0) = "0000100");
---------------------------------------
SPD <= ATN_int and to_stdl(DI(6 downto 0) = "0011001");
---------------------------------------
SPE <= ATN_int and to_stdl(DI(6 downto 0) = "0011000");
---------------------------------------
STB_int <= not ATN_int and SPAS;
STB <= STB_int;
---------------------------------------
TAG_int <= ATN_int and to_stdl(DI(6 downto 5) = "10");
TAG <= TAG_int;
---------------------------------------
TCT <= ATN_int and to_stdl(DI(6 downto 0) = "0001001");
---------------------------------------
UCG_int <= ATN_int and to_stdl(DI(6 downto 4) = "001");
UCG <= UCG_int;
---------------------------------------
UNL <= ATN_int and to_stdl(DI(6 downto 0) = "0111111");
---------------------------------------
UNT <= ATN_int and to_stdl(DI(6 downto 0) = "1011111");
end arch;
| gpl-3.0 | f6aef67176217dbcbb4c3d45441f8b71 | 0.450149 | 3.81549 | false | false | false | false |
mithro/HDMI2USB | hdl/jpeg_encoder/design/SingleSM.vhd | 5 | 5,666 | -------------------------------------------------------------------------------
-- File Name : SingleSM.vhd
--
-- Project :
--
-- Module :
--
-- Content :
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
-------------------------------------------------------------------------------
-- History :
-- 20080301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;
entity SingleSM is
port
(
CLK : in std_logic;
RST : in std_logic;
-- from/to SM(m)
start_i : in std_logic;
idle_o : out std_logic;
-- from/to SM(m+1)
idle_i : in std_logic;
start_o : out std_logic;
-- from/to processing block
pb_rdy_i : in std_logic;
pb_start_o : out std_logic;
-- state debug
fsm_o : out std_logic_vector(1 downto 0)
);
end entity SingleSM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture SingleSM_rtl of SingleSM is
-------------------------------------------------------------------------------
-- Architecture: Signal definition.
-------------------------------------------------------------------------------
type T_STATE is (IDLE, WAIT_FOR_BLK_RDY, WAIT_FOR_BLK_IDLE);
signal state : T_STATE;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fsm_o <= "00" when state = IDLE else
"01" when state = WAIT_FOR_BLK_RDY else
"10" when state = WAIT_FOR_BLK_IDLE else
"11";
------------------------------------------------------------------------------
-- FSM
------------------------------------------------------------------------------
p_fsm : process(CLK, RST)
begin
if RST = '1' then
idle_o <= '0';
start_o <= '0';
pb_start_o <= '0';
state <= IDLE;
elsif CLK'event and CLK = '1' then
idle_o <= '0';
start_o <= '0';
pb_start_o <= '0';
case state is
when IDLE =>
idle_o <= '1';
-- this fsm is started
if start_i = '1' then
state <= WAIT_FOR_BLK_RDY;
-- start processing block associated with this FSM
pb_start_o <= '1';
idle_o <= '0';
end if;
when WAIT_FOR_BLK_RDY =>
-- wait until processing block completes
if pb_rdy_i = '1' then
-- wait until next FSM is idle before starting it
if idle_i = '1' then
state <= IDLE;
start_o <= '1';
else
state <= WAIT_FOR_BLK_IDLE;
end if;
end if;
when WAIT_FOR_BLK_IDLE =>
if idle_i = '1' then
state <= IDLE;
start_o <= '1';
end if;
when others =>
idle_o <= '0';
start_o <= '0';
pb_start_o <= '0';
state <= IDLE;
end case;
end if;
end process;
end architecture SingleSM_rtl;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
| bsd-2-clause | f075ef87ef97ffbcd9711dbd7e168678 | 0.405224 | 5.045414 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/image_selector_fifo/simulation/image_selector_fifo_pkg.vhd | 3 | 11,635 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: image_selector_fifo_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE image_selector_fifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT image_selector_fifo_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT image_selector_fifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT image_selector_fifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT image_selector_fifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT image_selector_fifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT image_selector_fifo_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(24-1 DOWNTO 0);
DOUT : OUT std_logic_vector(24-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END image_selector_fifo_pkg;
PACKAGE BODY image_selector_fifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END image_selector_fifo_pkg;
| bsd-2-clause | e2e0629ec7262e1981fce485afbe2941 | 0.507263 | 3.961525 | false | false | false | false |
RickvanLoo/Synthesizer | sawlut_entity.vhd | 1 | 2,319 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
ENTITY sawlut_entity IS
GENERIC(lut_bit_width : integer := 8;
DATA_width: integer := 16
);
PORT(
phase_in : in unsigned(lut_bit_width-1 downto 0);
a_clk : in std_logic;
reset : in std_logic;
DATA : OUT std_logic_vector(15 downto 0)
);
END sawlut_entity;
architecture behav of sawlut_entity is
--LUT
type sine_lut is array (0 to (2**lut_bit_width)-1) of integer;
constant sinedata:sine_lut:= (-7938,-7876,-7814,-7752,-7690,-7628,-7566,-7504,-7442,-7380,-7318,-7256,-7194,-7132,-7070,-7008,-6946,-6884,-6822,-6760,-6698,-6636,-6574,-6512,-6450,-6388,-6326,-6264,-6202,-6140,-6078,-6016,-5954,-5892,-5830,-5768,-5706,-5644,-5582,-5520,-5458,-5396,-5334,-5272,-5210,-5148,-5086,-5024,-4962,-4900,-4838,-4776,-4714,-4652,-4590,-4528,-4466,-4404,-4342,-4280,-4218,-4156,-4094,-4032,-3970,-3908,-3846,-3784,-3722,-3660,-3598,-3536,-3474,-3412,-3350,-3288,-3226,-3164,-3102,-3040,-2978,-2916,-2854,-2792,-2730,-2668,-2606,-2544,-2482,-2420,-2358,-2296,-2234,-2172,-2110,-2048,-1986,-1924,-1862,-1800,-1738,-1676,-1614,-1552,-1490,-1428,-1366,-1304,-1242,-1180,-1118,-1056,-994,-932,-870,-808,-746,-684,-622,-560,-498,-436,-374,-312,-250,-188,-126,-64,-2,60,122,184,246,308,370,432,494,556,618,680,742,804,866,928,990,1052,1114,1176,1238,1300,1362,1424,1486,1548,1610,1672,1734,1796,1858,1920,1982,2044,2106,2168,2230,2292,2354,2416,2478,2540,2602,2664,2726,2788,2850,2912,2974,3036,3098,3160,3222,3284,3346,3408,3470,3532,3594,3656,3718,3780,3842,3904,3966,4028,4090,4152,4214,4276,4338,4400,4462,4524,4586,4648,4710,4772,4834,4896,4958,5020,5082,5144,5206,5268,5330,5392,5454,5516,5578,5640,5702,5764,5826,5888,5950,6012,6074,6136,6198,6260,6322,6384,6446,6508,6570,6632,6694,6756,6818,6880,6942,7004,7066,7128,7190,7252,7314,7376,7438,7500,7562,7624,7686,7748,7810,7872);
signal sDATA : std_logic_vector(15 downto 0);
begin
process(a_clk,reset)
variable lutindex : integer range 0 to (2**lut_bit_width)-1 := 0;
begin
if reset = '0' then
DATA <= (others => '0');
lutindex := 0;
elsif rising_edge(a_clk) then
lutindex := to_integer(phase_in);
sDATA <= std_logic_vector(to_signed(sinedata(lutindex), DATA_width));
DATA <= sDATA;
end if;
end process;
end behav; | mit | d549412a5694a5741019e48d2a776184 | 0.684778 | 2.777246 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/source/vhdl/lloyds_algorithm_pkg.vhd | 1 | 8,236 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: lloyds_algorithm_pkg - Package
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
use ieee.math_real.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package lloyds_algorithm_pkg is
constant N_MAX : integer := 32768;
constant D : integer := 3;
constant K_MAX : integer := 256;
constant L_MAX : integer := 6;
constant PARALLEL_UNITS : integer := 1;
constant USE_DSP_FOR_ADD : boolean := false;
constant COORD_BITWIDTH : integer := 16;
constant COORD_BITWIDTH_EXT : integer := 32;
constant INDEX_BITWIDTH : integer := integer(ceil(log2(real(K_MAX))));
constant NODE_POINTER_BITWIDTH : integer := integer(ceil(log2(real(N_MAX))));
constant MUL_FRACTIONAL_BITS : integer := 6;
constant MUL_INTEGER_BITS : integer := 12;
constant MUL_BITWIDTH : integer := MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS;
constant MUL_CORE_LATENCY : integer := 3;
constant SYNTHESIS : boolean := false;
subtype coord_type is std_logic_vector(COORD_BITWIDTH-1 downto 0);
subtype centre_index_type is unsigned(INDEX_BITWIDTH-1 downto 0);
subtype node_index_type is unsigned(NODE_POINTER_BITWIDTH-1 downto 0);
subtype node_address_type is std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
type data_type is array(0 to D-1) of coord_type;
subtype coord_type_ext is std_logic_vector(COORD_BITWIDTH_EXT-1 downto 0);
type data_type_ext is array(0 to D-1) of coord_type_ext;
type node_data_type is
record
position : data_type;
end record;
-- size of node_data_type : D*COORD_BITWIDTH
-- array types for parallelism
type par_centre_index_type is array(0 to PARALLEL_UNITS-1) of centre_index_type;
type par_coord_type is array(0 to PARALLEL_UNITS-1) of coord_type;
type par_coord_type_ext is array(0 to PARALLEL_UNITS-1) of coord_type_ext;
type par_data_type is array(0 to PARALLEL_UNITS-1) of data_type;
type par_data_type_ext is array(0 to PARALLEL_UNITS-1) of data_type_ext;
type par_node_data_type is array(0 to PARALLEL_UNITS-1) of node_data_type;
-- helper functions
function stdlogic_2_datapoint(c : std_logic_vector) return data_type;
function stdlogic_2_datapoint_ext(c : std_logic_vector) return data_type_ext;
function datapoint_2_stdlogic(c : data_type) return std_logic_vector;
function datapoint_ext_2_stdlogic(c : data_type_ext) return std_logic_vector;
function nodedata_2_stdlogic(n : node_data_type) return std_logic_vector;
function stdlogic_2_nodedata(n : std_logic_vector) return node_data_type;
function saturate(val : std_logic_vector) return std_logic_vector;
function sext(val : std_logic_vector; length : integer) return std_logic_vector;
function zext(val : std_logic_vector; length : integer) return std_logic_vector;
function conv_ext_2_normal(val : data_type_ext) return data_type;
function conv_normal_2_ext(val : data_type) return data_type_ext;
end lloyds_algorithm_pkg;
package body lloyds_algorithm_pkg is
function datapoint_2_stdlogic(c : data_type) return std_logic_vector is
variable result : std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
begin
for I in 0 to D-1 loop
result((I+1)*COORD_BITWIDTH-1 downto I*COORD_BITWIDTH) := std_logic_vector(c(I));
end loop;
return result;
end datapoint_2_stdlogic;
function datapoint_ext_2_stdlogic(c : data_type_ext) return std_logic_vector is
variable result : std_logic_vector(D*COORD_BITWIDTH_EXT-1 downto 0);
begin
for I in 0 to D-1 loop
result((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT) := std_logic_vector(c(I));
end loop;
return result;
end datapoint_ext_2_stdlogic;
function stdlogic_2_datapoint(c : std_logic_vector) return data_type is
variable result : data_type;
begin
for I in 0 to D-1 loop
result(I) := c((I+1)*COORD_BITWIDTH-1 downto I*COORD_BITWIDTH);
end loop;
return result;
end stdlogic_2_datapoint;
function stdlogic_2_datapoint_ext(c : std_logic_vector) return data_type_ext is
variable result : data_type_ext;
begin
for I in 0 to D-1 loop
result(I) := c((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT);
end loop;
return result;
end stdlogic_2_datapoint_ext;
function nodedata_2_stdlogic(n : node_data_type) return std_logic_vector is
variable result : std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
begin
result := datapoint_2_stdlogic(n.position);
return result;
end nodedata_2_stdlogic;
function stdlogic_2_nodedata(n : std_logic_vector) return node_data_type is
variable result : node_data_type;
begin
result.position := stdlogic_2_datapoint(n);
return result;
end stdlogic_2_nodedata;
function saturate(val : std_logic_vector) return std_logic_vector is
variable val_msb : std_logic;
variable comp : std_logic_vector((val'length-MUL_INTEGER_BITS-MUL_FRACTIONAL_BITS)-1 downto 0);
variable result : std_logic_vector(MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS-1 downto 0);
begin
if MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS < val'length then
val_msb := val(val'length-1);
for I in (val'length-MUL_INTEGER_BITS-MUL_FRACTIONAL_BITS)-1 downto 0 loop
comp(I) := val_msb;
end loop;
if val(val'length-2 downto MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS-1) = comp then
result := val(MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS-1 downto 0);
else
result(MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS-1) := val_msb;
result(MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS-2 downto 0) := (others => NOT(val_msb));
end if;
else
result := sext(val,MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS);
end if;
return result;
end saturate;
function sext(val : std_logic_vector; length : integer) return std_logic_vector is
variable val_msb : std_logic;
variable result : std_logic_vector(length-1 downto 0);
begin
val_msb := val(val'length-1);
result(val'length-1 downto 0) := val;
result(length-1 downto val'length) := (others => val_msb);
return result;
end sext;
function zext(val : std_logic_vector; length : integer) return std_logic_vector is
variable result : std_logic_vector(length-1 downto 0);
begin
result(val'length-1 downto 0) := val;
result(length-1 downto val'length) := (others => '0');
return result;
end zext;
function conv_ext_2_normal(val : data_type_ext) return data_type is
variable result : data_type;
begin
for I in 0 to D-1 loop
result(I) := val(I)(COORD_BITWIDTH-1 downto 0);
end loop;
return result;
end conv_ext_2_normal;
function conv_normal_2_ext(val : data_type) return data_type_ext is
variable result : data_type_ext;
begin
for I in 0 to D-1 loop
result(I) := sext(val(I),COORD_BITWIDTH_EXT);
end loop;
return result;
end conv_normal_2_ext;
end package body;
| bsd-3-clause | 134cf0a00f63b6a2d258304b1db47db9 | 0.602598 | 3.903318 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/source/vhdl/lloyds_algorithm_top.vhd | 1 | 9,999 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: lloyds_algorithm_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.lloyds_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lloyds_algorithm_top is
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
-- initial parameters
n : in node_index_type;
k : in centre_index_type;
-- init node and centre memory
wr_init_node : in std_logic;
wr_node_address_init : in node_address_type;
wr_node_data_init : in node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
-- outputs
valid : out std_logic;
clusters_out : out data_type;
distortion_out : out coord_type_ext;
-- processing done
rdy : out std_logic
);
end lloyds_algorithm_top;
architecture Behavioral of lloyds_algorithm_top is
type state_type is (phase_1_init, processing, readout, phase_2_init, gap_state1, reset_core, gap_state2, phase_2_start, done);
constant DIVIDER_II : integer := 2;
component lloyds_algorithm_core
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
-- initial parameters
n : in node_index_type;
k : in centre_index_type;
-- init node and centre memory
wr_init_node : in std_logic;
wr_node_address_init : in node_address_type;
wr_node_data_init : in node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
-- access centre buffer
rdo_centre_buffer : in std_logic;
centre_buffer_addr : in centre_index_type;
valid : out std_logic;
wgtCent_out : out data_type_ext;
sum_sq_out : out coord_type_ext;
count_out : out coord_type;
-- processing done
rdy : out std_logic
);
end component;
component divider_top
generic (
ROUND : boolean := false
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
dividend : in data_type_ext;
divisor : in coord_type;
rdy : out std_logic;
quotient : out data_type;
divide_by_zero : out std_logic
);
end component;
-- control
signal state : state_type;
signal single_sclr : std_logic;
signal single_start : std_logic;
signal readout_counter : centre_index_type;
signal readout_counter_done : std_logic;
signal readout_centre_buffers : std_logic;
signal init_counter : centre_index_type;
signal init_counter_done : std_logic;
signal divider_ii_counter : unsigned(integer(ceil(log2(real(DIVIDER_II))))-1 downto 0);
signal divider_ii_counter_done : std_logic;
signal iterations_counter : unsigned(integer(ceil(log2(real(L_MAX))))-1 downto 0);
signal iterations_counter_done : std_logic;
-- core input signals
signal mux_wr_init_pos : std_logic;
signal mux_wr_centre_list_pos_address_init : centre_index_type;
signal mux_wr_centre_list_pos_data_init : data_type;
-- core output signals
signal tmp_valid : std_logic;
signal tmp_wgtCent_out : data_type_ext;
signal tmp_sum_sq_out : coord_type_ext;
signal tmp_count_out : coord_type;
signal tmp_rdy : std_logic;
-- divider and final output signals
signal divider_nd : std_logic;
signal divider_wgtCent_in : data_type_ext;
signal divider_count_in : coord_type;
signal comb_rdy : std_logic;
signal comb_valid : std_logic;
signal comb_sum_sq_out : coord_type_ext;
signal comb_new_position : data_type;
signal divide_by_zero : std_logic;
begin
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
state <= phase_1_init;
elsif state = phase_1_init AND start = '1' then
state <= processing;
elsif state = processing AND comb_rdy = '1' then
state <= readout;
elsif state = readout AND readout_counter_done = '1' then
state <= phase_2_init;
elsif state = phase_2_init AND init_counter_done = '1' then
state <= gap_state1; -- 1 cycle
elsif state = gap_state1 then
state <= reset_core; -- we hope that the initialised blockram will not be flushed by this!!!
elsif state = reset_core then
state <= gap_state2; -- 1 cycle
elsif state = gap_state2 then
state <= phase_2_start; -- 1 cycle
elsif state = phase_2_start then
state <= processing; -- 1 cycle
end if;
end if;
end process fsm_proc;
single_sclr <= '1' WHEN sclr = '1' OR state = reset_core ELSE '0';
single_start <= '1' WHEN start = '1' OR state = phase_2_start ELSE '0';
readout_centre_buffers <= '1' WHEN state = readout AND divider_ii_counter = 0 ELSE '0';
counter_proc : process(clk)
begin
if rising_edge(clk) then
if state = processing OR divider_ii_counter_done = '1' then
divider_ii_counter <= (others => '0');
elsif state = readout then
divider_ii_counter <= divider_ii_counter + 1;
end if;
if state = processing then
readout_counter <= (others => '0');
elsif state = readout AND divider_ii_counter_done = '1' then
readout_counter <= readout_counter+1;
end if;
if state = processing then
init_counter <= (others => '0');
elsif comb_valid = '1' then
init_counter <= init_counter+1;
end if;
if sclr = '1' then
iterations_counter <= (others => '0');
elsif init_counter_done = '1' AND comb_valid = '1' then
iterations_counter <= iterations_counter+1;
end if;
end if;
end process counter_proc;
readout_counter_done <= '1' WHEN readout_counter = k ELSE '0';
init_counter_done <= '1' WHEN init_counter = k ELSE '0';
divider_ii_counter_done <= '1' WHEN divider_ii_counter = to_unsigned(DIVIDER_II-1,integer(ceil(log2(real(DIVIDER_II))))) ELSE '0';
iterations_counter_done <= '1' WHEN iterations_counter = to_unsigned(L_MAX-1,integer(ceil(log2(real(L_MAX))))) ELSE '0';
mux_wr_init_pos <= wr_init_pos WHEN state = phase_1_init ELSE comb_valid AND NOT(divide_by_zero);
mux_wr_centre_list_pos_address_init <= wr_centre_list_pos_address_init WHEN state = phase_1_init ELSE init_counter;
mux_wr_centre_list_pos_data_init <= wr_centre_list_pos_data_init WHEN state = phase_1_init ELSE comb_new_position;
lloyds_algorithm_core_inst : lloyds_algorithm_core
port map (
clk => clk,
sclr => single_sclr,
start => single_start,
-- initial parameters
n => n,
k => k,
-- init node and centre memory
wr_init_node => wr_init_node,
wr_node_address_init => wr_node_address_init,
wr_node_data_init => wr_node_data_init,
wr_init_pos => mux_wr_init_pos,
wr_centre_list_pos_address_init => mux_wr_centre_list_pos_address_init,
wr_centre_list_pos_data_init => mux_wr_centre_list_pos_data_init,
-- access centre buffer
rdo_centre_buffer => readout_centre_buffers,
centre_buffer_addr => readout_counter,
valid => tmp_valid,
wgtCent_out => tmp_wgtCent_out,
sum_sq_out => tmp_sum_sq_out,
count_out => tmp_count_out,
-- processing done
rdy => tmp_rdy
);
comb_rdy <= tmp_rdy;
divider_nd <= tmp_valid;
divider_wgtCent_in <= tmp_wgtCent_out;
divider_count_in <= tmp_count_out;
comb_sum_sq_out <= tmp_sum_sq_out;
divider_top_inst : divider_top
generic map (
ROUND => false
)
port map (
clk => clk,
sclr => sclr,
nd => divider_nd,
dividend => divider_wgtCent_in,
divisor => divider_count_in,
rdy => comb_valid,
quotient => comb_new_position,
divide_by_zero => divide_by_zero
);
-- TODO: accumulate comb_sum_sq_out and use it as a dynamic convergence criterion
valid <= comb_valid;
clusters_out <= comb_new_position;
distortion_out <= comb_sum_sq_out;
rdy <= iterations_counter_done AND init_counter_done AND comb_valid;
end Behavioral;
| bsd-3-clause | 00223d936caaab7881afc85d59a25f85 | 0.546255 | 4.044903 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/pcores/ready4hood_v1_00_a/hdl/vhdl/md5_working.vhd | 2 | 14,437 | --library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
--entity MD5 is
-- Port( Clk : in std_logic;
-- Reset : in std_logic;
-- Run : in std_logic;
-- FirstRun : in std_logic;
-- w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15 : in std_logic_vector(31 downto 0);
-- Done : out std_logic;
-- Hash_1, Hash_2, Hash_3, Hash_4 : out std_logic_vector(31 downto 0));
--end MD5;
--
--architecture Behavioral of MD5 is
--
----Initial Constants for Words A, B, C, and D
--constant aa : std_logic_vector(31 downto 0) := x"67452301";
--constant bb : std_logic_vector(31 downto 0) := x"EFCDAB89";
--constant cc : std_logic_vector(31 downto 0) := x"98BADCFE";
--constant dd : std_logic_vector(31 downto 0) := x"10325476";
--
--subtype arr8 is STD_LOGIC_VECTOR (7 downto 0);
--subtype arr32 is STD_LOGIC_VECTOR (31 downto 0);
--
----R[64] is used to determine the amount of left rotation
--type Rarray is array (63 downto 0) of arr8;
--constant R : Rarray :=( x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06",
-- x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04",
-- x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05",
-- x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07");
--
--
----K[64] = floor(abs(sin(i)) * 2^32)
--type Karray is array (63 downto 0) of arr32;
--constant K : Karray :=( x"eb86d391", x"2ad7d2bb", x"bd3af235", x"f7537e82", x"4e0811a1", x"a3014314", x"fe2ce6e0", x"6fa87e4f", x"85845dd1",
-- x"ffeff47d", x"8f0ccc92", x"655b59c3", x"fc93a039", x"ab9423a7", x"432aff97", x"f4292244", x"c4ac5665", x"1fa27cf8",
-- x"e6db99e5", x"d9d4d039", x"04881d05", x"d4ef3085", x"eaa127fa", x"289b7ec6", x"bebfbc70", x"f6bb4b60", x"4bdecfa9",
-- x"a4beea44", x"fde5380c", x"6d9d6122", x"8771f681", x"fffa3942", x"8d2a4c8a", x"676f02d9", x"fcefa3f8", x"a9e3e905",
-- x"455a14ed", x"f4d50d87", x"c33707d6", x"21e1cde6", x"e7d3fbc8", x"d8a1e681", x"02441453", x"d62f105d", x"e9b6c7aa",
-- x"265e5a51", x"c040b340", x"f61e2562", x"49b40821", x"a679438e", x"fd987193", x"6b901122", x"895cd7be", x"ffff5bb1",
-- x"8b44f7af", x"698098d8", x"fd469501", x"a8304613", x"4787c62a", x"f57c0faf", x"c1bdceee", x"242070db", x"e8c7b756",
-- x"d76aa478");
--
--type Warray is array (15 downto 0) of arr32;
--signal W : Warray;
--signal a, b, c, d, f : std_logic_vector(31 downto 0);
--signal g : integer range 0 to 15;
--signal i : integer range 0 to 64;
--
--type ctrl_state is (Halt, Process_1, Process_2, Process_3, Process_4, Waiting, Finished);
--signal State, Next_state : ctrl_state;
--
--begin
-- Assign_Next_State : process (Clk, Reset)
-- begin
-- if (Reset = '1') then
-- State <= Halt;
-- elsif (rising_edge(clk)) then
-- State <= Next_State;
-- end if;
-- end process;
--
-- Get_Next_State : process (State, Run, FirstRun, i)
-- begin
-- case State is
-- when Halt =>
-- if (FirstRun = '0') then
-- Next_state <= Halt;
-- else
-- Next_state <= Process_1;
-- end if;
-- when Process_1 => --Each Process is one of the four stages in the MD5 Algorithm
-- if(i = 15) then
-- Next_state <= Process_2;
-- else
-- Next_state <= Process_1;
-- end if;
-- when Process_2 =>
-- if(i = 31) then
-- Next_state <= Process_3;
-- else
-- Next_state <= Process_2;
-- end if;
-- when Process_3 =>
-- if(i = 47) then
-- Next_state <= Process_4;
-- else
-- Next_state <= Process_3;
-- end if;
-- when Process_4 =>
-- if(i = 63) then
-- Next_state <= Finished;
-- else
-- Next_state <= Process_4;
-- end if;
-- when Finished =>
-- Next_state <= Waiting;
-- when Waiting =>
-- if (Run = '0') then
-- Next_state <= Waiting;
-- else
-- Next_state <= Process_1;
-- end if;
-- when others =>
-- Next_state <= Halt;
-- end case;
-- end process;
--
-- Control_States : process (state, a, b, c, d, i)
-- begin
-- Done <= '0';
-- Hash_1 <= x"00000000";
-- Hash_2 <= x"00000000";
-- Hash_3 <= x"00000000";
-- Hash_4 <= x"00000000";
--
-- f <= x"00000000";
-- g <= 0;
-- case State is
-- when Process_1 =>
-- f <= (b and c) or ((not b) and d);
-- g <= i;
-- when Process_2 =>
-- f <= (d and b) or ((not d) and c);
-- g <= (((5*i) + 1) mod 16);
-- when Process_3 =>
-- f <= b xor c xor d;
-- g <= ((3*i) + 5) mod 16;
-- when Process_4 =>
-- f <= c xor (b or (not d));
-- g <= (7*i) mod 16;
-- when Finished =>
-- Done <= '1';
-- Hash_1 <= aa + a;
-- Hash_2 <= bb + b;
-- Hash_3 <= cc + c;
-- Hash_4 <= dd + d;
-- when others =>
-- NULL;
-- end case;
-- end process;
-- Process_MD5 : process (state, a, b, c, d, i, W, clk)
-- begin
-- if (rising_edge(clk)) then
-- case State is
-- when Halt =>
-- i <= 0;
-- a <= aa;
-- b <= bb;
-- c <= cc;
-- d <= dd;
--
-- W(0) <= w0;
-- W(1) <= w1;
-- W(2) <= w2;
-- W(3) <= w3;
-- W(4) <= w4;
-- W(5) <= w5;
-- W(6) <= w6;
-- W(7) <= w7;
-- W(8) <= w8;
-- W(9) <= w9;
-- W(10) <= w10;
-- W(11) <= w11;
-- W(12) <= w12;
-- W(13) <= w13;
-- W(14) <= w14;
-- W(15) <= w15;
-- when Process_1 =>
-- d <= c;
-- c <= b;
-- --Shift Left OR'ed with the Equivalent Shift Right is the same as Left Rotation
-- b <= b + (SHL((a + f + K(i) + W(g)), R(i)) or SHR((a + f + K(i) + W(g)), ("00100000" - R(i))));
-- a <= d;
-- i <= i + 1;
-- when Process_2 =>
-- d <= c;
-- c <= b;
-- --Shift Left OR'ed with the Equivalent Shift Right is the same as Left Rotation
-- b <= b + (SHL((a + f + K(i) + W(g)), R(i)) or SHR((a + f + K(i) + W(g)), ("00100000" - R(i))));
-- a <= d;
-- i <= i + 1;
-- when Process_3 =>
-- d <= c;
-- c <= b;
-- b <= b + (SHL((a + f + K(i) + W(g)), R(i)) or SHR((a + f + K(i) + W(g)), ("00100000" - R(i))));
-- a <= d;
-- i <= i + 1;
-- when Process_4 =>
-- d <= c;
-- c <= b;
-- b <= b + (SHL((a + f + K(i) + W(g)), R(i)) or SHR((a + f + K(i) + W(g)), ("00100000" - R(i))));
-- a <= d;
-- i <= i + 1;
-- when Waiting =>
-- i <= 0;
-- a <= aa;
-- b <= bb;
-- c <= cc;
-- d <= dd;
--
-- W(0) <= w0;
-- W(1) <= w1;
-- W(2) <= w2;
-- W(3) <= w3;
-- W(4) <= w4;
-- W(5) <= w5;
-- W(6) <= w6;
-- W(7) <= w7;
-- W(8) <= w8;
-- W(9) <= w9;
-- W(10) <= w10;
-- W(11) <= w11;
-- W(12) <= w12;
-- W(13) <= w13;
-- W(14) <= w14;
-- W(15) <= w15;
-- when others =>
-- NULL;
-- end case;
-- end if;
-- end process;
--end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--use ieee.numeric_bit.all;
entity MD5 is
port (
clk : in std_logic;
rstn : in std_logic;
i_start : in std_logic;
--i_data : in unsigned(71 downto 0); -- 8 chars + 1 appended bit
i_data_0 : in unsigned(31 downto 0); -- first 4 chars
i_data_1 : in unsigned(31 downto 0); -- next 4 chars
i_length : in std_logic_vector(7 downto 0); -- nbr of chars
o_done : out std_logic;
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end MD5;
architecture Behavioral of MD5 is
-- the initialization values of the loop variables --
constant a_init : unsigned(31 downto 0) := x"67452301";
constant b_init : unsigned(31 downto 0) := x"EFCDAB89";
constant c_init : unsigned(31 downto 0) := x"98BADCFE";
constant d_init : unsigned(31 downto 0) := x"10325476";
-- the array with the init values --
type w_array is array(15 downto 0) of unsigned(31 downto 0);
signal w : w_array; --w_n
-- loop signals --
signal a_c, a_n, b_c, b_n, c_c, c_n, d_c, d_n, f : unsigned(31 downto 0);
signal i_c, i_n : integer range 0 to 63;
signal g : integer range 0 to 15;
-- the states for the main loop --
type state is (stage_1, stage_2, stage_3, stage_4, waiting, finished, set_output);
signal state_c, state_n : state;
-- Specifies the amount to shift in the main loop, use rotate_left() --
type s_array is array(63 downto 0) of unsigned(7 downto 0);
constant s : s_array :=( x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06",
x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04",
x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05",
x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07");
-- 15 0f 0a 06 17 10 0b 04 14 0e 09 05 16 11 0c 07
-- fixed amount to add during the rotation --
type k_array is array(63 downto 0) of unsigned(31 downto 0);
constant k : k_array :=( x"eb86d391", x"2ad7d2bb", x"bd3af235", x"f7537e82", x"4e0811a1", x"a3014314", x"fe2ce6e0", x"6fa87e4f", x"85845dd1",
x"ffeff47d", x"8f0ccc92", x"655b59c3", x"fc93a039", x"ab9423a7", x"432aff97", x"f4292244", x"c4ac5665", x"1fa27cf8",
x"e6db99e5", x"d9d4d039", x"04881d05", x"d4ef3085", x"eaa127fa", x"289b7ec6", x"bebfbc70", x"f6bb4b60", x"4bdecfa9",
x"a4beea44", x"fde5380c", x"6d9d6122", x"8771f681", x"fffa3942", x"8d2a4c8a", x"676f02d9", x"fcefa3f8", x"a9e3e905",
x"455a14ed", x"f4d50d87", x"c33707d6", x"21e1cde6", x"e7d3fbc8", x"d8a1e681", x"02441453", x"d62f105d", x"e9b6c7aa",
x"265e5a51", x"c040b340", x"f61e2562", x"49b40821", x"a679438e", x"fd987193", x"6b901122", x"895cd7be", x"ffff5bb1",
x"8b44f7af", x"698098d8", x"fd469501", x"a8304613", x"4787c62a", x"f57c0faf", x"c1bdceee", x"242070db", x"e8c7b756",
x"d76aa478");
-- begin the Behavioral --
begin
-- the clock process --
clk_proc: process(clk)
begin
if rising_edge(clk) then
if rstn = '0' then
state_c <= waiting;
-- reset the main loop signals --
i_c <= 0;
a_c <= a_init;
b_c <= b_init;
c_c <= c_init;
d_c <= d_init;
else
state_c <= state_n;
i_c <= i_n;
a_c <= a_n;
b_c <= b_n;
c_c <= c_n;
d_c <= d_n;
end if;
end if;
end process;
-- the state control --
FSM: process(state_c, i_start, i_c)
begin
-- defaults --
state_n <= state_c;
case state_c is
when waiting =>
if i_start = '0' then
state_n <= waiting;
else
state_n <= stage_1;
end if;
when stage_1 =>
if i_c = 15 then -- state change depending on the counter
state_n <= stage_2;
else
state_n <= stage_1;
end if;
when stage_2 =>
if i_c = 31 then
state_n <= stage_3;
else
state_n <= stage_2;
end if;
when stage_3 =>
if i_c = 47 then
state_n <= stage_4;
else
state_n <= stage_3;
end if;
when stage_4 =>
if i_c = 63 then
state_n <= finished;
else
state_n <= stage_4;
end if;
when finished =>
state_n <= waiting;
when others =>
null;
end case;
end process;
-- set the outputs and update f & g --
data_path: process(a_c, b_c, c_c, d_c, f, g, i_c, w, state_c, i_data_0, i_data_1, i_length)
begin
-- set standard values --
o_done <= '0';
o_hash_0 <= (others => '0');
o_hash_1 <= (others => '0');
o_hash_2 <= (others => '0');
o_hash_3 <= (others => '0');
f <= (others => '0');
g <= 0;
-- set init vector-data values --
w(0) <= i_data_0;
w(1) <= i_data_1;
w(2) <= (others => '0');
w(3) <= (others => '0');
w(4) <= (others => '0');
w(5) <= (others => '0');
w(6) <= (others => '0');
w(7) <= (others => '0');
w(8) <= (others => '0');
w(9) <= (others => '0');
w(10) <= (others => '0');
w(11) <= (others => '0');
w(12) <= (others => '0');
w(13) <= (others => '0');
w(14) <= unsigned(x"000000" & i_length);
w(15) <= (others => '0');
-- main loop signals calc set as standard values --
d_n <= c_c;
c_n <= b_c;
b_n <= b_c + rotate_left(a_c + k(i_c) + w(g) + f, to_integer(s(i_c)));
a_n <= d_c;
if i_c < 63 then
i_n <= i_c + 1;
else
i_n <= i_c;
end if;
case state_c is
when waiting =>
i_n <= 0;
a_n <= a_init;
b_n <= b_init;
c_n <= c_init;
d_n <= d_init;
when stage_1 =>
f <= (b_c and c_c) or ((not b_c) and d_c);
g <= i_c;-- mod 16; CHECK THIS!!
when stage_2 =>
f <= (d_c and b_c) or ((not d_c) and c_c);
g <= ((5 * i_c) + 1) mod 16;
when stage_3 =>
f <= b_c xor c_c xor d_c;
g <= ((3 * i_c) + 5) mod 16;
when stage_4 =>
f <= c_c xor (b_c or (not d_c));
g <= (7 * i_c) mod 16;
when finished =>
o_done <= '1';
o_hash_0 <= (a_init + a_c);
o_hash_1 <= (b_init + b_c);
o_hash_2 <= (c_init + c_c);
o_hash_3 <= (d_init + d_c);
when others => null;
end case;
end process;
end Behavioral;
| mit | cc02a12503cf840037636869d6bf9e0f | 0.471012 | 2.444049 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/pcores/brutus_v1_00_a/hdl/vhdl/brutus.vhd | 1 | 6,522 | ------------------------------------------------------------------------------
-- brutus - entity/architecture pair
------------------------------------------------------------------------------
--
-- Filename: brutus
-- Version: 1.00.a
-- Description: Example FSL core (VHDL).
-- Date: Fri Sep 19 16:14:59 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity brutus is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
attribute SIGIS of FSL_S_Clk : signal is "Clk";
attribute SIGIS of FSL_M_Clk : signal is "Clk";
end brutus;
architecture Behavioral of brutus is
type states is (idle, read_charset, read_hash, write_outputs);
signal state_c, state_n : states;
signal r_count_c, r_count_n : unsigned(1 downto 0); -- read hash counter, 4 pieces
signal w_count_c, w_count_n : unsigned(0 downto 0); -- write hash counter, 2 pieces
signal hash_c, hash_n : std_logic_vector(31 downto 0);
signal password_c, password_n : unsigned(31 downto 0);
begin
-- CAUTION:
-- The sequence in which data are read in and written out should be
-- consistent with the sequence they are written and read in the
-- driver's brutus.c file
FSL_S_Read <= FSL_S_Exists when state_c = read_hash else '0'; -- DONT FORGET TO ADD OTHER STATES HERE IF NECESSARY
FSL_M_Write <= not FSL_M_Full when state_c = write_outputs else '0';
FSL_M_Data <= std_logic_vector(password_c);
clk_proc : process (FSL_Clk) is
begin -- process The_SW_accelerator
if rising_edge(FSL_Clk) then -- Rising clock edge
if FSL_Rst = '1' then -- Synchronous reset (active high)
state_c <= idle;
r_count_c <= (others => '0');
w_count_c <= (others => '0');
password_c <= (others => '0');
hash_c <= (others => '0');
else
state_c <= state_n;
r_count_c <= r_count_n;
w_count_c <= w_count_n;
password_c <= password_n;
hash_c <= hash_n;
end if;
end if;
end process;
fsm_proc: process(state_c, r_count_c, w_count_c, FSL_S_Exists, FSL_S_Data, FSL_M_Full, hash_c, password_c) is
begin
-- defaults --
r_count_n <= r_count_c;
w_count_n <= w_count_c;
state_n <= state_c;
password_n <= password_c;
hash_n <= hash_c;
case state_c is
when idle =>
if (FSL_S_Exists = '1') then
state_n <= read_hash; --read_charset; -- which characters to include
end if;
-- when read_charset =>
-- if FSL_S_Exists = '1' then
-- state_n <= read_hash;
-- end if;
when read_hash =>
if (FSL_S_Exists = '1') then
if FSL_S_Data = x"12345678" then
hash_n(31 downto 0) <= x"12345678"; --FSL_S_Data;
end if;
state_n <= write_outputs;
-- r_count_n <= r_count_c + 1;
--
--
-- if r_count_c = 0 then
-- hash_n(127 downto 96) <= FSL_S_Data;
-- elsif r_count_c = 1 then
-- hash_n(95 downto 64) <= FSL_S_Data;
-- elsif r_count_c = 2 then
-- hash_n(63 downto 32) <= FSL_S_Data;
-- else
-- hash_n(31 downto 0) <= FSL_S_Data;
-- end if;
--
-- if r_count_c = 3 then
-- r_count_n <= (others => '0');
-- state_n <= write_outputs;
-- end if;
end if;
when write_outputs =>
if (w_count_c = 1) then
state_n <= idle;
w_count_n <= (others => '0');
elsif (FSL_M_Full = '0') then
w_count_n <= w_count_c + 1;
password_n <= password_c + 5;
end if;
when others =>
null;
end case;
end process;
end architecture Behavioral; | mit | 98f48571ac4785fa10202c3b85ed265b | 0.493407 | 3.664045 | false | false | false | false |
RickvanLoo/Synthesizer | sinelut_entity.vhd | 1 | 2,331 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
ENTITY sinelut_entity IS
GENERIC(lut_bit_width : integer := 8;
DATA_width: integer := 16
);
PORT(
phase_in : in unsigned(lut_bit_width-1 downto 0);
a_clk : in std_logic;
reset : in std_logic;
DATA : OUT std_logic_vector(15 downto 0)
);
END sinelut_entity;
architecture behav of sinelut_entity is
--LUT
type sine_lut is array (0 to (2**lut_bit_width)-1) of integer;
constant sinedata:sine_lut:= (0,196,393,589,784,979,1174,1368,1561,1753,1944,2134,2322,2509,2695,2879,3061,3242,3420,3597,3771,3943,4113,4280,4445,4606,4766,4922,5075,5225,5372,5516,5657,5794,5928,6058,6184,6307,6426,6541,6652,6759,6862,6961,7055,7146,7232,7314,7391,7464,7532,7596,7656,7710,7760,7806,7846,7882,7913,7940,7961,7978,7990,7998,8000,7998,7990,7978,7961,7940,7913,7882,7846,7806,7760,7710,7656,7596,7532,7464,7391,7314,7232,7146,7055,6961,6862,6759,6652,6541,6426,6307,6184,6058,5928,5794,5657,5516,5372,5225,5075,4922,4766,4606,4445,4280,4113,3943,3771,3597,3420,3242,3061,2879,2695,2509,2322,2134,1944,1753,1561,1368,1174,979,784,589,393,196,0,-196,-393,-589,-784,-979,-1174,-1368,-1561,-1753,-1944,-2134,-2322,-2509,-2695,-2879,-3061,-3242,-3420,-3597,-3771,-3943,-4113,-4280,-4445,-4606,-4766,-4922,-5075,-5225,-5372,-5516,-5657,-5794,-5928,-6058,-6184,-6307,-6426,-6541,-6652,-6759,-6862,-6961,-7055,-7146,-7232,-7314,-7391,-7464,-7532,-7596,-7656,-7710,-7760,-7806,-7846,-7882,-7913,-7940,-7961,-7978,-7990,-7998,-8000,-7998,-7990,-7978,-7961,-7940,-7913,-7882,-7846,-7806,-7760,-7710,-7656,-7596,-7532,-7464,-7391,-7314,-7232,-7146,-7055,-6961,-6862,-6759,-6652,-6541,-6426,-6307,-6184,-6058,-5928,-5794,-5657,-5516,-5372,-5225,-5075,-4922,-4766,-4606,-4445,-4280,-4113,-3943,-3771,-3597,-3420,-3242,-3061,-2879,-2695,-2509,-2322,-2134,-1944,-1753,-1561,-1368,-1174,-979,-784,-589,-393,-196);
signal sDATA : std_logic_vector(15 downto 0);
begin
process(a_clk,reset)
variable lutindex : integer range 0 to (2**lut_bit_width)-1 := 0;
begin
if reset = '0' then
DATA <= (others => '0');
lutindex := 0;
elsif rising_edge(a_clk) then
lutindex := to_integer(phase_in);
sDATA <= std_logic_vector(to_signed(sinedata(lutindex), DATA_width));
DATA <= sDATA;
end if;
end process;
end behav; | mit | ea22f8da9687e56851aed25f2ddc4be2 | 0.687259 | 2.808434 | false | false | false | false |
alonho/game_of_life_vhdl | cell.vhdl | 2 | 677 | entity cell is
generic (
start_alive : integer range 0 to 1 := 0
);
port (
clock, left, right,
upper_left, upper, upper_right,
lower_left, lower, lower_right : in integer range 0 to 1;
alive : inout integer range 0 to 1 := start_alive
);
end cell;
architecture arch of cell is
begin
process (clock)
variable neighbors: integer range 0 to 8;
begin
neighbors := upper_left + upper + upper_right + left +
right + lower_left + lower + lower_right;
if (neighbors = 3) or (alive = 1 and (neighbors) = 2) then
alive <= 1;
else
alive <= 0;
end if;
end process;
end arch;
| bsd-3-clause | 56a4861ecdce516331418df22ca046ac | 0.580502 | 3.659459 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/pcores/bajsd_v1_00_a - Copy/hdl/vhdl/tb_md5.vhd | 1 | 2,846 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:12:46 09/15/2014
-- Design Name:
-- Module Name: H:/Documents/md5_test/tb_md5.vhd
-- Project Name: md5_test
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MD5
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_md5 IS
END tb_md5;
ARCHITECTURE behavior OF tb_md5 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MD5
PORT(
i_clk : IN std_logic;
i_rst_n : IN std_logic;
i_start : IN std_logic;
i_data : IN unsigned(71 downto 0);
o_done : OUT std_logic;
o_hash_0 : OUT unsigned(31 downto 0);
o_hash_1 : OUT unsigned(31 downto 0);
o_hash_2 : OUT unsigned(31 downto 0);
o_hash_3 : OUT unsigned(31 downto 0)
);
END COMPONENT;
--Inputs
signal i_clk : std_logic := '0';
signal i_rst_n : std_logic := '1';
signal i_start : std_logic := '0';
signal i_data : unsigned(71 downto 0) := (others => '0');
--Outputs
signal o_done : std_logic;
signal o_hash_0, o_hash_1, o_hash_2, o_hash_3 : unsigned(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MD5 PORT MAP (
i_clk => i_clk,
i_rst_n => i_rst_n,
i_start => i_start,
i_data => i_data,
o_done => o_done,
o_hash_0 => o_hash_0,
o_hash_1 => o_hash_1,
o_hash_2 => o_hash_2,
o_hash_3 => o_hash_3
);
-- Clock process definitions
clk_process :process
begin
i_clk <= '0';
wait for clk_period/2;
i_clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2;
i_rst_n <= '0';
wait for clk_period;
i_rst_n <= '1';
i_start <= '1';
i_data <= x"626161616161616180";
--i_data <= (others => '1');
wait for clk_period;
-- insert stimulus here
wait;
end process;
END;
| mit | 7e717c6d212f3b1b0a3d637a7ef68732 | 0.567112 | 3.348235 | false | true | false | false |
Nooxet/embedded_bruteforce | brutus_system/pcores/bajsd_v1_00_a - Copy/hdl/vhdl/tb_string_generator.vhd | 1 | 2,528 | --------------------------------------------------------------------------------
-- Engineer: Nox
--
-- Module Name: /home/noxet/vhdl/string_generator/tb_string_generator.vhd
-- Description:
-- A testbench for the string_generator module
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_string_generator IS
END tb_string_generator;
ARCHITECTURE behavior OF tb_string_generator IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT string_generator
PORT(
clk : IN std_logic;
rstn : IN std_logic;
i_start : IN std_logic;
i_halt : IN std_logic;
o_done : OUT std_logic;
o_string : OUT std_logic_vector(47 downto 0);
o_length : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rstn : std_logic := '0';
signal i_start : std_logic := '0';
signal i_halt : std_logic := '0';
--Outputs
signal o_done : std_logic;
signal o_length : std_logic_vector(2 downto 0);
signal o_string : std_logic_vector(47 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: string_generator PORT MAP (
clk => clk,
rstn => rstn,
i_start => i_start,
i_halt => i_halt,
o_done => o_done,
o_string => o_string,
o_length => o_length
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
rstn <= '1';
wait for clk_period*10;
i_start <= '1';
wait for clk_period;
i_start <= '0';
wait for 10*clk_period;
i_halt <= '1';
wait for 5*clk_period;
i_halt <= '0';
assert o_string = x"00000000006A" report "FAIL HALT, 'j'"; -- 10th letter = j
wait for 16*clk_period;
i_halt <= '1';
wait for 1*clk_period;
i_halt <= '0';
assert o_string = x"00000000007A" report "FAIL HALT, 'z'"; -- last letter = z
wait for 2*clk_period;
assert o_string = x"000000006161" report "FAIL OUTPUT, 'aa'";
assert o_length = "010" report "FAIL LENGTH, 2";
wait until o_done = '1';
wait;
end process;
END;
| mit | 5dd575b44e6694f4d91fcb74648b2a8a | 0.546677 | 3.550562 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/bytefifoFPGA/example_design/bytefifoFPGA_exdes.vhd | 3 | 5,893 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifoFPGA_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity bytefifoFPGA_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
UNDERFLOW : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end bytefifoFPGA_exdes;
architecture xilinx of bytefifoFPGA_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component bytefifoFPGA is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
UNDERFLOW : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : bytefifoFPGA
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
OVERFLOW => overflow,
UNDERFLOW => underflow,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| bsd-2-clause | 2677c8b80b72e6bc4a2454e3c890cb64 | 0.501103 | 4.968803 | false | false | false | false |
freecores/gpib_controller | vhdl/test/Fifo8b_Test.vhd | 1 | 4,177 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Author: Andrzej Paluch
-- Fifo8b test
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use ieee.std_logic_arith.all;
use work.helperComponents.all;
ENTITY Fifo8b_Test_vhd IS
END Fifo8b_Test_vhd;
ARCHITECTURE behavior OF Fifo8b_Test_vhd IS
constant clk_period : time := 1us;
SIGNAL reset : std_logic := '0';
SIGNAL clk : std_logic := '0';
-------------- fifo --------------------
SIGNAL bytesAvailable : std_logic;
SIGNAL availableBytesCount : std_logic_vector(10 downto 0);
SIGNAL bufferFull : std_logic;
SIGNAL resetFifo : std_logic := '0';
----------------------------------------
SIGNAL data_in : std_logic_vector(7 downto 0) := (others => '0');
SIGNAL ready_to_write : std_logic;
SIGNAL strobe_write : std_logic := '0';
----------------------------------------
SIGNAL data_out : std_logic_vector(7 downto 0);
SIGNAL ready_to_read : std_logic;
SIGNAL strobe_read : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
fifo: Fifo8b port map (
reset => reset,
clk => clk,
-------------- fifo --------------------
bytesAvailable => bytesAvailable,
availableBytesCount => availableBytesCount,
bufferFull => bufferFull,
resetFifo => resetFifo,
----------------------------------------
data_in => data_in,
ready_to_write => ready_to_write,
strobe_write => strobe_write,
----------------------------------------
data_out => data_out,
ready_to_read => ready_to_read,
strobe_read => strobe_read
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: PROCESS
BEGIN
reset <= '1';
wait for clk_period*4;
reset <= '0';
wait for clk_period*4;
data_in <= "00000010";
wait for clk_period;
strobe_write <= '1';
wait for clk_period;
strobe_write <= '0';
wait for clk_period*4;
data_in <= "00000011";
wait for clk_period;
strobe_write <= '1';
wait for clk_period;
strobe_write <= '0';
wait for clk_period*4;
strobe_read <= '1';
wait for clk_period;
strobe_read <= '0';
wait for clk_period*4;
strobe_read <= '1';
wait for clk_period;
strobe_read <= '0';
wait for clk_period*4;
data_in <= "00000100";
wait for clk_period;
strobe_write <= '1';
wait for clk_period;
strobe_write <= '0';
wait for clk_period*4;
strobe_read <= '1';
wait for clk_period;
strobe_read <= '0';
-- for i in 0 to 2**11-1 loop
-- data_in <= conv_std_logic_vector(i, 8);
-- wait for clk_period;
-- strobe_write <= '1';
-- wait until ready_to_write = '0';
-- strobe_write <= '0';
-- if i < 2**11-1 then
-- wait until ready_to_write = '1';
-- end if;
-- end loop;
--
-- wait for clk_period;
--
-- strobe_read <= '1';
-- wait for clk_period;
-- strobe_read <= '0';
--
-- wait for clk_period*3;
--
-- for i in 0 to 1 loop
-- data_in <= conv_std_logic_vector(i, 8);
-- wait for clk_period;
-- strobe_write <= '1';
-- wait until ready_to_write = '0';
-- strobe_write <= '0';
-- wait until ready_to_write = '1';
-- end loop;
wait; -- will wait forever
END PROCESS;
END;
| gpl-3.0 | 20e7db2f12ebe62df502748d373bea18 | 0.571223 | 3.243012 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/system_leds_8bits_wrapper.vhd | 1 | 4,995 | -------------------------------------------------------------------------------
-- system_leds_8bits_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_gpio_v1_01_b;
use axi_gpio_v1_01_b.all;
entity system_leds_8bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(7 downto 0);
GPIO_IO_O : out std_logic_vector(7 downto 0);
GPIO_IO_T : out std_logic_vector(7 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_leds_8bits_wrapper : entity is "axi_gpio_v1_01_b";
end system_leds_8bits_wrapper;
architecture STRUCTURE of system_leds_8bits_wrapper is
component axi_gpio is
generic (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : std_logic_vector(31 downto 0);
C_TRI_DEFAULT : std_logic_vector(31 downto 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : std_logic_vector(31 downto 0);
C_TRI_DEFAULT_2 : std_logic_vector(31 downto 0)
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_O : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_T : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO2_IO_I : in std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_O : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_T : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0)
);
end component;
begin
LEDs_8Bits : axi_gpio
generic map (
C_FAMILY => "spartan6",
C_INSTANCE => "LEDs_8Bits",
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"ffffffff",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"ffffffff"
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
IP2INTC_Irpt => IP2INTC_Irpt,
GPIO_IO_I => GPIO_IO_I,
GPIO_IO_O => GPIO_IO_O,
GPIO_IO_T => GPIO_IO_T,
GPIO2_IO_I => GPIO2_IO_I,
GPIO2_IO_O => GPIO2_IO_O,
GPIO2_IO_T => GPIO2_IO_T
);
end architecture STRUCTURE;
| mit | 02db62e34750c7961e03fb00497e9f7e | 0.585786 | 2.919345 | false | false | false | false |
freecores/gpib_controller | vhdl/src/wrapper/EventReg.vhd | 1 | 4,108 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: EventReg
-- Date:2011-11-11
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.helperComponents.all;
entity EventReg is
port (
reset : in std_logic;
clk : in std_logic;
strobe : in std_logic;
data_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
-------------------- gpib device ---------------------
-- device is local controlled
isLocal : in std_logic;
-- input buffer ready
in_buf_ready : in std_logic;
-- output buffer ready
out_buf_ready : in std_logic;
-- clear device (DC)
clr : in std_logic;
-- trigger device (DT)
trg : in std_logic;
-- addressed to talk(L or LE)
att : in std_logic;
-- addressed to listen (T or TE)
atl : in std_logic;
-- seriall poll active
spa : in std_logic;
-------------------- gpib controller ---------------------
-- controller write commands
cwrc : in std_logic;
-- controller write data
cwrd : in std_logic;
-- service requested
srq : in std_logic;
-- parallel poll ready
ppr : in std_logic;
-- stb received
stb_received : in std_logic;
REN : in std_logic;
ATN : in std_logic;
IFC : in std_logic
);
end EventReg;
architecture arch of EventReg is
signal i_clr : std_logic;
signal i_trg : std_logic;
signal i_srq : std_logic;
signal clr_app : std_logic;
signal trg_app : std_logic;
signal srq_app : std_logic;
signal t_clr_in, t_clr_out : std_logic;
signal t_trg_in, t_trg_out : std_logic;
signal t_srq_in, t_srq_out : std_logic;
begin
data_out(0) <= isLocal;
data_out(1) <= in_buf_ready;
data_out(2) <= out_buf_ready;
data_out(3) <= i_clr;
data_out(4) <= i_trg;
data_out(5) <= att;
data_out(6) <= atl;
data_out(7) <= spa;
data_out(8) <= cwrc;
data_out(9) <= cwrd;
data_out(10) <= i_srq;
data_out(11) <= ppr;
data_out(12) <= stb_received;
data_out(13) <= REN;
data_out(14) <= ATN;
data_out(15) <= IFC;
process (reset, strobe) begin
if reset = '1' then
t_clr_in <= '0';
t_trg_in <= '0';
t_srq_in <= '0';
elsif rising_edge(strobe) then
if data_in(3) = '0' then
t_clr_in <= not t_clr_out;
elsif data_in(4) = '0' then
t_trg_in <= not t_trg_out;
elsif data_in(10) = '0' then
t_srq_in <= not t_srq_out;
end if;
end if;
end process;
EVM1: EventMem port map (
reset => reset, occured => clr, approved => clr_app,
output => i_clr
);
SPG1: SinglePulseGenerator generic map (WIDTH => 1) port map(
reset => reset, clk => clk,
t_in => t_clr_in, t_out => t_clr_out,
pulse => clr_app
);
EVM2: EventMem port map (
reset => reset, occured => trg, approved => trg_app,
output => i_trg
);
SPG2: SinglePulseGenerator generic map (WIDTH => 1) port map(
reset => reset, clk => clk,
t_in => t_trg_in, t_out => t_trg_out,
pulse => trg_app
);
EVM3: EventMem port map (
reset => reset, occured => srq, approved => srq_app,
output => i_srq
);
SPG3: SinglePulseGenerator generic map (WIDTH => 1) port map(
reset => reset, clk => clk,
t_in => t_srq_in, t_out => t_srq_out,
pulse => srq_app
);
end arch;
| gpl-3.0 | 3927c38be8976148a7385fa7d10e2bfd | 0.592746 | 3.01394 | false | false | false | false |
mithro/HDMI2USB | hdl/jpeg_encoder/design/FDCT.vhd | 3 | 24,409 | -------------------------------------------------------------------------------
-- File Name : FDCT.vhd
--
-- Project : JPEG_ENC
--
-- Module : FDCT
--
-- Content : FDCT
--
-- Description : 2D Discrete Cosine Transform
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity FDCT is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
start_pb : in std_logic;
ready_pb : out std_logic;
fdct_sm_settings : in T_SM_SETTINGS;
-- BUF_FIFO
bf_fifo_rd : out std_logic;
bf_fifo_q : in std_logic_vector(23 downto 0);
bf_fifo_hf_full : in std_logic;
-- ZIG ZAG
zz_buf_sel : in std_logic;
zz_rd_addr : in std_logic_vector(5 downto 0);
zz_data : out std_logic_vector(11 downto 0);
zz_rden : in std_logic;
-- HOST
img_size_x : in std_logic_vector(15 downto 0);
img_size_y : in std_logic_vector(15 downto 0);
sof : in std_logic
);
end entity FDCT;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of FDCT is
constant C_Y_1 : signed(14 downto 0) := to_signed(4899, 15);
constant C_Y_2 : signed(14 downto 0) := to_signed(9617, 15);
constant C_Y_3 : signed(14 downto 0) := to_signed(1868, 15);
constant C_Cb_1 : signed(14 downto 0) := to_signed(-2764, 15);
constant C_Cb_2 : signed(14 downto 0) := to_signed(-5428, 15);
constant C_Cb_3 : signed(14 downto 0) := to_signed(8192, 15);
constant C_Cr_1 : signed(14 downto 0) := to_signed(8192, 15);
constant C_Cr_2 : signed(14 downto 0) := to_signed(-6860, 15);
constant C_Cr_3 : signed(14 downto 0) := to_signed(-1332, 15);
signal mdct_data_in : std_logic_vector(7 downto 0):=(others=>'0');
signal mdct_idval : std_logic:='0';
signal mdct_odval : std_logic:='0';
signal mdct_data_out : std_logic_vector(11 downto 0):=(others=>'0');
signal odv1 : std_logic:='0';
signal dcto1 : std_logic_vector(11 downto 0):=(others=>'0');
signal x_pixel_cnt : unsigned(15 downto 0):=(others=>'0');
signal y_line_cnt : unsigned(15 downto 0):=(others=>'0');
signal rd_addr : std_logic_vector(31 downto 0):=(others=>'0');
signal input_rd_cnt : unsigned(6 downto 0):=(others=>'0');
signal rd_en : std_logic:='0';
signal rd_en_d1 : std_logic:='0';
signal rdaddr : unsigned(31 downto 0):=(others=>'0');
signal bf_dval : std_logic:='0';
signal bf_dval_m1 : std_logic:='0';
signal bf_dval_m2 : std_logic:='0';
signal bf_dval_m3 : std_logic:='0';
signal wr_cnt : unsigned(5 downto 0):=(others=>'0');
signal dbuf_data : std_logic_vector(11 downto 0):=(others=>'0');
signal dbuf_q : std_logic_vector(11 downto 0):=(others=>'0');
signal dbuf_we : std_logic:='0';
signal dbuf_waddr : std_logic_vector(6 downto 0):=(others=>'0');
signal dbuf_raddr : std_logic_vector(6 downto 0):=(others=>'0');
signal xw_cnt : unsigned(2 downto 0):=(others=>'0');
signal yw_cnt : unsigned(2 downto 0):=(others=>'0');
signal dbuf_q_z1 : std_logic_vector(11 downto 0):=(others=>'0');
constant C_SIMA_ASZ : integer := 9;
signal sim_rd_addr : unsigned(C_SIMA_ASZ-1 downto 0):=(others=>'0');
signal Y_reg_1 : signed(23 downto 0):=(others=>'0');
signal Y_reg_2 : signed(23 downto 0):=(others=>'0');
signal Y_reg_3 : signed(23 downto 0):=(others=>'0');
signal Cb_reg_1 : signed(23 downto 0):=(others=>'0');
signal Cb_reg_2 : signed(23 downto 0):=(others=>'0');
signal Cb_reg_3 : signed(23 downto 0):=(others=>'0');
signal Cr_reg_1 : signed(23 downto 0):=(others=>'0');
signal Cr_reg_2 : signed(23 downto 0):=(others=>'0');
signal Cr_reg_3 : signed(23 downto 0):=(others=>'0');
signal Y_reg : signed(23 downto 0):=(others=>'0');
signal Cb_reg : signed(23 downto 0):=(others=>'0');
signal Cr_reg : signed(23 downto 0):=(others=>'0');
signal R_s : signed(8 downto 0):=(others=>'0');
signal G_s : signed(8 downto 0):=(others=>'0');
signal B_s : signed(8 downto 0):=(others=>'0');
signal Y_8bit : unsigned(7 downto 0):=(others=>'0');
signal Cb_8bit : unsigned(7 downto 0):=(others=>'0');
signal Cr_8bit : unsigned(7 downto 0):=(others=>'0');
signal cmp_idx : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx_d1 : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx_d2 : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx_d3 : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx_d4 : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx_d5 : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx_d6 : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx_d7 : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx_d8 : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx_d9 : unsigned(2 downto 0):=(others=>'0');
signal fifo1_rd : std_logic:='0';
signal fifo1_wr : std_logic:='0';
signal fifo1_q : std_logic_vector(11 downto 0):=(others=>'0');
signal fifo1_full : std_logic:='0';
signal fifo1_empty : std_logic:='0';
signal fifo1_count : std_logic_vector(9 downto 0):=(others=>'0');
signal fifo1_rd_cnt : unsigned(5 downto 0):=(others=>'0');
signal fifo1_q_dval : std_logic:='0';
signal fifo_data_in : std_logic_vector(11 downto 0):=(others=>'0');
signal fifo_rd_arm : std_logic:='0';
signal eoi_fdct : std_logic:='0';
signal bf_fifo_rd_s : std_logic:='0';
signal start_int : std_logic:='0';
signal start_int_d : std_logic_vector(4 downto 0):=(others=>'0');
signal fram1_data : std_logic_vector(23 downto 0):=(others=>'0');
signal fram1_q : std_logic_vector(23 downto 0):=(others=>'0');
signal fram1_we : std_logic:='0';
signal fram1_waddr : std_logic_vector(6 downto 0):=(others=>'0');
signal fram1_raddr : std_logic_vector(6 downto 0):=(others=>'0');
signal fram1_rd_d : std_logic_vector(8 downto 0):=(others=>'0');
signal fram1_rd : std_logic:='0';
signal rd_started : std_logic:='0';
signal writing_en : std_logic:='0';
signal fram1_q_vld : std_logic:='0';
signal fram1_line_cnt : unsigned(2 downto 0):=(others=>'0');
signal fram1_pix_cnt : unsigned(2 downto 0):=(others=>'0');
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
zz_data <= dbuf_q;
bf_fifo_rd <= bf_fifo_rd_s;
-------------------------------------------------------------------
-- FRAM1
-------------------------------------------------------------------
U_FRAM1 : entity work.RAMZ
generic map
(
RAMADDR_W => 7,
RAMDATA_W => 24
)
port map
(
d => fram1_data,
waddr => fram1_waddr,
raddr => fram1_raddr,
we => fram1_we,
clk => CLK,
q => fram1_q
);
fram1_we <= bf_dval;
fram1_data <= bf_fifo_q;
fram1_q_vld <= fram1_rd_d(5);
-------------------------------------------------------------------
-- FRAM1 process
-------------------------------------------------------------------
p_fram1_acc : process(CLK, RST)
begin
if RST = '1' then
fram1_waddr <= (others => '0');
elsif CLK'event and CLK = '1' then
if fram1_we = '1' then
fram1_waddr <= std_logic_vector(unsigned(fram1_waddr) + 1);
end if;
end if;
end process;
-------------------------------------------------------------------
-- IRAM read process
-------------------------------------------------------------------
p_counter1 : process(CLK, RST)
begin
if RST = '1' then
rd_en <= '0';
rd_en_d1 <= '0';
x_pixel_cnt <= (others => '0');
y_line_cnt <= (others => '0');
input_rd_cnt <= (others => '0');
cmp_idx <= (others => '0');
cur_cmp_idx <= (others => '0');
cur_cmp_idx_d1 <= (others => '0');
cur_cmp_idx_d2 <= (others => '0');
cur_cmp_idx_d3 <= (others => '0');
cur_cmp_idx_d4 <= (others => '0');
cur_cmp_idx_d5 <= (others => '0');
cur_cmp_idx_d6 <= (others => '0');
cur_cmp_idx_d7 <= (others => '0');
cur_cmp_idx_d8 <= (others => '0');
cur_cmp_idx_d9 <= (others => '0');
eoi_fdct <= '0';
start_int <= '0';
bf_fifo_rd_s <= '0';
bf_dval <= '0';
bf_dval_m1 <= '0';
bf_dval_m2 <= '0';
fram1_rd <= '0';
fram1_rd_d <= (others => '0');
start_int_d <= (others => '0');
fram1_raddr <= (others => '0');
fram1_line_cnt <= (others => '0');
fram1_pix_cnt <= (others => '0');
elsif CLK'event and CLK = '1' then
rd_en_d1 <= rd_en;
cur_cmp_idx_d1 <= cur_cmp_idx;
cur_cmp_idx_d2 <= cur_cmp_idx_d1;
cur_cmp_idx_d3 <= cur_cmp_idx_d2;
cur_cmp_idx_d4 <= cur_cmp_idx_d3;
cur_cmp_idx_d5 <= cur_cmp_idx_d4;
cur_cmp_idx_d6 <= cur_cmp_idx_d5;
cur_cmp_idx_d7 <= cur_cmp_idx_d6;
cur_cmp_idx_d8 <= cur_cmp_idx_d7;
cur_cmp_idx_d9 <= cur_cmp_idx_d8;
start_int <= '0';
bf_dval_m3 <= bf_fifo_rd_s;
bf_dval_m2 <= bf_dval_m3;
bf_dval_m1 <= bf_dval_m2;
bf_dval <= bf_dval_m1;
fram1_rd_d <= fram1_rd_d(fram1_rd_d'length-2 downto 0) & fram1_rd;
start_int_d <= start_int_d(start_int_d'length-2 downto 0) & start_int;
-- SOF or internal self-start
if (sof = '1' or start_int = '1') then
input_rd_cnt <= (others => '0');
-- enable BUF_FIFO/FRAM1 reading
rd_started <= '1';
-- component index
if cmp_idx = 4-1 then
cmp_idx <= (others => '0');
-- horizontal block counter
if x_pixel_cnt = unsigned(img_size_x)-16 then
x_pixel_cnt <= (others => '0');
-- vertical block counter
if y_line_cnt = unsigned(img_size_y)-8 then
y_line_cnt <= (others => '0');
-- set end of image flag
eoi_fdct <= '1';
else
y_line_cnt <= y_line_cnt + 8;
end if;
else
x_pixel_cnt <= x_pixel_cnt + 16;
end if;
else
cmp_idx <=cmp_idx + 1;
end if;
cur_cmp_idx <= cmp_idx;
end if;
-- wait until FIFO becomes half full but only for component 0
-- as we read buf FIFO only during component 0
if rd_started = '1' and (bf_fifo_hf_full = '1' or cur_cmp_idx > 1) then
rd_en <= '1';
rd_started <= '0';
end if;
bf_fifo_rd_s <= '0';
fram1_rd <= '0';
-- stall reading from input FIFO and writing to output FIFO
-- when output FIFO is almost full
if rd_en = '1' and unsigned(fifo1_count) < 512-64 and
(bf_fifo_hf_full = '1' or cur_cmp_idx > 1) then
-- read request goes to BUF_FIFO only for component 0.
if cur_cmp_idx < 2 then
bf_fifo_rd_s <= '1';
end if;
-- count number of samples read from input in one run
if input_rd_cnt = 64-1 then
rd_en <= '0';
-- internal restart
start_int <= '1' and not eoi_fdct;
eoi_fdct <= '0';
else
input_rd_cnt <= input_rd_cnt + 1;
end if;
-- FRAM read enable
fram1_rd <= '1';
end if;
-- increment FRAM1 read address according to subsampling
-- idea is to extract 8x8 from 16x8 block
-- there are two luminance blocks left and right
-- there is 2:1 subsampled Cb block
-- there is 2:1 subsampled Cr block
-- subsampling done as simple decimation by 2 wo/ averaging
if sof = '1' then
fram1_raddr <= (others => '0');
fram1_line_cnt <= (others => '0');
fram1_pix_cnt <= (others => '0');
elsif start_int_d(4) = '1' then
fram1_line_cnt <= (others => '0');
fram1_pix_cnt <= (others => '0');
case cur_cmp_idx_d4 is
-- Y1, Cr, Cb
when "000" | "010" | "011" =>
fram1_raddr <= (others => '0');
-- Y2
when "001" =>
fram1_raddr <= std_logic_vector(to_unsigned(64, fram1_raddr'length));
when others =>
null;
end case;
elsif fram1_rd_d(4) = '1' then
if fram1_pix_cnt = 8-1 then
fram1_pix_cnt <= (others => '0');
if fram1_line_cnt = 8-1 then
fram1_line_cnt <= (others => '0');
else
fram1_line_cnt <= fram1_line_cnt + 1;
end if;
else
fram1_pix_cnt <= fram1_pix_cnt + 1;
end if;
case cur_cmp_idx_d6 is
when "000" | "001" =>
fram1_raddr <= std_logic_vector(unsigned(fram1_raddr) + 1);
when "010" | "011" =>
if fram1_pix_cnt = 4-1 then
fram1_raddr <= std_logic_vector('1' & fram1_line_cnt & "000");
elsif fram1_pix_cnt = 8-1 then
if fram1_line_cnt = 8-1 then
fram1_raddr <= '0' & "000" & "000";
else
fram1_raddr <= std_logic_vector('0' & (fram1_line_cnt+1) & "000");
end if;
else
fram1_raddr <= std_logic_vector(unsigned(fram1_raddr) + 2);
end if;
when others =>
null;
end case;
end if;
end if;
end process;
-------------------------------------------------------------------
-- FDCT with input level shift
-------------------------------------------------------------------
U_MDCT : entity work.MDCT
port map
(
clk => CLK,
rst => RST,
dcti => mdct_data_in,
idv => mdct_idval,
odv => mdct_odval,
dcto => mdct_data_out,
odv1 => odv1,
dcto1 => dcto1
);
mdct_idval <= fram1_rd_d(8);
R_s <= signed('0' & fram1_q(7 downto 0));
G_s <= signed('0' & fram1_q(15 downto 8));
B_s <= signed('0' & fram1_q(23 downto 16));
-------------------------------------------------------------------
-- Mux1
-------------------------------------------------------------------
p_mux1 : process(CLK, RST)
begin
if RST = '1' then
mdct_data_in <= (others => '0');
elsif CLK'event and CLK = '1' then
case cur_cmp_idx_d9 is
when "000" | "001" =>
mdct_data_in <= std_logic_vector(Y_8bit);
when "010" =>
mdct_data_in <= std_logic_vector(Cb_8bit);
when "011" =>
mdct_data_in <= std_logic_vector(Cr_8bit);
when others =>
null;
end case;
end if;
end process;
-------------------------------------------------------------------
-- FIFO1
-------------------------------------------------------------------
U_FIFO1 : entity work.FIFO
generic map
(
DATA_WIDTH => 12,
ADDR_WIDTH => 9
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo1_rd,
winc => fifo1_wr,
datai => fifo_data_in,
datao => fifo1_q,
fullo => fifo1_full,
emptyo => fifo1_empty,
count => fifo1_count
);
fifo1_wr <= mdct_odval;
fifo_data_in <= mdct_data_out;
-------------------------------------------------------------------
-- FIFO1 rd controller
-------------------------------------------------------------------
p_fifo_rd_ctrl : process(CLK, RST)
begin
if RST = '1' then
fifo1_rd <= '0';
fifo_rd_arm <= '0';
fifo1_rd_cnt <= (others => '0');
fifo1_q_dval <= '0';
elsif CLK'event and CLK = '1' then
fifo1_rd <= '0';
fifo1_q_dval <= fifo1_rd;
if start_pb = '1' then
fifo_rd_arm <= '1';
fifo1_rd_cnt <= (others => '0');
end if;
if fifo_rd_arm = '1' then
if fifo1_rd_cnt = 64-1 then
fifo_rd_arm <= '0';
fifo1_rd <= '1';
elsif fifo1_empty = '0' then
fifo1_rd <= '1';
fifo1_rd_cnt <= fifo1_rd_cnt + 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- write counter
-------------------------------------------------------------------
p_wr_cnt : process(CLK, RST)
begin
if RST = '1' then
wr_cnt <= (others => '0');
ready_pb <= '0';
xw_cnt <= (others => '0');
yw_cnt <= (others => '0');
writing_en <= '0';
elsif CLK'event and CLK = '1' then
ready_pb <= '0';
if start_pb = '1' then
wr_cnt <= (others => '0');
xw_cnt <= (others => '0');
yw_cnt <= (others => '0');
writing_en <= '1';
end if;
if writing_en = '1' then
if fifo1_q_dval = '1' then
if wr_cnt = 64-1 then
wr_cnt <= (others => '0');
ready_pb <= '1';
writing_en <= '0';
else
wr_cnt <= wr_cnt + 1;
end if;
if yw_cnt = 8-1 then
yw_cnt <= (others => '0');
xw_cnt <= xw_cnt+1;
else
yw_cnt <= yw_cnt+1;
end if;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- RGB to YCbCr conversion
-------------------------------------------------------------------
p_rgb2ycbcr : process(CLK, RST)
begin
if RST = '1' then
Y_Reg_1 <= (others => '0');
Y_Reg_2 <= (others => '0');
Y_Reg_3 <= (others => '0');
Cb_Reg_1 <= (others => '0');
Cb_Reg_2 <= (others => '0');
Cb_Reg_3 <= (others => '0');
Cr_Reg_1 <= (others => '0');
Cr_Reg_2 <= (others => '0');
Cr_Reg_3 <= (others => '0');
Y_Reg <= (others => '0');
Cb_Reg <= (others => '0');
Cr_Reg <= (others => '0');
elsif CLK'event and CLK = '1' then
Y_Reg_1 <= R_s*C_Y_1;
Y_Reg_2 <= G_s*C_Y_2;
Y_Reg_3 <= B_s*C_Y_3;
Cb_Reg_1 <= R_s*C_Cb_1;
Cb_Reg_2 <= G_s*C_Cb_2;
Cb_Reg_3 <= B_s*C_Cb_3;
Cr_Reg_1 <= R_s*C_Cr_1;
Cr_Reg_2 <= G_s*C_Cr_2;
Cr_Reg_3 <= B_s*C_Cr_3;
Y_Reg <= Y_Reg_1 + Y_Reg_2 + Y_Reg_3;
Cb_Reg <= Cb_Reg_1 + Cb_Reg_2 + Cb_Reg_3 + to_signed(128*16384,Cb_Reg'length);
Cr_Reg <= Cr_Reg_1 + Cr_Reg_2 + Cr_Reg_3 + to_signed(128*16384,Cr_Reg'length);
end if;
end process;
Y_8bit <= unsigned(Y_Reg(21 downto 14));
Cb_8bit <= unsigned(Cb_Reg(21 downto 14));
Cr_8bit <= unsigned(Cr_Reg(21 downto 14));
-------------------------------------------------------------------
-- DBUF
-------------------------------------------------------------------
U_RAMZ : entity work.RAMZ
generic map
(
RAMADDR_W => 7,
RAMDATA_W => 12
)
port map
(
d => dbuf_data,
waddr => dbuf_waddr,
raddr => dbuf_raddr,
we => dbuf_we,
clk => CLK,
q => dbuf_q
);
dbuf_data <= fifo1_q;
dbuf_we <= fifo1_q_dval;
dbuf_waddr <= (not zz_buf_sel) & std_logic_vector(yw_cnt & xw_cnt);
dbuf_raddr <= zz_buf_sel & zz_rd_addr;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | bsd-2-clause | 2073f8a08e92c0dc174ec66c5a8e51e5 | 0.42218 | 3.784341 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-1/tcounter.vhd | 1 | 890 | --
-- Copyright 1991-2015 Mentor Graphics Corporation
--
-- All Rights Reserved.
--
-- THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
-- MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
--
entity test_counter is
PORT ( count : BUFFER bit_vector(8 downto 1));
end;
architecture only of test_counter is
COMPONENT counter
PORT ( count : BUFFER bit_vector(8 downto 1);
clk : IN bit;
reset : IN bit);
END COMPONENT ;
SIGNAL clk : bit := '0';
SIGNAL reset : bit := '0';
begin
dut : counter
PORT MAP (
count => count,
clk => clk,
reset => reset );
clock : PROCESS
begin
wait for 10 ns; clk <= not clk;
end PROCESS clock;
stimulus : PROCESS
begin
wait for 5 ns; reset <= '1';
wait for 4 ns; reset <= '0';
wait;
end PROCESS stimulus;
end only;
| gpl-3.0 | 4b536a61f37bac0b911c448a6f8b639a | 0.638202 | 3.58871 | false | false | false | false |
tsotnep/vhdl_soc_audio_mixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/audio_buffer_v1_00_a/hdl/vhdl/audio_buffer.vhd | 3 | 17,497 | ------------------------------------------------------------------------------
-- audio_buffer.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: audio_buffer.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Mon Apr 13 19:59:47 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library audio_buffer_v1_00_a;
use audio_buffer_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity audio_buffer is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
clk_48_i : in std_logic;
sample_data_L_in : in std_logic_vector(23 downto 0);
sample_data_R_in : in std_logic_vector(23 downto 0);
sample_data_L_out : out std_logic_vector(23 downto 0);
sample_data_R_out : out std_logic_vector(23 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity audio_buffer;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of audio_buffer is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 2;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity audio_buffer_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
clk_48_i => clk_48_i,
sample_data_L_in => sample_data_L_in,
sample_data_R_in => sample_data_R_in,
sample_data_L_out => sample_data_L_out,
sample_data_R_out => sample_data_R_out,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
| mit | 030c48680cd92b924de58e89ad268848 | 0.452135 | 4.1015 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/ddr2ram/user_design/sim/sim_tb_top.vhd | 3 | 30,249 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C3_HW_TESTING : string := "FALSE";
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_MEMCLK_PERIOD : integer := 3200;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CLK_PERIOD_NS : real := 3200.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 13;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_MEM_BURST_LEN : integer := 4;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_SIMULATION : string := "TRUE";
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p2_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000");
constant C3_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p3_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000006ff", x"06ffffff");
constant C3_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff800", x"f8000000");
constant C3_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000");
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component ddr2ram is
generic
(
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic; c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_rd_clk : in std_logic;
c3_p2_rd_en : in std_logic;
c3_p2_rd_data : out std_logic_vector(31 downto 0);
c3_p2_rd_full : out std_logic;
c3_p2_rd_empty : out std_logic;
c3_p2_rd_count : out std_logic_vector(6 downto 0);
c3_p2_rd_overflow : out std_logic;
c3_p2_rd_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_wr_clk : in std_logic;
c3_p3_wr_en : in std_logic;
c3_p3_wr_mask : in std_logic_vector(3 downto 0);
c3_p3_wr_data : in std_logic_vector(31 downto 0);
c3_p3_wr_full : out std_logic;
c3_p3_wr_empty : out std_logic;
c3_p3_wr_count : out std_logic_vector(6 downto 0);
c3_p3_wr_underrun : out std_logic;
c3_p3_wr_error : out std_logic
);
end component;
component ddr2_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_rdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
rdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic
);
end component;
component memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000500";
C_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p3_END_ADDRESS : std_logic_vector(31 downto 0) := X"000006ff";
C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000500"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p3_mcb_cmd_en_o : out std_logic;
p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p3_mcb_cmd_full_i : in std_logic;
p3_mcb_wr_en_o : out std_logic;
p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
p3_mcb_wr_data_o : out std_logic_vector(31 downto 0);
p3_mcb_wr_full_i : in std_logic;
p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
-- User design Sim
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_cmp_error : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal c3_p2_cmd_en : std_logic;
signal c3_p2_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p2_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p2_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p2_cmd_empty : std_logic;
signal c3_p2_cmd_full : std_logic;
signal c3_p2_rd_en : std_logic;
signal c3_p2_rd_data : std_logic_vector(31 downto 0);
signal c3_p2_rd_full : std_logic;
signal c3_p2_rd_empty : std_logic;
signal c3_p2_rd_count : std_logic_vector(6 downto 0);
signal c3_p2_rd_overflow : std_logic;
signal c3_p2_rd_error : std_logic;
signal c3_p3_cmd_en : std_logic;
signal c3_p3_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p3_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p3_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p3_cmd_empty : std_logic;
signal c3_p3_cmd_full : std_logic;
signal c3_p3_wr_en : std_logic;
signal c3_p3_wr_mask : std_logic_vector(3 downto 0);
signal c3_p3_wr_data : std_logic_vector(31 downto 0);
signal c3_p3_wr_full : std_logic;
signal c3_p3_wr_empty : std_logic;
signal c3_p3_wr_count : std_logic_vector(6 downto 0);
signal c3_p3_wr_underrun : std_logic;
signal c3_p3_wr_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
signal rzq3 : std_logic;
signal zio3 : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
error <= c3_error;
calib_done <= c3_calib_done;
-- The PULLDOWN component is connected to the ZIO signal primarily to avoid the
-- unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
zio_pulldown3 : PULLDOWN port map(O => zio3);
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : ddr2ram generic map
(
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,
c3_calib_done => c3_calib_done,
mcb3_rzq => rzq3,
mcb3_zio => zio3,
c3_p2_cmd_clk => (c3_clk0),
c3_p2_cmd_en => c3_p2_cmd_en,
c3_p2_cmd_instr => c3_p2_cmd_instr,
c3_p2_cmd_bl => c3_p2_cmd_bl,
c3_p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
c3_p2_cmd_empty => c3_p2_cmd_empty,
c3_p2_cmd_full => c3_p2_cmd_full,
c3_p2_rd_clk => (c3_clk0),
c3_p2_rd_en => c3_p2_rd_en,
c3_p2_rd_data => c3_p2_rd_data,
c3_p2_rd_full => c3_p2_rd_full,
c3_p2_rd_empty => c3_p2_rd_empty,
c3_p2_rd_count => c3_p2_rd_count,
c3_p2_rd_overflow => c3_p2_rd_overflow,
c3_p2_rd_error => c3_p2_rd_error,
c3_p3_cmd_clk => (c3_clk0),
c3_p3_cmd_en => c3_p3_cmd_en,
c3_p3_cmd_instr => c3_p3_cmd_instr,
c3_p3_cmd_bl => c3_p3_cmd_bl,
c3_p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
c3_p3_cmd_empty => c3_p3_cmd_empty,
c3_p3_cmd_full => c3_p3_cmd_full,
c3_p3_wr_clk => (c3_clk0),
c3_p3_wr_en => c3_p3_wr_en,
c3_p3_wr_mask => c3_p3_wr_mask,
c3_p3_wr_data => c3_p3_wr_data,
c3_p3_wr_full => c3_p3_wr_full,
c3_p3_wr_empty => c3_p3_wr_empty,
c3_p3_wr_count => c3_p3_wr_count,
c3_p3_wr_underrun => c3_p3_wr_underrun,
c3_p3_wr_error => c3_p3_wr_error
);
-- user interface
memc3_tb_top_inst : memc3_tb_top generic map
(
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_p2_BEGIN_ADDRESS => C3_p2_BEGIN_ADDRESS,
C_p2_DATA_MODE => C3_p2_DATA_MODE,
C_p2_END_ADDRESS => C3_p2_END_ADDRESS,
C_p2_PRBS_EADDR_MASK_POS => C3_p2_PRBS_EADDR_MASK_POS,
C_p2_PRBS_SADDR_MASK_POS => C3_p2_PRBS_SADDR_MASK_POS,
C_p3_BEGIN_ADDRESS => C3_p3_BEGIN_ADDRESS,
C_p3_DATA_MODE => C3_p3_DATA_MODE,
C_p3_END_ADDRESS => C3_p3_END_ADDRESS,
C_p3_PRBS_EADDR_MASK_POS => C3_p3_PRBS_EADDR_MASK_POS,
C_p3_PRBS_SADDR_MASK_POS => C3_p3_PRBS_SADDR_MASK_POS
)
port map
(
clk0 => c3_clk0,
rst0 => c3_rst0,
calib_done => c3_calib_done,
cmp_error => c3_cmp_error,
error => c3_error,
error_status => c3_error_status,
vio_modify_enable => c3_vio_modify_enable,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
p2_mcb_cmd_en_o => c3_p2_cmd_en,
p2_mcb_cmd_instr_o => c3_p2_cmd_instr,
p2_mcb_cmd_bl_o => c3_p2_cmd_bl,
p2_mcb_cmd_addr_o => c3_p2_cmd_byte_addr,
p2_mcb_cmd_full_i => c3_p2_cmd_full,
p2_mcb_rd_en_o => c3_p2_rd_en,
p2_mcb_rd_data_i => c3_p2_rd_data,
p2_mcb_rd_empty_i => c3_p2_rd_empty,
p2_mcb_rd_fifo_counts => c3_p2_rd_count,
p3_mcb_cmd_en_o => c3_p3_cmd_en,
p3_mcb_cmd_instr_o => c3_p3_cmd_instr,
p3_mcb_cmd_bl_o => c3_p3_cmd_bl,
p3_mcb_cmd_addr_o => c3_p3_cmd_byte_addr,
p3_mcb_cmd_full_i => c3_p3_cmd_full,
p3_mcb_wr_en_o => c3_p3_wr_en,
p3_mcb_wr_mask_o => c3_p3_wr_mask,
p3_mcb_wr_data_o => c3_p3_wr_data,
p3_mcb_wr_full_i => c3_p3_wr_full,
p3_mcb_wr_fifo_counts => c3_p3_wr_count
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr2_model_c3 port map(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_rdqs => mcb3_dram_dm_vector ,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
rdqs_n => open,
odt => mcb3_dram_odt
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
| bsd-2-clause | f5bac360176de1f786e1656c17024450 | 0.460908 | 3.379777 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/source/vhdl/adder_tree.vhd | 2 | 8,438 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: adder_tree - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity adder_tree is
generic (
USE_DSP_FOR_ADD : boolean := true;
NUMBER_OF_INPUTS : integer := 4;
INPUT_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
input_string : in std_logic_vector(NUMBER_OF_INPUTS*INPUT_BITWIDTH-1 downto 0);
rdy : out std_logic;
output : out std_logic_vector(INPUT_BITWIDTH+integer(ceil(log2(real(NUMBER_OF_INPUTS))))-1 downto 0)
);
end adder_tree;
architecture Behavioral of adder_tree is
constant LAYERS_TREE_ADDER : integer := integer(ceil(log2(real(NUMBER_OF_INPUTS))));
constant INT_BITWIDTH : integer := INPUT_BITWIDTH+LAYERS_TREE_ADDER;
constant SINGLE_ADDER_LAT : integer := 2;
constant TREE_ADDER_LAT : integer := SINGLE_ADDER_LAT*LAYERS_TREE_ADDER;
type input_array_type is array(0 to NUMBER_OF_INPUTS-1) of std_logic_vector(INPUT_BITWIDTH-1 downto 0);
type tree_adder_res_array_type is array(0 to LAYERS_TREE_ADDER-1, 0 to integer(ceil(real(NUMBER_OF_INPUTS)/real(2)))-1) of std_logic_vector(INT_BITWIDTH-1 downto 0);
type data_delay_type is array(0 to SINGLE_ADDER_LAT-1) of std_logic_vector(INT_BITWIDTH-1 downto 0);
type data_delay_array_type is array(0 to LAYERS_TREE_ADDER-1-1) of data_delay_type;
component addorsub
generic (
USE_DSP : boolean := true;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
signal input_array : input_array_type;
signal data_delay_array : data_delay_array_type;
signal ctrl_delay_line : std_logic_vector(0 to TREE_ADDER_LAT-1);
signal tmp_tree_adder_res : tree_adder_res_array_type;
begin
G0: for I in 0 to NUMBER_OF_INPUTS-1 generate
input_array(I) <= input_string((I+1)*INPUT_BITWIDTH-1 downto I*INPUT_BITWIDTH);
end generate G0;
G2: for I in 0 to LAYERS_TREE_ADDER-1 generate
G_TOP_LAYER: if I = 0 generate
G2_2: for J in 0 to (NUMBER_OF_INPUTS/(2**(I+1)))-1 generate
addorsub_inst_2 : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => INPUT_BITWIDTH,
B_BITWIDTH => INPUT_BITWIDTH,
RES_BITWIDTH => INT_BITWIDTH
)
port map (
clk => clk,
sclr => sclr,
nd => '1',
sub => sub,
a => input_array(2*J),
b => input_array(2*J+1),
res => tmp_tree_adder_res(I,J),
rdy => open
);
end generate G2_2;
G2_3: if NUMBER_OF_INPUTS/(2**(I+1)) < integer(ceil(real(NUMBER_OF_INPUTS)/real(2**(I+1)))) generate
data_delay_array_proc : process(clk)
begin
if rising_edge(clk) then
data_delay_array(I)(0)(INPUT_BITWIDTH-1 downto 0) <= input_array(NUMBER_OF_INPUTS/(2**(I+1))*2);
data_delay_array(I)(0)(INT_BITWIDTH-1 downto INPUT_BITWIDTH) <= (others => input_array(NUMBER_OF_INPUTS/(2**(I+1))*2)(INPUT_BITWIDTH-1));
data_delay_array(I)(1 to SINGLE_ADDER_LAT-1) <= data_delay_array(I)(0 to SINGLE_ADDER_LAT-2);
end if;
end process data_delay_array_proc;
tmp_tree_adder_res(I,NUMBER_OF_INPUTS/(2**(I+1))) <= data_delay_array(I)(SINGLE_ADDER_LAT-1);
end generate G2_3;
end generate G_TOP_LAYER;
G_OTHER_LAYER: if I > 0 AND I < LAYERS_TREE_ADDER-1 generate
G2_2: for J in 0 to ((NUMBER_OF_INPUTS+NUMBER_OF_INPUTS-(NUMBER_OF_INPUTS/(2**I))*(2**I))/(2**(I+1)))-1 generate
addorsub_inst_2 : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => INT_BITWIDTH,
B_BITWIDTH => INT_BITWIDTH,
RES_BITWIDTH => INT_BITWIDTH
)
port map (
clk => clk,
sclr => sclr,
nd => '1',
sub => sub,
a => tmp_tree_adder_res(I-1,2*J),
b => tmp_tree_adder_res(I-1,2*J+1),
res => tmp_tree_adder_res(I,J),
rdy => open
);
end generate G2_2;
G2_3: if ((NUMBER_OF_INPUTS+NUMBER_OF_INPUTS-(NUMBER_OF_INPUTS/(2**I))*(2**I))/(2**(I+1))) < integer(ceil(real(NUMBER_OF_INPUTS)/real(2**(I+1)))) generate
data_delay_array_proc : process(clk)
begin
if rising_edge(clk) then
data_delay_array(I)(0) <= tmp_tree_adder_res(I-1,NUMBER_OF_INPUTS/(2**(I+1))*2);
data_delay_array(I)(1 to SINGLE_ADDER_LAT-1) <= data_delay_array(I)(0 to SINGLE_ADDER_LAT-2);
end if;
end process data_delay_array_proc;
tmp_tree_adder_res(I,NUMBER_OF_INPUTS/(2**(I+1))) <= data_delay_array(I)(SINGLE_ADDER_LAT-1);
end generate G2_3;
end generate G_OTHER_LAYER;
G_BOTTOM_LAYER: if I = LAYERS_TREE_ADDER-1 AND LAYERS_TREE_ADDER > 1 generate
G2_2: for J in 0 to 0 generate
addorsub_inst_2 : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => INT_BITWIDTH,
B_BITWIDTH => INT_BITWIDTH,
RES_BITWIDTH => INT_BITWIDTH
)
port map (
clk => clk,
sclr => sclr,
nd => '1',
sub => sub,
a => tmp_tree_adder_res(I-1,2*J),
b => tmp_tree_adder_res(I-1,2*J+1),
res => tmp_tree_adder_res(I,J),
rdy => open
);
end generate G2_2;
end generate G_BOTTOM_LAYER;
end generate G2;
ctrl_delay_line_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
ctrl_delay_line <= (others => '0');
else
ctrl_delay_line(0) <= nd;
ctrl_delay_line(1 to TREE_ADDER_LAT-1) <= ctrl_delay_line(0 to TREE_ADDER_LAT-2);
end if;
end if;
end process ctrl_delay_line_proc;
rdy <= ctrl_delay_line(TREE_ADDER_LAT-1);
output <= tmp_tree_adder_res(LAYERS_TREE_ADDER-1,0);
end Behavioral;
| bsd-3-clause | f5b5f870e0f1606873d8354cc99378e2 | 0.476061 | 4.03539 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_HLS/rtl/simulation/testbench.vhd | 1 | 21,037 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- testbench - behavior
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.all;
use ieee.math_real.all;
use STD.textio.all;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
constant MY_N : integer := 2*128-1; -- 2*N_POINTS-1
constant MY_K : integer := 4;
constant MY_P : integer := 4; -- must match filtering_algorithm_top.h
constant D : integer := 3;
-- bit width defs
constant COORD_BITWIDTH : integer := 16;
constant COORD_BITWIDTH_EXT : integer := 32;
constant INDEX_BITWIDTH : integer := 8;
constant NODE_POINTER_BITWIDTH : integer := 16;
-- input data
file my_input_tree : TEXT open READ_MODE is "../../../simulation/tree_data_N128_K4_D3_s0.75.mat";
file my_input_cntr : TEXT open READ_MODE is "../../../simulation/initial_centres_N128_K4_D3_s0.75_1.mat";
--file my_input_tree : TEXT open READ_MODE is "../../../simulation/tree_data_N16384_K128_D3_s0.20.mat";
--file my_input_cntr : TEXT open READ_MODE is "../../../simulation/initial_centres_N16384_K128_D3_s0.20_1.mat";
-- Clock period definitions
constant CLK_PERIOD : time := 10 ns;
constant RESET_CYCLES : integer := 20;
constant INIT_CYCLES : integer := MY_N;
constant NUM_COLS : integer := 5+4*D;
type state_type is (readfile, reset, start_processing, processing, processing_done);
type file_tree_data_array_type is array(0 to NUM_COLS-1, 0 to MY_N-1) of integer;
type file_cntr_data_array_type is array(0 to D-1, 0 to MY_K-1) of integer;
subtype coord_type is std_logic_vector(COORD_BITWIDTH-1 downto 0);
subtype node_address_type is std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
type data_type is array(0 to D-1) of coord_type;
subtype coord_type_ext is std_logic_vector(COORD_BITWIDTH_EXT-1 downto 0);
type data_type_ext is array(0 to D-1) of coord_type_ext;
type node_data_type is
record
wgtCent : data_type_ext;
midPoint : data_type;
bnd_lo : data_type;
bnd_hi : data_type;
sum_sq : coord_type_ext;
count : coord_type;
left : node_address_type;
right : node_address_type;
end record;
function stdlogic_2_datapoint(c : std_logic_vector) return data_type is
variable result : data_type;
begin
for I in 0 to D-1 loop
result(I) := c((I+1)*COORD_BITWIDTH-1 downto I*COORD_BITWIDTH);
end loop;
return result;
end stdlogic_2_datapoint;
function datapoint_2_stdlogic(c : data_type) return std_logic_vector is
variable result : std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
begin
for I in 0 to D-1 loop
result((I+1)*COORD_BITWIDTH-1 downto I*COORD_BITWIDTH) := std_logic_vector(c(I));
end loop;
return result;
end datapoint_2_stdlogic;
function nodedata_2_stdlogic(n : node_data_type) return std_logic_vector is
variable result : std_logic_vector(D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+COORD_BITWIDTH_EXT+COORD_BITWIDTH+2*NODE_POINTER_BITWIDTH-1 downto 0);
begin
for I in 0 to D-1 loop
result((I+1)*COORD_BITWIDTH_EXT+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto I*COORD_BITWIDTH_EXT+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.wgtCent(I);
result(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.midPoint(I);
result(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+1*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+1*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.bnd_lo(I);
result(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+2*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+2*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.bnd_hi(I);
end loop;
result(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.sum_sq;
result(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.count;
result(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+1*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := std_logic_vector(n.left);
result(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+2*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+1*NODE_POINTER_BITWIDTH) := std_logic_vector(n.right);
return result;
end nodedata_2_stdlogic;
function stdlogic_2_nodedata(n : std_logic_vector) return node_data_type is
variable result : node_data_type;
begin
for I in 0 to D-1 loop
result.wgtCent(I) := n((I+1)*COORD_BITWIDTH_EXT+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto I*COORD_BITWIDTH_EXT+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.midPoint(I) := n(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.bnd_lo(I) := n(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+1*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+1*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.bnd_hi(I) := n(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+2*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+2*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
end loop;
result.sum_sq := n(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.count := n(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.left := n(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+1*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.right := n(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+2*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+1*NODE_POINTER_BITWIDTH);
return result;
end stdlogic_2_nodedata;
-- Component Declaration for the Unit Under Test (UUT)
component filtering_algorithm_top is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
node_data_dout : IN STD_LOGIC_VECTOR (3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0);
node_data_empty_n : IN STD_LOGIC;
node_data_read : OUT STD_LOGIC;
node_address_V_dout : IN STD_LOGIC_VECTOR (NODE_POINTER_BITWIDTH-1 downto 0);
node_address_V_empty_n : IN STD_LOGIC;
node_address_V_read : OUT STD_LOGIC;
cntr_pos_init_value_V_dout : IN STD_LOGIC_VECTOR (D*COORD_BITWIDTH-1 downto 0);
cntr_pos_init_value_V_empty_n : IN STD_LOGIC;
cntr_pos_init_value_V_read : OUT STD_LOGIC;
n_V : IN STD_LOGIC_VECTOR (NODE_POINTER_BITWIDTH-1 downto 0);
k_V : IN STD_LOGIC_VECTOR (INDEX_BITWIDTH-1 downto 0);
root_V_dout : IN STD_LOGIC_VECTOR (NODE_POINTER_BITWIDTH-1 downto 0);
root_V_empty_n : IN STD_LOGIC;
root_V_read : OUT STD_LOGIC;
distortion_out_V_din : OUT STD_LOGIC_VECTOR (COORD_BITWIDTH_EXT-1 downto 0);
distortion_out_V_full_n : IN STD_LOGIC;
distortion_out_V_write : OUT STD_LOGIC;
clusters_out_value_V_din : OUT STD_LOGIC_VECTOR (D*COORD_BITWIDTH-1 downto 0);
clusters_out_value_V_full_n : IN STD_LOGIC;
clusters_out_value_V_write : OUT STD_LOGIC
);
end component;
--Inputs
signal ap_clk : std_logic;
signal ap_rst : std_logic := '1';
signal ap_start : std_logic := '0';
signal node_data_dout : std_logic_vector (3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0);
signal node_type_node_data_dout : node_data_type;
signal node_data_empty_n : std_logic := '1';
signal node_address_V_dout : std_logic_vector (NODE_POINTER_BITWIDTH-1 downto 0);
signal node_address_V_empty_n : std_logic := '1';
signal cntr_pos_init_value_V_dout : std_logic_vector (D*COORD_BITWIDTH-1 downto 0);
signal data_type_cntr_pos_init_value_V_dout : data_type;
signal cntr_pos_init_value_V_empty_n : std_logic := '1';
signal n_V : std_logic_vector (NODE_POINTER_BITWIDTH-1 downto 0);
signal k_V : std_logic_vector (INDEX_BITWIDTH-1 downto 0);
signal root_V_dout : std_logic_vector (NODE_POINTER_BITWIDTH-1 downto 0);
signal root_V_empty_n : std_logic := '1';
signal distortion_out_V_full_n : std_logic := '1';
signal clusters_out_value_V_full_n : std_logic := '1';
-- Outputs
signal ap_done : std_logic;
signal ap_idle : std_logic;
signal node_data_read : std_logic;
signal node_address_V_read : std_logic;
signal root_V_read : std_logic;
signal cntr_pos_init_value_V_read : std_logic;
signal distortion_out_V_din : std_logic_vector (COORD_BITWIDTH_EXT-1 downto 0);
signal distortion_out_V_write : std_logic;
signal clusters_out_value_V_din : std_logic_vector (D*COORD_BITWIDTH-1 downto 0);
signal data_type_clusters_out_value_V_din : data_type;
signal clusters_out_value_V_write : std_logic;
-- file io
signal file_tree_data_array : file_tree_data_array_type;
signal file_cntr_data_array : file_cntr_data_array_type;
signal read_file_done : std_logic := '0';
-- Operation
signal state : state_type := readfile;
signal reset_counter : integer := 0;
signal init_root_counter : integer := 0;
signal init_node_counter : integer := 0;
signal init_node_addr_counter : integer := 0;
signal init_cntr_counter : integer := 0;
signal cycle_counter : integer := 0;
signal reset_counter_done : std_logic := '0';
signal init_counter_done : std_logic := '0';
BEGIN
-- PARALLEL_UNITS == 1 always in testbench!!!
-- Instantiate the Unit Under Test (UUT)
uut : filtering_algorithm_top
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => ap_start,
ap_done => ap_done,
ap_idle => ap_idle,
node_data_dout => node_data_dout,
node_data_empty_n => node_data_empty_n,
node_data_read => node_data_read,
node_address_V_dout => node_address_V_dout,
node_address_V_empty_n => node_address_V_empty_n,
node_address_V_read => node_address_V_read,
cntr_pos_init_value_V_dout => cntr_pos_init_value_V_dout,
cntr_pos_init_value_V_empty_n => cntr_pos_init_value_V_empty_n,
cntr_pos_init_value_V_read => cntr_pos_init_value_V_read,
n_V => n_V,
k_V => k_V,
root_V_dout => root_V_dout,
root_V_empty_n => root_V_empty_n,
root_V_read => root_V_read,
distortion_out_V_din => distortion_out_V_din,
distortion_out_V_full_n => distortion_out_V_full_n,
distortion_out_V_write => distortion_out_V_write,
clusters_out_value_V_din => clusters_out_value_V_din,
clusters_out_value_V_full_n => clusters_out_value_V_full_n,
clusters_out_value_V_write => clusters_out_value_V_write
);
data_type_clusters_out_value_V_din <= stdlogic_2_datapoint(clusters_out_value_V_din);
-- Clock process definitions
clk_process : process
begin
ap_clk <= '1';
wait for CLK_PERIOD/2;
ap_clk <= '0';
wait for CLK_PERIOD/2;
end process;
fsm_proc : process(ap_clk)
begin
if rising_edge(ap_clk) then
if state = readfile AND read_file_done = '1' then
state <= reset;
elsif state = reset AND reset_counter_done = '1' then
state <= start_processing;
elsif state = start_processing then
state <= processing;
elsif state = processing AND ap_done = '1' then
state <= processing_done;
end if;
end if;
end process fsm_proc;
ap_start <= '1' WHEN state = start_processing ELSE '0';
counter_proc : process(ap_clk)
begin
if rising_edge(ap_clk) then
if state = reset then
reset_counter <= reset_counter+1;
end if;
if root_V_read = '1' then
init_root_counter <= init_root_counter+1;
end if;
if node_data_read = '1' then
init_node_counter <= init_node_counter+1;
end if;
if node_address_V_read = '1' then
init_node_addr_counter <= init_node_addr_counter+1;
end if;
if cntr_pos_init_value_V_read = '1' then
init_cntr_counter <= init_cntr_counter+1;
end if;
if state = processing then
cycle_counter <= cycle_counter+1;
end if;
end if;
end process counter_proc;
reset_counter_done <= '1' WHEN reset_counter = RESET_CYCLES-1 ELSE '0';
reset_proc : process(state)
begin
if state = reset then
ap_rst <= '1';
else
ap_rst <= '0';
end if;
end process reset_proc;
n_V <= std_logic_vector(to_unsigned(MY_N-1-(MY_P-1),NODE_POINTER_BITWIDTH));
k_V <= std_logic_vector(to_unsigned(MY_K-1,INDEX_BITWIDTH));
--root_V <= std_logic_vector(to_unsigned(file_tree_data_array(0,0),NODE_POINTER_BITWIDTH));
init_proc : process(state, init_node_counter, init_node_addr_counter, init_cntr_counter, init_root_counter)
variable centre_pos : data_type;
variable node : node_data_type;
begin
-- tree_node_memory
if init_node_counter < 8*MY_N then
for I in 0 to D-1 loop
node.bnd_lo(I) := std_logic_vector(to_signed(file_tree_data_array(5+0*D+I,init_node_counter/8),COORD_BITWIDTH));
node.bnd_hi(I) := std_logic_vector(to_signed(file_tree_data_array(5+1*D+I,init_node_counter/8),COORD_BITWIDTH));
node.midPoint(I) := std_logic_vector(to_signed(file_tree_data_array(5+2*D+I,init_node_counter/8),COORD_BITWIDTH));
node.wgtCent(I) := std_logic_vector(to_signed(file_tree_data_array(5+3*D+I,init_node_counter/8),COORD_BITWIDTH_EXT));
end loop;
node.sum_sq := std_logic_vector(to_signed(file_tree_data_array(4,init_node_counter/8),COORD_BITWIDTH_EXT));
node.count := std_logic_vector(to_signed(file_tree_data_array(3,init_node_counter/8),COORD_BITWIDTH));
node.left := std_logic_vector(to_unsigned(file_tree_data_array(1,init_node_counter/8),NODE_POINTER_BITWIDTH));
node.right := std_logic_vector(to_unsigned(file_tree_data_array(2,init_node_counter/8),NODE_POINTER_BITWIDTH));
node_data_dout <= nodedata_2_stdlogic(node);
node_type_node_data_dout <= node;
end if;
if init_root_counter < MY_P then
root_V_dout <= std_logic_vector(to_unsigned(init_root_counter*(2**NODE_POINTER_BITWIDTH)/2/MY_P,NODE_POINTER_BITWIDTH));
end if;
if init_node_addr_counter < MY_N then
node_address_V_dout <= std_logic_vector(to_unsigned(file_tree_data_array(0,init_node_addr_counter),NODE_POINTER_BITWIDTH));
end if;
if init_cntr_counter < My_K then
for I in 0 to D-1 loop
centre_pos(I) := std_logic_vector(to_signed(file_cntr_data_array(I,init_cntr_counter),COORD_BITWIDTH));
end loop;
cntr_pos_init_value_V_dout <= datapoint_2_stdlogic(centre_pos);
data_type_cntr_pos_init_value_V_dout <= centre_pos;
end if;
end process init_proc;
-- read tree data and initial centres from file
read_file : process
variable my_line : LINE;
variable my_input_line : LINE;
variable tmp_line_counter_tree : integer;
variable tmp_line_counter_cntr : integer;
variable tmp_file_line_counter_cntr : integer;
variable tmp_d : integer;
variable tmp_file_data_tree : file_tree_data_array_type;
variable tmp_file_data_cntr : file_cntr_data_array_type;
begin
write(my_line, string'("reading input files"));
writeline(output, my_line);
tmp_line_counter_tree := 0;
loop
exit when endfile(my_input_tree) OR tmp_line_counter_tree = MY_N;
readline(my_input_tree, my_input_line);
for I in 0 to NUM_COLS-1 loop -- NUM_COLS columns
read(my_input_line,tmp_file_data_tree(I,tmp_line_counter_tree));
end loop;
tmp_line_counter_tree := tmp_line_counter_tree+1;
end loop;
file_tree_data_array <= tmp_file_data_tree;
write(my_line, string'("Number of lines:"));
writeline(output, my_line);
write(my_line, tmp_line_counter_tree);
writeline(output, my_line);
-- reading centres now
tmp_line_counter_cntr := 0;
tmp_file_line_counter_cntr := 0;
tmp_d := 0;
loop
exit when endfile(my_input_cntr) OR tmp_line_counter_cntr = D*MY_K;
readline(my_input_cntr, my_input_line);
read(my_input_line,tmp_file_data_cntr(tmp_d,tmp_file_line_counter_cntr));
-- if tmp_line_counter_cntr < MY_K then
-- read(my_input_line,tmp_file_data_cntr(0,tmp_line_counter_cntr));
-- else
-- read(my_input_line,tmp_file_data_cntr(1,tmp_line_counter_cntr-MY_K));
-- end if;
tmp_line_counter_cntr := tmp_line_counter_cntr+1;
tmp_file_line_counter_cntr := tmp_file_line_counter_cntr+1;
if tmp_file_line_counter_cntr = MY_K then
tmp_d := tmp_d +1;
tmp_file_line_counter_cntr := 0;
end if;
end loop;
file_cntr_data_array <= tmp_file_data_cntr;
write(my_line, string'("Number of lines:"));
writeline(output, my_line);
write(my_line, tmp_line_counter_cntr);
writeline(output, my_line);
read_file_done <= '1';
wait; -- one shot at time zero,
end process read_file;
END;
| bsd-3-clause | 159fa6c5e6ce00c6cb58db9d2cd42178 | 0.610163 | 3.309786 | false | false | false | false |
Nooxet/embedded_bruteforce | vhdl/tb_brutus.vhd | 2 | 2,254 | --------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Create Date: 17:00:22 09/23/2014
-- Module Name: C:/Users/ael10jso/Xilinx/embedded_bruteforce/vhdl/tb_brutus.vhd
-- Project Name: controller_sg_pp_md_comp
-- Description:
--
-- VHDL Test Bench Created by ISE for module: brutus_top
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_brutus IS
END tb_brutus;
ARCHITECTURE behavior OF tb_brutus IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT brutus_top
PORT(
clk : IN std_logic;
rstn : IN std_logic;
i_fsl_data_recv : IN std_logic;
i_fsl_hash : IN std_logic_vector(127 downto 0);
o_pw_found : OUT std_logic;
o_passwd : OUT std_logic_vector(47 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rstn : std_logic := '0';
signal i_fsl_data_recv : std_logic := '0';
signal i_fsl_hash : std_logic_vector(127 downto 0) := (others => '0');
--Outputs
signal o_pw_found : std_logic;
signal o_passwd : std_logic_vector(47 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: brutus_top PORT MAP (
clk => clk,
rstn => rstn,
i_fsl_data_recv => i_fsl_data_recv,
i_fsl_hash => i_fsl_hash,
o_pw_found => o_pw_found,
o_passwd => o_passwd
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
rstn <= '0';
wait for clk_period*10;
rstn <= '1';
i_fsl_hash <= x"4124bc0a9335c27f086f24ba207a4912"; -- "aa"
i_fsl_data_recv <= '1';
wait for clk_period;
i_fsl_data_recv <= '0';
wait;
end process;
END;
| mit | 7bef9f23f0fb4a030e3d6d9ef5746796 | 0.51819 | 3.65316 | false | false | false | false |
freecores/gpib_controller | vhdl/test/gpib_RL_Test.vhd | 1 | 14,517 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 23:21:05 10/21/2011
-- Design Name:
-- Module Name: /windows/h/projekty/elektronika/USB_to_HPIB/usbToHpib/test_scr//gpibInterfaceTest.vhd
-- Project Name: usbToHpib
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: gpibInterface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.gpibComponents.all;
use work.helperComponents.all;
ENTITY gpib_RL_Test IS
END gpib_RL_Test;
ARCHITECTURE behavior OF gpib_RL_Test IS
-- Component Declaration for the Unit Under Test (UUT)
component gpibCableEmulator is port (
-- interface signals
DIO_1 : in std_logic_vector (7 downto 0);
output_valid_1 : in std_logic;
DIO_2 : in std_logic_vector (7 downto 0);
output_valid_2 : in std_logic;
DIO : out std_logic_vector (7 downto 0);
-- attention
ATN_1 : in std_logic;
ATN_2 : in std_logic;
ATN : out std_logic;
-- data valid
DAV_1 : in std_logic;
DAV_2 : in std_logic;
DAV : out std_logic;
-- not ready for data
NRFD_1 : in std_logic;
NRFD_2 : in std_logic;
NRFD : out std_logic;
-- no data accepted
NDAC_1 : in std_logic;
NDAC_2 : in std_logic;
NDAC : out std_logic;
-- end or identify
EOI_1 : in std_logic;
EOI_2 : in std_logic;
EOI : out std_logic;
-- service request
SRQ_1 : in std_logic;
SRQ_2 : in std_logic;
SRQ : out std_logic;
-- interface clear
IFC_1 : in std_logic;
IFC_2 : in std_logic;
IFC : out std_logic;
-- remote enable
REN_1 : in std_logic;
REN_2 : in std_logic;
REN : out std_logic
);
end component;
-- inputs common
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal T1 : std_logic_vector(7 downto 0) := "00000100";
-- inputs 1
signal data_1 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_1 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_1 : std_logic := '0';
signal nba_1 : std_logic := '0';
signal ltn_1 : std_logic := '0';
signal lun_1 : std_logic := '0';
signal lon_1 : std_logic := '0';
signal ton_1 : std_logic := '0';
signal endOf_1 : std_logic := '0';
signal gts_1 : std_logic := '0';
signal rpp_1 : std_logic := '0';
signal tcs_1 : std_logic := '0';
signal tca_1 : std_logic := '0';
signal sic_1 : std_logic := '0';
signal rsc_1 : std_logic := '0';
signal sre_1 : std_logic := '0';
signal rtl_1 : std_logic := '0';
signal rsv_1 : std_logic := '0';
signal ist_1 : std_logic := '0';
signal lpe_1 : std_logic := '0';
-- inputs 2
signal data_2 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_2 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_2 : std_logic := '0';
signal nba_2 : std_logic := '0';
signal ltn_2 : std_logic := '0';
signal lun_2 : std_logic := '0';
signal lon_2 : std_logic := '0';
signal ton_2 : std_logic := '0';
signal endOf_2 : std_logic := '0';
signal gts_2 : std_logic := '0';
signal rpp_2 : std_logic := '0';
signal tcs_2 : std_logic := '0';
signal tca_2 : std_logic := '0';
signal sic_2 : std_logic := '0';
signal rsc_2 : std_logic := '0';
signal sre_2 : std_logic := '0';
signal rtl_2 : std_logic := '0';
signal rsv_2 : std_logic := '0';
signal ist_2 : std_logic := '0';
signal lpe_2 : std_logic := '0';
-- outputs 1
signal dvd_1 : std_logic;
signal wnc_1 : std_logic;
signal tac_1 : std_logic;
signal cwrc_1 : std_logic;
signal cwrd_1 : std_logic;
signal clr_1 : std_logic;
signal trg_1 : std_logic;
signal atl_1 : std_logic;
signal att_1 : std_logic;
signal mla_1 : std_logic;
signal lsb_1 : std_logic;
signal spa_1 : std_logic;
signal ppr_1 : std_logic;
signal sreq_1 : std_logic;
signal isLocal_1 : std_logic;
signal currentSecAddr_1 : std_logic_vector (4 downto 0);
-- outputs 2
signal dvd_2 : std_logic;
signal wnc_2 : std_logic;
signal tac_2 : std_logic;
signal cwrc_2 : std_logic;
signal cwrd_2 : std_logic;
signal clr_2 : std_logic;
signal trg_2 : std_logic;
signal atl_2 : std_logic;
signal att_2 : std_logic;
signal mla_2 : std_logic;
signal lsb_2 : std_logic;
signal spa_2 : std_logic;
signal ppr_2 : std_logic;
signal sreq_2 : std_logic;
signal isLocal_2 : std_logic;
signal currentSecAddr_2 : std_logic_vector (4 downto 0);
-- common
signal DO : std_logic_vector (7 downto 0);
signal DI_1 : std_logic_vector (7 downto 0);
signal output_valid_1 : std_logic;
signal DI_2 : std_logic_vector (7 downto 0);
signal output_valid_2 : std_logic;
signal ATN_1, ATN_2, ATN : std_logic;
signal DAV_1, DAV_2, DAV : std_logic;
signal NRFD_1, NRFD_2, NRFD : std_logic;
signal NDAC_1, NDAC_2, NDAC : std_logic;
signal EOI_1, EOI_2, EOI : std_logic;
signal SRQ_1, SRQ_2, SRQ : std_logic;
signal IFC_1, IFC_2, IFC : std_logic;
signal REN_1, REN_2, REN : std_logic;
-- gpib reader
signal buf_interrupt : std_logic;
signal data_available : std_logic;
signal last_byte_addr : std_logic_vector (3 downto 0);
signal end_of_stream : std_logic;
signal byte_addr : std_logic_vector (3 downto 0);
signal data_out : std_logic_vector (7 downto 0);
signal reset_buffer : std_logic := '0';
signal dataSecAddr : std_logic_vector (4 downto 0);
-- gpib writer
signal w_last_byte_addr : std_logic_vector (3 downto 0)
:= (others => '0');
signal w_end_of_stream : std_logic := '0';
signal w_data_available : std_logic := '0';
signal w_buf_interrupt : std_logic;
signal w_data_in : std_logic_vector (7 downto 0);
signal w_byte_addr : std_logic_vector (3 downto 0);
signal w_reset_buffer : std_logic := '0';
type WR_BUF_TYPE is
array (0 to 15) of std_logic_vector (7 downto 0);
signal w_write_buffer : WR_BUF_TYPE;
-- Clock period definitions
constant clk_period : time := 2ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
gpib1: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00001",
myTalkAddr => "00001",
secAddrMask => (others => '0'),
data => data_1,
status_byte => status_byte_1,
T1 => T1,
rdy => rdy_1,
nba => nba_1,
ltn => ltn_1,
lun => lun_1,
lon => lon_1,
ton => ton_1,
endOf => endOf_1,
gts => gts_1,
rpp => rpp_1,
tcs => tcs_1,
tca => tca_1,
sic => sic_1,
rsc => rsc_1,
sre => sre_1,
rtl => rtl_1,
rsv => rsv_1,
ist => ist_1,
lpe => lpe_1,
dvd => dvd_1,
wnc => wnc_1,
tac => tac_1,
cwrc => cwrc_1,
cwrd => cwrd_1,
clr => clr_1,
trg => trg_1,
atl => atl_1,
att => att_1,
mla => mla_1,
lsb => lsb_1,
spa => spa_1,
ppr => ppr_1,
sreq => sreq_1,
isLocal => isLocal_1,
currentSecAddr => currentSecAddr_1,
DI => DO,
DO => DI_1,
output_valid => output_valid_1,
ATN_in => ATN,
ATN_out => ATN_1,
DAV_in => DAV,
DAV_out => DAV_1,
NRFD_in => NRFD,
NRFD_out => NRFD_1,
NDAC_in => NDAC,
NDAC_out => NDAC_1,
EOI_in => EOI,
EOI_out => EOI_1,
SRQ_in => SRQ,
SRQ_out => SRQ_1,
IFC_in => IFC,
IFC_out => IFC_1,
REN_in => REN,
REN_out => REN_1
);
-- Instantiate the Unit Under Test (UUT)
gpib2: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00010",
myTalkAddr => "00010",
secAddrMask => (others => '0'),
data => data_2,
status_byte => status_byte_2,
T1 => T1,
rdy => rdy_2,
nba => nba_2,
ltn => ltn_2,
lun => lun_2,
lon => lon_2,
ton => ton_2,
endOf => endOf_2,
gts => gts_2,
rpp => rpp_2,
tcs => tcs_2,
tca => tca_2,
sic => sic_2,
rsc => rsc_2,
sre => sre_2,
rtl => rtl_2,
rsv => rsv_2,
ist => ist_2,
lpe => lpe_2,
dvd => dvd_2,
wnc => wnc_2,
tac => tac_2,
cwrc => cwrc_2,
cwrd => cwrd_2,
clr => clr_2,
trg => trg_2,
atl => atl_2,
att => att_2,
mla => mla_2,
lsb => lsb_2,
spa => spa_2,
ppr => ppr_2,
sreq => sreq_2,
isLocal => isLocal_2,
currentSecAddr => currentSecAddr_2,
DI => DO,
DO => DI_2,
output_valid => output_valid_2,
ATN_in => ATN,
ATN_out => ATN_2,
DAV_in => DAV,
DAV_out => DAV_2,
NRFD_in => NRFD,
NRFD_out => NRFD_2,
NDAC_in => NDAC,
NDAC_out => NDAC_2,
EOI_in => EOI,
EOI_out => EOI_2,
SRQ_in => SRQ,
SRQ_out => SRQ_2,
IFC_in => IFC,
IFC_out => IFC_2,
REN_in => REN,
REN_out => REN_2
);
ce: gpibCableEmulator port map (
-- interface signals
DIO_1 => DI_1,
output_valid_1 => output_valid_1,
DIO_2 => DI_2,
output_valid_2 => output_valid_2,
DIO => DO,
-- attention
ATN_1 => ATN_1, ATN_2 => ATN_2, ATN => ATN,
DAV_1 => DAV_1, DAV_2 => DAV_2, DAV => DAV,
NRFD_1 => NRFD_1, NRFD_2 => NRFD_2, NRFD => NRFD,
NDAC_1 => NDAC_1, NDAC_2 => NDAC_2, NDAC => NDAC,
EOI_1 => EOI_1, EOI_2 => EOI_2, EOI => EOI,
SRQ_1 => SRQ_1, SRQ_2 => SRQ_2, SRQ => SRQ,
IFC_1 => IFC_1, IFC_2 => IFC_2, IFC => IFC,
REN_1 => REN_1, REN_2 => REN_2, REN => REN
);
gr: gpibReader generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_in => DO, dvd => dvd_2, atl => atl_2, lsb => lsb_2, rdy => rdy_2,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isLE => '0', secAddr => (others => '0'), dataSecAddr => dataSecAddr,
buf_interrupt => buf_interrupt, data_available => data_available,
last_byte_addr => last_byte_addr, end_of_stream => end_of_stream,
byte_addr => byte_addr, data_out => data_out,
reset_buffer => reset_buffer
);
w_data_in <= w_write_buffer(conv_integer(w_byte_addr));
gw: gpibWriter generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_out => data_1, wnc => wnc_1, spa => spa_1, nba => nba_1,
endOf => endOf_1, att => att_1, cwrc => cwrc_1,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isTE => '0', secAddr => (others => '0'), dataSecAddr => (others => '0'),
last_byte_addr => w_last_byte_addr, end_of_stream => w_end_of_stream,
data_available => w_data_available, buf_interrupt => w_buf_interrupt,
data_in => w_data_in, byte_addr => w_byte_addr,
reset_buffer => w_reset_buffer
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 10 clock periods.
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*10;
-- requests system control
rsc_1 <= '1';
-- interface clear
sic_1 <= '1';
wait until IFC_1 = '1';
sic_1 <= '0';
wait until IFC_1 = '0';
assert isLocal_1 = '1';
assert isLocal_2 = '1';
assert REN = '0';
sre_1 <= '1';
wait until REN = '1';
assert isLocal_1 = '1';
assert isLocal_2 = '1';
assert REN = '1';
-- gpib2 to listen
w_write_buffer(0) <= "00100010";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt='1';
assert isLocal_1 = '1';
assert isLocal_2 = '0';
assert REN = '1';
rtl_2 <= '1';
wait until isLocal_2 = '1';
assert isLocal_2 = '1';
w_reset_buffer <= '1';
wait for clk_period*2;
w_reset_buffer <= '0';
-- send LLO (local lockout)
w_write_buffer(0) <= "10010001";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt='1';
assert isLocal_2 = '1';
w_reset_buffer <= '1';
wait for clk_period*2;
w_reset_buffer <= '0';
-- gpib2 to listen
w_write_buffer(0) <= "00100010";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt='1';
assert isLocal_2 = '0';
w_reset_buffer <= '1';
wait for clk_period*2;
w_reset_buffer <= '0';
-- send GTL (go to local)
w_write_buffer(0) <= "00000001";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt='1';
assert isLocal_2 = '1';
w_reset_buffer <= '1';
wait for clk_period*2;
w_reset_buffer <= '0';
-- gpib2 to listen
w_write_buffer(0) <= "00100010";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt='1';
assert isLocal_2 = '0';
sre_1 <= '0';
wait until REN = '0';
wait for clk_period*5;
assert isLocal_2 = '1';
report "$$$ END OF TEST - remote / local $$$";
wait;
end process;
END;
| gpl-3.0 | b849443c98eb78542424b64c5962f2e0 | 0.561411 | 2.862749 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/system_debug_module_wrapper.vhd | 1 | 39,146 | -------------------------------------------------------------------------------
-- system_debug_module_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library mdm_v2_10_a;
use mdm_v2_10_a.all;
entity system_debug_module_wrapper is
port (
Interrupt : out std_logic;
Debug_SYS_Rst : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 31);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 7);
Sl_MWrErr : out std_logic_vector(0 to 7);
Sl_MRdErr : out std_logic_vector(0 to 7);
Sl_MIRQ : out std_logic_vector(0 to 7);
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
bscan_tdi : out std_logic;
bscan_reset : out std_logic;
bscan_shift : out std_logic;
bscan_update : out std_logic;
bscan_capture : out std_logic;
bscan_sel1 : out std_logic;
bscan_drck1 : out std_logic;
bscan_tdo1 : in std_logic;
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_debug_module_wrapper : entity is "mdm_v2_10_a";
end system_debug_module_wrapper;
architecture STRUCTURE of system_debug_module_wrapper is
component mdm is
generic (
C_FAMILY : STRING;
C_JTAG_CHAIN : INTEGER;
C_INTERCONNECT : INTEGER;
C_BASEADDR : STD_LOGIC_VECTOR;
C_HIGHADDR : STD_LOGIC_VECTOR;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_MB_DBG_PORTS : INTEGER;
C_USE_UART : INTEGER;
C_USE_BSCAN : integer;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER
);
port (
Interrupt : out std_logic;
Debug_SYS_Rst : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
bscan_tdi : out std_logic;
bscan_reset : out std_logic;
bscan_shift : out std_logic;
bscan_update : out std_logic;
bscan_capture : out std_logic;
bscan_sel1 : out std_logic;
bscan_drck1 : out std_logic;
bscan_tdo1 : in std_logic;
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component;
begin
debug_module : mdm
generic map (
C_FAMILY => "spartan6",
C_JTAG_CHAIN => 2,
C_INTERCONNECT => 2,
C_BASEADDR => X"41400000",
C_HIGHADDR => X"4140ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 32,
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 3,
C_SPLB_NUM_MASTERS => 8,
C_SPLB_NATIVE_DWIDTH => 32,
C_SPLB_SUPPORT_BURSTS => 0,
C_MB_DBG_PORTS => 1,
C_USE_UART => 1,
C_USE_BSCAN => 0,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_DATA_WIDTH => 32
)
port map (
Interrupt => Interrupt,
Debug_SYS_Rst => Debug_SYS_Rst,
Ext_BRK => Ext_BRK,
Ext_NM_BRK => Ext_NM_BRK,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Dbg_Clk_0 => Dbg_Clk_0,
Dbg_TDI_0 => Dbg_TDI_0,
Dbg_TDO_0 => Dbg_TDO_0,
Dbg_Reg_En_0 => Dbg_Reg_En_0,
Dbg_Capture_0 => Dbg_Capture_0,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_Update_0 => Dbg_Update_0,
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Clk_1 => Dbg_Clk_1,
Dbg_TDI_1 => Dbg_TDI_1,
Dbg_TDO_1 => Dbg_TDO_1,
Dbg_Reg_En_1 => Dbg_Reg_En_1,
Dbg_Capture_1 => Dbg_Capture_1,
Dbg_Shift_1 => Dbg_Shift_1,
Dbg_Update_1 => Dbg_Update_1,
Dbg_Rst_1 => Dbg_Rst_1,
Dbg_Clk_2 => Dbg_Clk_2,
Dbg_TDI_2 => Dbg_TDI_2,
Dbg_TDO_2 => Dbg_TDO_2,
Dbg_Reg_En_2 => Dbg_Reg_En_2,
Dbg_Capture_2 => Dbg_Capture_2,
Dbg_Shift_2 => Dbg_Shift_2,
Dbg_Update_2 => Dbg_Update_2,
Dbg_Rst_2 => Dbg_Rst_2,
Dbg_Clk_3 => Dbg_Clk_3,
Dbg_TDI_3 => Dbg_TDI_3,
Dbg_TDO_3 => Dbg_TDO_3,
Dbg_Reg_En_3 => Dbg_Reg_En_3,
Dbg_Capture_3 => Dbg_Capture_3,
Dbg_Shift_3 => Dbg_Shift_3,
Dbg_Update_3 => Dbg_Update_3,
Dbg_Rst_3 => Dbg_Rst_3,
Dbg_Clk_4 => Dbg_Clk_4,
Dbg_TDI_4 => Dbg_TDI_4,
Dbg_TDO_4 => Dbg_TDO_4,
Dbg_Reg_En_4 => Dbg_Reg_En_4,
Dbg_Capture_4 => Dbg_Capture_4,
Dbg_Shift_4 => Dbg_Shift_4,
Dbg_Update_4 => Dbg_Update_4,
Dbg_Rst_4 => Dbg_Rst_4,
Dbg_Clk_5 => Dbg_Clk_5,
Dbg_TDI_5 => Dbg_TDI_5,
Dbg_TDO_5 => Dbg_TDO_5,
Dbg_Reg_En_5 => Dbg_Reg_En_5,
Dbg_Capture_5 => Dbg_Capture_5,
Dbg_Shift_5 => Dbg_Shift_5,
Dbg_Update_5 => Dbg_Update_5,
Dbg_Rst_5 => Dbg_Rst_5,
Dbg_Clk_6 => Dbg_Clk_6,
Dbg_TDI_6 => Dbg_TDI_6,
Dbg_TDO_6 => Dbg_TDO_6,
Dbg_Reg_En_6 => Dbg_Reg_En_6,
Dbg_Capture_6 => Dbg_Capture_6,
Dbg_Shift_6 => Dbg_Shift_6,
Dbg_Update_6 => Dbg_Update_6,
Dbg_Rst_6 => Dbg_Rst_6,
Dbg_Clk_7 => Dbg_Clk_7,
Dbg_TDI_7 => Dbg_TDI_7,
Dbg_TDO_7 => Dbg_TDO_7,
Dbg_Reg_En_7 => Dbg_Reg_En_7,
Dbg_Capture_7 => Dbg_Capture_7,
Dbg_Shift_7 => Dbg_Shift_7,
Dbg_Update_7 => Dbg_Update_7,
Dbg_Rst_7 => Dbg_Rst_7,
Dbg_Clk_8 => Dbg_Clk_8,
Dbg_TDI_8 => Dbg_TDI_8,
Dbg_TDO_8 => Dbg_TDO_8,
Dbg_Reg_En_8 => Dbg_Reg_En_8,
Dbg_Capture_8 => Dbg_Capture_8,
Dbg_Shift_8 => Dbg_Shift_8,
Dbg_Update_8 => Dbg_Update_8,
Dbg_Rst_8 => Dbg_Rst_8,
Dbg_Clk_9 => Dbg_Clk_9,
Dbg_TDI_9 => Dbg_TDI_9,
Dbg_TDO_9 => Dbg_TDO_9,
Dbg_Reg_En_9 => Dbg_Reg_En_9,
Dbg_Capture_9 => Dbg_Capture_9,
Dbg_Shift_9 => Dbg_Shift_9,
Dbg_Update_9 => Dbg_Update_9,
Dbg_Rst_9 => Dbg_Rst_9,
Dbg_Clk_10 => Dbg_Clk_10,
Dbg_TDI_10 => Dbg_TDI_10,
Dbg_TDO_10 => Dbg_TDO_10,
Dbg_Reg_En_10 => Dbg_Reg_En_10,
Dbg_Capture_10 => Dbg_Capture_10,
Dbg_Shift_10 => Dbg_Shift_10,
Dbg_Update_10 => Dbg_Update_10,
Dbg_Rst_10 => Dbg_Rst_10,
Dbg_Clk_11 => Dbg_Clk_11,
Dbg_TDI_11 => Dbg_TDI_11,
Dbg_TDO_11 => Dbg_TDO_11,
Dbg_Reg_En_11 => Dbg_Reg_En_11,
Dbg_Capture_11 => Dbg_Capture_11,
Dbg_Shift_11 => Dbg_Shift_11,
Dbg_Update_11 => Dbg_Update_11,
Dbg_Rst_11 => Dbg_Rst_11,
Dbg_Clk_12 => Dbg_Clk_12,
Dbg_TDI_12 => Dbg_TDI_12,
Dbg_TDO_12 => Dbg_TDO_12,
Dbg_Reg_En_12 => Dbg_Reg_En_12,
Dbg_Capture_12 => Dbg_Capture_12,
Dbg_Shift_12 => Dbg_Shift_12,
Dbg_Update_12 => Dbg_Update_12,
Dbg_Rst_12 => Dbg_Rst_12,
Dbg_Clk_13 => Dbg_Clk_13,
Dbg_TDI_13 => Dbg_TDI_13,
Dbg_TDO_13 => Dbg_TDO_13,
Dbg_Reg_En_13 => Dbg_Reg_En_13,
Dbg_Capture_13 => Dbg_Capture_13,
Dbg_Shift_13 => Dbg_Shift_13,
Dbg_Update_13 => Dbg_Update_13,
Dbg_Rst_13 => Dbg_Rst_13,
Dbg_Clk_14 => Dbg_Clk_14,
Dbg_TDI_14 => Dbg_TDI_14,
Dbg_TDO_14 => Dbg_TDO_14,
Dbg_Reg_En_14 => Dbg_Reg_En_14,
Dbg_Capture_14 => Dbg_Capture_14,
Dbg_Shift_14 => Dbg_Shift_14,
Dbg_Update_14 => Dbg_Update_14,
Dbg_Rst_14 => Dbg_Rst_14,
Dbg_Clk_15 => Dbg_Clk_15,
Dbg_TDI_15 => Dbg_TDI_15,
Dbg_TDO_15 => Dbg_TDO_15,
Dbg_Reg_En_15 => Dbg_Reg_En_15,
Dbg_Capture_15 => Dbg_Capture_15,
Dbg_Shift_15 => Dbg_Shift_15,
Dbg_Update_15 => Dbg_Update_15,
Dbg_Rst_15 => Dbg_Rst_15,
Dbg_Clk_16 => Dbg_Clk_16,
Dbg_TDI_16 => Dbg_TDI_16,
Dbg_TDO_16 => Dbg_TDO_16,
Dbg_Reg_En_16 => Dbg_Reg_En_16,
Dbg_Capture_16 => Dbg_Capture_16,
Dbg_Shift_16 => Dbg_Shift_16,
Dbg_Update_16 => Dbg_Update_16,
Dbg_Rst_16 => Dbg_Rst_16,
Dbg_Clk_17 => Dbg_Clk_17,
Dbg_TDI_17 => Dbg_TDI_17,
Dbg_TDO_17 => Dbg_TDO_17,
Dbg_Reg_En_17 => Dbg_Reg_En_17,
Dbg_Capture_17 => Dbg_Capture_17,
Dbg_Shift_17 => Dbg_Shift_17,
Dbg_Update_17 => Dbg_Update_17,
Dbg_Rst_17 => Dbg_Rst_17,
Dbg_Clk_18 => Dbg_Clk_18,
Dbg_TDI_18 => Dbg_TDI_18,
Dbg_TDO_18 => Dbg_TDO_18,
Dbg_Reg_En_18 => Dbg_Reg_En_18,
Dbg_Capture_18 => Dbg_Capture_18,
Dbg_Shift_18 => Dbg_Shift_18,
Dbg_Update_18 => Dbg_Update_18,
Dbg_Rst_18 => Dbg_Rst_18,
Dbg_Clk_19 => Dbg_Clk_19,
Dbg_TDI_19 => Dbg_TDI_19,
Dbg_TDO_19 => Dbg_TDO_19,
Dbg_Reg_En_19 => Dbg_Reg_En_19,
Dbg_Capture_19 => Dbg_Capture_19,
Dbg_Shift_19 => Dbg_Shift_19,
Dbg_Update_19 => Dbg_Update_19,
Dbg_Rst_19 => Dbg_Rst_19,
Dbg_Clk_20 => Dbg_Clk_20,
Dbg_TDI_20 => Dbg_TDI_20,
Dbg_TDO_20 => Dbg_TDO_20,
Dbg_Reg_En_20 => Dbg_Reg_En_20,
Dbg_Capture_20 => Dbg_Capture_20,
Dbg_Shift_20 => Dbg_Shift_20,
Dbg_Update_20 => Dbg_Update_20,
Dbg_Rst_20 => Dbg_Rst_20,
Dbg_Clk_21 => Dbg_Clk_21,
Dbg_TDI_21 => Dbg_TDI_21,
Dbg_TDO_21 => Dbg_TDO_21,
Dbg_Reg_En_21 => Dbg_Reg_En_21,
Dbg_Capture_21 => Dbg_Capture_21,
Dbg_Shift_21 => Dbg_Shift_21,
Dbg_Update_21 => Dbg_Update_21,
Dbg_Rst_21 => Dbg_Rst_21,
Dbg_Clk_22 => Dbg_Clk_22,
Dbg_TDI_22 => Dbg_TDI_22,
Dbg_TDO_22 => Dbg_TDO_22,
Dbg_Reg_En_22 => Dbg_Reg_En_22,
Dbg_Capture_22 => Dbg_Capture_22,
Dbg_Shift_22 => Dbg_Shift_22,
Dbg_Update_22 => Dbg_Update_22,
Dbg_Rst_22 => Dbg_Rst_22,
Dbg_Clk_23 => Dbg_Clk_23,
Dbg_TDI_23 => Dbg_TDI_23,
Dbg_TDO_23 => Dbg_TDO_23,
Dbg_Reg_En_23 => Dbg_Reg_En_23,
Dbg_Capture_23 => Dbg_Capture_23,
Dbg_Shift_23 => Dbg_Shift_23,
Dbg_Update_23 => Dbg_Update_23,
Dbg_Rst_23 => Dbg_Rst_23,
Dbg_Clk_24 => Dbg_Clk_24,
Dbg_TDI_24 => Dbg_TDI_24,
Dbg_TDO_24 => Dbg_TDO_24,
Dbg_Reg_En_24 => Dbg_Reg_En_24,
Dbg_Capture_24 => Dbg_Capture_24,
Dbg_Shift_24 => Dbg_Shift_24,
Dbg_Update_24 => Dbg_Update_24,
Dbg_Rst_24 => Dbg_Rst_24,
Dbg_Clk_25 => Dbg_Clk_25,
Dbg_TDI_25 => Dbg_TDI_25,
Dbg_TDO_25 => Dbg_TDO_25,
Dbg_Reg_En_25 => Dbg_Reg_En_25,
Dbg_Capture_25 => Dbg_Capture_25,
Dbg_Shift_25 => Dbg_Shift_25,
Dbg_Update_25 => Dbg_Update_25,
Dbg_Rst_25 => Dbg_Rst_25,
Dbg_Clk_26 => Dbg_Clk_26,
Dbg_TDI_26 => Dbg_TDI_26,
Dbg_TDO_26 => Dbg_TDO_26,
Dbg_Reg_En_26 => Dbg_Reg_En_26,
Dbg_Capture_26 => Dbg_Capture_26,
Dbg_Shift_26 => Dbg_Shift_26,
Dbg_Update_26 => Dbg_Update_26,
Dbg_Rst_26 => Dbg_Rst_26,
Dbg_Clk_27 => Dbg_Clk_27,
Dbg_TDI_27 => Dbg_TDI_27,
Dbg_TDO_27 => Dbg_TDO_27,
Dbg_Reg_En_27 => Dbg_Reg_En_27,
Dbg_Capture_27 => Dbg_Capture_27,
Dbg_Shift_27 => Dbg_Shift_27,
Dbg_Update_27 => Dbg_Update_27,
Dbg_Rst_27 => Dbg_Rst_27,
Dbg_Clk_28 => Dbg_Clk_28,
Dbg_TDI_28 => Dbg_TDI_28,
Dbg_TDO_28 => Dbg_TDO_28,
Dbg_Reg_En_28 => Dbg_Reg_En_28,
Dbg_Capture_28 => Dbg_Capture_28,
Dbg_Shift_28 => Dbg_Shift_28,
Dbg_Update_28 => Dbg_Update_28,
Dbg_Rst_28 => Dbg_Rst_28,
Dbg_Clk_29 => Dbg_Clk_29,
Dbg_TDI_29 => Dbg_TDI_29,
Dbg_TDO_29 => Dbg_TDO_29,
Dbg_Reg_En_29 => Dbg_Reg_En_29,
Dbg_Capture_29 => Dbg_Capture_29,
Dbg_Shift_29 => Dbg_Shift_29,
Dbg_Update_29 => Dbg_Update_29,
Dbg_Rst_29 => Dbg_Rst_29,
Dbg_Clk_30 => Dbg_Clk_30,
Dbg_TDI_30 => Dbg_TDI_30,
Dbg_TDO_30 => Dbg_TDO_30,
Dbg_Reg_En_30 => Dbg_Reg_En_30,
Dbg_Capture_30 => Dbg_Capture_30,
Dbg_Shift_30 => Dbg_Shift_30,
Dbg_Update_30 => Dbg_Update_30,
Dbg_Rst_30 => Dbg_Rst_30,
Dbg_Clk_31 => Dbg_Clk_31,
Dbg_TDI_31 => Dbg_TDI_31,
Dbg_TDO_31 => Dbg_TDO_31,
Dbg_Reg_En_31 => Dbg_Reg_En_31,
Dbg_Capture_31 => Dbg_Capture_31,
Dbg_Shift_31 => Dbg_Shift_31,
Dbg_Update_31 => Dbg_Update_31,
Dbg_Rst_31 => Dbg_Rst_31,
bscan_tdi => bscan_tdi,
bscan_reset => bscan_reset,
bscan_shift => bscan_shift,
bscan_update => bscan_update,
bscan_capture => bscan_capture,
bscan_sel1 => bscan_sel1,
bscan_drck1 => bscan_drck1,
bscan_tdo1 => bscan_tdo1,
bscan_ext_tdi => bscan_ext_tdi,
bscan_ext_reset => bscan_ext_reset,
bscan_ext_shift => bscan_ext_shift,
bscan_ext_update => bscan_ext_update,
bscan_ext_capture => bscan_ext_capture,
bscan_ext_sel => bscan_ext_sel,
bscan_ext_drck => bscan_ext_drck,
bscan_ext_tdo => bscan_ext_tdo,
Ext_JTAG_DRCK => Ext_JTAG_DRCK,
Ext_JTAG_RESET => Ext_JTAG_RESET,
Ext_JTAG_SEL => Ext_JTAG_SEL,
Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE,
Ext_JTAG_SHIFT => Ext_JTAG_SHIFT,
Ext_JTAG_UPDATE => Ext_JTAG_UPDATE,
Ext_JTAG_TDI => Ext_JTAG_TDI,
Ext_JTAG_TDO => Ext_JTAG_TDO
);
end architecture STRUCTURE;
| mit | 4feb1b7ff26b46f03e56632cec3c1c98 | 0.57633 | 2.803552 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib/gpibInterface.vhd | 1 | 14,830 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: gpibInterface
-- Date: 13:34 15/10/2011
-- Author: Andrzej Paluch
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.gpibComponents.all;
entity gpibInterface is
port (
clk : in std_logic;
reset : std_logic;
-- application interface
isLE : in std_logic;
isTE : in std_logic;
lpeUsed : in std_logic;
fixedPpLine : in std_logic_vector (2 downto 0);
eosUsed : in std_logic;
eosMark : in std_logic_vector (7 downto 0);
myListAddr : in std_logic_vector (4 downto 0);
myTalkAddr : in std_logic_vector (4 downto 0);
secAddrMask : in std_logic_vector (31 downto 0);
data : in std_logic_vector (7 downto 0);
status_byte : in std_logic_vector (7 downto 0);
T1 : in std_logic_vector (7 downto 0);
-- local commands to interface
rdy : in std_logic; -- ready for next message (AH)
nba : in std_logic; -- new byte available (SH)
ltn : in std_logic; -- listen (L, LE)
lun : in std_logic; -- local unlisten (L, LE)
lon : in std_logic; -- listen only (L, LE)
ton : in std_logic; -- talk only (T, TE)
endOf : in std_logic; -- end of byte string (T, TE)
gts : in std_logic; -- go to standby (C)
rpp : in std_logic; -- request parallel poll (C)
tcs : in std_logic; -- take control synchronously (C, AH)
tca : in std_logic; -- take control asynchronously (C)
sic : in std_logic; -- send interface clear (C)
rsc : in std_logic; -- request system control (C)
sre : in std_logic; -- send remote enable (C)
rtl : in std_logic; -- return to local (RL)
rsv : in std_logic; -- request service (SR)
ist : in std_logic; -- individual status (PP)
lpe : in std_logic; -- local poll enable (PP)
-- local commands from interface
dvd : out std_logic; -- data valid (AH)
wnc : out std_logic; -- wait for new cycle (SH)
tac : out std_logic; -- talker active (T, TE)
lac : out std_logic; -- listener active (L, LE)
cwrc : out std_logic; -- controller write commands
cwrd : out std_logic; -- controller write data
clr : out std_logic; -- clear device (DC)
trg : out std_logic; -- trigger device (DT)
atl : out std_logic; -- addressed to listen (T or TE)
att : out std_logic; -- addressed to talk(L or LE)
mla : out std_logic; -- my listen addres decoded (L or LE)
lsb : out std_logic; -- last byte
spa : out std_logic; -- seriall poll active
ppr : out std_logic; -- parallel poll ready
sreq : out std_logic; -- service requested
isLocal : out std_logic; -- device is local controlled
currentSecAddr : out std_logic_vector (4 downto 0); -- current sec addr
-- interface signals
DI : in std_logic_vector (7 downto 0);
DO : out std_logic_vector (7 downto 0);
output_valid : out std_logic;
-- attention
ATN_in : in std_logic;
ATN_out : out std_logic;
-- data valid
DAV_in : in std_logic;
DAV_out : out std_logic;
-- not ready for data
NRFD_in : in std_logic;
NRFD_out : out std_logic;
-- no data accepted
NDAC_in : in std_logic;
NDAC_out : out std_logic;
-- end or identify
EOI_in : in std_logic;
EOI_out : out std_logic;
-- service request
SRQ_in : in std_logic;
SRQ_out : out std_logic;
-- interface clear
IFC_in : in std_logic;
IFC_out : out std_logic;
-- remote enable
REN_in : in std_logic;
REN_out : out std_logic
;debug1 : out std_logic
);
end gpibInterface;
architecture Behavioral of gpibInterface is
-- function states
signal LACS, LADS, SPAS, TACS, CACS, CSBS, CPPS, CTRS, CSRS, SACS, ACDS,
TPAS, APRS, LPAS, TADS, ANRS, STRS, SDYS, PPAS, LOCS, LWLS : std_logic;
-- decoded remote commands
signal ATN_dec, DAC_dec, DAV_dec, END_c_dec, IDY_dec, IFC_dec, REN_dec,
RFD_dec, SRQ_dec : std_logic;
signal ACG_dec, DAB_dec, DCL_dec, EOS_dec, GET_dec, GTL_dec, LAG_dec,
LLO_dec, MLA_dec, MTA_dec, MSA_dec, NUL_dec, OSA_dec, OTA_dec, PCG_dec,
PPC_dec, PPE_dec, PPD_dec, PPR_dec, PPU_dec, RQS_dec, SCG_dec, SDC_dec,
SPD_dec, SPE_dec, STB_dec, TAG_dec, TCT_dec, UCG_dec, UNL_dec,
UNT_dec : std_logic;
-- encoded remote commands
signal ATN_enc, DAC_enc, RFD_enc, DAV_enc, END_OF_enc, IFC_enc, IDY_enc,
REN_enc, RQS_enc, DAB_enc, EOS_enc, STB_enc, TCT_enc, SRQ_enc,
PPR_enc : std_logic;
-- PPR command data
signal ppBitValue : std_logic;
signal ppLineNumber : std_logic_vector (2 downto 0);
-- internal signals
signal secAddrDetected : std_logic;
begin
dvd <= ACDS;
cwrc <= CACS;
cwrd <= CSBS;
atl <= LADS or LACS;
lac <= LACS;
att <= TACS or TADS or SPAS;
mla <= MLA_dec;
lsb <= ((eosUsed and EOS_dec) or END_c_dec) and ACDS; -- dvd = ACDS
spa <= SPAS;
ppr <= CPPS;
sreq <= CSRS and SACS;
isLocal <= LOCS or LWLS;
-- acceptor handshake
AH: if_func_AH port map(
clk => clk,
-----------------------------------------------------------------------
pon => reset, rdy => rdy, tcs => tcs,
-----------------------------------------------------------------------
LACS => LACS, LADS => LADS,
-----------------------------------------------------------------------
ATN => ATN_dec, DAV => DAV_dec,
-----------------------------------------------------------------------
RFD => RFD_enc, DAC=> DAC_enc,
-----------------------------------------------------------------------
ANRS => ANRS, ACDS => ACDS
);
-- source handshake
SH: if_func_SH port map(
clk => clk,
-----------------------------------------------------------------------
T1 => T1,
-----------------------------------------------------------------------
pon => reset, nba => nba,
-----------------------------------------------------------------------
TACS => TACS, SPAS => SPAS, CACS => CACS, CTRS => CTRS,
-----------------------------------------------------------------------
ATN => ATN_dec, DAC => DAC_dec, RFD => RFD_dec,
-----------------------------------------------------------------------
DAV => DAV_enc,
-----------------------------------------------------------------------
wnc => wnc,
-----------------------------------------------------------------------
STRS => STRS, SDYS => SDYS
);
-- listener, extended listener
L_LE: if_func_L_LE port map(
clk => clk,
-----------------------------------------------------------------------
isLE => isLE,
-----------------------------------------------------------------------
pon => reset, ltn => ltn, lun => lun, lon => lon,
-----------------------------------------------------------------------
ACDS => ACDS, CACS => CACS, TPAS => TPAS,
-----------------------------------------------------------------------
ATN => ATN_dec, IFC => IFC_dec, MLA => MLA_dec, MTA => MTA_dec,
UNL => UNL_dec, PCG => PCG_dec, MSA => MSA_dec,
-----------------------------------------------------------------------
LACS => LACS, LADS => LADS, LPAS => LPAS, debug1 => debug1
);
-- talker, extended talker
T_TE: if_func_T_TE port map(
clk => clk,
-----------------------------------------------------------------------
isTE => isTE,
-----------------------------------------------------------------------
pon => reset, ton => ton, endOf => endOf,
-----------------------------------------------------------------------
ACDS => ACDS, APRS => APRS, LPAS => LPAS,
-----------------------------------------------------------------------
ATN => ATN_dec, IFC => IFC_dec, SPE => SPE_dec, SPD => SPD_dec,
MTA => MTA_dec, OTA => OTA_dec, MLA => MLA_dec, OSA => OSA_dec,
MSA => MSA_dec, PCG => PCG_dec,
-----------------------------------------------------------------------
END_OF => END_OF_enc, RQS => RQS_enc, DAB => DAB_enc, EOS => EOS_enc,
STB => STB_enc,
-----------------------------------------------------------------------
tac => tac,
-----------------------------------------------------------------------
SPAS => SPAS, TPAS => TPAS, TADS => TADS, TACS => TACS
);
-- controller
C: if_func_C port map(
clk => clk,
-----------------------------------------------------------------------
pon => reset, gts => gts, rpp => rpp, tcs => tcs, tca => tca,
sic => sic, rsc => rsc, sre => sre,
-----------------------------------------------------------------------
TADS => TADS, ACDS => ACDS, ANRS => ANRS, STRS => STRS, SDYS => SDYS,
-----------------------------------------------------------------------
ATN_in => ATN_dec, IFC_in => IFC_dec, TCT_in => TCT_dec,
SRQ_in => SRQ_dec,
-----------------------------------------------------------------------
ATN_out => ATN_enc, IFC_out => IFC_enc, TCT_out => TCT_enc,
IDY_out => IDY_enc, REN_out => REN_enc,
-----------------------------------------------------------------------
CACS => CACS, CTRS => CTRS, CSBS => CSBS, CPPS => CPPS, CSRS => CSRS,
SACS => SACS
);
-- device clear
DC: if_func_DC port map(
clk => clk,
-----------------------------------------------------------------------
LADS => LADS, ACDS => ACDS,
-----------------------------------------------------------------------
DCL => DCL_dec, SDC => SDC_dec,
-----------------------------------------------------------------------
clr => clr
);
-- device trigger
DT: if_func_DT port map(
clk => clk,
-----------------------------------------------------------------------
LADS => LADS, ACDS => ACDS,
-----------------------------------------------------------------------
GET => GET_dec,
-----------------------------------------------------------------------
trg => trg
);
PP: if_func_PP port map(
clk => clk,
-----------------------------------------------------------------------
lpeUsed => lpeUsed, fixedPpLine => fixedPpLine,
-----------------------------------------------------------------------
pon => reset, lpe => lpe, ist => ist,
-----------------------------------------------------------------------
ACDS => ACDS, LADS => LADS,
-----------------------------------------------------------------------
dio_data => DI(3 downto 0),
-----------------------------------------------------------------------
IDY => IDY_dec, PPE => PPE_dec, PPD => PPD_dec, PPC => PPC_dec,
PPU => PPU_dec, PCG => PCG_dec,
-----------------------------------------------------------------------
PPR => PPR_enc, ppBitValue => ppBitValue, ppLineNumber => ppLineNumber,
-----------------------------------------------------------------------
PPAS => PPAS
);
RL: if_func_RL port map(
clk => clk,
-----------------------------------------------------------------------
pon => reset, rtl => rtl,
-----------------------------------------------------------------------
ACDS => ACDS, LADS => LADS,
-----------------------------------------------------------------------
REN => REN_dec, LLO => LLO_dec, MLA => MLA_dec, GTL => GTL_dec,
-----------------------------------------------------------------------
LOCS => LOCS, LWLS => LWLS
);
SR: if_func_SR port map(
clk => clk,
-----------------------------------------------------------------------
pon => reset, rsv => rsv,
-----------------------------------------------------------------------
SPAS => SPAS,
-----------------------------------------------------------------------
SRQ => SRQ_enc,
-----------------------------------------------------------------------
APRS => APRS
);
COMM_ENC: commandEcoder port map (
data => data, status_byte => status_byte,
-------------------------------------------------------------------
ppBitValue => ppBitValue, ppLineNumber => ppLineNumber,
-------------------------------------------------------------------
APRS => APRS, CACS => CACS,
-------------------------------------------------------------------
ATN => ATN_enc, END_OF => END_OF_enc, IDY => IDY_enc,
DAC => DAC_enc, RFD => RFD_enc, DAV => DAV_enc, IFC => IFC_enc,
REN => REN_enc, SRQ => SRQ_enc, DAB => DAB_enc, EOS => EOS_enc,
RQS => RQS_enc, STB => STB_enc, TCT => TCT_enc, PPR => PPR_enc,
-------------------------------------------------------------------
DO => DO, output_valid => output_valid,
-------------------------------------------------------------------
DAV_line => DAV_out, NRFD_line => NRFD_out, NDAC_line => NDAC_out,
ATN_line => ATN_out, EOI_line => EOI_out, SRQ_line => SRQ_out,
IFC_line => IFC_out, REN_line => REN_out
);
-- command decoder
COMM_DEC: commandDecoder port map (
DI => DI, DAV_line => DAV_in, NRFD_line => NRFD_in,
NDAC_line => NDAC_in, ATN_line => ATN_in, EOI_line => EOI_in,
SRQ_line => SRQ_in, IFC_line => IFC_in, REN_line => REN_in,
-----------------------------------------------------------------------
eosMark => eosMark, eosUsed =>eosUsed, myListAddr => myListAddr,
myTalkAddr => myTalkAddr, secAddrDetected => secAddrDetected,
-----------------------------------------------------------------------
SPAS => SPAS,
-----------------------------------------------------------------------
ATN => ATN_dec, DAC => DAC_dec, DAV => DAV_dec, END_c => END_c_dec,
IDY => IDY_dec, IFC => IFC_dec, REN => REN_dec, RFD => RFD_dec,
SRQ => SRQ_dec,
-----------------------------------------------------------------------
ACG => ACG_dec, DAB => DAB_dec, DCL => DCL_dec, EOS => EOS_dec,
GET => GET_dec, GTL => GTL_dec, LAG => LAG_dec, LLO => LLO_dec,
MLA => MLA_dec, MTA => MTA_dec, MSA => MSA_dec, NUL => NUL_dec,
OSA => OSA_dec, OTA => OTA_dec, PCG => PCG_dec, PPC => PPC_dec,
PPE => PPE_dec, PPD => PPD_dec, PPR => PPR_dec, PPU => PPU_dec,
RQS => RQS_dec, SCG => SCG_dec, SDC => SDC_dec, SPD => SPD_dec,
SPE => SPE_dec, STB => STB_dec, TAG => TAG_dec, TCT => TCT_dec,
UCG => UCG_dec, UNL => UNL_dec, UNT => UNT_dec
);
SECAD: SecondaryAddressDecoder port map (
secAddrMask => secAddrMask, DI => DI(4 downto 0),
secAddrDetected => secAddrDetected
);
SECADS: SecAddrSaver port map (
reset => reset,
TADS => TADS, TPAS => TPAS, LADS => LADS, LPAS => LPAS,
MSA_Dec => MSA_Dec, DI => DI(4 downto 0),
currentSecAddr => currentSecAddr
);
end Behavioral;
| gpl-3.0 | 9a60e0f606f19e2557655df460e3e338 | 0.427714 | 3.862985 | false | false | false | false |
pavsa/hackrf-spectrum-analyzer | src/hackrf-sweep/lib/hackrf/firmware/cpld/sgpio_if/top_tb.vhd | 19 | 3,604 | --
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY top_tb IS
END top_tb;
ARCHITECTURE behavior OF top_tb IS
COMPONENT top
PORT(
HOST_DATA : INOUT std_logic_vector(7 downto 0);
HOST_CAPTURE : OUT std_logic;
HOST_DISABLE : IN std_logic;
HOST_DIRECTION : IN std_logic;
HOST_DECIM_SEL : IN std_logic_vector(2 downto 0);
DA : IN std_logic_vector(7 downto 0);
DD : OUT std_logic_vector(9 downto 0);
CODEC_CLK : IN std_logic;
CODEC_X2_CLK : IN std_logic
);
END COMPONENT;
--Inputs
signal DA : std_logic_vector(7 downto 0) := (others => '0');
signal CODEC_CLK : std_logic := '0';
signal CODEC_X2_CLK : std_logic := '0';
signal HOST_DISABLE : std_logic := '1';
signal HOST_DIRECTION : std_logic := '0';
signal HOST_DECIM_SEL : std_logic_vector(2 downto 0) := "010";
--BiDirs
signal HOST_DATA : std_logic_vector(7 downto 0);
--Outputs
signal DD : std_logic_vector(9 downto 0);
signal HOST_CAPTURE : std_logic;
begin
uut: top PORT MAP (
HOST_DATA => HOST_DATA,
HOST_CAPTURE => HOST_CAPTURE,
HOST_DISABLE => HOST_DISABLE,
HOST_DIRECTION => HOST_DIRECTION,
HOST_DECIM_SEL => HOST_DECIM_SEL,
DA => DA,
DD => DD,
CODEC_CLK => CODEC_CLK,
CODEC_X2_CLK => CODEC_X2_CLK
);
clk_process :process
begin
CODEC_CLK <= '1';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
CODEC_CLK <= '0';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
end process;
adc_proc: process
begin
wait until rising_edge(CODEC_CLK);
wait for 9 ns;
DA <= "00000000";
wait until falling_edge(CODEC_CLK);
wait for 9 ns;
DA <= "00000001";
end process;
sgpio_proc: process
begin
HOST_DATA <= (others => 'Z');
HOST_DIRECTION <= '0';
HOST_DISABLE <= '1';
wait for 135 ns;
HOST_DISABLE <= '0';
wait for 1000 ns;
HOST_DISABLE <= '1';
wait for 100 ns;
HOST_DIRECTION <= '1';
wait for 100 ns;
HOST_DISABLE <= '0';
for i in 0 to 10 loop
HOST_DATA <= (others => '0');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
HOST_DATA <= (others => '1');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
end loop;
wait;
end process;
end;
| gpl-3.0 | f5adc7c38e474d36c17b7df1bb4dfb56 | 0.545505 | 3.738589 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-2/test_bench_sign_extend.vhd | 1 | 810 | library IEEE;
use ieee.std_logic_1164.all;
entity test_bench_sign_extend is
end test_bench_sign_extend;
architecture behav of test_bench_sign_extend is
component sign_extend
port(
instr15_0 : in std_logic_vector(15 downto 0);
clk, rst, pre, ce : in std_logic;
output : out std_logic_vector(31 downto 0));
end component;
--Inputs
signal instr15_0 : std_logic_vector(15 downto 0) := (others => '0');
signal clk, rst, pre, ce : std_logic :='0';
--Outputs
signal output : std_logic_vector(31 downto 0);
begin
test_bench: sign_extend port map(
instr15_0 => instr15_0,
clk => clk,
rst => rst,
pre => pre,
ce => ce,
output => output
);
stim_proc: process
begin
wait for 50 ns;
instr15_0 <= "0110000000011111";
clk <= '1';
rst <= '0';
pre <= '0';
ce <= '1';
wait;
end process;
end; | gpl-3.0 | a2cec975b06f988c803d1409b53a8286 | 0.653086 | 2.682119 | false | true | false | false |
Nooxet/embedded_bruteforce | brutus_system/pcores/myvga_v1_00_a/hdl/vhdl/myvga.vhd | 1 | 3,137 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity myvga is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
-- DO NOT EDIT ABOVE THIS LINE ---------------------
hsync : out std_logic;
vsync : out std_logic;
gr : out std_logic_vector(2 downto 0);
re : out std_logic_vector(2 downto 0);
bl : out std_logic_vector(1 downto 0)
);
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
attribute SIGIS of FSL_S_Clk : signal is "Clk";
end myvga;
architecture EXAMPLE of myvga is
constant hpixels : unsigned(9 downto 0) := "1100100000"; -- 800
constant vlines : unsigned(9 downto 0) := "1000001101"; -- 525
constant hbp : unsigned(9 downto 0) := "0010010000"; -- 144 backp h
constant hfp: unsigned(9 downto 0) := "1100010000"; -- 784 frontp h
constant vbp : unsigned(9 downto 0) := "0000011111"; -- 31 backp v
constant vfp : unsigned(9 downto 0) := "0111111111"; -- 511 frontp v
signal clk_div_c, clk_div_n : unsigned(1 downto 0); -- mod 4
signal h_count_c, h_count_n, v_count_c, v_count_n : unsigned(9 downto 0);
signal vsenable : std_logic; -- enable for vertical count
signal vidon : std_logic;
begin
FSL_S_Read <= '0';
clk_proc: process(FSL_Clk) is
begin
if FSL_Clk'event and FSL_Clk = '1' then
if FSL_Rst = '1' then
clk_div_c <= (others => '0');
h_count_c <= (others => '0');
v_count_c <= (others => '0');
else
clk_div_c <= clk_div_n;
h_count_c <= h_count_n;
v_count_c <= v_count_n;
end if;
end if;
end process;
clk_div_proc: process(clk_div_c)
begin
clk_div_n <= clk_div_c + 1;
if clk_div_c = 3 then
clk_div_n <= (others => '0');
end if;
end process;
h_proc: process(clk_div_c, h_count_c)
begin
vsenable <= '0';
h_count_n <= h_count_c;
if (clk_div_c = 3) then
h_count_n <= h_count_c + 1;
if h_count_c = hpixels - 1 then
h_count_n <= (others => '0');
vsenable <= '1';
end if;
end if;
end process;
hsync <= '0' when h_count_c < 96 else '1';
v_proc: process(clk_div_c, vsenable, v_count_c)
begin
v_count_n <= v_count_c;
if (clk_div_c = 3 and vsenable = '1') then
v_count_n <= v_count_c + 1;
if v_count_c = vlines - 1 then
v_count_n <= (others => '0');
end if;
end if;
end process;
vsync <= '0' when v_count_c < 2 else '1';
vidon <= '1' when (((h_count_c < hfp) and (h_count_c >= hbp)) and ((v_count_c < vfp) and (v_count_c >= vbp))) else '0';
rgb_proc: process(vidon)
begin
gr <= (others => '0');
re <= (others => '0');
bl <= (others => '0');
if (vidon = '1') then
re <= "111";
end if;
end process;
--hsync <= '0' when (h_count_c >= (HD+HF)) and (h_count_c <= (HD+HF+HR-1)) else '1';
--vsync <= '0' when (v_count_c >= (VD+VF)) and (h_count_c <= (VD+VF+VR-1)) else '1';
end architecture EXAMPLE;
| mit | 8a71b89bae48a8f3f79daf2f3f34168a | 0.579535 | 2.592562 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/system_fsl_v20_0_wrapper.vhd | 1 | 2,827 | -------------------------------------------------------------------------------
-- system_fsl_v20_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library fsl_v20_v2_11_e;
use fsl_v20_v2_11_e.all;
entity system_fsl_v20_0_wrapper is
port (
FSL_Clk : in std_logic;
SYS_Rst : in std_logic;
FSL_Rst : out std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Data : in std_logic_vector(0 to 31);
FSL_M_Control : in std_logic;
FSL_M_Write : in std_logic;
FSL_M_Full : out std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Data : out std_logic_vector(0 to 31);
FSL_S_Control : out std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
FSL_Full : out std_logic;
FSL_Has_Data : out std_logic;
FSL_Control_IRQ : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_fsl_v20_0_wrapper : entity is "fsl_v20_v2_11_e";
end system_fsl_v20_0_wrapper;
architecture STRUCTURE of system_fsl_v20_0_wrapper is
component fsl_v20 is
generic (
C_EXT_RESET_HIGH : integer;
C_ASYNC_CLKS : integer;
C_IMPL_STYLE : integer;
C_USE_CONTROL : integer;
C_FSL_DWIDTH : integer;
C_FSL_DEPTH : integer;
C_READ_CLOCK_PERIOD : integer
);
port (
FSL_Clk : in std_logic;
SYS_Rst : in std_logic;
FSL_Rst : out std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_M_Control : in std_logic;
FSL_M_Write : in std_logic;
FSL_M_Full : out std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_S_Control : out std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
FSL_Full : out std_logic;
FSL_Has_Data : out std_logic;
FSL_Control_IRQ : out std_logic
);
end component;
begin
fsl_v20_0 : fsl_v20
generic map (
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 0,
C_USE_CONTROL => 1,
C_FSL_DWIDTH => 32,
C_FSL_DEPTH => 16,
C_READ_CLOCK_PERIOD => 0
)
port map (
FSL_Clk => FSL_Clk,
SYS_Rst => SYS_Rst,
FSL_Rst => FSL_Rst,
FSL_M_Clk => FSL_M_Clk,
FSL_M_Data => FSL_M_Data,
FSL_M_Control => FSL_M_Control,
FSL_M_Write => FSL_M_Write,
FSL_M_Full => FSL_M_Full,
FSL_S_Clk => FSL_S_Clk,
FSL_S_Data => FSL_S_Data,
FSL_S_Control => FSL_S_Control,
FSL_S_Read => FSL_S_Read,
FSL_S_Exists => FSL_S_Exists,
FSL_Full => FSL_Full,
FSL_Has_Data => FSL_Has_Data,
FSL_Control_IRQ => FSL_Control_IRQ
);
end architecture STRUCTURE;
| mit | 316aad07b810add718b9bf3c253ef180 | 0.552883 | 2.975789 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/min_search.vhd | 1 | 4,265 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: min_search - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity min_search is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
metric_in : in coord_type_ext;
u_in : in node_data_type;
point_in : in data_type;
point_idx_in : in centre_index_type;
min_point : out data_type;
min_index : out centre_index_type;
max_idx : out centre_index_type;
u_out : out node_data_type;
rdy : out std_logic
);
end min_search;
architecture Behavioral of min_search is
type state_type is (idle, processing, delaying, done);
signal state : state_type;
signal metric_in_reg : coord_type_ext;
signal point_in_reg : data_type;
signal point_idx_in_reg : centre_index_type;
signal current_smallest : std_logic;
signal tmp_min_metric : coord_type_ext;
signal tmp_min_index : centre_index_type;
signal tmp_min_point : data_type;
signal tmp_u_in : node_data_type;
signal counter : centre_index_type;
signal counter_reg : centre_index_type;
signal rdy_reg : std_logic;
signal rdy_sig : std_logic;
begin
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
state <= idle;
elsif state = idle AND nd='1' then
state <= processing;
tmp_u_in <= u_in; -- save the u_in input (a bit dirty)
elsif state = processing AND nd='0' then -- assume continuous streaming
state <= idle;
elsif state = done then
state <= idle;
end if;
end if;
end process fsm_proc;
-- need to delay by one cycle due to state machine
input_reg_proc : process(clk)
begin
if rising_edge(clk) then
metric_in_reg <= metric_in;
point_in_reg <= point_in;
point_idx_in_reg <= point_idx_in;
counter_reg <= counter;
end if;
end process input_reg_proc;
current_smallest <= '1' WHEN state = processing AND unsigned(metric_in_reg) < unsigned(tmp_min_metric) ELSE '0';
min_distance_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' OR state = idle OR state = done then
tmp_min_metric(COORD_BITWIDTH_EXT-1 downto 0) <= (others => '1'); --largest possible value (assume unsigned metrics)
tmp_min_index <= (others => '0');
else
if current_smallest = '1' then
tmp_min_metric <= metric_in_reg;
tmp_min_index <= point_idx_in_reg;--counter;
tmp_min_point <= point_in_reg;
end if;
end if;
end if;
end process min_distance_proc;
counter_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' OR state = idle OR state = done then
counter <= (others => '0');
else
counter <= counter+1;
end if;
end if;
end process counter_proc;
rdy_sig <= '1' WHEN state = processing AND nd='0' ELSE '0';
rdy_proc : process(clk)
begin
if rising_edge(clk) then
if sclr ='1' then
rdy_reg <= '0';
else
rdy_reg <= rdy_sig;
end if;
end if;
end process rdy_proc;
min_point <= tmp_min_point;
min_index <= tmp_min_index;
max_idx <= counter_reg;
rdy <= rdy_reg;
u_out <= tmp_u_in;
end Behavioral;
| bsd-3-clause | 13c9c8e7b1b766a577d7a469f8be5616 | 0.528019 | 3.978545 | false | false | false | false |
kb3gtn/mojo_modulator | vhdl/src/command_interface.vhd | 1 | 10,313 | -------------------------------------------------------------------------------
-- command interface
--
-- This module encapsulates a serial to databus interface for controlling
-- the FPGA design from a computer serial port.
--
-- Blocks encapsulated here..
--
-- RS232 UART
-- handles ttl rs232 stream on io pins, output/sends bytes of data
-- Connects to the uart_db_interface block
--
-- UART_DB_INTERFACE
-- handles serial byte stream commands into databus master commands
-- performs the state machinery to interface the uart to the databus
-- master command interface.
--
-- DATABUS_MASTER
-- this block is the master of the register memory maps system.
-- produces a 7 address bit (127 register) memory map of 8 bit registers.
-- Databus slaves with interface to the provided memory interface.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity command_interface is
port (
i_clk : in std_logic; -- databus clock
i_srst : in std_logic; -- sync reset to clock provided
-- Serial Interface ------------------------------------------
i_rx_serial_stream : in std_logic; -- received TTL rs232 stream
o_tx_serial_stream : out std_logic; -- transmit TTL rs232 stream
-- data bus interface to slave devices -----------------------
o_db_addr : out std_logic_vector( 6 downto 0); -- address bus (7 bits)
o_db_wdata : out std_logic_vector( 7 downto 0); -- write data
i_db_rdata : in std_logic_vector( 7 downto 0); -- read data
o_db_rstrb : out std_logic; -- db_read_strobe
o_db_wstrb : out std_logic -- db_write_strobe
);
end entity command_interface;
architecture system of command_interface is
---------------------------------------
-- Components
---------------------------------------
-- uart to receive/transmit data to/from a ttl rs232 serial stream
component uart is
port (
i_clk : in std_logic; -- system clock
i_srst : in std_logic; -- synchronious reset, 1 - active
i_baud_div : in std_logic_vector(15 downto 0); -- clk divider to get to baud rate
-- uart interface
o_uart_tx : out std_logic; -- tx bit stream
i_uart_rx : in std_logic; -- uart rx bit stream input
-- fpga side
i_tx_send : in std_logic_vector(7 downto 0); -- data byte in
i_tx_send_we : in std_logic; -- write enable
o_tx_send_busy : out std_logic; -- tx is busy, writes are ignored.
o_rx_read : out std_logic_vector(7 downto 0); -- data byte out
o_rx_read_valid : out std_logic; -- read data valid this clock cycle
i_rx_read_rd : in std_logic -- read request, get next byte..
);
end component uart;
-- translate serial commands into databus master commands
component uart_db_interface is
port (
i_clk : in std_logic; -- input system clock
i_srst : in std_logic; -- sync reset to system clock
-- uart interface
i_rx_data : in std_logic_vector( 7 downto 0); -- data from uart
i_rx_data_valid : in std_logic; -- valid data from uart
o_rx_read_ack : out std_logic; -- tell uart we have read byte.
o_tx_send : out std_logic_vector( 7 downto 0); -- tx_send data
o_tx_send_wstrb : out std_logic; -- write data strobe
i_tx_send_busy : in std_logic; -- uart is busy tx, don't write anything.. (stall)
-- databus master interface
o_db_cmd_wstrb : out std_logic; -- write command strobe
o_db_cmd_out : out std_logic_vector( 7 downto 0); -- cmd to databus master
o_db_cmd_data_out : out std_logic_vector( 7 downto 0); -- write data to databus master
i_db_cmd_data_in : in std_logic_vector( 7 downto 0); -- read data from databus master
i_db_cmd_rdy : in std_logic -- db is ready to process a cmd / previous cmd is complete.
);
end component;
-- data bus master
component databus_master is
generic (
slave_latency_max : integer := 3 -- latency from read/write strb to when the
-- operation is complete in number of i_clk cycles.
-- 3 would give a slave 3 clock cycles to perform
-- the needed operation.
);
port (
-- clock and resets
i_clk : in std_logic; -- input system clock
i_srst : in std_logic; -- sync reset to system clock
-- db master cmd interface
i_db_cmd_in : in std_logic_vector( 7 downto 0); -- input cmd byte
i_db_cmd_wstrb : in std_logic; -- write strobe for cmd byte
o_db_cmd_rdy : out std_logic; -- '1' rdy to process next cmd, '0' busy
i_db_cmd_data_in : in std_logic_vector( 7 downto 0); -- input byte if cmd is a write (with wstrb)
o_db_cmd_data_out : out std_logic_vector( 7 downto 0); -- output byte if cmd was a read
-- data bus interface
o_db_addr : out std_logic_vector( 6 downto 0); -- 6 -> 0 bit address bus (7 bits)
o_db_write_data : out std_logic_vector( 7 downto 0); -- write data
i_db_read_data : in std_logic_vector( 7 downto 0); -- read data
o_db_read_strb : out std_logic; -- db_read_strobe
o_db_write_strb : out std_logic -- db_write_strobe
);
end component;
---------------------------------------
-- Signals
---------------------------------------
-- uart signals
signal baud_div : std_logic_vector( 15 downto 0);
signal tx_byte : std_logic_vector( 7 downto 0);
signal tx_byte_we : std_logic;
signal tx_byte_busy : std_logic;
signal rx_byte : std_logic_vector( 7 downto 0);
signal rx_byte_valid : std_logic;
signal rx_byte_rd : std_logic;
-- data bus master signals
signal db_cmd : std_logic_vector( 7 downto 0 );
signal db_cmd_wstrb : std_logic;
signal db_cmd_rdy : std_logic;
signal db_cmd_wr_data : std_logic_vector( 7 downto 0 );
signal db_cmd_rd_data : std_logic_vector( 7 downto 0 );
-- data bus interface to slaves
signal db_addr : std_logic_vector(6 downto 0);
signal db_wr_data : std_logic_vector(7 downto 0);
signal db_rd_data : std_logic_vector(7 downto 0);
signal db_wr_strb : std_logic;
signal db_rd_strb : std_logic;
signal serial_rx : std_logic;
signal serial_tx : std_logic;
begin
-- connect local signals to top level
-- Serial Interface ------------------------------------------
serial_rx <= i_rx_serial_stream;
o_tx_serial_stream <= serial_tx;
-- data bus interface to slave devices -----------------------
o_db_addr <= db_addr;
o_db_wdata <= db_wr_data;
db_rd_data <= i_db_rdata;
o_db_rstrb <= db_rd_strb;
o_db_wstrb <= db_wr_strb;
-- define baud rate
baud_div <= x"01B2"; -- 115200
-- uart
u_uart : uart
port map (
i_clk => i_clk,
i_srst => i_srst,
i_baud_div => baud_div,
-- uart interface
o_uart_tx => serial_tx,
i_uart_rx => serial_rx,
-- fpga side
i_tx_send => tx_byte,
i_tx_send_we => tx_byte_we,
o_tx_send_busy => tx_byte_busy,
o_rx_read => rx_byte,
o_rx_read_valid => rx_byte_valid,
i_rx_read_rd => rx_byte_rd
);
-- databus command state machine
u_udbi : uart_db_interface
port map (
i_clk => i_clk,
i_srst => i_srst,
-- uart interface
i_rx_data => rx_byte,
i_rx_data_valid => rx_byte_valid,
o_rx_read_ack => rx_byte_rd,
o_tx_send => tx_byte,
o_tx_send_wstrb => tx_byte_we,
i_tx_send_busy => tx_byte_busy,
-- databus master interface
o_db_cmd_wstrb => db_cmd_wstrb,
o_db_cmd_out => db_cmd,
o_db_cmd_data_out => db_cmd_wr_data,
i_db_cmd_data_in => db_cmd_rd_data,
i_db_cmd_rdy => db_cmd_rdy
);
-- data bus bus master
u_db_master : databus_master
generic map (
slave_latency_max => 3 -- latency from read/write strb to when the
-- operation is complete in number of i_clk cycles.
-- 3 would give a slave 3 clock cycles to perform
-- the needed operation.
)
port map (
-- clock and resets
i_clk => i_clk,
i_srst => i_srst,
-- db master cmd interface
i_db_cmd_in => db_cmd,
i_db_cmd_wstrb => db_cmd_wstrb,
o_db_cmd_rdy => db_cmd_rdy,
i_db_cmd_data_in => db_cmd_wr_data,
o_db_cmd_data_out => db_cmd_rd_data,
-- data bus interface
o_db_addr => db_addr,
o_db_write_data => db_wr_data,
i_db_read_data => db_rd_data,
o_db_read_strb => db_rd_strb,
o_db_write_strb => db_wr_strb
);
end architecture system;
| apache-2.0 | 80fc0a4565dc2baa30161c08c2a1ac0f | 0.485989 | 3.918313 | false | false | false | false |
UdayanSinha/Code_Blocks | VHDL/Projects/work/manchester_decode.vhd | 1 | 1,045 | LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY manchester_decode IS
PORT(input: IN STD_LOGIC;
output: OUT STD_LOGIC:='0');
END manchester_decode;
ARCHITECTURE behave OF manchester_decode IS
TYPE state_type IS (S0, S1, S2); --for FSM use
SIGNAL state_mc: state_type:=S0;
BEGIN
PROCESS(input)
BEGIN
CASE state_mc IS
WHEN S0=>
IF (input='1') THEN --maybe 10
state_mc<=S1;
ELSE --maybe 01
state_mc<=S2;
END IF;
WHEN S1=>
IF (input='0') THEN --confirmed 10
output<='1';
ELSE --confirmed 11
output<='0';
END IF;
state_mc<=S0;
WHEN S2=>
output<='0'; --output is 0 whether we get 00 or 01
state_mc<=S0;
WHEN OTHERS=>
state_mc<=S0;
output<='0';
END CASE;
END PROCESS;
END behave; | mit | b30a40935eef168a5dac6e72033fb320 | 0.570335 | 3.530405 | false | false | false | false |
mithro/HDMI2USB | hdl/jpeg_encoder/design/RleDoubleFifo.vhd | 5 | 8,129 | -------------------------------------------------------------------------------
-- File Name : RleDoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : RleDoubleFifo
--
-- Content : RleDoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity RleDoubleFifo is
port
(
CLK : in std_logic;
RST : in std_logic;
-- HUFFMAN
data_in : in std_logic_vector(19 downto 0);
wren : in std_logic;
-- BYTE STUFFER
buf_sel : in std_logic;
rd_req : in std_logic;
fifo_empty : out std_logic;
data_out : out std_logic_vector(19 downto 0)
);
end entity RleDoubleFifo;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of RleDoubleFifo is
signal fifo1_rd : std_logic;
signal fifo1_wr : std_logic;
signal fifo1_q : std_logic_vector(19 downto 0);
signal fifo1_full : std_logic;
signal fifo1_empty : std_logic;
signal fifo1_count : std_logic_vector(6 downto 0);
signal fifo2_rd : std_logic;
signal fifo2_wr : std_logic;
signal fifo2_q : std_logic_vector(19 downto 0);
signal fifo2_full : std_logic;
signal fifo2_empty : std_logic;
signal fifo2_count : std_logic_vector(6 downto 0);
signal fifo_data_in : std_logic_vector(19 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- FIFO 1
-------------------------------------------------------------------
U_FIFO_1 : entity work.FIFO
generic map
(
DATA_WIDTH => 20,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo1_rd,
winc => fifo1_wr,
datai => fifo_data_in,
datao => fifo1_q,
fullo => fifo1_full,
emptyo => fifo1_empty,
count => fifo1_count
);
-------------------------------------------------------------------
-- FIFO 2
-------------------------------------------------------------------
U_FIFO_2 : entity work.FIFO
generic map
(
DATA_WIDTH => 20,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo2_rd,
winc => fifo2_wr,
datai => fifo_data_in,
datao => fifo2_q,
fullo => fifo2_full,
emptyo => fifo2_empty,
count => fifo2_count
);
-------------------------------------------------------------------
-- mux2
-------------------------------------------------------------------
p_mux2 : process(CLK, RST)
begin
if RST = '1' then
fifo1_wr <= '0';
fifo2_wr <= '0';
fifo_data_in <= (others => '0');
elsif CLK'event and CLK = '1' then
if buf_sel = '0' then
fifo1_wr <= wren;
else
fifo2_wr <= wren;
end if;
fifo_data_in <= data_in;
end if;
end process;
-------------------------------------------------------------------
-- mux3
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
--data_out <= (others => '0');
--fifo1_rd <= '0';
--fifo2_rd <= '0';
--fifo_empty <= '0';
elsif CLK'event and CLK = '1' then
if buf_sel = '1' then
--data_out <= fifo1_q;
--fifo1_rd <= rd_req;
--fifo_empty <= fifo1_empty;
else
--data_out <= fifo2_q;
--fifo2_rd <= rd_req;
--fifo_empty <= fifo2_empty;
end if;
end if;
end process;
fifo1_rd <= rd_req when buf_sel = '1' else '0';
fifo2_rd <= rd_req when buf_sel = '0' else '0';
data_out <= fifo1_q when buf_sel = '1' else fifo2_q;
fifo_empty <= fifo1_empty when buf_sel = '1' else fifo2_empty;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | bsd-2-clause | dd139c2c7b9c468d250e5706973f9fc8 | 0.3597 | 5.254686 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-2/one_to_thirty_two_demux.vhd | 1 | 4,226 | library IEEE;
use ieee.std_logic_1164.all;
entity one_to_thirty_two_demux is
port(
input : in std_logic_vector(31 downto 0);
sel : in std_logic_vector(4 downto 0);
a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q, r, s, t, u ,v, w, x, y, z, out27, out28, out29, out30, out31, out32 : out std_logic_vector(31 downto 0);
ce0, ce1, ce2, ce3, ce4, ce5, ce6, ce7, ce8, ce9, ce10, ce11, ce12, ce13, ce14, ce15, ce16, ce17, ce18, ce19, ce20, ce21, ce22, ce23, ce24, ce25, ce26, ce27, ce28, ce29, ce30, ce31 : out std_logic
);
end one_to_thirty_two_demux;
architecture behav of one_to_thirty_two_demux is
begin
a <= input when sel="00000" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
b <= input when sel="00001" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
c <= input when sel="00010" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
d <= input when sel="00011" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
e <= input when sel="00100" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
f <= input when sel="00101" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
g <= input when sel="00110" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
h <= input when sel="00111" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
i <= input when sel="01000" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
j <= input when sel="01001" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
k <= input when sel="01010" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
l <= input when sel="01011" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
m <= input when sel="01100" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
n <= input when sel="01101" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
o <= input when sel="01110" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
p <= input when sel="01111" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
q <= input when sel="10000" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
r <= input when sel="10001" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
s <= input when sel="10010" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
t <= input when sel="10011" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
u <= input when sel="10100" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
v <= input when sel="10101" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
w <= input when sel="10110" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
x <= input when sel="10111" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
y <= input when sel="11000" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
z <= input when sel="11001" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
out27 <= input when sel="11010" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
out28 <= input when sel="11011" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
out29 <= input when sel="11100" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
out30 <= input when sel="11101" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
out31 <= input when sel="11110" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
out32 <= input when sel="11111" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
ce0 <= '1' when sel="00000" else '0';
ce1 <= '1' when sel="00001" else '0';
ce2 <= '1' when sel="00010" else '0';
ce3 <= '1' when sel="00011" else '0';
ce4 <= '1' when sel="00100" else '0';
ce5 <= '1' when sel="00101" else '0';
ce6 <= '1' when sel="00110" else '0';
ce7 <= '1' when sel="00111" else '0';
ce8 <= '1' when sel="01000" else '0';
ce9 <= '1' when sel="01001" else '0';
ce10 <= '1' when sel="01010" else '0';
ce11 <= '1' when sel="01011" else '0';
ce12 <= '1' when sel="01100" else '0';
ce13 <= '1' when sel="01101" else '0';
ce14 <= '1' when sel="01110" else '0';
ce15 <= '1' when sel="01111" else '0';
ce16 <= '1' when sel="10000" else '0';
ce17 <= '1' when sel="10001" else '0';
ce18 <= '1' when sel="10010" else '0';
ce19 <= '1' when sel="10011" else '0';
ce20 <= '1' when sel="10100" else '0';
ce21 <= '1' when sel="10101" else '0';
ce22 <= '1' when sel="10110" else '0';
ce23 <= '1' when sel="10111" else '0';
ce24 <= '1' when sel="11000" else '0';
ce25 <= '1' when sel="11001" else '0';
ce26 <= '1' when sel="11010" else '0';
ce27 <= '1' when sel="11011" else '0';
ce28 <= '1' when sel="11100" else '0';
ce29 <= '1' when sel="11101" else '0';
ce30 <= '1' when sel="11110" else '0';
ce31 <= '1' when sel="11111" else '0';
end behav; | gpl-3.0 | 6a82ee48919f0bf69815b09c7a6701fe | 0.675106 | 3.296412 | false | false | false | false |
kb3gtn/mojo_modulator | vhdl/src/cos_phase_table_full.vhd | 1 | 2,817 | -----------------------------------------------------------
-- cos_phase_table_full.vhd
--
-- Lookup 16bit value from a cos(x) table.
--
-- This version implementats the full period table.
-- a full period table works better in higher speed designs
-- because the math logic causes to much delays for the clock rates
--
-- Interface the same as the normal cos_phase_table.vhd file..
--
--
-- y = cos(x) -- where x is digital phase Q
--
--
-- Peter Fetterer (KB3GTN)
-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
entity cos_phase_table is
generic (
constant sample_depth : integer := 16; -- number of bits in output sample (1->N)
constant phase_depth : integer := 12 -- number of bits for phase input value (1->N)
);
port (
i_clk : in std_logic; -- input DSP clock
i_srst : in std_logic; -- input sync reset to dsp clock
---------------------------------------------------------
x : in unsigned( phase_depth-1 downto 0 ); -- digital normalized phase input (0->2*pi)
y : out signed( sample_depth-1 downto 0 ) -- output value signed 16b
);
end entity cos_phase_table;
architecture system of cos_phase_table is
----------------------------------
-- lookup table
-- pre-compute at compile time..
----------------------------------
constant memory_depth : integer := 2**phase_depth; -- how many memory entries do we need.
constant SCALE : real := real((2**(real(sample_depth)-1.0))-1.0); -- cos is normal 1.0 we want 2^(N-1)-1 (will all be positive values)
constant STEP : real := 1.0/(real(2**phase_depth)); -- phase increment per table entry)
-- memory table is 1/4 cos period, 1024 phase enteries of 16 bit samples
-- taking advantage of cos symmetry for the other 3/4 of the period.
type cos_table_mem is array ( 0 to memory_depth ) of signed( sample_depth-1 downto 0);
-- function to fill in cos_table_mem
function init_lookuptable return cos_table_mem is
variable tmp_mem : cos_table_mem;
begin
-- phase table is only
for i in 0 to integer((2**real(phase_depth))) loop
tmp_mem(i) := to_signed( integer( round( cos(real(MATH_2_PI*(real(i)*STEP)))*SCALE)), 16 );
end loop;
return tmp_mem;
end;
-- This is the lookup table, should synth into 1 blockram on Xilinx parts.
constant cos_lookup : cos_table_mem := init_lookuptable;
begin
-- lookup table
phase_decoder : process (i_clk)
begin
if ( rising_edge( i_clk ) ) then
y <= cos_lookup( to_integer( x ) );
end if;
end process;
end architecture system;
| apache-2.0 | c00e01856814c9e2da5b2d7f6497ec0b | 0.56727 | 3.917942 | false | false | false | false |
UdayanSinha/Code_Blocks | VHDL/Projects/work/counter_up_down_4bit.vhd | 1 | 1,036 | LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
USE IEEE.std_logic_signed.all; --math operations for signed std_logic
ENTITY counter_up_down_4bit IS
PORT(up, clk, reset: IN STD_LOGIC;
out1: OUT STD_LOGIC;
out2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END counter_up_down_4bit;
ARCHITECTURE behave OF counter_up_down_4bit IS
SIGNAL count : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS (clk, reset)
BEGIN
IF reset='0' THEN --asynchronous active low reset
count<=(OTHERS=>'0');
ELSIF rising_edge(clk) THEN
CASE up IS
WHEN '1'=>
count<=count+1;
WHEN OTHERS=>
count<=count-1;
END CASE;
IF ((count=15 AND up='1') OR (count=0 AND up='0')) THEN
out1<='1';
ELSE
out1<='0';
END IF;
out2<=count;
END IF;
END PROCESS;
END behave; -- Arch_counter_sig
| mit | 983b8e2b50233f9d67400ad750fd55f2 | 0.622587 | 3.44186 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/edidram/simulation/edidram_synth.vhd | 3 | 8,872 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: edidram_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY edidram_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE edidram_synth_ARCH OF edidram_synth IS
COMPONENT edidram_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: edidram_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
| bsd-2-clause | 6cee5f536a78ad48d3aedc5d497edec8 | 0.568305 | 3.600649 | false | false | false | false |
esar/hdmilight-v2 | fpga/scaler.vhd | 1 | 4,687 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity scaler is
generic (
xdivshift : integer := 5; -- divide X resolution by 32
ydivshift : integer := 5 -- divide Y resolution by 32
);
port (
CLK : in std_logic;
CE2 : in std_logic;
DE : in std_logic;
VBLANK : in std_logic;
RAVG : in std_logic_vector(7 downto 0);
GAVG : in std_logic_vector(7 downto 0);
BAVG : in std_logic_vector(7 downto 0);
LINE_BUF_ADDR : in std_logic_vector(6 downto 0);
LINE_BUF_DATA : out std_logic_vector(23 downto 0);
LINE_READY : out std_logic;
LINE_ADDR : out std_logic_vector(5 downto 0)
);
end scaler;
architecture Behavioral of scaler is
signal DE_LAST : std_logic;
signal END_OF_LINE : std_logic;
signal X_COUNT : std_logic_vector(11 downto 0);
signal X_COUNT_RST : std_logic;
signal Y_COUNT : std_logic_vector(10 downto 0);
signal Y_COUNT_CE : std_logic;
signal Y_COUNT_RST : std_logic;
signal Y_COUNT_LAST : std_logic_vector(10 downto 0);
signal Y_COUNT_LAST_CE : std_logic;
signal LINEBUF_RST : std_logic;
signal LINEBUF_WE : std_logic;
signal LINEBUF_ADDR : std_logic_vector(6 downto 0);
signal LINEBUF_D : std_logic_vector(63 downto 0);
signal LINEBUF_Q : std_logic_vector(63 downto 0);
signal LINEBUF_DB : std_logic_vector(63 downto 0);
begin
line_buffer : entity work.blockram
GENERIC MAP(
ADDR => 7,
DATA => 64
)
PORT MAP (
a_clk => CLK,
a_rst => LINEBUF_RST,
a_en => CE2,
a_wr => LINEBUF_WE,
a_addr => LINEBUF_ADDR,
a_din => LINEBUF_D,
a_dout => LINEBUF_Q,
b_clk => CLK,
b_en => '1',
b_wr => '0',
b_rst => '0',
b_addr => LINE_BUF_ADDR,
b_din => (others => '0'),
b_dout => LINEBUF_DB
);
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE2 = '1') then
if(Y_COUNT(4 downto 0) = "11111" and END_OF_LINE = '1') then
LINE_ADDR <= Y_COUNT_LAST(10 downto 5);
LINE_READY <= '1';
else
LINE_READY <= '0';
end if;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE2 = '1') then
if(DE = '0' and DE_LAST = '1') then
END_OF_LINE <= '1';
else
END_OF_LINE <= '0';
end if;
DE_LAST <= DE;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE2 = '1') then
if(X_COUNT_RST = '1') then
X_COUNT <= (others => '0');
else
X_COUNT <= std_logic_vector(unsigned(X_COUNT) + 1);
end if;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE2 = '1') then
if(Y_COUNT_RST = '1') then
Y_COUNT <= (others => '0');
else
if(Y_COUNT_CE = '1') then
Y_COUNT <= std_logic_vector(unsigned(Y_COUNT) + 1);
end if;
end if;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE2 = '1') then
if(Y_COUNT_LAST_CE = '1') then
Y_COUNT_LAST <= Y_COUNT;
end if;
end if;
end if;
end process;
X_COUNT_RST <= not DE;
Y_COUNT_RST <= VBLANK;
Y_COUNT_CE <= END_OF_LINE;
Y_COUNT_LAST_CE <= END_OF_LINE;
LINEBUF_ADDR <= Y_COUNT(5) & X_COUNT(9 downto 4);
LINEBUF_RST <= '1' when Y_COUNT(4 downto 0) = "00000" and X_COUNT(3 downto 1) = "000" else '0';
LINEBUF_WE <= X_COUNT(0);
LINEBUF_D(63 downto 48) <= (others => '0');
LINEBUF_D(47 downto 32) <= std_logic_vector(unsigned(LINEBUF_Q(47 downto 32)) + unsigned(RAVG));
LINEBUF_D(31 downto 16) <= std_logic_vector(unsigned(LINEBUF_Q(31 downto 16)) + unsigned(GAVG));
LINEBUF_D(15 downto 0) <= std_logic_vector(unsigned(LINEBUF_Q(15 downto 0)) + unsigned(BAVG));
LINE_BUF_DATA( 7 downto 0) <= LINEBUF_DB(15 downto 8);
LINE_BUF_DATA(15 downto 8) <= LINEBUF_DB(31 downto 24);
LINE_BUF_DATA(23 downto 16) <= LINEBUF_DB(47 downto 40);
end Behavioral;
| gpl-2.0 | 353db8532668d6b5806cc3528351c0c4 | 0.612332 | 2.828606 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/pcores/ready4hood_v1_00_a/hdl/vhdl/brutus_top.vhd | 2 | 7,474 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:29 09/22/2014
-- Design Name:
-- Module Name: brutus_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity brutus_top is
generic (
M : integer := 1
);
port (
clk : in std_logic;
rstn : in std_logic;
i_fsl_data_recv : in std_logic;
i_fsl_hash : in std_logic_vector(127 downto 0);
o_pw_found : out std_logic;
o_passwd : out std_logic_vector(47 downto 0)
);
end brutus_top;
architecture Behavioral of brutus_top is
component string_generator
port (
clk : in std_logic;
rstn : in std_logic; -- active low reset ofc
i_start : in std_logic;
i_halt : in std_logic;
o_done : out std_logic;
o_length : out std_logic_vector(2 downto 0); -- max 6 chars
o_string : out std_logic_vector(47 downto 0) -- 6 char string
);
end component;
component pre_process
Port ( i_data : in STD_LOGIC_VECTOR (47 downto 0);
i_length : in STD_LOGIC_VECTOR (2 downto 0);
o_data_0 : out unsigned (31 downto 0);
o_data_1 : out unsigned (31 downto 0);
o_length : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component MD5
port (
clk : in std_logic;
rstn : in std_logic;
i_start : in std_logic;
--i_data : in unsigned(71 downto 0); -- 8 chars + 1 appended bit
i_data_0 : in unsigned(31 downto 0); -- first 4 chars
i_data_1 : in unsigned(31 downto 0); -- next 4 chars
i_length : in std_logic_vector(7 downto 0); -- nbr of chars
o_done : out std_logic;
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end component;
component comp
port(
clk : in std_logic;
rstn : in std_logic; -- active low
i_hash_0, i_hash_1, i_hash_2, i_hash_3 : in unsigned(31 downto 0); -- hash from md5
i_cmp_hash : in std_logic_vector(127 downto 0); -- hash we are going to crack
i_start : in std_logic; -- 1 when we should read i_cmp_hash
o_equal : out std_logic -- 1 if we found the matching hash, else 0
);
end component;
component controller
generic (
N : integer
);
port (
clk : in std_logic;
rstn : in std_logic;
i_fsl_data_recv : in std_logic;
i_fsl_hash : in std_logic_vector(127 downto 0);
i_comp_eq : in std_logic; -- check if password was found
i_sg_done : in std_logic; -- string generator done signal
i_sg_string : in std_logic_vector(47 downto 0); -- current potential password
i_md5_done : in std_logic; -- done signal from the main MD5 core
o_passwd_hash : out std_logic_vector(127 downto 0); -- hash from FSL
o_pw_found : out std_logic; -- flag to indicate password found
-- o_pw_nfound : out ---
o_passwd : out std_logic_vector(47 downto 0); -- password string, send to user
o_start_sg_comp : out std_logic; -- start signals to sg and comp
o_start_md5 : out std_logic; -- start signal to MD5 cores
o_halt_sg : out std_logic; -- halt signal to sg
o_demux_sel : out std_logic_vector(M-1 downto 0); --
o_mux_sel : out std_logic_vector(M-1 downto 0) -- select signals to DEMUX/MUX
);
end component;
signal s_len_sg_pp : std_logic_vector(2 downto 0); -- length sg->pp
signal s_len_pp_md5 : std_logic_vector(7 downto 0); -- length pp->md5
signal s_string_sg_pp : std_logic_vector(47 downto 0);
signal s_string1_pp_md5 : unsigned(31 downto 0);
signal s_string2_pp_md5 : unsigned(31 downto 0);
signal h0, h1, h2, h3 : unsigned(31 downto 0); -- hashes from md5 to comparator
signal comp_ctrl_eq, sg_ctrl_done, md5_ctrl_done : std_logic;
signal sg_ctrl_string : std_logic_vector(47 downto 0);
signal ctrl_comp_hash : std_logic_vector(127 downto 0);
signal ctrl_sg_comp_start : std_logic; -- start signal to sg and comp
signal ctrl_md5_start : std_logic; -- start signal to MD5 cores
signal ctrl_sg_halt : std_logic; -- halt signal to sg
signal ctrl_demux_sel, ctrl_mux_sel : std_logic_vector(M-1 downto 0); -- mux/demux selectors
begin
controller_inst: controller
generic map (
N => M
)
port map (
clk => clk,
rstn => rstn,
i_fsl_data_recv => i_fsl_data_recv,
i_fsl_hash => i_fsl_hash,
i_comp_eq => comp_ctrl_eq,
i_sg_done => sg_ctrl_done,
i_sg_string => sg_ctrl_string,
i_md5_done => md5_ctrl_done,
o_passwd_hash => ctrl_comp_hash,
o_pw_found => o_pw_found,
o_passwd => o_passwd,
o_start_sg_comp => ctrl_sg_comp_start,
o_start_md5 => ctrl_md5_start,
o_halt_sg => ctrl_sg_halt,
o_demux_sel => open,
o_mux_sel => open
);
comp_inst: comp
port map (
clk => clk,
rstn => rstn,
i_cmp_hash => i_fsl_hash,
i_hash_0 => h0,
i_hash_1 => h1,
i_hash_2 => h2,
i_hash_3 => h3,
i_start => ctrl_sg_comp_start,
o_equal => comp_ctrl_eq
);
sg_ctrl_string <= s_string_sg_pp; -- string goes both to pp and controller
sg_inst: string_generator
port map (
clk => clk,
rstn => rstn,
i_start => ctrl_sg_comp_start,
i_halt => ctrl_sg_halt,
o_done => sg_ctrl_done,
o_length => s_len_sg_pp,
o_string => s_string_sg_pp
);
pp_inst: pre_process
port map(
i_data => s_string_sg_pp,
i_length => s_len_sg_pp,
o_data_0 => s_string1_pp_md5,
o_data_1 => s_string2_pp_md5,
o_length => s_len_pp_md5
);
MD5_inst: MD5
port map (
clk => clk,
rstn => rstn,
i_start => ctrl_md5_start,
i_data_0 => s_string1_pp_md5,
i_data_1 => s_string2_pp_md5,
i_length => s_len_pp_md5,
o_done => md5_ctrl_done,
o_hash_0 => h0, --o_hash(31 downto 0),
o_hash_1 => h1, --o_hash(63 downto 32),
o_hash_2 => h2, --o_hash(95 downto 64),
o_hash_3 => h3 --o_hash(127 downto 96)
);
end Behavioral;
| mit | 7be6351a4684c3ceb40d792808e3e734 | 0.494381 | 3.530468 | false | false | false | false |
RickvanLoo/Synthesizer | mixer_entity.vhd | 1 | 1,793 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
ENTITY mixer_entity IS
GENERIC(lut_bit_width : integer := 8;
DATA_width: integer := 16;
max_amplitude : integer := 32767;
min_amplitude : integer := -32767
);
PORT(
a_clk : in std_logic;
reset : in std_logic;
DATA_SI_1, DATA_SI_2 : in std_logic_vector(15 downto 0);
DATA_SQ_1, DATA_SQ_2 : in std_logic_vector(15 downto 0);
DATA_SA_1, DATA_SA_2 : in std_logic_vector(15 downto 0);
DATA_TR_1, DATA_TR_2 : in std_logic_vector(15 downto 0);
WAV_SELECT : in std_logic_vector(7 downto 0);
DATA_TO_AI : OUT std_logic_vector(15 downto 0)
);
END mixer_entity;
ARCHITECTURE behav of mixer_entity is
SIGNAL osc1,osc2,output : integer := 0;
BEGIN
process(a_clk, reset)
variable osc1,osc2 : integer := 0;
begin
if reset = '0' then
osc1 := 0;
osc2 := 0;
output <= 0;
DATA_TO_AI <= (others => '0');
elsif falling_edge(a_clk) then
case(WAV_SELECT) is
WHEN x"00" => -- SINE
osc1 := to_integer(signed(DATA_SI_1));
osc2 := to_integer(signed(DATA_SI_2));
WHEN x"01" => -- SQUARE
osc1 := to_integer(signed(DATA_SQ_1));
osc2 := to_integer(signed(DATA_SQ_2));
WHEN x"02" => -- SAW
osc1 := to_integer(signed(DATA_SA_1));
osc2 := to_integer(signed(DATA_SA_2));
WHEN x"03" => -- TRI
osc1 := to_integer(signed(DATA_TR_1));
osc2 := to_integer(signed(DATA_TR_2));
WHEN others => -- SINE
osc1 := to_integer(signed(DATA_SI_1));
osc2 := to_integer(signed(DATA_SI_2));
END CASE;
osc1 := osc1/4;
osc2 := osc2/4;
output <= osc1 + osc2;
DATA_TO_AI <= std_logic_vector(to_signed(output, DATA_width));
end if;
end process;
END ARCHITECTURE; | mit | d4c363533980ff525baa2f2f50b72f8e | 0.59063 | 2.716667 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/pcores/bajsd_v1_00_a - Copy/hdl/vhdl/tb_comp.vhd | 1 | 3,390 | --------------------------------------------------------------------------------
-- Company:
-- Engineer: Gabbe
--
-- Create Date: 12:04:52 09/17/2014
-- Design Name:
-- Module Name: H:/embedded_labs/comp/tb_comp.vhd
-- Project Name: comp
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: comp
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_comp IS
END tb_comp;
ARCHITECTURE behavior OF tb_comp IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT comp
PORT(
clk : IN std_logic;
rstn : IN std_logic;
i_hash_0 : IN unsigned(31 downto 0);
i_hash_1 : IN unsigned(31 downto 0);
i_hash_2 : IN unsigned(31 downto 0);
i_hash_3 : IN unsigned(31 downto 0);
i_cmp_hash : IN std_logic_vector(127 downto 0);
i_start : IN std_logic;
o_equal : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rstn : std_logic := '1';
signal i_hash_0 : unsigned(31 downto 0) := (others => '0');
signal i_hash_1 : unsigned(31 downto 0) := (others => '0');
signal i_hash_2 : unsigned(31 downto 0) := (others => '0');
signal i_hash_3 : unsigned(31 downto 0) := (others => '0');
signal i_cmp_hash : std_logic_vector(127 downto 0) := (others => '0');
signal i_start : std_logic := '0';
--Outputs
signal o_equal : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: comp PORT MAP (
clk => clk,
rstn => rstn,
i_hash_0 => i_hash_0,
i_hash_1 => i_hash_1,
i_hash_2 => i_hash_2,
i_hash_3 => i_hash_3,
i_cmp_hash => i_cmp_hash,
i_start => i_start,
o_equal => o_res
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2;
rstn <= '0';
wait for clk_period;
rstn <= '1';
i_cmp_hash <= x"13121110232221203332313043424140";
i_start <= '1';
wait for clk_period;
i_start <= '0';
i_hash_0 <= x"10111213";
i_hash_1 <= x"20212223";
i_hash_2 <= x"30313233";
i_hash_3 <= x"40414243";
assert o_equal = '1' report "correct hash compared wrong";
wait for clk_period*4;
i_hash_0 <= x"11111111";
i_hash_1 <= x"11111111";
i_hash_2 <= x"11111111";
i_hash_3 <= x"11111111";
wait for clk_period;
assert o_equal = '0' report "false hash compared wrong";
wait;
end process;
END;
| mit | 47c8200b4ff0e21dcd65934c8ae67cbb | 0.573156 | 3.353116 | false | false | false | false |
esar/hdmilight-v2 | fpga/test_colourTransformer.vhd | 1 | 7,143 | -- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY test_colourTransformer IS
END test_colourTransformer;
ARCHITECTURE behavior OF test_colourTransformer IS
COMPONENT resultDistributor
PORT(
clk : in std_logic;
start : in std_logic;
driverReadyVect : in std_logic_vector(7 downto 0);
driverStartVect : out std_logic_vector(7 downto 0);
driverData : out std_logic_vector(23 downto 0);
outputMapAddr : out std_logic_vector(11 downto 0);
outputMapData : in std_logic_vector(15 downto 0);
areaResultAddr : out std_logic_vector(8 downto 0);
areaResultR : in std_logic_vector(7 downto 0);
areaResultG : in std_logic_vector(7 downto 0);
arearesultB : in std_logic_vector(7 downto 0);
colourCoefAddr : out std_logic_vector(8 downto 0);
colourCoefData : in std_logic_vector(63 downto 0);
gammaTableRAddr : out std_logic_vector(10 downto 0);
gammaTableRData : in std_logic_vector(7 downto 0);
gammaTableGAddr : out std_logic_vector(10 downto 0);
gammaTableGData : in std_logic_vector(7 downto 0);
gammaTableBAddr : out std_logic_vector(10 downto 0);
gammaTableBData : in std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT ws2811Driver
PORT(
clk : in STD_LOGIC;
idle : out STD_LOGIC;
load : in STD_LOGIC;
datain : in STD_LOGIC_VECTOR (23 downto 0);
dataout : out STD_LOGIC
);
END COMPONENT;
signal clk : std_logic;
signal start : std_logic;
signal driverReady : std_logic_vector(7 downto 0);
signal driverStart : std_logic_vector(7 downto 0);
signal driverData : std_logic_vector(23 downto 0);
signal driverOutput : std_logic_vector(7 downto 0);
signal outputMapAddr : std_logic_vector(11 downto 0);
signal outputMapData : std_logic_vector(15 downto 0);
signal areaResultAddr : std_logic_vector(8 downto 0);
signal areaResultR : std_logic_vector(7 downto 0);
signal areaResultG : std_logic_vector(7 downto 0);
signal arearesultB : std_logic_vector(7 downto 0);
signal colourCoefAddr : std_logic_vector(8 downto 0);
signal colourCoefData : std_logic_vector(63 downto 0);
signal gammaTableRAddr : std_logic_vector(10 downto 0);
signal gammaTableRData : std_logic_vector(7 downto 0);
signal gammaTableGAddr : std_logic_vector(10 downto 0);
signal gammaTableGData : std_logic_vector(7 downto 0);
signal gammaTableBAddr : std_logic_vector(10 downto 0);
signal gammaTableBData : std_logic_vector(7 downto 0);
constant clkperiod : time := 10 ns;
type outputMapArray is array (0 to 4096) of std_logic_vector(15 downto 0);
shared variable outputMap : outputMapArray := (others => "1000000000000000");
type colourCoefArray is array (0 to 511) of std_logic_vector(63 downto 0);
shared variable colourCoef : colourCoefArray := (
x"0000100010001000",
x"000000000000FF00",
x"00000000FF000000",
x"0000FF0000000000",
others => (others => '0'));
type gammaTableArray is array (0 to 255) of std_logic_vector(7 downto 0);
constant gammaTableR : gammaTableArray := (others => (others => '0'));
constant gammaTableG : gammaTableArray := (others => (others => '0'));
constant gammaTableB : gammaTableArray := (others => (others => '0'));
BEGIN
rd: resultDistributor PORT MAP (
clk => clk,
start => start,
driverReadyVect => driverReady,
driverStartVect => driverStart,
driverData => driverData,
outputMapAddr => outputMapAddr,
outputMapData => outputMapData,
areaResultAddr => areaResultAddr,
areaResultR => areaResultR,
areaResultG => areaResultG,
arearesultB => areaResultB,
colourCoefAddr => colourCoefAddr,
colourCoefData => colourCoefData,
gammaTableRAddr => gammaTableRAddr,
gammaTableRData => gammaTableRData,
gammaTableGAddr => gammaTableGAddr,
gammaTableGData => gammaTableGData,
gammaTableBAddr => gammaTableBAddr,
gammaTableBData => gammaTableBData
);
drv0: ws2811Driver PORT MAP(clk => clk, idle => driverReady(0), load => driverStart(0), datain => driverData, dataout => driverOutput(0));
drv1: ws2811Driver PORT MAP(clk => clk, idle => driverReady(1), load => driverStart(1), datain => driverData, dataout => driverOutput(1));
drv2: ws2811Driver PORT MAP(clk => clk, idle => driverReady(2), load => driverStart(2), datain => driverData, dataout => driverOutput(2));
drv3: ws2811Driver PORT MAP(clk => clk, idle => driverReady(3), load => driverStart(3), datain => driverData, dataout => driverOutput(3));
drv4: ws2811Driver PORT MAP(clk => clk, idle => driverReady(4), load => driverStart(4), datain => driverData, dataout => driverOutput(4));
drv5: ws2811Driver PORT MAP(clk => clk, idle => driverReady(5), load => driverStart(5), datain => driverData, dataout => driverOutput(5));
drv6: ws2811Driver PORT MAP(clk => clk, idle => driverReady(6), load => driverStart(6), datain => driverData, dataout => driverOutput(6));
drv7: ws2811Driver PORT MAP(clk => clk, idle => driverReady(7), load => driverStart(7), datain => driverData, dataout => driverOutput(7));
process(clk)
begin
if(rising_edge(clk)) then
areaResultR <= areaResultAddr(7 downto 0);
areaResultG <= areaResultAddr(7 downto 0);
areaResultB <= areaResultAddr(7 downto 0);
outputMapData <= outputMap(to_integer(unsigned(outputMapAddr)));
colourCoefData <= colourCoef(to_integer(unsigned(colourCoefAddr)));
--gammaTableRData <= gammaTableR(to_integer(unsigned(gammaTableRAddr)));
--gammaTableGData <= gammaTableR(to_integer(unsigned(gammaTableGAddr)));
--gammaTableBData <= gammaTableR(to_integer(unsigned(gammaTableBAddr)));
gammaTableRData <= gammaTableRAddr(7 downto 0);
gammaTableGData <= gammaTableGAddr(7 downto 0);
gammaTableBData <= gammaTableBAddr(7 downto 0);
end if;
end process;
-- Test Bench Statements
tb : PROCESS
BEGIN
clk <= '0';
start <= '0';
colourCoef(0) := "0000000000" & ('0' & x"00" & "000000000") & ('0' & x"00" & "000000000") & ('1' & x"ff" & "000000000");
colourCoef(1) := "0000000000" & ('0' & x"00" & "000000000") & ('1' & x"ff" & "000000000") & ('0' & x"00" & "000000000");
colourCoef(2) := "0000000000" & ('1' & x"ff" & "000000000") & ('0' & x"00" & "000000000") & ('0' & x"00" & "000000000");
colourCoef(3) := "0000000000" & ('0' & x"ff" & "000000000") & ('0' & x"ff" & "000000000") & ('0' & x"ff" & "000000000");
for x in 0 to 4095 loop
outputMap(x) := "10000000" & std_logic_vector(to_unsigned(x, 8));
end loop;
for x in (6*512 + 254) to (6*512 + 511) loop
outputMap(x) := "0000000000000000";
end loop;
wait for 100 ns; -- wait until global set/reset completes
clk <= '1';
wait for clkperiod;
clk <= '0';
wait for clkperiod;
start <= '1';
clk <= '1';
wait for clkperiod;
clk <= '0';
wait for clkperiod;
for x in 0 to 1000000 loop
clk <= '1';
wait for clkperiod;
clk <= '0';
wait for clkperiod;
end loop;
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
| gpl-2.0 | 8e0ce612094f3073b8bf0d0dd0dda619 | 0.670587 | 3.479299 | false | false | false | false |
mithro/HDMI2USB | hdl/hdmi2usb.vhd | 3 | 20,889 | -- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2012, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-- /*!
-- HDMI 2 USB(jpeg) converter top lever module.
-- this file contains all the necessary modules needed.
-- description of each module is given in its top level file.
-- Useful links are
-- http://www.xilinx.com/support/documentation/application_notes/xapp495_S6TMDS_Video_Interface.pdf
-- http://www.xilinx.com/support/documentation/spartan-6.htm
-- http://www.evernew.com.tw/HDMISpecification13a.pdf
-- http://read.pudn.com/downloads110/ebook/456020/E-EDID%20Standard.pdf
-- http://www.nxp.com/documents/user_manual/UM10204.pdf
-- http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,836&Prod=ATLYS
-- http://en.wikipedia.org/wiki/Extended_display_identification_data
-- http://en.wikipedia.org/wiki/I%C2%B2C
-- http://en.wikipedia.org/wiki/Hdmi
-- */
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity hdmi2usb is
generic (
SIMULATION : string := "FALSE";
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3200;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port
(
HDMI_RX0_tmds_p : in std_logic_vector(3 downto 0);
HDMI_RX0_tmds_n : in std_logic_vector(3 downto 0);
HDMI_RX0_scl : in std_logic; -- DDC scl connected with PC
HDMI_RX0_sda : inout std_logic; -- DDC sda connected with PC
HDMI_RX1_tmds_p : in std_logic_vector(3 downto 0);
HDMI_RX1_tmds_n : in std_logic_vector(3 downto 0);
HDMI_RX1_scl : in std_logic; -- DDC scl connected with PC
HDMI_RX1_sda : inout std_logic; -- DDC sda connected with PC
HDMI_TX0_tmds_p : out std_logic_vector(3 downto 0);
HDMI_TX0_tmds_n : out std_logic_vector(3 downto 0);
HDMI_TX0_scl : out std_logic; -- DDC scl connected with LCD
HDMI_TX0_sda : inout std_logic; -- DDC sda connected with LCD
HDMI_TX1_tmds_p : out std_logic_vector(3 downto 0);
HDMI_TX1_tmds_n : out std_logic_vector(3 downto 0);
-- HDMI_TX1_scl : out std_logic; -- DDC scl connected with LCD
-- HDMI_TX1_sda : inout std_logic; -- DDC sda connected with LCD
btnc : in std_logic;
btnu : in std_logic;
btnl : in std_logic;
btnr : in std_logic;
btnd : in std_logic;
LED : out std_logic_vector(7 downto 0);
sw : in std_logic_vector(7 downto 0);
-- USB Chip
fx2_addr : out std_logic_vector(1 downto 0);
fx2_data : inout std_logic_vector(7 downto 0);
fx2_flagA : in std_logic;
fx2_flagB : in std_logic; -- flag_full(flagB)
fx2_flagC : in std_logic; -- flag_empty(flagC)
fx2_slwr : out std_logic;
fx2_slrd : out std_logic;
fx2_sloe : out std_logic;
fx2_pktend : out std_logic;
fx2_slcs : out std_logic;
fx2_ifclk : in std_logic;
-- DDR2 RAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n: inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
--UART
rx : in std_logic;
tx : out std_logic;
rst_n : in std_logic;
clk : in std_logic
);
end entity hdmi2usb;
architecture rtl of hdmi2usb is
signal de_H : std_logic;
signal de : std_logic;
signal hsync : std_logic;
signal vsync : std_logic;
signal pclk_H : std_logic;
signal resx : std_logic_vector(15 DOWNTO 0);
signal resy : std_logic_vector(15 DOWNTO 0);
signal rgb : std_logic_vector(23 DOWNTO 0);
signal rgb_H : std_logic_vector(23 DOWNTO 0);
signal rdy_H0 : std_logic;
signal de_H0 : std_logic;
signal rgb_H0 : std_logic_vector(23 downto 0);
signal hsync_H0 : std_logic;
signal vsync_H0 : std_logic;
signal pclk_H0 : std_logic;
signal resx_H0 : std_logic_vector(15 DOWNTO 0);
signal resy_H0 : std_logic_vector(15 DOWNTO 0);
signal rdy_H1 : std_logic;
signal de_H1 : std_logic;
signal rgb_H1 : std_logic_vector(23 downto 0);
signal hsync_H1 : std_logic;
signal vsync_H1 : std_logic;
signal pclk_H1 : std_logic;
signal resx_H1 : std_logic_vector(15 DOWNTO 0);
signal resy_H1 : std_logic_vector(15 DOWNTO 0);
signal de_vga : std_logic;
signal hsync_vga : std_logic;
signal vsync_vga : std_logic;
signal pclk_vga : std_logic;
signal resx_vga : std_logic_vector(15 DOWNTO 0);
signal resy_vga : std_logic_vector(15 DOWNTO 0);
signal rgb_vga : std_logic_vector(23 downto 0);
signal de_tp : std_logic;
signal hsync_tp : std_logic;
signal vsync_tp : std_logic;
signal pclk_tp : std_logic;
signal resx_tp : std_logic_vector(15 DOWNTO 0);
signal resy_tp : std_logic_vector(15 DOWNTO 0);
signal rgb_tp : std_logic_vector(23 downto 0);
signal rst : std_logic;
signal edid0_byte : std_logic_vector(7 downto 0);
signal edid0_byte_en : std_logic;
signal hpd : std_logic;
signal edid1_byte : std_logic_vector(7 downto 0);
signal edid1_byte_en : std_logic;
signal slwr_i : std_logic;
signal cmd_en : std_logic;
signal cmd_byte : std_logic_vector(7 downto 0);
signal uvc_rst : std_logic;
signal jpg_start : std_logic;
signal jpg_done : std_logic;
signal jpg_busy : std_logic;
signal hdmi_cmd : std_logic_vector(1 downto 0);
signal dvi_only : std_logic_vector(1 downto 0);
signal usb_cmd : std_logic_vector(2 downto 0);
signal selector_cmd : std_logic_vector(12 downto 0);
signal status : std_logic_vector(4 downto 0);
signal img_clk : std_logic;
signal jpg_enable : std_logic;
signal raw_fifo_full : std_logic;
signal img_out_en : std_logic;
signal ycbcr_en : std_logic;
signal img_out : std_logic_vector(23 downto 0);
signal ycbcr : std_logic_vector(23 downto 0);
signal jpeg_encoder_cmd : std_logic_vector(1 downto 0);
signal outif_almost_full : std_logic;
signal btnr_s : std_logic;
signal btnu_s : std_logic;
signal btnd_s : std_logic;
signal btnl_s : std_logic;
signal jpeg_byte : std_logic_vector(7 downto 0);
signal jpeg_en : std_logic;
signal jpg_fifo_afull : std_logic;
signal error_ram : std_logic;
signal to_send : std_logic_vector(23 downto 0);
signal pktend_s:std_logic;
signal HB_on : std_logic;
signal rd_uart_s : std_logic;
signal rx_empty_s : std_logic;
signal uart_din_s : std_logic_vector(7 downto 0);
signal dout : std_logic_vector(15 downto 0);
--debug signals
signal write_img:std_logic;
signal no_frame_read:std_logic;
signal uart_byte:std_logic_vector(7 downto 0);
signal uart_en: std_logic;
signal clk_50Mhz:std_logic;
signal frame_size:std_logic_vector(23 downto 0);
signal debug_byte:std_logic_vector(7 downto 0);
signal debug_index:integer range 0 to 15;
signal eof_jpg: std_logic;
---------------------------------------------------------------------------------------------------------------------
begin
rst <= not rst_n;
fx2_slcs <= '0';
fx2_slwr <= slwr_i;
LED(0) <= de_H0;
LED(1) <= de_H1;
LED(2) <= usb_cmd(1);
LED(3) <= fx2_flagB; -- full flag
LED(4) <= fx2_flagC; -- empty flag
LED(5) <= slwr_i;
LED(6) <= selector_cmd(0);
LED(7) <= selector_cmd(1);
fx2_pktend <= pktend_s;
debouncerBtnc : entity work.debouncer
port map(clk => img_clk,
rst_n => rst_n,
insig => btnc,
outsig => hpd);
debouncerBtnu : entity work.debouncer
port map(clk => img_clk,
rst_n => rst_n,
insig => btnu,
outsig => btnu_s);
debouncerBtnd : entity work.debouncer
port map(clk => img_clk,
rst_n => rst_n,
insig => btnd,
outsig => btnd_s);
debouncerBtnl : entity work.debouncer
port map(clk => img_clk,
rst_n => rst_n,
insig => btnl,
outsig => btnl_s);
debouncerBtnr : entity work.debouncer
port map(clk => img_clk,
rst_n => rst_n,
insig => btnr,
outsig => btnr_s);
jpeg_encoder : entity work.jpeg_encoder_top
port map(
--debug signal
frame_size => frame_size,
clk => img_clk,
uvc_rst => uvc_rst,
iram_wdata => img_out,
iram_wren => img_out_en,
iram_fifo_afull => jpg_fifo_afull,
ram_byte => jpeg_byte,
ram_wren => jpeg_en,
outif_almost_full => outif_almost_full,
resx => resx,
resy => resy,
jpeg_encoder_cmd => jpeg_encoder_cmd,
enable => jpg_enable,
start => jpg_start,
done => jpg_done,
busy => jpg_busy);
jpg_enable <= (usb_cmd(2) and usb_cmd(1));
ddr2_comp : entity work.image_buffer
generic map(C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C3_SIMULATION => C3_SIMULATION,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH)
port map(
--debug signals
no_frame_read => no_frame_read,
write_img_s => write_img,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
img_in => rgb,
img_in_en => de,
img_out => img_out,
img_out_en => img_out_en,
jpg_fifo_afull => jpg_fifo_afull,
raw_fifo_afull => raw_fifo_full,
clk => clk,
clk_out => img_clk,
jpg_or_raw => usb_cmd(1),
vsync => vsync,
jpg_busy => jpg_busy,
jpg_done => jpg_done,
jpg_start => jpg_start,
resX => resX,
resY => resY,
to_send => to_send,
rst => rst,
uvc_rst => uvc_rst,
error => error_ram);
img_sel_comp : entity work.image_selector
port map(rgb_H0 => rgb_H0,
de_H0 => de_H0,
pclk_H0 => pclk_H0,
hsync_H0 => hsync_H0,
vsync_H0 => vsync_H0,
resX_H0 => resX_H0,
resY_H0 => resY_H0,
rgb_H1 => rgb_H1,
de_H1 => de_H1,
pclk_H1 => pclk_H1,
hsync_H1 => hsync_H1,
vsync_H1 => vsync_H1,
resX_H1 => resX_H1,
resY_H1 => resY_H1,
rgb_tp => rgb_tp,
de_tp => de_tp,
pclk_tp => pclk_tp,
hsync_tp => hsync_tp,
vsync_tp => vsync_tp,
resX_tp => resX_tp,
resY_tp => resY_tp,
rgb_vga => rgb_vga,
de_vga => de_vga,
pclk_vga => pclk_vga,
hsync_vga => hsync_vga,
vsync_vga => vsync_vga,
resX_vga => resX_vga,
resY_vga => resY_vga,
selector_cmd => selector_cmd,
HB_on => HB_on,
HB_sw => sw(0),
rgb => rgb,
de => de,
hsync => hsync,
vsync => vsync,
resX => resX,
resY => resY,
rgb_H => rgb_H,
de_H => de_H,
pclk_H => pclk_H,
clk => img_clk,
rst => rst);
hdmiMatri_Comp : entity work.hdmimatrix
port map(rst_n => rst_n,
HDMI_RX0_tmds_p => HDMI_RX0_tmds_p,
HDMI_RX0_tmds_n => HDMI_RX0_tmds_n,
HDMI_TX0_tmds_p => HDMI_TX0_tmds_p,
HDMI_TX0_tmds_n => HDMI_TX0_tmds_n,
HDMI_RX1_tmds_p => HDMI_RX1_tmds_p,
HDMI_RX1_tmds_n => HDMI_RX1_tmds_n,
HDMI_TX1_tmds_p => HDMI_TX1_tmds_p,
HDMI_TX1_tmds_n => HDMI_TX1_tmds_n,
rx0_de => de_H0,
rx1_de => de_H1,
rx1_hsync => hsync_H1,
rx0_hsync => hsync_H0,
rx1_vsync => vsync_H1,
rx0_vsync => vsync_H0,
rx1_pclk => pclk_H1,
rx0_pclk => pclk_H0,
rdy0 => rdy_H0,
rdy1 => rdy_H1,
rx0_rgb => rgb_H0,
rx1_rgb => rgb_H1,
tx_rgb => rgb_H,
tx_de => de_H,
tx_hsync => hsync,
tx_vsync => vsync,
tx_pclk => pclk_H,
rst => rst);
calc_res0 : entity work.calc_res
port map(rst_n => rst_n,
clk => pclk_H0,
de => de_H0,
hsync => hsync_H0,
vsync => vsync_H0,
resX => resX_H0,
resY => resY_H0);
calc_res1 : entity work.calc_res
port map(rst_n => rst_n,
clk => pclk_H1,
de => de_H1,
hsync => hsync_H1,
vsync => vsync_H1,
resX => resX_H1,
resY => resY_H1);
edid_hack0 : entity work.edid_master_slave_hack
port map(rst_n => rst_n,
clk => img_clk,
sda_lcd => HDMI_TX0_sda,
scl_lcd => HDMI_TX0_scl,
sda_pc => HDMI_RX0_sda,
scl_pc => HDMI_RX0_scl,
hpd_lcd => hpd,
hpd_pc => open,
sda_byte => edid0_byte,
sda_byte_en => edid0_byte_en,
dvi_only => dvi_only(0),
hdmi_dvi => hdmi_cmd(0));
edid_hack1 : entity work.edid_master_slave_hack
port map(rst_n => rst_n,
clk => img_clk,
sda_lcd => open,
scl_lcd => open,
sda_pc => HDMI_RX1_sda,
scl_pc => HDMI_RX1_scl,
hpd_lcd => hpd,
hpd_pc => open,
sda_byte => edid1_byte,
sda_byte_en => edid1_byte_en,
dvi_only => dvi_only(1),
hdmi_dvi => hdmi_cmd(1));
rgb2ycbcr_comp: entity work.rgb2ycbcr
port map(
rgb => img_out,
de_in => img_out_en,
ycbcr => ycbcr,
de_out => ycbcr_en,
rst_n => rst_n,
clk => img_clk);
usb_comp: entity work.usb_top
port map(edid0_byte => edid0_byte,
edid0_byte_en => edid0_byte_en,
edid1_byte => edid1_byte,
edid1_byte_en => edid1_byte_en,
jpeg_byte => jpeg_byte,
jpeg_clk => img_clk,
jpeg_en => jpeg_en,
jpeg_fifo_full => outif_almost_full,
raw_en => ycbcr_en,
raw_bytes => ycbcr,
raw_fifo_full => raw_fifo_full,
raw_clk => img_clk,
faddr => fx2_addr,
fdata => fx2_data,
flag_full => fx2_flagB,
flag_empty => fx2_flagC,
slwr => slwr_i,
slrd => fx2_slrd,
sloe => fx2_sloe,
pktend => pktend_s,
ifclk => fx2_ifclk,
resX_H0 => resX_H0,
resY_H0 => resY_H0,
resX_H1 => resX_H1,
resY_H1 => resY_H1,
de_H0 => de_H0,
de_H1 => de_H1,
status => status,
usb_cmd => usb_cmd,
jpeg_encoder_cmd => jpeg_encoder_cmd,
selector_cmd => selector_cmd,
hdmi_cmd => hdmi_cmd,
debug_byte => debug_byte,
debug_index => debug_index,
eof_jpg => eof_jpg,
uvc_rst => uvc_rst,
to_send => to_send,
cmd_en => cmd_en,
cmd => cmd_byte,
rst => rst,
clk => img_clk);
testpattern_comp : entity work.pattern
generic map( SIMULATION => SIMULATION)
port map(rgb => rgb_tp,
resX => resX_tp,
resY => resY_tp,
de => de_tp,
pclk => pclk_tp,
vsync => vsync_tp,
hsync => hsync_tp,
clk => clk,
rst_n => rst_n);
controller_comp : entity work.controller
port map(
status => status,
usb_cmd => usb_cmd,
jpeg_encoder_cmd => jpeg_encoder_cmd,
selector_cmd => selector_cmd,
HB_on => HB_on,
uart_rd => rd_uart_s,
uart_rx_empty => rx_empty_s,
uart_din => uart_din_s,
uart_clk => clk_50Mhz,
usb_or_uart => sw(1),
hdmi_cmd => hdmi_cmd,
hdmi_dvi => dvi_only,
rdy_H => (rdy_H1 & rdy_H0),
btnu => btnu_s,
btnd => btnd_s,
btnl => btnl_s,
btnr => btnr_s,
uvc_rst => uvc_rst,
cmd_byte => cmd_byte,
cmd_en => cmd_en,
rst => rst,
ifclk => fx2_ifclk,
clk => img_clk);
debug_module: entity work.debug_top
port map(
clk => clk,
clk_50Mhz => clk_50Mhz,
rst => rst,
vsync => vsync,
no_frame_read => no_frame_read,
pktend => pktend_s,
jpg_busy => jpg_busy,
write_img => write_img,
sw => sw,
uart_en => uart_en,
frame_size => frame_size,
de_H0 => de_H0,
vsync_H0 => vsync_H0,
hsync_H0 => hsync_H0,
de_H1 => de_H1,
vsync_H1 => vsync_H1,
hsync_H1 => hsync_H1,
jpgORraw => usb_cmd(1),
input_source => selector_cmd(0) & selector_cmd(1),
encoding_Q => jpeg_encoder_cmd(1 downto 0),
resX => resX,
resY => resY,
eof_jpg => eof_jpg,
debug_byte => debug_byte,
debug_index => debug_index,
uart_byte => uart_byte
);
uart_module: entity work.uart
port map(
clk => clk_50Mhz,
reset => rst,
rd_uart => rd_uart_s,
r_data => uart_din_s,
rx_empty => rx_empty_s,
wr_uart => uart_en,
rx => rx,
w_data => uart_byte,
tx => tx
);
end architecture rtl;
| bsd-2-clause | 8f00f2bcce1cc5d514dbadcd725d1f43 | 0.545359 | 2.969296 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/closest_to_point.vhd | 1 | 6,265 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: closest_to_point_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity closest_to_point_top is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
u_in : in node_data_type;
point : in data_type_ext; -- assume always ext!!
point_list_d : in data_type; -- assume FIFO interface !!!
point_list_idx : in centre_index_type;
max_idx : out centre_index_type;
min_point : out data_type;
min_index : out centre_index_type;
point_list_d_out : out data_type; -- feed input to output
point_list_idx_out : out centre_index_type; -- feed input to output
u_out : out node_data_type;
closest_n_first_rdy : out std_logic;
point_list_rdy : out std_logic
);
end closest_to_point_top;
architecture Behavioral of closest_to_point_top is
type state_type is (idle, processing);
constant LAT_DOT_PRODUCT : integer := MUL_CORE_LATENCY+2*integer(ceil(log2(real(D))));
constant LAT_SUB : integer := 2;
constant LATENCY : integer := LAT_DOT_PRODUCT+LAT_SUB;
type node_data_delay_type is array(0 to LATENCY-1) of node_data_type;
component compute_distance_top
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
point_1 : in data_type_ext;
point_2 : in data_type_ext;
point_2_idx : in centre_index_type;
distance : out coord_type_ext;
point_1_out : out data_type_ext;
point_2_out : out data_type_ext;
point_2_idx_out : out centre_index_type;
rdy : out std_logic
);
end component;
component min_search is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
metric_in : in coord_type_ext;
u_in : in node_data_type;
point_in : in data_type;
point_idx_in : in centre_index_type;
min_point : out data_type;
min_index : out centre_index_type;
max_idx : out centre_index_type;
u_out : out node_data_type;
rdy : out std_logic
);
end component;
signal reg_u_in : node_data_type;
signal reg_point : data_type_ext;
signal reg_point_list_d : data_type;
signal reg_point_list_idx : centre_index_type;
signal state : state_type;
signal compute_distance_nd : std_logic;
signal compute_distance_rdy : std_logic;
signal distance : coord_type_ext;
signal point_list_d_delayed_ext : data_type_ext;
signal point_list_d_delayed : data_type;
signal point_list_idx_delayed : centre_index_type;
signal tmp_min_index : centre_index_type;
signal tmp_min_point : data_type;
signal tmp_min_search_rdy : std_logic;
signal node_data_delay : node_data_delay_type;
begin
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
state <= idle;
elsif state = idle AND nd='1' then
state <= processing;
elsif state = processing AND nd='0' then
state <= idle;
end if;
end if;
end process fsm_proc;
-- need to delay by one cycle due to state machine
reg_point_list_d_proc : process(clk)
begin
if rising_edge(clk) then
if state = idle AND nd='1' then
reg_u_in <= u_in;
reg_point <= point;
end if;
reg_point_list_d <= point_list_d;
reg_point_list_idx <= point_list_idx;
end if;
end process reg_point_list_d_proc;
compute_distance_nd <= '1' WHEN state = processing ELSE '0';
compute_distance_top_inst : compute_distance_top
port map (
clk => clk,
sclr => sclr,
nd => compute_distance_nd,
point_1 => reg_point,
point_2 => conv_normal_2_ext(reg_point_list_d),
point_2_idx => reg_point_list_idx,
distance => distance,
point_1_out => open,
point_2_out => point_list_d_delayed_ext,
point_2_idx_out => point_list_idx_delayed,
rdy => compute_distance_rdy
);
point_list_d_delayed <= conv_ext_2_normal(point_list_d_delayed_ext);
-- feed u_in from input of dot-product to output of dot-product
data_delay_proc : process(clk)
begin
if rising_edge(clk) then
node_data_delay(0) <= reg_u_in;
node_data_delay(1 to LATENCY-1) <= node_data_delay(0 to LATENCY-2);
end if;
end process data_delay_proc;
-- search min
min_search_inst : min_search
port map (
clk => clk,
sclr => sclr,
nd => compute_distance_rdy,
metric_in => distance,
u_in => node_data_delay(LATENCY-1),
point_in => point_list_d_delayed,
point_idx_in => point_list_idx_delayed,
min_point => tmp_min_point,
min_index => tmp_min_index,
max_idx => max_idx,
u_out => u_out,
rdy => tmp_min_search_rdy
);
min_point <= tmp_min_point;
min_index <= tmp_min_index;
closest_n_first_rdy <= tmp_min_search_rdy;
point_list_d_out <= point_list_d_delayed;
point_list_idx_out <= point_list_idx_delayed;
point_list_rdy <= compute_distance_rdy;
end Behavioral;
| bsd-3-clause | e2e4f31a06d1325a5c80aac071a830fc | 0.538228 | 3.785498 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-2/multicycle_datapath.vhd | 1 | 5,103 | library IEEE;
use ieee.std_logic_1164.all;
entity multicycle_datapath is
port(
clk, rst, pre, ce : in std_logic
);
end multicycle_datapath;
architecture behav of multicycle_datapath is
signal pcWriteCond, pcWrite, IorD, memRead, memWrite, memToReg, irWrite, ALUSrcA, regWrite, regDst, pcControl, ALUZeroCond, bne, branch_type, branch, less, ainvert, binvert, cin, cout, set, overflow : std_logic;
signal pcSource, ALUSrcB, ALUOp, AluCuOp : std_logic_vector(1 downto 0);
signal instr31_26, instr5_0 : std_logic_vector(5 downto 0);
signal instr25_21, instr20_16, instr15_11, writeReg : std_logic_vector(4 downto 0);
signal instr15_0 : std_logic_vector(15 downto 0);
signal instr25_0 : std_logic_vector(25 downto 0);
signal pcIn, pcOut, ALU_BUF_IN, ALU_BUF_OUT, address, A_BUF_IN, A_BUF_OUT, B_BUF_IN, B_BUF_OUT, memDataIn, memDataOut, writeData, sign_extend_out, shift_left_2_sign_extend, immediate_four, ALU_A_IN, ALU_B_IN, instr25_0_32_bit, jump28 : std_logic_vector(31 downto 0);
signal operation : std_logic_vector(2 downto 0);
begin
pcControl <= pcWrite or (pcWriteCond and branch);
immediate_four <= "00000000000000000000000000000100";
jump28(31) <= pcOut(31);
jump28(30) <= pcOut(30);
jump28(29) <= pcOut(29);
jump28(28) <= pcOut(28);
cin <= '0';
less <= '0';
ainvert <= '0';
set <= '0';
overflow <= '0';
instr25_0_32_bit(31) <= '0';
instr25_0_32_bit(30) <= '0';
instr25_0_32_bit(29) <= '0';
instr25_0_32_bit(28) <= '0';
instr25_0_32_bit(27) <= '0';
instr25_0_32_bit(26) <= '0';
instr25_0_32_bit(25) <= instr25_0(25);
instr25_0_32_bit(24) <= instr25_0(24);
instr25_0_32_bit(23) <= instr25_0(23);
instr25_0_32_bit(22) <= instr25_0(22);
instr25_0_32_bit(21) <= instr25_0(21);
instr25_0_32_bit(20) <= instr25_0(20);
instr25_0_32_bit(19) <= instr25_0(19);
instr25_0_32_bit(18) <= instr25_0(18);
instr25_0_32_bit(17) <= instr25_0(17);
instr25_0_32_bit(16) <= instr25_0(16);
instr25_0_32_bit(15) <= instr25_0(15);
instr25_0_32_bit(14) <= instr25_0(14);
instr25_0_32_bit(13) <= instr25_0(13);
instr25_0_32_bit(12) <= instr25_0(12);
instr25_0_32_bit(11) <= instr25_0(11);
instr25_0_32_bit(10) <= instr25_0(10);
instr25_0_32_bit(9) <= instr25_0(9);
instr25_0_32_bit(8) <= instr25_0(8);
instr25_0_32_bit(7) <= instr25_0(7);
instr25_0_32_bit(6) <= instr25_0(6);
instr25_0_32_bit(5) <= instr25_0(5);
instr25_0_32_bit(4) <= instr25_0(4);
instr25_0_32_bit(3) <= instr25_0(3);
instr25_0_32_bit(2) <= instr25_0(2);
instr25_0_32_bit(1) <= instr25_0(1);
instr25_0_32_bit(0) <= instr25_0(0);
AluCuOp(1) <= operation(1);
AluCuOp(0) <= operation(0);
BEQ_MUX : entity work.two_to_one_mux_1_bit(behav) port map(ALUZeroCond, bne, branch_type, branch);
alu_cu : entity work.alu_cu(behav) port map(instr5_0, ALUOp, instr31_26, operation);
control_unit : entity work.control_unit(behav) port map(instr31_26, clk, pcWriteCond, pcWrite, IorD, memRead, memWrite, memToReg, irWrite, ALUSrcA, regWrite, regDst, branch_type, pcSource, ALUSrcB, ALUOp);
instruction_register : entity work.instr_reg(behav) port map(memDataIn, irWrite, instr31_26, instr5_0, instr25_21, instr20_16, instr15_11, instr15_0, instr25_0);
writeRegMux : entity work.two_to_one_mux_5_bit(behav) port map(instr20_16, instr15_11, regDst, writeReg);
register_file : entity work.registers(behav) port map(instr25_21, instr20_16, writeReg, writeData, clk, rst, pre, regWrite, A_BUF_IN, B_BUF_IN);
writeDataMux : entity work.two_to_one_mux(behav) port map(ALU_BUF_OUT, memDataOut, memToReg, writeData);
memDataReg : entity work.memory_data_register(behav) port map(memDataIn, clk, rst, pre, ce, memDataOut);
RAM : entity work.memory(behav) port map(address, B_BUF_OUT, clk, memRead, memWrite, memDataIn);
PC : entity work.program_counter(behav) port map(pcIn, clk, rst, pre, ce, pcControl, pcOut);
PC_MUX : entity work.two_to_one_mux(behav) port map(pcOut, ALU_BUF_OUT, IorD, address);
sign_extend : entity work.sign_extend(behav) port map(instr15_0, clk, rst, pre, ce, sign_extend_out);
shift_left_2_ALU_B_MUX : entity work.shift_register_by2(behav) port map(sign_extend_out, shift_left_2_sign_extend);
ALU_B_MUX : entity work.four_to_one_mux(behav) port map(B_BUF_OUT, immediate_four, sign_extend_out, shift_left_2_sign_extend, ALUSrcB, ALU_B_IN);
A_BUF : entity work.A(behav) port map(A_BUF_IN, clk, rst, pre, ce, A_BUF_OUT);
B_BUF : entity work.B(behav) port map(B_BUF_IN, clk, rst, pre, ce, operation(2), B_BUF_OUT);
ALU_PC_A_MUX : entity work.two_to_one_mux(behav) port map(pcOut, A_BUF_OUT, ALUSrcA, ALU_A_IN);
ALU : entity work.thirty_two_bit_alu(behav) port map(ALU_A_IN, ALU_B_IN, less, ainvert, operation(2), cin, clk, rst, pre, ce, AluCuOp, ALU_BUF_IN, cout, set, overflow, ALUZeroCond, bne);
ALU_BUF : entity work.ALUOut(behav) port map(ALU_BUF_IN, clk, rst, pre, ce, ALU_BUF_OUT);
JUMP_Shift_Left : entity work.shift_register_by2(behav) port map(instr25_0_32_bit, jump28);
JUMP_MUX : entity work.four_to_one_mux(behav) port map(ALU_BUF_IN, ALU_BUF_OUT, jump28, pcIn, pcSource, pcIn);
end behav;
| gpl-3.0 | 7eae83d0028fc0d0f6ec8faa0aad17ba | 0.681756 | 2.505155 | false | false | false | false |
esar/hdmilight-v2 | fpga/lightConfigRam.vhd | 1 | 2,215 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2014 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lightConfigRam is
port (
-- Port A
a_clk : in std_logic;
a_wr : in std_logic;
a_addr : in std_logic_vector(11 downto 0);
a_din : in std_logic_vector(7 downto 0);
a_dout : out std_logic_vector(7 downto 0);
-- Port B
b_clk : in std_logic;
b_addr : in std_logic_vector(8 downto 0);
b_dout : out std_logic_vector(31 downto 0)
);
end lightConfigRam;
architecture Behavioral of lightConfigRam is
type mem_t is array (0 to 2047) of std_logic_vector(7 downto 0);
shared variable mem : mem_t := (others => "11111111");
begin
-- Port A
process(a_clk)
begin
if(rising_edge(a_clk)) then
if(a_wr = '1' and a_addr(11) = '0') then
mem(conv_integer(a_addr)) := a_din;
end if;
a_dout <= mem(conv_integer(a_addr));
end if;
end process;
-- Port B
process(b_clk)
begin
if(rising_edge(b_clk)) then
b_dout(31 downto 24) <= mem(conv_integer(b_addr & "11"));
b_dout(23 downto 16) <= mem(conv_integer(b_addr & "10"));
b_dout(15 downto 8) <= mem(conv_integer(b_addr & "01"));
b_dout( 7 downto 0) <= mem(conv_integer(b_addr & "00"));
end if;
end process;
end Behavioral;
| gpl-2.0 | bae9869ff47ff03aa871161938527ce8 | 0.595937 | 3.450156 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/source/vhdl/process_node.vhd | 1 | 2,696 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: process_node - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.lloyds_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity process_node is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
u_in : in node_data_type;
centre_positions_in : in data_type;
rdy : out std_logic;
final_index_out : out centre_index_type;
sum_sq_out : out coord_type_ext;
u_out : out node_data_type
);
end process_node;
architecture Behavioral of process_node is
component closest_to_point_top
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
u_in : in node_data_type;
point : in data_type;
point_list_d : in data_type; -- assume FIFO interface !!!
min_point : out data_type;
min_index : out centre_index_type;
min_distance : out coord_type_ext;
u_out : out node_data_type;
rdy : out std_logic
);
end component;
-- closest centre
signal closest_centre : data_type;
signal closest_index : centre_index_type;
signal closest_distance : coord_type_ext;
signal u_out_delayed : node_data_type;
signal closest_rdy : std_logic;
-- write back
signal tmp_final_index : centre_index_type;
begin
closest_to_point_inst : closest_to_point_top
port map (
clk => clk,
sclr => sclr,
nd => nd,
u_in => u_in,
point => u_in.position,
point_list_d => centre_positions_in,
min_point => closest_centre,
min_index => closest_index,
min_distance => closest_distance,
u_out => u_out_delayed,
rdy => closest_rdy
);
rdy <= closest_rdy;
final_index_out <= closest_index;
sum_sq_out <= closest_distance;
u_out <= u_out_delayed;
end Behavioral;
| bsd-3-clause | 401f8b02a0704bf222c8c681f3efa570 | 0.543769 | 4.097264 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-2/B.vhd | 1 | 30,450 | library IEEE;
use ieee.std_logic_1164.all;
entity B is
port(
B32 : in std_logic_vector(31 downto 0);
clk, rst, pre, ce, binvert : in std_logic;
output : out std_logic_vector(31 downto 0)
);
end B;
architecture behav of B is
signal bout, b2comp : std_logic_vector(31 downto 0);
begin
process(clk) is
begin
if rising_edge(clk) then
if (B32(0)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= not B32(1);
b2comp(2) <= not B32(2);
b2comp(3) <= not B32(3);
b2comp(4) <= not B32(4);
b2comp(5) <= not B32(5);
b2comp(6) <= not B32(6);
b2comp(7) <= not B32(7);
b2comp(8) <= not B32(8);
b2comp(9) <= not B32(9);
b2comp(10) <= not B32(10);
b2comp(11) <= not B32(11);
b2comp(12) <= not B32(12);
b2comp(13) <= not B32(13);
b2comp(14) <= not B32(14);
b2comp(15) <= not B32(15);
b2comp(16) <= not B32(16);
b2comp(17) <= not B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(1)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= not B32(2);
b2comp(3) <= not B32(3);
b2comp(4) <= not B32(4);
b2comp(5) <= not B32(5);
b2comp(6) <= not B32(6);
b2comp(7) <= not B32(7);
b2comp(8) <= not B32(8);
b2comp(9) <= not B32(9);
b2comp(10) <= not B32(10);
b2comp(11) <= not B32(11);
b2comp(12) <= not B32(12);
b2comp(13) <= not B32(13);
b2comp(14) <= not B32(14);
b2comp(15) <= not B32(15);
b2comp(16) <= not B32(16);
b2comp(17) <= not B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(2)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= not B32(3);
b2comp(4) <= not B32(4);
b2comp(5) <= not B32(5);
b2comp(6) <= not B32(6);
b2comp(7) <= not B32(7);
b2comp(8) <= not B32(8);
b2comp(9) <= not B32(9);
b2comp(10) <= not B32(10);
b2comp(11) <= not B32(11);
b2comp(12) <= not B32(12);
b2comp(13) <= not B32(13);
b2comp(14) <= not B32(14);
b2comp(15) <= not B32(15);
b2comp(16) <= not B32(16);
b2comp(17) <= not B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(3)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= not B32(4);
b2comp(5) <= not B32(5);
b2comp(6) <= not B32(6);
b2comp(7) <= not B32(7);
b2comp(8) <= not B32(8);
b2comp(9) <= not B32(9);
b2comp(10) <= not B32(10);
b2comp(11) <= not B32(11);
b2comp(12) <= not B32(12);
b2comp(13) <= not B32(13);
b2comp(14) <= not B32(14);
b2comp(15) <= not B32(15);
b2comp(16) <= not B32(16);
b2comp(17) <= not B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(4)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= not B32(5);
b2comp(6) <= not B32(6);
b2comp(7) <= not B32(7);
b2comp(8) <= not B32(8);
b2comp(9) <= not B32(9);
b2comp(10) <= not B32(10);
b2comp(11) <= not B32(11);
b2comp(12) <= not B32(12);
b2comp(13) <= not B32(13);
b2comp(14) <= not B32(14);
b2comp(15) <= not B32(15);
b2comp(16) <= not B32(16);
b2comp(17) <= not B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(5)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= not B32(6);
b2comp(7) <= not B32(7);
b2comp(8) <= not B32(8);
b2comp(9) <= not B32(9);
b2comp(10) <= not B32(10);
b2comp(11) <= not B32(11);
b2comp(12) <= not B32(12);
b2comp(13) <= not B32(13);
b2comp(14) <= not B32(14);
b2comp(15) <= not B32(15);
b2comp(16) <= not B32(16);
b2comp(17) <= not B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(6)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= not B32(7);
b2comp(8) <= not B32(8);
b2comp(9) <= not B32(9);
b2comp(10) <= not B32(10);
b2comp(11) <= not B32(11);
b2comp(12) <= not B32(12);
b2comp(13) <= not B32(13);
b2comp(14) <= not B32(14);
b2comp(15) <= not B32(15);
b2comp(16) <= not B32(16);
b2comp(17) <= not B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(7)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= not B32(8);
b2comp(9) <= not B32(9);
b2comp(10) <= not B32(10);
b2comp(11) <= not B32(11);
b2comp(12) <= not B32(12);
b2comp(13) <= not B32(13);
b2comp(14) <= not B32(14);
b2comp(15) <= not B32(15);
b2comp(16) <= not B32(16);
b2comp(17) <= not B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(8)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= not B32(9);
b2comp(10) <= not B32(10);
b2comp(11) <= not B32(11);
b2comp(12) <= not B32(12);
b2comp(13) <= not B32(13);
b2comp(14) <= not B32(14);
b2comp(15) <= not B32(15);
b2comp(16) <= not B32(16);
b2comp(17) <= not B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(9)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= not B32(10);
b2comp(11) <= not B32(11);
b2comp(12) <= not B32(12);
b2comp(13) <= not B32(13);
b2comp(14) <= not B32(14);
b2comp(15) <= not B32(15);
b2comp(16) <= not B32(16);
b2comp(17) <= not B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(10)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= not B32(11);
b2comp(12) <= not B32(12);
b2comp(13) <= not B32(13);
b2comp(14) <= not B32(14);
b2comp(15) <= not B32(15);
b2comp(16) <= not B32(16);
b2comp(17) <= not B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(11)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= not B32(12);
b2comp(13) <= not B32(13);
b2comp(14) <= not B32(14);
b2comp(15) <= not B32(15);
b2comp(16) <= not B32(16);
b2comp(17) <= not B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(12)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= not B32(13);
b2comp(14) <= not B32(14);
b2comp(15) <= not B32(15);
b2comp(16) <= not B32(16);
b2comp(17) <= not B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(13)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= not B32(14);
b2comp(15) <= not B32(15);
b2comp(16) <= not B32(16);
b2comp(17) <= not B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(14)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= not B32(15);
b2comp(16) <= not B32(16);
b2comp(17) <= not B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(15)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= B32(15);
b2comp(16) <= not B32(16);
b2comp(17) <= not B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(16)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= B32(15);
b2comp(16) <= B32(16);
b2comp(17) <= not B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(17)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= B32(15);
b2comp(16) <= B32(16);
b2comp(17) <= B32(17);
b2comp(18) <= not B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(18)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= B32(15);
b2comp(16) <= B32(16);
b2comp(17) <= B32(17);
b2comp(18) <= B32(18);
b2comp(19) <= not B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(19)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= B32(15);
b2comp(16) <= B32(16);
b2comp(17) <= B32(17);
b2comp(18) <= B32(18);
b2comp(19) <= B32(19);
b2comp(20) <= not B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(20)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= B32(15);
b2comp(16) <= B32(16);
b2comp(17) <= B32(17);
b2comp(18) <= B32(18);
b2comp(19) <= B32(19);
b2comp(20) <= B32(20);
b2comp(21) <= not B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(21)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= B32(15);
b2comp(16) <= B32(16);
b2comp(17) <= B32(17);
b2comp(18) <= B32(18);
b2comp(19) <= B32(19);
b2comp(20) <= B32(20);
b2comp(21) <= B32(21);
b2comp(22) <= not B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(22)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= B32(15);
b2comp(16) <= B32(16);
b2comp(17) <= B32(17);
b2comp(18) <= B32(18);
b2comp(19) <= B32(19);
b2comp(20) <= B32(20);
b2comp(21) <= B32(21);
b2comp(22) <= B32(22);
b2comp(23) <= not B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(23)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= B32(15);
b2comp(16) <= B32(16);
b2comp(17) <= B32(17);
b2comp(18) <= B32(18);
b2comp(19) <= B32(19);
b2comp(20) <= B32(20);
b2comp(21) <= B32(21);
b2comp(22) <= B32(22);
b2comp(23) <= B32(23);
b2comp(24) <= not B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(24)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= B32(15);
b2comp(16) <= B32(16);
b2comp(17) <= B32(17);
b2comp(18) <= B32(18);
b2comp(19) <= B32(19);
b2comp(20) <= B32(20);
b2comp(21) <= B32(21);
b2comp(22) <= B32(22);
b2comp(23) <= B32(23);
b2comp(24) <= B32(24);
b2comp(25) <= not B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(25)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= B32(15);
b2comp(16) <= B32(16);
b2comp(17) <= B32(17);
b2comp(18) <= B32(18);
b2comp(19) <= B32(19);
b2comp(20) <= B32(20);
b2comp(21) <= B32(21);
b2comp(22) <= B32(22);
b2comp(23) <= B32(23);
b2comp(24) <= B32(24);
b2comp(25) <= B32(25);
b2comp(26) <= not B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(26)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= B32(15);
b2comp(16) <= B32(16);
b2comp(17) <= B32(17);
b2comp(18) <= B32(18);
b2comp(19) <= B32(19);
b2comp(20) <= B32(20);
b2comp(21) <= B32(21);
b2comp(22) <= B32(22);
b2comp(23) <= B32(23);
b2comp(24) <= B32(24);
b2comp(25) <= B32(25);
b2comp(26) <= B32(26);
b2comp(27) <= not B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(27)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= B32(15);
b2comp(16) <= B32(16);
b2comp(17) <= B32(17);
b2comp(18) <= B32(18);
b2comp(19) <= B32(19);
b2comp(20) <= B32(20);
b2comp(21) <= B32(21);
b2comp(22) <= B32(22);
b2comp(23) <= B32(23);
b2comp(24) <= B32(24);
b2comp(25) <= B32(25);
b2comp(26) <= B32(26);
b2comp(27) <= B32(27);
b2comp(28) <= not B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(28)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= B32(15);
b2comp(16) <= B32(16);
b2comp(17) <= B32(17);
b2comp(18) <= B32(18);
b2comp(19) <= B32(19);
b2comp(20) <= B32(20);
b2comp(21) <= B32(21);
b2comp(22) <= B32(22);
b2comp(23) <= B32(23);
b2comp(24) <= B32(24);
b2comp(25) <= B32(25);
b2comp(26) <= B32(26);
b2comp(27) <= B32(27);
b2comp(28) <= B32(28);
b2comp(29) <= not B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(29)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= B32(15);
b2comp(16) <= B32(16);
b2comp(17) <= B32(17);
b2comp(18) <= B32(18);
b2comp(19) <= B32(19);
b2comp(20) <= B32(20);
b2comp(21) <= B32(21);
b2comp(22) <= B32(22);
b2comp(23) <= B32(23);
b2comp(24) <= B32(24);
b2comp(25) <= B32(25);
b2comp(26) <= B32(26);
b2comp(27) <= B32(27);
b2comp(28) <= B32(28);
b2comp(29) <= B32(29);
b2comp(30) <= not B32(30);
b2comp(31) <= not B32(31);
elsif (B32(30)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= B32(15);
b2comp(16) <= B32(16);
b2comp(17) <= B32(17);
b2comp(18) <= B32(18);
b2comp(19) <= B32(19);
b2comp(20) <= B32(20);
b2comp(21) <= B32(21);
b2comp(22) <= B32(22);
b2comp(23) <= B32(23);
b2comp(24) <= B32(24);
b2comp(25) <= B32(25);
b2comp(26) <= B32(26);
b2comp(27) <= B32(27);
b2comp(28) <= B32(28);
b2comp(29) <= B32(29);
b2comp(30) <= B32(30);
b2comp(31) <= not B32(31);
elsif (B32(31)='1') then
b2comp(0) <= B32(0);
b2comp(1) <= B32(1);
b2comp(2) <= B32(2);
b2comp(3) <= B32(3);
b2comp(4) <= B32(4);
b2comp(5) <= B32(5);
b2comp(6) <= B32(6);
b2comp(7) <= B32(7);
b2comp(8) <= B32(8);
b2comp(9) <= B32(9);
b2comp(10) <= B32(10);
b2comp(11) <= B32(11);
b2comp(12) <= B32(12);
b2comp(13) <= B32(13);
b2comp(14) <= B32(14);
b2comp(15) <= B32(15);
b2comp(16) <= B32(16);
b2comp(17) <= B32(17);
b2comp(18) <= B32(18);
b2comp(19) <= B32(19);
b2comp(20) <= B32(20);
b2comp(21) <= B32(21);
b2comp(22) <= B32(22);
b2comp(23) <= B32(23);
b2comp(24) <= B32(24);
b2comp(25) <= B32(25);
b2comp(26) <= B32(26);
b2comp(27) <= B32(27);
b2comp(28) <= B32(28);
b2comp(29) <= B32(29);
b2comp(30) <= B32(30);
b2comp(31) <= B32(31);
end if;
end if;
end process;
MUX : entity work.two_to_one_mux(behav) port map(B32, b2comp, binvert, bout);
PASB : entity work.thirty_two_bit_register(behav) port map(bout, clk, rst, pre, ce, output);
end behav; | gpl-3.0 | e3d0b74c8494909f06c415975c141b8a | 0.493202 | 1.973812 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-2/shift_register_by2.vhd | 1 | 1,093 | library IEEE;
use ieee.std_logic_1164.all;
entity shift_register_by2 is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0)
);
end shift_register_by2;
architecture behav of shift_register_by2 is
begin
output(31) <= input(29);
output(30) <= input(28);
output(29) <= input(27);
output(28) <= input(26);
output(27) <= input(25);
output(26) <= input(24);
output(25) <= input(23);
output(24) <= input(22);
output(23) <= input(21);
output(22) <= input(20);
output(21) <= input(19);
output(20) <= input(18);
output(19) <= input(17);
output(18) <= input(16);
output(17) <= input(15);
output(16) <= input(14);
output(15) <= input(13);
output(14) <= input(12);
output(13) <= input(11);
output(12) <= input(10);
output(11) <= input(9);
output(10) <= input(8);
output(9) <= input(7);
output(8) <= input(6);
output(7) <= input(5);
output(6) <= input(4);
output(5) <= input(3);
output(4) <= input(2);
output(3) <= input(1);
output(2) <= input(0);
output(1) <= '0';
output(0) <= '0';
end behav; | gpl-3.0 | 4955a13d08a3ad8104cd8bbb2485819a | 0.585544 | 2.478458 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib_helper/EdgeDetector.vhd | 1 | 2,097 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: EdgeDetector
-- Date:2011-11-25
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.helperComponents.all;
entity EdgeDetector is
generic (
RISING : std_logic := '1';
FALLING : std_logic := '0';
PULSE_WIDTH : integer := 10
);
port (
reset : in std_logic;
clk : in std_logic;
in_data : in std_logic;
pulse : out std_logic
);
end EdgeDetector;
architecture arch of EdgeDetector is
signal t_i, t_o : std_logic;
signal lastData : std_logic;
begin
process(reset, clk, t_o, in_data) begin
if reset = '1' then
t_i <= t_o;
lastData <= in_data;
elsif rising_edge(clk) then
if lastData /= in_data then
if RISING='1' and lastData='0' and in_data='1' then
t_i <= not t_o;
end if;
if FALLING='1' and lastData='1' and in_data='0' then
t_i <= not t_o;
end if;
end if;
lastData <= in_data;
end if;
end process;
spg: SinglePulseGenerator generic map (WIDTH => PULSE_WIDTH) port map (
reset => reset, clk => clk, t_in => t_i, t_out => t_o, pulse => pulse
);
end arch;
| gpl-3.0 | fc117c53868972c754001651d358044e | 0.59752 | 3.572402 | false | false | false | false |
tomoasleep/vhdl_test_script | examples/alu_depending.vhd | 2 | 1,330 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- DOCTEST DEPENDENCIES: test.vhd
-- TEST
-- a |b |control b|output|zero
-- 18 |9 |000 |0 |1
-- | |001 |27 |0
-- | |010 |27 |0
-- | |110 |9 |0
-- | |111 |0 |1
-- 18 |18 |111 |0 |1
-- 18 |19 | |1 |0
-- 18 |100 | |1 |0
-- /TEST
entity alu is
port (
a, b : in std_logic_vector(31 downto 0);
control : in std_logic_vector(2 downto 0);
output : out std_logic_vector(31 downto 0);
zero : out std_logic);
end alu;
architecture behave of alu is
signal bb : std_logic_vector(31 downto 0);
signal c : std_logic;
signal o0, o1, o2, o3 : std_logic_vector(31 downto 0);
signal out_buf : std_logic_vector(31 downto 0);
begin -- behave
c <= control(2);
bb <= not b when control(2) = '1' else b;
o0 <= a and bb;
o1 <= a or b;
o2 <= a + bb + c;
o3 <= x"0000000" & "000" & o2(31);
out_buf <= o0 when control(1 downto 0) = "00" else
o1 when control(1 downto 0) = "01" else
o2 when control(1 downto 0) = "10" else
o3 when control(1 downto 0) = "11";
output <= out_buf;
zero <= '1' when out_buf = x"00000000" else '0';
end behave;
| mit | 122b01f3a9b7de744fdff59c4c019a28 | 0.524812 | 2.747934 | false | true | false | false |
RickvanLoo/Synthesizer | audio_interface.vhd | 1 | 13,177 | -- audio_interface
--
-- This entity implements A/D and D/A capability on the Altera DE2
-- WM8731 Audio Codec. Setup of the codec requires the use of I2C
-- to set parameters located in I2C registers. Setup options can
-- be found in the SCI_REG_ROM and SCI_DAT_ROM. This entity is
-- capable of sampling at 48 kHz with 16 bit samples, one sample
-- for the left channel and one sample for the right channel.
--
-- http://courses.engr.illinois.edu/ECE298/lectures/Sound-Documentation.html
--
--
-- Version 1.0
--
-- Designer: Koushik Roy
-- April 23, 2010
--
-- Changes July 16, 2014
-- 1) unused signal INIT removed
-- 2) non IEEE packages removed (and necessary changes are made)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY audio_interface IS
PORT
(
LDATA, RDATA : IN std_logic_vector(15 downto 0); -- parallel external data inputs
clk, Reset : IN std_logic;
INIT_FINISH : OUT std_logic;
adc_full : OUT std_logic;
data_over : OUT std_logic; -- sample sync pulse
AUD_MCLK : OUT std_logic; -- Codec master clock OUTPUT
AUD_BCLK : IN std_logic; -- Digital Audio bit clock
AUD_ADCDAT : IN std_logic;
AUD_DACDAT : OUT std_logic; -- DAC data line
AUD_DACLRCK : IN std_logic; -- DAC data left/right select
AUD_ADCLRCK : IN std_logic; -- DAC data left/right select
I2C_SDAT : OUT std_logic; -- serial interface data line
I2C_SCLK : OUT std_logic; -- serial interface clock
ADCDATA : OUT std_logic_vector(31 downto 0)
);
END audio_interface;
ARCHITECTURE Behavorial OF audio_interface IS
TYPE I2C_state is (initialize, start, b0, b1, b2, b3, b4, b5, b6, b7, b_ack,
a0, a1, a2, a3, a4, a5, a6, a7, a_ack,
d0, d1, d2, d3, d4, d5, d6, d7, d_ack,
b_stop0, b_stop1, b_end);
TYPE DAC_state is (initial, sync, shift, refill, reload);
TYPE ADC_state is (adc_initial, adc_sync, adc_sync2, adc_shift, adc_ready);
signal Bcount : integer range 0 to 31;
signal adc_count : integer range 0 to 32;
signal word_count : integer range 0 to 12;
signal LRDATA : std_logic_vector(31 downto 0); -- stores L&R data
signal state, next_state : I2C_state;
signal SCI_ADDR, SCI_WORD1, SCI_WORD2 : std_logic_vector(7 downto 0);
signal i2c_counter : unsigned(9 downto 0);
signal SCLK_int, init_over, sck0, sck1, count_en, word_reset : std_logic;
signal SCLK_inhibit : std_logic;
signal dack0, dack1, bck0, bck1, adck0, adck1, flag, flag1 : std_logic;
signal adc_reg_val : std_logic_vector(31 downto 0);
CONSTANT word_limit : integer := 8;
type rom_type is array (0 to word_limit) of std_logic_vector(7 downto 0);
constant SCI_REG_ROM : rom_type := (
x"12", -- Deactivate, R9
x"01", -- Mute L/R, Load Simul, R0
x"05", -- Headphone volume - R2
x"08", -- DAC Unmute, R4
x"0A", -- DAC Stuff, R5
x"0C", -- More DAC stuff, R6
x"0E", -- Format, R7
x"10", -- Normal Mode, R8
x"12" -- Reactivate, R9
);
constant SCI_DAT_ROM : rom_type := (
"00000000", -- Deactivate - R9
"00011111", -- ADC L/R Volume - R0 Old: "00011111"
"11110101", -- Headphone volume - R2 Old: "11111001" "11110001"
"11010000", -- Select DAC - R4
"00000101", -- Turn off de-emphasis, Off with HPF, unmute; DAC Old: "00010110" - R5
"01100000", -- Device power on, ADC/DAC power on - R6
"01000011", -- Master, 16-bits, DSP mode; Old: "00001011" - R7
"00000000", -- Normal, 8kHz - R8 old : "00001100"
"00000001" -- Reactivate - R9
);
BEGIN
SCI_ADDR <= "00110100"; -- Device address
-- Load new L/R channel data on the rising edge of DACLRCK.
-- Decrease sample count
DACData_reg : process(Clk, Reset, LDATA, RDATA, dack0, dack1, Bcount, flag1)
begin
if (Reset = '0') then
LRDATA <= (OTHERS=>'0');
Bcount <= 31;
-- flag1<='1' of '0';
elsif(rising_edge(Clk)) then
if (dack0 = '1' and dack1 = '0') then -- Rising edge
LRDATA <= LDATA & RDATA;
Bcount <= 31;
flag1 <= '1';
elsif (bck0 = '1' and bck1 = '0' and flag1 = '1') then
flag1 <= '0';
elsif (bck0 = '0' and bck1 = '1') then -- BCLK falling edge
Bcount <= Bcount - 1;
end if;
end if;
end process;
-- Clock dividing counter
I2C_Count : process(Clk, Reset)
begin
if (Reset = '0') then
i2c_counter <= (OTHERS => '0');
elsif (rising_edge(Clk)) then
i2c_counter <= i2c_counter + 1;
end if;
end process;
-- Sample SCLK
SCLK_sample : process(Clk, Reset, SCLK_int)
begin
if (Reset = '0') then
sck0 <= '0';
sck1 <= '0';
elsif(rising_edge(Clk)) then
sck1 <= sck0;
sck0 <= SCLK_int;
end if;
end process;
-- Sample DALRCK
DALRCK_sample : process(Clk, Reset, AUD_DACLRCK)
begin
if (Reset = '0') then
dack0 <= '0';
dack1 <= '0';
elsif(rising_edge(Clk)) then
dack1 <= dack0;
dack0 <= AUD_DACLRCK;
end if;
end process;
-- Sample ADCLRCK
ADCLRCK_sample : process(Clk, Reset, AUD_DACLRCK)
begin
if (Reset = '0') then
adck0 <= '0';
adck1 <= '0';
elsif(rising_edge(Clk)) then
adck1 <= adck0;
adck0 <= AUD_ADCLRCK;
end if;
end process;
-- Sample BCLK
BCLK_sample : process(Clk, Reset, AUD_BCLK)
begin
if (Reset = '0') then
bck0 <= '0';
bck1 <= '0';
elsif(rising_edge(Clk)) then
bck1 <= bck0;
bck0 <= AUD_BCLK;
end if;
end process;
-- Track number of actual transmitted configuration data frames.
word_counter : process(SCLK_int, Count_EN, Reset, word_reset)
begin
if (Reset = '0' or word_reset = '1') then
word_count <= 0;
elsif(falling_edge(SCLK_int)) then
if (Count_EN = '1') then
word_count <= word_count + 1;
else
word_count <= word_count;
end if;
end if;
end process;
state_machine : process(Clk, Reset)
begin
if (Reset = '0') then
state <= initialize;
elsif(rising_edge(Clk)) then
state <= next_state;
end if;
end process;
-- Go through the I2C process, one step at a time. The state machine
-- progresses through states on the falling edge of SCLK.
next_state_i2c : process(Clk, state, SCLK_int, sck0, sck1, word_count)
begin
word_reset <= '0';
case state is
when initialize =>
if (SCLK_INT = '1') then
next_state <= start;
else
next_state <= initialize;
end if;
when start =>
if (sck0 = '0' and sck1 = '1') then
next_state <= b0; -- Start condition
else
next_state <= start;
end if;
when b0 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= b1;
else
next_state <= b0;
end if;
when b1 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= b2;
else
next_state <= b1;
end if;
when b2 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= b3;
else
next_state <= b2;
end if;
when b3 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= b4;
else
next_state <= b3;
end if;
when b4 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= b5;
else
next_state <= b4;
end if;
when b5 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= b6;
else
next_state <= b5;
end if;
when b6 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= b7;
else
next_state <= b6;
end if;
when b7 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= b_ack;
else
next_state <= b7;
end if;
when b_ack =>
if (sck0 = '0' and sck1 = '1') then
next_state <= a0; -- First ack.
else
next_state <= b_ack;
end if;
when a0 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= a1;
else
next_state <= a0;
end if;
when a1 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= a2;
else
next_state <= a1;
end if;
when a2 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= a3;
else
next_state <= a2;
end if;
when a3 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= a4;
else
next_state <= a3;
end if;
when a4 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= a5;
else
next_state <= a4;
end if;
when a5 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= a6;
else
next_state <= a5;
end if;
when a6 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= a7;
else
next_state <= a6;
end if;
when a7 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= a_ack;
else
next_state <= a7;
end if;
when a_ack =>
if (sck0 = '0' and sck1 = '1') then
next_state <= d0; -- Second ack
else
next_state <= a_ack;
end if;
when d0 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= d1;
else
next_state <= d0;
end if;
when d1 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= d2;
else
next_state <= d1;
end if;
when d2 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= d3;
else
next_state <= d2;
end if;
when d3 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= d4;
else
next_state <= d3;
end if;
when d4 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= d5;
else
next_state <= d4;
end if;
when d5 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= d6;
else
next_state <= d5;
end if;
when d6 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= d7;
else
next_state <= d6;
end if;
when d7 =>
if (sck0 = '0' and sck1 = '1') then
next_state <= d_ack; -- Last ack
else
next_state <= d7;
end if;
when d_ack =>
-- Check to see if we've transmitted the correct number
-- of words. If so, done. If not, transmit more.
if (sck0 = '0' and sck1 = '1') then
if (word_count = word_limit+1) then
next_state <= b_stop0;
else
next_state <= initialize;
end if;
else
next_state <= d_ack;
end if;
when b_stop0 =>
-- If we're done, generate a stop condition
if (SCLK_INT = '1') then
next_state <= b_stop1;
else
next_state <= b_stop0;
end if;
when b_stop1 =>
next_state <= b_end;
when b_end =>
next_state <= b_end;
word_reset <= '1';
end case;
end process;
outputs_i2c : process(state, SCI_ADDR, word_count)
begin
init_over <= '0';
count_en <= '0';
sclk_inhibit <= '0';
case state is
when initialize =>
I2C_SDAT <= '1'; -- SDAT starts high
when start =>
I2C_SDAT <= '0'; -- SDAT falling edge
when b0 =>
I2C_SDAT <= SCI_ADDR(7);
when b1 =>
I2C_SDAT <= SCI_ADDR(6);
when b2 =>
I2C_SDAT <= SCI_ADDR(5);
when b3 =>
I2C_SDAT <= SCI_ADDR(4);
when b4 =>
I2C_SDAT <= SCI_ADDR(3);
when b5 =>
I2C_SDAT <= SCI_ADDR(2);
when b6 =>
I2C_SDAT <= SCI_ADDR(1);
when b7 =>
I2C_SDAT <= SCI_ADDR(0);
when b_ack =>
I2C_SDAT <= 'Z';
when a0 =>
I2C_SDAT <= SCI_REG_ROM(word_count)(7);
when a1 =>
I2C_SDAT <= SCI_REG_ROM(word_count)(6);
when a2 =>
I2C_SDAT <= SCI_REG_ROM(word_count)(5);
when a3 =>
I2C_SDAT <= SCI_REG_ROM(word_count)(4);
when a4 =>
I2C_SDAT <= SCI_REG_ROM(word_count)(3);
when a5 =>
I2C_SDAT <= SCI_REG_ROM(word_count)(2);
when a6 =>
I2C_SDAT <= SCI_REG_ROM(word_count)(1);
when a7 =>
I2C_SDAT <= SCI_REG_ROM(word_count)(0);
when a_ack =>
I2C_SDAT <= 'Z';
when d0 =>
I2C_SDAT <= SCI_DAT_ROM(word_count)(7);
when d1 =>
I2C_SDAT <= SCI_DAT_ROM(word_count)(6);
when d2 =>
I2C_SDAT <= SCI_DAT_ROM(word_count)(5);
when d3 =>
I2C_SDAT <= SCI_DAT_ROM(word_count)(4);
when d4 =>
I2C_SDAT <= SCI_DAT_ROM(word_count)(3);
when d5 =>
I2C_SDAT <= SCI_DAT_ROM(word_count)(2);
when d6 =>
I2C_SDAT <= SCI_DAT_ROM(word_count)(1);
when d7 =>
I2C_SDAT <= SCI_DAT_ROM(word_count)(0);
when d_ack =>
I2C_SDAT <= 'Z';
count_en <= '1';
when b_stop0 =>
-- Keep SDAT at low until SCLK goes high
I2C_SDAT <= '0';
when b_stop1 =>
-- SCLK is high, so SDAT has a rising edge
I2C_SDAT <= '1';
sclk_inhibit <= '1';
when b_end =>
I2C_SDAT <= '1';
init_over <= '1';
sclk_inhibit <= '1';
end case;
end process;
adc_proc : process(Clk, bck0, bck1, adc_reg_val, adck0, adck1, Reset, adc_count, flag)
begin
if (Reset = '0') then
adc_reg_val <= (OTHERS => '0');
adc_count <= 31;
adc_full <= '0';
elsif(rising_edge(Clk)) then
adc_reg_val(adc_count) <= AUD_ADCDAT;
adc_full <= '0';
if (adc_count = 0) then
adc_full <= '1';
end if;
if (adck0 = '1' and adck1 = '0') then -- Rising edge
adc_count <= 31; -- Read in more new ADC data on a ADCLRC rising edge
elsif ( (not (adc_count = 0)) and bck0 = '0' and bck1 = '1') then -- Falling edge
adc_count <= adc_count - 1; -- When not feeding with new data, shift new bit in
end if;
end if;
end process;
SCLK_int <= I2C_counter(9) or SCLK_inhibit; -- SCLK = CLK / 512 = 97.65 kHz ~= 100 kHz
--SCLK_int <= I2C_counter(3) or SCLK_inhibit; -- For simulation only
AUD_MCLK <= I2C_counter(2); -- MCLK = CLK / 4
I2C_SCLK <= SCLK_int;
AUD_DACDAT <= LRDATA(Bcount);
data_over <= flag1;
init_finish <= init_over;
ADCDATA <= adc_reg_val;
end Behavorial;
| mit | dcb7a4cda83ef6fc3e3dc7e1460d95e9 | 0.572285 | 2.608274 | false | false | false | false |
tomoasleep/vhdl_test_script | examples/alu.vhd | 2 | 1,296 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- TEST
-- a |b |control b|output|zero
-- 18 |9 |000 |0 |1
-- | |001 |27 |0
-- | |010 |27 |0
-- | |110 |9 |0
-- | |111 |0 |1
-- 18 |18 |111 |0 |1
-- 18 |19 | |1 |0
-- 18 |100 | |1 |0
-- /TEST
entity alu is
port (
a, b : in std_logic_vector(31 downto 0);
control : in std_logic_vector(2 downto 0);
output : out std_logic_vector(31 downto 0);
zero : out std_logic);
end alu;
architecture behave of alu is
signal bb : std_logic_vector(31 downto 0);
signal c : std_logic;
signal o0, o1, o2, o3 : std_logic_vector(31 downto 0);
signal out_buf : std_logic_vector(31 downto 0);
begin -- behave
c <= control(2);
bb <= not b when control(2) = '1' else b;
o0 <= a and bb;
o1 <= a or b;
o2 <= a + bb + c;
o3 <= x"0000000" & "000" & o2(31);
out_buf <= o0 when control(1 downto 0) = "00" else
o1 when control(1 downto 0) = "01" else
o2 when control(1 downto 0) = "10" else
o3 when control(1 downto 0) = "11";
output <= out_buf;
zero <= '1' when out_buf = x"00000000" else '0';
end behave;
| mit | a14dabca6c5f2c3f98a84c0e6fe2243d | 0.518519 | 2.734177 | false | false | false | false |
Nooxet/embedded_bruteforce | vhdl/brutus_top.vhd | 2 | 10,563 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:29 09/22/2014
-- Design Name:
-- Module Name: brutus_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.hash_array_pkg.all;
entity brutus_top is
generic (
M : integer := 2
);
port (
clk : in std_logic;
rstn : in std_logic;
i_fsl_data_recv : in std_logic;
i_fsl_hash : in std_logic_vector(127 downto 0);
o_pw_found : out std_logic;
o_passwd : out std_logic_vector(47 downto 0)
);
end brutus_top;
architecture Behavioral of brutus_top is
component string_generator
port (
clk : in std_logic;
rstn : in std_logic; -- active low reset ofc
i_start : in std_logic;
i_halt : in std_logic;
o_done : out std_logic;
o_length : out std_logic_vector(2 downto 0); -- max 6 chars
o_string : out std_logic_vector(47 downto 0) -- 6 char string
);
end component;
component pre_process
Port ( i_data : in STD_LOGIC_VECTOR (47 downto 0);
i_length : in STD_LOGIC_VECTOR (2 downto 0);
o_data_0 : out unsigned (31 downto 0);
o_data_1 : out unsigned (31 downto 0);
o_length : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component md5_demux
generic (
N : integer
);
port (
i_md5_indata : in md5_indata_t;
i_select : in unsigned(N-1 downto 0); -- should be ceil(log2(N-1))
o_md5_indata_0 : out md5_indata_t; --_array(N-1 downto 0)
o_md5_indata_1 : out md5_indata_t --_array(N-1 downto 0)
);
end component;
component MD5
port (
clk : in std_logic;
rstn : in std_logic;
i_start : in std_logic;
--i_data : in unsigned(71 downto 0); -- 8 chars + 1 appended bit
i_data_0 : in unsigned(31 downto 0); -- first 4 chars
i_data_1 : in unsigned(31 downto 0); -- next 4 chars
i_length : in std_logic_vector(7 downto 0); -- nbr of chars
o_done : out std_logic;
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end component;
component md5_mux
generic (
N : integer
);
port (
clk : in std_logic;
rstn : in std_logic;
i_hash_0 : in unsigned(127 downto 0); --hash_array(N-1 downto 0);
i_hash_1 : in unsigned(127 downto 0); --hash_array(N-1 downto 0);
i_select : in unsigned(N-1 downto 0); -- should be ceil(log2(N-1))
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end component;
component comp
port(
clk : in std_logic;
rstn : in std_logic; -- active low
i_hash_0, i_hash_1, i_hash_2, i_hash_3 : in unsigned(31 downto 0); -- hash from md5
i_cmp_hash : in std_logic_vector(127 downto 0); -- hash we are going to crack
i_start : in std_logic; -- 1 when we should read i_cmp_hash
o_equal : out std_logic -- 1 if we found the matching hash, else 0
);
end component;
component controller
generic (
N : integer
);
port (
clk : in std_logic;
rstn : in std_logic;
i_fsl_data_recv : in std_logic;
i_fsl_hash : in std_logic_vector(127 downto 0);
i_comp_eq : in std_logic; -- check if password was found
i_sg_done : in std_logic; -- string generator done signal
i_sg_string : in std_logic_vector(47 downto 0); -- current potential password
i_md5_done : in std_logic; -- done signal from the main MD5 core
o_passwd_hash : out std_logic_vector(127 downto 0); -- hash from FSL
o_pw_found : out std_logic; -- flag to indicate password found
-- o_pw_nfound : out ---
o_passwd : out std_logic_vector(47 downto 0); -- password string, send to user
o_start_sg_comp : out std_logic; -- start signals to sg and comp
o_start_md5 : out std_logic; -- start signal to MD5 cores
o_halt_sg : out std_logic; -- halt signal to sg
o_demux_sel : out unsigned(M-1 downto 0); --
o_mux_sel : out unsigned(M-1 downto 0) -- select signals to DEMUX/MUX
);
end component;
signal s_len_sg_pp : std_logic_vector(2 downto 0); -- length sg->pp
signal s_len_pp_demux, s_len_demux_md5_0, s_len_demux_md5_1 : std_logic_vector(7 downto 0); -- length pp->md5
signal s_string_sg_pp : std_logic_vector(47 downto 0);
signal s_string1_pp_demux, s_string1_demux_md5_0, s_string1_demux_md5_1 : unsigned(31 downto 0);
signal s_string2_pp_demux, s_string2_demux_md5_0, s_string2_demux_md5_1 : unsigned(31 downto 0);
signal hm0_0, hm1_0, hm2_0, hm3_0 : unsigned(31 downto 0); -- hashes from md5 to mux
signal hm0_1, hm1_1, hm2_1, hm3_1 : unsigned(31 downto 0); -- hashes from md5 to mux
signal hc0_0, hc1_0, hc2_0, hc3_0 : unsigned(31 downto 0); -- hashes from mux to comp
signal comp_ctrl_eq, sg_ctrl_done, md5_ctrl_done : std_logic;
signal sg_ctrl_string : std_logic_vector(47 downto 0);
signal ctrl_comp_hash : std_logic_vector(127 downto 0);
signal ctrl_sg_comp_start : std_logic; -- start signal to sg and comp
signal ctrl_demux_start, demux_md5_start_0, demux_md5_start_1 : std_logic; -- start signal to MD5 cores
signal ctrl_sg_halt : std_logic; -- halt signal to sg
--signal ctrl_demux_sel, ctrl_mux_sel : std_logic_vector(M-1 downto 0); -- mux/demux selectors
signal s_ctrl_demux_sel, s_ctrl_mux_sel : unsigned(M-1 downto 0);
signal temp_hash_0, temp_hash_1 : unsigned(127 downto 0);
begin
controller_inst: controller
generic map (
N => M
)
port map (
clk => clk,
rstn => rstn,
i_fsl_data_recv => i_fsl_data_recv,
i_fsl_hash => i_fsl_hash,
i_comp_eq => comp_ctrl_eq,
i_sg_done => sg_ctrl_done,
i_sg_string => sg_ctrl_string,
i_md5_done => md5_ctrl_done,
o_passwd_hash => ctrl_comp_hash,
o_pw_found => o_pw_found,
o_passwd => o_passwd,
o_start_sg_comp => ctrl_sg_comp_start,
o_start_md5 => ctrl_demux_start,
o_halt_sg => ctrl_sg_halt,
o_demux_sel => s_ctrl_demux_sel,
o_mux_sel => s_ctrl_mux_sel
);
comp_inst: comp
port map (
clk => clk,
rstn => rstn,
i_cmp_hash => i_fsl_hash,
i_hash_0 => hc0_0,
i_hash_1 => hc1_0,
i_hash_2 => hc2_0,
i_hash_3 => hc3_0,
i_start => ctrl_sg_comp_start,
o_equal => comp_ctrl_eq
);
sg_ctrl_string <= s_string_sg_pp; -- string goes both to pp and controller
sg_inst: string_generator
port map (
clk => clk,
rstn => rstn,
i_start => ctrl_sg_comp_start,
i_halt => ctrl_sg_halt,
o_done => sg_ctrl_done,
o_length => s_len_sg_pp,
o_string => s_string_sg_pp
);
pp_inst: pre_process
port map(
i_data => s_string_sg_pp,
i_length => s_len_sg_pp,
o_data_0 => s_string1_pp_demux,
o_data_1 => s_string2_pp_demux,
o_length => s_len_pp_demux
);
demux_inst: md5_demux
generic map (
N => M
)
port map (
i_md5_indata.start => ctrl_demux_start,
i_md5_indata.data_0 => s_string1_pp_demux,
i_md5_indata.data_1 => s_string2_pp_demux,
i_md5_indata.len => s_len_pp_demux,
i_select => s_ctrl_demux_sel,
o_md5_indata_0.start => demux_md5_start_0,
o_md5_indata_0.data_0 => s_string1_demux_md5_0,
o_md5_indata_0.data_1 => s_string2_demux_md5_0,
o_md5_indata_0.len => s_len_demux_md5_0,
o_md5_indata_1.start => demux_md5_start_1,
o_md5_indata_1.data_0 => s_string1_demux_md5_1,
o_md5_indata_1.data_1 => s_string2_demux_md5_1,
o_md5_indata_1.len => s_len_demux_md5_1
);
MD5_inst_0: MD5
port map (
clk => clk,
rstn => rstn,
i_start => demux_md5_start_0,
i_data_0 => s_string1_demux_md5_0,
i_data_1 => s_string2_demux_md5_0,
i_length => s_len_demux_md5_0,
o_done => md5_ctrl_done, -- only first md5 connected to controller
o_hash_0 => hm0_0, --o_hash(31 downto 0),
o_hash_1 => hm1_0, --o_hash(63 downto 32),
o_hash_2 => hm2_0, --o_hash(95 downto 64),
o_hash_3 => hm3_0 --o_hash(127 downto 96)
);
MD5_inst_1: MD5
port map (
clk => clk,
rstn => rstn,
i_start => demux_md5_start_1,
i_data_0 => s_string1_demux_md5_1,
i_data_1 => s_string2_demux_md5_1,
i_length => s_len_demux_md5_1,
o_done => open,
o_hash_0 => hm0_1, --o_hash(31 downto 0),
o_hash_1 => hm1_1, --o_hash(63 downto 32),
o_hash_2 => hm2_1, --o_hash(95 downto 64),
o_hash_3 => hm3_1 --o_hash(127 downto 96)
);
temp_hash_0 <= hm0_0 & hm1_0 & hm2_0 & hm3_0;
temp_hash_1 <= hm0_1 & hm1_1 & hm2_1 & hm3_1;
mux_inst: md5_mux
generic map (
N => M
)
port map (
clk => clk,
rstn => rstn,
i_hash_0 => temp_hash_0,
i_hash_1 => temp_hash_1,
i_select => s_ctrl_mux_sel,
o_hash_0 => hc0_0,
o_hash_1 => hc1_0,
o_hash_2 => hc2_0,
o_hash_3 => hc3_0
);
end Behavioral;
| mit | dbdedb5118e650caada727571c828bee | 0.516236 | 3.122377 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/system_proc_sys_reset_0_wrapper.vhd | 1 | 4,214 | -------------------------------------------------------------------------------
-- system_proc_sys_reset_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library proc_sys_reset_v3_00_a;
use proc_sys_reset_v3_00_a.all;
entity system_proc_sys_reset_0_wrapper is
port (
Slowest_sync_clk : in std_logic;
Ext_Reset_In : in std_logic;
Aux_Reset_In : in std_logic;
MB_Debug_Sys_Rst : in std_logic;
Core_Reset_Req_0 : in std_logic;
Chip_Reset_Req_0 : in std_logic;
System_Reset_Req_0 : in std_logic;
Core_Reset_Req_1 : in std_logic;
Chip_Reset_Req_1 : in std_logic;
System_Reset_Req_1 : in std_logic;
Dcm_locked : in std_logic;
RstcPPCresetcore_0 : out std_logic;
RstcPPCresetchip_0 : out std_logic;
RstcPPCresetsys_0 : out std_logic;
RstcPPCresetcore_1 : out std_logic;
RstcPPCresetchip_1 : out std_logic;
RstcPPCresetsys_1 : out std_logic;
MB_Reset : out std_logic;
Bus_Struct_Reset : out std_logic_vector(0 to 0);
Peripheral_Reset : out std_logic_vector(0 to 0);
Interconnect_aresetn : out std_logic_vector(0 to 0);
Peripheral_aresetn : out std_logic_vector(0 to 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_proc_sys_reset_0_wrapper : entity is "proc_sys_reset_v3_00_a";
end system_proc_sys_reset_0_wrapper;
architecture STRUCTURE of system_proc_sys_reset_0_wrapper is
component proc_sys_reset is
generic (
C_EXT_RST_WIDTH : integer;
C_AUX_RST_WIDTH : integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic;
C_NUM_BUS_RST : integer;
C_NUM_PERP_RST : integer;
C_NUM_INTERCONNECT_ARESETN : integer;
C_NUM_PERP_ARESETN : integer
);
port (
Slowest_sync_clk : in std_logic;
Ext_Reset_In : in std_logic;
Aux_Reset_In : in std_logic;
MB_Debug_Sys_Rst : in std_logic;
Core_Reset_Req_0 : in std_logic;
Chip_Reset_Req_0 : in std_logic;
System_Reset_Req_0 : in std_logic;
Core_Reset_Req_1 : in std_logic;
Chip_Reset_Req_1 : in std_logic;
System_Reset_Req_1 : in std_logic;
Dcm_locked : in std_logic;
RstcPPCresetcore_0 : out std_logic;
RstcPPCresetchip_0 : out std_logic;
RstcPPCresetsys_0 : out std_logic;
RstcPPCresetcore_1 : out std_logic;
RstcPPCresetchip_1 : out std_logic;
RstcPPCresetsys_1 : out std_logic;
MB_Reset : out std_logic;
Bus_Struct_Reset : out std_logic_vector(0 to C_NUM_BUS_RST-1);
Peripheral_Reset : out std_logic_vector(0 to C_NUM_PERP_RST-1);
Interconnect_aresetn : out std_logic_vector(0 to C_NUM_INTERCONNECT_ARESETN-1);
Peripheral_aresetn : out std_logic_vector(0 to C_NUM_PERP_ARESETN-1)
);
end component;
begin
proc_sys_reset_0 : proc_sys_reset
generic map (
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '1',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
port map (
Slowest_sync_clk => Slowest_sync_clk,
Ext_Reset_In => Ext_Reset_In,
Aux_Reset_In => Aux_Reset_In,
MB_Debug_Sys_Rst => MB_Debug_Sys_Rst,
Core_Reset_Req_0 => Core_Reset_Req_0,
Chip_Reset_Req_0 => Chip_Reset_Req_0,
System_Reset_Req_0 => System_Reset_Req_0,
Core_Reset_Req_1 => Core_Reset_Req_1,
Chip_Reset_Req_1 => Chip_Reset_Req_1,
System_Reset_Req_1 => System_Reset_Req_1,
Dcm_locked => Dcm_locked,
RstcPPCresetcore_0 => RstcPPCresetcore_0,
RstcPPCresetchip_0 => RstcPPCresetchip_0,
RstcPPCresetsys_0 => RstcPPCresetsys_0,
RstcPPCresetcore_1 => RstcPPCresetcore_1,
RstcPPCresetchip_1 => RstcPPCresetchip_1,
RstcPPCresetsys_1 => RstcPPCresetsys_1,
MB_Reset => MB_Reset,
Bus_Struct_Reset => Bus_Struct_Reset,
Peripheral_Reset => Peripheral_Reset,
Interconnect_aresetn => Interconnect_aresetn,
Peripheral_aresetn => Peripheral_aresetn
);
end architecture STRUCTURE;
| mit | 3681a2dc349096ee921b558736c7ed3c | 0.616991 | 3.299922 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/pruning_test.vhd | 1 | 15,628 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: madd - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pruning_test is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
cand : in data_type;
closest_cand : in data_type;
bnd_lo : in data_type;
bnd_hi : in data_type;
result : out std_logic;
rdy : out std_logic
);
end pruning_test;
architecture Behavioral of pruning_test is
constant SUB_LATENCY : integer := 2;
constant LAYERS_TREE_ADDER : integer := integer(ceil(log2(real(D))));
constant SCALE_MUL_RESULT : integer := MUL_FRACTIONAL_BITS;
-- latency of the entire unit
constant LATENCY : integer := 2*SUB_LATENCY+MUL_CORE_LATENCY+SUB_LATENCY*LAYERS_TREE_ADDER;
type sub_res_array_type is array(0 to D-1) of std_logic_vector(COORD_BITWIDTH+1-1 downto 0);
type sub_res_array_delay_type is array(0 to SUB_LATENCY-1) of sub_res_array_type;
type mul_res_array_type is array(0 to D-1) of std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1-1 downto 0);
--type tree_adder_res_array_type is array(0 to LAYERS_TREE_ADDER-1, 0 to D/2-1) of std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
type data_delay_type is array(0 to SUB_LATENCY-1) of data_type;
component addorsub
generic (
USE_DSP : boolean := true;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
component madd
generic (
MUL_LATENCY : integer := 3;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
INCLUDE_ADD : boolean := false;
C_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
c : in std_logic_vector(C_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
component adder_tree
generic (
NUMBER_OF_INPUTS : integer := 4;
INPUT_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
input_string : in std_logic_vector(NUMBER_OF_INPUTS*INPUT_BITWIDTH-1 downto 0);
rdy : out std_logic;
output : out std_logic_vector(INPUT_BITWIDTH+integer(ceil(log2(real(NUMBER_OF_INPUTS))))-1 downto 0)
);
end component;
signal tmp_diff_1 : sub_res_array_type;
signal tmp_diff_1_rdy : std_logic;
signal tmp_input_2 : data_type;
signal tmp_diff_2 : sub_res_array_type;
signal tmp_diff_2_rdy : std_logic;
signal diff_1_delay_line : sub_res_array_delay_type;
signal tmp_diff_1_1 : sub_res_array_type;
signal tmp_mul_1 : mul_res_array_type;
signal tmp_mul_1_rdy : std_logic;
signal tmp_mul_2 : mul_res_array_type;
signal tmp_mul_2_rdy : std_logic;
signal const_0 : std_logic_vector(MUL_BITWIDTH-1 downto 0);
--signal tmp_tree_adder_res_1 : tree_adder_res_array_type;
signal tmp_tree_adder_1_input_string : std_logic_vector(D*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)-1 downto 0);
signal tmp_tree_adder_res_1_clean : std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
signal tmp_tree_adder_res_1_ext : std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER+1-1 downto 0);
signal tmp_tree_adder_1_rdy : std_logic;
--signal tmp_tree_adder_res_2 : tree_adder_res_array_type;
signal tmp_tree_adder_2_input_string : std_logic_vector(D*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)-1 downto 0);
signal tmp_tree_adder_res_2_clean : std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
signal tmp_tree_adder_res_2_ext : std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER+1-1 downto 0);
--signal delay_line_tree_adder : std_logic_vector(0 to SUB_LATENCY*LAYERS_TREE_ADDER-1);
signal bndbox_delay_lo : data_delay_type;
signal bndbox_delay_hi : data_delay_type;
signal closest_cand_delay : data_delay_type;
signal tmp_final_result : std_logic;
begin
G1: for I in 0 to D-1 generate
G_FIRST: if I = 0 generate
addorsub_inst : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => COORD_BITWIDTH,
B_BITWIDTH => COORD_BITWIDTH,
RES_BITWIDTH => COORD_BITWIDTH+1
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
sub => '1',
a => cand(I),
b => closest_cand(I),
res => tmp_diff_1(I), -- ccComp
rdy => tmp_diff_1_rdy
);
end generate G_FIRST;
G_OTHER: if I > 0 generate
addorsub_inst : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => COORD_BITWIDTH,
B_BITWIDTH => COORD_BITWIDTH,
RES_BITWIDTH => COORD_BITWIDTH+1
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
sub => '1',
a => cand(I),
b => closest_cand(I),
res => tmp_diff_1(I), --ccComp
rdy => open
);
end generate G_OTHER;
end generate G1;
-- delay bndbox
bndbox_delay_proc : process(clk)
begin
if rising_edge(clk) then
bndbox_delay_lo(0) <= bnd_lo;
bndbox_delay_lo(1 to SUB_LATENCY-1) <= bndbox_delay_lo(0 to SUB_LATENCY-2);
bndbox_delay_hi(0) <= bnd_hi;
bndbox_delay_hi(1 to SUB_LATENCY-1) <= bndbox_delay_hi(0 to SUB_LATENCY-2);
closest_cand_delay(0) <= closest_cand;
closest_cand_delay(1 to SUB_LATENCY-1) <= closest_cand_delay(0 to SUB_LATENCY-2);
end if;
end process bndbox_delay_proc;
G2: for I in 0 to D-1 generate
tmp_input_2(I) <= bndbox_delay_hi(SUB_LATENCY-1)(I) WHEN signed(tmp_diff_1(I)) > 0 ELSE bndbox_delay_lo(SUB_LATENCY-1)(I);
G_FIRST: if I = 0 generate
addorsub_inst : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => COORD_BITWIDTH,
B_BITWIDTH => COORD_BITWIDTH,
RES_BITWIDTH => COORD_BITWIDTH+1
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_diff_1_rdy,
sub => '1',
a => tmp_input_2(I),
b => closest_cand_delay(SUB_LATENCY-1)(I),
res => tmp_diff_2(I),
rdy => tmp_diff_2_rdy
);
end generate G_FIRST;
G_OTHER: if I > 0 generate
addorsub_inst : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => COORD_BITWIDTH,
B_BITWIDTH => COORD_BITWIDTH,
RES_BITWIDTH => COORD_BITWIDTH+1
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_diff_1_rdy,
sub => '1',
a => tmp_input_2(I),
b => closest_cand_delay(SUB_LATENCY-1)(I),
res => tmp_diff_2(I),
rdy => open
);
end generate G_OTHER;
end generate G2;
-- delay tmp_diff_1
diff_1_delay_line_proc : process(clk)
begin
if rising_edge(clk) then
diff_1_delay_line(0) <= tmp_diff_1;
diff_1_delay_line(1 to SUB_LATENCY-1) <= diff_1_delay_line(0 to SUB_LATENCY-2);
end if;
end process diff_1_delay_line_proc;
tmp_diff_1_1 <= diff_1_delay_line(SUB_LATENCY-1);
const_0 <= (others => '0');
G3: for I in 0 to D-1 generate
G_FIRST: if I = 0 generate
madd_inst_1 : madd
generic map(
MUL_LATENCY => MUL_CORE_LATENCY,
A_BITWIDTH => MUL_BITWIDTH,
B_BITWIDTH => MUL_BITWIDTH,
INCLUDE_ADD => false,
C_BITWIDTH => MUL_BITWIDTH,
RES_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_diff_2_rdy,
a => saturate(tmp_diff_1_1(I)),
b => saturate(tmp_diff_1_1(I)),
c => const_0,
res => tmp_mul_1(I),
rdy => tmp_mul_1_rdy
);
madd_inst_2 : madd
generic map(
MUL_LATENCY => MUL_CORE_LATENCY,
A_BITWIDTH => MUL_BITWIDTH,
B_BITWIDTH => MUL_BITWIDTH,
INCLUDE_ADD => false,
C_BITWIDTH => MUL_BITWIDTH,
RES_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_diff_2_rdy,
a => saturate(tmp_diff_2(I)),
b => saturate(tmp_diff_1_1(I)),
c => const_0,
res => tmp_mul_2(I),
rdy => tmp_mul_2_rdy
);
end generate G_FIRST;
G_OTHER: if I > 0 generate
madd_inst_1 : madd
generic map(
MUL_LATENCY => MUL_CORE_LATENCY,
A_BITWIDTH => MUL_BITWIDTH,
B_BITWIDTH => MUL_BITWIDTH,
INCLUDE_ADD => false,
C_BITWIDTH => MUL_BITWIDTH,
RES_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_diff_2_rdy,
a => saturate(tmp_diff_1_1(I)),
b => saturate(tmp_diff_1_1(I)),
c => const_0,
res => tmp_mul_1(I),
rdy => open
);
madd_inst_2 : madd
generic map(
MUL_LATENCY => MUL_CORE_LATENCY,
A_BITWIDTH => MUL_BITWIDTH,
B_BITWIDTH => MUL_BITWIDTH,
INCLUDE_ADD => false,
C_BITWIDTH => MUL_BITWIDTH,
RES_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_diff_2_rdy,
a => saturate(tmp_diff_2(I)),
b => saturate(tmp_diff_1_1(I)),
c => const_0,
res => tmp_mul_2(I),
rdy => open
);
end generate G_OTHER;
end generate G3;
-- adder trees
G4 : for I in 0 to D-1 generate
tmp_tree_adder_1_input_string((I+1)*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)-1 downto I*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)) <= tmp_mul_1(I);
tmp_tree_adder_2_input_string((I+1)*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)-1 downto I*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)) <= tmp_mul_2(I);
end generate G4;
adder_tree_inst_1 : adder_tree
generic map (
NUMBER_OF_INPUTS => D,
INPUT_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map(
clk => clk,
sclr => sclr,
nd => tmp_mul_1_rdy,
sub => '0',
input_string => tmp_tree_adder_1_input_string,
rdy => tmp_tree_adder_1_rdy,
output => tmp_tree_adder_res_1_clean
);
adder_tree_inst_2 : adder_tree
generic map (
NUMBER_OF_INPUTS => D,
INPUT_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map(
clk => clk,
sclr => sclr,
nd => tmp_mul_1_rdy,
sub => '0',
input_string => tmp_tree_adder_2_input_string,
rdy => open,
output => tmp_tree_adder_res_2_clean
);
-- 1*tmp_tree_adder_res_1_clean (always positive)
tmp_tree_adder_res_1_ext <= '0' & tmp_tree_adder_res_1_clean;
-- 2*tmp_tree_adder_res_2_clean
tmp_tree_adder_res_2_ext <= tmp_tree_adder_res_2_clean & '0';
--tmp_final_result <= '1';-- WHEN signed(tmp_tree_adder_res_1_ext) > signed(tmp_tree_adder_res_2_ext) ELSE '0';
--rdy <= delay_line_tree_adder(SUB_LATENCY*LAYERS_TREE_ADDER-1);
rdy <= tmp_tree_adder_1_rdy;
result <= '1' WHEN signed(tmp_tree_adder_res_1_ext) > signed(tmp_tree_adder_res_2_ext) ELSE '0';
end Behavioral;
| bsd-3-clause | d25a95809bf46e9cbb12c423099740aa | 0.45924 | 4.050804 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-2/four_to_one_mux.vhd | 1 | 564 | library IEEE;
use ieee.std_logic_1164.all;
entity four_to_one_mux is
port(
a, b, c, d : in std_logic_vector(31 downto 0);
sel : in std_logic_vector(1 downto 0);
output : out std_logic_vector(31 downto 0)
);
end entity four_to_one_mux;
architecture behav of four_to_one_mux is
begin
--output <= (a and (not sel(0)) and (not sel(1))) or (b and sel(0) and (not sel(1))) or (c and (not sel(0)) and sel(1)) or (d and sel(0) and sel(1));
output <= a when (sel = "00") else b when (sel = "01") else c when (sel = "10") else d when (sel = "11");
end behav; | gpl-3.0 | 47b3fcdbb99ac9440520124d86028825 | 0.62766 | 2.575342 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/source/vhdl/closest_to_point.vhd | 1 | 5,308 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: closest_to_point_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.lloyds_algorithm_pkg.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity closest_to_point_top is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
u_in : in node_data_type;
point : in data_type;
point_list_d : in data_type; -- assume FIFO interface !!!
min_point : out data_type;
min_index : out centre_index_type;
min_distance : out coord_type_ext;
u_out : out node_data_type;
rdy : out std_logic
);
end closest_to_point_top;
architecture Behavioral of closest_to_point_top is
type state_type is (idle, processing);
constant LAT_DOT_PRODUCT : integer := 3+2*integer(ceil(log2(real(D))));
constant LAT_SUB : integer := 2;
constant LATENCY : integer := LAT_DOT_PRODUCT+LAT_SUB;
type node_data_delay_type is array(0 to LATENCY-1) of node_data_type;
component compute_distance_top
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
point_1 : in data_type;
point_2 : in data_type;
distance : out coord_type_ext;
point_1_out : out data_type;
point_2_out : out data_type;
rdy : out std_logic
);
end component;
component min_search is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
metric_in : in coord_type_ext;
u_in : in node_data_type;
point_in : in data_type;
min_point : out data_type;
min_index : out centre_index_type;
min_metric : out coord_type_ext;
u_out : out node_data_type;
rdy : out std_logic
);
end component;
signal reg_u_in : node_data_type;
signal reg_point : data_type;
signal reg_point_list_d : data_type;
signal state : state_type;
signal compute_distance_nd : std_logic;
signal compute_distance_rdy : std_logic;
signal distance : coord_type_ext;
signal point_list_d_delayed : data_type;
signal point_list_idx_delayed : centre_index_type;
signal tmp_min_index : centre_index_type;
signal tmp_min_point : data_type;
signal tmp_min_distance : coord_type_ext;
signal tmp_min_search_rdy : std_logic;
signal node_data_delay : node_data_delay_type;
begin
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
state <= idle;
elsif state = idle AND nd='1' then
state <= processing;
elsif state = processing AND nd='0' then
state <= idle;
end if;
end if;
end process fsm_proc;
-- need to delay by one cycle due to state machine
reg_point_list_d_proc : process(clk)
begin
if rising_edge(clk) then
if state = idle AND nd= '1' then
reg_u_in <= u_in;
reg_point <= point;
end if;
reg_point_list_d <= point_list_d;
end if;
end process reg_point_list_d_proc;
compute_distance_nd <= '1' WHEN state = processing ELSE '0';
compute_distance_top_inst : compute_distance_top
port map (
clk => clk,
sclr => sclr,
nd => compute_distance_nd,
point_1 => reg_point,
point_2 => reg_point_list_d,
distance => distance,
point_1_out => open,
point_2_out => point_list_d_delayed,
rdy => compute_distance_rdy
);
-- feed u_in from input of dot-product to output of dot-product
data_delay_proc : process(clk)
begin
if rising_edge(clk) then
node_data_delay(0) <= reg_u_in;
node_data_delay(1 to LATENCY-1) <= node_data_delay(0 to LATENCY-2);
end if;
end process data_delay_proc;
-- search min
min_search_inst : min_search
port map (
clk => clk,
sclr => sclr,
nd => compute_distance_rdy,
metric_in => distance,
u_in => node_data_delay(LATENCY-1),
point_in => point_list_d_delayed,
min_point => tmp_min_point,
min_index => tmp_min_index,
min_metric => tmp_min_distance,
u_out => u_out,
rdy => tmp_min_search_rdy
);
min_point <= tmp_min_point;
min_index <= tmp_min_index;
min_distance <= tmp_min_distance;
rdy <= tmp_min_search_rdy;
end Behavioral;
| bsd-3-clause | ea579f8539041f016443e06c6c4c354d | 0.526564 | 3.902941 | false | false | false | false |
RickvanLoo/Synthesizer | pulselut_entity.vhd | 1 | 1,056 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
ENTITY pulselut_entity IS
GENERIC(lut_bit_width : integer := 8;
DATA_width: integer := 16
);
PORT(
phase_in : in unsigned(lut_bit_width-1 downto 0);
a_clk : in std_logic;
reset : in std_logic;
DATA : OUT std_logic_vector(15 downto 0)
);
END pulselut_entity;
architecture behav of pulselut_entity is
--LUT
type sine_lut is array (0 to 1) of integer;
constant sinedata:sine_lut:= (-8000,8000);
signal sDATA : std_logic_vector(15 downto 0);
begin
process(a_clk,reset)
variable lutindex : integer range 0 to (2**lut_bit_width)-1 := 0;
begin
if reset = '0' then
DATA <= (others => '0');
lutindex := 0;
elsif rising_edge(a_clk) then
lutindex := to_integer(phase_in);
if lutindex < 128 then
sDATA <= std_logic_vector(to_signed(sinedata(0), DATA_width));
else
sDATA <= std_logic_vector(to_signed(sinedata(1), DATA_width));
end if;
DATA <= sDATA;
end if;
end process;
end behav; | mit | ed829104d0b623326c272ba3f0420583 | 0.631629 | 2.974648 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/filtering_algorithm_wrapper.vhd | 1 | 8,339 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: filtering_algorithm_wrapper - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity filtering_algorithm_wrapper is
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
select_input : in std_logic_vector(1 downto 0);
select_par : in std_logic_vector(integer(ceil(log2(real(PARALLEL_UNITS))))-1 downto 0);
-- initial parameters
k : in unsigned(INDEX_BITWIDTH-1 downto 0);
root_address : in std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
-- init node and centre memory
wr_init_nd : in std_logic;
wr_data_init : in std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0);
wr_address_init : in std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
-- outputs
valid : out std_logic;
clusters_out : out data_type;
distortion_out : out coord_type_ext;
-- processing done
rdy : out std_logic
);
end filtering_algorithm_wrapper;
architecture Behavioral of filtering_algorithm_wrapper is
component filtering_alogrithm_top is
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
-- initial parameters
k : in centre_index_type;
root_address : in par_node_address_type;
-- init node and centre memory
wr_init_cent : in std_logic;
wr_centre_list_address_init : in centre_list_address_type;
wr_centre_list_data_init : in centre_index_type;
wr_init_node : in std_logic_vector(0 to PARALLEL_UNITS-1);
wr_node_address_init : in par_node_address_type;
wr_node_data_init : in par_node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
-- outputs
valid : out std_logic;
clusters_out : out data_type;
distortion_out : out coord_type_ext;
-- processing done
rdy : out std_logic
);
end component;
signal tmp_clk : std_logic;
signal reg_sclr : std_logic;
signal reg_start : std_logic;
-- initial parameters
signal reg_k : centre_index_type;
signal reg_root_address : node_address_type;
signal tmp_root_address : par_node_address_type;
-- init node and centre memory
signal reg_wr_init_cent : std_logic;
signal reg_wr_centre_list_address_init : centre_list_address_type;
signal reg_wr_centre_list_data_init : centre_index_type;
signal reg_wr_init_node : std_logic_vector(0 to PARALLEL_UNITS-1);
signal reg_wr_node_address_init : node_address_type;
signal tmp_wr_node_address_init : par_node_address_type;
signal reg_wr_node_data_init : node_data_type;
signal tmp_wr_node_data_init : par_node_data_type;
signal reg_wr_init_pos : std_logic;
signal reg_wr_centre_list_pos_address_init : centre_index_type;
signal reg_wr_centre_list_pos_data_init : data_type;
-- outputs
signal tmp_valid : std_logic;
signal reg_valid : std_logic;
signal tmp_clusters_out : data_type;
signal reg_clusters_out : data_type;
signal tmp_distortion_out : coord_type_ext;
signal reg_distortion_out : coord_type_ext;
-- processing done
signal tmp_rdy : std_logic;
signal reg_rdy : std_logic;
begin
ClkBuffer: IBUFG
port map (
I => clk,
O => tmp_clk
);
input_reg : process(tmp_clk)
begin
if rising_edge(tmp_clk) then
if select_input = "00" then
reg_wr_init_cent <= wr_init_nd;
reg_wr_init_pos <= '0';
elsif select_input = "01" then
reg_wr_init_cent <= '0';
reg_wr_init_pos <= '0';
else
reg_wr_init_cent <= '0';
reg_wr_init_pos <= wr_init_nd;
end if;
for I in 0 to PARALLEL_UNITS-1 loop
if select_par = std_logic_vector(to_unsigned(I,integer(ceil(log2(real(PARALLEL_UNITS)))))) then
if select_input = "00" then
reg_wr_init_node(I) <= '0';
elsif select_input = "01" then
reg_wr_init_node(I) <= wr_init_nd;
else
reg_wr_init_node(I) <= '0';
end if;
else
reg_wr_init_node(I) <= '0';
end if;
end loop;
reg_wr_centre_list_address_init <= wr_address_init(CNTR_POINTER_BITWIDTH-1 downto 0);
reg_wr_centre_list_data_init <= unsigned(wr_data_init(INDEX_BITWIDTH-1 downto 0));
reg_wr_node_address_init <= wr_address_init(NODE_POINTER_BITWIDTH-1 downto 0);
reg_wr_node_data_init <= stdlogic_2_nodedata(wr_data_init);
reg_wr_centre_list_pos_address_init <= unsigned(wr_address_init(INDEX_BITWIDTH-1 downto 0));
reg_wr_centre_list_pos_data_init <= stdlogic_2_datapoint(wr_data_init(D*COORD_BITWIDTH-1 downto 0));
reg_sclr <= sclr;
reg_start <= start;
reg_k <= k;
reg_root_address <= root_address;
end if;
end process input_reg;
-- parallel units will be initialiased one after the other (a controlled by reg_wr_init_node)
G0_PAR : for I in 0 to PARALLEL_UNITS-1 generate
tmp_wr_node_address_init(I) <= reg_wr_node_address_init;
tmp_wr_node_data_init(I) <= reg_wr_node_data_init;
tmp_root_address(I) <= reg_root_address;
end generate G0_PAR;
filtering_alogrithm_top_inst : filtering_alogrithm_top
port map(
clk => tmp_clk,
sclr => reg_sclr,
start => reg_start,
-- initial parameters
k => reg_k,
root_address => tmp_root_address,
-- init node and centre memory
wr_init_cent => reg_wr_init_cent,
wr_centre_list_address_init => reg_wr_centre_list_address_init,
wr_centre_list_data_init => reg_wr_centre_list_data_init,
wr_init_node => reg_wr_init_node,
wr_node_address_init => tmp_wr_node_address_init,
wr_node_data_init => tmp_wr_node_data_init,
wr_init_pos => reg_wr_init_pos,
wr_centre_list_pos_address_init => reg_wr_centre_list_pos_address_init,
wr_centre_list_pos_data_init => reg_wr_centre_list_pos_data_init,
-- outputs
valid => tmp_valid,
clusters_out => tmp_clusters_out,
distortion_out => tmp_distortion_out,
-- processing done
rdy => tmp_rdy
);
output_reg : process(tmp_clk)
begin
if rising_edge(tmp_clk) then
reg_valid <= tmp_valid;
reg_clusters_out <= tmp_clusters_out;
reg_distortion_out <= tmp_distortion_out;
reg_rdy <= tmp_rdy;
end if;
end process output_reg;
valid <= reg_valid;
clusters_out <= reg_clusters_out;
distortion_out <= reg_distortion_out;
rdy <= reg_rdy;
end Behavioral;
| bsd-3-clause | 191c71815d2e7ac07b7ae3be7af00981 | 0.539033 | 3.896729 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-2/alu_cu.vhd | 1 | 981 | library IEEE;
use ieee.std_logic_1164.all;
entity alu_cu is
port(
--Inputs
FC: in std_logic_vector(5 downto 0);
ALUOp: in std_logic_vector(1 downto 0);
opc : in std_logic_vector(5 downto 0);
--Output
Operation: out std_logic_vector (2 downto 0)
);
end entity alu_cu;
architecture behav of alu_cu is
signal orgateop0, andgateop0, notorgateop1, andgateop2, orgateop2, op0, op1, op2 : std_logic :='0';
signal FuCo, FuCo1 : std_logic_vector(5 downto 0);
--signal OP : std_logic_vector(2 downto 0);
begin
FuCo1<= FC when (ALUOp = "10") else "000000";
FuCo<="100100" when (opc ="001100") else FuCo1;
orgateop0 <= FuCo(3) or FuCo(0);
andgateop0 <= orgateop0 and ALUOp(1);
notorgateop1 <= (not ALUOp(1)) or (not FuCo(2));
andgateop2 <= ALUOp(1) and FuCo(1);
orgateop2 <= ALUOp(0) or andgateop2;
op2 <= orgateop2;
op1 <= notorgateop1;
op0 <= orgateop0;
Operation(2) <= op2;
Operation(1) <= op1;
Operation(0) <= op0;
end behav;
| gpl-3.0 | 7ff1c33aa74b89dfd3f69c01b3756d91 | 0.653415 | 2.588391 | false | false | false | false |
Nooxet/embedded_bruteforce | vhdl/tb_md5_working.vhd | 1 | 3,495 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:06:02 09/17/2014
-- Design Name:
-- Module Name: H:/Documents/md5_test/tb_md5_working.vhd
-- Project Name: md5_test
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MD5
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_md5_working IS
END tb_md5_working;
ARCHITECTURE behavior OF tb_md5_working IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MD5
PORT(
clk : IN std_logic;
rstn : IN std_logic;
i_start : IN std_logic;
i_data_0 : IN unsigned(31 downto 0);
i_data_1 : IN unsigned(31 downto 0);
i_length : IN std_logic_vector(7 downto 0);
o_done : OUT std_logic;
o_hash_0 : OUT unsigned(31 downto 0);
o_hash_1 : OUT unsigned(31 downto 0);
o_hash_2 : OUT unsigned(31 downto 0);
o_hash_3 : OUT unsigned(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rstn : std_logic := '0';
signal i_start : std_logic := '0';
signal i_data_0 : unsigned(31 downto 0) := (others => '0');
signal i_data_1 : unsigned(31 downto 0) := (others => '0');
signal i_length : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal o_done : std_logic;
signal o_hash_0 : unsigned(31 downto 0);
signal o_hash_1 : unsigned(31 downto 0);
signal o_hash_2 : unsigned(31 downto 0);
signal o_hash_3 : unsigned(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MD5 PORT MAP (
clk => clk,
rstn => rstn,
i_start => i_start,
i_data_0 => i_data_0,
i_data_1 => i_data_1,
i_length => i_length,
o_done => o_done,
o_hash_0 => o_hash_0,
o_hash_1 => o_hash_1,
o_hash_2 => o_hash_2,
o_hash_3 => o_hash_3
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for clk_period/2;
rstn <= '0';
wait for clk_period;
rstn <= '1';
i_start <= '1';
i_data_0 <= x"00008061";
i_data_1 <= x"00000000";
i_length <= x"08";
wait until o_done = '1';
i_data_0 <= x"80636261";
i_data_1 <= x"00000000";
i_length <= x"18";
wait;
end process;
END;
| mit | 45249e219772cf1c0e77b88d10fe5113 | 0.540773 | 3.470705 | false | true | false | false |
freecores/gpib_controller | vhdl/test/gpib_SeriallPoll_Test.vhd | 1 | 17,234 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 23:21:05 10/21/2011
-- Design Name:
-- Module Name: /windows/h/projekty/elektronika/USB_to_HPIB/usbToHpib/test_scr//gpibInterfaceTest.vhd
-- Project Name: usbToHpib
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: gpibInterface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use ieee.std_logic_arith.all;
use work.gpibComponents.all;
use work.helperComponents.all;
ENTITY gpib_SeriallPoll_Test IS
END gpib_SeriallPoll_Test;
ARCHITECTURE behavior OF gpib_SeriallPoll_Test IS
-- Component Declaration for the Unit Under Test (UUT)
component gpibCableEmulator is port (
-- interface signals
DIO_1 : in std_logic_vector (7 downto 0);
output_valid_1 : in std_logic;
DIO_2 : in std_logic_vector (7 downto 0);
output_valid_2 : in std_logic;
DIO : out std_logic_vector (7 downto 0);
-- attention
ATN_1 : in std_logic;
ATN_2 : in std_logic;
ATN : out std_logic;
-- data valid
DAV_1 : in std_logic;
DAV_2 : in std_logic;
DAV : out std_logic;
-- not ready for data
NRFD_1 : in std_logic;
NRFD_2 : in std_logic;
NRFD : out std_logic;
-- no data accepted
NDAC_1 : in std_logic;
NDAC_2 : in std_logic;
NDAC : out std_logic;
-- end or identify
EOI_1 : in std_logic;
EOI_2 : in std_logic;
EOI : out std_logic;
-- service request
SRQ_1 : in std_logic;
SRQ_2 : in std_logic;
SRQ : out std_logic;
-- interface clear
IFC_1 : in std_logic;
IFC_2 : in std_logic;
IFC : out std_logic;
-- remote enable
REN_1 : in std_logic;
REN_2 : in std_logic;
REN : out std_logic
);
end component;
-- inputs common
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal T1 : std_logic_vector(7 downto 0) := "00000100";
-- inputs 1
signal data_1 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_1 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_1 : std_logic := '0';
signal nba_1 : std_logic := '0';
signal ltn_1 : std_logic := '0';
signal lun_1 : std_logic := '0';
signal lon_1 : std_logic := '0';
signal ton_1 : std_logic := '0';
signal endOf_1 : std_logic := '0';
signal gts_1 : std_logic := '0';
signal rpp_1 : std_logic := '0';
signal tcs_1 : std_logic := '0';
signal tca_1 : std_logic := '0';
signal sic_1 : std_logic := '0';
signal rsc_1 : std_logic := '0';
signal sre_1 : std_logic := '0';
signal rtl_1 : std_logic := '0';
signal rsv_1 : std_logic := '0';
signal ist_1 : std_logic := '0';
signal lpe_1 : std_logic := '0';
-- inputs 2
signal lpeUsed_2 : std_logic := '0';
signal data_2 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_2 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_2 : std_logic := '0';
signal nba_2 : std_logic := '0';
signal ltn_2 : std_logic := '0';
signal lun_2 : std_logic := '0';
signal lon_2 : std_logic := '0';
signal ton_2 : std_logic := '0';
signal endOf_2 : std_logic := '0';
signal gts_2 : std_logic := '0';
signal rpp_2 : std_logic := '0';
signal tcs_2 : std_logic := '0';
signal tca_2 : std_logic := '0';
signal sic_2 : std_logic := '0';
signal rsc_2 : std_logic := '0';
signal sre_2 : std_logic := '0';
signal rtl_2 : std_logic := '0';
signal rsv_2 : std_logic := '0';
signal ist_2 : std_logic := '0';
signal lpe_2 : std_logic := '0';
-- outputs 1
signal dvd_1 : std_logic;
signal wnc_1 : std_logic;
signal tac_1 : std_logic;
signal lac_1 : std_logic;
signal cwrc_1 : std_logic;
signal cwrd_1 : std_logic;
signal clr_1 : std_logic;
signal trg_1 : std_logic;
signal atl_1 : std_logic;
signal att_1 : std_logic;
signal mla_1 : std_logic;
signal lsb_1 : std_logic;
signal spa_1 : std_logic;
signal ppr_1 : std_logic;
signal sreq_1 : std_logic;
signal isLocal_1 : std_logic;
signal currentSecAddr_1 : std_logic_vector (4 downto 0);
-- outputs 2
signal dvd_2 : std_logic;
signal wnc_2 : std_logic;
signal tac_2 : std_logic;
signal lac_2 : std_logic;
signal cwrc_2 : std_logic;
signal cwrd_2 : std_logic;
signal clr_2 : std_logic;
signal trg_2 : std_logic;
signal atl_2 : std_logic;
signal att_2 : std_logic;
signal mla_2 : std_logic;
signal lsb_2 : std_logic;
signal spa_2 : std_logic;
signal ppr_2 : std_logic;
signal sreq_2 : std_logic;
signal isLocal_2 : std_logic;
signal currentSecAddr_2 : std_logic_vector (4 downto 0);
-- common
signal DO : std_logic_vector (7 downto 0);
signal DI_1 : std_logic_vector (7 downto 0);
signal output_valid_1 : std_logic;
signal DI_2 : std_logic_vector (7 downto 0);
signal output_valid_2 : std_logic;
signal ATN_1, ATN_2, ATN : std_logic;
signal DAV_1, DAV_2, DAV : std_logic;
signal NRFD_1, NRFD_2, NRFD : std_logic;
signal NDAC_1, NDAC_2, NDAC : std_logic;
signal EOI_1, EOI_2, EOI : std_logic;
signal SRQ_1, SRQ_2, SRQ : std_logic;
signal IFC_1, IFC_2, IFC : std_logic;
signal REN_1, REN_2, REN : std_logic;
-- gpib reader 1
signal rd1_buf_interrupt : std_logic;
signal rd1_data_available : std_logic;
signal rd1_last_byte_addr : std_logic_vector (3 downto 0);
signal rd1_end_of_stream : std_logic;
signal rd1_byte_addr : std_logic_vector (3 downto 0);
signal rd1_data_out : std_logic_vector (7 downto 0);
signal rd1_reset_buffer : std_logic := '0';
signal dataSecAddr_1 : std_logic_vector (4 downto 0);
-- gpib reader 2
signal buf_interrupt : std_logic;
signal data_available : std_logic;
signal last_byte_addr : std_logic_vector (3 downto 0);
signal end_of_stream : std_logic;
signal byte_addr : std_logic_vector (3 downto 0);
signal data_out : std_logic_vector (7 downto 0);
signal reset_buffer : std_logic := '0';
signal dataSecAddr_2 : std_logic_vector (4 downto 0);
-- gpib writer
signal w_last_byte_addr : std_logic_vector (3 downto 0)
:= (others => '0');
signal w_end_of_stream : std_logic := '0';
signal w_data_available : std_logic := '0';
signal w_buf_interrupt : std_logic;
signal w_data_in : std_logic_vector (7 downto 0);
signal w_byte_addr : std_logic_vector (3 downto 0);
signal w_reset_buffer : std_logic := '0';
type WR_BUF_TYPE is
array (0 to 15) of std_logic_vector (7 downto 0);
signal w_write_buffer : WR_BUF_TYPE;
-- gpib writer 2
signal w_last_byte_addr_2 : std_logic_vector (3 downto 0)
:= (others => '0');
signal w_end_of_stream_2 : std_logic := '0';
signal w_data_available_2 : std_logic := '0';
signal w_buf_interrupt_2 : std_logic;
signal w_data_in_2 : std_logic_vector (7 downto 0);
signal w_byte_addr_2 : std_logic_vector (3 downto 0);
signal w_reset_buffer_2 : std_logic := '0';
type WR_BUF_TYPE_2 is
array (0 to 15) of std_logic_vector (7 downto 0);
signal w_write_buffer_2 : WR_BUF_TYPE;
-- serial poll coordinator
signal rec_stb : std_logic := '0';
signal stb_received : std_logic;
signal spc_ATN_in : std_logic;
signal spc_out_valid_in : std_logic;
-- Clock period definitions
constant clk_period : time := 2ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
gpib1: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00001",
myTalkAddr => "00001",
secAddrMask => (others => '0'),
data => data_1,
status_byte => status_byte_1,
T1 => T1,
rdy => rdy_1,
nba => nba_1,
ltn => ltn_1,
lun => lun_1,
lon => lon_1,
ton => ton_1,
endOf => endOf_1,
gts => gts_1,
rpp => rpp_1,
tcs => tcs_1,
tca => tca_1,
sic => sic_1,
rsc => rsc_1,
sre => sre_1,
rtl => rtl_1,
rsv => rsv_1,
ist => ist_1,
lpe => lpe_1,
dvd => dvd_1,
wnc => wnc_1,
tac => tac_1,
lac => lac_1,
cwrc => cwrc_1,
cwrd => cwrd_1,
clr => clr_1,
trg => trg_1,
atl => atl_1,
att => att_1,
mla => mla_1,
lsb => lsb_1,
spa => spa_1,
ppr => ppr_1,
sreq => sreq_1,
isLocal => isLocal_1,
currentSecAddr => currentSecAddr_1,
DI => DO,
DO => DI_1,
output_valid => spc_out_valid_in,
ATN_in => ATN,
ATN_out => spc_ATN_in,
DAV_in => DAV,
DAV_out => DAV_1,
NRFD_in => NRFD,
NRFD_out => NRFD_1,
NDAC_in => NDAC,
NDAC_out => NDAC_1,
EOI_in => EOI,
EOI_out => EOI_1,
SRQ_in => SRQ,
SRQ_out => SRQ_1,
IFC_in => IFC,
IFC_out => IFC_1,
REN_in => REN,
REN_out => REN_1
);
-- Instantiate the Unit Under Test (UUT)
gpib2: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => lpeUsed_2,
fixedPpLine => "001",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00010",
myTalkAddr => "00010",
secAddrMask => (others => '0'),
data => data_2,
status_byte => status_byte_2,
T1 => T1,
rdy => rdy_2,
nba => nba_2,
ltn => ltn_2,
lun => lun_2,
lon => lon_2,
ton => ton_2,
endOf => endOf_2,
gts => gts_2,
rpp => rpp_2,
tcs => tcs_2,
tca => tca_2,
sic => sic_2,
rsc => rsc_2,
sre => sre_2,
rtl => rtl_2,
rsv => rsv_2,
ist => ist_2,
lpe => lpe_2,
dvd => dvd_2,
wnc => wnc_2,
tac => tac_2,
lac => lac_2,
cwrc => cwrc_2,
cwrd => cwrd_2,
clr => clr_2,
trg => trg_2,
atl => atl_2,
att => att_2,
mla => mla_2,
lsb => lsb_2,
spa => spa_2,
ppr => ppr_2,
sreq => sreq_2,
isLocal => isLocal_2,
currentSecAddr => currentSecAddr_2,
DI => DO,
DO => DI_2,
output_valid => output_valid_2,
ATN_in => ATN,
ATN_out => ATN_2,
DAV_in => DAV,
DAV_out => DAV_2,
NRFD_in => NRFD,
NRFD_out => NRFD_2,
NDAC_in => NDAC,
NDAC_out => NDAC_2,
EOI_in => EOI,
EOI_out => EOI_2,
SRQ_in => SRQ,
SRQ_out => SRQ_2,
IFC_in => IFC,
IFC_out => IFC_2,
REN_in => REN,
REN_out => REN_2
);
ce: gpibCableEmulator port map (
-- interface signals
DIO_1 => DI_1,
output_valid_1 => output_valid_1,
DIO_2 => DI_2,
output_valid_2 => output_valid_2,
DIO => DO,
-- attention
ATN_1 => ATN_1, ATN_2 => ATN_2, ATN => ATN,
DAV_1 => DAV_1, DAV_2 => DAV_2, DAV => DAV,
NRFD_1 => NRFD_1, NRFD_2 => NRFD_2, NRFD => NRFD,
NDAC_1 => NDAC_1, NDAC_2 => NDAC_2, NDAC => NDAC,
EOI_1 => EOI_1, EOI_2 => EOI_2, EOI => EOI,
SRQ_1 => SRQ_1, SRQ_2 => SRQ_2, SRQ => SRQ,
IFC_1 => IFC_1, IFC_2 => IFC_2, IFC => IFC,
REN_1 => REN_1, REN_2 => REN_2, REN => REN
);
gr1: gpibReader generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_in => DO, dvd => dvd_1, lac => lac_1, lsb => lsb_1, rdy => rdy_1,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isLE => '0', secAddr => (others => '0'), dataSecAddr => dataSecAddr_1,
buf_interrupt => rd1_buf_interrupt, data_available => rd1_data_available,
last_byte_addr => rd1_last_byte_addr, end_of_stream => rd1_end_of_stream,
byte_addr => rd1_byte_addr, data_out => rd1_data_out,
reset_buffer => rd1_reset_buffer
);
gr2: gpibReader generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_in => DO, dvd => dvd_2, lac => lac_2, lsb => lsb_2, rdy => rdy_2,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isLE => '0', secAddr => (others => '0'), dataSecAddr => dataSecAddr_2,
buf_interrupt => buf_interrupt, data_available => data_available,
last_byte_addr => last_byte_addr, end_of_stream => end_of_stream,
byte_addr => byte_addr, data_out => data_out,
reset_buffer => reset_buffer
);
w_data_in <= w_write_buffer(conv_integer(w_byte_addr));
gw: gpibWriter generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_out => data_1, wnc => wnc_1, spa => spa_1, nba => nba_1,
endOf => endOf_1, tac => tac_1, cwrc => cwrc_1,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isTE => '0', secAddr => (others => '0'), dataSecAddr => (others => '0'),
last_byte_addr => w_last_byte_addr, end_of_stream => w_end_of_stream,
data_available => w_data_available, buf_interrupt => w_buf_interrupt,
data_in => w_data_in, byte_addr => w_byte_addr,
reset_buffer => w_reset_buffer
);
w_data_in <= w_write_buffer(conv_integer(w_byte_addr));
gw2: gpibWriter generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_out => data_2, wnc => wnc_2, spa => spa_2, nba => nba_2,
endOf => endOf_2, tac => tac_2, cwrc => cwrc_2,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isTE => '0', secAddr => (others => '0'), dataSecAddr => (others => '0'),
last_byte_addr => w_last_byte_addr_2, end_of_stream => w_end_of_stream_2,
data_available => w_data_available_2, buf_interrupt => w_buf_interrupt_2,
data_in => w_data_in_2, byte_addr => w_byte_addr_2,
reset_buffer => w_reset_buffer_2
);
spc1: SerialPollCoordinator port map ( clk => clk, reset=> reset,
DAC => not NDAC,
-- receive status byte
rec_stb => rec_stb,
-- attention in
ATN_in => spc_ATN_in,
-- attention out
ATN_out => ATN_1,
output_valid_in => spc_out_valid_in,
output_valid_out => output_valid_1,
-- stb received
stb_received => stb_received
);
--ATN_1 <= spc_ATN_in;
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 10 clock periods.
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*10;
-- requests system control
rsc_1 <= '1';
-- interface clear
sic_1 <= '1';
wait until IFC_1 = '1';
sic_1 <= '0';
wait until IFC_1 = '0';
rsv_2 <= '1';
status_byte_2 <= "10010101";
assert sreq_1 = '0';
assert sreq_2 = '0';
wait until sreq_1 = '1';
assert sreq_1 = '1';
assert sreq_2 = '0';
-- gpib2 to talk
w_write_buffer(0) <= "01000010";
-- gpib1 to listen
w_write_buffer(1) <= "00100001";
-- serial poll enable
w_write_buffer(2) <= "00011000";
w_last_byte_addr <= "0010";
w_data_available <= '1';
wait until w_buf_interrupt = '1';
rec_stb <= '1';
wait until stb_received = '1';
rec_stb <= '0';
wait for clk_period*1;
rd1_byte_addr <= conv_std_logic_vector(0, 4);
wait for clk_period*1;
assert rd1_data_out = "11010101";
assert rd1_last_byte_addr = "0000";
assert rd1_data_available = '1';
report "$$$ END OF TEST - serial poll $$$";
wait;
end process;
END;
| gpl-3.0 | d57705c2abcea3d4e970daf4ab0da3a1 | 0.549321 | 2.97497 | false | false | false | false |
RickvanLoo/Synthesizer | sample_clk_gen_entity.vhd | 1 | 730 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
entity sample_clk_gen_entity is
GENERIC(divider : integer := 512
);
PORT (clk : IN std_logic;
reset : IN std_logic;
a_clk, a_clk_main : OUT std_logic
);
END sample_clk_gen_entity;
architecture behav of sample_clk_gen_entity is
signal local_clk : std_logic := '0';
begin
process(clk, reset)
variable count : integer := 0;
begin
if reset = '0' then
count := 0;
local_clk <= '0';
elsif falling_edge(clk) then
if count = divider then
local_clk <= not local_clk;
count := 0;
end if;
count := count + 1;
end if;
a_clk <= local_clk;
a_clk_main <= local_clk;
end process;
end behav; | mit | 7ba3060ba5e0c72c8f88cff7e4c8a5c2 | 0.612329 | 2.851563 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-2/thirty_two_to_one_mux.vhd | 1 | 1,634 | library IEEE;
use ieee.std_logic_1164.all;
entity thirty_two_to_one_mux is
port(
in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in15, in16, in17, in18, in19, in20, in21, in22, in23, in24, in25, in26, in27, in28, in29, in30, in31 : in std_logic_vector(31 downto 0);
sel : in std_logic_vector(4 downto 0);
output : out std_logic_vector(31 downto 0)
);
end entity thirty_two_to_one_mux;
architecture behav of thirty_two_to_one_mux is
begin
--output <= (a and (not sel(0)) and (not sel(1))) or (b and sel(0) and (not sel(1))) or (c and (not sel(0)) and sel(1)) or (d and sel(0) and sel(1));
output <= in0 when (sel = "00000") else in1 when (sel = "00001") else in2 when (sel = "00010") else in3 when (sel = "00011") else in4 when (sel = "00100") else in5 when (sel = "00101") else in6 when (sel = "00110") else in7 when (sel = "00111") else in8 when (sel = "01000") else in9 when (sel = "01001") else in10 when (sel = "01010") else in11 when (sel = "01011") else in12 when (sel = "01100") else in13 when (sel = "01101") else in14 when (sel = "01110") else in15 when (sel = "01111") else in16 when (sel = "10000") else in17 when (sel = "10001") else in18 when (sel = "10010") else in19 when (sel = "10011") else in20 when (sel = "10100") else in21 when (sel = "10101") else in22 when (sel = "10110") else in23 when (sel = "10111") else in24 when (sel = "11000") else in25 when (sel = "11001") else in26 when (sel = "11010") else in27 when (sel = "11011") else in28 when (sel = "11100") else in29 when (sel = "11101") else in30 when (sel = "11110") else in31 when (sel = "11111");
end behav; | gpl-3.0 | a6c746e5a670328326b2bd1f1003e7be | 0.646879 | 2.737018 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-1/counter.vhd | 1 | 1,189 | --
-- Copyright 1991-2015 Mentor Graphics Corporation
--
-- All Rights Reserved.
--
-- THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
-- MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
--
entity counter is
port (count : buffer bit_vector(8 downto 1);
clk : in bit;
reset : in bit);
end;
architecture only of counter is
constant tpd_reset_to_count : time := 3 ns;
constant tpd_clk_to_count : time := 2 ns;
function increment(val : bit_vector) return bit_vector
is
-- normalize the indexing
alias input : bit_vector(val'length downto 1) is val;
variable result : bit_vector(input'range) := input;
variable carry : bit := '1';
begin
for i in input'low to input'high loop
result(i) := input(i) xor carry;
carry := input(i) and carry;
exit when carry = '0';
end loop;
return result;
end increment;
begin
ctr:
process(clk, reset)
begin
if (reset = '1') then
if reset'event then
count <= (others => '0') after tpd_reset_to_count;
end if;
elsif clk'event and (clk = '1') then
count <= increment(count) after tpd_clk_to_count;
end if;
end process;
end only;
| gpl-3.0 | 2ad7195f4114c1b72c847e9cd5039221 | 0.67704 | 3.128947 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib/if_func_SH.vhd | 1 | 4,614 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 01:04:57 10/01/2011
-- Design Name:
-- Module Name: if_func_SH - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.utilPkg.all;
entity if_func_SH is
port(
-- device inputs
clk : in std_logic; -- clock
-- settingd
T1 : in std_logic_vector (7 downto 0);
-- local commands
pon : in std_logic; -- power on
nba : in std_logic; -- new byte available
-- state inputs
TACS : in std_logic; -- talker active state
SPAS : in std_logic; -- seriall poll active state
CACS : in std_logic; -- controller active state
CTRS : in std_logic; -- controller transfer state
-- interface inputs
ATN : in std_logic; -- attention
DAC : in std_logic; -- data accepted
RFD : in std_logic; -- ready for data
-- remote instructions
DAV : out std_logic; -- data address valid
-- device outputs
wnc : out std_logic; -- wait for new cycle
-- reported states
STRS : out std_logic; -- source transfer state
SDYS : out std_logic -- source delay state
);
end if_func_SH;
architecture Behavioral of if_func_SH is
-- states
type SH_STATE is (
-- source idle state
ST_SIDS,
-- source generate state
ST_SGNS,
-- source delay state
ST_SDYS,
-- source transfer state
ST_STRS,
-- source wait for new cycle state
ST_SWNS,
-- source idle wait state
ST_SIWS
);
-- current state
signal current_state : SH_STATE;
-- predicates
signal pred1 : boolean;
signal pred2 : boolean;
-- timers
constant TIMER_T1_MAX : integer := 255;
signal timerT1 : integer range 0 to TIMER_T1_MAX;
signal timerT1Expired : boolean;
begin
-- state machine process
process(pon, clk) begin
if pon = '1' then
current_state <= ST_SIDS;
elsif rising_edge(clk) then
case current_state is
------------------
when ST_SIDS =>
if pred1 then
current_state <= ST_SGNS;
end if;
------------------
when ST_SGNS =>
if nba='1' then
timerT1 <= 0;
current_state <= ST_SDYS;
elsif pred2 then
current_state <= ST_SIDS;
end if;
------------------
when ST_SDYS =>
if pred2 then
current_state <= ST_SIDS;
elsif RFD='1' and timerT1Expired then
current_state <= ST_STRS;
end if;
if timerT1 < TIMER_T1_MAX then
timerT1 <= timerT1 + 1;
end if;
------------------
when ST_STRS =>
if DAC='1' then
current_state <= ST_SWNS;
elsif pred2 then
current_state <= ST_SIWS;
end if;
------------------
when ST_SWNS =>
if nba='0' then
current_state <= ST_SGNS;
elsif pred2 then
current_state <= ST_SIWS;
end if;
------------------
when ST_SIWS =>
if nba='0' then
current_state <= ST_SIDS;
elsif pred1 then
current_state <= ST_SWNS;
end if;
------------------
when others =>
current_state <= ST_SIDS;
end case;
end if;
end process;
-- events
pred1 <= TACS='1' or SPAS='1' or CACS='1';
pred2 <= (ATN='1' and not(CACS='1' or CTRS='1')) or
(ATN='0' and not(TACS='1' or SPAS='1'));
-- timers
timerT1Expired <= timerT1 >= conv_integer(UNSIGNED(T1));
-- DAV command
DAV <= to_stdl(current_state = ST_STRS);
-- wnc command
wnc <= to_stdl(current_state = ST_SWNS);
-- STRS command
STRS <= to_stdl(current_state = ST_STRS);
-- SDYS command
SDYS <= to_stdl(current_state = ST_SDYS);
end Behavioral;
| gpl-3.0 | 8e6408f45da24284af0908d1c231ee0f | 0.58886 | 3.407681 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/centre_buffer_mgmt.vhd | 1 | 6,388 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: centre_buffer_mgmt - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity centre_buffer_mgmt is
port (
clk : in std_logic;
sclr : in std_logic;
init : in std_logic;
addr_in_init : in centre_index_type;
nd : in std_logic;
request_rdo : in std_logic;
addr_in : in centre_index_type;
wgtCent_in : in data_type_ext;
sum_sq_in : in coord_type_ext;
count_in : in coord_type;
valid : out std_logic;
wgtCent_out : out data_type_ext;
sum_sq_out : out coord_type_ext;
count_out : out coord_type
);
end centre_buffer_mgmt;
architecture Behavioral of centre_buffer_mgmt is
constant DIM : integer := D;
constant LAT : integer := 2;
type state_type is (read, write);
component centre_buffer_dist
port (
a : IN STD_LOGIC_VECTOR(integer(ceil(log2(real(K_MAX))))-1 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(integer(ceil(log2(real(K_MAX))))-1 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DIM*COORD_BITWIDTH_EXT-1 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
qdpo : OUT STD_LOGIC_VECTOR(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DIM*COORD_BITWIDTH_EXT-1 DOWNTO 0)
);
end component;
signal state : state_type;
signal tmp_we : std_logic;
signal we_reg : std_logic;
signal rdo_delay : std_logic_vector(0 to LAT-1);
signal wr_addr_in_reg : centre_index_type;
signal rd_addr_in_reg : centre_index_type;
signal wgtCent_reg : data_type_ext;
signal sum_sq_reg : coord_type_ext;
signal count_reg : coord_type;
signal tmp_dina : std_logic_vector(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DIM*COORD_BITWIDTH_EXT-1 downto 0);
signal tmp_doutb : std_logic_vector(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DIM*COORD_BITWIDTH_EXT-1 downto 0);
signal tmp_wgtCent_int : data_type_ext;
signal tmp_sum_sq_int : coord_type_ext;
signal tmp_count_int : coord_type;
signal tmp_wgtCent_int_sum : data_type_ext;
signal tmp_sum_sq_int_sum : coord_type_ext;
signal tmp_count_int_sum : coord_type;
begin
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
state <= read;
elsif state = read AND nd = '1' then
state <= write;
elsif state = write then
state <= read;
end if;
end if;
end process fsm_proc;
tmp_we <= '1' WHEN state = write ELSE '0';
reg_proc : process(clk)
begin
if rising_edge(clk) then
if init = '1' then
wr_addr_in_reg <= addr_in_init;
rd_addr_in_reg <= addr_in;
for I in 0 to D-1 loop
wgtCent_reg(I) <= (others => '0');
end loop;
sum_sq_reg <= (others => '0');
count_reg <= (others => '0');
elsif nd = '1' OR request_rdo='1' then
wr_addr_in_reg <= addr_in;
rd_addr_in_reg <= addr_in;
--addr_in_reg <= addr_in;
wgtCent_reg <= wgtCent_in;
sum_sq_reg <= sum_sq_in;
count_reg <= count_in;
end if;
end if;
end process reg_proc;
reg_proc2 : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
we_reg <= '0';
rdo_delay <= (others => '0');
else
we_reg <= tmp_we OR init;
rdo_delay(0) <= request_rdo;
rdo_delay(1 to LAT-1) <= rdo_delay(0 to LAT-2);
end if;
end if;
end process reg_proc2;
centre_buffer_dist_inst : centre_buffer_dist
port map (
a => std_logic_vector(wr_addr_in_reg(integer(ceil(log2(real(K_MAX))))-1 downto 0)),
dpra => std_logic_vector(rd_addr_in_reg(integer(ceil(log2(real(K_MAX))))-1 downto 0)),
d => tmp_dina,
clk => clk,
we => we_reg,
qdpo_srst => init,
qdpo => tmp_doutb
);
G1: for I in 0 to D-1 generate
tmp_wgtCent_int(I) <= tmp_doutb((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT);
end generate G1;
tmp_sum_sq_int <= tmp_doutb(1*COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT-1 downto 0*COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT);
tmp_count_int <= tmp_doutb(COORD_BITWIDTH+COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT-1 downto 0+COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT);
G2: for I in 0 to D-1 generate
tmp_wgtCent_int_sum(I) <= std_logic_vector(signed(tmp_wgtCent_int(I)) + signed(wgtCent_reg(I)));
tmp_dina((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT) <= (tmp_wgtCent_int_sum(I));
end generate G2;
tmp_sum_sq_int_sum <= std_logic_vector(signed(tmp_sum_sq_int) + signed(sum_sq_reg));
tmp_dina(1*COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT-1 downto 0*COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT) <= tmp_sum_sq_int_sum;
tmp_count_int_sum <= std_logic_vector(signed(tmp_count_int) + signed(count_reg));
tmp_dina(COORD_BITWIDTH+COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT-1 downto 0+COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT) <= tmp_count_int_sum;
valid <= rdo_delay(LAT-1);
wgtCent_out <= tmp_wgtCent_int;
sum_sq_out <= tmp_sum_sq_int;
count_out <= tmp_count_int;
end Behavioral;
| bsd-3-clause | ef1779bc7a02927689ac436c0c0d3e72 | 0.555573 | 3.552836 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/source/vhdl/memory_mgmt.vhd | 1 | 8,794 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: memory_mgmt - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.lloyds_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity memory_mgmt is
port (
clk : in std_logic;
sclr : in std_logic;
rd : in std_logic;
rd_node_addr : in node_address_type;
k : in centre_index_type;
wr_init_node : in std_logic;
wr_node_address_init : in node_address_type;
wr_node_data_init : in node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
valid : out std_logic_vector(0 to PARALLEL_UNITS-1);
rd_node_data : out par_node_data_type;
rd_centre_list_pos_data : out par_data_type
);
end memory_mgmt;
architecture Behavioral of memory_mgmt is
constant MEM_LAT : integer := 2;
type rd_state_type is (idle, reading_centre_list);
type pos_addr_delay_type is array(1 to PARALLEL_UNITS-1) of centre_index_type;
component node_memory
port (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(NODE_POINTER_BITWIDTH-1 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(D*COORD_BITWIDTH-1 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(NODE_POINTER_BITWIDTH-1 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(D*COORD_BITWIDTH-1 DOWNTO 0)
);
end component;
component centre_positions_memory_top
port (
clk : in std_logic;
wea : in std_logic_vector(0 to PARALLEL_UNITS-1);
addra : in par_centre_index_type;
dina : in par_data_type;
addrb : in par_centre_index_type;
doutb : out par_data_type
);
end component;
signal rd_state : rd_state_type;
signal rd_counter_done : std_logic;
signal rd_counter : centre_index_type;
signal reading_centres : std_logic;
signal delay_line : std_logic_vector(0 to MEM_LAT+PARALLEL_UNITS-1-1);
signal rd_k_reg : centre_index_type;
signal rd_node_address_reg : node_address_type;
signal wr_node_reg : std_logic;
signal wr_node_address_reg : node_address_type;
signal wr_node_data_reg : node_data_type;
signal tmp_wr_node_address : std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
signal tmp_wr_node_data_in : std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
signal tmp_rd_node_data_out : std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
signal tmp_rd_node_address : std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
signal wr_pos_reg : std_logic;
signal wr_pos_address_reg : centre_index_type;
signal wr_pos_data_reg : data_type;
signal tmp_wr_centre_list_pos_data_init : std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
signal tmp_centre_pos_out : std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
signal pos_wea : std_logic_vector(0 to PARALLEL_UNITS-1);
signal pos_wr_address : par_centre_index_type;
signal pos_wr_data : par_data_type;
signal pos_rd_address : par_centre_index_type;
signal pos_rd_data : par_data_type;
signal pos_addr_delay : pos_addr_delay_type;
begin
--writing to memories
-- delay buffer wr input by one cycle due to state machine
wr_input_reg_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
wr_node_reg <= '0';
wr_pos_reg <= '0';
else
wr_node_reg <= wr_init_node;
wr_pos_reg <= wr_init_pos;
end if;
wr_node_address_reg <= wr_node_address_init;
wr_node_data_reg <= wr_node_data_init;
wr_pos_address_reg <= wr_centre_list_pos_address_init;
wr_pos_data_reg <= wr_centre_list_pos_data_init;
end if;
end process wr_input_reg_proc;
tmp_wr_node_address <= std_logic_vector(wr_node_address_reg);
tmp_wr_node_data_in <= nodedata_2_stdlogic(wr_node_data_reg);
tmp_wr_centre_list_pos_data_init <= datapoint_2_stdlogic(wr_pos_data_reg);
-- reading memories
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
rd_state <= idle;
elsif rd_state = idle AND rd = '1' then
rd_state <= reading_centre_list;
elsif rd_state = reading_centre_list AND rd_counter_done = '1' then
rd_state <= idle;
end if;
end if;
end process fsm_proc;
counter_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
rd_counter <= (others => '0');
else
if rd_state <= idle then
rd_counter <= (others => '0');
else
rd_counter <= rd_counter+1;
end if;
end if;
end if;
end process counter_proc;
rd_counter_done <= '1' WHEN rd_counter = rd_k_reg AND rd_state = reading_centre_list ELSE '0';
addr_reg_proc : process(clk)
begin
if rising_edge(clk) then
if rd = '1' then
rd_node_address_reg <= rd_node_addr;
rd_k_reg <= k;
end if;
end if;
end process addr_reg_proc;
tmp_rd_node_address <= std_logic_vector(rd_node_address_reg);
node_memory_inst : node_memory
port map(
clka => clk,
wea(0) => wr_node_reg,
addra => tmp_wr_node_address,
dina => tmp_wr_node_data_in,
clkb => clk,
addrb => tmp_rd_node_address,
doutb => tmp_rd_node_data_out
);
G_PAR_0 : for I in 0 to PARALLEL_UNITS-1 generate
rd_node_data(I) <= stdlogic_2_nodedata(tmp_rd_node_data_out);
end generate G_PAR_0;
G_PAR_1 : for I in 0 to PARALLEL_UNITS-1 generate
pos_wea(I) <= wr_pos_reg;
pos_wr_address(I) <= wr_pos_address_reg;
pos_wr_data(I) <= wr_pos_data_reg;
end generate G_PAR_1;
G_PAR_1_1 : if PARALLEL_UNITS > 1 generate
pos_addr_delay_proc : process(clk)
begin
if rising_edge(clk) then
pos_addr_delay(1) <= rd_counter;
pos_addr_delay(2 to PARALLEL_UNITS-1) <= pos_addr_delay(1 to PARALLEL_UNITS-2);
end if;
end process pos_addr_delay_proc;
end generate G_PAR_1_1;
pos_rd_address(0) <= rd_counter;
G_PAR_2 : for I in 1 to PARALLEL_UNITS-1 generate
pos_rd_address(I) <= pos_addr_delay(I);
end generate G_PAR_2;
centre_positions_memory_top_inst : centre_positions_memory_top
port map (
clk => clk,
wea => pos_wea,
addra => pos_wr_address,
dina => pos_wr_data,
addrb => pos_rd_address,
doutb => pos_rd_data
);
reading_centres <= '1' WHEN rd_state = reading_centre_list ELSE '0';
dely_line_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
delay_line <= (others => '0');
else
delay_line(0) <= reading_centres;
delay_line(1 to MEM_LAT+PARALLEL_UNITS-1-1) <= delay_line(0 to MEM_LAT+PARALLEL_UNITS-1-2);
end if;
end if;
end process dely_line_proc;
G_PAR_3 : for I in 0 to PARALLEL_UNITS-1 generate
valid(I) <= delay_line(MEM_LAT+I-1);
rd_centre_list_pos_data(I) <= pos_rd_data(I);
end generate G_PAR_3;
end Behavioral;
| bsd-3-clause | a43cb98374a70f010297c7c6d0e7c83b | 0.536502 | 3.708984 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/filtering_alogrithm_top.vhd | 1 | 17,349 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: filtering_algorithm_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity filtering_alogrithm_top is
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
-- initial parameters
k : in centre_index_type;
root_address : in par_node_address_type;
-- init node and centre memory
wr_init_cent : in std_logic;
wr_centre_list_address_init : in centre_list_address_type;
wr_centre_list_data_init : in centre_index_type;
wr_init_node : in std_logic_vector(0 to PARALLEL_UNITS-1);
wr_node_address_init : in par_node_address_type;
wr_node_data_init : in par_node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
-- outputs
valid : out std_logic;
clusters_out : out data_type;
distortion_out : out coord_type_ext;
-- processing done
rdy : out std_logic
);
end filtering_alogrithm_top;
architecture Behavioral of filtering_alogrithm_top is
type state_type is (phase_1_init, processing, readout, phase_2_init, gap_state1, reset_core, gap_state2, phase_2_start, done);
constant DIVIDER_II : integer := 2; --5;
component filtering_alogrithm_single
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
-- initial parameters
k : in centre_index_type;
root_address : in node_address_type;
-- init node and centre memory
wr_init_cent : in std_logic;
wr_centre_list_address_init : in centre_list_address_type;
wr_centre_list_data_init : in centre_index_type;
wr_init_node : in std_logic;
wr_node_address_init : in node_address_type;
wr_node_data_init : in node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
-- access centre buffer
rdo_centre_buffer : in std_logic;
centre_buffer_addr : in centre_index_type;
valid : out std_logic;
wgtCent_out : out data_type_ext;
sum_sq_out : out coord_type_ext;
count_out : out coord_type;
-- processing done
rdy : out std_logic
);
end component;
component adder_tree
generic (
USE_DSP_FOR_ADD : boolean := true;
NUMBER_OF_INPUTS : integer := 4;
INPUT_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
input_string : in std_logic_vector(NUMBER_OF_INPUTS*INPUT_BITWIDTH-1 downto 0);
rdy : out std_logic;
output : out std_logic_vector(INPUT_BITWIDTH+integer(ceil(log2(real(NUMBER_OF_INPUTS))))-1 downto 0)
);
end component;
component divider_top
generic (
ROUND : boolean := false
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
dividend : in data_type_ext;
divisor : in coord_type;
rdy : out std_logic;
quotient : out data_type;
divide_by_zero : out std_logic
);
end component;
-- control
signal state : state_type;
signal single_sclr : std_logic;
signal single_start : std_logic;
signal readout_counter : centre_index_type;
signal readout_counter_done : std_logic;
signal readout_centre_buffers : std_logic;
signal init_counter : centre_index_type;
signal init_counter_done : std_logic;
signal divider_ii_counter : unsigned(integer(ceil(log2(real(DIVIDER_II))))-1 downto 0);
signal divider_ii_counter_done : std_logic;
signal iterations_counter : unsigned(integer(ceil(log2(real(L_MAX))))-1 downto 0);
signal iterations_counter_done : std_logic;
-- core input signals
signal mux_wr_init_cent : std_logic;
signal mux_wr_centre_list_address_init : centre_list_address_type;
signal mux_wr_centre_list_data_init : centre_index_type;
signal mux_wr_init_pos : std_logic;
signal mux_wr_centre_list_pos_address_init : centre_index_type;
signal mux_wr_centre_list_pos_data_init : data_type;
-- core output signals
signal tmp_valid : std_logic_vector(0 to PARALLEL_UNITS-1);
signal tmp_wgtCent_out : par_data_type_ext;
signal tmp_sum_sq_out : par_coord_type_ext;
signal tmp_count_out : par_coord_type;
signal tmp_rdy : std_logic_vector(0 to PARALLEL_UNITS-1);
signal reg_rdy : std_logic_vector(0 to PARALLEL_UNITS-1);
-- adder tree
signal at_input_string_count : std_logic_vector(PARALLEL_UNITS*COORD_BITWIDTH-1 downto 0);
signal at_count_rdy : std_logic;
signal at_count_out : std_logic_vector(COORD_BITWIDTH+integer(ceil(log2(real(PARALLEL_UNITS))))-1 downto 0);
signal at_input_string_wgtCent : par_element_type_ext;
signal at_wgtCent_rdy : std_logic;
signal at_wgtCent_out : par_element_type_ext_sum;
signal tmp_wgtCent_out2 : data_type_ext;
signal at_input_string_sum_sq : std_logic_vector(PARALLEL_UNITS*COORD_BITWIDTH_EXT-1 downto 0);
signal at_sum_sq_rdy : std_logic;
signal at_sum_sq_out : std_logic_vector(COORD_BITWIDTH_EXT+integer(ceil(log2(real(PARALLEL_UNITS))))-1 downto 0);
-- signals after tree reduction
signal divider_nd : std_logic;
signal divider_wgtCent_in : data_type_ext;
signal divider_count_in : coord_type;
signal comb_rdy : std_logic;
signal comb_valid : std_logic;
signal comb_sum_sq_out : coord_type_ext;
signal comb_new_position : data_type;
signal divide_by_zero : std_logic;
-- type coord_type_array is array(0 to 4) of coord_type;
-- constant test_input_dim0 : coord_type_array := (std_logic_vector(to_signed(-579,COORD_BITWIDTH)), std_logic_vector(to_signed(-878,COORD_BITWIDTH)), std_logic_vector(to_signed(290,COORD_BITWIDTH)), std_logic_vector(to_signed(358,COORD_BITWIDTH)), std_logic_vector(to_signed(0,COORD_BITWIDTH)));
-- constant test_input_dim1 : coord_type_array := (std_logic_vector(to_signed(-258,COORD_BITWIDTH)), std_logic_vector(to_signed(-396,COORD_BITWIDTH)), std_logic_vector(to_signed(-115,COORD_BITWIDTH)), std_logic_vector(to_signed(-723,COORD_BITWIDTH)), std_logic_vector(to_signed(0,COORD_BITWIDTH)));
-- signal test_input : data_type;
begin
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
state <= phase_1_init;
elsif state = phase_1_init AND start = '1' then
state <= processing;
elsif state = processing AND comb_rdy = '1' then
state <= readout;
elsif state = readout AND readout_counter_done = '1' then
state <= phase_2_init;
elsif state = phase_2_init AND init_counter_done = '1' then
state <= gap_state1; -- 1 cycle
elsif state = gap_state1 then
state <= reset_core; -- we hope that the initialised blockram will not be flushed by this!!!
elsif state = reset_core then
state <= gap_state2; -- 1 cycle
elsif state = gap_state2 then
state <= phase_2_start; -- 1 cycle
elsif state = phase_2_start then
state <= processing; -- 1 cycle
end if;
end if;
end process fsm_proc;
single_sclr <= '1' WHEN sclr = '1' OR state = reset_core ELSE '0';
single_start <= '1' WHEN start = '1' OR state = phase_2_start ELSE '0';
readout_centre_buffers <= '1' WHEN state = readout AND divider_ii_counter = 0 ELSE '0';
counter_proc : process(clk)
begin
if rising_edge(clk) then
if state = processing OR divider_ii_counter_done = '1' then
divider_ii_counter <= (others => '0');
elsif state = readout then
divider_ii_counter <= divider_ii_counter + 1;
end if;
if state = processing then
readout_counter <= (others => '0');
elsif state = readout AND divider_ii_counter_done = '1' then
readout_counter <= readout_counter+1;
end if;
if state = processing then
init_counter <= (others => '0');
elsif comb_valid = '1' then
init_counter <= init_counter+1;
end if;
if sclr = '1' then
iterations_counter <= (others => '0');
elsif init_counter_done = '1' AND comb_valid = '1' then
iterations_counter <= iterations_counter+1;
end if;
end if;
end process counter_proc;
readout_counter_done <= '1' WHEN readout_counter = k ELSE '0';
init_counter_done <= '1' WHEN init_counter = k ELSE '0';
divider_ii_counter_done <= '1' WHEN divider_ii_counter = to_unsigned(DIVIDER_II-1,integer(ceil(log2(real(DIVIDER_II))))) ELSE '0';
iterations_counter_done <= '1' WHEN iterations_counter = to_unsigned(L_MAX-1,integer(ceil(log2(real(L_MAX))))) ELSE '0';
-- test_input(0) <= test_input_dim0(to_integer(init_counter));
-- test_input(1) <= test_input_dim1(to_integer(init_counter));
mux_wr_init_cent <= wr_init_cent; --needs to be written only once
mux_wr_centre_list_address_init <= std_logic_vector(to_unsigned(0,CNTR_POINTER_BITWIDTH));
mux_wr_centre_list_data_init <= wr_centre_list_data_init; --needs to be written only once
mux_wr_init_pos <= wr_init_pos WHEN state = phase_1_init ELSE comb_valid AND NOT(divide_by_zero); -- do not update centre if count was zero
mux_wr_centre_list_pos_address_init <= wr_centre_list_pos_address_init WHEN state = phase_1_init ELSE init_counter;
mux_wr_centre_list_pos_data_init <= wr_centre_list_pos_data_init WHEN state = phase_1_init ELSE comb_new_position;
G_PAR_2 : for I in 0 to PARALLEL_UNITS-1 generate
filtering_alogrithm_single_inst : filtering_alogrithm_single
port map(
clk => clk,
sclr => single_sclr,
start => single_start,
-- initial parameters
k => k,
root_address => root_address(I),
-- init node and centre memory
wr_init_cent => mux_wr_init_cent,
wr_centre_list_address_init => mux_wr_centre_list_address_init,
wr_centre_list_data_init => mux_wr_centre_list_data_init,
wr_init_node => wr_init_node(I),
wr_node_address_init => wr_node_address_init(I),
wr_node_data_init => wr_node_data_init(I),
wr_init_pos => mux_wr_init_pos,
wr_centre_list_pos_address_init => mux_wr_centre_list_pos_address_init,
wr_centre_list_pos_data_init => mux_wr_centre_list_pos_data_init,
-- access centre buffer
rdo_centre_buffer => readout_centre_buffers,
centre_buffer_addr => readout_counter,
valid => tmp_valid(I),
wgtCent_out => tmp_wgtCent_out(I),
sum_sq_out => tmp_sum_sq_out(I),
count_out => tmp_count_out(I),
-- processing done
rdy => tmp_rdy(I)
);
at_input_string_count((I+1)*COORD_BITWIDTH-1 downto I*COORD_BITWIDTH) <= tmp_count_out(I);
at_input_string_sum_sq((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT) <= tmp_sum_sq_out(I);
G_PAR_2_1 : for J in 0 to D-1 generate
at_input_string_wgtCent(J)((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT) <= tmp_wgtCent_out(I)(J);
end generate G_PAR_2_1;
end generate G_PAR_2;
-- wait till all parallel units have asserted rdy signal
core_rdy_reg_proc : process(clk)
begin
if rising_edge(clk) then
if single_sclr = '1' then
reg_rdy <= (others => '0');
else
for I in 0 to PARALLEL_UNITS-1 loop
reg_rdy(I) <= tmp_rdy(I);
end loop;
end if;
end if;
end process core_rdy_reg_proc;
core_rdy_proc : process(reg_rdy)
variable var_rdy : std_logic;
begin
var_rdy := '1';
for I in 0 to PARALLEL_UNITS-1 loop
var_rdy := var_rdy AND reg_rdy(I);
end loop;
comb_rdy <= var_rdy;
end process core_rdy_proc;
-- tree adders
G_PAR_3 : if PARALLEL_UNITS > 1 generate
adder_tree_inst_count : adder_tree
generic map (
USE_DSP_FOR_ADD => USE_DSP_FOR_ADD,
NUMBER_OF_INPUTS => PARALLEL_UNITS,
INPUT_BITWIDTH => COORD_BITWIDTH
)
port map(
clk => clk,
sclr => single_sclr,
nd => tmp_valid(0),
sub => '0',
input_string => at_input_string_count,
rdy => at_count_rdy,
output => at_count_out
);
G_PAR_3_1 : for J in 0 to D-1 generate
adder_tree_inst_wgtCent : adder_tree
generic map (
USE_DSP_FOR_ADD => USE_DSP_FOR_ADD,
NUMBER_OF_INPUTS => PARALLEL_UNITS,
INPUT_BITWIDTH => COORD_BITWIDTH_EXT
)
port map(
clk => clk,
sclr => single_sclr,
nd => tmp_valid(0),
sub => '0',
input_string => at_input_string_wgtCent(J),
rdy => at_wgtCent_rdy,
output => at_wgtCent_out(J)
);
tmp_wgtCent_out2(J) <= at_wgtCent_out(J)(COORD_BITWIDTH_EXT-1 downto 0);
end generate G_PAR_3_1;
adder_tree_inst_sum_sq : adder_tree
generic map (
USE_DSP_FOR_ADD => USE_DSP_FOR_ADD,
NUMBER_OF_INPUTS => PARALLEL_UNITS,
INPUT_BITWIDTH => COORD_BITWIDTH_EXT
)
port map(
clk => clk,
sclr => single_sclr,
nd => tmp_valid(0),
sub => '0',
input_string => at_input_string_sum_sq,
rdy => at_sum_sq_rdy,
output => at_sum_sq_out
);
divider_nd <= at_count_rdy;
divider_wgtCent_in <= tmp_wgtCent_out2;
divider_count_in <= at_count_out(COORD_BITWIDTH-1 downto 0);
comb_sum_sq_out <= at_sum_sq_out(COORD_BITWIDTH_EXT-1 downto 0);
end generate G_PAR_3;
G_PAR_4 : if PARALLEL_UNITS = 1 generate
divider_nd <= tmp_valid(0);
divider_wgtCent_in <= tmp_wgtCent_out(0);
divider_count_in <= tmp_count_out(0);
comb_sum_sq_out <= tmp_sum_sq_out(0);
end generate G_PAR_4;
divider_top_inst : divider_top
generic map (
ROUND => false
)
port map (
clk => clk,
sclr => sclr,
nd => divider_nd,
dividend => divider_wgtCent_in,
divisor => divider_count_in,
rdy => comb_valid,
quotient => comb_new_position,
divide_by_zero => divide_by_zero
);
-- TODO: accumulate comb_sum_sq_out and use it as a dynamic convergence criterion
valid <= comb_valid;
clusters_out <= comb_new_position;
distortion_out <= comb_sum_sq_out;
rdy <= iterations_counter_done AND init_counter_done AND comb_valid;
end Behavioral;
| bsd-3-clause | 5ebdfb5fdbb515878a4defe1f527bd88 | 0.541933 | 3.89515 | false | false | false | false |
whitef0x0/EECE353-Lab4 | lab4_challenge.vhd | 1 | 4,247 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lab4_challenge is
port(CLOCK_50 : in std_logic;
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(17 downto 0);
LEDG : out std_logic_vector(7 downto 0);
LEDR : out STD_LOGIC_VECTOR(17 downto 0);
VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0); -- The outs go to VGA controller
VGA_HS : out std_logic;
VGA_VS : out std_logic;
VGA_BLANK : out std_logic;
VGA_SYNC : out std_logic;
VGA_CLK : out std_logic);
end lab4_challenge;
architecture rtl of lab4_challenge is
-- Component from the Verilog file: vga_adapter.v
component vga_adapter
generic(RESOLUTION : string);
port (
resetn : in std_logic;
clock : in std_logic;
colour : in std_logic_vector(2 downto 0);
x : in std_logic_vector(7 downto 0);
y : in std_logic_vector(6 downto 0);
plot : in std_logic;
VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0);
VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK : out std_logic);
end component;
component fsm_challenge is
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
xdone, ydone, ldone : IN STD_LOGIC;
sw : IN STD_LOGIC_VECTOR(17 downto 0);
draw : IN STD_LOGIC;
initx, inity, loady, loadx, plot, initl, drawl : OUT STD_LOGIC;
colour : OUT STD_LOGIC_VECTOR(2 downto 0);
x : OUT STD_LOGIC_VECTOR(7 downto 0);
y : OUT STD_LOGIC_VECTOR(6 downto 0);
initLoad: OUT STD_LOGIC;
ledg : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component datapath_challenge is
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
initx, inity, loady, loadx, initl, drawl : IN STD_LOGIC;
x : OUT STD_LOGIC_VECTOR(7 downto 0);
y : OUT STD_LOGIC_VECTOR(6 downto 0);
xin : IN STD_LOGIC_VECTOR(7 downto 0); -- x1
yin : IN STD_LOGIC_VECTOR(6 downto 0); -- y1
initLoad: IN STD_LOGIC;
ledr: OUT STD_LOGIC_VECTOR(17 downto 0);
xdone, ydone, ldone : OUT STD_LOGIC
);
end component;
signal x : std_logic_vector(7 downto 0) := "00000000";
signal y : std_logic_vector(6 downto 0) := "0000000";
signal colour : std_logic_vector(2 downto 0);
signal plot : std_logic;
signal inity, initx, initl : std_logic;
signal xdone, ydone, ldone : std_logic;
signal loady, loadx, drawl : std_logic;
signal s_initLoad : std_logic;
signal xmid : std_logic_vector(7 downto 0);
signal ymid : std_logic_vector(6 downto 0);
begin
vga_u0 : vga_adapter
generic map(RESOLUTION => "160x120")
port map(resetn => KEY(3),
clock => CLOCK_50,
colour => colour,
x => x,
y => y,
plot => plot,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_HS => VGA_HS,
VGA_VS => VGA_VS,
VGA_BLANK => VGA_BLANK,
VGA_SYNC => VGA_SYNC,
VGA_CLK => VGA_CLK
);
fsm_challenge0 : fsm_challenge PORT MAP(
clock => CLOCK_50,
resetb => KEY(3),
xdone => xdone,
ydone => ydone,
ldone => ldone,
sw => SW,
draw => KEY(0),
initx => initx,
inity => inity,
loady => loady,
loadx => loadx,
plot => plot,
initl => initl,
drawl => drawl,
colour => colour,
x => xmid,
y => ymid,
initLoad => s_initLoad,
ledg => LEDG
);
datapath_challenge0 : datapath_challenge PORT MAP(
clock => CLOCK_50,
resetb => KEY(3),
initx => initx,
inity => inity,
initl => initl,
drawl => drawl,
x => x,
y => y,
xin => xmid,
yin => ymid,
xdone => xdone,
ydone => ydone,
ldone => ldone,
loady => loady,
initLoad => s_initLoad,
ledr => LEDR,
loadx => loadx
);
end rtl;
| mit | 96ac4e66207131a3e38a0314f52d0734 | 0.521074 | 3.188438 | false | false | false | false |
tsotnep/vhdl_soc_audio_mixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/axi_spdif_tx.vhd | 3 | 13,720 | ------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Copyright 2011(c) Analog Devices, Inc.
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- [email protected] (c) Analog Devices Inc.
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_spdif_tx_v1_00_a;
use axi_spdif_tx_v1_00_a.user_logic;
entity axi_spdif_tx is
generic
(
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
--SPDIF ports
spdif_data_clk : in std_logic;
spdif_tx_o : out std_logic;
spdif_tx_int_o : out std_logic;
--AXI Lite interface
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
--AXI streaming interface
ACLK : in std_logic;
ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of ACLK : signal is "Clk";
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_spdif_tx;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_spdif_tx is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 8;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity axi_spdif_tx_v1_00_a.user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
--SPDIF interface
spdif_data_clk => spdif_data_clk,
spdif_tx_o => spdif_tx_o,
spdif_tx_int_o => spdif_tx_int_o,
--AXI Lite interface
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
--AXI streaming interface
S_AXIS_ACLK => ACLK,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TVALID => S_AXIS_TVALID
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
| mit | c41b8404a55e11947d0c4502b08bbe04 | 0.482289 | 3.948201 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-2/d_flip_flop.vhd | 1 | 404 | library IEEE;
use ieee.std_logic_1164.all;
entity d_flip_flop is
port(
clk, d, rst, pre, ce : in std_logic;
q : out std_logic
);
end d_flip_flop;
architecture behav of d_flip_flop is
begin
process(clk) is
begin
if rising_edge(clk) then
if (rst='1') then
q <= '0';
elsif (pre='1') then
q <= '1';
elsif (ce='1') then
q <= d;
end if;
end if;
end process;
end behav;
| gpl-3.0 | 3579052d704054d57e11b6700caabe26 | 0.594059 | 2.463415 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/pcores/ready4hood_v1_00_a/hdl/vhdl/hash_ctrl.vhd | 3 | 4,163 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:14:33 09/17/2014
-- Design Name:
-- Module Name: hash_ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity hash_ctrl is
generic(
N : integer := 1
);
port(
clk : in std_logic;
rstn : in std_logic;
i_string_done : in std_logic; -- from string_generator
i_md5_done : in std_logic; -- the done signal from the first md5
i_hash : in std_logic_vector(127 downto 0); -- the hash to crack
i_start : in std_logic; -- from MB to start cracking
o_md5_select : out std_logic_vector(N-1 downto 0); -- to the dmux which decides which md5 to start
o_start : out std_logic; -- start signals to string-generator and cmp
o_string_halt : out std_logic; -- pause the string-generator
o_cmp_hash : out std_logic_vector(127 downto 0) -- the hash to the cmp
);
end hash_ctrl;
architecture Behavioral of hash_ctrl is
-- local signals here --
signal i_c, i_n : unsigned(N-1 downto 0);
-- the selection has to be delayed --
signal md5_sel_c, md5_sel_n : std_logic_vector(N-1 downto 0);
type state is (waiting, init, counting);
signal state_c, state_n : state;
begin
clk_proc: process(clk, rstn)
begin
if rising_edge(clk) then
if rstn = '0' then
i_c <= (others => '0');
md5_sel_c <= (others => '0');
state_c <= waiting;
else
i_c <= i_n;
md5_sel_c <= md5_sel_n;
state_c <= state_n;
end if;
end if;
end process;
FSM_proc: process(state_c, i_start, i_c, i_string_done)
begin
state_n <= state_c;
case state_c is
-- waits for a start signal --
when waiting =>
if i_start = '1' then
state_n <= init;
else
state_n <= waiting;
end if;
-- set the hash value to cmp, initialize the string_gen, wait until all md5 have data --
when init =>
if i_c = N then
state_n <= counting;
else
state_n <= init;
end if;
-- waits for a md5 to be done and checks if the hash has been cracked --
when counting =>
if i_string_done = '1' then
state_n <= waiting;
else
state_n <= counting;
end if;
end case;
end process;
data_proc: process(md5_sel_c, state_c, i_hash, i_c, i_md5_done)
begin
-- halt everything as standard --
md5_sel_n <= (others => '0');
o_start <= '0';
o_string_halt <= '1';
o_cmp_hash <= (others => '0');
o_md5_select <= md5_sel_c;
i_n <= (others => '0');
case state_c is
when init =>
-- start the string-gen and cmp --
if i_c = 0 then
o_start <= '1';
o_cmp_hash <= i_hash;
else
o_start <= '0';
o_cmp_hash <= (others => '0');
end if;
-- loop through all the md5's to give them strings and start signals --
o_string_halt <= '0';
md5_sel_n <= (others => '0');
md5_sel_n(to_integer(i_c)) <= '1';
if i_c /= N then
i_n <= i_c + 1;
else
i_n <= (others => '0');
end if;
when counting =>
if i_md5_done = '1' then
-- the first md5 is finished, start counting --
o_string_halt <= '0';
md5_sel_n <= (others => '0');
md5_sel_n(to_integer(i_c)) <= '1';
i_n <= i_c + 1;
else
if (i_c < N) and (i_c /= 0) then
-- we haven't started all the md5:s yet --
o_string_halt <= '0';
md5_sel_n <= (others => '0');
md5_sel_n(to_integer(i_c)) <= '1';
i_n <= i_c + 1;
else
-- just waiting for the done signal --
o_string_halt <= '1';
md5_sel_n <= (others => '0');
i_n <= (others => '0');
end if;
end if;
when others =>
-- we don't do anything here because the halt signals are set as standard values --
NULL;
end case;
end process;
end Behavioral;
| mit | 47d4b64c3c68ba534857ba3c4f2f4cfb | 0.531348 | 2.935825 | false | false | false | false |
RickvanLoo/Synthesizer | spi_async.vhd | 1 | 2,411 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY spi_async IS
PORT ( SCLK : IN std_logic;
RESET : IN std_logic;
SDATA : IN std_logic;
CS : IN std_logic;
BYTE0, BYTE1 : OUT std_logic_vector(7 downto 0);
dig0, dig1, dig2, dig3 : OUT std_logic_vector(6 DOWNTO 0) -- show key pressed on display dig2 en dig3 (resp high & low).
);
END spi_async;
ARCHITECTURE behav of spi_async is
FUNCTION hex2display (n:std_logic_vector(3 DOWNTO 0)) RETURN std_logic_vector IS
VARIABLE res : std_logic_vector(6 DOWNTO 0);
BEGIN
CASE n IS -- gfedcba; low active
WHEN "0000" => RETURN NOT "0111111";
WHEN "0001" => RETURN NOT "0000110";
WHEN "0010" => RETURN NOT "1011011";
WHEN "0011" => RETURN NOT "1001111";
WHEN "0100" => RETURN NOT "1100110";
WHEN "0101" => RETURN NOT "1101101";
WHEN "0110" => RETURN NOT "1111101";
WHEN "0111" => RETURN NOT "0000111";
WHEN "1000" => RETURN NOT "1111111";
WHEN "1001" => RETURN NOT "1101111";
WHEN "1010" => RETURN NOT "1110111";
WHEN "1011" => RETURN NOT "1111100";
WHEN "1100" => RETURN NOT "0111001";
WHEN "1101" => RETURN NOT "1011110";
WHEN "1110" => RETURN NOT "1111001";
WHEN OTHERS => RETURN NOT "1110001";
END CASE;
END hex2display;
signal SDATA_register : std_logic_vector(15 downto 0);
BEGIN
PROCESS(RESET, SCLK, CS)
variable byte0_reg, byte1_reg : std_logic_vector(7 downto 0);
BEGIN
if reset = '0' then
SDATA_register <= (others => '0');
BYTE0 <= (others => '0');
BYTE1 <= (others => '0');
byte0_reg := (others => '0');
byte1_reg := (others => '0');
dig0 <= hex2display("0000");
dig1 <= hex2display("0000");
dig2 <= hex2display("0000");
dig3 <= hex2display("0000");
elsif CS = '1' then
byte0_reg := SDATA_register(15 downto 8);
dig0 <= hex2display(byte0_reg(3 downto 0));
dig1 <= hex2display(byte0_reg(7 downto 4));
BYTE0 <= byte0_reg;
byte1_reg := SDATA_register(7 downto 0);
dig2 <= hex2display(byte1_reg(3 downto 0));
dig3 <= hex2display(byte1_reg(7 downto 4));
BYTE1 <= byte1_reg;
elsif rising_edge(SCLK) then
if CS = '0' then --Only get SDATA when slave is selected (Active low)
SDATA_register <= SDATA_register(14 downto 0) & SDATA; --Shift register 16 bytes
end if;
end if;
END PROCESS;
END behav; | mit | 909d2a8733eccfec5d400072c812f69e | 0.613853 | 3.14752 | false | false | false | false |
esar/hdmilight-v2 | fpga/outputConfigRam.vhd | 1 | 2,592 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2014 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity outputConfigRam is
port (
-- Port A
a_clk : in std_logic;
a_wr : in std_logic;
a_addr : in std_logic_vector(12 downto 0);
a_din : in std_logic_vector(7 downto 0);
a_dout : out std_logic_vector(7 downto 0);
-- Port B
b_clk : in std_logic;
b_addr : in std_logic_vector(11 downto 0);
b_data : out std_logic_vector(15 downto 0)
);
end outputConfigRam;
architecture Behavioral of outputConfigRam is
type mem_t is array (0 to 4095) of std_logic_vector(7 downto 0);
shared variable memOdd : mem_t;
shared variable memEven : mem_t;
signal a_doutOdd : std_logic_vector(7 downto 0);
signal a_doutEven : std_logic_vector(7 downto 0);
begin
-- Port A
process(a_clk)
begin
if(rising_edge(a_clk)) then
if(a_addr(0) = '0') then
if(a_wr = '1') then
memOdd(conv_integer(a_addr(12 downto 1))) := a_din;
end if;
end if;
a_doutOdd <= memOdd(conv_integer(a_addr(12 downto 1)));
end if;
end process;
process(a_clk)
begin
if(rising_edge(a_clk)) then
if(a_addr(0) = '1') then
if(a_wr = '1') then
memEven(conv_integer(a_addr(12 downto 1))) := a_din;
end if;
end if;
a_doutEven <= memEven(conv_integer(a_addr(12 downto 1)));
end if;
end process;
a_dout <= a_doutOdd when a_addr(0) = '0' else a_doutEven;
-- Port B
process(b_clk)
begin
if(rising_edge(b_clk)) then
b_data( 7 downto 0) <= memOdd(conv_integer(b_addr(11 downto 0)));
end if;
end process;
process(b_clk)
begin
if(rising_edge(b_clk)) then
b_data(15 downto 8) <= memEven(conv_integer(b_addr(11 downto 0)));
end if;
end process;
end Behavioral;
| gpl-2.0 | f067a6cca640b2852158df1cc06ee11a | 0.633873 | 3.056604 | false | false | false | false |
freecores/gpib_controller | vhdl/src/common/helperComponents.vhd | 1 | 7,831 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: helperComponents
-- Date:2011-11-10
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package helperComponents is
component gpibReader is
port (
-- clock
clk : in std_logic;
-- reset
reset : std_logic;
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
-- input data
data_in : in std_logic_vector (7 downto 0);
-- data valid
dvd : in std_logic;
-- listener active
lac : in std_logic;
-- last byte
lsb : in std_logic;
-- ready to next byte
rdy : out std_logic;
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
-- is LE function active
isLE : in std_logic;
-- current secondary address
secAddr : in std_logic_vector (4 downto 0);
-- secondary address of data
dataSecAddr : out std_logic_vector (4 downto 0);
-- buffer ready interrupt
buf_interrupt : out std_logic;
-- indicates end of stream
end_of_stream : out std_logic;
-- resets reader
reset_reader : in std_logic;
------------------ fifo --------------------------------------
-- indicates fifo full
fifo_full : in std_logic;
-- indicates fifo ready to write
fifo_ready_to_write : in std_logic;
-- indicates at least one byte in fifo
at_least_one_byte_in_fifo : in std_logic;
-- output data
data_out : out std_logic_vector (7 downto 0);
-- fifo strobe
fifo_strobe : out std_logic
);
end component;
component gpibWriter is
port (
-- clock
clk : in std_logic;
-- reset
reset : std_logic;
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
-- output data
data_out : out std_logic_vector (7 downto 0);
-- wait for new cycle
wnc : in std_logic;
-- seriall poll active
spa : in std_logic;
-- new byte available
nba : out std_logic;
-- end of string
endOf : out std_logic;
-- talker active
tac : in std_logic;
-- controller write command
cwrc : in std_logic;
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
-- TE is extended
isTE : in std_logic;
-- current secondary address
secAddr : in std_logic_vector (4 downto 0);
-- secondary address of data
dataSecAddr : in std_logic_vector (4 downto 0);
-- buffer consumed
buf_interrupt : out std_logic;
-- indicates end of stream
end_of_stream : in std_logic;
-- resets writer
reset_writer : in std_logic;
-- enables writer
writer_enable : in std_logic;
---------------- fifo ---------------------------
availableFifoBytesCount : in std_logic_vector(10 downto 0);
-- fifo read strobe
fifo_read_strobe : out std_logic;
-- indicates fifo ready to read
fifo_ready_to_read : in std_logic;
-- input data
fifo_data_in : in std_logic_vector (7 downto 0)
);
end component;
component SerialPollCoordinator is
port (
-- clock
clk : in std_logic;
-- reset
reset : in std_logic;
-- data accepted
DAC : in std_logic;
-- receive status byte
rec_stb : in std_logic;
-- attention in
ATN_in : in std_logic;
-- attention out
ATN_out : out std_logic;
-- output valid in
output_valid_in : in std_logic;
-- output valid out
output_valid_out : out std_logic;
-- stb received
stb_received : out std_logic
);
end component;
component MemoryBlock is
port (
reset : in std_logic;
clk : in std_logic;
-------------------------------------------------
p1_addr : in std_logic_vector(10 downto 0);
p1_data_in : in std_logic_vector(7 downto 0);
p1_strobe : in std_logic;
p1_data_out : out std_logic_vector(7 downto 0);
-------------------------------------------------
p2_addr : in std_logic_vector(10 downto 0);
p2_data_in : in std_logic_vector(7 downto 0);
p2_strobe : in std_logic;
p2_data_out : out std_logic_vector(7 downto 0)
);
end component;
component Fifo8b is
generic (
MAX_ADDR_BIT_NUM : integer := 10
);
port (
reset : in std_logic;
clk : in std_logic;
-------------- fifo --------------------
bytesAvailable : out std_logic;
availableBytesCount : out std_logic_vector(MAX_ADDR_BIT_NUM downto 0);
bufferFull : out std_logic;
resetFifo : in std_logic;
----------------------------------------
data_in : in std_logic_vector(7 downto 0);
ready_to_write :out std_logic;
strobe_write : in std_logic;
----------------------------------------
data_out : out std_logic_vector(7 downto 0);
ready_to_read : out std_logic;
strobe_read : in std_logic
);
end component;
component Clk2x is
port (
reset: in std_logic;
clk : in std_logic;
clk2x : out std_logic
);
end component;
component SinglePulseGenerator is
generic (
WIDTH : integer := 3
);
port (
reset : in std_logic;
clk : in std_logic;
t_in: in std_logic;
t_out : out std_logic;
pulse : out std_logic
);
end component;
component EdgeDetector is
generic (
RISING : std_logic := '1';
FALLING : std_logic := '0';
PULSE_WIDTH : integer := 10
);
port (
reset : in std_logic;
clk : in std_logic;
in_data : in std_logic;
pulse : out std_logic
);
end component;
component EventMem is
port (
reset : std_logic;
-- event occured
occured : in std_logic;
-- event approved
approved : in std_logic;
-- output
output : out std_logic
);
end component;
component GpibSynchronizer is
port (
-- clk
clk : std_logic;
-- DIO
DI : in std_logic_vector (7 downto 0);
DO : out std_logic_vector (7 downto 0);
-- attention
ATN_in : in std_logic;
ATN_out : out std_logic;
-- data valid
DAV_in : in std_logic;
DAV_out : out std_logic;
-- not ready for data
NRFD_in : in std_logic;
NRFD_out : out std_logic;
-- no data accepted
NDAC_in : in std_logic;
NDAC_out : out std_logic;
-- end or identify
EOI_in : in std_logic;
EOI_out : out std_logic;
-- service request
SRQ_in : in std_logic;
SRQ_out : out std_logic;
-- interface clear
IFC_in : in std_logic;
IFC_out : out std_logic;
-- remote enable
REN_in : in std_logic;
REN_out : out std_logic
);
end component;
end helperComponents;
| gpl-3.0 | 6b406cea4d343b3e837d7d4243daae53 | 0.532116 | 3.697356 | false | false | false | false |
mithro/HDMI2USB | hdl/jpeg_encoder/design/MDCT_PKG.vhd | 5 | 4,295 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : MDCT_PKG
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : MDCT_PKG.VHD
-- Created : Sat Mar 5 2006
--
--------------------------------------------------------------------------------
--
-- Description : Package for MDCT core
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package MDCT_PKG is
constant IP_W : INTEGER := 8;
constant OP_W : INTEGER := 12;
constant N : INTEGER := 8;
constant COE_W : INTEGER := 12;
constant ROMDATA_W : INTEGER := COE_W+2;
constant ROMADDR_W : INTEGER := 6;
constant RAMDATA_W : INTEGER := 10;
constant RAMADRR_W : INTEGER := 6;
constant COL_MAX : INTEGER := N-1;
constant ROW_MAX : INTEGER := N-1;
constant LEVEL_SHIFT : INTEGER := 128;
constant DA_W : INTEGER := ROMDATA_W+IP_W;
constant DA2_W : INTEGER := DA_W+2;
-- 2's complement numbers
constant AP : INTEGER := 1448;
constant BP : INTEGER := 1892;
constant CP : INTEGER := 784;
constant DP : INTEGER := 2009;
constant EP : INTEGER := 1703;
constant FP : INTEGER := 1138;
constant GP : INTEGER := 400;
constant AM : INTEGER := -1448;
constant BM : INTEGER := -1892;
constant CM : INTEGER := -784;
constant DM : INTEGER := -2009;
constant EM : INTEGER := -1703;
constant FM : INTEGER := -1138;
constant GM : INTEGER := -400;
type T_ROM1DATAO is array(0 to 8) of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
type T_ROM1ADDRO is array(0 to 8) of STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
type T_ROM2DATAO is array(0 to 10) of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
type T_ROM2ADDRO is array(0 to 10) of STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
end MDCT_PKG; | bsd-2-clause | bb4cf106310467fe780a165913a8363c | 0.504307 | 4.564293 | false | false | false | false |
kb3gtn/mojo_modulator | vhdl/src/cos_nco.vhd | 1 | 3,767 | ----------------------------------------------------------------------------------
-- cos_nco.vhd
--
-- This block implements a cos generating Numerically Controlled Oscilator (NCO)
--
-- This block is basically a phase accumulator and a cos phase lookup table.
--
-- This block has a 3 clock delay between when a input parameter (phase offset or
-- freq) is changed untill the output responds to it.
--
-- This delay also affects startup out of a reset. It will take 3 clock cycles for
-- the NCO to produce the output based on the input.
--
-- NCO default output value while starting up is 0
--
-- This block can be used to generate a sin() function as well by just adding
-- 1/4 phase depth to the phase_offset port.
--
-- Peter Fetterer (KB3GTN)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity cos_nco is
generic (
constant phase_acc_size : integer := 32; -- 32bit freq resultion
constant sample_depth : integer := 16; -- number of bits in output samples
constant phase_depth : integer := 12 -- resolution of the phase generation
);
port (
i_clk : in std_logic; -- sample rate clock
i_srst : in std_logic; -- sync reset to provided clock
----------------------------------------
i_phase_offset : in unsigned( phase_depth-1 downto 0 ); -- phase shift input
i_freq_word : in unsigned( phase_acc_size-1 downto 0); -- frequency input
o_sample : out signed( sample_depth-1 downto 0) -- output samples, every clock
);
end entity cos_nco;
architecture system of cos_nco is
----------------------
-- components
----------------------
component cos_phase_table is
generic (
constant sample_depth : integer := 16; -- number of bits in output sample (1->N)
constant phase_depth : integer := 12 -- number of bits for phase input value (1->N)
);
port (
i_clk : in std_logic; -- input DSP clock
i_srst : in std_logic; -- input sync reset to dsp clock
---------------------------------------------------------
x : in unsigned( phase_depth-1 downto 0 ); -- digital normalized phase input (0->2*pi)
y : out signed( sample_depth-1 downto 0 ) -- output value signed 16b
);
end component cos_phase_table;
------------------------
-- signals
------------------------
signal phase_acc : unsigned( phase_acc_size-1 downto 0 ); -- phase accumulator
signal gen_phase : unsigned( phase_depth-1 downto 0 ); -- phase to lookup table
begin
-- Instantiate the Unit Under Test (UUT)
u_phase_table: cos_phase_table
GENERIC Map (
sample_depth => sample_depth,
phase_depth => phase_depth
)
PORT MAP (
i_clk => i_clk,
i_srst => i_srst,
x => gen_phase,
y => o_sample
);
-- accumulate phase to generate full period of cos wave..
phase_accumulator : process( i_clk )
begin
if ( rising_edge(i_clk) ) then
if ( i_srst = '1' ) then
phase_acc <= (others=>'0'); -- reset phase accumulator to 0 phase
else
-- overflows roll over..
phase_acc <= (phase_acc + i_freq_word); -- add phase_steps/clock period
gen_phase <= phase_acc(phase_acc_size-1 downto (phase_acc_size-phase_depth)) + i_phase_offset;
end if;
end if;
end process;
end architecture system;
| apache-2.0 | 35c42b67c7d02eef2cf684201adca48a | 0.522963 | 4.339862 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/compute_distance.vhd | 1 | 5,680 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: compute_distance_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity compute_distance_top is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
point_1 : in data_type_ext;
point_2 : in data_type_ext;
point_2_idx : in centre_index_type;
distance : out coord_type_ext;
point_1_out : out data_type_ext;
point_2_out : out data_type_ext;
point_2_idx_out : out centre_index_type;
rdy : out std_logic
);
end compute_distance_top;
architecture Behavioral of compute_distance_top is
constant LAT_DOT_PRODUCT : integer := MUL_CORE_LATENCY+2*integer(ceil(log2(real(D))));
constant LAT_SUB : integer := 2;
constant LATENCY : integer := LAT_DOT_PRODUCT+LAT_SUB;
type data_delay_type is array(0 to LATENCY-1) of data_type_ext;
type idx_delay_type is array(0 to LATENCY-1) of centre_index_type;
component addorsub
generic (
USE_DSP : boolean := true;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
component dot_product
generic (
SCALE_MUL_RESULT : integer := 0
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
point_1 : in data_type_ext;
point_2 : in data_type_ext;
result : out coord_type_ext;
rdy : out std_logic
);
end component;
signal tmp_diff : data_type_ext;
signal tmp_sub_rdy : std_logic;
signal tmp_dot_product_rdy : std_logic;
signal tmp_dot_product_result : coord_type_ext;
signal data_delay_1 : data_delay_type;
signal data_delay_2 : data_delay_type;
signal idx_delay_2 : idx_delay_type;
begin
G1: for I in 0 to D-1 generate
G_FIRST: if I = 0 generate
addorsub_inst : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => COORD_BITWIDTH_EXT,
B_BITWIDTH => COORD_BITWIDTH_EXT,
RES_BITWIDTH => COORD_BITWIDTH_EXT
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
sub => '1',
a => point_1(I),
b => point_2(I),
res => tmp_diff(I),
rdy => tmp_sub_rdy
);
end generate G_FIRST;
G_OTHER: if I > 0 generate
addorsub_inst : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => COORD_BITWIDTH_EXT,
B_BITWIDTH => COORD_BITWIDTH_EXT,
RES_BITWIDTH => COORD_BITWIDTH_EXT
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
sub => '1',
a => point_1(I),
b => point_2(I),
res => tmp_diff(I),
rdy => open
);
end generate G_OTHER;
end generate G1;
dot_product_inst : dot_product
generic map (
SCALE_MUL_RESULT => MUL_FRACTIONAL_BITS
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_sub_rdy,
point_1 => tmp_diff,
point_2 => tmp_diff,
result => tmp_dot_product_result,
rdy => tmp_dot_product_rdy
);
-- feed point_2 from input of this unit to output
data_delay_proc : process(clk)
begin
if rising_edge(clk) then
data_delay_1(0) <= point_1;
data_delay_1(1 to LATENCY-1) <= data_delay_1(0 to LATENCY-2);
data_delay_2(0) <= point_2;
data_delay_2(1 to LATENCY-1) <= data_delay_2(0 to LATENCY-2);
idx_delay_2(0) <= point_2_idx;
idx_delay_2(1 to LATENCY-1) <= idx_delay_2(0 to LATENCY-2);
end if;
end process data_delay_proc;
rdy <= tmp_dot_product_rdy;
distance <= tmp_dot_product_result;
point_1_out <= data_delay_1(LATENCY-1);
point_2_out <= data_delay_2(LATENCY-1);
point_2_idx_out <= idx_delay_2(LATENCY-1);
end Behavioral;
| bsd-3-clause | 221e1e435ed3ff0ab6c55ec7a86e4a7d | 0.486092 | 4.083393 | false | false | false | false |
RickvanLoo/Synthesizer | trilut_entity.vhd | 1 | 2,320 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
ENTITY trilut_entity IS
GENERIC(lut_bit_width : integer := 8;
DATA_width: integer := 16
);
PORT(
phase_in : in unsigned(lut_bit_width-1 downto 0);
a_clk : in std_logic;
reset : in std_logic;
DATA : OUT std_logic_vector(15 downto 0)
);
END trilut_entity;
architecture behav of trilut_entity is
--LUT
type sine_lut is array (0 to (2**lut_bit_width)-1) of integer;
constant sinedata:sine_lut:= (-7875,-7750,-7625,-7500,-7375,-7250,-7125,-7000,-6875,-6750,-6625,-6500,-6375,-6250,-6125,-6000,-5875,-5750,-5625,-5500,-5375,-5250,-5125,-5000,-4875,-4750,-4625,-4500,-4375,-4250,-4125,-4000,-3875,-3750,-3625,-3500,-3375,-3250,-3125,-3000,-2875,-2750,-2625,-2500,-2375,-2250,-2125,-2000,-1875,-1750,-1625,-1500,-1375,-1250,-1125,-1000,-875,-750,-625,-500,-375,-250,-125,0,125,250,375,500,625,750,875,1000,1125,1250,1375,1500,1625,1750,1875,2000,2125,2250,2375,2500,2625,2750,2875,3000,3125,3250,3375,3500,3625,3750,3875,4000,4125,4250,4375,4500,4625,4750,4875,5000,5125,5250,5375,5500,5625,5750,5875,6000,6125,6250,6375,6500,6625,6750,6875,7000,7125,7250,7375,7500,7625,7750,7875,8000,7875,7750,7625,7500,7375,7250,7125,7000,6875,6750,6625,6500,6375,6250,6125,6000,5875,5750,5625,5500,5375,5250,5125,5000,4875,4750,4625,4500,4375,4250,4125,4000,3875,3750,3625,3500,3375,3250,3125,3000,2875,2750,2625,2500,2375,2250,2125,2000,1875,1750,1625,1500,1375,1250,1125,1000,875,750,625,500,375,250,125,0,-125,-250,-375,-500,-625,-750,-875,-1000,-1125,-1250,-1375,-1500,-1625,-1750,-1875,-2000,-2125,-2250,-2375,-2500,-2625,-2750,-2875,-3000,-3125,-3250,-3375,-3500,-3625,-3750,-3875,-4000,-4125,-4250,-4375,-4500,-4625,-4750,-4875,-5000,-5125,-5250,-5375,-5500,-5625,-5750,-5875,-6000,-6125,-6250,-6375,-6500,-6625,-6750,-6875,-7000,-7125,-7250,-7375,-7500,-7625,-7750,-7875,-8000);
signal sDATA : std_logic_vector(15 downto 0);
begin
process(a_clk,reset)
variable lutindex : integer range 0 to (2**lut_bit_width)-1 := 0;
begin
if reset = '0' then
DATA <= (others => '0');
lutindex := 0;
elsif rising_edge(a_clk) then
lutindex := to_integer(phase_in);
sDATA <= std_logic_vector(to_signed(sinedata(lutindex), DATA_width));
DATA <= sDATA;
end if;
end process;
end behav; | mit | e4894ebbeadbaca245e6343196cf7908 | 0.685776 | 2.785114 | false | false | false | false |
whitef0x0/EECE353-Lab4 | fsm.vhd | 1 | 3,635 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.ALL;
ENTITY fsm IS
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
xdone, ydone, ldone : IN STD_LOGIC;
sw : IN STD_LOGIC_VECTOR(17 downto 0);
draw : IN STD_LOGIC;
resetx, resety, incr_y, incr_x, plot, initl, drawl : OUT STD_LOGIC;
colour : OUT STD_LOGIC_VECTOR(2 downto 0);
x : OUT STD_LOGIC_VECTOR(7 downto 0);
y : OUT STD_LOGIC_VECTOR(6 downto 0);
ledg : OUT STD_LOGIC_VECTOR(7 downto 0)
);
END fsm;
ARCHITECTURE behavioural OF fsm IS
TYPE state_types is (CLEAR_START, CLEAR_NEXTROW, CLEAR_NEXTCOL, LOAD_INPUT, INIT_LINE, DRAW_LINE, DONE_LINE);
SIGNAL curr_state, next_state : state_types := CLEAR_START;
BEGIN
PROCESS(clock, resetb)
--VARIABLE next_state : state_types;
BEGIN
IF (resetb = '0') THEN
curr_state <= CLEAR_START;
ELSIF rising_edge(clock) THEN
curr_state <= next_state;
END IF;
END PROCESS;
PROCESS(curr_state, next_state)
BEGIN
CASE curr_state IS
WHEN CLEAR_START =>
resetx <= '1';
resety <= '1';
incr_y <= '1';
incr_x <= '1';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
colour <= "000";
ledg <= "00000000";
next_state <= CLEAR_NEXTCOL;
--Clear next row
WHEN CLEAR_NEXTROW =>
resetx <= '1';
resety <= '0';
incr_y <= '1';
incr_x <= '1';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
ledg <= "00000001";
next_state <= CLEAR_NEXTCOL;
--Clear next column
WHEN CLEAR_NEXTCOL =>
resetx <= '0';
resety <= '0';
incr_y <= '0';
incr_x <= '1';
INITL <= '0';
DRAWL <= '0';
PLOT <= '1';
ledg <= "00000010";
IF (XDONE = '0') THEN
next_state <= CLEAR_NEXTCOL;
ELSIF (XDONE = '1' AND YDONE = '0') THEN
next_state <= CLEAR_NEXTROW;
ELSE
next_state <= LOAD_INPUT;
END IF;
when LOAD_INPUT =>
resetx <= '0';
resety <= '0';
incr_y <= '0';
incr_x <= '0';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
ledg <= "00000100";
--When draw signal is low, initialize line with input
IF (draw = '0') THEN
x <= sw(17 downto 10);
y <= sw(9 downto 3);
--Clip input to within bounds
IF (unsigned(sw(17 downto 10)) > 159) THEN
x <= "10011111";
END IF;
IF (unsigned(sw(9 downto 3)) > 119) THEN
y <= "1110111";
END IF;
next_state <= INIT_LINE;
ELSE
next_state <= LOAD_INPUT;
END IF;
WHEN INIT_LINE =>
resetx <= '0';
resety <= '0';
incr_y <= '0';
incr_x <= '0';
INITL <= '1';
DRAWL <= '0';
PLOT <= '0';
ledg <= "00001000";
--colour <= "000";
colour <= sw(2 downto 0);
next_state <= DRAW_LINE;
WHEN DRAW_LINE =>
colour <= sw(2 downto 0);
resetx <= '0';
resety <= '0';
incr_y <= '0';
incr_x <= '0';
INITL <= '0';
DRAWL <= '1';
PLOT <= '1';
ledg <= "00010000";
--If line is done drawing, move to finished line (DONE_LINE) state
IF (LDONE = '1') THEN
ledg <= "11111111";
next_state <= DONE_LINE;
ELSE
next_state <= DRAW_LINE;
END IF;
WHEN DONE_LINE =>
resetx <= '0';
resety <= '0';
incr_y <= '0';
incr_x <= '0';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
next_state <= LOAD_INPUT;
WHEN others =>
resetx <= '0';
resety <= '0';
incr_y <= '0';
incr_x <= '0';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
next_state <= DONE_LINE;
END CASE;
END PROCESS;
END behavioural;
| mit | 21dd9ccd71ff156dfa0ec8745d20f5a5 | 0.514168 | 2.905675 | false | false | false | false |
freecores/gpib_controller | vhdl/src/wrapper/WriterControlReg0.vhd | 1 | 3,127 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: WriterControlReg0
-- Date:2011-11-10
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.utilPkg.all;
use work.helperComponents.all;
entity WriterControlReg0 is
port (
clk : in std_logic;
reset : in std_logic;
strobe : in std_logic;
data_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
------------------- gpib -------------------------
-- buffer consumed
buf_interrupt : in std_logic;
-- data avilable - at least one byte in buffer
data_available : out std_logic;
-- indicates end of stream
end_of_stream : out std_logic;
-- resets buffer
reset_buffer : out std_logic;
-- secondary address of data
dataSecAddr : out std_logic_vector (4 downto 0);
-- serial poll status byte
status_byte : out std_logic_vector (6 downto 0)
);
end WriterControlReg0;
architecture arch of WriterControlReg0 is
signal i_data_available : std_logic;
signal i_end_of_stream : std_logic;
signal i_reset_buffer : std_logic;
signal i_dataSecAddr : std_logic_vector (4 downto 0);
signal i_status_byte : std_logic_vector (6 downto 0);
signal t_in, t_out : std_logic;
begin
data_out(0) <= buf_interrupt;
data_out(1) <= i_data_available;
data_out(2) <= i_end_of_stream;
data_out(3) <= i_reset_buffer;
data_out(8 downto 4) <= i_dataSecAddr;
data_out(15 downto 9) <= i_status_byte;
data_available <= i_data_available;
end_of_stream <= i_end_of_stream;
reset_buffer <= i_reset_buffer;
dataSecAddr <= i_dataSecAddr;
status_byte <= i_status_byte;
process (reset, strobe) begin
if reset = '1' then
t_in <= '0';
i_data_available <= '1';
elsif rising_edge(strobe) then
i_data_available <= data_in(1);
i_end_of_stream <= data_in(2);
if data_in(3) = '1' then
t_in <= not t_out;
end if;
i_dataSecAddr <= data_in(8 downto 4);
i_status_byte <= data_in(15 downto 9);
end if;
end process;
spg: SinglePulseGenerator generic map (WIDTH => 3) port map(
reset => reset, clk => clk,
t_in => t_in, t_out => t_out,
pulse => i_reset_buffer
);
end arch;
| gpl-3.0 | 5d5fc46bfbd3ddac8a40de6785185502 | 0.622961 | 3.387866 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/edidram/simulation/random.vhd | 6 | 4,108 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
| bsd-2-clause | ff4ee4cc7ab186542451287993d56baf | 0.59445 | 4.711009 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/cmdfifo/simulation/cmdfifo_dgen.vhd | 3 | 5,110 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cmdfifo_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.cmdfifo_pkg.ALL;
ENTITY cmdfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF cmdfifo_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
SIGNAL wr_d_sel : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:cmdfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= (AND_REDUCE(wr_d_sel)) AND PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DOUT_WIDTH-C_DIN_WIDTH*conv_integer(wr_d_sel)-1 DOWNTO C_DOUT_WIDTH-C_DIN_WIDTH*(conv_integer(wr_d_sel)+1));
PROCESS(WR_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
wr_d_sel <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK = '1') THEN
IF(FULL = '0' AND PRC_WR_EN = '1') THEN
wr_d_sel <= wr_d_sel + "1";
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| bsd-2-clause | 0d8ac252e7caf41155e9b4f4f9ac7e6f | 0.593151 | 4.026793 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/patternClk/simulation/patternClk_tb.vhd | 3 | 6,141 | -- file: patternClk_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity patternClk_tb is
end patternClk_tb;
architecture test of patternClk_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.0 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component patternClk_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : patternClk_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
| bsd-2-clause | 2de221b6ca87d697c71a49d4ef43db1d | 0.639635 | 4.324648 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/ISE/fsl_test/tb_fsl_test.vhd | 1 | 3,758 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:07:54 09/29/2014
-- Design Name:
-- Module Name: C:/Users/ael10jso/Xilinx/embedded_bruteforce/brutus_system/ISE/fsl_test/tb_fsl_test.vhd
-- Project Name: fsl_test
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: test
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_fsl_test IS
END tb_fsl_test;
ARCHITECTURE behavior OF tb_fsl_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT test
PORT(
FSL_Clk : IN std_logic;
FSL_Rst : IN std_logic;
FSL_S_Clk : IN std_logic;
FSL_S_Read : OUT std_logic;
FSL_S_Data : IN std_logic_vector(0 to 31);
FSL_S_Control : IN std_logic;
FSL_S_Exists : IN std_logic;
FSL_M_Clk : IN std_logic;
FSL_M_Write : OUT std_logic;
FSL_M_Data : OUT std_logic_vector(0 to 31);
FSL_M_Control : OUT std_logic;
FSL_M_Full : IN std_logic
);
END COMPONENT;
--Inputs
signal FSL_Clk : std_logic := '0';
signal FSL_Rst : std_logic := '0';
signal FSL_S_Clk : std_logic := '0';
signal FSL_S_Data : std_logic_vector(0 to 31) := (others => '0');
signal FSL_S_Control : std_logic := '0';
signal FSL_S_Exists : std_logic := '0';
signal FSL_M_Clk : std_logic := '0';
signal FSL_M_Full : std_logic := '0';
--Outputs
signal FSL_S_Read : std_logic;
signal FSL_M_Write : std_logic;
signal FSL_M_Data : std_logic_vector(0 to 31);
signal FSL_M_Control : std_logic;
-- Clock period definitions
constant FSL_Clk_period : time := 10 ns;
constant FSL_S_Clk_period : time := 10 ns;
constant FSL_M_Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: test PORT MAP (
FSL_Clk => FSL_Clk,
FSL_Rst => FSL_Rst,
FSL_S_Clk => FSL_S_Clk,
FSL_S_Read => FSL_S_Read,
FSL_S_Data => FSL_S_Data,
FSL_S_Control => FSL_S_Control,
FSL_S_Exists => FSL_S_Exists,
FSL_M_Clk => FSL_M_Clk,
FSL_M_Write => FSL_M_Write,
FSL_M_Data => FSL_M_Data,
FSL_M_Control => FSL_M_Control,
FSL_M_Full => FSL_M_Full
);
-- Clock process definitions
FSL_Clk_process :process
begin
FSL_Clk <= '0';
wait for FSL_Clk_period/2;
FSL_Clk <= '1';
wait for FSL_Clk_period/2;
end process;
FSL_S_Clk_process :process
begin
FSL_S_Clk <= '0';
wait for FSL_S_Clk_period/2;
FSL_S_Clk <= '1';
wait for FSL_S_Clk_period/2;
end process;
FSL_M_Clk_process :process
begin
FSL_M_Clk <= '0';
wait for FSL_M_Clk_period/2;
FSL_M_Clk <= '1';
wait for FSL_M_Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for FSL_Clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit | 4cd94d79a72f9786eb42103ddb82ebc3 | 0.576637 | 3.296491 | false | true | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/memory_mgmt.vhd | 1 | 14,561 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: memory_mgmt - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity memory_mgmt is
port (
clk : in std_logic;
sclr : in std_logic;
rd : in std_logic;
rd_node_addr : in node_address_type;
rd_centre_list_address : in centre_list_address_type;
rd_k : in centre_index_type;
wr_cent_nd : in std_logic;
wr_cent : in std_logic;
wr_centre_list_address : in centre_list_address_type;
wr_centre_list_data : in centre_index_type;
wr_init_cent : in std_logic;
wr_centre_list_address_init : in centre_list_address_type;
wr_centre_list_data_init : in centre_index_type;
wr_init_node : in std_logic;
wr_node_address_init : in node_address_type;
wr_node_data_init : in node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
valid : out std_logic;
rd_node_data : out node_data_type;
rd_centre_list_data : out centre_index_type;
rd_centre_list_pos_data : out data_type;
last_centre : out std_logic;
item_read_twice : out std_logic;
rd_centre_list_address_out : out centre_list_address_type
);
end memory_mgmt;
architecture Behavioral of memory_mgmt is
constant CENTRE_LIST_ADDR_BITWIDTH : integer := CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH;
constant MEM_LAT : integer := 3;
constant MEM_POS_LAT : integer := 2;
type rd_state_type is (idle, reading_centre_list);
type wr_state_type is (idle, writing_centre_list);
type centre_index_delay_type is array(0 to MEM_POS_LAT-1) of centre_index_type;
type node_data_delay_type is array(0 to MEM_POS_LAT-1) of node_data_type;
type centre_list_address_delay_type is array(0 to MEM_POS_LAT-1) of centre_list_address_type;
component node_memory_top
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
dina : in std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0);
clkb : in std_logic;
addrb : in std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
doutb : out std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0)
);
end component;
component centre_index_memory_top
port (
clk : in std_logic;
sclr : in std_logic;
rd : in std_logic;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
item_read_twice : out std_logic;
item_address : out std_logic_vector(CNTR_POINTER_BITWIDTH-1 downto 0)
);
end component;
component centre_positions_memory
port (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(D*COORD_BITWIDTH-1 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(D*COORD_BITWIDTH-1 DOWNTO 0)
);
end component;
signal rd_state : rd_state_type;
signal rd_counter_done : std_logic;
signal rd_counter : centre_index_type;
signal wr_state : wr_state_type;
signal wr_counter : centre_index_type;
signal reading_centres : std_logic;
signal delay_line : std_logic_vector(0 to MEM_LAT+MEM_POS_LAT+1-1);
signal rd_centre_list_address_reg : centre_list_address_type;
signal tmp_rd_centre_list_address : std_logic_vector(CENTRE_LIST_ADDR_BITWIDTH-1 downto 0);
signal rd_k_reg : centre_index_type;
signal rd_node_address_reg : node_address_type;
signal wr_centre_list_wea : std_logic;
signal virtual_write_address_reg : std_logic;
signal wr_centre_list_address_mux : centre_list_address_type;
signal wr_centre_list_address_reg : centre_list_address_type;
signal tmp_wr_centre_list_address : std_logic_vector(CENTRE_LIST_ADDR_BITWIDTH-1 downto 0);
signal wr_cent_reg : std_logic;
signal wr_centre_list_data_mux : centre_index_type;
signal wr_centre_list_data_reg : centre_index_type;
signal tmp_item_read_twice : std_logic;
signal tmp_item_address : centre_list_address_type;
signal wr_node_reg : std_logic;
signal wr_node_address_reg : node_address_type;
signal wr_node_data_reg : node_data_type;
signal tmp_wr_node_address : std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
signal tmp_wr_node_data_in : std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0);
signal tmp_rd_node_data_out : std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0);
signal tmp_rd_node_address : std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
signal node_data_delay : node_data_delay_type;
signal tmp_centre_in : std_logic_vector(INDEX_BITWIDTH-1 downto 0);
signal tmp_centre_out : std_logic_vector(INDEX_BITWIDTH-1 downto 0);
signal centre_out_delay_line : centre_index_delay_type;
signal item_read_twice_delay_line : std_logic_vector(0 to MEM_POS_LAT-1);
signal centre_list_address_delay : centre_list_address_delay_type;
signal tmp_wr_centre_list_pos_data_init : std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
signal tmp_centre_pos_out : std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
begin
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
rd_state <= idle;
elsif rd_state = idle AND rd = '1' then
rd_state <= reading_centre_list;
elsif rd_state = reading_centre_list AND rd_counter_done = '1' then
rd_state <= idle;
end if;
if sclr = '1' then
wr_state <= idle;
elsif wr_state = idle AND (wr_cent_nd = '1' OR wr_init_cent = '1') then
wr_state <= writing_centre_list;
elsif wr_state = writing_centre_list AND (wr_cent_nd = '0' AND wr_init_cent = '0') then
wr_state <= idle;
end if;
end if;
end process fsm_proc;
counter_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
rd_counter <= (others => '0');
else
if rd_state <= idle then
rd_counter <= (others => '0');
else
rd_counter <= rd_counter+1;
end if;
end if;
if sclr = '1' then
wr_counter <= (others => '0');
else
if wr_state <= idle then
wr_counter <= (others => '0');
elsif wr_cent_reg = '1' then --(wr_cent_nd ='1' AND wr_cent='1') OR wr_init_cent='1' then
wr_counter <= wr_counter+1;
end if;
end if;
end if;
end process counter_proc;
rd_counter_done <= '1' WHEN rd_counter = rd_k_reg AND rd_state = reading_centre_list ELSE '0';
addr_reg_proc : process(clk)
begin
if rising_edge(clk) then
if rd_state = idle AND rd = '1' then
rd_centre_list_address_reg <= rd_centre_list_address;
rd_node_address_reg <= rd_node_addr;
rd_k_reg <= rd_k;
end if;
end if;
end process addr_reg_proc;
-- mux between init and normal wr
wr_centre_list_address_mux <= wr_centre_list_address WHEN wr_init_cent = '0' ELSE wr_centre_list_address_init;
wr_centre_list_data_mux <= wr_centre_list_data WHEN wr_init_cent = '0' ELSE wr_centre_list_data_init;
-- delay buffer wr input by one cycle due to state machine
wr_input_reg_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
wr_cent_reg <= '0';
wr_node_reg <= '0';
else
wr_cent_reg <= (wr_cent_nd AND wr_cent) OR wr_init_cent;
wr_node_reg <= wr_init_node;
end if;
if ((wr_state = idle AND wr_cent_nd = '1') OR wr_init_cent = '1') then
wr_centre_list_address_reg <= wr_centre_list_address_mux;
end if;
if sclr = '1' then
virtual_write_address_reg <= '0';
elsif (wr_state = idle AND wr_cent_nd = '1') then
if wr_centre_list_address = std_logic_vector(to_unsigned(0,CNTR_POINTER_BITWIDTH)) then
virtual_write_address_reg <= '1';
else
virtual_write_address_reg <= '0';
end if;
end if;
wr_centre_list_data_reg <= wr_centre_list_data_mux;
wr_node_address_reg <= wr_node_address_init;
wr_node_data_reg <= wr_node_data_init;
end if;
end process wr_input_reg_proc;
tmp_rd_centre_list_address(CENTRE_LIST_ADDR_BITWIDTH-1 downto INDEX_BITWIDTH) <= std_logic_vector(rd_centre_list_address_reg);
tmp_rd_centre_list_address(INDEX_BITWIDTH-1 downto 0) <= std_logic_vector(rd_counter);
tmp_wr_centre_list_address(CENTRE_LIST_ADDR_BITWIDTH-1 downto INDEX_BITWIDTH) <= std_logic_vector(wr_centre_list_address_reg);
tmp_wr_centre_list_address(INDEX_BITWIDTH-1 downto 0) <= std_logic_vector(wr_counter);
tmp_centre_in <= std_logic_vector(wr_centre_list_data_reg);
wr_centre_list_wea <= wr_cent_reg AND NOT(virtual_write_address_reg);
centre_index_memory_top_inst : centre_index_memory_top
port map (
clk => clk,
sclr => sclr,
rd => reading_centres,
wea(0) => wr_centre_list_wea,
addra => tmp_wr_centre_list_address,
dina => tmp_centre_in,
addrb => tmp_rd_centre_list_address,
doutb => tmp_centre_out,
item_read_twice => tmp_item_read_twice,
item_address => tmp_item_address
);
tmp_rd_node_address <= std_logic_vector(rd_node_address_reg);
tmp_wr_node_address <= std_logic_vector(wr_node_address_reg);
tmp_wr_node_data_in <= nodedata_2_stdlogic(wr_node_data_reg);
node_memory_top_inst : node_memory_top
port map(
clka => clk,
wea(0) => wr_node_reg,
addra => tmp_wr_node_address,
dina => tmp_wr_node_data_in,
clkb => clk,
addrb => tmp_rd_node_address,
doutb => tmp_rd_node_data_out
);
reading_centres <= '1' WHEN rd_state = reading_centre_list ELSE '0';
dely_line_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
delay_line <= (others => '0');
else
delay_line(0) <= reading_centres;
delay_line(1 to MEM_LAT+MEM_POS_LAT+1-1) <= delay_line(0 to MEM_LAT+MEM_POS_LAT+1-2);
centre_out_delay_line(0) <= unsigned(tmp_centre_out);
centre_out_delay_line(1 to MEM_POS_LAT-1) <= centre_out_delay_line(0 to MEM_POS_LAT-2);
node_data_delay(0) <= stdlogic_2_nodedata(tmp_rd_node_data_out);
node_data_delay(1 to MEM_POS_LAT-1) <= node_data_delay(0 to MEM_POS_LAT-2);
item_read_twice_delay_line(0) <= tmp_item_read_twice;
item_read_twice_delay_line(1 to MEM_POS_LAT-1) <= item_read_twice_delay_line(0 to MEM_POS_LAT-2);
centre_list_address_delay(0) <= tmp_item_address;
centre_list_address_delay(1 to MEM_POS_LAT-1) <= centre_list_address_delay(0 to MEM_POS_LAT-2);
end if;
end if;
end process dely_line_proc;
tmp_wr_centre_list_pos_data_init <= datapoint_2_stdlogic(wr_centre_list_pos_data_init);
centre_positions_memory_inst : centre_positions_memory
port map (
clka => clk,
wea(0) => wr_init_pos,
addra => std_logic_vector(wr_centre_list_pos_address_init),
dina => tmp_wr_centre_list_pos_data_init,
clkb => clk,
addrb => tmp_centre_out,
doutb => tmp_centre_pos_out
);
valid <= delay_line(MEM_LAT+MEM_POS_LAT-1);
rd_centre_list_data <= centre_out_delay_line(MEM_POS_LAT-1);
rd_node_data <= node_data_delay(MEM_POS_LAT-1);
rd_centre_list_pos_data <= stdlogic_2_datapoint(tmp_centre_pos_out);
last_centre <= delay_line(MEM_LAT+MEM_POS_LAT-1) AND NOT(delay_line(MEM_LAT+MEM_POS_LAT-2));
item_read_twice <= item_read_twice_delay_line(MEM_POS_LAT-1);
rd_centre_list_address_out <= centre_list_address_delay(MEM_POS_LAT-1);
end Behavioral;
| bsd-3-clause | 8e6f701fa416deeb941f514388c2bc5a | 0.571046 | 3.570623 | false | false | false | false |
mithro/HDMI2USB | hdl/usb/cdc_out.vhd | 3 | 3,325 | -- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity cdc_out is
port
(
-- in signals
fdata : in std_logic_vector(7 downto 0);
flag_empty : in std_logic;
faddr : in std_logic_vector(1 downto 0);
cdcout : in std_logic_vector(1 downto 0);
-- out signals
slrd : out std_logic;
cmd : out std_logic_vector(7 downto 0);
cmd_en : out std_logic;
cdc_out_free: out std_logic;
-- ifclk,rst
rst : in std_logic;
ifclk : in std_logic
);
end entity cdc_out;
architecture rtl of cdc_out is
type states is (s_wait_for_cdc,s_reset,s_read_data,s_free_cdc,s_skip);
signal ps : states;
begin -- architecture
process(ifclk,rst)
begin
if rst = '1' then
slrd <= '1';
cmd <= (others => '0');
cmd_en <= '0';
cdc_out_free <= '1';
ps <= s_reset;
elsif falling_edge(ifclk) then
slrd <= '1';
cmd <= (others => '0');
cmd_en <= '0';
case ps is
when s_reset =>
slrd <= '1';
cmd <= (others => '0');
cmd_en <= '0';
cdc_out_free <= '1';
ps <= s_wait_for_cdc;
when s_wait_for_cdc =>
if faddr = cdcout then
ps <= s_read_data;
cdc_out_free <= '0';
end if;
when s_read_data =>
ps <= s_free_cdc;
if flag_empty = '1' then -- some data in fifo
slrd <= '0';
cmd_en <= '1';
cmd <= fdata;
end if;
when s_free_cdc =>
ps <= s_skip;
cdc_out_free <= '1';
when s_skip =>
ps <= s_wait_for_cdc;
when others =>
ps <= s_reset;
end case;
end if;
end process;
end architecture;
| bsd-2-clause | e293934b52c5fe555e6906c119accb93 | 0.602707 | 3.259804 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/bytefifo/example_design/bytefifo_exdes.vhd | 3 | 5,869 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifo_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity bytefifo_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
UNDERFLOW : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end bytefifo_exdes;
architecture xilinx of bytefifo_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component bytefifo is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
UNDERFLOW : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : bytefifo
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
OVERFLOW => overflow,
UNDERFLOW => underflow,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| bsd-2-clause | 13fbc6d380cbc91601e6515db06410bc | 0.499063 | 4.948567 | false | false | false | false |
freecores/gpib_controller | vhdl/src/wrapper/SecAddrReg.vhd | 1 | 1,721 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: SecAddrReg
-- Date:2011-11-09
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SecAddrReg is
port (
reset : in std_logic;
strobe : in std_logic;
data_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
-- gpib
secAddrMask : out std_logic_vector (15 downto 0)
);
end SecAddrReg;
architecture arch of SecAddrReg is
signal inner_buf : std_logic_vector (15 downto 0);
begin
data_out <= inner_buf;
secAddrMask <= inner_buf;
process (reset, strobe) begin
if reset = '1' then
inner_buf <= "0000000000000000";
elsif rising_edge(strobe) then
inner_buf <= data_in;
end if;
end process;
end arch;
| gpl-3.0 | 5419fa625015a0c567b901ddace385ab | 0.616502 | 3.974596 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib_helper/MemoryBlock_by_logic.vhd | 1 | 2,416 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: MemoryBlock
-- Date:2011-11-14
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.vcomponents.all;
use work.utilPkg.all;
use work.helperComponents.all;
entity MemoryBlock is
port (
reset : in std_logic;
clk : in std_logic;
-------------------------------------------------
p1_addr : in std_logic_vector(10 downto 0);
p1_data_in : in std_logic_vector(7 downto 0);
p1_strobe : in std_logic;
p1_data_out : out std_logic_vector(7 downto 0);
-------------------------------------------------
p2_addr : in std_logic_vector(10 downto 0);
p2_data_in : in std_logic_vector(7 downto 0);
p2_strobe : in std_logic;
p2_data_out : out std_logic_vector(7 downto 0)
);
end MemoryBlock;
architecture arch of MemoryBlock is
type mem is array(0 to 31) of std_logic_vector(7 downto 0);
signal memory : mem;
signal addrP1, addrP2 : integer range 0 to 31;
begin
addrP1 <= conv_integer(UNSIGNED(p1_addr));
addrP2 <= conv_integer(UNSIGNED(p2_addr));
process(reset, clk) begin
if reset = '1' then
elsif rising_edge(clk) then
p1_data_out <= memory(addrP1);
p2_data_out <= memory(addrP2);
if p1_strobe = '1' then
memory(addrP1) <= p1_data_in;
end if;
if p2_strobe = '1' then
memory(addrP2) <= p2_data_in;
end if;
end if;
end process;
end arch;
| gpl-3.0 | 1e482cbc4ee9ddd1dd770431b49972b5 | 0.600579 | 3.521866 | false | false | false | false |
tomoasleep/vhdl_test_script | templetes/util.vhd | 1 | 6,342 |
-- This is from http://www.eda-stds.org/vhdl-200x/vhdl-200x-ft/packages_old/
library ieee;
use ieee.std_logic_1164.all;
package vhdl_test_script_utils is
function to_string (value : STD_ULOGIC) return STRING;
function to_string (value : STD_ULOGIC_VECTOR) return STRING;
function to_string (value : STD_LOGIC_VECTOR) return STRING;
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BSTRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_LOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
function TO_HSTRING (VALUE : STD_LOGIC) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_LOGIC_VECTOR return STRING];
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING
end package vhdl_test_script_utils;
package body vhdl_test_script_utils is
-----------------------------------------------------------------------------
-- New string functions for vhdl-200x fast track
-----------------------------------------------------------------------------
function to_string (value : STD_ULOGIC) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := MVL9_to_char (value);
return result;
end function to_string;
-------------------------------------------------------------------
-- TO_STRING (an alias called "to_bstring" is provide)
-------------------------------------------------------------------
function to_string (value : STD_ULOGIC_VECTOR) return STRING is
alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
end function to_string;
-------------------------------------------------------------------
-- TO_HSTRING
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
function to_hstring (value : STD_LOGIC) return STRING is
variable vector_value : std_ulogic_vector(0 downto 0);
variable result : STRING(1 to 1);
begin
vector_value(0) := value;
result := to_hstring(vector_value);
return result;
end function to_hstring;
-------------------------------------------------------------------
-- TO_OSTRING
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_string (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_string (to_stdulogicvector (value));
end function to_string;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_ostring (to_stdulogicvector (value));
end function to_ostring;
end package body vhdl_test_script_utils;
| mit | 7323be3bacd0324b62fc28b7bd3ece61 | 0.536582 | 3.521377 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-2/memory.vhd | 1 | 3,277 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory is
port(
address, writeData : in std_logic_vector(31 downto 0);
clk, memRead, memWrite : in std_logic;
memData : out std_logic_vector(31 downto 0)
);
end memory;
architecture behav of memory is
type ram is array (65536 downto 0) of std_logic_vector(7 downto 0);
signal inByte0, inByte1, inByte2, inByte3, outByte0, outByte1, outByte2, outByte3 : std_logic_vector(7 downto 0);
signal writeDataBuf : std_logic_vector(31 downto 0);
signal mem : ram;
signal addr : integer range 0 to 65536;
begin
inByte0(0) <= writeData(0);
inByte0(1) <= writeData(1);
inByte0(2) <= writeData(2);
inByte0(3) <= writeData(3);
inByte0(4) <= writeData(4);
inByte0(5) <= writeData(5);
inByte0(6) <= writeData(6);
inByte0(7) <= writeData(7);
inByte1(0) <= writeData(8);
inByte1(1) <= writeData(9);
inByte1(2) <= writeData(10);
inByte1(3) <= writeData(11);
inByte1(4) <= writeData(12);
inByte1(5) <= writeData(13);
inByte1(6) <= writeData(14);
inByte1(7) <= writeData(15);
inByte2(0) <= writeData(16);
inByte2(1) <= writeData(17);
inByte2(2) <= writeData(18);
inByte2(3) <= writeData(19);
inByte2(4) <= writeData(20);
inByte2(5) <= writeData(21);
inByte2(6) <= writeData(22);
inByte2(7) <= writeData(23);
inByte3(0) <= writeData(24);
inByte3(1) <= writeData(25);
inByte3(2) <= writeData(26);
inByte3(3) <= writeData(27);
inByte3(4) <= writeData(28);
inByte3(5) <= writeData(29);
inByte3(6) <= writeData(30);
inByte3(7) <= writeData(31);
outByte0 <= mem(addr);
outByte1 <= mem(addr+1);
outByte2 <= mem(addr+2);
outByte3 <= mem(addr+3);
writeDataBuf(0) <= outByte0(0);
writeDataBuf(1) <= outByte0(1);
writeDataBuf(2) <= outByte0(2);
writeDataBuf(3) <= outByte0(3);
writeDataBuf(4) <= outByte0(4);
writeDataBuf(5) <= outByte0(5);
writeDataBuf(6) <= outByte0(6);
writeDataBuf(7) <= outByte0(7);
writeDataBuf(8) <= outByte1(0);
writeDataBuf(9) <= outByte1(1);
writeDataBuf(10) <= outByte1(2);
writeDataBuf(11) <= outByte1(3);
writeDataBuf(12) <= outByte1(4);
writeDataBuf(13) <= outByte1(5);
writeDataBuf(14) <= outByte1(6);
writeDataBuf(15) <= outByte1(7);
writeDataBuf(16) <= outByte2(0);
writeDataBuf(17) <= outByte2(1);
writeDataBuf(18) <= outByte2(2);
writeDataBuf(19) <= outByte2(3);
writeDataBuf(20) <= outByte2(4);
writeDataBuf(21) <= outByte2(5);
writeDataBuf(22) <= outByte2(6);
writeDataBuf(23) <= outByte2(7);
writeDataBuf(24) <= outByte3(0);
writeDataBuf(25) <= outByte3(1);
writeDataBuf(26) <= outByte3(2);
writeDataBuf(27) <= outByte3(3);
writeDataBuf(28) <= outByte3(4);
writeDataBuf(29) <= outByte3(5);
writeDataBuf(30) <= outByte3(6);
writeDataBuf(31) <= outByte3(7);
process(address, writeData, clk, memRead, memWrite)
begin
addr <= to_integer(unsigned(address));
if rising_edge(clk) then
if (memWrite='1') and (memRead='0') then
mem(addr)<=inByte0;
mem(addr+1)<=inByte1;
mem(addr+2)<=inByte2;
mem(addr+3)<=inByte3;
end if;
end if;
if falling_edge(clk) then
if (memWrite='0') and (memRead='1') then
memData<=writeDataBuf;
end if;
end if;
end process;
end behav;
| gpl-3.0 | 789d274f1b9ba55ad64e5361dc0b9623 | 0.641745 | 2.810463 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/node_memory_top.vhd | 1 | 8,454 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: node_memory_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity node_memory_top is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
dina : in std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0);
clkb : in std_logic;
addrb : in std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
doutb : out std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0)
);
end node_memory_top;
architecture Behavioral of node_memory_top is
constant MEM_LAT : integer := 2;
constant ADDR_BITWIDTH : integer := NODE_POINTER_BITWIDTH-1;
type addr_delay_type is array(0 to MEM_LAT-1) of std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
component leaf_node_memory
port (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(ADDR_BITWIDTH-1 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(D*COORD_BITWIDTH_EXT+COORD_BITWIDTH_EXT-1 downto 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(ADDR_BITWIDTH-1 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(D*COORD_BITWIDTH_EXT+COORD_BITWIDTH_EXT-1 downto 0)
);
end component;
component int_node_memory
port (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(ADDR_BITWIDTH-1 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(ADDR_BITWIDTH-1 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 DOWNTO 0)
);
end component;
signal tmp_addra : std_logic_vector(ADDR_BITWIDTH-1 downto 0);
signal tmp_addrb : std_logic_vector(ADDR_BITWIDTH-1 downto 0);
signal din_leaf_mem : std_logic_vector(D*COORD_BITWIDTH_EXT+COORD_BITWIDTH_EXT-1 downto 0);
signal dout_leaf_mem : std_logic_vector(D*COORD_BITWIDTH_EXT+COORD_BITWIDTH_EXT-1 downto 0);
signal dout_leaf_mem_ext : std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0);
signal din_int_mem : std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0);
signal dout_int_mem : std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0);
signal wea_leaf_mem : std_logic;
signal wea_int_mem : std_logic;
signal addr_delay_line : addr_delay_type;
begin
wea_leaf_mem <= wea(0) AND addra(NODE_POINTER_BITWIDTH-1);
wea_int_mem <= wea(0) AND NOT(addra(NODE_POINTER_BITWIDTH-1));
tmp_addra <= addra(ADDR_BITWIDTH-1 downto 0);
tmp_addrb <= addrb(ADDR_BITWIDTH-1 downto 0);
-- this must be in sync with function nodedata_2_stdlogic!!
G0 : for I in 0 to D-1 generate
din_leaf_mem((I+1)*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH_EXT) <= dina((I+1)*COORD_BITWIDTH_EXT+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto I*COORD_BITWIDTH_EXT+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
end generate G0;
din_leaf_mem(D*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH_EXT-1 downto D*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH_EXT) <= dina(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
din_int_mem <= dina;
leaf_node_memory_inst : leaf_node_memory
port map(
clka => clka,
wea(0) => wea_leaf_mem,
addra => tmp_addra,
dina => din_leaf_mem,
clkb => clkb,
addrb => tmp_addrb,
doutb => dout_leaf_mem
);
int_node_memory_inst : int_node_memory
port map(
clka => clka,
wea(0) => wea_int_mem,
addra => tmp_addra,
dina => din_int_mem,
clkb => clkb,
addrb => tmp_addrb,
doutb => dout_int_mem
);
addr_delay_line_proc : process(clkb)
begin
if rising_edge(clkb) then
addr_delay_line(0) <= addrb;
addr_delay_line(1 to MEM_LAT-1) <= addr_delay_line(0 to MEM_LAT-2);
end if;
end process addr_delay_line_proc;
-- this must be in sync with function nodedata_2_stdlogic!!
G1 : for I in 0 to D-1 generate
dout_leaf_mem_ext((I+1)*COORD_BITWIDTH_EXT+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto I*COORD_BITWIDTH_EXT+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) <= dout_leaf_mem((I+1)*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH_EXT);
dout_leaf_mem_ext(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) <= (others => '0');
dout_leaf_mem_ext(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+1*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+1*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) <= (others => '0');
dout_leaf_mem_ext(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+2*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+2*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) <= (others => '0');
end generate G1;
dout_leaf_mem_ext(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) <= dout_leaf_mem(D*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH_EXT-1 downto D*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH_EXT);
dout_leaf_mem_ext(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) <= std_logic_vector(to_unsigned(1,COORD_BITWIDTH));
dout_leaf_mem_ext(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+1*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) <= (others => '0');
dout_leaf_mem_ext(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+2*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+1*NODE_POINTER_BITWIDTH) <= (others => '0');
-- output mux
doutb <= dout_leaf_mem_ext WHEN addr_delay_line(MEM_LAT-1)(NODE_POINTER_BITWIDTH-1) = '1' ELSE dout_int_mem;
end Behavioral;
| bsd-3-clause | 4c6b6eedae575884d5e97727ac99f29b | 0.666667 | 3.208349 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib_helper/gpibWriter.vhd | 1 | 4,610 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: gpibWriter
-- Date: 2011-11-01
-- Author: Andrzej Paluch
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.utilPkg.all;
entity gpibWriter is
port (
-- clock
clk : in std_logic;
-- reset
reset : std_logic;
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
-- output data
data_out : out std_logic_vector (7 downto 0);
-- wait for new cycle
wnc : in std_logic;
-- seriall poll active
spa : in std_logic;
-- new byte available
nba : out std_logic;
-- end of string
endOf : out std_logic;
-- talker active
tac : in std_logic;
-- controller write command
cwrc : in std_logic;
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
-- TE is extended
isTE : in std_logic;
-- current secondary address
secAddr : in std_logic_vector (4 downto 0);
-- secondary address of data
dataSecAddr : in std_logic_vector (4 downto 0);
-- buffer consumed
buf_interrupt : out std_logic;
-- indicates end of stream
end_of_stream : in std_logic;
-- resets writer
reset_writer : in std_logic;
-- enables writer
writer_enable : in std_logic;
---------------- fifo ---------------------------
availableFifoBytesCount : in std_logic_vector(10 downto 0);
-- fifo read strobe
fifo_read_strobe : out std_logic;
-- indicates fifo ready to read
fifo_ready_to_read : in std_logic;
-- input data
fifo_data_in : in std_logic_vector (7 downto 0)
);
end gpibWriter;
architecture arch of gpibWriter is
-- writer states
type WRITER_STATE is (
ST_IDLE,
ST_WAIT_WNC_1,
ST_WAIT_WNC_0
);
signal current_state : WRITER_STATE;
-- triggered by spa
signal tr_by_spa : std_logic;
signal readyToSend : boolean;
signal at_least_one_byte_in_fifo : boolean;
begin
buf_interrupt <= to_stdl(not at_least_one_byte_in_fifo);
data_out <= fifo_data_in;
at_least_one_byte_in_fifo <= availableFifoBytesCount /= "000000000000";
readyToSend <=
(
writer_enable = '1'
and
at_least_one_byte_in_fifo
and
(
(
tac='1'
and
(
(isTE='1' and dataSecAddr=secAddr)
or
isTE='0'
)
)
or
cwrc='1'
)
and
fifo_ready_to_read='1'
)
or
spa='1';
process (clk, reset, reset_writer) begin
if reset = '1' or reset_writer = '1' then
nba <= '0';
endOf <= '0';
fifo_read_strobe <= '0';
tr_by_spa <= '0';
current_state <= ST_IDLE;
elsif rising_edge(clk) then
case current_state is
when ST_IDLE =>
if readyToSend then
nba <= '1';
tr_by_spa <= spa;
if availableFifoBytesCount="000000000001" and
end_of_stream='1' and spa='0' and tac='1' and
cwrc='0' then
endOf <= '1';
end if;
current_state <= ST_WAIT_WNC_1;
end if;
when ST_WAIT_WNC_1 =>
if wnc='1' then
nba <= '0';
if tr_by_spa='0' then
endOf <= '0';
fifo_read_strobe <= '1';
end if;
current_state <= ST_WAIT_WNC_0;
end if;
when ST_WAIT_WNC_0 =>
if wnc='0' then
if tr_by_spa='0' then
fifo_read_strobe <= '0';
end if;
current_state <= ST_IDLE;
end if;
when others =>
current_state <= ST_IDLE;
end case;
end if;
end process;
end arch;
| gpl-3.0 | 25456b8bfa6735da6726c3b57a1ebdee | 0.532755 | 3.570875 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/image_selector_fifo/simulation/image_selector_fifo_pctrl.vhd | 3 | 20,488 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: image_selector_fifo_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.image_selector_fifo_pkg.ALL;
ENTITY image_selector_fifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF image_selector_fifo_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL full_d1 : STD_LOGIC := '0';
SIGNAL full_rd_dom1 : STD_LOGIC := '0';
SIGNAL full_rd_dom2 : STD_LOGIC := '0';
SIGNAL af_chk_d1 : STD_LOGIC := '0';
SIGNAL af_chk_rd1 : STD_LOGIC := '0';
SIGNAL af_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & af_chk_rd2 & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (empty_wr_dom2 = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND full_rd_dom2 = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
af_chk_d1 <= '0';
full_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
full_d1 <= FULL;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
af_chk_d1 <= af_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
af_chk_rd1 <= '0';
af_chk_rd2 <= '0';
full_rd_dom1 <= '0';
full_rd_dom2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
af_chk_rd1 <= af_chk_d1;
af_chk_rd2 <= af_chk_rd1;
full_rd_dom1 <= full_d1;
full_rd_dom2 <= full_rd_dom1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:image_selector_fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:image_selector_fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| bsd-2-clause | db9e52f89250a0ef2da6b28a337310d6 | 0.509762 | 3.196256 | false | false | false | false |
UdayanSinha/Code_Blocks | VHDL/Projects/work/frequency_divider_generic.vhd | 1 | 893 | LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
USE IEEE.std_logic_signed.all; --math operations for signed std_logic
ENTITY frequency_divider_generic IS
GENERIC(divide_by: INTEGER);
PORT(clk_in, reset: IN STD_LOGIC;
output: OUT STD_LOGIC);
END frequency_divider_generic;
ARCHITECTURE behave OF frequency_divider_generic IS
SIGNAL count: INTEGER RANGE 0 TO divide_by:=0;
BEGIN
PROCESS(clk_in, reset)
BEGIN
If reset='0' THEN --asynchronous, active low reset
output<='0';
count<=0;
ELSIF rising_edge(clk_in) THEN
count<=count+1;
IF (count=divide_by-1) THEN
output<='1';
count<=0;
ELSE
output<='0';
END IF;
END IF;
END PROCESS;
END behave; | mit | 265c9c13d32b6b0b3cf166c6f3f820ce | 0.669653 | 3.600806 | false | false | false | false |
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