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boztalay/OldProjects | FPGA/Sync_Mem/four_dig_7seg.vhd | 3 | 3,099 | ----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--
--Module Title: 4dig_7seg
--Module Description:
-- This is a 4-digit, 7-segment display decoder. It outputs in 16-bit values
-- on the Digilent Nexys 2 board's 4-digit display in hexadecimal. Simply
-- give it a 50 MHz clock and data and it'll start working.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity four_dig_7seg is
Port ( clock : in STD_LOGIC;
display_data : in STD_LOGIC_VECTOR (15 downto 0);
anodes : out STD_LOGIC_VECTOR (3 downto 0);
to_display : out STD_LOGIC_VECTOR (6 downto 0));
end four_dig_7seg;
architecture Behavioral of four_dig_7seg is
--//Signals\\--
signal to_decoder : STD_LOGIC_VECTOR(3 downto 0);
--\\Signals//--
begin
--This process takes the data to display and
--multiplexes 4-bit chunks of it according
--to the input clock. The 4-bit chunks are
--sent to the decoder and the anode lines
--are switched to activate one digit at a time
disp_data: process(display_data, clock) is
variable clk_count : integer := 0; --A variable to count the clock ticks
variable disp_count : integer := 0; --A variable to hold on to which digit
begin --is currently being displayed
if rising_edge(clock) then
clk_count := clk_count + 1;
if clk_count = 100000 then --Refresh rate with 100000 is about 125 Hz for the entire display
disp_count := disp_count + 1;
clk_count := 0;
if disp_count = 4 then
disp_count := 0;
end if;
end if;
end if;
if disp_count = 0 then --First digit
anodes <= "1110";
to_decoder <= display_data(3 downto 0);
elsif disp_count = 1 then --Second digit
anodes <= "1101";
to_decoder <= display_data(7 downto 4);
elsif disp_count = 2 then --Third digit
anodes <= "1011";
to_decoder <= display_data(11 downto 8);
elsif disp_count = 3 then --Fourth digit
anodes <= "0111";
to_decoder <= display_data(15 downto 12);
end if;
end process;
--This represents a ROM that will act as the
--individual 7-segment decoder for each digit
--of the display
with to_decoder select
to_display <= "0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",
"0001000" when "1010",
"1100000" when "1011",
"0110001" when "1100",
"1000010" when "1101",
"0110000" when "1110",
"0111000" when "1111",
"0000001" when others;
end Behavioral;
| mit | 7e3759c2f74bd74413de1f8ddd3b4215 | 0.594063 | 3.680523 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/zigzag.vhd | 2 | 1,095 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity zigzag is
generic(
sample_width : integer := 8
);
port(
x : in std_logic_vector((16*sample_width)-1 downto 0);
y : out std_logic_vector((16*sample_width)-1 downto 0)
);
end entity zigzag;
architecture rtl of zigzag is
type block_type is array(15 downto 0) of integer;
constant order : block_type := (0,1,4,8,5,2,3,6,9,12,13,10,7,11,14,15);
begin
g0: for i in 15 downto 0 generate
constant zigzag_i : integer := order(15-i);
constant pre_lower_index : integer := i * sample_width;
constant pre_upper_index : integer := pre_lower_index + sample_width - 1;
constant post_lower_index : integer := zigzag_i * sample_width;
constant post_upper_index : integer := post_lower_index + sample_width - 1;
begin
y(post_upper_index downto post_lower_index) <=
x(pre_upper_index downto pre_lower_index);
end generate;
end architecture rtl; | mit | cedf555dee36f73cfa2c22cfffa907e3 | 0.632877 | 3.308157 | false | false | false | false |
boztalay/OldProjects | FPGA/testytest/fifo.vhd | 1 | 2,741 | --------------------------------------------------------------------------------
--
-- Design unit generated by Aldec IP Core Generator, version 8.2.
-- Copyright (c) 1997 - 2009 by Aldec, Inc. All rights reserved.
--
--------------------------------------------------------------------------------
--
-- Created on Saturday 2010-08-14, 17:08:02
--
--------------------------------------------------------------------------------
-- Details:
-- Type: First In - First Out (FIFO) Memory
-- Data width: 16
-- Depth: 16
-- Clock input CLK active high
-- Synchronous Clear input CLR active high
-- Read input RD active high
-- Write input WR active high
-- Empty flag output EMPTY active high
-- Full flag output FULL active high
--------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {fifo} architecture {fifo_arch}}
library IEEE;
use IEEE.std_logic_1164.all;
entity fifo is
port(
CLR : in std_logic;
CLK : in std_logic;
RD : in std_logic;
WR : in std_logic;
DATA : in std_logic_vector(15 downto 0);
EMPTY : out std_logic;
FULL : out std_logic;
Q : out std_logic_vector(15 downto 0)
);
end entity;
--}} End of automatically maintained section
library IEEE;
use IEEE.std_logic_unsigned.all;
architecture fifo_arch of fifo is
type fifo_array_type is array (15 downto 0) of std_logic_vector(15 downto 0);
signal fifo_array : fifo_array_type;
signal WR_PTR : INTEGER range 0 to 15;
signal RD_PTR : INTEGER range 0 to 15;
begin
process (CLK)
begin
if rising_edge(CLK) then
if CLR = '1' then
for INDEX in 15 downto 0 loop
fifo_array(INDEX) <= (others => '0');
end loop;
elsif WR = '1' then
fifo_array(WR_PTR) <= DATA;
end if;
end if;
end process;
process (CLK)
variable PTR : INTEGER range 0 to 16;
begin
if rising_edge(CLK) then
if CLR = '1' then
WR_PTR <= 0;
RD_PTR <= 0;
EMPTY <= '1';
FULL <= '0';
PTR := 0;
elsif WR = '1' and PTR < 16 then
if WR_PTR < 15 then
WR_PTR <= WR_PTR + 1;
elsif WR_PTR = 15 then
WR_PTR <= 0;
end if;
PTR := PTR + 1;
elsif RD = '1' and PTR > 0 then
if RD_PTR<15 then
RD_PTR <= RD_PTR + 1;
elsif RD_PTR = 15 then
RD_PTR <= 0;
end if;
PTR := PTR - 1;
end if;
if PTR = 0 then
EMPTY <= '1';
else
EMPTY <= '0';
end if;
if PTR = 16 then
FULL<= '1';
else
FULL <= '0';
end if;
end if;
end process;
Q <= fifo_array(RD_PTR) when RD = '1' else (others => 'Z');
end architecture;
| mit | fbff6fed759da27b300308c4f05a62c2 | 0.512587 | 3.278708 | false | false | false | false |
pyrohaz/SSD1306_VHDLImplementation | ROM.vhd | 1 | 5,571 | -- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY ROM IS
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ROM;
ARCHITECTURE SYN OF rom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "ROM.mif",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1024,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 10,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "ROM.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "ROM.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| mit | d388d16b6c494d1ed552e95229519857 | 0.670257 | 3.718959 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/bd/week1/ip/week1_audio_mixer_0_0/synth/week1_audio_mixer_0_0.vhd | 1 | 4,346 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: tsotnep:userLibrary:audio_mixer:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY week1_audio_mixer_0_0 IS
PORT (
audio_mixed_a_b_left_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_mixed_a_b_right_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_channel_a_left_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_channel_a_right_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_channel_b_left_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_channel_b_right_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END week1_audio_mixer_0_0;
ARCHITECTURE week1_audio_mixer_0_0_arch OF week1_audio_mixer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF week1_audio_mixer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT top_level IS
GENERIC (
size : INTEGER
);
PORT (
audio_mixed_a_b_left_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_mixed_a_b_right_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_channel_a_left_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_channel_a_right_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_channel_b_left_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_channel_b_right_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT top_level;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF week1_audio_mixer_0_0_arch: ARCHITECTURE IS "top_level,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF week1_audio_mixer_0_0_arch : ARCHITECTURE IS "week1_audio_mixer_0_0,top_level,{}";
BEGIN
U0 : top_level
GENERIC MAP (
size => 24
)
PORT MAP (
audio_mixed_a_b_left_out => audio_mixed_a_b_left_out,
audio_mixed_a_b_right_out => audio_mixed_a_b_right_out,
audio_channel_a_left_in => audio_channel_a_left_in,
audio_channel_a_right_in => audio_channel_a_right_in,
audio_channel_b_left_in => audio_channel_b_left_in,
audio_channel_b_right_in => audio_channel_b_right_in
);
END week1_audio_mixer_0_0_arch;
| lgpl-3.0 | 0f1179fd20e53c5fedf70ac7ee189640 | 0.724114 | 3.633779 | false | false | false | false |
DaveyPocket/btrace448 | core/vga/rectangular_device.vhd | 1 | 1,244 | -- Btrace 448
-- Rectangular Device - Draws Rectangles
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pongpack.all;
entity rectangular_device is
port(addr_x, addr_y: in std_logic_vector(9 downto 0);
px1, py1, px2, py2: in std_logic_vector(9 downto 0);
dev_on: out std_logic;
color: color_t;
rgb: out std_logic_vector(2 downto 0));
end rectangular_device;
architecture arch of rectangular_device is
signal ipx1, ipy1, ipx2, ipy2: integer;
signal ia_x, ia_y: integer;
signal inx, iny: std_logic;
begin
ipx1 <= to_integer(unsigned(px1));
ipy1 <= to_integer(unsigned(py1));
ipx2 <= to_integer(unsigned(px2));
ipy2 <= to_integer(unsigned(py2));
ia_x <= to_integer(unsigned(addr_x));
ia_y <= to_integer(unsigned(addr_y));
inx <= '1' when (ia_x >= ipx1) and (ipx2 >= ia_x) else '0';
iny <= '1' when (ia_y >= ipy1) and (ipy2 >= ia_y) else '0';
with color select
rgb <= "000" when black,
"100" when red,
"010" when green,
"110" when yellow,
"001" when blue,
"101" when magenta,
"011" when cyan,
"111" when others;
dev_on <= inx and iny;
end arch;
| gpl-3.0 | 58f589767df2a635367e2086a94a391c | 0.607717 | 2.764444 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia_save/initiateur.vhd | 1 | 8,691 | -- ########################################################################
-- $Software: busiac
-- $section : hardware component
-- $Id: initiateur.vhd 327 2015-06-03 19:18:19Z ia $
-- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/initiateur.vhd $
-- $Author : Ivan Auge (Email: [email protected])
-- ########################################################################
--
-- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge.
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- BUSIAC software is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY ; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-- Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with the GNU C Library; see the file COPYING. If not, write to the Free
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
-- ######################################################################*/
-------------------------------------------------------------------------------
-- Ce module transfert tous les messages venant de busin sur busout.
-- De plus, ce module récupère 4 octets B3,B2,B1,B0 1 par 1 sur RS232in et
-- les regroupe pour réaliser un message (0000,addrsrc,addrdest,data)
-- (voir bus.txt) qu'il transfert sur busout.
-- B0 est le premier octet reçu, B3 est le dernier octet reçu.
--
-- addrsrc = 11111111 (255)
-- addrdest = B3
-- data = B2<<16 | B1<<8 | B0
--
-- Du coté busin, il suit le protocole "poignée de main" (signaux: busin,
-- busin_valid, busin_eated).
-- Du coté busout, il suit le protocole "poignée de main" (signaux: busout,
-- busout_valid, busout_eated).
-- Du coté RS232in, il suit le protocole du module RS232in (signaux: Data, Ndata).
--
-- Attention:
-- - il n'y a pas de contrôle de flux du cote RS232in, donc si des données
-- arrive sur Data et que le bus est bloqué, elles seront perdues.
-- - ce module assume que Data reste stable au moins 3 cycles après la pulse Ndata
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY initiateur IS
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
-- interface busin
busin : in STD_LOGIC_VECTOR(43 DOWNTO 0);
busin_valid : in STD_LOGIC;
busin_eated : out STD_LOGIC;
-- interface busout
busout : OUT STD_LOGIC_VECTOR(43 DOWNTO 0);
busout_valid : OUT STD_LOGIC;
busout_eated : IN STD_LOGIC;
-- interface vers rs232out
Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Ndata : IN STD_LOGIC);
END initiateur;
ARCHITECTURE Montage OF initiateur IS
-- compteur donnant le nombre d'octets a mettre dans R_32
TYPE T_CMD_i IS (NOOP, COUNT, INIT);
SIGNAL CMD_i : T_CMD_i ;
SIGNAL R_i : INTEGER RANGE 0 TO 4;
SIGNAL VT_endLoop: STD_LOGIC;
-- accumule les octets venant de Data.
TYPE T_CMD_32 IS (NOOP, SHIFT);
SIGNAL CMD_32 : T_CMD_32 ;
SIGNAL R_32 : STD_LOGIC_VECTOR (31 DOWNTO 0);
-- Registre de transfert entre busin et busout
TYPE T_CMD_tft IS (INIT, NOOP);
SIGNAL CMD_tft : T_CMD_tft ;
SIGNAL R_tft : STD_LOGIC_VECTOR (43 DOWNTO 0);
-- Sauve une pulse de Ndata qd on est dans les etats de la FSM
-- qui ne teste pas Ndata
TYPE T_CMD_pulse IS (CLEAR, LOAD);
SIGNAL CMD_pulse : T_CMD_pulse ;
SIGNAL R_pulse : STD_LOGIC;
SIGNAL R_data : STD_LOGIC_VECTOR(7 DOWNTO 0);
-- les sources d'ecriture sur busout
SIGNAL busout_rs232 : STD_LOGIC_VECTOR(43 DOWNTO 0);
SIGNAL busout_tft : STD_LOGIC_VECTOR(43 DOWNTO 0);
--Description des �tats
TYPE STATE_TYPE IS (
ST_INIT,ST_WAIT_BUSIN_OR_NDATA,
ST_BUSIN_AND_NDATA_LOADED,
ST_NDATA_LOADED, ST_BUSIN_LOADED,
ST_EndLoop, ST_NDATA_WRITE);
SIGNAL state : STATE_TYPE;
BEGIN
-------------------------------------------------------------------------------
-- Partie Op�rative
-------------------------------------------------------------------------------
PROCESS (clk)
BEGIN IF clk'EVENT AND clk = '1' THEN
-- R_i
if ( CMD_i = INIT ) then
R_i <= 4 ;
elsif ( CMD_i = COUNT ) then
R_i <= R_i - 1;
else
R_i <= R_i;
end if;
-- R_32
if ( CMD_32 = SHIFT ) then
R_32(31 DOWNTO 24) <= R_data;
R_32(23 DOWNTO 16) <= R_32(31 DOWNTO 24);
R_32(15 DOWNTO 8) <= R_32(23 DOWNTO 16);
R_32( 7 DOWNTO 0) <= R_32(15 DOWNTO 8);
else
R_32 <= R_32 ;
end if;
-- R_tft
if ( CMD_tft = INIT ) then
R_tft <= busin ;
else
R_tft <= R_tft ;
end if;
-- R_pulse
if ( CMD_pulse = LOAD ) then
R_pulse <= R_pulse OR Ndata ;
else -- CLEAR
R_pulse <= '0' ;
end if;
-- R_data
if (Ndata = '1') then
R_data <= data;
else
R_data <= R_data;
end if;
END IF; END PROCESS;
VT_endLoop <= '1' when R_i=0 else '0' ;
busout_rs232(43 DOWNTO 40) <= "0000";
busout_rs232(39 DOWNTO 32) <= "11111111";
busout_rs232(31 DOWNTO 0) <= R_32;
busout_tft <= R_tft;
-------------------------------------------------------------------------------
-- Partie Contr�le
-------------------------------------------------------------------------------
-- Inputs: busout_eated Ndata R_pulse VT_endLoop busin_valid
-- Outputs: busout_valid CMD_i CMD_32 busin_eated CMD_tft CMD_pulse busout
-------------------------------------------------------------------------------
-- fonction de transitition
PROCESS (reset,clk)
BEGIN
if reset = '1' then
state <= ST_INIT;
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN ST_INIT =>
state <= ST_WAIT_BUSIN_OR_NDATA;
WHEN ST_WAIT_BUSIN_OR_NDATA =>
IF busin_valid = '1' AND R_pulse = '1' THEN
state <= ST_BUSIN_AND_NDATA_LOADED;
ELSIF R_pulse = '1' THEN
state <= ST_NDATA_LOADED;
ELSIF busin_valid = '1' THEN
state <= ST_BUSIN_LOADED;
END IF;
WHEN ST_BUSIN_LOADED =>
if busout_eated = '1' then
state <= ST_WAIT_BUSIN_OR_NDATA;
END IF;
WHEN ST_BUSIN_AND_NDATA_LOADED =>
if busout_eated = '1' then
state <= ST_NDATA_LOADED;
END IF;
WHEN ST_NDATA_LOADED =>
state <= ST_EndLoop;
WHEN ST_EndLoop =>
IF VT_EndLoop = '1' THEN
state <= ST_NDATA_WRITE;
else
state <= ST_WAIT_BUSIN_OR_NDATA;
END IF;
WHEN ST_NDATA_WRITE =>
if busout_eated = '1' then
state <= ST_WAIT_BUSIN_OR_NDATA;
END IF;
END CASE;
END IF;
END PROCESS;
-- fonction de sortie
WITH state SELECT busout_valid <=
'1' WHEN ST_BUSIN_LOADED,
'1' WHEN ST_NDATA_WRITE,
'0' WHEN OTHERS;
WITH state SELECT CMD_i <=
INIT WHEN ST_INIT,
INIT WHEN ST_NDATA_WRITE,
COUNT WHEN ST_NDATA_LOADED,
NOOP WHEN OTHERS;
WITH state SELECT CMD_32 <=
SHIFT WHEN ST_NDATA_LOADED,
NOOP WHEN OTHERS;
WITH state SELECT busin_eated <=
'1' WHEN ST_WAIT_BUSIN_OR_NDATA,
'0' WHEN OTHERS;
WITH state SELECT CMD_tft <=
INIT WHEN ST_WAIT_BUSIN_OR_NDATA,
NOOP WHEN OTHERS;
WITH state SELECT CMD_pulse <=
CLEAR WHEN ST_NDATA_LOADED,
LOAD WHEN OTHERS;
WITH state SELECT busout <=
busout_rs232 WHEN ST_NDATA_WRITE,
busout_tft WHEN OTHERS;
END Montage;
| gpl-3.0 | b3dec593df304eb160b4419f46502ad9 | 0.495329 | 3.921755 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/intra_prediction_node.vhd | 1 | 20,269 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity intra_prediction_node is
generic (
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
--debugging
s_intra_idle : out std_logic;
s_intra_data_rxd : out std_logic;
s_intra_write_sample : out std_logic;
s_intra_start_pred : out std_logic;
s_intra_start_tx_loop : out std_logic;
s_intra_start_tx_loop_hold : out std_logic;
s_intra_tx : out std_logic;
s_intra_tx_hold : out std_logic;
s_intra_tx_gen_next : out std_logic;
s_intra_dequeue_rx : out std_logic
);
end entity intra_prediction_node;
architecture fsmd of intra_prediction_node is
---------------------------------------------------------------------------
--- Constants -------------------------------------------------------------
---------------------------------------------------------------------------
constant size_of_byte : integer := 8;
--- for parsing cmd byte --------------------------------------------------
constant cmd_start : integer := 0;
constant cmd_bytes : integer := 1;
constant cmd_end : integer := cmd_start + cmd_bytes * size_of_byte - 1;
--- for parsing set samples command ---------------------------------------
constant wr_addr_start : integer := cmd_end + 1;
constant wr_addr_bytes : integer := 1;
constant wr_addr_end : integer := wr_addr_start + wr_addr_bytes * size_of_byte - 1;
constant samples_start : integer := wr_addr_end + 1;
constant samples_bytes : integer := 4;
constant samples_end : integer := samples_start + samples_bytes * size_of_byte - 1;
--- for parsing perform prediction command --------------------------------
constant block_size_start : integer := cmd_end + 1;
constant block_size_bytes : integer := 1;
constant block_size_end : integer := block_size_start + block_size_bytes * size_of_byte - 1;
constant mode_start : integer := block_size_end + 1;
constant mode_bytes : integer := 1;
constant mode_end : integer := mode_start + mode_bytes * size_of_byte - 1;
constant availible_mask_start : integer := mode_end + 1;
constant availible_mask_bytes : integer := 4;
constant availible_mask_end : integer := availible_mask_start + availible_mask_bytes * size_of_byte - 1;
constant identifier_start : integer := availible_mask_end + 1;
constant identifier_bytes : integer := 1;
constant identifier_end : integer := identifier_start + identifier_bytes * size_of_byte - 1;
--- commands
constant cmd_write_sample : std_logic_vector(7 downto 0) := "00000001";
constant cmd_predict : std_logic_vector(7 downto 0) := "00000010";
--- tx constants ----------------------------------------------------------
constant flit_size : integer := data_width;
constant tx_len_16x16 : integer := 32; --todo --(16*16)/(flit_size/size_of_byte);
constant tx_len_8x8 : integer := 16; --todo --(8*8)/(flit_size/size_of_byte);
constant tx_len_4x4 : integer := 8; --todo --todo
constant tx_loop_max_16x16 : integer := tx_len_16x16;--integer( real(tx_len_16x16) / real(flit_size/size_of_byte) + 0.5 );
constant tx_loop_max_8x8 : integer := tx_len_8x8 ;--integer( real(tx_len_8x8 ) / real(flit_size/size_of_byte) + 0.5 );
constant tx_loop_max_4x4 : integer := tx_len_4x4 ;--integer( real(tx_len_4x4 ) / real(flit_size/size_of_byte) + 0.5 );
constant header_pad_size : integer := 0;
constant header_pad : std_logic_vector := std_logic_vector(to_unsigned(0, header_pad_size));
---------------------------------------------------------------------------
--- Components ------------------------------------------------------------
---------------------------------------------------------------------------
component intra_prediction_core is
port(
clk : in std_logic;
rst : in std_logic;
--interface to enable "set samples" command
sample_data : in std_logic_vector(31 downto 0);
sample_write_addr : in unsigned(7 downto 0);
sample_write_enable : in std_logic;
--interface to enable "perform prediction" command
block_size : in unsigned(7 downto 0);
mode : in unsigned(7 downto 0);
row_addr : in unsigned(7 downto 0);
availible_mask : in std_logic_vector(31 downto 0);
row_data : out unsigned(127 downto 0)
);
end component intra_prediction_core;
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
---------------------------------------------------------------------------
-- Types ------------------------------------------------------------------
---------------------------------------------------------------------------
type intra_node_ctrl_states is ( intra_idle,
intra_data_rxd,
intra_write_sample,
intra_start_pred,
intra_start_tx_loop,
intra_start_tx_loop_hold,
intra_tx,
intra_tx_hold,
intra_tx_gen_next,
intra_tx_gen_next_hold,
intra_dequeue_rx );
---------------------------------------------------------------------------
--- Signals ---------------------------------------------------------------
---------------------------------------------------------------------------
signal sample_data : std_logic_vector(31 downto 0);
signal sample_write_addr : unsigned(7 downto 0);
signal sample_write_enable : std_logic;
signal block_size : unsigned(7 downto 0);
signal mode : unsigned(7 downto 0);
signal row_addr : unsigned(7 downto 0);
signal availible_mask : std_logic_vector(31 downto 0);
signal row_data : unsigned(127 downto 0);
signal wr_sample_data : std_logic;
signal wr_sample_write_addr : std_logic;
signal wr_sample_write_enable : std_logic;
signal wr_block_size : std_logic;
signal wr_mode : std_logic;
signal wr_row_addr : std_logic;
signal wr_availible_mask : std_logic;
signal wr_row_data : std_logic;
signal parsed_cmd : std_logic_vector(7 downto 0);
signal parsed_wr_addr : std_logic_vector(7 downto 0);
signal parsed_samples : std_logic_vector(31 downto 0);
signal parsed_block_size : std_logic_vector(7 downto 0);
signal parsed_mode : std_logic_vector(7 downto 0);
signal parsed_availible_mask : std_logic_vector(31 downto 0);
signal parsed_identifier : std_logic_vector(7 downto 0);
signal tx_loop_count_q : unsigned(7 downto 0);
signal tx_loop_count_d : unsigned(7 downto 0);
signal tx_loop_done : std_logic;
signal last_loop : std_logic;
signal send_data_internal : std_logic_vector(flit_size-1 downto 0);
signal intra_state : intra_node_ctrl_states;
signal next_intra_state : intra_node_ctrl_states;
signal selected_vc_encoder : std_logic_vector(vc_sel_width-1 downto 0);
signal row_seg_full : std_logic_vector(127 downto 0);
signal row_seg : std_logic_vector(flit_size-1 downto 0);
signal selected_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal padded_id : std_logic_vector(31 downto 0);
signal padded_block_size : std_logic_vector(31 downto 0);
begin
---------------------------------------------------------------------------
--- Datapath --------------------------------------------------------------
---------------------------------------------------------------------------
--- instantiate the intra prediction core --------------------------------
core0: component intra_prediction_core port map(
clk => clk ,
rst => rst ,
sample_data => sample_data ,
sample_write_addr => sample_write_addr ,
sample_write_enable => sample_write_enable ,
block_size => block_size ,
mode => mode ,
row_addr => row_addr ,
availible_mask => availible_mask ,
row_data => row_data
);
-- instantiate priority_encoder for vc selection
encoded0: component priority_encoder generic map (
encoded_word_size => vc_sel_width
) Port map(
input => data_in_buffer,
output => selected_vc_encoder
);
--- implement data parser -------------------------------------------------
parsed_cmd <= recv_data(cmd_end downto cmd_start );
parsed_wr_addr <= recv_data(wr_addr_end downto wr_addr_start );
parsed_samples <= recv_data(samples_end downto samples_start );
parsed_block_size <= recv_data(block_size_end downto block_size_start );
parsed_mode <= recv_data(mode_end downto mode_start );
parsed_availible_mask <= recv_data(availible_mask_end downto availible_mask_start);
parsed_identifier <= recv_data(identifier_end downto identifier_start);
--- hook up parsed data to intra prediction core --------------------------
sample_data <= parsed_samples;
sample_write_addr <= unsigned(parsed_wr_addr);
block_size <= unsigned(parsed_block_size);
mode <= unsigned(parsed_mode);
availible_mask <= parsed_availible_mask;
--- data path registers ---------------------------------------------------
dp_regs: process(clk, rst) begin
if rst = '1' then
tx_loop_count_q <= (others => '0');
selected_vc_q <= (others => '0');
elsif rising_edge(clk) then
tx_loop_count_q <= tx_loop_count_d;
selected_vc_q <= selected_vc_d;
end if;
end process;
--- tx loop check ---------------------------------------------------------
tx_loop_done <= '0' when tx_loop_count_q < tx_loop_max_16x16 and block_size = to_unsigned(16, 8) else
'0' when tx_loop_count_q < tx_loop_max_8x8 and block_size = to_unsigned(8, 8) else
'0' when tx_loop_count_q < tx_loop_max_4x4 and block_size = to_unsigned(4, 8) else
'1';
last_loop <= '0' when tx_loop_count_q < (tx_loop_max_16x16 - 1) and block_size = to_unsigned(16, 8) else
'0' when tx_loop_count_q < (tx_loop_max_8x8 - 1) and block_size = to_unsigned(8, 8) else
'0' when tx_loop_count_q < (tx_loop_max_4x4 - 1) and block_size = to_unsigned(4, 8) else
'1';
--- row read address generator --------------------------------------------
-- supports 128, 64, and 32 bit flit data feilds
assert flit_size = 128 or flit_size = 64 or flit_size = 32 report "intra_prediction_node: unsupported flit size" severity failure;
row_addr <= tx_loop_count_q when flit_size = 128 else -- tx's full row per flit
shift_right(tx_loop_count_q, 1) when flit_size = 64 else -- tx's half row per flit
shift_right(tx_loop_count_q, 2) when flit_size = 32 else -- tx's quarter row per flit
(others => '0');
--- row segment selection -------------------------------------------------
row_seg_full <= std_logic_vector(row_data) when flit_size = 128 else
std_logic_vector(to_unsigned(0, 64)) & std_logic_vector(row_data(127 downto 64)) when flit_size = 64 and tx_loop_count_q(0) = '0' else
std_logic_vector(to_unsigned(0, 64)) & std_logic_vector(row_data(63 downto 0)) when flit_size = 64 and tx_loop_count_q(0) = '1' else
std_logic_vector(to_unsigned(0, 96)) & std_logic_vector(row_data(127 downto 96)) when flit_size = 32 and tx_loop_count_q(1 downto 0) = "00" else
std_logic_vector(to_unsigned(0, 96)) & std_logic_vector(row_data(95 downto 64)) when flit_size = 32 and tx_loop_count_q(1 downto 0) = "01" else
std_logic_vector(to_unsigned(0, 96)) & std_logic_vector(row_data(63 downto 32)) when flit_size = 32 and tx_loop_count_q(1 downto 0) = "10" else
std_logic_vector(to_unsigned(0, 96)) & std_logic_vector(row_data(31 downto 0) ) when flit_size = 32 and tx_loop_count_q(1 downto 0) = "11" else
(others => '0');
row_seg <= row_seg_full(flit_size-1 downto 0);
--- misc assignments ------------------------------------------------------
select_vc_read <= selected_vc_q;
padded_id <= std_logic_vector(to_unsigned(0, 24)) & parsed_identifier;
padded_block_size <= std_logic_vector(to_unsigned(0, 24)) & parsed_block_size;
---------------------------------------------------------------------------
--- State Machine ---------------------------------------------------------
---------------------------------------------------------------------------
--- FSM State Register ----------------------------------------------------
state_reg: process(clk, rst) begin
if rst = '1' then
intra_state <= intra_idle;
elsif rising_edge(clk) then
intra_state <= next_intra_state;
end if;
end process;
--- FSM Update Logic ------------------------------------------------------
state_update: process(parsed_cmd, intra_state, tx_loop_done) begin
-- default
next_intra_state <= intra_state;
-- wait for new data to arrive
if intra_state = intra_idle and or_reduce(data_in_buffer) = '1' then
next_intra_state <= intra_data_rxd;
end if;
-- write samples to intra_core
if intra_state = intra_data_rxd and parsed_cmd = cmd_write_sample then
next_intra_state <= intra_write_sample;
end if;
if intra_state = intra_write_sample then
next_intra_state <= intra_dequeue_rx;
end if;
-- perform prediction
if intra_state = intra_data_rxd and parsed_cmd = cmd_predict then
next_intra_state <= intra_start_pred;
end if;
if intra_state = intra_start_pred and ready_to_send = '1' then
next_intra_state <= intra_start_tx_loop;
end if;
--transmit result
if intra_state = intra_start_tx_loop then
next_intra_state <= intra_start_tx_loop_hold;
end if;
if intra_state = intra_start_tx_loop_hold and ready_to_send = '1' then
next_intra_state <= intra_tx;
end if;
if intra_state = intra_tx then
next_intra_state <= intra_tx_hold;
end if;
if intra_state = intra_tx_hold and tx_loop_done = '0' then
next_intra_state <= intra_tx_gen_next;
end if;
if intra_state = intra_tx_hold and tx_loop_done = '1' then
next_intra_state <= intra_dequeue_rx;
end if;
if intra_state = intra_tx_gen_next then
next_intra_state <= intra_tx_gen_next_hold;
end if;
if intra_state = intra_tx_gen_next_hold and ready_to_send = '1' then
next_intra_state <= intra_tx;
end if;
if intra_state = intra_dequeue_rx then
next_intra_state <= intra_idle;
end if;
end process;
--- FSM output logic ------------------------------------------------------
sample_write_enable <= '1' when intra_state = intra_write_sample else '0';
tx_loop_count_d <= (others => '0') when intra_state = intra_start_pred else
tx_loop_count_q + to_unsigned(1, 8) when intra_state = intra_tx else
tx_loop_count_q;
send_data <= header_pad & padded_block_size & padded_id when intra_state = intra_start_tx_loop or intra_state = intra_start_tx_loop_hold else
row_seg;
selected_vc_d <= selected_vc_encoder when intra_state = intra_data_rxd else selected_vc_q;
dequeue <= "01" when selected_vc_q = "0" and intra_state = intra_dequeue_rx else
"10" when selected_vc_q = "1" and intra_state = intra_dequeue_rx else
"00";
dest_addr <= std_logic_vector(to_unsigned(7, addr_width));
set_tail_flit <= '1' when last_loop = '1' else '0';
send_flit <= '1' when intra_state = intra_start_tx_loop else
'1' when intra_state = intra_tx else
'0';
--- debug outputs ---------------------------------------------------------
--tx <= '1' when intra_state = intra_start_tx_loop or intra_state = intra_tx else '0';
--rx <= or_reduce(data_in_buffer);
--idle <= '1' when intra_state = intra_idle else '0';
--wr_ing <= '1' when intra_state = intra_write_sample else '0';
--pred_ing <= '1' when intra_state = intra_start_pred or intra_state = intra_tx_gen_next else '0';
s_intra_idle <= '1' when intra_state = intra_idle else '0';
s_intra_data_rxd <= '1' when intra_state = intra_data_rxd else '0';
s_intra_write_sample <= '1' when intra_state = intra_write_sample else '0';
s_intra_start_pred <= '1' when intra_state = intra_start_pred else '0';
s_intra_start_tx_loop <= '1' when intra_state = intra_start_tx_loop else '0';
s_intra_start_tx_loop_hold <= '1' when intra_state = intra_start_tx_loop_hold else '0';
s_intra_tx <= '1' when intra_state = intra_tx else '0';
s_intra_tx_hold <= '1' when intra_state = intra_tx_hold else '0';
s_intra_tx_gen_next <= '1' when intra_state = intra_tx_gen_next else '0';
s_intra_dequeue_rx <= '1' when intra_state = intra_dequeue_rx else '0';
end architecture fsmd; | mit | 2ce69780964a3ed5f04b7b300b9735e2 | 0.493562 | 3.998619 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/tsotnep/volume_pregain_v1_0/75ddc6aa/src/AmplifierFP.vhd | 2 | 2,738 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:27:41 04/17/2015
-- Design Name:
-- Module Name: AmplifierFP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AmplifierFP is
generic ( INTBIT_WIDTH : integer;
FRACBIT_WIDTH : integer);
Port ( CLK : in std_logic;
RESET : in std_logic;
IN_SIG : in signed ((INTBIT_WIDTH - 1) downto 0); --amplifier input signal
IN_COEF : in signed (((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); --amplifying coefficient
OUT_AMP : out signed ((INTBIT_WIDTH - 1) downto 0) := (others => '0'); --amplifier output
OUT_RDY : out std_logic
);
end AmplifierFP;
architecture Behavioral of AmplifierFP is
COMPONENT MultiplierFP
generic ( INTBIT_WIDTH : integer;
FRACBIT_WIDTH : integer);
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
IN_SIG : IN signed((INTBIT_WIDTH - 1) downto 0);
IN_COEF : IN signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0);
OUT_MULT : OUT signed((2*(INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0);
READY : OUT std_logic
);
END COMPONENT;
signal mult_out : signed ((2*(INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0) := (others => '0');
signal AMP_OUT_in, AMP_OUT_out : signed ((INTBIT_WIDTH - 1) downto 0) := (others => '0');
signal mult_ready : std_logic := '0';
begin
Amp_multiplier: MultiplierFP
generic map(
INTBIT_WIDTH => INTBIT_WIDTH,
FRACBIT_WIDTH => FRACBIT_WIDTH
)PORT MAP(
CLK => CLK,
RESET => RESET,
IN_SIG => IN_SIG,
IN_COEF => IN_COEF,
OUT_MULT => mult_out,
READY => mult_ready
);
-- for fixed point
-- AMP_OUT_in <= mult_out(2*BIT_WIDTH - BIT_WIDTH - 1 downto 0);
-- for integers
AMP_OUT_in <= mult_out((2*FRACBIT_WIDTH + INTBIT_WIDTH) - 1 downto (2*FRACBIT_WIDTH ));
seq_proc : process (CLK)
begin
if(CLK'event and CLK = '1')then
-- update the ready signal when new values gets written to the buffer
if (mult_ready = '1') then
AMP_OUT_out <= AMP_OUT_in;
end if;
end if;
end process;
OUT_RDY <= mult_ready;
OUT_AMP <= AMP_OUT_out;
end Behavioral; | lgpl-3.0 | e147e680b990cb6b075744d67c3ef70a | 0.533966 | 3.602632 | false | false | false | false |
boztalay/OldProjects | FPGA/Subsystems/Subsys_LCDDriver/Subsys_LCDDriver.vhd | 1 | 1,812 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 21:48:20 04/12/2009
-- Design Name:
-- Module Name: Subsys_LCDDriver - Behavioral
-- Project Name: LCD Driver
-- Target Devices:
-- Tool versions:
-- Description: A reusable LCD driver
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Subsys_LCDDriver is
Port ( CLK : in STD_LOGIC;
RS : in STD_LOGIC;
RW : in STD_LOGIC;
CLR : in STD_LOGIC;
RH : in STD_LOGIC;
SC : in STD_LOGIC;
datai : in STD_LOGIC_VECTOR (7 downto 0);
Eo : out STD_LOGIC;
RSo : out STD_LOGIC;
RWo : out STD_LOGIC;
datao : out STD_LOGIC_VECTOR (7 downto 0));
end Subsys_LCDDriver;
architecture Behavioral of Subsys_LCDDriver is
begin
main : process (CLK, RS, RW, CLR, RH, SC, datai)
variable data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
variable RSv, RWv : STD_LOGIC := '0';
begin
RSv := RS;
RWv := RW;
data := datai;
if (CLR = '1') then
RSv := '0';
RWv := '0';
data := "00000001";
end if;
if (RH = '1') then
RSv := '0';
RWv := '0';
data := "00000010";
end if;
if (SC = '1') then
RSv := '0';
RWv := '0';
data := "00010100";
end if;
Eo <= CLK;
RSo <= RSv;
RWo <= RWv;
datao <= data;
end process;
end Behavioral;
| mit | 02483e32b2bb8c5b5dd6b1cca89ceb2f | 0.532009 | 3.201413 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/user.org/audio_to_axi_v1_0/27de6532/hdl/audio_to_AXI_v1_0.vhd | 2 | 4,272 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity audio_to_AXI_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
audio_in_l : in std_logic_vector(23 downto 0);
audio_in_r : in std_logic_vector(23 downto 0);
audio_in_valid : in std_logic;
audio_out_valid_irq : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end audio_to_AXI_v1_0;
architecture arch_imp of audio_to_AXI_v1_0 is
-- component declaration
component audio_to_AXI_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
audio_in_l : in std_logic_vector(23 downto 0);
audio_in_r : in std_logic_vector(23 downto 0);
audio_in_valid : in std_logic;
audio_out_valid_irq : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component audio_to_AXI_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
audio_to_AXI_v1_0_S00_AXI_inst : audio_to_AXI_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
audio_out_valid_irq => audio_out_valid_irq,
audio_in_valid => audio_in_valid,
audio_in_l => audio_in_l,
audio_in_r => audio_in_r,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
| lgpl-3.0 | 61e5545c83fb24182b94495fddaf4909 | 0.65824 | 2.419026 | false | false | false | false |
boztalay/OldProjects | FPGA/Sys_SecondTimer/Comp_Counter2bit.vhd | 1 | 1,501 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 23:08:49 07/29/2009
-- Design Name:
-- Module Name: Comp_Counter - Behavioral
-- Project Name: Binary Counter
-- Target Devices:
-- Tool versions:
-- Description: A binary counter with synchronous reset.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - First draft written
-- Revision 0.15 - Syntax errors fixed
-- Revision 1.00 - Generated programming file with a successful test on hardware
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Comp_Counter2bit is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (1 downto 0));
end Comp_Counter2bit;
architecture Behavioral of Comp_Counter2bit is
begin
main : process(reset, clock) is
variable value : STD_LOGIC_VECTOR(1 downto 0) := "00";
begin
if falling_edge(clock) then
if reset = '1' or value = b"11" then
value := b"00";
else
value := value + b"01";
end if;
end if;
output <= value;
end process main;
end Behavioral;
| mit | 5ee0f261101863f5acc19e48892bca3c | 0.598934 | 3.7525 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia_save/rs232in.vhd | 1 | 7,432 | -- ########################################################################
-- $Software: busiac
-- $section : hardware component
-- $Id: rs232in.vhd 325 2015-06-03 12:47:32Z ia $
-- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/rs232in.vhd $
-- $Author : Ivan Auge (Email: [email protected])
-- ########################################################################
--
-- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge.
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- BUSIAC software is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY ; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-- Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with the GNU C Library; see the file COPYING. If not, write to the Free
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
-- ######################################################################*/
-------------------------------------------------------------------------------
-- Ce module désérialise l'entrée RX dans la sortie DATA de 8 bits.
--
-- le format lu est:
-- - 1 start bit
-- - 8 bit de données
-- - 1 ou plusieurs stop bits
--
-- Ce module met NDATA à 1 pendant un cycle quand une nouvelle
-- valeur est présente sur DATA d'où le chronogramme suivant
-- avec A, B et C des valeurs stables de NDATA.
-- La valeur reste stable pendant un BAUD.
--
-- NDATA 0000100000000000000000001000000000000000100000000000
-- DATA ????AAAAA???????????????BBBBB???????????CCCCC???????
--
-- Pour fixer le BAUD du composant utilisez les paramètres génériques
-- BAUD et FREQ ci dessous.
-------------------------------------------------------------------------------
library IEEE ;
use IEEE.std_logic_1164.all ;
entity rs232in is
generic(
FREQ : integer := 50000000; -- Frequence de clk
BAUD : integer := 9600); -- Baud de Rx
port(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
rx : IN STD_LOGIC;
Ndata : OUT STD_LOGIC;
Data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-- debug
debug : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end rs232in;
architecture montage of rs232in is
signal CMD_sh: STD_LOGIC; -- 0:noop, 1:shift
signal R_sh: STD_LOGIC_VECTOR(7 DOWNTO 0);
type T_CMD_baud is (COUNT, INIT1P5B, INIT1B) ;
signal CMD_baud: T_CMD_baud;
signal VT_baud: STD_LOGIC;
signal R_baud: INTEGER RANGE 0 TO (2*FREQ)/BAUD;
type T_CMD_i is (NOOP, COUNT, INIT);
signal CMD_i: T_CMD_i;
signal R_i: INTEGER RANGE 0 TO 10;
signal VT_i: STD_LOGIC;
-- rx input avoid glitch
signal rx_R : std_logic;
signal rx_fifo_R : std_logic_vector(2 downto 0);
--Description des états
type STATE_TYPE is ( WAIT_StartBit, WAIT_1P5B, MainLoop, ECRIRE,
WAIT_1B, GEN_PULSE, WAIT_FIN);
signal state : STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
VT_baud <= '1' when R_baud=0 else '0';
VT_i <= '1' when R_i=0 else '0';
Data <= R_sh;
process (clk)
begin if clk'event and clk='1' then
if CMD_baud=INIT1P5B then
R_baud <= (FREQ+FREQ/2)/BAUD; -- init à 1.5 * F/B
elsif CMD_baud=INIT1B then
R_baud <= FREQ/BAUD; -- init à F/B
else
R_baud <= R_baud - 1;
end if;
-- R_i
if CMD_i=NOOP then
R_i <= R_i ; -- on ne fait rien (noop)
elsif CMD_i=INIT then
R_i <= 8; -- init à 8
else
R_i <= R_i - 1; -- on compte
end if;
-- R_sh
if CMD_sh='1' then
R_sh(6 downto 0) <= R_sh(7 downto 1);
R_sh(7) <= rx_R;
end if;
-- rx input avoid glitch
rx_fifo_R(2 downto 1) <= rx_fifo_R(1 downto 0);
rx_fifo_R(0) <= rx;
if rx_fifo_R = "000" or rx_fifo_R = "111" then
rx_R <= rx_fifo_R(2);
end if;
end if; end process;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- fonction de transitition
process (reset,clk)
begin
if reset = '1' then
state <= WAIT_StartBit;
elsif clk'event and clk = '1' then case state is
when WAIT_StartBit =>
if rx_R = '0' then
state <= WAIT_1P5B;
else
state <= WAIT_StartBit;
end if;
when WAIT_1P5B =>
if VT_baud='1' then
state <= MainLoop;
else
state <= WAIT_1P5B;
end if;
when MainLoop=>
if VT_i='1' then
state <= GEN_PULSE;
else
state <= ECRIRE;
end if;
when ECRIRE=>
state <= WAIT_1B;
when WAIT_1B=>
if VT_baud='1' then
state <= MainLoop;
else
state <= WAIT_1B;
end if;
when GEN_PULSE =>
state <= WAIT_FIN;
when WAIT_FIN=>
if VT_baud='1' then
state <= WAIT_StartBit;
else
state <= WAIT_FIN;
end if;
when others =>
state <= WAIT_StartBit;
end case; end if; end process;
-- fonction de sortie
with state select nData <=
'1' when GEN_PULSE,
'0' when others;
with state select CMD_sh <=
'1' when ECRIRE,
'0' when others;
with state select CMD_baud <=
INIT1B when MainLoop,
INIT1B when ECRIRE,
INIT1P5B when WAIT_StartBit,
COUNT when others;
with state select CMD_i <=
INIT when WAIT_StartBit,
INIT when WAIT_1P5B,
COUNT when MainLoop,
NOOP when others;
debug(7) <= rx_R;
with state select debug(6 downto 0) <=
"1000000" when WAIT_StartBit,
"0100000" when WAIT_1P5B,
"0010000" when MainLoop,
"0001000" when ECRIRE,
"0000100" when WAIT_1B,
"0000010" when GEN_PULSE,
"0000001" when WAIT_FIN,
"1111111" when others;
end montage;
| gpl-3.0 | 2586ae41c5f1de108d79d3a4cda9d14c | 0.449946 | 4.074561 | false | false | false | false |
boztalay/OldProjects | FPGA/Tests/SM_mem_init_test.vhd | 1 | 7,558 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SM_mem_init_test is
Port (clock : in STD_LOGIC;
reset : in STD_LOGIC;
RAM_wait : in STD_LOGIC;
memory_data_bus : inout STD_LOGIC_VECTOR(15 downto 0);
memory_address_bus : out STD_LOGIC_VECTOR(22 downto 0);
SM_reset : out STD_LOGIC;
RAM_ce : out STD_LOGIC;
RAM_we : out STD_LOGIC;
RAM_oe : out STD_LOGIC;
RAM_lb : out STD_LOGIC;
RAM_ub : out STD_LOGIC;
RAM_cre : out STD_LOGIC;
RAM_adv : out STD_LOGIC;
RAM_clk : out STD_LOGIC);
end entity;
architecture Behavioral of SM_mem_init_test is
component four_dig_7seg is
Port ( clock : in STD_LOGIC;
display_data : in STD_LOGIC_VECTOR (15 downto 0);
anodes : out STD_LOGIC_VECTOR (3 downto 0);
to_display : out STD_LOGIC_VECTOR (6 downto 0));
end component;
signal state : STD_LOGIC_VECTOR(4 downto 0);
signal SM_wait_counter : STD_LOGIC_VECTOR(2 downto 0);
signal clk_100MHz : STD_LOGIC;
signal RAM_clk_en : STD_LOGIC;
signal output_enable : STD_LOGIC;
signal memory_data_bus_in : STD_LOGIC_VECTOR(15 downto 0);
signal memory_data_bus_out : STD_LOGIC_VECTOR(15 downto 0);
signal collected_data : STD_LOGIC_VECTOR(15 downto 0);
begin
--The state machine
process (clk_100MHz, reset)
begin
if reset = '1' then
state <= "00000";
SM_reset <= '1';
SM_wait_counter <= "000";
output_enable <= '0';
RAM_ce <= '1';
RAM_we <= '1';
RAM_oe <= '0';
RAM_adv <= '1';
RAM_lb <= '0';
RAM_ub <= '0';
RAM_cre <= '0';
RAM_clk_en <= '0';
elsif falling_edge(clk_100MHz) then
case state is
--These first states put the memory into synchronous mode
--Read cycle one
when "00000" =>
SM_reset <= '1';
RAM_ce <= '0';
RAM_we <= '1';
RAM_oe <= '0';
RAM_lb <= '0';
RAM_ub <= '0';
RAM_clk_en <= '0';
RAM_cre <= '0';
memory_address_bus <= (others => '1');
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00001";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00000";
end if;
when "00001" =>
RAM_ce <= '1';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00010";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00001";
end if;
--Read cycle two
when "00010" =>
RAM_ce <= '0';
memory_address_bus <= (others => '1');
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00011";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00010";
end if;
when "00011" =>
RAM_ce <= '1';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00100";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00011";
end if;
--Write cycle one
when "00100" =>
--Setup state for the first write cycle
RAM_oe <= '1';
RAM_ce <= '0';
memory_address_bus <= (others => '1');
output_enable <= '1';
memory_data_bus_out <= x"0001";
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00101";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00100";
end if;
when "00101" =>
--Second half of the first write cycle
RAM_we <= '0';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00110";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00101";
end if;
when "00110" =>
RAM_ce <= '1';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00111";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00110";
end if;
--Second write cycle
when "00111" =>
RAM_ce <= '0';
memory_data_bus_out <= b"0001110101001111"; --BCR data
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "01000";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00111";
end if;
when "01000" =>
output_enable <= '0';
RAM_ce <= '1';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "01001";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "01000";
end if;
--End of initialization, begin normal operation
--Wait state, also enable RAM_clk
when "01001" =>
RAM_clk_en <= '1';
output_enable <= '1';
state <= "01010";
--Set up the signals for a write
when "01010" =>
RAM_ce <= '0';
RAM_adv <= '0';
RAM_we <= '0';
RAM_oe <= '1';
memory_address_bus <= b"00000000000000000000001";
state <= "01011";
--Wait for RAM_wait
when "01100" =>
RAM_adv <= '0';
if RAM_wait = '1' then
state <= "01101";
else
state <= "01100";
end if;
--Begin the writes
when "01101" =>
memory_data_bus_out <= x"000F";
state <= "01110";
when "01110" =>
memory_data_bus_out <= x"000E";
state <= "01111";
when "01111" =>
memory_data_bus_out <= x"000D";
state <= "10000";
when "10000" =>
memory_data_bus_out <= x"000C";
state <= "10001";
--End the write
when "10001" =>
RAM_ce <= '1';
state <= "10010";
--A wait cycle
when "10010" =>
state <= "10011";
--Set up the signals for a read
when "10011" =>
RAM_ce <= '0';
RAM_adv <= '0';
RAM_oe <= '0';
RAM_we <= '1';
output_enable <= '0';
memory_address_bus <= b"00000000000000000000001";
state <= "10100";
--Read into a register
when "10100" =>
collected_data(3 downto 0) <= memory_data_bus_in(3 downto 0);
state <= "10101";
when "10101" =>
collected_data(7 downto 4) <= memory_data_bus_in(3 downto 0);
state <= "10110";
when "10110" =>
collected_data(11 downto 8) <= memory_data_bus_in(3 downto 0);
state <= "10111";
when "10111" =>
collected_data(15 downto 12) <= memory_data_bus_in(3 downto 0);
state <= "11000";
--End the read and wait here
when "11000" =>
RAM_ce <= '1';
RAM_oe <= '1';
RAM_we <= '1';
state <= "11000";
when others =>
state <= "00000";
end case;
end if;
end process;
--A tristate buffer for the memory data bus
tristate : process (output_enable, memory_data_bus_in)
begin
if output_enable = '1' then
memory_data_bus <= memory_data_bus_out;
else
memory_data_bus <= (others => 'Z');
end if;
memory_data_bus_in <= memory_data_bus;
end process;
--Handles the enabling of the RAM clock
RAM_clock : process (RAM_clk, RAM_clk_en)
begin
if RAM_clk_en = '1' then
RAM_clk <= clk_100MHz;
else
RAM_clk <= 'Z';
end if;
end process;
display: four_dig_7seg port map (clock => clock,
display_data => collected_data,
anodes => anodes,
to_display => decoder_out);
clk_100MHz <= clock;
end Behavioral; | mit | 0657b4b3d0e13adb3154f16d7d7db25d | 0.511379 | 3.100082 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/iqit_node.vhd | 1 | 16,706 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity iqit_node is
generic(
sample_width : integer := 8;
qp_width : integer := 8;
wo_dc_width : integer := 8;
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic--;
----debug
-- state_out : out std_logic_vector(7 downto 0);
-- input_sample_0 : out std_logic_vector(7 downto 0);
-- input_sample_1 : out std_logic_vector(7 downto 0);
-- input_sample_2 : out std_logic_vector(7 downto 0);
-- input_sample_3 : out std_logic_vector(7 downto 0);
-- input_sample_4 : out std_logic_vector(7 downto 0);
-- input_sample_5 : out std_logic_vector(7 downto 0);
-- input_sample_6 : out std_logic_vector(7 downto 0);
-- input_sample_7 : out std_logic_vector(7 downto 0);
-- input_sample_8 : out std_logic_vector(7 downto 0);
-- input_sample_9 : out std_logic_vector(7 downto 0);
-- input_sample_A : out std_logic_vector(7 downto 0);
-- input_sample_B : out std_logic_vector(7 downto 0);
-- input_sample_C : out std_logic_vector(7 downto 0);
-- input_sample_D : out std_logic_vector(7 downto 0);
-- input_sample_E : out std_logic_vector(7 downto 0);
-- input_sample_F : out std_logic_vector(7 downto 0);
-- qp_out : out std_logic_vector(7 downto 0);
-- zigzag_0 : out std_logic_vector(7 downto 0);
-- zigzag_1 : out std_logic_vector(7 downto 0);
-- zigzag_2 : out std_logic_vector(7 downto 0);
-- zigzag_3 : out std_logic_vector(7 downto 0);
-- zigzag_4 : out std_logic_vector(7 downto 0);
-- zigzag_5 : out std_logic_vector(7 downto 0);
-- zigzag_6 : out std_logic_vector(7 downto 0);
-- zigzag_7 : out std_logic_vector(7 downto 0);
-- zigzag_8 : out std_logic_vector(7 downto 0);
-- zigzag_9 : out std_logic_vector(7 downto 0);
-- zigzag_A : out std_logic_vector(7 downto 0);
-- zigzag_B : out std_logic_vector(7 downto 0);
-- zigzag_C : out std_logic_vector(7 downto 0);
-- zigzag_D : out std_logic_vector(7 downto 0);
-- zigzag_E : out std_logic_vector(7 downto 0);
-- zigzag_F : out std_logic_vector(7 downto 0);
-- dequant_0 : out std_logic_vector(15 downto 0);
-- dequant_1 : out std_logic_vector(15 downto 0);
-- dequant_2 : out std_logic_vector(15 downto 0);
-- dequant_3 : out std_logic_vector(15 downto 0);
-- dequant_4 : out std_logic_vector(15 downto 0);
-- dequant_5 : out std_logic_vector(15 downto 0);
-- dequant_6 : out std_logic_vector(15 downto 0);
-- dequant_7 : out std_logic_vector(15 downto 0);
-- dequant_8 : out std_logic_vector(15 downto 0);
-- dequant_9 : out std_logic_vector(15 downto 0);
-- dequant_A : out std_logic_vector(15 downto 0);
-- dequant_B : out std_logic_vector(15 downto 0);
-- dequant_C : out std_logic_vector(15 downto 0);
-- dequant_D : out std_logic_vector(15 downto 0);
-- dequant_E : out std_logic_vector(15 downto 0);
-- dequant_F : out std_logic_vector(15 downto 0);
-- result_0 : out std_logic_vector(7 downto 0);
-- result_1 : out std_logic_vector(7 downto 0);
-- result_2 : out std_logic_vector(7 downto 0);
-- result_3 : out std_logic_vector(7 downto 0);
-- result_4 : out std_logic_vector(7 downto 0);
-- result_5 : out std_logic_vector(7 downto 0);
-- result_6 : out std_logic_vector(7 downto 0);
-- result_7 : out std_logic_vector(7 downto 0);
-- result_8 : out std_logic_vector(7 downto 0);
-- result_9 : out std_logic_vector(7 downto 0);
-- result_A : out std_logic_vector(7 downto 0);
-- result_B : out std_logic_vector(7 downto 0);
-- result_C : out std_logic_vector(7 downto 0);
-- result_D : out std_logic_vector(7 downto 0);
-- result_E : out std_logic_vector(7 downto 0);
-- result_F : out std_logic_vector(7 downto 0)
);
end entity iqit_node;
architecture fsmd of iqit_node is
--- COMPONENTS ------------------------------------------------------------
component zigzag is
generic(
sample_width : integer := 8
);
port(
x : in std_logic_vector((16*sample_width)-1 downto 0);
y : out std_logic_vector((16*sample_width)-1 downto 0)
);
end component zigzag;
component inverse_quant is
generic(
in_sample_width : integer := 8;
out_sample_width : integer := 16;
qp_width : integer := 8;
wo_dc_width : integer := 8
);
port(
quantized_samples : in std_logic_vector((16*in_sample_width)-1 downto 0);
quant_param : in std_logic_vector(qp_width-1 downto 0);
without_dc : in std_logic_vector(wo_dc_width-1 downto 0);
dequant_samples : out std_logic_vector((16*out_sample_width)-1 downto 0)
);
end component inverse_quant;
component inverse_transform is
generic(
in_sample_width : integer := 16;
out_sample_width : integer := 8
);
port(
transform_block : in std_logic_vector((16*in_sample_width)-1 downto 0);
inv_transform_block : out std_logic_vector((16*out_sample_width)-1 downto 0);
sign_mask : out std_logic_vector(15 downto 0)
);
end component inverse_transform;
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
--- TYPES -----------------------------------------------------------------
type iqit_states is (idle,
sel_vc,
rx_header,
dequeue_header,
wait_row_4_3,
rx_row_4_3,
dequeue_row_4_3,
wait_row_2_1,
rx_row_2_1,
dequeue_row_2_1,
wait_tx_header,
tx_header,
wait_tx_row_4_3,
tx_row_4_3,
wait_tx_row_2_1,
tx_row_2_1
);
--- SIGNALS ---------------------------------------------------------------
signal state : iqit_states;
signal next_state : iqit_states;
signal quant_param_d : std_logic_vector(qp_width-1 downto 0);
signal quant_param_q : std_logic_vector(qp_width-1 downto 0);
signal without_dc_d : std_logic_vector(wo_dc_width-1 downto 0);
signal without_dc_q : std_logic_vector(wo_dc_width-1 downto 0);
signal identifier_d : std_logic_vector(7 downto 0);
signal identifier_q : std_logic_vector(7 downto 0);
signal input_samples_d : std_logic_vector((16*sample_width)-1 downto 0);
signal input_samples_q : std_logic_vector((16*sample_width)-1 downto 0);
signal samples_after_zigzag : std_logic_vector((16*sample_width)-1 downto 0);
signal samples_after_inv_q : std_logic_vector((16*2*sample_width)-1 downto 0);
signal inv_t_input : std_logic_vector((16*2*sample_width)-1 downto 0);
signal result_samples : std_logic_vector((16*sample_width)-1 downto 0);
signal tx_header_data : std_logic_vector(data_width-1 downto 0);
signal tx_row_4_3_data : std_logic_vector(data_width-1 downto 0);
signal tx_row_2_1_data : std_logic_vector(data_width-1 downto 0);
signal sel_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_enc : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_one_hot : std_logic_vector(num_vc-1 downto 0);
signal dc_high_byte_q : std_logic_vector(7 downto 0);
signal dc_high_byte_d : std_logic_vector(7 downto 0);
signal sign_mask : std_logic_vector(15 downto 0);
signal x_pass_thru_d : std_logic_vector(10 downto 0);
signal y_pass_thru_d : std_logic_vector(10 downto 0);
signal LCbCr_pass_thru_d : std_logic_vector(1 downto 0);
signal x_pass_thru_q : std_logic_vector(10 downto 0);
signal y_pass_thru_q : std_logic_vector(10 downto 0);
signal LCbCr_pass_thru_q : std_logic_vector(1 downto 0);
constant do_iqit_cmd : std_logic_vector(7 downto 0) := x"03";
begin
--- DATAPATH --------------------------------------------------------------
u0: component zigzag
generic map(
sample_width => sample_width
)
port map(
x => input_samples_q,
y => samples_after_zigzag
);
u1: component inverse_quant
generic map(
in_sample_width => sample_width,
out_sample_width => 2*sample_width,
qp_width => qp_width,
wo_dc_width => wo_dc_width
)
port map(
quantized_samples => samples_after_zigzag,
quant_param => quant_param_q,
without_dc => without_dc_q,
dequant_samples => samples_after_inv_q
);
u2: component inverse_transform
generic map(
in_sample_width => 2*sample_width,
out_sample_width => sample_width
)
port map(
transform_block => inv_t_input,
inv_transform_block => result_samples,
sign_mask => sign_mask
);
u3: component priority_encoder
generic map(
encoded_word_size => vc_sel_width
)
Port map(
input => data_in_buffer,
output => sel_vc_enc
);
--register process
process(clk, rst) begin
if rst = '1' then
state <= idle;
quant_param_q <= (others => '0');
without_dc_q <= (others => '0');
identifier_q <= (others => '0');
input_samples_q <= (others => '0');
sel_vc_q <= (others => '0');
dc_high_byte_q <= (others => '0');
x_pass_thru_q <= (others => '0');
y_pass_thru_q <= (others => '0');
LCbCr_pass_thru_q <= (others => '0');
elsif rising_edge(clk) then
state <= next_state;
quant_param_q <= quant_param_d;
without_dc_q <= without_dc_d;
identifier_q <= identifier_d;
input_samples_q <= input_samples_d;
sel_vc_q <= sel_vc_d;
dc_high_byte_q <= dc_high_byte_d;
x_pass_thru_q <= x_pass_thru_d;
y_pass_thru_q <= y_pass_thru_d;
LCbCr_pass_thru_q <= LCbCr_pass_thru_d;
end if;
end process;
--insert high byte of dc into signal if non-zero
inv_t_input <= samples_after_inv_q(16*2*sample_width-1 downto sample_width*2) & dc_high_byte_q & samples_after_inv_q(sample_width-1 downto 0) when or_reduce(dc_high_byte_q) = '1' else
samples_after_inv_q;
--parse packet
quant_param_d <= recv_data(47 downto 40) when state = rx_header else quant_param_q;
without_dc_d <= recv_data(39 downto 32) when state = rx_header else without_dc_q;
identifier_d <= recv_data(7 downto 0) when state = rx_header else identifier_q;
dc_high_byte_d <= recv_data(55 downto 48) when state = rx_header else dc_high_byte_q;
x_pass_thru_d <= recv_data(18 downto 8) when state = rx_header else x_pass_thru_q;
y_pass_thru_d <= recv_data(29 downto 19) when state = rx_header else y_pass_thru_q;
LCbCr_pass_thru_d <= recv_data(31 downto 30) when state = rx_header else LCbCr_pass_thru_q;
input_samples_d((16*sample_width)-1 downto (8*sample_width)) <= recv_data when state = rx_row_4_3 else
input_samples_q((16*sample_width)-1 downto (8*sample_width));
input_samples_d((8*sample_width)-1 downto 0) <= recv_data when state = rx_row_2_1 else
input_samples_q((8*sample_width)-1 downto 0);
-- format repsonse packet
tx_header_data <= x_pass_thru_q & "00000" &sign_mask& "000" & LCbCr_pass_thru_q & y_pass_thru_q &do_iqit_cmd&identifier_q;
tx_row_4_3_data <= result_samples((16*sample_width)-1 downto (8*sample_width));
tx_row_2_1_data <= result_samples((8*sample_width)-1 downto 0) ;
-- channel selection logic
sel_vc_d <= sel_vc_enc when state = sel_vc else sel_vc_q;
--rx controls
dequeue <= sel_vc_one_hot when state = dequeue_header or state = dequeue_row_4_3 or state = dequeue_row_2_1 else "00";
select_vc_read <= sel_vc_q;
sel_vc_one_hot <= "01" when sel_vc_q = "0" else "10";
--packet generation
send_data <= tx_header_data when state = wait_tx_header or state = tx_header else
tx_row_4_3_data when state = wait_tx_row_4_3 or state = tx_row_4_3 else
tx_row_2_1_data when state = wait_tx_row_2_1 or state = tx_row_2_1 else
std_logic_vector(to_unsigned(0, data_width));
dest_addr <= std_logic_vector(to_unsigned(7, addr_width));
set_tail_flit <= '1' when state = wait_row_2_1 or state = tx_row_2_1 else '0';
send_flit <= '1' when state = tx_header or state = tx_row_4_3 or state = tx_row_2_1 else '0';
-- STATE MACHINE ----------------------------------------------------------
process(state, data_in_buffer, is_tail_flit, sel_vc_one_hot, ready_to_send)
begin
next_state <= state; --default behaviour
if state = idle and or_reduce(data_in_buffer) = '1' then
next_state <= sel_vc;
end if;
if state = sel_vc then
next_state <= rx_header;
end if;
if state = rx_header then
next_state <= dequeue_header;
end if;
if state = dequeue_header then
next_state <= wait_row_4_3;
end if;
if state = wait_row_4_3 and or_reduce(sel_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx_row_4_3;
end if;
if state = rx_row_4_3 then
next_state <= dequeue_row_4_3;
end if;
if state = dequeue_row_4_3 then
next_state <= wait_row_2_1;
end if;
if state = wait_row_2_1 and or_reduce(sel_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx_row_2_1;
end if;
if state = rx_row_2_1 then
next_state <= dequeue_row_2_1;
end if;
if state = dequeue_row_2_1 then
next_state <= wait_tx_header;
end if;
if state = wait_tx_header and ready_to_send = '1' then
next_state <= tx_header;
end if;
if state = tx_header then
next_state <= wait_tx_row_4_3;
end if;
if state = wait_tx_row_4_3 and ready_to_send = '1' then
next_state <= tx_row_4_3;
end if;
if state = tx_row_4_3 then
next_state <= wait_tx_row_2_1;
end if;
if state = wait_tx_row_2_1 and ready_to_send = '1' then
next_state <= tx_row_2_1;
end if;
if state = tx_row_2_1 then
next_state <= idle;
end if;
end process;
end architecture fsmd; | mit | 4f6bb3d778595c9f7b2fe67f89752036 | 0.539507 | 3.383836 | false | false | false | false |
boztalay/OldProjects | FPGA/Sys_SecondTimer/Comp_ClockGen1Hz.vhd | 1 | 1,732 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 14:57:12 07/30/2009
-- Design Name:
-- Module Name: Comp_ClockGen - Behavioral
-- Project Name: Clock Generator
-- Target Devices:
-- Tool versions:
-- Description: A device that generates a buffered clock signal in refernce to
-- a 50 MHz outside clock. The output can be reconfigured through
-- software to generate a different frequency.
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - First draft written
-- Revision 0.15 - Sytax errors fixed
-- Revision 0.30 - UCF File written
-- Revision 1.00 - Generated programming file with a successful hardware test
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Comp_ClockGen1Hz is
Port ( Board_Clk : in STD_LOGIC;
Clock_Out : out STD_LOGIC);
end Comp_ClockGen1Hz;
architecture Behavioral of Comp_ClockGen1Hz is
begin
main : process(Board_Clk) is
constant hertz : integer := 1;
constant cycles : integer := (25_000_000/hertz);
variable count : integer := 0;
variable output : STD_LOGIC := '0';
begin
if rising_edge(Board_Clk) then
count := count + 1;
if count > cycles then
count := 0;
output := not output;
end if;
end if;
Clock_Out <= output;
end process main;
end Behavioral;
| mit | 3fc050efcc8e1d4fb4e30d785998847c | 0.618938 | 3.848889 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/terminateur/terminateur.vhd | 3 | 6,218 | -- ########################################################################
-- $Software: busiac
-- $section : hardware component
-- $Id: terminateur.vhd 322 2015-05-29 06:43:59Z ia $
-- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/terminateur.vhd $
-- $Author : Ivan Auge (Email: [email protected])
-- ########################################################################
--
-- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge.
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- BUSIAC software is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY ; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-- Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with the GNU C Library; see the file COPYING. If not, write to the Free
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
-- ######################################################################*/
-------------------------------------------------------------------------------
-- ATTENTION:
-- Ceci un template, les trous marqués "..." doivent être comblés pour
-- pouvoir être compilé, puis fonctionné.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Ce module transfert tous les messages (????,addrsrc,addrdest,data) venant de
-- busin.
-- Si ????=???1, il transmet le messages sur busdump.
-- Si ????=???0 et addrdest!=MYADDR, il transmet sur busout le message
-- (???1,addrsrc,addrdest,data).
-- Si addrdest==MYADDR, il transmet le message sur busdump.
--
-- Du coté busin, il suit le protocole "poignée de main" (signaux: busin,
-- busin_valid, busin_eated).
-- Du coté busout, il suit le protocole "poignée de main" (signaux: busout,
-- busout_valid, busout_eated).
-- Du coté busdump, il suit le protocole "poignée de main" (signaux: busdump,
-- busdump_valid, busdump_eated).
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity terminateur is
generic(
MYADDR : STD_LOGIC_VECTOR(7 downto 0) := "11111111" -- 255
);
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- interface busin
busin : in STD_LOGIC_VECTOR(43 downto 0);
busin_valid : in STD_LOGIC;
busin_eated : out STD_LOGIC;
-- interface busout
busout : out STD_LOGIC_VECTOR(43 downto 0);
busout_valid : out STD_LOGIC;
busout_eated : in STD_LOGIC;
-- interface busdump
busdump : out STD_LOGIC_VECTOR(43 downto 0);
busdump_valid: out STD_LOGIC;
busdump_eated: in STD_LOGIC);
end terminateur;
architecture montage of terminateur is
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
-- Registre de transfert entre busin et busout
type T_CMD_tft is (INIT, NOOP);
signal CMD_tft : T_CMD_tft ;
signal R_tft : STD_LOGIC_VECTOR (43 downto 0);
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- adresse destination & bit de boucle du message lu
alias busin_addrdest : STD_LOGIC_VECTOR(7 downto 0) is busin(31 downto 24);
alias busin_loop : STD_LOGIC is busin(40);
type STATE_TYPE is (
ST_READ_BUSIN, ST_WRITE_OUT, ST_WRITE_DUMP
);
signal state : STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
process (clk)
begin if clk'event and clk = '1' then
IF CMD_tft = INIT THEN
R_tft <= busin ;
END IF;
end if; end process;
busout(43 downto 41) <= R_tft(43 downto 41);
busout(40) <= '1';
busout(39 downto 0) <= R_tft(39 downto 0);
busdump <= R_tft;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: busin_valid, busout_eated, busdump_eated, busin_addrdest, busin_loop
-- Outputs: busin_eated, busout_valid, busdump_valid, CMD_tft
-------------------------------------------------------------------------------
-- fonction de transitition
process (reset,clk)
begin
if reset = '1' then
state <= ST_READ_BUSIN;
elsif clk'event and clk = '1' then
case state is
when ST_READ_BUSIN =>
IF busin_valid='1' THEN
IF busin_loop = '1' OR busin_addrdest = MYADDR THEN
state <= ST_WRITE_DUMP ;
ELSE
state <= ST_WRITE_OUT ;
END IF ;
END IF ;
when ST_WRITE_OUT =>
IF busout_eated = '1' THEN
state <= ST_READ_BUSIN;
END IF ;
when ST_WRITE_DUMP =>
IF busdump_eated = '1' THEN
state <= ST_READ_BUSIN;
END IF ;
end case;
end if;
end process;
-- fonction de sortie
with state select busin_eated <=
'1' when ST_READ_BUSIN,
'0' when others;
with state select busout_valid <=
'1' when ST_WRITE_OUT,
'0' when others;
with state select busdump_valid <=
'1' when ST_WRITE_DUMP,
'0' when others;
with state select CMD_tft <=
INIT when ST_READ_BUSIN,
NOOP when others;
end montage;
| gpl-3.0 | d69649b2788bf8b0d9e393996db1ca0a | 0.479845 | 4.461871 | false | false | false | false |
DaveyPocket/btrace448 | core/vga/list_ch13_01_font_rom.vhd | 1 | 51,592 | -- Obtained from: http://academic.csuohio.edu/chu_p/rtl/fpga_vhdl_book/fpga_vhdl_src.zip
-- Listing 13.1
-- ROM with synchonous read (inferring Block RAM)
-- character ROM
-- - 8-by-16 (8-by-2^4) font
-- - 128 (2^7) characters
-- - ROM size: 512-by-8 (2^11-by-8) bits
-- 16K bits: 1 BRAM
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity font_rom is
port(
clk: in std_logic;
addr: in std_logic_vector(10 downto 0);
data: out std_logic_vector(7 downto 0)
);
end font_rom;
architecture arch of font_rom is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1)
of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition
constant ROM: rom_type:=( -- 2^11-by-8
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x510
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process (clk)
begin
if (clk'event and clk = '1') then
addr_reg <= addr;
end if;
end process;
data <= ROM(to_integer(unsigned(addr_reg)));
end arch;
| gpl-3.0 | 0543432e1c45b95c7bd2f73888f672d3 | 0.388083 | 3.24376 | false | false | false | false |
DaveyPocket/btrace448 | math/squareroot_TB.vhd | 1 | 861 | -- Btrace 448
-- Square Root Unit Test Bench
--
-- Bradley Boccuzzi
-- 2016
library ieee;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity squareroot_TB is
end entity;
architecture arch of squareroot_TB is
constant clkPd: time := 20 ns;
signal clk: std_logic;
signal din: ufixed(15 downto -16) := (others => '0');
signal dout: ufixed(15 downto -16);
begin
uut: entity work.squareroot port map(clk, din, dout);
clkProc: process
begin
wait for clkPd/2;
clk <= '1';
wait for clkPd/2;
clk <= '0';
end process clkProc;
mainTB: process
begin
wait for clkPd/3;
din <= x"00040000"; -- 4
wait for 3*clkPd;
din <= x"00100000"; -- 16
wait for 3*clkPd;
din <= x"00018000"; -- 1.5
wait for 3*clkPd;
din <= x"0FF00000";
wait;
end process mainTB;
end arch;
| gpl-3.0 | e9614f4cf2a45fe6c62efb5bac758db8 | 0.670151 | 2.813725 | false | false | false | false |
AfterRace/SoC_Project | vivado/ip_repo/adau1761_audio_1.0/hdl/audio_testbench.vhd | 1 | 5,486 | ----------------------------------------------------------------------------------
-- Testbench for Audiointerface for Zedboard
--
-- Stefan Scholl, DC9ST
-- Microelectronic Systems Design Research Group
-- TU Kaiserslautern
-- 2014
----------------------------------------------------------------------------------
-- This testbench can operate in two different modes:
--
-- 1: sawtooth mode: outputs a simple sawtool signal on l and right headphone output (discards input signals)
-- 2: loopback mode: line in signals are routed to the headphone output
--
-- choose between the two mode by commenting the code blocks below
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity audio_testbench is
Port ( clk_100 : in STD_LOGIC; -- 100 mhz master takt
AC_ADR0 : out STD_LOGIC; -- control signals to ADAU chip
AC_ADR1 : out STD_LOGIC;
AC_GPIO0 : out STD_LOGIC; -- I2S MISO
AC_GPIO1 : in STD_LOGIC; -- I2S MOSI
AC_GPIO2 : in STD_LOGIC; -- I2S_bclk
AC_GPIO3 : in STD_LOGIC; -- I2S_LR
AC_MCLK : out STD_LOGIC;
AC_SCK : out STD_LOGIC;
AC_SDA : inout STD_LOGIC
);
end audio_testbench;
architecture Behavioral of audio_testbench is
COMPONENT audio_top
Port ( clk_100 : in STD_LOGIC; -- 100 mhz input clock
AC_ADR0 : out STD_LOGIC; -- contol signals to audio chip
AC_ADR1 : out STD_LOGIC;
AC_GPIO0 : out STD_LOGIC; -- I2S MISO
AC_GPIO1 : in STD_LOGIC; -- I2S MOSI
AC_GPIO2 : in STD_LOGIC; -- I2S_bclk
AC_GPIO3 : in STD_LOGIC; -- I2S_LR
AC_MCLK : out STD_LOGIC;
AC_SCK : out STD_LOGIC;
AC_SDA : inout STD_LOGIC;
hphone_l : in STD_LOGIC_VECTOR(23 downto 0);
hphone_l_valid : in std_logic;
hphone_r : in STD_LOGIC_VECTOR(23 downto 0);
hphone_r_valid_dummy : in std_logic;
line_in_l : out STD_LOGIC_VECTOR(23 downto 0);
line_in_r : out STD_LOGIC_VECTOR(23 downto 0);
new_sample : out STD_LOGIC; -- goes up for 1 clk cycle if new sample is transmitted received
sample_clk_48k : out std_logic -- sample clock
);
END COMPONENT;
signal clk_100_buffered: std_logic;
signal counter : unsigned (5 downto 0);
signal hphone_l, hphone_r : std_logic_vector (23 downto 0);
signal hphone_valid: std_logic;
signal new_sample : std_logic;
signal sample_clk_48k: std_logic;
signal line_in_l, line_in_r : std_logic_vector (23 downto 0);
-- keep signals for tracking them with the Logic Analyzer
attribute keep : string;
attribute keep of sample_clk_48k : signal is "true";
attribute keep of hphone_l : signal is "true";
attribute keep of hphone_r : signal is "true";
attribute keep of line_in_l : signal is "true";
attribute keep of line_in_r : signal is "true";
begin
i_audio : audio_top port map (
clk_100 => clk_100_buffered,
AC_ADR0 => AC_ADR0,
AC_ADR1 => AC_ADR1,
AC_GPIO0 => AC_GPIO0,
AC_GPIO1 => AC_GPIO1,
AC_GPIO2 => AC_GPIO2,
AC_GPIO3 => AC_GPIO3,
AC_MCLK => AC_MCLK,
AC_SCK => AC_SCK,
AC_SDA => AC_SDA,
hphone_l => hphone_l,
hphone_l_valid => hphone_valid,
hphone_r => hphone_r,
hphone_r_valid_dummy => hphone_valid, -- this valid will be discarded later
line_in_l => line_in_l,
line_in_r => line_in_r,
new_sample => new_sample,
sample_clk_48k => sample_clk_48k
);
-- use comments to switch between TEST 1 (sawtooth) and 2 (loopback)
--------------------------------------------------
-- TEST 1: output sawtooth signal, discard input data
process (clk_100)
begin
if (clk_100'event and clk_100 = '1') then
hphone_valid <= '0';
hphone_l <= (others => '0');
hphone_r <= (others => '0');
if new_sample = '1' then
counter <= counter + 1;
hphone_valid <= '1';
hphone_l <= std_logic_vector(counter) & "000000000000000000" ;
hphone_r <= std_logic_vector(counter) & "000000000000000000";
end if;
end if;
end process;
-----------------------------------------------------
-- TEST 2: loopback "line in" data to headphone output
-- process (clk_100)
-- begin
-- if (clk_100'event and clk_100 = '1') then
-- hphone_valid <= '0';
-- hphone_l <= (others => '0');
-- hphone_r <= (others => '0');
-- if new_sample = '1' then
-- counter <= counter + 1;
-- hphone_valid <= '1';
-- hphone_l <= line_in_l ;
-- hphone_r <= line_in_r;
-- end if;
-- end if;
-- end process;
-- global clock buffer for the clock signal
BUFG_inst : BUFG
port map (
O => clk_100_buffered, -- 1-bit output: Clock output
I => clk_100 -- 1-bit input: Clock input
);
end Behavioral;
| lgpl-3.0 | 920aa67542f7ff57c14d8b47c443ec96 | 0.538279 | 3.689307 | false | false | false | false |
boztalay/OldProjects | FPGA/Sync_Mem/Sync_Mem.vhd | 1 | 5,131 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:05:03 07/02/2010
-- Design Name:
-- Module Name: Sync_Mem - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity Sync_Mem is
Port( clock : in STD_LOGIC;
reset : in STD_LOGIC;
RAM_wait : in STD_LOGIC;
memory_data_bus : inout STD_LOGIC_VECTOR(15 downto 0);
memory_address_bus : out STD_LOGIC_VECTOR(22 downto 0);
anodes : out STD_LOGIC_VECTOR(3 downto 0);
decoder_out : out STD_LOGIC_VECTOR(6 downto 0);
RAM_ce : out STD_LOGIC;
RAM_lb : out STD_LOGIC;
RAM_ub : out STD_LOGIC;
RAM_adv : out STD_LOGIC;
RAM_cre : out STD_LOGIC;
RAM_clk : out STD_LOGIC;
RAM_oe : out STD_LOGIC;
RAM_we : out STD_LOGIC;
flash_ce : out STD_LOGIC);
end Sync_Mem;
architecture Behavioral of Sync_Mem is
component four_dig_7seg is
Port ( clock : in STD_LOGIC;
display_data : in STD_LOGIC_VECTOR (15 downto 0);
anodes : out STD_LOGIC_VECTOR (3 downto 0);
to_display : out STD_LOGIC_VECTOR (6 downto 0));
end component;
signal write_enable : STD_LOGIC;
signal data_in : STD_LOGIC_VECTOR(15 downto 0);
signal data_out : STD_LOGIC_VECTOR(15 downto 0);
signal clk_200MHz : STD_LOGIC;
signal read_data : STD_LOGIC_VECTOR(15 downto 0);
signal state : STD_LOGIC_VECTOR(3 downto 0);
begin
DCM_1 : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 2, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 8, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 20.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "HIGH", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLKFX => clk_200MHz, -- DCM CLK synthesis out (M/D)
CLKIN => clock
);
state_machine: process(clk_200MHz, reset, state)
begin
if reset = '1' then
state <= "0000";
elsif falling_edge(clk_200MHz) then
case (state) is
when "0000" =>
memory_address_bus <= b"00000000000000000000001";
write_enable <= '0';
RAM_adv <= '0';
RAM_ce <= '0';
RAM_we <= '0';
RAM_oe <= '1';
state <= "0001";
when "0001" =>
RAM_adv <= '1';
--Wait for WAIT to go high
if RAM_wait = '0' then
state <= "0001";
else
state <= "0010";
write_enable <= '1';
data_out <= x"98DA";
end if;
when "0010" =>
state <= "0110";
RAM_ce <= '1';
write_enable <= '0';
when "0110" =>
RAM_ce <= '0';
RAM_adv <= '0';
RAM_oe <= '0';
RAM_we <= '1';
state <= "0111";
when "0111" =>
RAM_adv <= '1';
--Wait for WAIT
if RAM_wait = '0' then
state <= "0111";
else
state <= "1001";
read_data <= data_in;
end if;
when "1001" =>
state <= "1100";
RAM_ce <= '1';
when others =>
state <= "1100";
end case;
end if;
end process;
--This models a 3-state buffer for using the bidirectional data bus
buffer3 : process (write_enable, data_in, data_out) is
begin
if write_enable = '1' then
memory_data_bus <= data_out;
--Otherwise, don't drive the bus
else
memory_data_bus <= "ZZZZZZZZZZZZZZZZ";
end if;
data_in <= memory_data_bus;
end process;
display: four_dig_7seg port map (clock => clock,
display_data => read_data,
anodes => anodes,
to_display => decoder_out);
RAM_clk <= clk_200MHz;
end Behavioral;
| mit | d311f446c25803cf74a27a928d2c41dc | 0.545508 | 3.301802 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/user.org/zed_audio_v1_0/8de2dafc/hdl/audio_top.vhd | 2 | 9,495 | ----------------------------------------------------------------------------------
-- Audiointerface for Zedboard based on Hamster Works's Design
--
-- Stefan Scholl, DC9ST
-- Microelectronic Systems Design Research Group
-- TU Kaiserslautern, Germany
-- 2014
--
-- Description:
-- Audio Interface for the ADAU1716 on Zedboard:
-- 1) Audio samples are read from the blue "line in" jack and are provided by line_in_l and _r to the FPGA logic.
-- new "line in" samples are signaled by a rising edge of new_sample and the rising edge of sample_clk_48k.
-- 2) Audio samples can be passed to the ADAU1761 for output on the black headphone jack via the hphone_l and _r signals
-- Note, that after a new "line in" sample has been signalized, the design accepts a sample for the headphone within nearly one sample period (i.e. within ~2000 clock cycles)
--
-- attention: hphone inputs l and r are simultaneously sampled on valid signal of channel l
-- valid signal of ch r (hphone_r_valid_dummy) is discarded and is only there to be able to form an AXIS interface in the Vivado Packager)
-- IN MONO OPERATION USE L CHANNEL!
--
-- Configuration data for the ADAU 1761 is provided by I2C. Transmission of adui data to the ADAU1761 is accomplished by I2S.
-- The interface to the FPGA logic is provided at 100 MHz (clk_100). Since the interior clock of the original hamsterworks design works at 48 MHz (clkout0), clock domain crossing (CDC) is required.
-- The ADAU1761 chip is clocked by this design at 48MHz/2 = 24 MHz.
--
-- For packaging the design as IP code in Vivado disable audio_testbench.vhd in Vivado before packaging.
--
-- A testbench is provided (audio_testbench.vhd), which can be used as a
-- top level module for a reference design (two mode available: loopback and sawtooth generator).
-- See audio_testbench.vhd for more information.
--
--
-- Main differences to Hamsterwork's Design:
-- * ready to use as a standalone IP block: filters removed, switches removed, new top level file
-- * improved interface
-- * ported to Vivado
-- * clock generation simplified
-- * added testbench to test line in and headphone out
-- * improved documentation
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity audio_top is
Port ( clk_100 : in STD_LOGIC; -- 100 mhz input clock from top level logic
AC_MCLK : out STD_LOGIC; -- 24 Mhz for ADAU1761
AC_ADR0 : out STD_LOGIC; -- I2C contol signals to ADAU1761, for configuration
AC_ADR1 : out STD_LOGIC;
AC_SCK : out STD_LOGIC;
AC_SDA : inout STD_LOGIC;
AC_GPIO0 : out STD_LOGIC; -- I2S MISO
AC_GPIO1 : in STD_LOGIC; -- I2S MOSI
AC_GPIO2 : in STD_LOGIC; -- I2S_bclk
AC_GPIO3 : in STD_LOGIC; -- I2S_LR
hphone_l : in STD_LOGIC_VECTOR(23 downto 0); -- samples to head phone jack
hphone_l_valid : in std_logic;
hphone_r : in STD_LOGIC_VECTOR(23 downto 0);
hphone_r_valid_dummy : in std_logic; -- dummy valid signal to create AXIS interface in Vivado (r and l channel synchronous to hphone_l_valid
line_in_l : out STD_LOGIC_VECTOR(23 downto 0); -- samples from "line in" jack
line_in_r : out STD_LOGIC_VECTOR(23 downto 0);
new_sample : out STD_LOGIC; -- active for 1 clk cycle if new "line in" sample is tranmitted/received
sample_clk_48k : out std_logic -- sample clock (new sample at rising edge)
);
end audio_top;
architecture Behavioral of audio_top is
COMPONENT adau1761_izedboard
PORT(
clk_48 : IN std_logic;
AC_GPIO1 : IN std_logic;
AC_GPIO2 : IN std_logic;
AC_GPIO3 : IN std_logic;
hphone_l : IN std_logic_vector(23 downto 0);
hphone_r : IN std_logic_vector(23 downto 0);
AC_SDA : INOUT std_logic;
AC_ADR0 : OUT std_logic;
AC_ADR1 : OUT std_logic;
AC_GPIO0 : OUT std_logic;
AC_MCLK : OUT std_logic;
AC_SCK : OUT std_logic;
line_in_l : OUT std_logic_vector(23 downto 0);
line_in_r : OUT std_logic_vector(23 downto 0);
new_sample: out std_logic;
sw : in std_logic_vector(1 downto 0);
active : out std_logic_vector(1 downto 0)
);
END COMPONENT;
-- generates 48 MHz (internal) out of 100 MHz (external clock)
component clocking
port(
CLK_100 : in std_logic;
CLK_48 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
signal clk_48 : std_logic; -- this is the master clock (48Mhz) of the design
signal new_sample_100: std_logic; -- new_samples signal in the 100 MHz domain
signal line_in_l_freeze_48, line_in_r_freeze_48: STD_LOGIC_VECTOR(23 downto 0); -- "line in" signals from I2S receiver to external interface (are freezed by the I2S receiver)
signal sample_clk_48k_d1_48, sample_clk_48k_d2_48, sample_clk_48k_d3_48: std_logic; -- delay and synchronization registers for the sample clock (48k)
signal sample_clk_48k_d4_100, sample_clk_48k_d5_100, sample_clk_48k_d6_100 : std_logic;
signal hphone_l_freeze_100, hphone_r_freeze_100: STD_LOGIC_VECTOR(23 downto 0); -- for CDC 100 -> 48 Mhz freeze registers
signal hphone_valid : std_logic; -- internal signal for hphone_l_valid
begin
-- converts 100 mhz input into 48 mhz clk
i_clocking : clocking port map (
CLK_100 => clk_100,
CLK_48 => clk_48,
RESET => '0',
LOCKED => open
);
Inst_adau1761_izedboard: adau1761_izedboard PORT MAP(
clk_48 => clk_48,
AC_ADR0 => AC_ADR0,
AC_ADR1 => AC_ADR1,
AC_GPIO0 => AC_GPIO0,
AC_GPIO1 => AC_GPIO1,
AC_GPIO2 => AC_GPIO2,
AC_GPIO3 => AC_GPIO3,
AC_MCLK => AC_MCLK,
AC_SCK => AC_SCK,
AC_SDA => AC_SDA,
hphone_l => hphone_l_freeze_100,
hphone_r => hphone_r_freeze_100,
line_in_l => line_in_l_freeze_48,
line_in_r => line_in_r_freeze_48,
new_sample => open, -- new_sample is generated in the correct clock domain
sw => (others => '0'), -- all swichtes signals are tied to 0
active => open
);
hphone_valid <= hphone_l_valid; -- hphone_l_valid is "master" valid for hphone
------------------------------------------------------------------------------------------------
-- audio interface signal generation and clock domain crossing between 48 MHz and 100 MHz
-- 1) generation of new_sample and sample clock in the 100 MHZ domain
-- here: asynchonous input port AC_GPIO3 -> 48 MHz -> 100 MHz
-- 3 registers for input of L/R clock (sample clock) for synch and delay
process (clk_48)
begin
if (clk_48'event and clk_48 = '1') then
sample_clk_48k_d1_48 <= AC_GPIO3;
sample_clk_48k_d2_48 <= sample_clk_48k_d1_48;
sample_clk_48k_d3_48 <= sample_clk_48k_d2_48;
end if;
end process;
-- four registers for sample clk (synchronization and edge detection) in the 100 MHz domain
-- and generation of a new new_sample signal in the 100 MHz domain (new_sample_100)
process (clk_100)
begin
if (clk_100'event and clk_100 = '1') then
sample_clk_48k_d4_100 <= sample_clk_48k_d3_48; -- ff1 & 2 for synchronization
sample_clk_48k_d5_100 <= sample_clk_48k_d4_100;
sample_clk_48k_d6_100 <= sample_clk_48k_d5_100; -- ff3 for edge detection
sample_clk_48k <= sample_clk_48k_d6_100; -- additional FF for signal delay (alignment to data)
if (sample_clk_48k_d5_100 = '1' and sample_clk_48k_d6_100 = '0') then
new_sample_100 <= '1';
else
new_sample_100 <= '0';
end if;
new_sample <= new_sample_100; -- additional FF for signal delay (alignment to data)
end if;
end process;
-- 2) hphone audio data (l&r) CDC 100 MHz -> 48 MHz
-- freeze FF to keep data before CDC
process (clk_100)
begin
if (clk_100'event and clk_100 = '1') then
if (hphone_valid = '1') then
hphone_l_freeze_100 <= hphone_l;
hphone_r_freeze_100 <= hphone_r;
end if;
end if;
end process;
-- 3) line_in audio data: CDC 48 MHz -> 100 MHz
-- line_in_l/r_freeze is already freezed as designed in the I2S receiver (i2s_data_interface)
process (clk_100)
begin
if (clk_100'event and clk_100 = '1') then
if (new_sample_100 = '1') then
line_in_l <= line_in_l_freeze_48;
line_in_r <= line_in_r_freeze_48;
end if;
end if;
end process;
end Behavioral;
| lgpl-3.0 | 5a656030c71532117534691dfcbf1cf8 | 0.565877 | 3.673114 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/noc_controller.vhd | 1 | 8,821 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity noc_controller is
generic(
data_width : integer := 128;
addr_width : integer := 2;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- interface with hps
data_in : in std_logic_vector(data_width-1 downto 0);
data_out : out std_logic_vector(data_width-1 downto 0);
noc_ctrl : in std_logic_vector(31 downto 0);
noc_sts : out std_logic_vector(31 downto 0);
--network sending interface
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
--network receiving interface
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
--debugging
has_rxd : out std_logic;
tx_non_zero : out std_logic
);
end entity noc_controller;
architecture fsmd of noc_controller is
constant identifier_msb : integer := 7;
constant identifier_lsb : integer := 0;
constant num_data_regs : integer := 1;
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
type regs is array(num_data_regs-1 downto 0) of std_logic_vector(data_width-1 downto 0);
signal data_register_d, data_register_q : regs;
signal data_in_buffer_q, data_in_buffer_delay : std_logic_vector(num_vc-1 downto 0);
signal write_enable : std_logic;
signal selected_vc_q, selected_vc_d, selected_vc_encoder : std_logic_vector(vc_sel_width-1 downto 0);
signal identifier : std_logic_vector(7 downto 0);
signal id_select : std_logic_vector(7 downto 0);
signal has_rxd_d, has_rxd_q : std_logic;
signal send_flit_once_edge, send_flit_once_d, send_flit_once_q, send_flit_once_q2 : std_logic;
type send_states is (idle, send, waiting);
signal send_state, next_send_state : send_states;
type rx_states is (rx_idle, rx_addr_rst, rx_start_read, rx_sel_vc, rx_rxd, rx_wait_cpu, rx_dequeue, rx_wait_flits);
signal rx_state, next_rx_state : rx_states;
signal selected_vc_one_hot : std_logic_vector(1 downto 0);
signal state : std_logic_vector(3 downto 0);
signal cpu_read_ctrl : std_logic;
begin
---------------------------------------------------------------------------
-- Sending Controls -------------------------------------------------------
---------------------------------------------------------------------------
-- output logic
send_data <= data_in;
dest_addr <= noc_ctrl(addr_width-1 downto 0);
set_tail_flit <= noc_ctrl(8);
send_flit <= '1' when send_state = send else '0';
-- state register
process(clk, rst) begin
if rst = '1' then
send_state <= idle;
elsif rising_edge(clk) then
send_state <= next_send_state;
end if;
end process;
-- state transition logic
process(send_state, noc_ctrl(9)) begin
next_send_state <= send_state;
if send_state = idle and noc_ctrl(9) = '1' then
next_send_state <= send;
end if;
if send_state = send then
next_send_state <= waiting;
end if;
if send_state = waiting and noc_ctrl(9) = '0' then
next_send_state <= idle;
end if;
end process;
---------------------------------------------------------------------------
-- receive inteface controls ----------------------------------------------
---------------------------------------------------------------------------
--rx_idle, rx_sel_vc, rx_rxd, rx_wait_cpu, rx_dequeue, rx_wait_flits, rx_addr_rst, rx_start_read
--- output logic ---
dequeue <= "01" when selected_vc_q = "0" and rx_state = rx_dequeue else
"10" when selected_vc_q = "1" and rx_state = rx_dequeue else
"00";
selected_vc_one_hot <= "01" when selected_vc_q = "0" else
"10";
select_vc_read <= selected_vc_q;
state <= std_logic_vector(to_unsigned(0, 4)) when rx_state = rx_idle else
std_logic_vector(to_unsigned(1, 4)) when rx_state = rx_sel_vc else
std_logic_vector(to_unsigned(2, 4)) when rx_state = rx_addr_rst else
std_logic_vector(to_unsigned(3, 4)) when rx_state = rx_start_read else
std_logic_vector(to_unsigned(4, 4)) when rx_state = rx_rxd else
std_logic_vector(to_unsigned(5, 4)) when rx_state = rx_wait_cpu else
std_logic_vector(to_unsigned(6, 4)) when rx_state = rx_dequeue else
std_logic_vector(to_unsigned(7, 4)) when rx_state = rx_wait_flits else
std_logic_vector(to_unsigned(15, 4));
--- data path ---
-- data path registers
process(clk, rst) begin
if rst = '1' then
selected_vc_q <=(others => '0');
elsif rising_edge(clk) then
selected_vc_q <= selected_vc_d;
end if;
end process;
--data path components
u0: priority_encoder generic map(vc_sel_width)
port map(data_in_buffer, selected_vc_encoder);
-- data path logic
selected_vc_d <= selected_vc_encoder when rx_state = rx_sel_vc else selected_vc_q;
cpu_read_ctrl <= noc_ctrl(14);
--- FSM ---
-- state register
process(clk, rst) begin
if rst = '1' then
rx_state <= rx_idle;
elsif rising_edge(clk) then
rx_state <= next_rx_state;
end if;
end process;
--- state transition logic
--rx_idle, rx_sel_vc, rx_rxd, rx_wait_cpu, rx_dequeue, rx_wait_flits
process(rx_state, data_in_buffer, selected_vc_q) begin
next_rx_state <= rx_state;
if rx_state = rx_idle and or_reduce(data_in_buffer) = '1' then
next_rx_state <= rx_sel_vc;
end if;
if rx_state = rx_sel_vc then
next_rx_state <= rx_addr_rst;
end if;
if rx_state = rx_addr_rst and cpu_read_ctrl = '1' then
next_rx_state <= rx_start_read;
end if;
if rx_state = rx_start_read and cpu_read_ctrl = '0' then
next_rx_state <= rx_rxd;
end if;
if rx_state = rx_rxd and cpu_read_ctrl = '1' then
next_rx_state <= rx_wait_cpu;
end if;
if rx_state = rx_wait_cpu and cpu_read_ctrl = '0' then
next_rx_state <= rx_dequeue;
end if;
if rx_state = rx_dequeue and is_tail_flit = '1' then
next_rx_state <= rx_idle;
end if;
if rx_state = rx_dequeue and is_tail_flit = '0' then
next_rx_state <= rx_wait_flits;
end if;
if rx_state = rx_wait_flits and or_reduce(data_in_buffer and selected_vc_one_hot) = '1' then
next_rx_state <= rx_rxd;
end if;
end process;
---------------------------------------------------------------------------
-- User Rx Interface -----------------------------------------------------
---------------------------------------------------------------------------
id_select <= noc_ctrl(31 downto 24);
--data_out <= data_register_q(to_integer(unsigned(id_select)));
data_out <= recv_data;
noc_sts(24 + addr_width - 1 downto 24) <= src_addr;
noc_sts(23 downto 20) <= state;
noc_sts(0) <= not ready_to_send;
noc_sts(19 downto 1) <= (others => '0');
---------------------------------------------------------------------------
-- debug ------------------------------------------------------------------
---------------------------------------------------------------------------
has_rxd <= or_reduce(data_in_buffer); --has_rxd_q;
tx_non_zero <= or_reduce(recv_data);
end architecture fsmd;
| mit | 9b4d49f1a5116e2fb75f04aca6aa1695 | 0.504705 | 3.725084 | false | false | false | false |
boztalay/OldProjects | FPGA/LCD_Control/TestCPU1_OutPins_TB.vhd | 1 | 2,641 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:28:08 10/04/2009
-- Design Name:
-- Module Name: C:/Users/Ben/Desktop/Folders/FPGA/Projects/Current Projects/Systems/TestCPU1/TestCPU1_OutPins_TB.vhd
-- Project Name: TestCPU1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: TestCPU1_OutPins
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY TestCPU1_OutPins_TB IS
END TestCPU1_OutPins_TB;
ARCHITECTURE behavior OF TestCPU1_OutPins_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TestCPU1_OutPins
PORT(
clock : IN std_logic;
reset : IN std_logic;
act : IN std_logic;
data : IN std_logic_vector(15 downto 0);
output_pins : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal act : std_logic := '0';
signal data : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal output_pins : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TestCPU1_OutPins PORT MAP (
clock => clock,
reset => reset,
act => act,
data => data,
output_pins => output_pins
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 20 ns;
act <= '1';
data <= "0000000000100001";
wait for 10 ns;
data <= "0000000000101101";
wait for 10 ns;
data <= "0000000000001101";
wait for 10 ns;
reset <= '1';
wait;
end process;
END;
| mit | 1cb615607579bbaeb36d6b56101f5d9f | 0.573646 | 3.855474 | false | true | false | false |
bargei/NoC264 | NoC264_3x3/iqit_node.vhd | 1 | 13,015 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity iqit_node is
generic(
sample_width : integer := 8;
qp_width : integer := 8;
wo_dc_width : integer := 8;
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic
);
end entity iqit_node;
architecture fsmd of iqit_node is
--- COMPONENTS ------------------------------------------------------------
component zigzag is
generic(
sample_width : integer := 8
);
port(
x : in std_logic_vector((16*sample_width)-1 downto 0);
y : out std_logic_vector((16*sample_width)-1 downto 0)
);
end component zigzag;
component inverse_quant is
generic(
in_sample_width : integer := 8;
out_sample_width : integer := 16;
qp_width : integer := 8;
wo_dc_width : integer := 8
);
port(
quantized_samples : in std_logic_vector((16*in_sample_width)-1 downto 0);
quant_param : in std_logic_vector(qp_width-1 downto 0);
without_dc : in std_logic_vector(wo_dc_width-1 downto 0);
dequant_samples : out std_logic_vector((16*out_sample_width)-1 downto 0)
);
end component inverse_quant;
component inverse_transform is
generic(
in_sample_width : integer := 16;
out_sample_width : integer := 8
);
port(
transform_block : in std_logic_vector((16*in_sample_width)-1 downto 0);
inv_transform_block : out std_logic_vector((16*out_sample_width)-1 downto 0);
sign_mask : out std_logic_vector(15 downto 0)
);
end component inverse_transform;
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
--- TYPES -----------------------------------------------------------------
type iqit_states is (idle,
sel_vc,
rx_header,
dequeue_header,
wait_row_4_3,
rx_row_4_3,
dequeue_row_4_3,
wait_row_2_1,
rx_row_2_1,
dequeue_row_2_1,
wait_tx_header,
tx_header,
wait_tx_row_4_3,
tx_row_4_3,
wait_tx_row_2_1,
tx_row_2_1
);
--- SIGNALS ---------------------------------------------------------------
signal state : iqit_states;
signal next_state : iqit_states;
signal quant_param_d : std_logic_vector(qp_width-1 downto 0);
signal quant_param_q : std_logic_vector(qp_width-1 downto 0);
signal without_dc_d : std_logic_vector(wo_dc_width-1 downto 0);
signal without_dc_q : std_logic_vector(wo_dc_width-1 downto 0);
signal identifier_d : std_logic_vector(7 downto 0);
signal identifier_q : std_logic_vector(7 downto 0);
signal input_samples_d : std_logic_vector((16*sample_width)-1 downto 0);
signal input_samples_q : std_logic_vector((16*sample_width)-1 downto 0);
signal samples_after_zigzag : std_logic_vector((16*sample_width)-1 downto 0);
signal samples_after_inv_q : std_logic_vector((16*2*sample_width)-1 downto 0);
signal inv_t_input : std_logic_vector((16*2*sample_width)-1 downto 0);
signal result_samples : std_logic_vector((16*sample_width)-1 downto 0);
signal tx_header_data : std_logic_vector(data_width-1 downto 0);
signal tx_row_4_3_data : std_logic_vector(data_width-1 downto 0);
signal tx_row_2_1_data : std_logic_vector(data_width-1 downto 0);
signal sel_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_enc : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_one_hot : std_logic_vector(num_vc-1 downto 0);
signal dc_high_byte_q : std_logic_vector(7 downto 0);
signal dc_high_byte_d : std_logic_vector(7 downto 0);
signal sign_mask : std_logic_vector(15 downto 0);
signal x_pass_thru_d : std_logic_vector(10 downto 0);
signal y_pass_thru_d : std_logic_vector(10 downto 0);
signal LCbCr_pass_thru_d : std_logic_vector(1 downto 0);
signal x_pass_thru_q : std_logic_vector(10 downto 0);
signal y_pass_thru_q : std_logic_vector(10 downto 0);
signal LCbCr_pass_thru_q : std_logic_vector(1 downto 0);
constant do_iqit_cmd : std_logic_vector(7 downto 0) := x"03";
begin
--- DATAPATH --------------------------------------------------------------
u0: component zigzag
generic map(
sample_width => sample_width
)
port map(
x => input_samples_q,
y => samples_after_zigzag
);
u1: component inverse_quant
generic map(
in_sample_width => sample_width,
out_sample_width => 2*sample_width,
qp_width => qp_width,
wo_dc_width => wo_dc_width
)
port map(
quantized_samples => samples_after_zigzag,
quant_param => quant_param_q,
without_dc => without_dc_q,
dequant_samples => samples_after_inv_q
);
u2: component inverse_transform
generic map(
in_sample_width => 2*sample_width,
out_sample_width => sample_width
)
port map(
transform_block => inv_t_input,
inv_transform_block => result_samples,
sign_mask => sign_mask
);
u3: component priority_encoder
generic map(
encoded_word_size => vc_sel_width
)
Port map(
input => data_in_buffer,
output => sel_vc_enc
);
--register process
process(clk, rst) begin
if rst = '1' then
state <= idle;
quant_param_q <= (others => '0');
without_dc_q <= (others => '0');
identifier_q <= (others => '0');
input_samples_q <= (others => '0');
sel_vc_q <= (others => '0');
dc_high_byte_q <= (others => '0');
x_pass_thru_q <= (others => '0');
y_pass_thru_q <= (others => '0');
LCbCr_pass_thru_q <= (others => '0');
elsif rising_edge(clk) then
state <= next_state;
quant_param_q <= quant_param_d;
without_dc_q <= without_dc_d;
identifier_q <= identifier_d;
input_samples_q <= input_samples_d;
sel_vc_q <= sel_vc_d;
dc_high_byte_q <= dc_high_byte_d;
x_pass_thru_q <= x_pass_thru_d;
y_pass_thru_q <= y_pass_thru_d;
LCbCr_pass_thru_q <= LCbCr_pass_thru_d;
end if;
end process;
--insert high byte of dc into signal if non-zero
inv_t_input <= samples_after_inv_q(16*2*sample_width-1 downto sample_width*2) & dc_high_byte_q & samples_after_inv_q(sample_width-1 downto 0) when or_reduce(dc_high_byte_q) = '1' else
samples_after_inv_q;
--parse packet
quant_param_d <= recv_data(47 downto 40) when state = rx_header else quant_param_q;
without_dc_d <= recv_data(39 downto 32) when state = rx_header else without_dc_q;
identifier_d <= recv_data(7 downto 0) when state = rx_header else identifier_q;
dc_high_byte_d <= recv_data(55 downto 48) when state = rx_header else dc_high_byte_q;
x_pass_thru_d <= recv_data(18 downto 8) when state = rx_header else x_pass_thru_q;
y_pass_thru_d <= recv_data(29 downto 19) when state = rx_header else y_pass_thru_q;
LCbCr_pass_thru_d <= recv_data(31 downto 30) when state = rx_header else LCbCr_pass_thru_q;
input_samples_d((16*sample_width)-1 downto (8*sample_width)) <= recv_data when state = rx_row_4_3 else
input_samples_q((16*sample_width)-1 downto (8*sample_width));
input_samples_d((8*sample_width)-1 downto 0) <= recv_data when state = rx_row_2_1 else
input_samples_q((8*sample_width)-1 downto 0);
-- format repsonse packet
tx_header_data <= x_pass_thru_q & "00000" &sign_mask& "000" & LCbCr_pass_thru_q & y_pass_thru_q &do_iqit_cmd&identifier_q;
tx_row_4_3_data <= result_samples((16*sample_width)-1 downto (8*sample_width));
tx_row_2_1_data <= result_samples((8*sample_width)-1 downto 0) ;
-- channel selection logic
sel_vc_d <= sel_vc_enc when state = sel_vc else sel_vc_q;
--rx controls
dequeue <= sel_vc_one_hot when state = dequeue_header or state = dequeue_row_4_3 or state = dequeue_row_2_1 else "00";
select_vc_read <= sel_vc_q;
sel_vc_one_hot <= "01" when sel_vc_q = "0" else "10";
--packet generation
send_data <= tx_header_data when state = wait_tx_header or state = tx_header else
tx_row_4_3_data when state = wait_tx_row_4_3 or state = tx_row_4_3 else
tx_row_2_1_data when state = wait_tx_row_2_1 or state = tx_row_2_1 else
std_logic_vector(to_unsigned(0, data_width));
dest_addr <= std_logic_vector(to_unsigned(7, addr_width));
set_tail_flit <= '1' when state = wait_row_2_1 or state = tx_row_2_1 else '0';
send_flit <= '1' when state = tx_header or state = tx_row_4_3 or state = tx_row_2_1 else '0';
-- STATE MACHINE ----------------------------------------------------------
process(state, data_in_buffer, is_tail_flit, sel_vc_one_hot, ready_to_send)
begin
next_state <= state; --default behaviour
if state = idle and or_reduce(data_in_buffer) = '1' then
next_state <= sel_vc;
end if;
if state = sel_vc then
next_state <= rx_header;
end if;
if state = rx_header then
next_state <= dequeue_header;
end if;
if state = dequeue_header then
next_state <= wait_row_4_3;
end if;
if state = wait_row_4_3 and or_reduce(sel_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx_row_4_3;
end if;
if state = rx_row_4_3 then
next_state <= dequeue_row_4_3;
end if;
if state = dequeue_row_4_3 then
next_state <= wait_row_2_1;
end if;
if state = wait_row_2_1 and or_reduce(sel_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx_row_2_1;
end if;
if state = rx_row_2_1 then
next_state <= dequeue_row_2_1;
end if;
if state = dequeue_row_2_1 then
next_state <= wait_tx_header;
end if;
if state = wait_tx_header and ready_to_send = '1' then
next_state <= tx_header;
end if;
if state = tx_header then
next_state <= wait_tx_row_4_3;
end if;
if state = wait_tx_row_4_3 and ready_to_send = '1' then
next_state <= tx_row_4_3;
end if;
if state = tx_row_4_3 then
next_state <= wait_tx_row_2_1;
end if;
if state = wait_tx_row_2_1 and ready_to_send = '1' then
next_state <= tx_row_2_1;
end if;
if state = tx_row_2_1 then
next_state <= idle;
end if;
end process;
end architecture fsmd; | mit | 8e8dc9915ddb8f3bca9109881158ff58 | 0.521322 | 3.50148 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/ram_dual.vhd | 1 | 1,571 | --source code below originally from:
-- http://quartushelp.altera.com/14.1/mergedprojects/hdl/vhdl/vhdl_pro_ram_inferred.htm
--
-- modified to use generics
-- should produce infered ram
library ieee;
use ieee.std_logic_1164.all;
--package ram_package is
-- constant ram_width : integer := 4;
-- constant ram_depth : integer := 1024;
--
-- type word is array(0 to ram_width - 1) of std_logic;
-- type ram is array(0 to ram_depth - 1) of word;
-- subtype address_vector is integer range 0 to ram_depth - 1;
--
--end ram_package;
library ieee;
use ieee.std_logic_1164.all;
--use work.ram_package.all;
entity ram_dual is
generic
(
ram_width : integer := 24;
ram_depth : integer := 65536
);
port
(
clock1 : in std_logic;
clock2 : in std_logic;
data : in std_logic_vector(ram_width-1 downto 0);
write_address : in integer;
read_address : in integer;
we : in std_logic;
q : out std_logic_vector(ram_width-1 downto 0)
);
end ram_dual;
architecture rtl of ram_dual is
type ram is array(0 to ram_depth - 1) of std_logic_vector(ram_width-1 downto 0);
signal ram_block : ram;
begin
process (clock1)
begin
if (clock1'event and clock1 = '1') then
if (we = '1') then
ram_block(write_address) <= data;
end if;
end if;
end process;
process (clock2)
begin
if (clock2'event and clock2 = '1') then
q <= ram_block(read_address);
end if;
end process;
end rtl; | mit | 5618ce31a19fc5c2cfd90ab64963932f | 0.600891 | 3.193089 | false | false | false | false |
boztalay/OldProjects | FPGA/FlashProgrammer/GenReg.vhd | 2 | 1,481 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:58:50 10/27/2009
-- Design Name:
-- Module Name: GenReg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.90 - File written and syntax checked. No simulation necessary
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity GenReg is
generic (size: integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ((size - 1) downto 0);
output : out STD_LOGIC_VECTOR ((size - 1) downto 0));
end GenReg;
architecture Behavioral of GenReg is
begin
main: process (clock, reset) is
variable data_reg : STD_LOGIC_VECTOR((size - 1) downto 0);
begin
if rising_edge(clock) then
if reset = '1' then
data_reg := (others => '0');
elsif enable = '1' then
data_reg := data;
end if;
end if;
output <= data_reg;
end process;
end Behavioral;
| mit | 97476ef33db449bad5f370213ad6f65a | 0.557731 | 3.665842 | false | false | false | false |
fkolacek/FIT-VUT | INP1/fpga/ledc8x8.vhd | 1 | 2,142 | --- Projekt: INP 1 - Maticovy displej
--- Autor: Frantisek Kolacek ([email protected])
--- Datum: 28. 10. 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- Definice rozhrani pro praci s maticovym displejem
entity ledc8x8 is
port (
SMCLK: in std_logic;
RESET: in std_logic;
ROW: out std_logic_vector(0 to 7);
LED: out std_logic_vector(0 to 7)
);
end ledc8x8;
--- Definice architektury
architecture behav of ledc8x8 is
--- Signal pro novy clock
signal customCLK: std_logic;
--- Registr pro uchovani hodnoty citace
signal customReg: std_logic_vector(7 downto 0);
--- Registr pro adresaci radku
signal customRow: std_logic_vector(7 downto 0);
begin
--- Proces pro vytvoreni vlastniho clock
process(SMCLK, RESET, customCLK, customReg)
begin
if RESET = '1' then
customReg <= (others => '0');
elsif SMCLK'event and SMCLK = '1' then
customReg <= customReg + 1;
end if;
customCLK <= customReg(7);
end process;
--- Proces pro obsluhu kruhoveho registru pracujiciho s nabeznou hranou
process(customCLK, RESET)
begin
if RESET = '1' then
customRow <= "01111111";
elsif customCLK'event AND customCLK = '1' then
customRow <= customRow(0) & customRow(7 downto 1);
end if;
end process;
--- Switch (dekoder) signalu pro rozsveceni diod
process(customRow)
begin
case customRow is
when "01111111" => LED <= "11110000";
when "10111111" => LED <= "10000000";
when "11011111" => LED <= "11100000";
when "11101111" => LED <= "10001001";
when "11110111" => LED <= "10001010";
when "11111011" => LED <= "10001100";
when "11111101" => LED <= "00001010";
when "11111110" => LED <= "00001001";
when others => LED <= "00000000";
end case;
end process;
ROW <= customRow;
end behav;
| apache-2.0 | 369a4fec9b5bf390351ac6eb4bec50f5 | 0.57563 | 3.56406 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/inter_core_reg_file.vhd | 1 | 3,705 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity inter_core_reg_file is
generic(
size_x : integer := 20;
size_y : integer := 20;
interp_x : integer := 1;
interp_y : integer := 1;
sample_size : integer := 4;
samples_per_wr : integer := 1
);
port(
clk : in std_logic;
rst : in std_logic;
--read interface
rd_addr_x : in std_logic_vector(7 downto 0);
rd_addr_y : in std_logic_vector(7 downto 0);
rd_samples : out std_logic_vector((interp_x+5)*(interp_y+5)*sample_size-1 downto 0);
--write interface
wr_addr_x : in std_logic_vector(7 downto 0);
wr_addr_y : in std_logic_vector(7 downto 0);
wr_enable : in std_logic;
wr_samples : in std_logic_vector(samples_per_wr*sample_size-1 downto 0)
);
end entity inter_core_reg_file;
architecture rtl of inter_core_reg_file is
signal register_bits_d : std_logic_vector(size_x*size_y*sample_size-1 downto 0);
signal register_bits_q : std_logic_vector(size_x*size_y*sample_size-1 downto 0);
signal offset : natural;
signal rd_addr_x_int : integer;
signal rd_addr_y_int : integer;
begin
--register process
process(clk, rst)
begin
if rst = '1' then
register_bits_q <= (others => '0');
elsif rising_edge(clk) then
register_bits_q <= register_bits_d;
end if;
end process;
--register update logic
assert ((size_x*size_y) mod samples_per_wr) = 0 report "bad samples_per_wr" severity error;
g0: for n in ((size_x*size_y)/samples_per_wr)-1 downto 0 generate
constant x_location : integer := n mod (size_x/samples_per_wr);
constant y_location : integer := n / (size_x/samples_per_wr);
constant vector_index_low : integer := n * sample_size * samples_per_wr;
constant vector_index_high : integer := vector_index_low + sample_size * samples_per_wr - 1;
begin
register_bits_d(vector_index_high downto vector_index_low) <=
(others => '0') when rst = '1' else
wr_samples
when to_integer(unsigned(wr_addr_x)) = x_location
and to_integer(unsigned(wr_addr_y)) = y_location
and wr_enable = '1' else
register_bits_q(vector_index_high downto vector_index_low);
end generate;
--read logic
assert ((size_x - 4) mod interp_x) = 0 report "size_x/interp_x conflict" severity warning;
assert ((size_y - 4) mod interp_y) = 0 report "size_y/interp_y conflict" severity warning;
rd_addr_x_int <= to_integer(signed(rd_addr_x));
rd_addr_y_int <= to_integer(signed(rd_addr_y));
offset <= 256 when rd_addr_y_int = 4 else 0;
g1: for n in (interp_y+5)-1 downto 0 generate
--indexes into the result vector
constant bits_per_row : integer := (interp_x+5) * sample_size;
constant rd_samples_low : integer := n * bits_per_row;
constant rd_samples_high : integer := rd_samples_low + bits_per_row - 1;
--indexes relative to offset of read data
constant rel_lin_addr : integer := n * size_x * sample_size;
begin
rd_samples(rd_samples_high downto rd_samples_low) <= register_bits_q(offset + rel_lin_addr + bits_per_row -1
downto offset + rel_lin_addr);
end generate;
end architecture rtl; | mit | 002ec914f30e85290434f68434979c9f | 0.568961 | 3.462617 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/HPSFPGA.vhd | 2 | 67,625 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
ENTITY HPSFPGA IS
PORT(
---------fpga connections-------------
clock_50: in std_logic;
sw:in std_logic_vector(9 downto 0);
ledr: out std_logic_vector(9 downto 0);
---------hps connections---------------
hps_conv_usb_n:inout std_logic;
hps_ddr3_addr:out std_logic_vector(14 downto 0);
hps_ddr3_ba: out std_logic_vector(2 downto 0);
hps_ddr3_cas_n: out std_logic;
hps_ddr3_cke:out std_logic;
hps_ddr3_ck_n: out std_logic;
hps_ddr3_ck_p: out std_logic;
hps_ddr3_cs_n: out std_logic;
hps_ddr3_dm: out std_logic_vector(3 downto 0);
hps_ddr3_dq: inout std_logic_vector(31 downto 0);
hps_ddr3_dqs_n: inout std_logic_vector(3 downto 0);
hps_ddr3_dqs_p: inout std_logic_vector(3 downto 0);
hps_ddr3_odt: out std_logic;
hps_ddr3_ras_n: out std_logic;
hps_ddr3_reset_n: out std_logic;
hps_ddr3_rzq: in std_logic;
hps_ddr3_we_n: out std_logic;
hps_enet_gtx_clk: out std_logic;
hps_enet_int_n:inout std_logic;
hps_enet_mdc:out std_logic;
hps_enet_mdio:inout std_logic;
hps_enet_rx_clk: in std_logic;
hps_enet_rx_data: in std_logic_vector(3 downto 0);
hps_enet_rx_dv: in std_logic;
hps_enet_tx_data: out std_logic_vector(3 downto 0);
hps_enet_tx_en: out std_logic;
hps_key: inout std_logic;
hps_sd_clk: out std_logic;
hps_sd_cmd: inout std_logic;
hps_sd_data: inout std_logic_vector(3 downto 0);
hps_uart_rx: in std_logic;
hps_uart_tx: out std_logic;
hps_usb_clkout: in std_logic;
hps_usb_data:inout std_logic_vector(7 downto 0);
hps_usb_dir: in std_logic;
hps_usb_nxt: in std_logic;
hps_usb_stp: out std_logic
);
END HPSFPGA;
ARCHITECTURE MAIN OF HPSFPGA IS
-- constants
constant data_width : integer := 64;
constant addr_width : integer := 4;
constant vc_sel_width : integer := 1;
constant num_vc : integer := 2;
constant flit_buff_depth : integer := 8;
component hps_fpga is
port (
clk_clk : in std_logic := 'X'; -- clk
hps_0_h2f_reset_reset_n : out std_logic; -- reset_n
hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
flit_rx_2_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
led_external_connection_export : out std_logic_vector(9 downto 0); -- export
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
flit_word_0_export : out std_logic_vector(31 downto 0); -- export
flit_rx_0_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
flit_word_2_export : out std_logic_vector(31 downto 0); -- export
flit_word_1_export : out std_logic_vector(31 downto 0); -- export
flit_rx_1_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
sw_external_connection_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
flit_word_3_export : out std_logic_vector(31 downto 0); -- export
flit_rx_3_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
noc_ctrl_export : out std_logic_vector(31 downto 0);
noc_status_export : in std_logic_vector(31 downto 0)
);
end component hps_fpga;
component intra_prediction_node is
generic (
data_width : integer := 128;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
--debugging
s_intra_idle : out std_logic;
s_intra_data_rxd : out std_logic;
s_intra_write_sample : out std_logic;
s_intra_start_pred : out std_logic;
s_intra_start_tx_loop : out std_logic;
s_intra_start_tx_loop_hold : out std_logic;
s_intra_tx : out std_logic;
s_intra_tx_hold : out std_logic;
s_intra_tx_gen_next : out std_logic;
s_intra_dequeue_rx : out std_logic
);
end component intra_prediction_node;
component network_interface is
generic(
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
--clk, reset
clk : in std_logic;
rst : in std_logic;
--user sending interface
send_data : in std_logic_vector(data_width-1 downto 0);
dest_addr : in std_logic_vector(addr_width-1 downto 0);
set_tail_flit : in std_logic;
send_flit : in std_logic;
ready_to_send : out std_logic;
--user receiving interface
recv_data : out std_logic_vector(data_width-1 downto 0);
src_addr : out std_logic_vector(addr_width-1 downto 0);
is_tail_flit : out std_logic;
data_in_buffer : out std_logic_vector(num_vc-1 downto 0);
dequeue : in std_logic_vector(num_vc-1 downto 0);
select_vc_read : in std_logic_vector(vc_sel_width-1 downto 0);
--interface to network
send_putFlit_flit_in : out std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
EN_send_putFlit : out std_logic;
EN_send_getNonFullVCs : out std_logic;
send_getNonFullVCs : in std_logic_vector(num_vc-1 downto 0);
EN_recv_getFlit : out std_logic;
recv_getFlit : in std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
recv_putNonFullVCs_nonFullVCs : out std_logic_vector(num_vc-1 downto 0);
EN_recv_putNonFullVCs : out std_logic;
recv_info_getRecvPortID : in std_logic_vector(addr_width-1 downto 0)
);
end component network_interface;
component mkNetworkSimple is
port(
CLK : in std_logic;
RST_N : in std_logic;
send_ports_0_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_0_putFlit : in std_logic;
EN_send_ports_0_getNonFullVCs : in std_logic;
send_ports_0_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_1_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_1_putFlit : in std_logic;
EN_send_ports_1_getNonFullVCs : in std_logic;
send_ports_1_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_2_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_2_putFlit : in std_logic;
EN_send_ports_2_getNonFullVCs : in std_logic;
send_ports_2_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_3_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_3_putFlit : in std_logic;
EN_send_ports_3_getNonFullVCs : in std_logic;
send_ports_3_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_4_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_4_putFlit : in std_logic;
EN_send_ports_4_getNonFullVCs : in std_logic;
send_ports_4_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_5_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_5_putFlit : in std_logic;
EN_send_ports_5_getNonFullVCs : in std_logic;
send_ports_5_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_6_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_6_putFlit : in std_logic;
EN_send_ports_6_getNonFullVCs : in std_logic;
send_ports_6_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_7_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_7_putFlit : in std_logic;
EN_send_ports_7_getNonFullVCs : in std_logic;
send_ports_7_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_8_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_8_putFlit : in std_logic;
EN_send_ports_8_getNonFullVCs : in std_logic;
send_ports_8_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_9_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_9_putFlit : in std_logic;
EN_send_ports_9_getNonFullVCs : in std_logic;
send_ports_9_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_10_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_10_putFlit : in std_logic;
EN_send_ports_10_getNonFullVCs : in std_logic;
send_ports_10_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_11_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_11_putFlit : in std_logic;
EN_send_ports_11_getNonFullVCs : in std_logic;
send_ports_11_getNonFullVCs : out std_logic_vector(1 downto 0);
EN_recv_ports_0_getFlit : in std_logic;
recv_ports_0_getFlit : out std_logic_vector(70 downto 0);
recv_ports_0_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_0_putNonFullVCs : in std_logic;
EN_recv_ports_1_getFlit : in std_logic;
recv_ports_1_getFlit : out std_logic_vector(70 downto 0);
recv_ports_1_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_1_putNonFullVCs : in std_logic;
EN_recv_ports_2_getFlit : in std_logic;
recv_ports_2_getFlit : out std_logic_vector(70 downto 0);
recv_ports_2_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_2_putNonFullVCs : in std_logic;
EN_recv_ports_3_getFlit : in std_logic;
recv_ports_3_getFlit : out std_logic_vector(70 downto 0);
recv_ports_3_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_3_putNonFullVCs : in std_logic;
EN_recv_ports_4_getFlit : in std_logic;
recv_ports_4_getFlit : out std_logic_vector(70 downto 0);
recv_ports_4_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_4_putNonFullVCs : in std_logic;
EN_recv_ports_5_getFlit : in std_logic;
recv_ports_5_getFlit : out std_logic_vector(70 downto 0);
recv_ports_5_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_5_putNonFullVCs : in std_logic;
EN_recv_ports_6_getFlit : in std_logic;
recv_ports_6_getFlit : out std_logic_vector(70 downto 0);
recv_ports_6_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_6_putNonFullVCs : in std_logic;
EN_recv_ports_7_getFlit : in std_logic;
recv_ports_7_getFlit : out std_logic_vector(70 downto 0);
recv_ports_7_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_7_putNonFullVCs : in std_logic;
EN_recv_ports_8_getFlit : in std_logic;
recv_ports_8_getFlit : out std_logic_vector(70 downto 0);
recv_ports_8_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_8_putNonFullVCs : in std_logic;
EN_recv_ports_9_getFlit : in std_logic;
recv_ports_9_getFlit : out std_logic_vector(70 downto 0);
recv_ports_9_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_9_putNonFullVCs : in std_logic;
EN_recv_ports_10_getFlit : in std_logic;
recv_ports_10_getFlit : out std_logic_vector(70 downto 0);
recv_ports_10_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_10_putNonFullVCs : in std_logic;
EN_recv_ports_11_getFlit : in std_logic;
recv_ports_11_getFlit : out std_logic_vector(70 downto 0);
recv_ports_11_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_11_putNonFullVCs : in std_logic;
recv_ports_info_0_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_1_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_2_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_3_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_4_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_5_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_6_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_7_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_8_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_9_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_10_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_11_getRecvPortID : out std_logic_vector(3 downto 0)
);
end component mkNetworkSimple;
component deblocking_filter_node is
generic (
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
has_rxd : out std_logic;
is_idle : out std_logic;
is_filtering : out std_logic;
is_tx_ing : out std_logic;
is_cleanup_ing : out std_logic;
rx_non_zero : out std_logic;
tx_non_zero : out std_logic
);
end component deblocking_filter_node;
component noc_controller is
generic(
data_width : integer := 128;
addr_width : integer := 2;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- interface with hps
data_in : in std_logic_vector(data_width-1 downto 0);
data_out : out std_logic_vector(data_width-1 downto 0);
noc_ctrl : in std_logic_vector(31 downto 0);
noc_sts : out std_logic_vector(31 downto 0);
--network sending interface
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
--network receiving interface
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
--debugging
has_rxd : out std_logic;
tx_non_zero : out std_logic
);
end component noc_controller;
component inter_node is
generic(
size_x : integer := 12; --20 ; --12; --20 --20
size_y : integer := 12; --20 ; --12; --20 --20
interp_x : integer := 8; --4 ; --8; --2 --4
interp_y : integer := 2; --4 ; --1; --2 --4
sample_size : integer := 8; --8 ; --8;
samples_per_wr : integer := 16; --16 ; --8; --4 --16
data_width : integer := 128;--128 ; --64; --32 --128
addr_width : integer := 1; --1 ; --1;
vc_sel_width : integer := 1; --1 ; --1;
num_vc : integer := 2; --2 ; --2;
flit_buff_depth : integer := 8 --8 --8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic
);
end component inter_node;
signal hps_h2f_rst : std_logic;
signal flit_word_0_export : std_logic_vector(31 downto 0);
signal flit_rx_0_export : std_logic_vector(31 downto 0);
signal flit_word_2_export : std_logic_vector(31 downto 0);
signal flit_rx_2_export : std_logic_vector(31 downto 0);
signal flit_word_1_export : std_logic_vector(31 downto 0);
signal flit_rx_1_export : std_logic_vector(31 downto 0);
signal flit_word_3_export : std_logic_vector(31 downto 0);
signal flit_rx_3_export : std_logic_vector(31 downto 0);
signal send_ports_0_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_0_putFlit : std_logic;
signal EN_send_ports_0_getNonFullVCs : std_logic;
signal send_ports_0_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_1_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_1_putFlit : std_logic;
signal EN_send_ports_1_getNonFullVCs : std_logic;
signal send_ports_1_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_2_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_2_putFlit : std_logic;
signal EN_send_ports_2_getNonFullVCs : std_logic;
signal send_ports_2_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_3_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_3_putFlit : std_logic;
signal EN_send_ports_3_getNonFullVCs : std_logic;
signal send_ports_3_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_4_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_4_putFlit : std_logic;
signal EN_send_ports_4_getNonFullVCs : std_logic;
signal send_ports_4_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_5_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_5_putFlit : std_logic;
signal EN_send_ports_5_getNonFullVCs : std_logic;
signal send_ports_5_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_6_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_6_putFlit : std_logic;
signal EN_send_ports_6_getNonFullVCs : std_logic;
signal send_ports_6_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_7_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_7_putFlit : std_logic;
signal EN_send_ports_7_getNonFullVCs : std_logic;
signal send_ports_7_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_8_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_8_putFlit : std_logic;
signal EN_send_ports_8_getNonFullVCs : std_logic;
signal send_ports_8_getNonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_0_getFlit : std_logic;
signal recv_ports_0_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_0_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_0_putNonFullVCs : std_logic;
signal EN_recv_ports_1_getFlit : std_logic;
signal recv_ports_1_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_1_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_1_putNonFullVCs : std_logic;
signal EN_recv_ports_2_getFlit : std_logic;
signal recv_ports_2_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_2_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_2_putNonFullVCs : std_logic;
signal EN_recv_ports_3_getFlit : std_logic;
signal recv_ports_3_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_3_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_3_putNonFullVCs : std_logic;
signal EN_recv_ports_4_getFlit : std_logic;
signal recv_ports_4_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_4_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_4_putNonFullVCs : std_logic;
signal EN_recv_ports_5_getFlit : std_logic;
signal recv_ports_5_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_5_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_5_putNonFullVCs : std_logic;
signal EN_recv_ports_6_getFlit : std_logic;
signal recv_ports_6_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_6_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_6_putNonFullVCs : std_logic;
signal EN_recv_ports_7_getFlit : std_logic;
signal recv_ports_7_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_7_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_7_putNonFullVCs : std_logic;
signal EN_recv_ports_8_getFlit : std_logic;
signal recv_ports_8_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_8_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_8_putNonFullVCs : std_logic;
signal recv_ports_info_0_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_1_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_2_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_3_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_4_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_5_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_6_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_7_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_8_getRecvPortID : std_logic_vector(3 downto 0);
signal send_ports_9_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_9_putFlit : std_logic;
signal EN_send_ports_9_getNonFullVCs : std_logic;
signal send_ports_9_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_10_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_10_putFlit : std_logic;
signal EN_send_ports_10_getNonFullVCs : std_logic;
signal send_ports_10_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_11_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_11_putFlit : std_logic;
signal EN_send_ports_11_getNonFullVCs : std_logic;
signal send_ports_11_getNonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_9_getFlit : std_logic;
signal recv_ports_9_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_9_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_9_putNonFullVCs : std_logic;
signal EN_recv_ports_10_getFlit : std_logic;
signal recv_ports_10_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_10_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_10_putNonFullVCs : std_logic;
signal EN_recv_ports_11_getFlit : std_logic;
signal recv_ports_11_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_11_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_11_putNonFullVCs : std_logic;
signal recv_ports_info_9_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_10_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_11_getRecvPortID : std_logic_vector(3 downto 0);
signal send_data_pe0 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe0 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe0 : std_logic;
signal send_flit_pe0 : std_logic;
signal ready_to_send_pe0 : std_logic;
signal recv_data_pe0 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe0 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe0 : std_logic;
signal data_in_buffer_pe0 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe0 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe0 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe1 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe1 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe1 : std_logic;
signal send_flit_pe1 : std_logic;
signal ready_to_send_pe1 : std_logic;
signal recv_data_pe1 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe1 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe1 : std_logic;
signal data_in_buffer_pe1 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe1 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe1 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe2 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe2 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe2 : std_logic;
signal send_flit_pe2 : std_logic;
signal ready_to_send_pe2 : std_logic;
signal recv_data_pe2 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe2 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe2 : std_logic;
signal data_in_buffer_pe2 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe2 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe2 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe3 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe3 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe3 : std_logic;
signal send_flit_pe3 : std_logic;
signal ready_to_send_pe3 : std_logic;
signal recv_data_pe3 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe3 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe3 : std_logic;
signal data_in_buffer_pe3 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe3 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe3 : std_logic_vector(vc_sel_width-1 downto 0);
signal noc_rst : std_logic;
signal noc_ctrl_export : std_logic_vector(31 downto 0);
signal noc_status_export : std_logic_vector(31 downto 0);
signal data_out : std_logic_vector(data_width-1 downto 0);
signal LEDR_NOPE : std_logic_vector(9 downto 0);
signal is_idle : std_logic_vector(2 downto 0);
signal is_filtering : std_logic_vector(2 downto 0);
signal is_tx_ing : std_logic_vector(2 downto 0);
signal is_cleanup_ing : std_logic_vector(2 downto 0);
BEGIN
u0 : component hps_fpga
port map (
clk_clk => CLOCK_50, -- clk.clk
reset_reset_n => '1', -- reset.reset_n
memory_mem_a => HPS_DDR3_ADDR, -- memory.mem_a
memory_mem_ba => HPS_DDR3_BA, -- .mem_ba
memory_mem_ck => HPS_DDR3_CK_P, -- .mem_ck
memory_mem_ck_n => HPS_DDR3_CK_N, -- .mem_ck_n
memory_mem_cke => HPS_DDR3_CKE, -- .mem_cke
memory_mem_cs_n => HPS_DDR3_CS_N, -- .mem_cs_n
memory_mem_ras_n => HPS_DDR3_RAS_N, -- .mem_ras_n
memory_mem_cas_n => HPS_DDR3_CAS_N, -- .mem_cas_n
memory_mem_we_n => HPS_DDR3_WE_N, -- .mem_we_n
memory_mem_reset_n => HPS_DDR3_RESET_N, -- .mem_reset_n
memory_mem_dq => HPS_DDR3_DQ, -- .mem_dq
memory_mem_dqs => HPS_DDR3_DQS_P, -- .mem_dqs
memory_mem_dqs_n => HPS_DDR3_DQS_N, -- .mem_dqs_n
memory_mem_odt => HPS_DDR3_ODT, -- .mem_odt
memory_mem_dm => HPS_DDR3_DM, -- .mem_dm
memory_oct_rzqin => HPS_DDR3_RZQ, -- .oct_rzqin
hps_0_h2f_reset_reset_n => HPS_H2F_RST, -- hps_0_h2f_reset.reset_n
led_external_connection_export => LEDR_NOPE, -- led_external_connection.export
sw_external_connection_export => SW, -- sw_external_connection.export
hps_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK, -- hps_io.hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0), -- .hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1), -- .hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2), -- .hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3), -- .hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0), -- .hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO, -- .hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC, -- .hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV, -- .hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN, -- .hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1), -- .hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2), -- .hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3), -- .hps_io_emac1_inst_RXD3
hps_io_hps_io_sdio_inst_CMD => HPS_SD_CMD, -- .hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0), -- .hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1), -- .hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK => HPS_SD_CLK, -- .hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2), -- .hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3), -- .hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0), -- .hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1), -- .hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2), -- .hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3), -- .hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4), -- .hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5), -- .hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6), -- .hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7), -- .hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT, -- .hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP => HPS_USB_STP, -- .hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR => HPS_USB_DIR, -- .hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT => HPS_USB_NXT, -- .hps_io_usb1_inst_NXT
hps_io_hps_io_uart0_inst_RX => HPS_UART_RX, -- .hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX => HPS_UART_TX, -- .hps_io_uart0_inst_TX
flit_word_0_export => flit_word_0_export,
flit_rx_0_export => flit_rx_0_export ,
flit_word_2_export => flit_word_2_export,
flit_rx_2_export => flit_rx_2_export ,
flit_word_1_export => flit_word_1_export,
flit_rx_1_export => flit_rx_1_export ,
flit_word_3_export => flit_word_3_export,
flit_rx_3_export => flit_rx_3_export ,
noc_ctrl_export => noc_ctrl_export ,
noc_status_export => noc_status_export
);
u1 : component mkNetworkSimple
port map(
CLK => CLOCK_50 ,
RST_N => not noc_rst ,
send_ports_0_putFlit_flit_in => send_ports_0_putFlit_flit_in ,
EN_send_ports_0_putFlit => EN_send_ports_0_putFlit ,
EN_send_ports_0_getNonFullVCs => EN_send_ports_0_getNonFullVCs ,
send_ports_0_getNonFullVCs => send_ports_0_getNonFullVCs ,
send_ports_1_putFlit_flit_in => send_ports_1_putFlit_flit_in ,
EN_send_ports_1_putFlit => EN_send_ports_1_putFlit ,
EN_send_ports_1_getNonFullVCs => EN_send_ports_1_getNonFullVCs ,
send_ports_1_getNonFullVCs => send_ports_1_getNonFullVCs ,
send_ports_2_putFlit_flit_in => send_ports_2_putFlit_flit_in ,
EN_send_ports_2_putFlit => EN_send_ports_2_putFlit ,
EN_send_ports_2_getNonFullVCs => EN_send_ports_2_getNonFullVCs ,
send_ports_2_getNonFullVCs => send_ports_2_getNonFullVCs ,
send_ports_3_putFlit_flit_in => send_ports_3_putFlit_flit_in ,
EN_send_ports_3_putFlit => EN_send_ports_3_putFlit ,
EN_send_ports_3_getNonFullVCs => EN_send_ports_3_getNonFullVCs ,
send_ports_3_getNonFullVCs => send_ports_3_getNonFullVCs ,
send_ports_4_putFlit_flit_in => send_ports_4_putFlit_flit_in ,
EN_send_ports_4_putFlit => EN_send_ports_4_putFlit ,
EN_send_ports_4_getNonFullVCs => EN_send_ports_4_getNonFullVCs ,
send_ports_4_getNonFullVCs => send_ports_4_getNonFullVCs ,
send_ports_5_putFlit_flit_in => send_ports_5_putFlit_flit_in ,
EN_send_ports_5_putFlit => EN_send_ports_5_putFlit ,
EN_send_ports_5_getNonFullVCs => EN_send_ports_5_getNonFullVCs ,
send_ports_5_getNonFullVCs => send_ports_5_getNonFullVCs ,
send_ports_6_putFlit_flit_in => send_ports_6_putFlit_flit_in ,
EN_send_ports_6_putFlit => EN_send_ports_6_putFlit ,
EN_send_ports_6_getNonFullVCs => EN_send_ports_6_getNonFullVCs ,
send_ports_6_getNonFullVCs => send_ports_6_getNonFullVCs ,
send_ports_7_putFlit_flit_in => send_ports_7_putFlit_flit_in ,
EN_send_ports_7_putFlit => EN_send_ports_7_putFlit ,
EN_send_ports_7_getNonFullVCs => EN_send_ports_7_getNonFullVCs ,
send_ports_7_getNonFullVCs => send_ports_7_getNonFullVCs ,
send_ports_8_putFlit_flit_in => send_ports_8_putFlit_flit_in ,
EN_send_ports_8_putFlit => EN_send_ports_8_putFlit ,
EN_send_ports_8_getNonFullVCs => EN_send_ports_8_getNonFullVCs ,
send_ports_8_getNonFullVCs => send_ports_8_getNonFullVCs ,
EN_recv_ports_0_getFlit => EN_recv_ports_0_getFlit ,
recv_ports_0_getFlit => recv_ports_0_getFlit ,
recv_ports_0_putNonFullVCs_nonFullVCs => recv_ports_0_putNonFullVCs_nonFullVCs ,
EN_recv_ports_0_putNonFullVCs => EN_recv_ports_0_putNonFullVCs ,
EN_recv_ports_1_getFlit => EN_recv_ports_1_getFlit ,
recv_ports_1_getFlit => recv_ports_1_getFlit ,
recv_ports_1_putNonFullVCs_nonFullVCs => recv_ports_1_putNonFullVCs_nonFullVCs ,
EN_recv_ports_1_putNonFullVCs => EN_recv_ports_1_putNonFullVCs ,
EN_recv_ports_2_getFlit => EN_recv_ports_2_getFlit ,
recv_ports_2_getFlit => recv_ports_2_getFlit ,
recv_ports_2_putNonFullVCs_nonFullVCs => recv_ports_2_putNonFullVCs_nonFullVCs ,
EN_recv_ports_2_putNonFullVCs => EN_recv_ports_2_putNonFullVCs ,
EN_recv_ports_3_getFlit => EN_recv_ports_3_getFlit ,
recv_ports_3_getFlit => recv_ports_3_getFlit ,
recv_ports_3_putNonFullVCs_nonFullVCs => recv_ports_3_putNonFullVCs_nonFullVCs ,
EN_recv_ports_3_putNonFullVCs => EN_recv_ports_3_putNonFullVCs ,
EN_recv_ports_4_getFlit => EN_recv_ports_4_getFlit ,
recv_ports_4_getFlit => recv_ports_4_getFlit ,
recv_ports_4_putNonFullVCs_nonFullVCs => recv_ports_4_putNonFullVCs_nonFullVCs ,
EN_recv_ports_4_putNonFullVCs => EN_recv_ports_4_putNonFullVCs ,
EN_recv_ports_5_getFlit => EN_recv_ports_5_getFlit ,
recv_ports_5_getFlit => recv_ports_5_getFlit ,
recv_ports_5_putNonFullVCs_nonFullVCs => recv_ports_5_putNonFullVCs_nonFullVCs ,
EN_recv_ports_5_putNonFullVCs => EN_recv_ports_5_putNonFullVCs ,
EN_recv_ports_6_getFlit => EN_recv_ports_6_getFlit ,
recv_ports_6_getFlit => recv_ports_6_getFlit ,
recv_ports_6_putNonFullVCs_nonFullVCs => recv_ports_6_putNonFullVCs_nonFullVCs ,
EN_recv_ports_6_putNonFullVCs => EN_recv_ports_6_putNonFullVCs ,
EN_recv_ports_7_getFlit => EN_recv_ports_7_getFlit ,
recv_ports_7_getFlit => recv_ports_7_getFlit ,
recv_ports_7_putNonFullVCs_nonFullVCs => recv_ports_7_putNonFullVCs_nonFullVCs ,
EN_recv_ports_7_putNonFullVCs => EN_recv_ports_7_putNonFullVCs ,
EN_recv_ports_8_getFlit => EN_recv_ports_8_getFlit ,
recv_ports_8_getFlit => recv_ports_8_getFlit ,
recv_ports_8_putNonFullVCs_nonFullVCs => recv_ports_8_putNonFullVCs_nonFullVCs ,
EN_recv_ports_8_putNonFullVCs => EN_recv_ports_8_putNonFullVCs ,
recv_ports_info_0_getRecvPortID => recv_ports_info_0_getRecvPortID ,
recv_ports_info_1_getRecvPortID => recv_ports_info_1_getRecvPortID ,
recv_ports_info_2_getRecvPortID => recv_ports_info_2_getRecvPortID ,
recv_ports_info_3_getRecvPortID => recv_ports_info_3_getRecvPortID ,
recv_ports_info_4_getRecvPortID => recv_ports_info_4_getRecvPortID ,
recv_ports_info_5_getRecvPortID => recv_ports_info_5_getRecvPortID ,
recv_ports_info_6_getRecvPortID => recv_ports_info_6_getRecvPortID ,
recv_ports_info_7_getRecvPortID => recv_ports_info_7_getRecvPortID ,
recv_ports_info_8_getRecvPortID => recv_ports_info_8_getRecvPortID ,
send_ports_9_putFlit_flit_in => send_ports_9_putFlit_flit_in ,
EN_send_ports_9_putFlit => EN_send_ports_9_putFlit ,
EN_send_ports_9_getNonFullVCs => EN_send_ports_9_getNonFullVCs ,
send_ports_9_getNonFullVCs => send_ports_9_getNonFullVCs ,
send_ports_10_putFlit_flit_in => send_ports_10_putFlit_flit_in ,
EN_send_ports_10_putFlit => EN_send_ports_10_putFlit ,
EN_send_ports_10_getNonFullVCs => EN_send_ports_10_getNonFullVCs ,
send_ports_10_getNonFullVCs => send_ports_10_getNonFullVCs ,
send_ports_11_putFlit_flit_in => send_ports_11_putFlit_flit_in ,
EN_send_ports_11_putFlit => EN_send_ports_11_putFlit ,
EN_send_ports_11_getNonFullVCs => EN_send_ports_11_getNonFullVCs ,
send_ports_11_getNonFullVCs => send_ports_11_getNonFullVCs ,
EN_recv_ports_9_getFlit => EN_recv_ports_9_getFlit ,
recv_ports_9_getFlit => recv_ports_9_getFlit ,
recv_ports_9_putNonFullVCs_nonFullVCs => recv_ports_9_putNonFullVCs_nonFullVCs ,
EN_recv_ports_9_putNonFullVCs => EN_recv_ports_9_putNonFullVCs ,
EN_recv_ports_10_getFlit => EN_recv_ports_10_getFlit ,
recv_ports_10_getFlit => recv_ports_10_getFlit ,
recv_ports_10_putNonFullVCs_nonFullVCs => recv_ports_10_putNonFullVCs_nonFullVCs ,
EN_recv_ports_10_putNonFullVCs => EN_recv_ports_10_putNonFullVCs ,
EN_recv_ports_11_getFlit => EN_recv_ports_11_getFlit ,
recv_ports_11_getFlit => recv_ports_11_getFlit ,
recv_ports_11_putNonFullVCs_nonFullVCs => recv_ports_11_putNonFullVCs_nonFullVCs ,
EN_recv_ports_11_putNonFullVCs => EN_recv_ports_11_putNonFullVCs ,
recv_ports_info_9_getRecvPortID => recv_ports_info_9_getRecvPortID ,
recv_ports_info_10_getRecvPortID => recv_ports_info_10_getRecvPortID ,
recv_ports_info_11_getRecvPortID => recv_ports_info_11_getRecvPortID
);
i0: network_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe0,
dest_addr => dest_addr_pe0,
set_tail_flit => set_tail_flit_pe0,
send_flit => send_flit_pe0,
ready_to_send => ready_to_send_pe0,
recv_data => recv_data_pe0,
src_addr => src_addr_pe0,
is_tail_flit => is_tail_flit_pe0,
data_in_buffer => data_in_buffer_pe0,
dequeue => dequeue_pe0,
select_vc_read => select_vc_read_pe0,
send_putFlit_flit_in => send_ports_0_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_0_putFlit,
EN_send_getNonFullVCs => EN_send_ports_0_getNonFullVCs,
send_getNonFullVCs => send_ports_0_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_0_getFlit,
recv_getFlit => recv_ports_0_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_0_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_0_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_0_getRecvPortID);
i1: network_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe1,
dest_addr => dest_addr_pe1,
set_tail_flit => set_tail_flit_pe1,
send_flit => send_flit_pe1,
ready_to_send => ready_to_send_pe1,
recv_data => recv_data_pe1,
src_addr => src_addr_pe1,
is_tail_flit => is_tail_flit_pe1,
data_in_buffer => data_in_buffer_pe1,
dequeue => dequeue_pe1,
select_vc_read => select_vc_read_pe1,
send_putFlit_flit_in => send_ports_1_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_1_putFlit,
EN_send_getNonFullVCs => EN_send_ports_1_getNonFullVCs,
send_getNonFullVCs => send_ports_1_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_1_getFlit,
recv_getFlit => recv_ports_1_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_1_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_1_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_1_getRecvPortID);
i2: network_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe2,
dest_addr => dest_addr_pe2,
set_tail_flit => set_tail_flit_pe2,
send_flit => send_flit_pe2,
ready_to_send => ready_to_send_pe2,
recv_data => recv_data_pe2,
src_addr => src_addr_pe2,
is_tail_flit => is_tail_flit_pe2,
data_in_buffer => data_in_buffer_pe2,
dequeue => dequeue_pe2,
select_vc_read => select_vc_read_pe2,
send_putFlit_flit_in => send_ports_2_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_2_putFlit,
EN_send_getNonFullVCs => EN_send_ports_2_getNonFullVCs,
send_getNonFullVCs => send_ports_2_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_2_getFlit,
recv_getFlit => recv_ports_2_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_2_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_2_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_2_getRecvPortID);
i3: network_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe3,
dest_addr => dest_addr_pe3,
set_tail_flit => set_tail_flit_pe3,
send_flit => send_flit_pe3,
ready_to_send => ready_to_send_pe3,
recv_data => recv_data_pe3,
src_addr => src_addr_pe3,
is_tail_flit => is_tail_flit_pe3,
data_in_buffer => data_in_buffer_pe3,
dequeue => dequeue_pe3,
select_vc_read => select_vc_read_pe3,
send_putFlit_flit_in => send_ports_3_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_3_putFlit,
EN_send_getNonFullVCs => EN_send_ports_3_getNonFullVCs,
send_getNonFullVCs => send_ports_3_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_3_getFlit,
recv_getFlit => recv_ports_3_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_3_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_3_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_3_getRecvPortID);
n0: component deblocking_filter_node
generic map(
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe1,
src_addr => src_addr_pe1,
is_tail_flit => is_tail_flit_pe1,
data_in_buffer => data_in_buffer_pe1,
dequeue => dequeue_pe1,
select_vc_read => select_vc_read_pe1,
send_data => send_data_pe1,
dest_addr => dest_addr_pe1,
set_tail_flit => set_tail_flit_pe1,
send_flit => send_flit_pe1,
ready_to_send => ready_to_send_pe1
);
n1: component inter_node
generic map(
size_x => 12,
size_y => 6,
interp_x => 8 ,
interp_y => 1 ,
sample_size => 8 ,
samples_per_wr => 8 ,
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe2,
src_addr => src_addr_pe2,
is_tail_flit => is_tail_flit_pe2,
data_in_buffer => data_in_buffer_pe2,
dequeue => dequeue_pe2,
select_vc_read => select_vc_read_pe2,
send_data => send_data_pe2,
dest_addr => dest_addr_pe2,
set_tail_flit => set_tail_flit_pe2,
send_flit => send_flit_pe2,
ready_to_send => ready_to_send_pe2
);
n2: component intra_prediction_node
generic map(
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe3,
src_addr => src_addr_pe3,
is_tail_flit => is_tail_flit_pe3,
data_in_buffer => data_in_buffer_pe3,
dequeue => dequeue_pe3,
select_vc_read => select_vc_read_pe3,
send_data => send_data_pe3,
dest_addr => dest_addr_pe3,
set_tail_flit => set_tail_flit_pe3,
send_flit => send_flit_pe3,
ready_to_send => ready_to_send_pe3,
s_intra_idle => ledr(0),
s_intra_data_rxd => ledr(1),
s_intra_write_sample => ledr(2),
s_intra_start_pred => ledr(3),
s_intra_start_tx_loop => ledr(4),
s_intra_start_tx_loop_hold => ledr(5),
s_intra_tx => ledr(6),
s_intra_tx_hold => ledr(7),
s_intra_tx_gen_next => ledr(8),
s_intra_dequeue_rx => ledr(9)
);
n3: component noc_controller
generic map(
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
data_in => flit_word_0_export & flit_word_1_export,
data_out => data_out,
noc_ctrl => noc_ctrl_export,
noc_sts => noc_status_export,
send_data => send_data_pe0,
dest_addr => dest_addr_pe0,
set_tail_flit => set_tail_flit_pe0,
send_flit => send_flit_pe0,
ready_to_send => ready_to_send_pe0,
recv_data => recv_data_pe0,
src_addr => src_addr_pe0,
is_tail_flit => is_tail_flit_pe0,
data_in_buffer => data_in_buffer_pe0,
dequeue => dequeue_pe0,
select_vc_read => select_vc_read_pe0
);
--noc_status_export(31 downto 4) <= (others => '0');
flit_rx_1_export <= data_out(31 downto 0);
flit_rx_0_export <= data_out(63 downto 32);
flit_rx_3_export <= (others => '0');
flit_rx_2_export <= (others => '0');
noc_rst <= noc_ctrl_export(15);
--ledr(8) <= '0';
--ledr(3) <= '0';
--ledr(7) <= sw(7) and or_reduce(is_idle);
--ledr(6) <= sw(6) and or_reduce(is_filtering);
--ledr(5) <= sw(5) and or_reduce(is_tx_ing);
--ledr(4) <= sw(4) and or_reduce(is_cleanup_ing);
--noc_status_export(1) <= not ready_to_send_pe1;
--noc_status_export(2) <= not ready_to_send_pe2;
--noc_status_export(3) <= not ready_to_send_pe3;
END MAIN; | mit | 84f597b9833ab4e08f247e4bee854ff7 | 0.496562 | 3.622897 | false | false | false | false |
DaveyPocket/btrace448 | core/vga/vga_sync.vhd | 1 | 3,686 | -- Btrace 448
-- VGA Sync
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vga_sync is
port(
clk, reset: in std_logic;
hsync, vsync: out std_logic;
video_on, p_tick: out std_logic;
pixel_x, pixel_y: out std_logic_vector (9 downto 0)
);
end vga_sync;
architecture arch of vga_sync is
-- VGA 640-by-480 sync parameters
constant HD: integer:=639; --horizontal display area
constant HF: integer:=16 ; --h. front porch
constant HB: integer:=48 ; --h. back porch
constant HR: integer:=96 ; --h. retrace
constant VD: integer:=479; --vertical display area
constant VF: integer:=10; --v. front porch
constant VB: integer:=33; --v. back porch
constant VR: integer:=2; --v. retrace
constant THREE : std_logic_vector(1 downto 0) := "11";
-- sync counters
signal v_count_reg, v_count_next: std_logic_vector(9 downto 0);
signal h_count_reg, h_count_next: std_logic_vector(9 downto 0);
-- output buffer
signal v_sync_reg, h_sync_reg: std_logic;
signal v_sync_next, h_sync_next: std_logic;
-- status signal
signal h_end, v_end, pixel_tick: std_logic;
signal count_3 : std_logic_vector(1 downto 0);
begin
-- registers
process (clk,reset)
begin
if reset='1' then
v_count_reg <= (others=>'0');
h_count_reg <= (others=>'0');
v_sync_reg <= '1';
h_sync_reg <= '1';
elsif (clk'event and clk='1') then
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
v_sync_reg <= v_sync_next;
h_sync_reg <= h_sync_next;
end if;
end process;
-- circuit to generate 25 MHz enable tick
process (clk, reset)
begin
if reset='1' then
count_3 <= (others =>'0');
elsif rising_edge(clk) then
count_3 <= count_3 + 1;
end if;
end process;
-- 25 MHz pixel tick
pixel_tick <= '1' when count_3 = THREE else '0';
-- status
h_end <= -- end of horizontal counter
'1' when h_count_reg=(HD+HF+HB+HR-1) else --799
'0';
v_end <= -- end of vertical counter
'1' when v_count_reg=(VD+VF+VB+VR-1) else --524
'0';
-- mod-800 horizontal sync counter
process (h_count_reg,h_end,pixel_tick)
begin
if pixel_tick='1' then -- 25 MHz tick
if h_end='1' then
h_count_next <= (others=>'0');
else
h_count_next <= h_count_reg + 1;
end if;
else
h_count_next <= h_count_reg;
end if;
end process;
-- mod-525 vertical sync counter
process (v_count_reg,h_end,v_end,pixel_tick)
begin
if pixel_tick='1' and h_end='1' then
if (v_end='1') then
v_count_next <= (others=>'0');
else
v_count_next <= v_count_reg + 1;
end if;
else
v_count_next <= v_count_reg;
end if;
end process;
-- horizontal and vertical sync, buffered to avoid glitch
h_sync_next <=
'0' when (h_count_reg>=(HD+HF)) --656
and (h_count_reg<=(HD+HF+HR-1)) else --751
'1';
v_sync_next <=
'0' when (v_count_reg>=(VD+VF)) --490
and (v_count_reg<=(VD+VF+VR-1)) else --491
'1';
-- video on/off
video_on <=
'1' when (h_count_reg<HD) and (v_count_reg<VD) else
'0';
-- output signal
hsync <= h_sync_reg;
vsync <= v_sync_reg;
pixel_x <= std_logic_vector(h_count_reg);
pixel_y <= std_logic_vector(v_count_reg);
p_tick <= pixel_tick;
end arch;
| gpl-3.0 | 843c88733c7447b2017fa48a46bb0375 | 0.544493 | 3.199653 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/inter_core.vhd | 1 | 32,480 | -- Inter-Prediction Interpolator Filter
-- see ITU Std. 8.4.2.2.1 and 8.4.2.2.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity inter_core is
generic(
x_len : integer := 4;
y_len : integer := 4;
sample_size : integer := 8
);
port(
samples : in std_logic_vector((x_len+5)*(y_len+5)*sample_size-1 downto 0);
sel : in std_logic_vector(7 downto 0);
result : out std_logic_vector(x_len*y_len*sample_size-1 downto 0)
);
end entity inter_core;
architecture rtl of inter_core is
---------------------------------------------------------------------------
--- Components ------------------------------------------------------------
---------------------------------------------------------------------------
component half_pixel_interpolator_fir is
port(
x0 : in std_logic_vector(7 downto 0);
x1 : in std_logic_vector(7 downto 0);
x2 : in std_logic_vector(7 downto 0);
x3 : in std_logic_vector(7 downto 0);
x4 : in std_logic_vector(7 downto 0);
x5 : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0)
);
end component half_pixel_interpolator_fir;
component avg2 is
port(
x0 : in std_logic_vector(7 downto 0);
x1 : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0)
);
end component avg2;
---------------------------------------------------------------------------
--- TYPES -----------------------------------------------------------------
---------------------------------------------------------------------------
type sample_row is array(x_len - 1 downto 0) of std_logic_vector(sample_size-1 downto 0);
type sample_array is array(y_len - 1 downto 0) of sample_row;
---------------------------------------------------------------------------
--- SIGNALS ---------------------------------------------------------------
---------------------------------------------------------------------------
--input samples
signal A_in : sample_array;
signal B_in : sample_array;
signal C_in : sample_array;
signal D_in : sample_array;
signal E_in : sample_array;
signal F_in : sample_array;
signal G_in : sample_array;
signal H_in : sample_array;
signal I_in : sample_array;
signal J_in : sample_array;
signal K_in : sample_array;
signal L_in : sample_array;
signal M_in : sample_array;
signal N_in : sample_array;
signal P_in : sample_array;
signal Q_in : sample_array;
signal R_in : sample_array;
signal S_in : sample_array;
signal T_in : sample_array;
signal U_in : sample_array;
-- intermediate interpolation results
signal aa : sample_array;
signal bb : sample_array;
signal cc : sample_array;
signal dd : sample_array;
signal ee : sample_array;
signal ff : sample_array;
signal gg : sample_array;
signal hh : sample_array;
-- final interpolation results
signal a : sample_array;
signal b : sample_array;
signal c : sample_array;
signal d : sample_array;
signal e : sample_array;
signal f : sample_array;
signal g : sample_array;
signal h : sample_array;
signal i : sample_array;
signal j : sample_array;
signal k : sample_array;
signal m : sample_array; --apparently ITU hates the letter l...
signal n : sample_array;
signal p : sample_array;
signal q : sample_array;
signal r : sample_array;
signal s : sample_array;
-- selected interpolation result
signal y : sample_array;
begin
interpx: for nx in x_len-1 downto 0 generate
begin
interpy: for ny in y_len-1 downto 0 generate
-- constants for parsing samples out of "samples"
constant row_0_start : integer := ny * (x_len+5) + nx;
constant row_1_start : integer := (ny+1) * (x_len+5) + nx;
constant row_2_start : integer := (ny+2) * (x_len+5) + nx;
constant row_3_start : integer := (ny+3) * (x_len+5) + nx;
constant row_4_start : integer := (ny+4) * (x_len+5) + nx;
constant row_5_start : integer := (ny+5) * (x_len+5) + nx;
constant g_in_row_pos : integer := 2;
constant g_in_row : integer := row_2_start;
constant g_in_sample_num : integer := g_in_row + g_in_row_pos;
constant g_in_low : integer := g_in_sample_num * sample_size;
constant g_in_high : integer := g_in_low + sample_size - 1;
constant h_in_row_pos : integer := 3;
constant h_in_row : integer := row_2_start;
constant h_in_sample_num : integer := h_in_row + h_in_row_pos;
constant h_in_low : integer := h_in_sample_num * sample_size;
constant h_in_high : integer := h_in_low + sample_size - 1;
constant m_in_row_pos : integer := 2;
constant m_in_row : integer := row_3_start;
constant m_in_sample_num : integer := m_in_row + m_in_row_pos;
constant m_in_low : integer := m_in_sample_num * sample_size;
constant m_in_high : integer := m_in_low + sample_size - 1;
constant sample_0_0_in_row_pos : integer := 0;
constant sample_0_0_in_row : integer := row_0_start;
constant sample_0_0_in_sample_num : integer := sample_0_0_in_row + sample_0_0_in_row_pos;
constant sample_0_0_in_low : integer := sample_0_0_in_sample_num * sample_size;
constant sample_0_0_in_high : integer := sample_0_0_in_low + sample_size - 1;
constant sample_0_1_in_row_pos : integer := 1;
constant sample_0_1_in_row : integer := row_0_start;
constant sample_0_1_in_sample_num : integer := sample_0_1_in_row + sample_0_1_in_row_pos;
constant sample_0_1_in_low : integer := sample_0_1_in_sample_num * sample_size;
constant sample_0_1_in_high : integer := sample_0_1_in_low + sample_size - 1;
constant sample_0_2_in_row_pos : integer := 2;
constant sample_0_2_in_row : integer := row_0_start;
constant sample_0_2_in_sample_num : integer := sample_0_2_in_row + sample_0_2_in_row_pos;
constant sample_0_2_in_low : integer := sample_0_2_in_sample_num * sample_size;
constant sample_0_2_in_high : integer := sample_0_2_in_low + sample_size - 1;
constant sample_0_3_in_row_pos : integer := 3;
constant sample_0_3_in_row : integer := row_0_start;
constant sample_0_3_in_sample_num : integer := sample_0_3_in_row + sample_0_3_in_row_pos;
constant sample_0_3_in_low : integer := sample_0_3_in_sample_num * sample_size;
constant sample_0_3_in_high : integer := sample_0_3_in_low + sample_size - 1;
constant sample_0_4_in_row_pos : integer := 4;
constant sample_0_4_in_row : integer := row_0_start;
constant sample_0_4_in_sample_num : integer := sample_0_4_in_row + sample_0_4_in_row_pos;
constant sample_0_4_in_low : integer := sample_0_4_in_sample_num * sample_size;
constant sample_0_4_in_high : integer := sample_0_4_in_low + sample_size - 1;
constant sample_0_5_in_row_pos : integer := 5;
constant sample_0_5_in_row : integer := row_0_start;
constant sample_0_5_in_sample_num : integer := sample_0_5_in_row + sample_0_5_in_row_pos;
constant sample_0_5_in_low : integer := sample_0_5_in_sample_num * sample_size;
constant sample_0_5_in_high : integer := sample_0_5_in_low + sample_size - 1;
constant sample_1_0_in_row_pos : integer := 0;
constant sample_1_0_in_row : integer := row_1_start;
constant sample_1_0_in_sample_num : integer := sample_1_0_in_row + sample_1_0_in_row_pos;
constant sample_1_0_in_low : integer := sample_1_0_in_sample_num * sample_size;
constant sample_1_0_in_high : integer := sample_1_0_in_low + sample_size - 1;
constant sample_1_1_in_row_pos : integer := 1;
constant sample_1_1_in_row : integer := row_1_start;
constant sample_1_1_in_sample_num : integer := sample_1_1_in_row + sample_1_1_in_row_pos;
constant sample_1_1_in_low : integer := sample_1_1_in_sample_num * sample_size;
constant sample_1_1_in_high : integer := sample_1_1_in_low + sample_size - 1;
constant sample_1_2_in_row_pos : integer := 2;
constant sample_1_2_in_row : integer := row_1_start;
constant sample_1_2_in_sample_num : integer := sample_1_2_in_row + sample_1_2_in_row_pos;
constant sample_1_2_in_low : integer := sample_1_2_in_sample_num * sample_size;
constant sample_1_2_in_high : integer := sample_1_2_in_low + sample_size - 1;
constant sample_1_3_in_row_pos : integer := 3;
constant sample_1_3_in_row : integer := row_1_start;
constant sample_1_3_in_sample_num : integer := sample_1_3_in_row + sample_1_3_in_row_pos;
constant sample_1_3_in_low : integer := sample_1_3_in_sample_num * sample_size;
constant sample_1_3_in_high : integer := sample_1_3_in_low + sample_size - 1;
constant sample_1_4_in_row_pos : integer := 4;
constant sample_1_4_in_row : integer := row_1_start;
constant sample_1_4_in_sample_num : integer := sample_1_4_in_row + sample_1_4_in_row_pos;
constant sample_1_4_in_low : integer := sample_1_4_in_sample_num * sample_size;
constant sample_1_4_in_high : integer := sample_1_4_in_low + sample_size - 1;
constant sample_1_5_in_row_pos : integer := 5;
constant sample_1_5_in_row : integer := row_1_start;
constant sample_1_5_in_sample_num : integer := sample_1_5_in_row + sample_1_5_in_row_pos;
constant sample_1_5_in_low : integer := sample_1_5_in_sample_num * sample_size;
constant sample_1_5_in_high : integer := sample_1_5_in_low + sample_size - 1;
constant sample_2_0_in_row_pos : integer := 0;
constant sample_2_0_in_row : integer := row_2_start;
constant sample_2_0_in_sample_num : integer := sample_2_0_in_row + sample_2_0_in_row_pos;
constant sample_2_0_in_low : integer := sample_2_0_in_sample_num * sample_size;
constant sample_2_0_in_high : integer := sample_2_0_in_low + sample_size - 1;
constant sample_2_1_in_row_pos : integer := 1;
constant sample_2_1_in_row : integer := row_2_start;
constant sample_2_1_in_sample_num : integer := sample_2_1_in_row + sample_2_1_in_row_pos;
constant sample_2_1_in_low : integer := sample_2_1_in_sample_num * sample_size;
constant sample_2_1_in_high : integer := sample_2_1_in_low + sample_size - 1;
constant sample_2_2_in_row_pos : integer := 2;
constant sample_2_2_in_row : integer := row_2_start;
constant sample_2_2_in_sample_num : integer := sample_2_2_in_row + sample_2_2_in_row_pos;
constant sample_2_2_in_low : integer := sample_2_2_in_sample_num * sample_size;
constant sample_2_2_in_high : integer := sample_2_2_in_low + sample_size - 1;
constant sample_2_3_in_row_pos : integer := 3;
constant sample_2_3_in_row : integer := row_2_start;
constant sample_2_3_in_sample_num : integer := sample_2_3_in_row + sample_2_3_in_row_pos;
constant sample_2_3_in_low : integer := sample_2_3_in_sample_num * sample_size;
constant sample_2_3_in_high : integer := sample_2_3_in_low + sample_size - 1;
constant sample_2_4_in_row_pos : integer := 4;
constant sample_2_4_in_row : integer := row_2_start;
constant sample_2_4_in_sample_num : integer := sample_2_4_in_row + sample_2_4_in_row_pos;
constant sample_2_4_in_low : integer := sample_2_4_in_sample_num * sample_size;
constant sample_2_4_in_high : integer := sample_2_4_in_low + sample_size - 1;
constant sample_2_5_in_row_pos : integer := 5;
constant sample_2_5_in_row : integer := row_2_start;
constant sample_2_5_in_sample_num : integer := sample_2_5_in_row + sample_2_5_in_row_pos;
constant sample_2_5_in_low : integer := sample_2_5_in_sample_num * sample_size;
constant sample_2_5_in_high : integer := sample_2_5_in_low + sample_size - 1;
constant sample_3_0_in_row_pos : integer := 0;
constant sample_3_0_in_row : integer := row_3_start;
constant sample_3_0_in_sample_num : integer := sample_3_0_in_row + sample_3_0_in_row_pos;
constant sample_3_0_in_low : integer := sample_3_0_in_sample_num * sample_size;
constant sample_3_0_in_high : integer := sample_3_0_in_low + sample_size - 1;
constant sample_3_1_in_row_pos : integer := 1;
constant sample_3_1_in_row : integer := row_3_start;
constant sample_3_1_in_sample_num : integer := sample_3_1_in_row + sample_3_1_in_row_pos;
constant sample_3_1_in_low : integer := sample_3_1_in_sample_num * sample_size;
constant sample_3_1_in_high : integer := sample_3_1_in_low + sample_size - 1;
constant sample_3_2_in_row_pos : integer := 2;
constant sample_3_2_in_row : integer := row_3_start;
constant sample_3_2_in_sample_num : integer := sample_3_2_in_row + sample_3_2_in_row_pos;
constant sample_3_2_in_low : integer := sample_3_2_in_sample_num * sample_size;
constant sample_3_2_in_high : integer := sample_3_2_in_low + sample_size - 1;
constant sample_3_3_in_row_pos : integer := 3;
constant sample_3_3_in_row : integer := row_3_start;
constant sample_3_3_in_sample_num : integer := sample_3_3_in_row + sample_3_3_in_row_pos;
constant sample_3_3_in_low : integer := sample_3_3_in_sample_num * sample_size;
constant sample_3_3_in_high : integer := sample_3_3_in_low + sample_size - 1;
constant sample_3_4_in_row_pos : integer := 4;
constant sample_3_4_in_row : integer := row_3_start;
constant sample_3_4_in_sample_num : integer := sample_3_4_in_row + sample_3_4_in_row_pos;
constant sample_3_4_in_low : integer := sample_3_4_in_sample_num * sample_size;
constant sample_3_4_in_high : integer := sample_3_4_in_low + sample_size - 1;
constant sample_3_5_in_row_pos : integer := 5;
constant sample_3_5_in_row : integer := row_3_start;
constant sample_3_5_in_sample_num : integer := sample_3_5_in_row + sample_3_5_in_row_pos;
constant sample_3_5_in_low : integer := sample_3_5_in_sample_num * sample_size;
constant sample_3_5_in_high : integer := sample_3_5_in_low + sample_size - 1;
constant sample_4_0_in_row_pos : integer := 0;
constant sample_4_0_in_row : integer := row_4_start;
constant sample_4_0_in_sample_num : integer := sample_4_0_in_row + sample_4_0_in_row_pos;
constant sample_4_0_in_low : integer := sample_4_0_in_sample_num * sample_size;
constant sample_4_0_in_high : integer := sample_4_0_in_low + sample_size - 1;
constant sample_4_1_in_row_pos : integer := 1;
constant sample_4_1_in_row : integer := row_4_start;
constant sample_4_1_in_sample_num : integer := sample_4_1_in_row + sample_4_1_in_row_pos;
constant sample_4_1_in_low : integer := sample_4_1_in_sample_num * sample_size;
constant sample_4_1_in_high : integer := sample_4_1_in_low + sample_size - 1;
constant sample_4_2_in_row_pos : integer := 2;
constant sample_4_2_in_row : integer := row_4_start;
constant sample_4_2_in_sample_num : integer := sample_4_2_in_row + sample_4_2_in_row_pos;
constant sample_4_2_in_low : integer := sample_4_2_in_sample_num * sample_size;
constant sample_4_2_in_high : integer := sample_4_2_in_low + sample_size - 1;
constant sample_4_3_in_row_pos : integer := 3;
constant sample_4_3_in_row : integer := row_4_start;
constant sample_4_3_in_sample_num : integer := sample_4_3_in_row + sample_4_3_in_row_pos;
constant sample_4_3_in_low : integer := sample_4_3_in_sample_num * sample_size;
constant sample_4_3_in_high : integer := sample_4_3_in_low + sample_size - 1;
constant sample_4_4_in_row_pos : integer := 4;
constant sample_4_4_in_row : integer := row_4_start;
constant sample_4_4_in_sample_num : integer := sample_4_4_in_row + sample_4_4_in_row_pos;
constant sample_4_4_in_low : integer := sample_4_4_in_sample_num * sample_size;
constant sample_4_4_in_high : integer := sample_4_4_in_low + sample_size - 1;
constant sample_4_5_in_row_pos : integer := 5;
constant sample_4_5_in_row : integer := row_4_start;
constant sample_4_5_in_sample_num : integer := sample_4_5_in_row + sample_4_5_in_row_pos;
constant sample_4_5_in_low : integer := sample_4_5_in_sample_num * sample_size;
constant sample_4_5_in_high : integer := sample_4_5_in_low + sample_size - 1;
constant sample_5_0_in_row_pos : integer := 0;
constant sample_5_0_in_row : integer := row_5_start;
constant sample_5_0_in_sample_num : integer := sample_5_0_in_row + sample_5_0_in_row_pos;
constant sample_5_0_in_low : integer := sample_5_0_in_sample_num * sample_size;
constant sample_5_0_in_high : integer := sample_5_0_in_low + sample_size - 1;
constant sample_5_1_in_row_pos : integer := 1;
constant sample_5_1_in_row : integer := row_5_start;
constant sample_5_1_in_sample_num : integer := sample_5_1_in_row + sample_5_1_in_row_pos;
constant sample_5_1_in_low : integer := sample_5_1_in_sample_num * sample_size;
constant sample_5_1_in_high : integer := sample_5_1_in_low + sample_size - 1;
constant sample_5_2_in_row_pos : integer := 2;
constant sample_5_2_in_row : integer := row_5_start;
constant sample_5_2_in_sample_num : integer := sample_5_2_in_row + sample_5_2_in_row_pos;
constant sample_5_2_in_low : integer := sample_5_2_in_sample_num * sample_size;
constant sample_5_2_in_high : integer := sample_5_2_in_low + sample_size - 1;
constant sample_5_3_in_row_pos : integer := 3;
constant sample_5_3_in_row : integer := row_5_start;
constant sample_5_3_in_sample_num : integer := sample_5_3_in_row + sample_5_3_in_row_pos;
constant sample_5_3_in_low : integer := sample_5_3_in_sample_num * sample_size;
constant sample_5_3_in_high : integer := sample_5_3_in_low + sample_size - 1;
constant sample_5_4_in_row_pos : integer := 4;
constant sample_5_4_in_row : integer := row_5_start;
constant sample_5_4_in_sample_num : integer := sample_5_4_in_row + sample_5_4_in_row_pos;
constant sample_5_4_in_low : integer := sample_5_4_in_sample_num * sample_size;
constant sample_5_4_in_high : integer := sample_5_4_in_low + sample_size - 1;
constant sample_5_5_in_row_pos : integer := 5;
constant sample_5_5_in_row : integer := row_5_start;
constant sample_5_5_in_sample_num : integer := sample_5_5_in_row + sample_5_5_in_row_pos;
constant sample_5_5_in_low : integer := sample_5_5_in_sample_num * sample_size;
constant sample_5_5_in_high : integer := sample_5_5_in_low + sample_size - 1;
begin
--parse input samples out of the input vector samples
G_in(ny)(nx) <= samples(g_in_high downto g_in_low);
H_in(ny)(nx) <= samples(h_in_high downto h_in_low);
M_in(ny)(nx) <= samples(m_in_high downto m_in_low);
-- half pixel interpolation between whole pixel values
fir_aa: component half_pixel_interpolator_fir port map(
x0 => samples(sample_0_0_in_high downto sample_0_0_in_low),
x1 => samples(sample_0_1_in_high downto sample_0_1_in_low),
x2 => samples(sample_0_2_in_high downto sample_0_2_in_low),
x3 => samples(sample_0_3_in_high downto sample_0_3_in_low),
x4 => samples(sample_0_4_in_high downto sample_0_4_in_low),
x5 => samples(sample_0_5_in_high downto sample_0_5_in_low),
y => aa(ny)(nx)
);
fir_bb: component half_pixel_interpolator_fir port map(
x0 => samples(sample_1_0_in_high downto sample_1_0_in_low),
x1 => samples(sample_1_1_in_high downto sample_1_1_in_low),
x2 => samples(sample_1_2_in_high downto sample_1_2_in_low),
x3 => samples(sample_1_3_in_high downto sample_1_3_in_low),
x4 => samples(sample_1_4_in_high downto sample_1_4_in_low),
x5 => samples(sample_1_5_in_high downto sample_1_5_in_low),
y => bb(ny)(nx)
);
fir_b: component half_pixel_interpolator_fir port map(
x0 => samples(sample_2_0_in_high downto sample_2_0_in_low),
x1 => samples(sample_2_1_in_high downto sample_2_1_in_low),
x2 => samples(sample_2_2_in_high downto sample_2_2_in_low),
x3 => samples(sample_2_3_in_high downto sample_2_3_in_low),
x4 => samples(sample_2_4_in_high downto sample_2_4_in_low),
x5 => samples(sample_2_5_in_high downto sample_2_5_in_low),
y => b(ny)(nx)
);
fir_s: component half_pixel_interpolator_fir port map(
x0 => samples(sample_3_0_in_high downto sample_3_0_in_low),
x1 => samples(sample_3_1_in_high downto sample_3_1_in_low),
x2 => samples(sample_3_2_in_high downto sample_3_2_in_low),
x3 => samples(sample_3_3_in_high downto sample_3_3_in_low),
x4 => samples(sample_3_4_in_high downto sample_3_4_in_low),
x5 => samples(sample_3_5_in_high downto sample_3_5_in_low),
y => s(ny)(nx)
);
fir_gg: component half_pixel_interpolator_fir port map(
x0 => samples(sample_4_0_in_high downto sample_4_0_in_low),
x1 => samples(sample_4_1_in_high downto sample_4_1_in_low),
x2 => samples(sample_4_2_in_high downto sample_4_2_in_low),
x3 => samples(sample_4_3_in_high downto sample_4_3_in_low),
x4 => samples(sample_4_4_in_high downto sample_4_4_in_low),
x5 => samples(sample_4_5_in_high downto sample_4_5_in_low),
y => gg(ny)(nx)
);
fir_hh: component half_pixel_interpolator_fir port map(
x0 => samples(sample_5_0_in_high downto sample_5_0_in_low),
x1 => samples(sample_5_1_in_high downto sample_5_1_in_low),
x2 => samples(sample_5_2_in_high downto sample_5_2_in_low),
x3 => samples(sample_5_3_in_high downto sample_5_3_in_low),
x4 => samples(sample_5_4_in_high downto sample_5_4_in_low),
x5 => samples(sample_5_5_in_high downto sample_5_5_in_low),
y => hh(ny)(nx)
);
fir_cc: component half_pixel_interpolator_fir port map(
x0 => samples(sample_0_0_in_high downto sample_0_0_in_low),
x1 => samples(sample_1_0_in_high downto sample_1_0_in_low),
x2 => samples(sample_2_0_in_high downto sample_2_0_in_low),
x3 => samples(sample_3_0_in_high downto sample_3_0_in_low),
x4 => samples(sample_4_0_in_high downto sample_4_0_in_low),
x5 => samples(sample_5_0_in_high downto sample_5_0_in_low),
y => cc(ny)(nx)
);
fir_dd: component half_pixel_interpolator_fir port map(
x0 => samples(sample_0_1_in_high downto sample_0_1_in_low),
x1 => samples(sample_1_1_in_high downto sample_1_1_in_low),
x2 => samples(sample_2_1_in_high downto sample_2_1_in_low),
x3 => samples(sample_3_1_in_high downto sample_3_1_in_low),
x4 => samples(sample_4_1_in_high downto sample_4_1_in_low),
x5 => samples(sample_5_1_in_high downto sample_5_1_in_low),
y => dd(ny)(nx)
);
fir_h: component half_pixel_interpolator_fir port map(
x0 => samples(sample_0_2_in_high downto sample_0_2_in_low),
x1 => samples(sample_1_2_in_high downto sample_1_2_in_low),
x2 => samples(sample_2_2_in_high downto sample_2_2_in_low),
x3 => samples(sample_3_2_in_high downto sample_3_2_in_low),
x4 => samples(sample_4_2_in_high downto sample_4_2_in_low),
x5 => samples(sample_5_2_in_high downto sample_5_2_in_low),
y => h(ny)(nx)
);
fir_m: component half_pixel_interpolator_fir port map(
x0 => samples(sample_0_3_in_high downto sample_0_3_in_low),
x1 => samples(sample_1_3_in_high downto sample_1_3_in_low),
x2 => samples(sample_2_3_in_high downto sample_2_3_in_low),
x3 => samples(sample_3_3_in_high downto sample_3_3_in_low),
x4 => samples(sample_4_3_in_high downto sample_4_3_in_low),
x5 => samples(sample_5_3_in_high downto sample_5_3_in_low),
y => m(ny)(nx)
);
fir_ee: component half_pixel_interpolator_fir port map(
x0 => samples(sample_0_4_in_high downto sample_0_4_in_low),
x1 => samples(sample_1_4_in_high downto sample_1_4_in_low),
x2 => samples(sample_2_4_in_high downto sample_2_4_in_low),
x3 => samples(sample_3_4_in_high downto sample_3_4_in_low),
x4 => samples(sample_4_4_in_high downto sample_4_4_in_low),
x5 => samples(sample_5_4_in_high downto sample_5_4_in_low),
y => ee(ny)(nx)
);
fir_ff: component half_pixel_interpolator_fir port map(
x0 => samples(sample_0_5_in_high downto sample_0_5_in_low),
x1 => samples(sample_1_5_in_high downto sample_1_5_in_low),
x2 => samples(sample_2_5_in_high downto sample_2_5_in_low),
x3 => samples(sample_3_5_in_high downto sample_3_5_in_low),
x4 => samples(sample_4_5_in_high downto sample_4_5_in_low),
x5 => samples(sample_5_5_in_high downto sample_5_5_in_low),
y => ff(ny)(nx)
);
-- half pixel interpolation from neighboring half pixel values
fir_j: component half_pixel_interpolator_fir port map(
x0 => aa(ny)(nx),
x1 => bb(ny)(nx),
x2 => b(ny)(nx),
x3 => s(ny)(nx),
x4 => gg(ny)(nx),
x5 => hh(ny)(nx),
y => j(ny)(nx)
);
-- quarter pixel interpolation
avg_a: component avg2 port map(x0 => G_in(ny)(nx), x1 => b(ny)(nx), y => a(ny)(nx));
avg_c: component avg2 port map(x0 => H_in(ny)(nx), x1 => b(ny)(nx), y => c(ny)(nx));
avg_d: component avg2 port map(x0 => G_in(ny)(nx), x1 => h(ny)(nx), y => d(ny)(nx));
avg_e: component avg2 port map(x0 => b(ny)(nx) , x1 => h(ny)(nx), y => e(ny)(nx));
avg_f: component avg2 port map(x0 => b(ny)(nx) , x1 => j(ny)(nx), y => f(ny)(nx));
avg_g: component avg2 port map(x0 => b(ny)(nx) , x1 => m(ny)(nx), y => g(ny)(nx));
avg_i: component avg2 port map(x0 => h(ny)(nx) , x1 => j(ny)(nx), y => i(ny)(nx));
avg_k: component avg2 port map(x0 => j(ny)(nx) , x1 => m(ny)(nx), y => k(ny)(nx));
avg_n: component avg2 port map(x0 => M_in(ny)(nx), x1 => h(ny)(nx), y => n(ny)(nx));
avg_p: component avg2 port map(x0 => h(ny)(nx) , x1 => s(ny)(nx), y => p(ny)(nx));
avg_q: component avg2 port map(x0 => j(ny)(nx) , x1 => s(ny)(nx), y => q(ny)(nx));
avg_r: component avg2 port map(x0 => m(ny)(nx) , x1 => s(ny)(nx), y => r(ny)(nx));
--assign output
y(ny)(nx) <= a(ny)(nx) when sel = x"01" else
b(ny)(nx) when sel = x"02" else
c(ny)(nx) when sel = x"03" else
d(ny)(nx) when sel = x"04" else
e(ny)(nx) when sel = x"05" else
f(ny)(nx) when sel = x"06" else
g(ny)(nx) when sel = x"07" else
h(ny)(nx) when sel = x"08" else
i(ny)(nx) when sel = x"09" else
j(ny)(nx) when sel = x"0A" else
k(ny)(nx) when sel = x"0B" else
n(ny)(nx) when sel = x"0C" else
p(ny)(nx) when sel = x"0D" else
q(ny)(nx) when sel = x"0E" else
r(ny)(nx) when sel = x"0F" else
G_in(ny)(nx) when sel = x"00" else
X"00";
end generate;
end generate;
--result <= y(0)(0) & y(1)(0) & -- y(2)(0) & y(3)(0) &
-- y(0)(1) & y(1)(1) ;--& y(2)(1) & y(3)(1) &
-- --y(0)(2) & y(1)(2) & y(2)(2) & y(3)(2) &
-- --y(0)(3) & y(1)(3) & y(2)(3) & y(3)(3);
result <= y(0)(0) & y(0)(1) & y(0)(2) & y(0)(3) & y(1)(0) & y(1)(1) & y(1)(2) & y(1)(3);
--result <= y(0)(0) & y(1)(0) & y(2)(0) & y(3)(0) &
-- y(0)(1) & y(1)(1) & y(2)(1) & y(3)(1) &
-- y(0)(2) & y(1)(2) & y(2)(2) & y(3)(2) &
-- y(0)(3) & y(1)(3) & y(2)(3) & y(3)(3);
--result <= y(0)(0) & y(0)(1) & y(0)(2) & y(0)(3) & y(0)(4) & y(0)(5) & y(0)(6) & y(0)(7) &
-- y(1)(0) & y(1)(1) & y(1)(2) & y(1)(3) & y(1)(4) & y(1)(5) & y(1)(6) & y(1)(7);
end architecture rtl;
| mit | fd7ee210a7e9da92ed6f94acdf8499d2 | 0.509883 | 3.17715 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/bouton_diode/bouton_diode.vhd | 1 | 985 | -- includes
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY bouton_diode IS
PORT (
-- le bouton
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
B : IN STD_LOGIC;
D : OUT STD_LOGIC
);
END bouton_diode ;
ARCHITECTURE arch OF bouton_diode IS
TYPE STATE_TYPE IS (debut, a0, a1, e0);
SIGNAL state : STATE_TYPE ;
BEGIN
PROCESS(clk,rst)
BEGIN
IF rst='1' THEN
state <= debut ;
ELSIF clk'EVENT AND clk='1' THEN
CASE state IS
WHEN debut =>
IF B='1' THEN
state <= a0 ;
END IF;
WHEN a0 =>
IF B='0' THEN
state <= a1 ;
END IF;
WHEN a1 =>
IF B='1' THEN
state <= e0 ;
END IF;
WHEN e0 =>
IF B='0' THEN
state <= debut ;
END IF;
END CASE ;
END IF;
END PROCESS ;
WITH state SELECT D <=
'0' WHEN debut,
'1' WHEN a0,
'1' WHEN a1,
'0' WHEN OTHERS
;
END arch;
| gpl-3.0 | 3818a959a7360fca86bc338a86cee526 | 0.507614 | 2.880117 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia/wrapper_tick1000.vhd | 1 | 5,198 | -------------------------------------------------------------------------------
--
-- Ce bloc est le wrapper dans le bus ia
--
-- Ce module transfert tous les messages (????,addrsrc,addrdest,data) venant de
-- busin.
--
-- Si addrdest==MYADDR, data est transmis sur busv
-- Sinon, tout le message est transféré sur busout
--
-- Du coté busin, il suit le protocole "poignée de main" (signaux: busin,
-- busin_valid, busin_eated).
--
-- Du coté busout, il suit le protocole "poignée de main" (signaux: busout,
-- busout_valid, busout_eated).
--
-- Tous les 1000 ticks, ce bloc envoit un message au PC
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY wrapper_tick1000 IS
GENERIC(
MYADDR : STD_LOGIC_VECTOR(7 downto 0) := "00001100" -- 12
);
PORT(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- la valeur du tick
T : in STD_LOGIC;
-- interface busin
busin : in STD_LOGIC_VECTOR(43 downto 0);
busin_valid : in STD_LOGIC;
busin_eated : out STD_LOGIC;
-- interface busout
busout : out STD_LOGIC_VECTOR(43 downto 0);
busout_valid : out STD_LOGIC;
busout_eated : in STD_LOGIC
);
END wrapper_tick1000;
ARCHITECTURE montage OF wrapper_tick1000 IS
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
-- Registre de transfert entre busin et busout
type T_CMD_tft is (INIT, NOOP, TICK);
signal CMD_tft : T_CMD_tft ;
signal R_tft : STD_LOGIC_VECTOR (43 downto 0);
type T_CMD_msg is (LOAD, NOOP);
signal CMD_msg : T_CMD_msg ;
-- registre indiquant qu'un message doit être envoyé tous les 1000 ticks ou non
signal R_CHCK : STD_LOGIC;
-- registre comptant le nombre de tick
signal R_CNT : unsigned(9 downto 0);
-- message pingant le PC tous les 1000 ticks
SIGNAL mess_resultat : STD_LOGIC_VECTOR (43 DOWNTO 0);
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- adresse destination
alias busin_addrdest : STD_LOGIC_VECTOR(7 downto 0) is busin(31 downto 24);
type STATE_TYPE is (
ST_READ_BUSIN, ST_WRITE_OUT, ST_LOAD_CHCK, ST_TICK
);
signal state : STATE_TYPE;
BEGIN
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
PROCESS (reset, clk)
BEGIN
-- si on reset
IF reset = '1' THEN
-- on met le compteur à 0
R_CNT <= to_unsigned(0, 10);
ELSIF clk'event AND clk = '1' THEN
-- commandes de transfert bus ia
-- si l'on doit lire le message, on le stocke
-- dans le registre 'R_tft'
IF CMD_tft = INIT THEN
R_tft <= busin ;
END IF;
-- on charge la valeur de 'N'
IF CMD_msg = LOAD THEN
R_CHCK <= R_tft(0);
END IF ;
-- on compte le nombre de tick
IF T = '1' THEN
IF R_CNT = to_unsigned(1000, 10) THEN
R_CNT <= to_unsigned(0, 10);
ELSE
R_CNT <= R_CNT + 1;
END IF;
END IF;
END IF;
END PROCESS;
-- crée le message à envoyer au PC
mess_resultat(43 DOWNTO 40) <= "0000";
mess_resultat(39 DOWNTO 32) <= MYADDR;
mess_resultat(31 DOWNTO 24) <= R_tft(39 DOWNTO 32);
mess_resultat(23 DOWNTO 0) <= "000000000000000000000001";
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: busin_valid, busout_eated, busin_addrdest
-- Outputs: busin_eated, busout_valid, CMD_tft
-------------------------------------------------------------------------------
-- fonction de transitition
PROCESS (reset,clk)
BEGIN
IF reset = '1' THEN
state <= ST_READ_BUSIN;
ELSIF clk'event AND clk = '1' THEN
CASE state IS
WHEN ST_READ_BUSIN =>
IF busin_valid='1' THEN
IF R_CHCK = '1' AND R_CNT = to_unsigned(1000, 10) THEN
state <= ST_TICK;
ELSIF busin_addrdest = MYADDR THEN
state <= ST_LOAD_CHCK;
ELSE
state <= ST_WRITE_OUT ;
END IF ;
END IF ;
WHEN ST_WRITE_OUT =>
IF busout_eated = '1' THEN
state <= ST_READ_BUSIN;
END IF ;
WHEN ST_LOAD_CHCK =>
state <= ST_READ_BUSIN;
WHEN ST_TICK =>
state <= ST_READ_BUSIN;
END CASE;
END IF;
END PROCESS;
-- fonction de sortie
with state select busin_eated <=
'1' when ST_READ_BUSIN,
'0' when others
;
with state select busout_valid <=
'1' when ST_WRITE_OUT,
'1' when ST_TICK,
'0' when others
;
with state select CMD_tft <=
INIT when ST_READ_BUSIN,
NOOP when others
;
with state SELECT busout <=
mess_resultat WHEN ST_TICK,
R_tft WHEN OTHERS
;
with state select CMD_msg <=
LOAD when ST_LOAD_CHCK,
NOOP when others
;
end montage;
| gpl-3.0 | 0ef594bef999d73a969e724d86aa7998 | 0.508779 | 3.609331 | false | false | false | false |
DaveyPocket/btrace448 | btrace/spheregen.vhd | 1 | 1,974 | -- Btrace 448
-- Sphere Generator
--
-- Bradley Boccuzzi
-- 2016
library ieee;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.btrace_pack.all;
-- This is used to test the intersection of a sphere with a ray.
entity sphere_gen is
generic(int, frac: integer := 16);
port(clk: in std_logic;
direction_vector: in vector;
ray_origin: in point;
obj: in object;
result: out std_logic_vector((int+frac)-1 downto 0);
-- Status
obj_hit: out std_logic);
end sphere_gen;
architecture arch of sphere_gen is
signal v: vector;
signal q, dot_self, vv, subr, ex_size: sfixed((2*int)-1 downto -(2*frac));
signal q_inv: sfixed((2*int) downto -(2*frac));
signal mul, q_sq, disc: sfixed((4*int)-1 downto -(4*frac));
signal disc_std, sq_result: std_logic_vector(31 downto 0);
signal resulta: std_logic_vector(32 downto 0);
begin
-- Could be replaced with something more compact.
v.m_x <= (ray_origin.x(14 downto -16) - obj.position.x(14 downto -16));
v.m_y <= (ray_origin.y(14 downto -16) - obj.position.y(14 downto -16));
v.m_z <= (ray_origin.z(14 downto -16) - obj.position.z(14 downto -16));
q_dot: entity work.dot generic map(int, frac) port map(v, direction_vector, q);
dot_self_dot: entity work.dot generic map(int, frac) port map(direction_vector, direction_vector, dot_self);
vv_dt: entity work.dot generic map(int, frac) port map(v, v, vv);
ex_size <= resize(obj.size(15 downto -16), ex_size);
subr <= vv(30 downto -32) - ex_size(30 downto -32);
mul <= subr * dot_self;
q_sq <= q*q;
disc <= q_sq(62 downto -64) - mul(62 downto -64);
disc_std <= std_logic_vector(disc(31 downto 0)); -- not right... but do it anyway
obj_hit <= '1' when disc(63) = '0' else '0';
sq: entity work.squareroot port map(clk, disc_std, sq_result);
q_inv <= -q;
resulta <= std_logic_vector(q_inv((int)-1 downto -(frac)) - to_sfixed(sq_result,15, -16));
result <= resulta(31 downto 0);
end arch;
| gpl-3.0 | 5ceb69205fe22068501c74a5f285eab7 | 0.672746 | 2.715268 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/fifo_buffer.vhd | 2 | 1,830 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_buffer is
generic(
word_len : integer := 64;
buff_len : integer := 8
);
port(
write_data : in std_logic_vector(word_len-1 downto 0);
read_data : out std_logic_vector(word_len-1 downto 0);
buffer_full : out std_logic;
buffer_empty : out std_logic;
enqueue : in std_logic;
dequeue : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end entity fifo_buffer;
architecture behavioral of fifo_buffer is
signal enqueue_pointer : integer;
type buffer_type is array(buff_len-1 downto 0) of std_logic_vector(word_len-1 downto 0);
signal the_buffer : buffer_type;
signal buffer_full_sig : std_logic;
signal buffer_empty_sig : std_logic;
begin
--read/write to buffer
process(clk, rst)
begin
if rst = '1' then
enqueue_pointer <= 0;
the_buffer <= (others => (others => '0'));
elsif rising_edge(clk) then
if enqueue = '1' and buffer_full_sig = '0' then
the_buffer(enqueue_pointer) <= write_data;
enqueue_pointer <= enqueue_pointer + 1;
end if;
if dequeue = '1' and buffer_empty_sig = '0' then
enqueue_pointer <= enqueue_pointer - 1;
the_buffer(buff_len-2 downto 0) <= the_buffer(buff_len-1 downto 1);
end if;
end if;
end process;
--output logic
read_data <= the_buffer(0);
buffer_full_sig <= '0' when enqueue_pointer < buff_len else '1';
buffer_empty_sig <= '0' when enqueue_pointer > 0 else '1';
buffer_full <= buffer_full_sig;
buffer_empty <= buffer_empty_sig;
end architecture behavioral; | mit | 8c3f19dc32bc7ffdd0c96b173071f4a8 | 0.571038 | 3.581213 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/bd/week1/ip/week1_FILTER_IIR_0_0/synth/week1_FILTER_IIR_0_0.vhd | 1 | 9,117 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: tsotnep:userLibrary:FILTER_IIR:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY week1_FILTER_IIR_0_0 IS
PORT (
AUDIO_OUT_L : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
AUDIO_OUT_R : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
FILTER_DONE : OUT STD_LOGIC;
SAMPLE_TRIG : IN STD_LOGIC;
AUDIO_IN_L : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
AUDIO_IN_R : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s00_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END week1_FILTER_IIR_0_0;
ARCHITECTURE week1_FILTER_IIR_0_0_arch OF week1_FILTER_IIR_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF week1_FILTER_IIR_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT FILTER_IIR_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER -- Width of S_AXI address bus
);
PORT (
AUDIO_OUT_L : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
AUDIO_OUT_R : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
FILTER_DONE : OUT STD_LOGIC;
SAMPLE_TRIG : IN STD_LOGIC;
AUDIO_IN_L : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
AUDIO_IN_R : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s00_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT FILTER_IIR_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF week1_FILTER_IIR_0_0_arch: ARCHITECTURE IS "FILTER_IIR_v1_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF week1_FILTER_IIR_0_0_arch : ARCHITECTURE IS "week1_FILTER_IIR_0_0,FILTER_IIR_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
BEGIN
U0 : FILTER_IIR_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 7
)
PORT MAP (
AUDIO_OUT_L => AUDIO_OUT_L,
AUDIO_OUT_R => AUDIO_OUT_R,
FILTER_DONE => FILTER_DONE,
SAMPLE_TRIG => SAMPLE_TRIG,
AUDIO_IN_L => AUDIO_IN_L,
AUDIO_IN_R => AUDIO_IN_R,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END week1_FILTER_IIR_0_0_arch;
| lgpl-3.0 | 7c7081796c59052b385943c0f5ce94f7 | 0.70023 | 3.202318 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/half_pixel_interpolator_fir.vhd | 1 | 1,994 | -- Inter-Prediction Interpolator Filter
-- see ITU Std. 8.4.2.2.1 and 8.4.2.2.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity half_pixel_interpolator_fir is
port(
x0 : in std_logic_vector(7 downto 0);
x1 : in std_logic_vector(7 downto 0);
x2 : in std_logic_vector(7 downto 0);
x3 : in std_logic_vector(7 downto 0);
x4 : in std_logic_vector(7 downto 0);
x5 : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0)
);
end entity half_pixel_interpolator_fir;
architecture dsp of half_pixel_interpolator_fir is
--interpolation equation
--y_1 = x0 -5*x1 + 20*x2 + 20*x3 - 5*x4 + x5
--y = clip1((y_1 + 16)>>5)
signal x0_u : unsigned(31 downto 0);
signal x1_u : unsigned(15 downto 0);
signal x2_u : unsigned(15 downto 0);
signal x3_u : unsigned(15 downto 0);
signal x4_u : unsigned(15 downto 0);
signal x5_u : unsigned(31 downto 0);
signal y_a : unsigned(31 downto 0);
signal y_b : unsigned(31 downto 0);
signal y_c : std_logic_vector(31 downto 0);
begin
x0_u <= unsigned(X"000000" & x0);
x1_u <= unsigned(X"00" & x1);
x2_u <= unsigned(X"00" & x2);
x3_u <= unsigned(X"00" & x3);
x4_u <= unsigned(X"00" & x4);
x5_u <= unsigned(X"000000" & x5);
y_a <= x0_u -
to_unsigned(5, 16) * x1_u +
to_unsigned(20, 16) * x2_u +
to_unsigned(20, 16) * x3_u -
to_unsigned(5, 16) * x4_u +
x5_u;
y_b <= shift_right(y_a, 5);
y_c <= std_logic_vector(y_b);
y <= y_c(7 downto 0) when y_b >= to_unsigned(0, 16) and y_b <= to_unsigned(255, 16) else
std_logic_vector(to_unsigned(0, 8)) when y_b < to_unsigned(0, 16) else
std_logic_vector(to_unsigned(255, 8));
end architecture dsp;
| mit | de3945ba44ca148d26537f227c3f5377 | 0.549649 | 2.757953 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/rs232out/rs232out.vhd | 1 | 6,430 | -- ########################################################################
-- $Software: busiac
-- $section : hardware component
-- $Id: rs232out.vhd 322 2015-05-29 06:43:59Z ia $
-- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/rs232out.vhd $
-- $Author : Ivan Auge (Email: [email protected])
-- ########################################################################
--
-- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge.
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- BUSIAC software is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY ; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-- Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with the GNU C Library; see the file COPYING. If not, write to the Free
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
-- ######################################################################*/
-------------------------------------------------------------------------------
-- ATTENTION:
-- Ceci un template, les trous marqués "..." doivent être comblés pour
-- pouvoir être compilé, puis fonctionné.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Ce module sérialise l'entrée DATA de 8 bits sur la sortie TX.
--
-- le format écrit est:
-- - 1 start bit
-- - 8 bit de données
-- - 1 stop bits
--
-- La sortie BUSY indique que le module est en train de sérialiser.
--
-- Pour sérialiser une nouvelle valeur, il faut:
-- * attendre que BUSY soit nul.
-- * la positionner sur DATA et mettre NDATA à 1 au moins 1 cycle.
--
-- Pour fixer le BAUD du composant utilisez les paramètres génériques
-- BAUD et FREQ ci dessous.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity rs232out is
generic(
FREQ : integer := 50000000; -- Frequence de clk
BAUD : integer := 9600); -- Baud de Rx
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
Tx : out STD_LOGIC;
Data : in STD_LOGIC_VECTOR(7 downto 0);
Ndata : in STD_LOGIC;
Busy : out STD_LOGIC);
end rs232out;
architecture montage of rs232out is
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
type T_CMD_i is (NOOP, COUNT, INIT);
signal CMD_i : T_CMD_i ;
signal R_i : integer RANGE 0 TO 15;
signal VT_endLoop: STD_LOGIC;
type T_CMD_baud is (NOOP, COUNT, INIT);
signal CMD_baud : T_CMD_baud ;
signal R_baud: integer RANGE 0 TO (FREQ)/BAUD;
signal VT_endbaud: STD_LOGIC;
type T_CMD_data is (NOOP, SHIFT, INIT);
signal CMD_data : T_CMD_data ;
signal R_data : STD_LOGIC_VECTOR(8 downto 0); -- 0 : 1 start bit
-- 8:1 : 8 data bits
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
--Description des états
type STATE_TYPE is (ST_BEGIN, ST_FOR, ST_ATT, ST_ADV);
signal state : STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
process (clk)
begin if clk'event and clk = '1' then
-- R_i
if ( CMD_i = INIT ) then
R_i <= 11 ;
elsif ( CMD_i = COUNT ) then
R_i <= R_i - 1;
else
R_i <= R_i;
end if;
-- R_baud
if ( CMD_baud = INIT ) then
R_baud <= FREQ/BAUD ;
elsif ( CMD_baud = COUNT ) then
R_baud <= R_baud - 1;
else
R_baud <= R_baud;
end if;
-- R_data
if ( CMD_data = INIT ) then
-- V = E + '0'
R_data(8 downto 1) <= Data;
R_data(0) <= '0';
elsif ( CMD_data = SHIFT ) then
-- v = '1' + (v >> 1)
R_data(7 downto 0) <= R_data(8 downto 1);
R_data(8) <= '1';
else
R_data <= R_data;
end if ;
end if; end process;
VT_endbaud <= '1' WHEN R_Baud = 0 ELSE '0' ;
VT_endLoop <= '1' WHEN R_i = 0 ELSE '0' ;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: Ndata VT_endLoop VT_endBaud
-- Outputs: Tx Busy CMD_i CMD_baud CMD_data
-------------------------------------------------------------------------------
-- fonction de transitition
process (reset,clk)
begin
if reset = '1' then
state <= ST_BEGIN;
elsif clk'event and clk = '1' then
case state is
when ST_BEGIN =>
-- si go, alors on commence à serialiser
if Ndata = '0' then
state <= ST_FOR;
end if;
when ST_FOR =>
if VT_endLoop = '1' then
state <= ST_BEGIN;
else
state <= ST_ATT;
end if;
when ST_ATT =>
if VT_endbaud = '1' then
state <= ST_ADV;
end if;
when ST_ADV =>
state <= ST_FOR;
end case;
end if;
end process;
-- fonction de sortie
with state select tx <=
'1' when ST_BEGIN,
R_Data(0) when others
;
with state select busy <=
'0' when ST_BEGIN,
'1' when others
;
with state select CMD_i <=
INIT when ST_BEGIN,
COUNT when ST_ADV,
NOOP when others
;
with state select CMD_baud <=
COUNT when ST_ATT,
INIT when others
;
with state select CMD_data <=
INIT when ST_BEGIN,
SHIFT when ST_ADV,
NOOP when others
;
end montage;
| gpl-3.0 | 6bfe3b018d37772535089aac4e64ac63 | 0.453184 | 3.955556 | false | false | false | false |
peladex/RHD2132_FPGA | quartus/test_spi_de0/hex27seg.vhd | 1 | 3,043 | ---------------------------------------------------------
-- hex27seg
-- creacion 20/08/16
-- modificado de bcd27seg
-- seg_out(6 downto 0)= abcdefg
---------------------------------------------------------
-----------------------------------------------------------
----- PACKAGE pk_bcd27seg
-----------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
PACKAGE pk_hex27seg IS
COMPONENT hex27seg IS
PORT(
hex_in : IN STD_LOGIC_VECTOR(3 downto 0);
seg_out : OUT STD_LOGIC_VECTOR(6 downto 0)
);
END COMPONENT;
END PACKAGE;
-----------------------------------------------------------
----- ENTITY bcd27seg
-----------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY hex27seg IS
PORT(
hex_in : IN STD_LOGIC_VECTOR(3 downto 0);
seg_out : OUT STD_LOGIC_VECTOR(6 downto 0)
);
END hex27seg;
ARCHITECTURE synth of hex27seg IS
--constants
-- "abcdefg"
CONSTANT cero : std_logic_vector(6 DOWNTO 0):= "0000001";
CONSTANT uno : std_logic_vector(6 DOWNTO 0):= "1001111";
CONSTANT dos : std_logic_vector(6 DOWNTO 0):= "0010010";
CONSTANT tres : std_logic_vector(6 DOWNTO 0):= "0000110";
CONSTANT cuatro : std_logic_vector(6 DOWNTO 0):= "1001100";
CONSTANT cinco : std_logic_vector(6 DOWNTO 0):= "0100100";
CONSTANT seis : std_logic_vector(6 DOWNTO 0):= "0100000";
CONSTANT siete : std_logic_vector(6 DOWNTO 0):= "0001101";
CONSTANT ocho : std_logic_vector(6 DOWNTO 0):= "0000000";
CONSTANT nueve : std_logic_vector(6 DOWNTO 0):= "0000100";
CONSTANT A : std_logic_vector(6 DOWNTO 0):= "0001000";
CONSTANT b : std_logic_vector(6 DOWNTO 0):= "1100000";
CONSTANT C : std_logic_vector(6 DOWNTO 0):= "0110001";
CONSTANT d : std_logic_vector(6 DOWNTO 0):= "1000010";
CONSTANT E : std_logic_vector(6 DOWNTO 0):= "0110000";
CONSTANT F : std_logic_vector(6 DOWNTO 0):= "0111000";
BEGIN
--***********
seg_decoder:
--***********
PROCESS (hex_in)
BEGIN
CASE hex_in IS
WHEN X"0" =>
seg_out <= cero;
WHEN X"1" =>
seg_out <= uno;
WHEN X"2" =>
seg_out <= dos;
WHEN X"3" =>
seg_out <= tres;
WHEN X"4" =>
seg_out <= cuatro;
WHEN X"5" =>
seg_out <= cinco;
WHEN X"6" =>
seg_out <= seis;
WHEN X"7" =>
seg_out <= siete;
WHEN X"8" =>
seg_out <= ocho;
WHEN X"9" =>
seg_out <= nueve;
WHEN X"A" =>
seg_out <= A;
WHEN X"B" =>
seg_out <= b;
WHEN X"C" =>
seg_out <= C;
WHEN X"D" =>
seg_out <= d;
WHEN X"E" =>
seg_out <= E;
WHEN X"F" =>
seg_out <= F;
END CASE;
END PROCESS;
END synth;
| gpl-3.0 | a983e9a24cf7ab4b56b3e6a12a0f5065 | 0.482419 | 3.461889 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/tsotnep/filter_iir_v1_0/263d46e2/hdl/FILTER_IIR_v1_0.vhd | 2 | 4,872 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FILTER_IIR_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic;
SAMPLE_TRIG : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end FILTER_IIR_v1_0;
architecture arch_imp of FILTER_IIR_v1_0 is
-- component declaration
component FILTER_IIR_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 7
);
port (
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic;
SAMPLE_TRIG : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component FILTER_IIR_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
FILTER_IIR_v1_0_S00_AXI_inst : FILTER_IIR_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
AUDIO_OUT_L => AUDIO_OUT_L,
AUDIO_OUT_R => AUDIO_OUT_R,
FILTER_DONE => FILTER_DONE,
SAMPLE_TRIG => SAMPLE_TRIG,
AUDIO_IN_L => AUDIO_IN_L,
AUDIO_IN_R => AUDIO_IN_R,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
| lgpl-3.0 | 0ff4503e03beac0e5121fcef00ff59f8 | 0.605296 | 2.637791 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/bd/week1/ip/week1_FILTER_IIR_0_1/synth/week1_FILTER_IIR_0_1.vhd | 1 | 9,117 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: tsotnep:userLibrary:FILTER_IIR:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY week1_FILTER_IIR_0_1 IS
PORT (
AUDIO_OUT_L : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
AUDIO_OUT_R : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
FILTER_DONE : OUT STD_LOGIC;
SAMPLE_TRIG : IN STD_LOGIC;
AUDIO_IN_L : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
AUDIO_IN_R : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s00_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END week1_FILTER_IIR_0_1;
ARCHITECTURE week1_FILTER_IIR_0_1_arch OF week1_FILTER_IIR_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF week1_FILTER_IIR_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT FILTER_IIR_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER -- Width of S_AXI address bus
);
PORT (
AUDIO_OUT_L : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
AUDIO_OUT_R : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
FILTER_DONE : OUT STD_LOGIC;
SAMPLE_TRIG : IN STD_LOGIC;
AUDIO_IN_L : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
AUDIO_IN_R : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s00_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT FILTER_IIR_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF week1_FILTER_IIR_0_1_arch: ARCHITECTURE IS "FILTER_IIR_v1_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF week1_FILTER_IIR_0_1_arch : ARCHITECTURE IS "week1_FILTER_IIR_0_1,FILTER_IIR_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
BEGIN
U0 : FILTER_IIR_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 7
)
PORT MAP (
AUDIO_OUT_L => AUDIO_OUT_L,
AUDIO_OUT_R => AUDIO_OUT_R,
FILTER_DONE => FILTER_DONE,
SAMPLE_TRIG => SAMPLE_TRIG,
AUDIO_IN_L => AUDIO_IN_L,
AUDIO_IN_R => AUDIO_IN_R,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END week1_FILTER_IIR_0_1_arch;
| lgpl-3.0 | cb9e268d974bfdc6ae5ac1bd89e7dc7d | 0.70023 | 3.202318 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/user.org/zed_audio_v1_0/8de2dafc/hdl/i2s_data_interface.vhd | 2 | 3,225 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: i2s_data_interface - Behavioral
-- Description: Send & Receive I2S data
-- New_sample is asserted for one cycle when a new sample has been
-- received (and one transmitted)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2s_data_interface is
Port ( clk : in STD_LOGIC;
audio_l_in : in STD_LOGIC_VECTOR (23 downto 0);
audio_r_in : in STD_LOGIC_VECTOR (23 downto 0);
audio_l_out : out STD_LOGIC_VECTOR (23 downto 0);
audio_r_out : out STD_LOGIC_VECTOR (23 downto 0);
new_sample : out STD_LOGIC;
i2s_bclk : in STD_LOGIC;
i2s_d_out : out STD_LOGIC;
i2s_d_in : in STD_LOGIC;
i2s_lr : in STD_LOGIC);
end i2s_data_interface;
architecture Behavioral of i2s_data_interface is
signal bit_counter : unsigned(5 downto 0) := (others => '0');
signal bclk_delay : std_logic_vector(9 downto 0) := (others => '0');
signal lr_delay : std_logic_vector(9 downto 0) := (others => '0');
signal sr_in : std_logic_vector(126 downto 0) := (others => '0');
signal sr_out : std_logic_vector(63 downto 0) := (others => '0');
signal i2s_lr_last : std_logic := '0';
signal i2s_d_in_last : std_logic := '0';
begin
process(clk)
begin
-- Process to predict when the falling edge of i2s_bclk should be
if rising_edge(clk) then
new_sample <= '0';
------------------------------
-- is there a rising edge two cycles ago? If so the data bit is
-- validand we can capture a bit
------------------------------
if bclk_delay(bclk_delay'high-1 downto bclk_delay'high-2) = "10" then
sr_in <= sr_in(sr_in'high-1 downto 0) & i2s_d_in_last;
end if;
------------------------------
-- Was there a rising edge on BCLK 9 cycles ago?
-- If so, this should be about the falling edge so
-- the output can change.
------------------------------
if bclk_delay(1 downto 0) = "10" then
i2s_d_out <= sr_out(sr_out'high);
-- if we are starting a new frame, then load the samples into the shift register
if i2s_lr = '1' and i2s_lr_last = '0' then
audio_l_out <= sr_in(sr_in'high downto sr_in'high-23);
audio_r_out <= sr_in(sr_in'high-32 downto sr_in'high-23-32);
sr_out <= audio_l_in & x"00" & audio_r_in & x"00";
new_sample <= '1';
else
sr_out <= sr_out(sr_out'high-1 downto 0) & '0';
end if;
-- remember what lr was, for edge detection
i2s_lr_last <= i2s_lr;
end if;
bclk_delay <= i2s_bclk & bclk_delay(bclk_delay'high downto 1);
i2s_d_in_last <= i2s_d_in;
end if;
end process;
end Behavioral; | lgpl-3.0 | dd1d00e3312223f0b06cf4d963f0d48b | 0.490853 | 3.575388 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/vga_node.vhd | 1 | 13,778 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity vga_node is
generic(
data_width : integer := 64;
addr_width : integer := 4;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
-- vga connections
clk27 : in std_logic;
rst27 : in std_logic;
vga_red : out std_logic_vector(5 downto 0);
vga_blue : out std_logic_vector(5 downto 0);
vga_green : out std_logic_vector(5 downto 0);
vga_v_sync : out std_logic;
vga_h_sync : out std_logic
);
end entity vga_node;
architecture fsmd of vga_node is
--- Components ------------------------------------------------------------
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
component vga_controller is
generic(
h_pulse : integer := 208; --horiztonal sync pulse width in pixels
h_bp : integer := 336; --horiztonal back porch width in pixels
h_pixels : integer := 1920; --horiztonal display width in pixels
h_fp : integer := 128; --horiztonal front porch width in pixels
h_pol : std_logic := '0'; --horizontal sync pulse polarity (1 = positive, 0 = negative)
v_pulse : integer := 3; --vertical sync pulse width in rows
v_bp : integer := 38; --vertical back porch width in rows
v_pixels : integer := 1200; --vertical display width in rows
v_fp : integer := 1; --vertical front porch width in rows
v_pol : std_logic := '1'); --vertical sync pulse polarity (1 = positive, 0 = negative)
port(
pixel_clk : in std_logic; --pixel clock at frequency of vga mode being used
reset_n : in std_logic; --active low asycnchronous reset
h_sync : out std_logic; --horiztonal sync pulse
v_sync : out std_logic; --vertical sync pulse
disp_ena : out std_logic; --display enable ('1' = display time, '0' = blanking time)
column : out integer; --horizontal pixel coordinate
row : out integer; --vertical pixel coordinate
n_blank : out std_logic; --direct blacking output to dac
n_sync : out std_logic); --sync-on-green output to dac
end component vga_controller;
component ram_dual is
generic
(
ram_width : integer := 24;
ram_depth : integer := 65536
);
port
(
clock1 : in std_logic;
clock2 : in std_logic;
data : in std_logic_vector(ram_width-1 downto 0);
write_address : in integer;
read_address : in integer;
we : in std_logic;
q : out std_logic_vector(ram_width-1 downto 0)
);
end component ram_dual;
component ycbcr_to_rgb is
port(
clk : in std_logic;
y : in std_logic_vector(7 downto 0);
cb : in std_logic_vector(7 downto 0);
cr : in std_logic_vector(7 downto 0);
red : out std_logic_vector(7 downto 0);
green : out std_logic_vector(7 downto 0);
blue : out std_logic_vector(7 downto 0)
);
end component ycbcr_to_rgb;
--- Constants -------------------------------------------------------------
constant rgb_size : integer := 6;
constant horizontal : integer := 320;
constant vertical : integer := 200;
constant addr_size : integer := 19;
--- Types -----------------------------------------------------------------
type vga_node_states is (idle,
sel_vc,
rx,
convert_0,
wr_rgb_0,
convert_1,
wr_rgb_1,
dequeue_flit
);
--- signals and registers -------------------------------------------------
signal state : vga_node_states;
signal next_state : vga_node_states;
signal convert_counter_d : unsigned(7 downto 0);
signal convert_counter_q : unsigned(7 downto 0);
signal red_in : std_logic_vector(rgb_size-1 downto 0);
signal green_in : std_logic_vector(rgb_size-1 downto 0);
signal blue_in : std_logic_vector(rgb_size-1 downto 0);
signal wr_addr : integer;
signal wr_enable : std_logic;
signal red_out : std_logic_vector(rgb_size-1 downto 0);
signal green_out : std_logic_vector(rgb_size-1 downto 0);
signal blue_out : std_logic_vector(rgb_size-1 downto 0);
signal rd_addr : integer;
signal y : std_logic_vector(7 downto 0);
signal cb : std_logic_vector(7 downto 0);
signal cr : std_logic_vector(7 downto 0);
signal red : std_logic_vector(7 downto 0);
signal green : std_logic_vector(7 downto 0);
signal blue : std_logic_vector(7 downto 0);
signal r : std_logic_vector(9 downto 0);
signal g : std_logic_vector(9 downto 0);
signal b : std_logic_vector(9 downto 0);
signal current_x : integer;
signal current_y : integer;
signal request : std_logic;
signal vga_r : std_logic_vector(9 downto 0);
signal vga_g : std_logic_vector(9 downto 0);
signal vga_b : std_logic_vector(9 downto 0);
signal vga_hs : std_logic;
signal vga_vs : std_logic;
signal vga_blank : std_logic;
signal vga_clock : std_logic;
signal rd_addr_32 : std_logic_vector(31 downto 0);
signal sel_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_enc : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_one_hot : std_logic_vector(num_vc-1 downto 0);
signal rgb_read : std_logic_vector(3*rgb_size-1 downto 0);
signal disp_ena : std_logic;
begin
---------------------------------------------------------------------------
--- DATAPATH --------------------------------------------------------------
---------------------------------------------------------------------------
--components
u0: component priority_encoder
generic map(
encoded_word_size => vc_sel_width
)
Port map(
input => data_in_buffer,
output => sel_vc_enc
);
red_ram: component ram_dual
generic map
(
ram_width => 6,
ram_depth => horizontal*vertical
)
port map
(
clock1 => clk,
clock2 => clk27,
data => red_in,
write_address => wr_addr,
read_address => rd_addr,
we => wr_enable,
q => red_out
);
blue_ram: component ram_dual
generic map
(
ram_width => 6,
ram_depth => horizontal*vertical
)
port map
(
clock1 => clk,
clock2 => clk27,
data => blue_in,
write_address => wr_addr,
read_address => rd_addr,
we => wr_enable,
q => blue_out
);
green_ram: component ram_dual
generic map
(
ram_width => 6,
ram_depth => horizontal*vertical
)
port map
(
clock1 => clk,
clock2 => clk27,
data => green_in,
write_address => wr_addr,
read_address => rd_addr,
we => wr_enable,
q => green_out
);
u2: component ycbcr_to_rgb
port map(
clk => clk ,
y => y ,
cb => cb ,
cr => cr ,
red => red ,
green => green,
blue => blue
);
u3: component vga_controller
generic map(
h_pulse => 96,
h_bp => 48,
h_pixels => 640,
h_fp => 16,
h_pol => '0',
v_pulse => 2,
v_bp => 35,
v_pixels => 400,
v_fp => 12,
v_pol => '1'
)
port map(
pixel_clk => clk27,
reset_n => not rst27,
h_sync => vga_hs,
v_sync => vga_vs,
column => current_x,
row => current_y,
disp_ena => disp_ena
);
rd_addr <= (current_x mod horizontal) +
(current_y mod vertical ) * horizontal;
vga_red <= red_out when disp_ena = '1' else "000000"; --red_out;
vga_blue <= blue_out when disp_ena = '1' else "000000"; --green_out;
vga_green <= green_out when disp_ena = '1' else "000000"; --blue_out;
vga_v_sync <= vga_vs;
vga_h_sync <= vga_hs;
y <= recv_data(63 downto 56) when state = convert_0 else recv_data(39 downto 32);
cb <= recv_data(55 downto 48) when state = convert_0 else recv_data(31 downto 24);
cr <= recv_data(47 downto 40) when state = convert_0 else recv_data(23 downto 16);
red_in <= red(7 downto 2);
green_in <= green(7 downto 2);
blue_in <= blue(7 downto 2);
wr_addr <= to_integer(unsigned(recv_data(15 downto 0))) when state = wr_rgb_0 or state = convert_0 else
to_integer(unsigned(recv_data(15 downto 0))) + 1;
wr_enable <= '1' when state = wr_rgb_0 else
'1' when state = wr_rgb_1 else
'0';
--counter for coversion wait states
convert_counter_d <= convert_counter_q + to_unsigned(1, 8) when state = convert_0 else
convert_counter_q + to_unsigned(1, 8) when state = convert_1 else
to_unsigned(0, 8);
process(clk, rst)
begin
if rst = '1' then
sel_vc_q <= (others => '0');
convert_counter_q <= (others => '0');
elsif rising_edge(clk) then
convert_counter_q <= convert_counter_d;
sel_vc_q <= sel_vc_d;
end if;
end process;
--packet generation
send_data <= (others => '0');
dest_addr <= (others => '0');
set_tail_flit <= '0';
send_flit <= '0';
--rx controls
sel_vc_d <= sel_vc_enc when state = sel_vc else sel_vc_q;
dequeue <= sel_vc_one_hot when state = dequeue_flit else "00";
select_vc_read <= sel_vc_q;
sel_vc_one_hot <= "01" when sel_vc_q = "0" else "10";
---------------------------------------------------------------------------
--- STATE MACHINE ---------------------------------------------------------
---------------------------------------------------------------------------
process(clk, rst)
begin
if rst = '1' then
state <= idle;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;
process(state, data_in_buffer, is_tail_flit, sel_vc_one_hot, ready_to_send, convert_counter_q)
begin
next_state <= state;
if state = idle and or_reduce(data_in_buffer) = '1' then
next_state <= sel_vc;
end if;
if state = sel_vc then
next_state <= rx;
end if;
if state = rx then
next_state <= convert_0;
end if;
if state = convert_0 and convert_counter_q > to_unsigned(2, 8) then
next_state <= wr_rgb_0;
end if;
if state = wr_rgb_0 then
next_state <= convert_1;
end if;
if state = convert_1 and convert_counter_q > to_unsigned(2, 8) then
next_state <= wr_rgb_1;
end if;
if state = wr_rgb_1 then
next_state <= dequeue_flit;
end if;
if state = dequeue_flit then
next_state <= idle;
end if;
end process;
end architecture;
| mit | 47e1ff81bf3369efca3c80a9db454b8b | 0.465597 | 3.958058 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/bd/week1/ipshared/xilinx.com/lib_cdc_v1_0/3c38df9f/hdl/src/vhdl/cdc_sync.vhd | 21 | 47,317 |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Used to transfer level
-- signal. Input signal should change only when prmry_ack is detected
--
--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
-- Set to 0 when incoming signal is purely floped signal.
--
--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
-- it might be needed.
-- 0 means reset not needed for sync flops
-- 1 means reset needed for sync flops. i
-- In this case prmry_resetn should be in prmry clock,
-- while scndry_reset should be in scndry clock.
--
--C_SINGLE_BIT : CDC should normally be done for single bit signals only.
-- However, based on design buses can also be CDC'ed.
-- 0 means it is a bus. In this case input be connected to prmry_vect_in.
-- Output is on scndry_vect_out.
-- 1 means it is a single bit. In this case input be connected to prmry_in.
-- Output is on scndry_out.
--
--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
--
--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
-- Value of 0, 1 is allowed only for level CDC.
-- Min value for Pulse CDC is 2
--
--Whenever this file is used following XDC constraint has to be added
-- set_false_path -to [get_pins -hier *cdc_to*/D]
--IO Ports
--
-- prmry_aclk : clock of originating domain (source domain)
-- prmry_resetn : sync reset of originating clock domain (source domain)
-- prmry_in : input signal bit. This should be a pure flop output without
-- any combi logic. This is source.
-- prmry_vect_in : bus signal. From Source domain.
-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain.
-- Used only when C_CDC_TYPE = 2
-- scndry_aclk : destination clock.
-- scndry_resetn : sync reset of destination domain
-- scndry_out : sync'ed output in destination domain. Single bit.
-- scndry_vect_out : sync'ed output in destination domain. bus.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.FDR;
entity cdc_sync is
generic (
C_CDC_TYPE : integer range 0 to 2 := 1 ;
-- 0 is pulse synch
-- 1 is level synch
-- 2 is ack based level sync
C_RESET_STATE : integer range 0 to 1 := 0 ;
-- 0 is reset not needed
-- 1 is reset needed
C_SINGLE_BIT : integer range 0 to 1 := 1 ;
-- 0 is bus input
-- 1 is single bit input
C_FLOP_INPUT : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
C_MTBF_STAGES : integer range 0 to 6 := 2
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
prmry_in : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_ack : out std_logic ;
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Primary to Secondary Clock Crossing --
scndry_out : out std_logic ; --
--
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end cdc_sync;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of cdc_sync is
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
--attribute DONT_TOUCH : STRING;
--attribute KEEP : STRING;
--attribute DONT_TOUCH of implementation : architecture is "yes";
signal prmry_resetn1 : std_logic := '0';
signal scndry_resetn1 : std_logic := '0';
signal prmry_reset2 : std_logic := '0';
signal scndry_reset2 : std_logic := '0';
--attribute KEEP of prmry_resetn1 : signal is "true";
--attribute KEEP of scndry_resetn1 : signal is "true";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
HAS_RESET : if C_RESET_STATE = 1 generate
begin
prmry_resetn1 <= prmry_resetn;
scndry_resetn1 <= scndry_resetn;
end generate HAS_RESET;
HAS_NO_RESET : if C_RESET_STATE = 0 generate
begin
prmry_resetn1 <= '1';
scndry_resetn1 <= '1';
end generate HAS_NO_RESET;
prmry_reset2 <= not prmry_resetn1;
scndry_reset2 <= not scndry_resetn1;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true";
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_d5 : std_logic := '0';
signal s_out_d6 : std_logic := '0';
signal s_out_d7 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
--------------------------------------REG_P_IN : process(prmry_aclk)
-------------------------------------- begin
-------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
-------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
-------------------------------------- p_in_d1_cdc_from <= '0';
-------------------------------------- else
-------------------------------------- p_in_d1_cdc_from <= prmry_in_xored;
-------------------------------------- end if;
-------------------------------------- end if;
-------------------------------------- end process REG_P_IN;
REG_P_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in_xored,
R => prmry_reset2
);
REG_P_IN2_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d1_cdc_to,
C => scndry_aclk,
D => p_in_d1_cdc_from,
R => scndry_reset2
);
------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk)
------------------------------------ begin
------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------ s_out_d2 <= '0';
------------------------------------ s_out_d3 <= '0';
------------------------------------ s_out_d4 <= '0';
------------------------------------ s_out_d5 <= '0';
------------------------------------ s_out_d6 <= '0';
------------------------------------ s_out_d7 <= '0';
------------------------------------ scndry_out <= '0';
------------------------------------ else
------------------------------------ s_out_d2 <= s_out_d1_cdc_to;
------------------------------------ s_out_d3 <= s_out_d2;
------------------------------------ s_out_d4 <= s_out_d3;
------------------------------------ s_out_d5 <= s_out_d4;
------------------------------------ s_out_d6 <= s_out_d5;
------------------------------------ s_out_d7 <= s_out_d6;
------------------------------------ scndry_out <= s_out_re;
------------------------------------ end if;
------------------------------------ end if;
------------------------------------ end process P_IN_CROSS2SCNDRY;
P_IN_CROSS2SCNDRY_s_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d2,
C => scndry_aclk,
D => s_out_d1_cdc_to,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d3,
C => scndry_aclk,
D => s_out_d2,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d4,
C => scndry_aclk,
D => s_out_d3,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d5,
C => scndry_aclk,
D => s_out_d4,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d6,
C => scndry_aclk,
D => s_out_d5,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d7,
C => scndry_aclk,
D => s_out_d6,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_scndry_out : component FDR
generic map(INIT => '0'
)port map (
Q => scndry_out,
C => scndry_aclk,
D => s_out_re,
R => scndry_reset2
);
MTBF_2 : if C_MTBF_STAGES = 2 generate
begin
s_out_re <= s_out_d2 xor s_out_d3;
end generate MTBF_2;
MTBF_3 : if C_MTBF_STAGES = 3 generate
begin
s_out_re <= s_out_d3 xor s_out_d4;
end generate MTBF_3;
MTBF_4 : if C_MTBF_STAGES = 4 generate
begin
s_out_re <= s_out_d4 xor s_out_d5;
end generate MTBF_4;
MTBF_5 : if C_MTBF_STAGES = 5 generate
begin
s_out_re <= s_out_d5 xor s_out_d6;
end generate MTBF_5;
MTBF_6 : if C_MTBF_STAGES = 6 generate
begin
s_out_re <= s_out_d6 xor s_out_d7;
end generate MTBF_6;
-- Feed secondary pulse out
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
begin
-- Primary to Secondary
SINGLE_BIT : if C_SINGLE_BIT = 1 generate
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
---------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
---------------------------------- begin
---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
---------------------------------- p_level_in_d1_cdc_from <= '0';
---------------------------------- else
---------------------------------- p_level_in_d1_cdc_from <= prmry_in;
---------------------------------- end if;
---------------------------------- end if;
---------------------------------- end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------ begin
------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------ s_level_out_d2 <= '0';
------------------------------ s_level_out_d3 <= '0';
------------------------------ s_level_out_d4 <= '0';
------------------------------ s_level_out_d5 <= '0';
------------------------------ s_level_out_d6 <= '0';
------------------------------ else
------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------ end if;
------------------------------ end if;
------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_out <= s_level_out_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_out <= s_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out <= s_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out <= s_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out <= s_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out <= s_level_out_d6;
end generate MTBF_L6;
end generate SINGLE_BIT;
MULTI_BIT : if C_SINGLE_BIT = 0 generate
signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0);
signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
--attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true";
signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_out <= '0';
prmry_ack <= '0';
INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate
begin
----------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
----------------------------------- begin
----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0');
----------------------------------- else
----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in;
----------------------------------- end if;
----------------------------------- end if;
----------------------------------- end process REG_PLEVEL_IN;
FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate
begin
REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_bus_d1_cdc_from (i),
C => prmry_aclk,
D => prmry_vect_in (i),
R => prmry_reset2
);
end generate FOR_REG_PLEVEL_IN;
p_level_in_bus_int <= p_level_in_bus_d1_cdc_from;
end generate INPUT_FLOP_BUS;
NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate
begin
p_level_in_bus_int <= prmry_vect_in;
end generate NO_INPUT_FLOP_BUS;
FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d1_cdc_to (i),
C => scndry_aclk,
D => p_level_in_bus_int (i),
R => scndry_reset2
);
end generate FOR_IN_cdc_to;
----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
----------------------------------------- begin
----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then
----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------------- s_level_out_bus_d2 <= (others => '0');
----------------------------------------- s_level_out_bus_d3 <= (others => '0');
----------------------------------------- s_level_out_bus_d4 <= (others => '0');
----------------------------------------- s_level_out_bus_d5 <= (others => '0');
----------------------------------------- s_level_out_bus_d6 <= (others => '0');
----------------------------------------- else
----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to;
----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2;
----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3;
----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4;
----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5;
----------------------------------------- end if;
----------------------------------------- end if;
----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d2 (i),
C => scndry_aclk,
D => s_level_out_bus_d1_cdc_to (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d3 (i),
C => scndry_aclk,
D => s_level_out_bus_d2 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d4 (i),
C => scndry_aclk,
D => s_level_out_bus_d3 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d5 (i),
C => scndry_aclk,
D => s_level_out_bus_d4 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d6 (i),
C => scndry_aclk,
D => s_level_out_bus_d5 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6;
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_vect_out <= s_level_out_bus_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_vect_out <= s_level_out_bus_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_vect_out <= s_level_out_bus_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_vect_out <= s_level_out_bus_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_vect_out <= s_level_out_bus_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_vect_out <= s_level_out_bus_d6;
end generate MTBF_L6;
end generate MULTI_BIT;
end generate GENERATE_LEVEL_P_S_CDC;
GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true";
signal p_level_out_d2 : std_logic := '0';
signal p_level_out_d3 : std_logic := '0';
signal p_level_out_d4 : std_logic := '0';
signal p_level_out_d5 : std_logic := '0';
signal p_level_out_d6 : std_logic := '0';
signal p_level_out_d7 : std_logic := '0';
signal scndry_out_int : std_logic := '0';
signal prmry_pulse_ack : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk)
------------------------------------------ begin
------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then
------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------ p_level_in_d1_cdc_from <= '0';
------------------------------------------ else
------------------------------------------ p_level_in_d1_cdc_from <= prmry_in;
------------------------------------------ end if;
------------------------------------------ end if;
------------------------------------------ end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------------------------ begin
------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------------ s_level_out_d2 <= '0';
------------------------------------------------ s_level_out_d3 <= '0';
------------------------------------------------ s_level_out_d4 <= '0';
------------------------------------------------ s_level_out_d5 <= '0';
------------------------------------------------ s_level_out_d6 <= '0';
------------------------------------------------ else
------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------------------------ end if;
------------------------------------------------ end if;
------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
--------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
--------------------------------------------------- begin
--------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
--------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
--------------------------------------------------- p_level_out_d1_cdc_to <= '0';
--------------------------------------------------- p_level_out_d2 <= '0';
--------------------------------------------------- p_level_out_d3 <= '0';
--------------------------------------------------- p_level_out_d4 <= '0';
--------------------------------------------------- p_level_out_d5 <= '0';
--------------------------------------------------- p_level_out_d6 <= '0';
--------------------------------------------------- p_level_out_d7 <= '0';
--------------------------------------------------- prmry_ack <= '0';
--------------------------------------------------- else
--------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int;
--------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to;
--------------------------------------------------- p_level_out_d3 <= p_level_out_d2;
--------------------------------------------------- p_level_out_d4 <= p_level_out_d3;
--------------------------------------------------- p_level_out_d5 <= p_level_out_d4;
--------------------------------------------------- p_level_out_d6 <= p_level_out_d5;
--------------------------------------------------- p_level_out_d7 <= p_level_out_d6;
--------------------------------------------------- prmry_ack <= prmry_pulse_ack;
--------------------------------------------------- end if;
--------------------------------------------------- end if;
--------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY;
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d1_cdc_to,
C => prmry_aclk,
D => scndry_out_int,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d2,
C => prmry_aclk,
D => p_level_out_d1_cdc_to,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d3,
C => prmry_aclk,
D => p_level_out_d2,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d4,
C => prmry_aclk,
D => p_level_out_d3,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d5,
C => prmry_aclk,
D => p_level_out_d4,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d6,
C => prmry_aclk,
D => p_level_out_d5,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d7,
C => prmry_aclk,
D => p_level_out_d6,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR
generic map(INIT => '0'
)port map (
Q => prmry_ack,
C => prmry_aclk,
D => prmry_pulse_ack,
R => prmry_reset2
);
MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
begin
scndry_out_int <= s_level_out_d2;
--prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out_int <= s_level_out_d3;
--prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out_int <= s_level_out_d4;
--prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out_int <= s_level_out_d5;
--prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out_int <= s_level_out_d6;
--prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6;
end generate MTBF_L6;
scndry_out <= scndry_out_int;
end generate GENERATE_LEVEL_ACK_P_S_CDC;
end implementation;
| lgpl-3.0 | 1856f8ec5fb02b959fae185a69143376 | 0.384111 | 4.257423 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/user.org/axi_to_audio_v1_0/6d2e43c7/hdl/AXI_to_audio_v1_0.vhd | 2 | 4,309 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AXI_to_audio_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
-- Users to add ports here
audio_out_l : out std_logic_vector(23 downto 0);
audio_out_r : out std_logic_vector(23 downto 0);
audio_out_valid : out std_logic;
audio_in_valid_irq : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end AXI_to_audio_v1_0;
architecture arch_imp of AXI_to_audio_v1_0 is
-- component declaration
component AXI_to_audio_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
audio_out_l : out std_logic_vector(23 downto 0);
audio_out_r : out std_logic_vector(23 downto 0);
audio_out_valid : out std_logic;
audio_in_valid_irq : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component AXI_to_audio_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
AXI_to_audio_v1_0_S00_AXI_inst : AXI_to_audio_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
audio_in_valid_irq => audio_in_valid_irq,
audio_out_valid => audio_out_valid,
audio_out_l => audio_out_l,
audio_out_r => audio_out_r,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
| lgpl-3.0 | dfce6bae85a9236bf1d091158b0f3a4f | 0.659782 | 2.428974 | false | false | false | false |
peladex/RHD2132_FPGA | src/spi_master_slave/spi_loopback.vhd | 2 | 6,078 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:44:37 05/17/2011
-- Design Name:
-- Module Name: spi_loopback - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is a simple wrapper for the 'spi_master' and 'spi_slave' cores, to synthesize the 2 cores and
-- test them in the simulator.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.all;
entity spi_loopback is
Generic (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2; -- prefetch lookahead cycles
SPI_2X_CLK_DIV : positive := 5 -- for a 100MHz sclk_i, yields a 10MHz SCK
);
Port(
----------------MASTER-----------------------
m_clk_i : IN std_logic;
m_rst_i : IN std_logic;
m_spi_ssel_o : OUT std_logic;
m_spi_sck_o : OUT std_logic;
m_spi_mosi_o : OUT std_logic;
m_spi_miso_i : IN std_logic;
m_di_req_o : OUT std_logic;
m_di_i : IN std_logic_vector(N-1 downto 0);
m_wren_i : IN std_logic;
m_do_valid_o : OUT std_logic;
m_do_o : OUT std_logic_vector(N-1 downto 0);
----- debug -----
m_do_transfer_o : OUT std_logic;
m_wren_o : OUT std_logic;
m_wren_ack_o : OUT std_logic;
m_rx_bit_reg_o : OUT std_logic;
m_state_dbg_o : OUT std_logic_vector(5 downto 0);
m_core_clk_o : OUT std_logic;
m_core_n_clk_o : OUT std_logic;
m_sh_reg_dbg_o : OUT std_logic_vector(N-1 downto 0);
----------------SLAVE-----------------------
s_clk_i : IN std_logic;
s_spi_ssel_i : IN std_logic;
s_spi_sck_i : IN std_logic;
s_spi_mosi_i : IN std_logic;
s_spi_miso_o : OUT std_logic;
s_di_req_o : OUT std_logic; -- preload lookahead data request line
s_di_i : IN std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i)
s_wren_i : IN std_logic := 'X'; -- user data write enable
s_do_valid_o : OUT std_logic; -- do_o data valid strobe, valid during one clk_i rising edge.
s_do_o : OUT std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i)
----- debug -----
s_do_transfer_o : OUT std_logic; -- debug: internal transfer driver
s_wren_o : OUT std_logic;
s_wren_ack_o : OUT std_logic;
s_rx_bit_reg_o : OUT std_logic;
s_state_dbg_o : OUT std_logic_vector (5 downto 0) -- debug: internal state register
-- s_sh_reg_dbg_o : OUT std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end spi_loopback;
architecture Structural of spi_loopback is
begin
--=============================================================================================
-- Component instantiation for the SPI master port
--=============================================================================================
Inst_spi_master: entity work.spi_master(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
port map(
sclk_i => m_clk_i, -- system clock is used for serial and parallel ports
pclk_i => m_clk_i,
rst_i => m_rst_i,
spi_ssel_o => m_spi_ssel_o,
spi_sck_o => m_spi_sck_o,
spi_mosi_o => m_spi_mosi_o,
spi_miso_i => m_spi_miso_i,
di_req_o => m_di_req_o,
di_i => m_di_i,
wren_i => m_wren_i,
do_valid_o => m_do_valid_o,
do_o => m_do_o,
----- debug -----
do_transfer_o => m_do_transfer_o,
wren_o => m_wren_o,
wren_ack_o => m_wren_ack_o,
rx_bit_reg_o => m_rx_bit_reg_o,
state_dbg_o => m_state_dbg_o,
core_clk_o => m_core_clk_o,
core_n_clk_o => m_core_n_clk_o,
sh_reg_dbg_o => m_sh_reg_dbg_o
);
--=============================================================================================
-- Component instantiation for the SPI slave port
--=============================================================================================
Inst_spi_slave: entity work.spi_slave(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH)
port map(
clk_i => s_clk_i,
spi_ssel_i => s_spi_ssel_i,
spi_sck_i => s_spi_sck_i,
spi_mosi_i => s_spi_mosi_i,
spi_miso_o => s_spi_miso_o,
di_req_o => s_di_req_o,
di_i => s_di_i,
wren_i => s_wren_i,
do_valid_o => s_do_valid_o,
do_o => s_do_o,
----- debug -----
do_transfer_o => s_do_transfer_o,
wren_o => s_wren_o,
wren_ack_o => s_wren_ack_o,
rx_bit_reg_o => s_rx_bit_reg_o,
state_dbg_o => s_state_dbg_o
-- sh_reg_dbg_o => s_sh_reg_dbg_o
);
end Structural;
| gpl-3.0 | d4b28c826bb784891c5fe1de21b52168 | 0.422178 | 3.731123 | false | false | false | false |
boztalay/OldProjects | FPGA/LCD_Control/TestCPU1_dRAM_TB.vhd | 1 | 3,002 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:14:07 10/04/2009
-- Design Name:
-- Module Name: C:/Users/Ben/Desktop/Folders/FPGA/Projects/Current Projects/Systems/TestCPU1/TestCPU1_dRAM_TB.vhd
-- Project Name: TestCPU1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: TestCPU1_dRAM
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY TestCPU1_dRAM_TB IS
END TestCPU1_dRAM_TB;
ARCHITECTURE behavior OF TestCPU1_dRAM_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TestCPU1_dRAM
PORT(
clock : IN std_logic;
reset : IN std_logic;
write_e : IN std_logic;
read_e : IN std_logic;
addr : IN std_logic_vector(7 downto 0);
data : IN std_logic_vector(15 downto 0);
to_reg_file : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal write_e : std_logic := '0';
signal read_e : std_logic := '0';
signal addr : std_logic_vector(7 downto 0) := (others => '0');
signal data : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal to_reg_file : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TestCPU1_dRAM PORT MAP (
clock => clock,
reset => reset,
write_e => write_e,
read_e => read_e,
addr => addr,
data => data,
to_reg_file => to_reg_file
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 20 ns;
write_e <= '1';
addr <= x"01";
data <= x"0001";
wait for 10 ns;
addr <= x"02";
data <= x"0002";
wait for 10 ns;
write_e <= '0';
read_e <= '1';
wait for 10 ns;
addr <= x"01";
wait for 10 ns;
reset <= '1';
wait for 10 ns;
reset <= '0';
read_e <= '0';
wait;
end process;
END;
| mit | 026733ae1fc230d87f6262f88908453c | 0.549967 | 3.556872 | false | true | false | false |
boztalay/OldProjects | FPGA/testytest/top_level_TB.vhd | 1 | 4,141 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:42:21 08/16/2010
-- Design Name:
-- Module Name: C:/Users/georgecuris/Desktop/Folders/FPGA/Projects/Current Projects/Systems/testytest/top_level_TB.vhd
-- Project Name: testytest
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: top_level
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY top_level_TB IS
END top_level_TB;
ARCHITECTURE behavior OF top_level_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top_level
PORT(
mclk : IN std_logic;
rst : IN std_logic;
CQ_write_en : IN std_logic;
VQ_read_en : IN std_logic;
memory_address_bus : INOUT std_logic_vector(22 downto 0);
memory_data_bus : INOUT std_logic_vector(15 downto 0);
anodes : OUT std_logic_vector(3 downto 0);
decoder_out : OUT std_logic_vector(6 downto 0);
RAM_oe : OUT std_logic;
RAM_we : OUT std_logic;
RAM_adv : OUT std_logic;
RAM_clk : OUT std_logic;
RAM_ub : OUT std_logic;
RAM_lb : OUT std_logic;
RAM_ce : OUT std_logic;
RAM_cre : OUT std_logic;
RAM_wait : IN std_logic;
LEDs : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal mclk : std_logic := '0';
signal rst : std_logic := '0';
signal CQ_write_en : std_logic := '0';
signal VQ_read_en : std_logic := '0';
signal RAM_wait : std_logic := '0';
--BiDirs
signal memory_address_bus : std_logic_vector(22 downto 0);
signal memory_data_bus : std_logic_vector(15 downto 0);
--Outputs
signal anodes : std_logic_vector(3 downto 0);
signal decoder_out : std_logic_vector(6 downto 0);
signal RAM_oe : std_logic;
signal RAM_we : std_logic;
signal RAM_adv : std_logic;
signal RAM_clk : std_logic;
signal RAM_ub : std_logic;
signal RAM_lb : std_logic;
signal RAM_ce : std_logic;
signal RAM_cre : std_logic;
signal LEDs : std_logic_vector(7 downto 0);
-- Clock period definitions
constant mclk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top_level PORT MAP (
mclk => mclk,
rst => rst,
CQ_write_en => CQ_write_en,
VQ_read_en => VQ_read_en,
memory_address_bus => memory_address_bus,
memory_data_bus => memory_data_bus,
anodes => anodes,
decoder_out => decoder_out,
RAM_oe => RAM_oe,
RAM_we => RAM_we,
RAM_adv => RAM_adv,
RAM_clk => RAM_clk,
RAM_ub => RAM_ub,
RAM_lb => RAM_lb,
RAM_ce => RAM_ce,
RAM_cre => RAM_cre,
RAM_wait => RAM_wait,
LEDs => LEDs
);
-- Clock process definitions
mclk_process :process
begin
mclk <= '1';
wait for mclk_period/2;
mclk <= '0';
wait for mclk_period/2;
end process;
RAM_wait_proc :process
begin
RAM_wait <= '0';
wait for 980 ns;
RAM_wait <= '0';
wait for 35 ns;
RAM_wait <= '1';
wait for 40 ns;
RAM_wait <= '0';
wait;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 300 ns;
rst <= '0';
wait;
end process;
END;
| mit | 72ed589332f49a10c19a4d941b243c2d | 0.549626 | 3.518267 | false | true | false | false |
freecores/line_codes | bench/vhdl/smlt_ami_dec.vhd | 1 | 957 | -- smlttion for AMI decoder.
entity smlt_ami_dec is
end smlt_ami_dec;
architecture behaviour of smlt_ami_dec is
--data type:
component ami_dec
port (
clr_bar,
e0, e1: in bit;
s : out bit);
end component;
--binding:
for a: ami_dec use entity work.ami_dec;
--declaring the signals present in this architecture:
signal CLK, S, E0, E1, clrb: bit;
signal input0, input1: bit_vector(0 to 26);
begin --architecture.
a: ami_dec port map
( clr_bar => clrb, e0 => E0, e1 => E1, s => S );
input0 <= "000100010000100100001000010";
input1 <= "000001001000001000100000101";
process begin
clrb <= '1';
for i in 0 to 26 loop
E0 <= input0(i);
E1 <= input1(i);
CLK <= '0';
wait for 9 ns;
CLK <= '1';
wait for 1 ns;
end loop;
wait;
end process;
end behaviour;
| gpl-2.0 | 5061fc071d739d59c02f4d3704a7aa57 | 0.53187 | 3.277397 | false | false | false | false |
freecores/usb_fpga_2_16 | examples/usb-fpga-2.16/2.16b/lightshow/fpga/lightshow.vhd | 17 | 3,116 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lightshow is
port(
led1 : out std_logic_vector(9 downto 0); -- LED1 on debug board
led2 : out std_logic_vector(19 downto 0); -- LED2 + LED3 on debug board
sw : in std_logic_vector(3 downto 0);
fxclk : in std_logic
);
end lightshow;
--signal declaration
architecture RTL of lightshow is
type tPattern1 is array(9 downto 0) of integer range 0 to 255;
type tPattern2 is array(19 downto 0) of integer range 0 to 255;
signal pattern1 : tPattern1 := (0, 10, 41, 92, 163, 255, 163, 92, 41, 10); -- pattern for LED1
signal pattern20 : tPattern2 := (0, 1, 2, 9, 16, 25, 36, 49, 64, 81, 64, 49, 36, 25, 16, 9, 2, 1, 0, 0); -- 1st pattern for LED2
signal pattern21 : tPattern2 := (0, 19, 77, 174, 77, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); -- 2nd pattern for LED2
signal pattern2 : tPattern2; -- pattern20 + pattern21
signal cnt1,cnt20, cnt21 : std_logic_vector(22 downto 0);
signal pwm_cnt : std_logic_vector(19 downto 0);
signal pwm_cnt8 : std_logic_vector(7 downto 0);
begin
pwm_cnt8 <= pwm_cnt(19 downto 12);
dp_fxclk: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
-- pattern for led 1
if ( cnt1 >= conv_std_logic_vector(7200000,23) ) -- 1/1.5 Hz
then
if ( sw(0) = '1' )
then
pattern1(8 downto 0) <= pattern1(9 downto 1);
pattern1(9) <= pattern1(0);
else
pattern1(9 downto 1) <= pattern1(8 downto 0);
pattern1(0) <= pattern1(9);
end if;
cnt1 <= (others => '0');
else
cnt1 <= cnt1 + 1;
end if;
-- pattern for led 2
if ( ( cnt20 >= conv_std_logic_vector(4800000,23) ) or ( (sw(2)= '1') and (cnt20 >= conv_std_logic_vector(1600000,23)) ) ) -- SW1 off: 1/3Hz, SW1 on: 1Hz
then
pattern20(18 downto 0) <= pattern20(19 downto 1);
pattern20(19) <= pattern20(0);
cnt20 <= (others => '0');
else
cnt20 <= cnt20 + 1;
end if;
if ( ( cnt21 >= conv_std_logic_vector(2000000,23) ) or ( (sw(3)= '1') and (cnt21 >= conv_std_logic_vector(500000,23)) ) )
then
if ( sw(1) = '1' )
then
pattern21(18 downto 0) <= pattern21(19 downto 1);
pattern21(19) <= pattern21(0);
else
pattern21(19 downto 1) <= pattern21(18 downto 0);
pattern21(0) <= pattern21(19);
end if;
cnt21 <= (others => '0');
else
cnt21 <= cnt21 + 1;
end if;
for i in 0 to 19 loop
pattern2(i) <= pattern20(i) + pattern21(i);
end loop;
-- pwm
if ( pwm_cnt8 = conv_std_logic_vector(255,8) )
then
pwm_cnt <= ( others => '0' );
else
pwm_cnt <= pwm_cnt + 1;
end if;
-- led1
for i in 0 to 9 loop
if ( pwm_cnt8 < pattern1(i) )
then
led1(i) <= '1';
else
led1(i) <= '0';
end if;
end loop;
for i in 0 to 19 loop
if (pwm_cnt8 < pattern2(i) )
then
led2(i) <= '1';
else
led2(i) <= '0';
end if;
end loop;
end if;
end process dp_fxclk;
end RTL;
| gpl-3.0 | 4da7275055ba75782cf1c47b88355891 | 0.562901 | 2.80468 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia/tickswitch.vhd | 1 | 2,482 | -------------------------------------------------------------------------------
-- Ce module prends un fil en entrée, 1 si c'est un tick, 0 sinon
-- Sa sortie change entre '0' et '1' à chaque tick
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY tickswitch IS
PORT(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
T : in STD_LOGIC;
S : out STD_LOGIC
);
END tickswitch;
ARCHITECTURE montage OF tickswitch IS
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
TYPE T_CMD IS (INIT, SWITCH, NOOP);
-- la commande courante
signal CMD : T_CMD;
-- registre de sortie
signal R : STD_LOGIC ;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
type STATE_TYPE is (
ST_INIT, ST_SWITCH, ST_WAIT
);
signal state : STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
process (reset, clk)
begin
IF reset = '1' THEN
R <= '1';
ELSIF clk'event and clk = '1' then
IF CMD = INIT THEN
R <= '0';
ELSIF CMD = SWITCH THEN
R <= not(R);
END IF;
end if;
end process;
-- la sortie == le registre de stockage
S <= R ;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: T
-- Outputs: S, CMD
-------------------------------------------------------------------------------
-- fonction de transitition
process (reset, clk)
begin
if reset = '1' then
state <= ST_INIT;
elsif clk'event and clk = '1' then
case state is
when ST_INIT =>
state <= ST_WAIT ;
when ST_WAIT =>
IF T = '1' THEN
state <= ST_SWITCH ;
END IF ;
when ST_SWITCH =>
state <= ST_WAIT;
end case;
end if;
end process;
-- fonction de sortie
with state select CMD <=
INIT when ST_INIT,
SWITCH when ST_SWITCH,
NOOP when ST_WAIT
;
end montage;
| gpl-3.0 | 2e9e5c34dd092c411a7eff9b03a54dc7 | 0.368336 | 4.610801 | false | false | false | false |
DaveyPocket/btrace448 | btrace/spheregen_TB.vhd | 1 | 1,098 | -- Btrace 448
-- Sphere Generator - Test Bench
--
-- Bradley Boccuzzi
-- 2016
library ieee;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.btrace_pack.all;
entity spheregen_TB is
end spheregen_TB;
architecture arch of spheregen_TB is
constant clkPd: time := 20 ns;
signal clk, rst: std_logic;
signal d_vect: vector := (x"00000000", x"00000000", x"03E80000");
signal origin_point: point := (x"00000000", x"00000000", x"00000000");
-- should be positioned at z = 16, x = 0, y = 0
-- size 2
signal myObject: object := ((x"00000000", x"00000000", x"01900000"), x"00500000", x"F00");
signal obj_hit: std_logic;
signal result: std_logic_vector(31 downto 0);
begin
uut: entity work.sphere_gen port map(clk, d_vect, origin_point, myObject, result, obj_hit);
clkProc: process
begin
clk <= '1';
wait for clkPd/2;
clk <= '0';
wait for clkPd/2;
end process clkProc;
mainProc: process
begin
rst <= '1';
wait for clkPd/3;
wait for clkPd;
rst <= '0';
wait;
end process mainProc;
end arch;
| gpl-3.0 | c942882fb05434c981c8c69081f96faa | 0.679417 | 2.808184 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia/sept.vhd | 1 | 1,043 | -- includes
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
-- prototypage
ENTITY sept IS
PORT (
e : IN STD_LOGIC_VECTOR (3 downto 0) ; -- 2^4 = 16, codes les entiers de 0 à 9
S : OUT STD_LOGIC_VECTOR(6 downto 0);
err : OUT STD_LOGIC
);
END sept;
-- architecture
ARCHITECTURE arch OF sept IS
signal r : STD_LOGIC_VECTOR (6 downto 0);
BEGIN
WITH e SELECT s <=
"0000001" WHEN "0000", -- 0 => abcdef-
"1001111" WHEN "0001", -- 1 => -bc----
"0010010" WHEN "0010",
"0000110" WHEN "0011",
"1001100" WHEN "0100",
"0100100" WHEN "0101",
"0100000" WHEN "0110",
"0001101" WHEN "0111",
"0000000" WHEN "1000",
"0000100" WHEN "1001",
"0110000" WHEN OTHERS -- >= 10 => affiches 'E'
;
WITH e SELECT err <=
'0' WHEN "0000", -- diode eteinte
'0' WHEN "0001", -- diode eteinte
'0' WHEN "0010",
'0' WHEN "0011",
'0' WHEN "0100",
'0' WHEN "0101",
'0' WHEN "0110",
'0' WHEN "0111",
'0' WHEN "1000",
'0' WHEN "1001",
'1' WHEN OTHERS -- diode allumée (>= 10)
;
END arch ;
| gpl-3.0 | 58392b4dc460bca3277437e2c0c49840 | 0.589817 | 2.642132 | false | false | false | false |
DaveyPocket/btrace448 | btrace/point_reg.vhd | 1 | 546 | -- Btrace 448
-- Point Register
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
use work.btrace_pack.all;
entity point_reg is
port(clk, rst, en: in std_logic;
Din: in point;
Dout: out point);
end point_reg;
architecture arch of point_reg is
constant zero_point: point := ((others => '0'), (others => '0'), (others => '0'));
begin
process(clk, rst)
begin
if rst = '1' then
Dout <= zero_point;
elsif rising_edge(clk) then
if en = '1' then
Dout <= Din;
end if;
end if;
end process;
end arch;
| gpl-3.0 | 99e97fc07c23a318150c5ef0fa594f3d | 0.635531 | 2.785714 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/bd/week1/ip/week1_rst_processing_system7_0_100M_0/synth/week1_rst_processing_system7_0_100M_0.vhd | 1 | 6,795 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY week1_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END week1_rst_processing_system7_0_100M_0;
ARCHITECTURE week1_rst_processing_system7_0_100M_0_arch OF week1_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF week1_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF week1_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF week1_rst_processing_system7_0_100M_0_arch : ARCHITECTURE IS "week1_rst_processing_system7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF week1_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "week1_rst_processing_system7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END week1_rst_processing_system7_0_100M_0_arch;
| lgpl-3.0 | f7ee52415e9d30ef1dd0a6ac390a0686 | 0.717586 | 3.438765 | false | false | false | false |
boztalay/OldProjects | FPGA/LCD_Control/TestCPU1_ALU_TB.vhd | 1 | 2,522 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:13:11 10/03/2009
-- Design Name:
-- Module Name: C:/Users/Ben/Desktop/Folders/FPGA/Projects/Current Projects/Systems/TestCPU1/TestCPU1_ALU_TB.vhd
-- Project Name: TestCPU1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: TestCPU1_ALU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY TestCPU1_ALU_TB IS
END TestCPU1_ALU_TB;
ARCHITECTURE behavior OF TestCPU1_ALU_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TestCPU1_ALU
PORT(
operation : IN std_logic;
to_bus_e : IN std_logic;
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
result : OUT std_logic_vector(15 downto 0);
z_flag : OUT std_logic
);
END COMPONENT;
--Inputs
signal operation : std_logic := '0';
signal to_bus_e : std_logic := '0';
signal A : std_logic_vector(15 downto 0) := (others => '0');
signal B : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal result : std_logic_vector(15 downto 0);
signal z_flag : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TestCPU1_ALU PORT MAP (
operation => operation,
to_bus_e => to_bus_e,
A => A,
B => B,
result => result,
z_flag => z_flag
);
-- Stimulus process
stim_proc: process
begin
wait for 20 ns;
A <= x"0003";
B <= x"0001";
operation <= '1';
to_bus_e <= '1';
wait for 10 ns;
operation <= '0';
wait for 10 ns;
B <= x"0003";
operation <= '1';
wait for 10 ns;
to_bus_e <= '0';
wait;
end process;
END;
| mit | a15c8a6f84f17ac2a5d4d551cfcd35af | 0.550357 | 3.587482 | false | true | false | false |
boztalay/OldProjects | FPGA/testytest/DCMi_80.vhd | 1 | 2,738 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 10.1
-- \ \ Application : xaw2vhdl
-- / / Filename : DCMi_80.vhd
-- /___/ /\ Timestamp : 07/08/2010 14:30:24
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdlDCMi_80.xaw DCMi_80.vhd
--Design Name: DCMi_80
--Device: xc3s500e-fg320-4
--
-- Module DCMi_80
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.08 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.95 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity DCMi_80 is
port ( CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLK0_OUT : out std_logic);
end DCMi_80;
architecture BEHAVIORAL of DCMi_80 is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 8,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 40.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IN,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>open,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| mit | 53c5604f9052b91168e34f06a45d3f94 | 0.451424 | 3.715061 | false | false | false | false |
boztalay/OldProjects | FPGA/Test_Project/Test_Project.vhd | 1 | 3,271 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:46:30 06/12/2010
-- Design Name:
-- Module Name: Test_Project - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity Test_Project is
Port ( clock : in STD_LOGIC;
-- switches : in STD_LOGIC_VECTOR(7 downto 0);
output : out STD_LOGIC);
end Test_Project;
architecture Behavioral of Test_Project is
signal clock_buf : STD_LOGIC;
signal new_clock : STD_LOGIC;
signal new_clock_buf : STD_LOGIC;
signal DCM1_feedback_in : STD_LOGIC;
begin
--This BUFG buffers the board clock
board_clk: BUFG
port map (O => clock_buf,
I => clock);
DCM_1 : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 2, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 40.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLKIN => clock_buf,
CLKFB => DCM1_feedback_in,
CLK0 => new_clock
);
--This BUFG buffers DCM1's feedback
DCM1_feedback: BUF
port map (O => DCM1_feedback_in,
I => new_clock);
buf_new_clk: BUFG
port map (O => new_clock_buf,
I => new_clock);
main: process (new_clock_buf) is
-- variable count : STD_LOGIC_VECTOR(7 downto 0);
begin
-- if rising_edge(clock_buf) then
-- count := count + 1;
-- if count > switches then
-- count := (others => '0');
-- new_clock <= '0';
-- end if;
-- if count = ('0' & switches(7 downto 1)) then
-- new_clock <= '1';
-- end if;
-- end if;
output <= new_clock_buf;
end process;
end Behavioral;
| mit | fd18c442358300e6d8fc16779861839c | 0.560073 | 3.327569 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/bd/week1/ip/week1_Volume_Pregain_0_0/synth/week1_Volume_Pregain_0_0.vhd | 1 | 9,117 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: tsotnep:userLibrary:Volume_Pregain:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY week1_Volume_Pregain_0_0 IS
PORT (
OUT_VOLCTRL_L : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
OUT_VOLCTRL_R : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
OUT_RDY : OUT STD_LOGIC;
IN_SIG_L : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
IN_SIG_R : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END week1_Volume_Pregain_0_0;
ARCHITECTURE week1_Volume_Pregain_0_0_arch OF week1_Volume_Pregain_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF week1_Volume_Pregain_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Volume_Pregain_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
INTBIT_WIDTH : INTEGER
);
PORT (
OUT_VOLCTRL_L : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
OUT_VOLCTRL_R : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
OUT_RDY : OUT STD_LOGIC;
IN_SIG_L : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
IN_SIG_R : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT Volume_Pregain_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF week1_Volume_Pregain_0_0_arch: ARCHITECTURE IS "Volume_Pregain_v1_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF week1_Volume_Pregain_0_0_arch : ARCHITECTURE IS "week1_Volume_Pregain_0_0,Volume_Pregain_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
BEGIN
U0 : Volume_Pregain_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
INTBIT_WIDTH => 24
)
PORT MAP (
OUT_VOLCTRL_L => OUT_VOLCTRL_L,
OUT_VOLCTRL_R => OUT_VOLCTRL_R,
OUT_RDY => OUT_RDY,
IN_SIG_L => IN_SIG_L,
IN_SIG_R => IN_SIG_R,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END week1_Volume_Pregain_0_0_arch;
| lgpl-3.0 | 5d8d511e1e74b08777e4eff4f079a818 | 0.701876 | 3.21928 | false | false | false | false |
boztalay/OldProjects | FPGA/Systems/Sys_LCDTest/Sys_LCDTest.vhd | 1 | 8,262 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 23:02:09 04/12/2009
-- Design Name:
-- Module Name: Sys_LCDTest - Behavioral
-- Project Name: LCD Test
-- Target Devices:
-- Tool versions:
-- Description: An LCD test system
--
-- Dependencies: Subsys_LCDDrive.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- 0.10 - Successfully Displayed "BEN" on LCD
-- 0.11 - Successfully Displayed "Cat rocks my socks!" on LCD
-- Additional Comments:
--
----------------------------------------------------------------------------------
---------Begin-----------
--Frequency Divder Code--
---------Begin-----------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FrequencyDivider is
Port ( MainCLK : in STD_LOGIC;
CLK1MHz : out STD_LOGIC);
end FrequencyDivider;
architecture Behavioral of FrequencyDivider is
begin
main : process(MainCLK)
variable cnt, cnt2 : integer := 0;
begin
if (MainCLK'event and MainCLK = '1') then
cnt := cnt + 1;
--Division for CLK1MHz
if (cnt = 25) then
CLK1MHz <= '1';
end if;
if (cnt = 50) then
CLK1MHz <= '0';
cnt := 0;
end if;
end if;
end process;
end architecture Behavioral;
----------End------------
--Frequency Divder Code--
----------End------------
------Begin--------
--LCD Driver Code--
------Begin--------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity Sys_LCDTest is
Port ( SysCLK : in STD_LOGIC;
RS : out STD_LOGIC := '0';
RW : out STD_LOGIC;
databus : out STD_LOGIC_VECTOR (7 downto 0);
E : out STD_LOGIC := '0');
end Sys_LCDTest;
--Architecture Begin--
architecture Behavioral of Sys_LCDTest is
--\Signals/--
signal Buf_SysCLK : STD_LOGIC;
signal Buf_CLK1MHz : STD_LOGIC;
signal Unbuf_CLK1MHz : STD_LOGIC;
--/Signals\--
--\Components/--
component FrequencyDivider is
Port ( MainCLK : in STD_LOGIC;
CLK1MHz : out STD_LOGIC);
end component;
--/Components\--
--\Functions/--
function char2slv (char : in character) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (7 downto 0);
begin
case (char) is
when ' ' =>
result := "00100000";
when '!' =>
result := "00100001";
when '#' =>
result := "00100011";
when '$' =>
result := "00100100";
when '%' =>
result := "00100101";
when '&' =>
result := "00100110";
when ''' =>
result := "00100111";
when '(' =>
result := "00101000";
when ')' =>
result := "00101001";
when '*' =>
result := "00101010";
when '+' =>
result := "00101011";
when ',' =>
result := "00101100";
when '-' =>
result := "00101101";
when '.' =>
result := "00101110";
when '/' =>
result := "00101111";
when '0' =>
result := "00110000";
when '1' =>
result := "00110001";
when '2' =>
result := "00110010";
when '3' =>
result := "00110011";
when '4' =>
result := "00110100";
when '5' =>
result := "00110101";
when '6' =>
result := "00110110";
when '7' =>
result := "00110111";
when '8' =>
result := "00111000";
when '9' =>
result := "00111001";
when ':' =>
result := "00111010";
when ';' =>
result := "00111011";
when '<' =>
result := "00111100";
when '=' =>
result := "00111101";
when '>' =>
result := "00111110";
when '?' =>
result := "00111111";
when '@' =>
result := "01000000";
when 'A' =>
result := "01000001";
when 'B' =>
result := "01000010";
when 'C' =>
result := "01000011";
when 'D' =>
result := "01000100";
when 'E' =>
result := "01000101";
when 'F' =>
result := "01000110";
when 'G' =>
result := "01000111";
when 'H' =>
result := "01001000";
when 'I' =>
result := "01001001";
when 'J' =>
result := "01001010";
when 'K' =>
result := "01001011";
when 'L' =>
result := "01001100";
when 'M' =>
result := "01001101";
when 'N' =>
result := "01001110";
when 'O' =>
result := "01001111";
when 'P' =>
result := "01010000";
when 'Q' =>
result := "01010001";
when 'R' =>
result := "01010010";
when 'S' =>
result := "01010011";
when 'T' =>
result := "01010100";
when 'U' =>
result := "01010101";
when 'V' =>
result := "01010110";
when 'W' =>
result := "01010111";
when 'X' =>
result := "01011000";
when 'Y' =>
result := "01011001";
when 'Z' =>
result := "01011010";
when '[' =>
result := "01011011";
when ']' =>
result := "01011101";
when '^' =>
result := "01011110";
when '_' =>
result := "01011111";
when '`' =>
result := "01100000";
when 'a' =>
result := "01100001";
when 'b' =>
result := "01100010";
when 'c' =>
result := "01100011";
when 'd' =>
result := "01100100";
when 'e' =>
result := "01100101";
when 'f' =>
result := "01100110";
when 'g' =>
result := "01100111";
when 'h' =>
result := "01101000";
when 'i' =>
result := "01101001";
when 'j' =>
result := "01101010";
when 'k' =>
result := "01101011";
when 'l' =>
result := "01101100";
when 'm' =>
result := "01101101";
when 'n' =>
result := "01101110";
when 'o' =>
result := "01101111";
when 'p' =>
result := "01110000";
when 'q' =>
result := "01110001";
when 'r' =>
result := "01110010";
when 's' =>
result := "01110011";
when 't' =>
result := "01110100";
when 'u' =>
result := "01110101";
when 'v' =>
result := "01110110";
when 'w' =>
result := "01110111";
when 'x' =>
result := "01111000";
when 'y' =>
result := "01111001";
when 'z' =>
result := "01111010";
when '{' =>
result := "01111011";
when '|' =>
result := "01111100";
when '}' =>
result := "01111101";
when others =>
result := "11110011";
end case;
return result;
end function char2slv;
--/Functions\--
begin
--\BUFG Instantiations/--
BUFG_BufSysCLK : BUFG
port map (
O => Buf_SysCLK,
I => SysCLK
);
BUFG_BufCLK1MHz : BUFG
port map (
O => Buf_CLK1MHz,
I => Unbuf_CLK1MHz
);
--/BUFG Instantiations\--
G1: FrequencyDivider port map (Buf_SysCLK, Unbuf_CLK1MHz);
main : process(Buf_CLK1MHz)
subtype LCDstring is string(1 to 12);
subtype short is integer range 0 to 13;
variable count_us : integer := 0;
variable index : short := 1;
variable message : LCDstring := "Hzllo World!";
variable wait_time : integer := 0;
variable write_msg : boolean := false;
constant begin_write_time : integer := 22000;
begin
if(Buf_CLK1MHz'event and Buf_CLK1MHz = '1') then
count_us := count_us + 1;
end if;
--First part of startup sequence
if (count_us >= 20000) then
RS <= '0';
RW <= '0';
E <= '1';
databus <= "00111000";
if (count_us = 20050) then
E <= '0';
end if;
end if;
--Second part of startup sequence
if (count_us >= 20100) then
RS <= '0';
RW <= '0';
E <= '1';
databus <= "00001111";
if (count_us = 20150) then
E <= '0';
end if;
end if;
--Third part of startup sequence
if (count_us >= 20200) then
RS <= '0';
RW <= '0';
E <= '1';
databus <= "00000001";
if (count_us = 20250) then
E <= '0';
end if;
end if;
--Write message
if (count_us >= begin_write_time) then
RS <= '1';
RW <= '0';
E <= '1';
databus <= char2slv(message(1));
if((count_us = (begin_write_time + 50))) then
E <= '0';
wait_time := wait_time + 50;
--index := index + 1;
end if;
end if;
if (count_us >= begin_write_time + 100) then
RS <= '1';
RW <= '0';
E <= '1';
databus <= char2slv(message(2));
if((count_us = (begin_write_time + 150))) then
E <= '0';
wait_time := wait_time + 50;
--index := index + 1;
end if;
end if;
end process;
end Behavioral;
-------End---------
--LCD Driver Code--
-------End---------
| mit | a83d6786714a8f223e9049a9a4c8f5b9 | 0.515372 | 3.088598 | false | false | false | false |
fkolacek/FIT-VUT | INP2/fpga/cpu.vhd | 1 | 10,694 | -- cpu.vhd: Simple 8-bit CPU (BrainFuck interpreter)
-- Copyright (C) 2011 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): Zdenek Vasicek <vasicek AT fit.vutbr.cz>
-- Frantisek Kolacek <xkolac12 AT stud.fit.vutbr.cz>
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- ----------------------------------------------------------------------------
-- Entity S_DEClaration
-- ----------------------------------------------------------------------------
entity cpu is
port (
CLK : in std_logic; -- hodinovy signal
RESET : in std_logic; -- asynchronni reset procesoru
EN : in std_logic; -- povoleni cinnosti procesoru
-- synchronni pamet ROM
CODE_ADDR : out std_logic_vector(11 downto 0); -- adresa do pameti
CODE_DATA : in std_logic_vector(7 downto 0); -- CODE_DATA <- rom[CODE_ADDR] pokud CODE_EN='1'
CODE_EN : out std_logic; -- povoleni cinnosti
-- synchronni pamet RAM
DATA_ADDR : out std_logic_vector(9 downto 0); -- adresa do pameti
DATA_WDATA : out std_logic_vector(7 downto 0); -- mem[DATA_ADDR] <- DATA_WDATA pokud DATA_EN='1'
DATA_RDATA : in std_logic_vector(7 downto 0); -- DATA_RDATA <- ram[DATA_ADDR] pokud DATA_EN='1'
DATA_RDWR : out std_logic; -- cteni (0) / zapis (1)
DATA_EN : out std_logic; -- povoleni cinnosti
-- vstupni port
IN_DATA : in std_logic_vector(7 downto 0); -- IN_DATA <- stav klavesnice pokud IN_VLD='1' a IN_REQ='1'
IN_VLD : in std_logic; -- data platna
IN_REQ : out std_logic; -- pozadavek na vstup data
-- vystupni port
OUT_DATA : out std_logic_vector(7 downto 0); -- zapisovana data
OUT_BUSY : in std_logic; -- LCD je zaneprazdnen (1), nelze zapisovat
OUT_WE : out std_logic -- LCD <- OUT_DATA pokud OUT_WE='1' a OUT_BUSY='0'
);
end cpu;
-- ----------------------------------------------------------------------------
-- Architecture S_DEClaration
-- ----------------------------------------------------------------------------
architecture behavioral of cpu is
--
-- Signaly pro praci s pocitadlem
signal counterRegister : std_logic_vector (7 downto 0);
signal counterSet : std_logic;
signal counterInc : std_logic;
signal counterDec : std_logic;
-- Signaly pro praci s ukazatelem
signal pointerRegister : std_logic_vector (9 downto 0);
signal pointerSet : std_logic;
signal pointerInc : std_logic;
signal pointerDec : std_logic;
-- Signaly pro praci s pcRegister
signal pcRegister : std_logic_vector (11 downto 0);
signal pcSet : std_logic;
signal pcInc : std_logic;
signal pcDec : std_logic;
-- Instrukce v jazyce brainfuck
type instructions is (I_IDLE, I_INC, I_DEC, I_MOVE_LEFT, I_MOVE_RIGHT, I_OUTPUT, I_INPUT, I_LOOP_START, I_LOOP_END, I_NOOP);
signal instructionsPointer : instructions;
-- Stavy procesoru
type cpuStates is (S_IDLE, S_LOAD, S_STOP, S_INC, S_DEC, S_IN, S_OUT, S_LOOP_START, S_LOOP_END, S_LOOP_CONT, S_LOOP_CONT_END, S_LOOP_REV, S_LOOP_REV_END);
signal cpuPresentState : cpuStates;
signal cpuNextState : cpuStates;
--
begin
CODE_ADDR <= pcRegister;
DATA_ADDR <= pointerRegister;
-- Proces pro nacteni a dekodovani instrukce
cpuLoadInstruction: process (CODE_DATA)
begin
case CODE_DATA is
-- +
when X"2B" =>
instructionsPointer <= I_INC;
-- ,
when X"2C" =>
instructionsPointer <= I_INPUT;
-- -
when X"2D" =>
instructionsPointer <= I_DEC;
-- .
when X"2E" =>
instructionsPointer <= I_OUTPUT;
-- <
when X"3C" =>
instructionsPointer <= I_MOVE_LEFT;
-- >
when X"3E" =>
instructionsPointer <= I_MOVE_RIGHT;
-- [
when X"5B" =>
instructionsPointer <= I_LOOP_START;
-- ]
when X"5D" =>
instructionsPointer <= I_LOOP_END;
-- EOF
when X"00" =>
instructionsPointer <= I_NOOP;
when others =>
instructionsPointer <= I_IDLE;
end case;
end process;
-- Proces pro pocitadlo counter
counter: process (RESET, CLK)
begin
if (RESET = '1') then
counterRegister <= "00000000";
elsif (CLK'event and CLK = '1') then
if (counterInc = '1') then
counterRegister <= counterRegister + 1;
elsif (counterDec = '1') then
counterRegister <= counterRegister - 1;
elsif (counterSet = '1') then
counterRegister <= "00000001";
end if;
end if;
end process;
-- Proces pro pocitadlo pointer
pointer: process (RESET, CLK)
begin
if (RESET = '1') then
pointerRegister <= "0000000000";
elsif (CLK'event and CLK = '1') then
if (pointerInc = '1') then
pointerRegister <= pointerRegister + 1;
elsif (pointerDec = '1') then
pointerRegister <= pointerRegister - 1;
end if;
end if;
end process;
-- Proces pro pocitadlo pc
pc: process (RESET, CLK)
begin
if (RESET = '1') then
pcRegister <= "000000000000";
elsif (CLK'event and CLK = '1') then
if (pcInc = '1') then
pcRegister <= pcRegister + 1;
elsif (pcDec = '1') then
pcRegister <= pcRegister - 1;
end if;
end if;
end process;
-- Present state
cpuPresentStateProcess: process (RESET, CLK, EN)
begin
if (RESET = '1') then
cpuPresentState <= S_IDLE;
elsif (CLK'event and CLK = '1') then
if (EN = '1') then
cpuPresentState <= cpuNextState;
end if;
end if;
end process;
-- Next state
cpuNextStateProcess: process (CODE_DATA, DATA_RDATA, EN, IN_DATA, IN_VLD, OUT_BUSY, cpuPresentState, instructionsPointer, counterRegister)
begin
CODE_EN <= '0';
DATA_EN <= '0';
OUT_WE <= '0';
IN_REQ <= '0';
counterInc <= '0';
counterDec <= '0';
counterSet <= '0';
pointerSet <= '0';
pointerInc <= '0';
pointerDec <= '0';
pcSet <= '0';
pcInc <= '0';
pcDec <= '0';
cpuNextState <= S_IDLE;
case cpuPresentState is
-- Pocatecni stav
when S_IDLE =>
CODE_EN <= '1';
cpuNextState <= S_LOAD;
-- Konecny stav
when S_STOP =>
cpuNextState <= S_STOP;
-- Inc
when S_INC =>
DATA_WDATA <= DATA_RDATA + 1;
DATA_RDWR <= '1';
DATA_EN <= '1';
pcInc <= '1';
cpuNextState <= S_IDLE;
-- Dec
when S_DEC =>
DATA_WDATA <= DATA_RDATA - 1;
DATA_RDWR <= '1';
DATA_EN <= '1';
pcInc <= '1';
cpuNextState <= S_IDLE;
-- Out
when S_OUT =>
if (OUT_BUSY = '0') then
OUT_DATA <= DATA_RDATA;
OUT_WE <= '1';
pcInc <= '1';
cpuNextState <= S_IDLE;
else
cpuNextState <= S_OUT;
end if;
-- In
when S_IN =>
if (IN_VLD = '1') then
DATA_RDWR <= '1';
DATA_WDATA <= IN_DATA;
DATA_EN <= '1';
pcInc <= '1';
cpuNextState <= S_IDLE;
else
IN_REQ <= '1';
cpuNextState <= S_IN;
end if;
-- Nacani a dekodovani instrukci
when S_LOAD =>
case instructionsPointer is
-- +
when I_INC =>
DATA_EN <= '1';
DATA_RDWR <= '0';
cpuNextState <= S_INC;
-- -
when I_DEC =>
DATA_EN <= '1';
DATA_RDWR <= '0';
cpuNextState <= S_DEC;
-- <
when I_MOVE_LEFT =>
pointerDec <= '1';
pcInc <= '1';
cpuNextState <= S_IDLE;
-- >
when I_MOVE_RIGHT =>
pointerInc <= '1';
pcInc <= '1';
cpuNextState <= S_IDLE;
-- [
when I_LOOP_START =>
DATA_EN <= '1';
DATA_RDWR <= '0';
cpuNextState <= S_LOOP_START;
-- ]
when I_LOOP_END =>
DATA_EN <= '1';
DATA_RDWR <= '0';
cpuNextState <= S_LOOP_END;
-- .
when I_OUTPUT =>
DATA_EN <= '1';
DATA_RDWR <= '0';
cpuNextState <= S_OUT;
-- ,
when I_INPUT =>
IN_REQ <= '1';
cpuNextState <= S_IN;
-- EOF
when I_NOOP =>
cpuNextState <= S_STOP;
--
when others =>
pcInc <= '1';
cpuNextState <= S_IDLE;
end case;
-- Loop start
when S_LOOP_START =>
if (DATA_RDATA = 0) then
counterInc <= '1';
pcInc <= '1';
cpuNextState <= S_LOOP_CONT_END;
else
pcInc <= '1';
cpuNextState <= S_IDLE;
end if;
-- Loop end
when S_LOOP_END =>
if (DATA_RDATA = 0) then
pcInc <= '1';
cpuNextState <= S_IDLE;
else
pcDec <= '1';
counterSet <= '1';
cpuNextState <= S_LOOP_REV_END;
end if;
-- Loop forward
when S_LOOP_CONT =>
if (counterRegister = 0) then
cpuNextState <= S_IDLE;
elsif (instructionsPointer = I_LOOP_END) then
pcInc <= '1';
counterDec <= '1';
cpuNextState <= S_LOOP_CONT_END;
elsif (instructionsPointer = I_LOOP_START) then
pcInc <= '1';
counterInc <= '1';
cpuNextState <= S_LOOP_CONT_END;
else
pcInc <= '1';
cpuNextState <= S_LOOP_CONT_END;
end if;
-- Loop rev
when S_LOOP_REV =>
if (instructionsPointer = I_LOOP_END) then
counterInc <= '1';
pcDec <= '1';
cpuNextState <= S_LOOP_REV_END;
elsif (instructionsPointer = I_LOOP_START and counterRegister = 1) then
counterDec <= '1';
cpuNextState <= S_IDLE;
elsif (instructionsPointer = I_LOOP_START) then
pcDec <= '1';
counterDec <= '1';
cpuNextState <= S_LOOP_REV_END;
else
pcDec <= '1';
CODE_EN <= '1';
cpuNextState <= S_LOOP_REV_END;
end if;
-- Loop end forward
when S_LOOP_CONT_END =>
CODE_EN <= '1';
cpuNextState <= S_LOOP_CONT;
-- Loop end rev
when S_LOOP_REV_END =>
CODE_EN <= '1';
cpuNextState <= S_LOOP_REV;
when others =>
cpuNextState <= S_IDLE;
end case; -- case present state
end process;
end behavioral;
| apache-2.0 | ac400f8d7cace6c3486633db13ec3fcb | 0.50374 | 3.850918 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/intra_prediction_core.vhd | 1 | 35,713 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity intra_prediction_core is
port(
clk : in std_logic;
rst : in std_logic;
--interface to enable "set samples" command
sample_data : in std_logic_vector(31 downto 0);
sample_write_addr : in unsigned(7 downto 0);
sample_write_enable : in std_logic;
--interface to enable "perform prediction" command
block_size : in unsigned(7 downto 0);
mode : in unsigned(7 downto 0);
row_addr : in unsigned(7 downto 0);
availible_mask : in std_logic_vector(31 downto 0);
row_data : out unsigned(127 downto 0)
);
end entity intra_prediction_core;
architecture rtl of intra_prediction_core is
constant dc_default : unsigned := "0000000010000000";
type row is array(15 downto 0) of unsigned(7 downto 0);
type macroblock_type is array (15 downto 0) of row;
signal macroblock : macroblock_type;
type sample_reg is array(8 downto 0) of std_logic_vector(31 downto 0);
signal samples_d, samples_q : sample_reg;
type samples_type is array(32 downto 0) of std_logic_vector(7 downto 0);
signal the_samples : samples_type;
type sample_array_row is array(16 downto 0) of unsigned(9 downto 0);
type sample_array_type is array(16 downto 0) of sample_array_row;
signal sample_array : sample_array_type;
signal dc_4_value : unsigned(15 downto 0);
signal dc_8_value : unsigned(15 downto 0);
signal dc_16_value : unsigned(15 downto 0);
signal dc_value : unsigned(9 downto 0);
type plane_value_row_type is array(16 downto 0) of signed(33 downto 0);
type plane_value_array_type is array(16 downto 0) of plane_value_row_type;
type plane_hv_type is array(7 downto 0) of signed(17 downto 0);
signal h,v : plane_hv_type;
signal a,b,c : signed(25 downto 0);
begin
--register file for holding sample data
reg_file: process(clk, rst) begin
if rst = '1' then
samples_q <= (others => (others => '0'));
elsif rising_edge(clk) then
samples_q <= samples_d;
end if;
end process;
reg_file_update: for i in 8 downto 0 generate
samples_d(i) <= sample_data when sample_write_enable = '1' and i = to_integer(unsigned(sample_write_addr))
else samples_q(i);
end generate;
--place neighbor samples into sample array
-- y\x-->
-- | \ |<--0--->| |<--1--->| |<--2--->| |<--3--->| |<-4->|
-- | \ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
-- | \___________________________________________________
--___ V 0 |0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
-- 1 |17 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 5 2 |18 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 3 |19 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
--___ 4 |20 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 5 |21 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 6 6 |22 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 7 |23 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
--___ 8 |24 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 9 |25 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 7 10 |26 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 11 |27 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
--___ 12 |28 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 13 |29 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 8 14 |30 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 15 |31 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
--___ 16 |32 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
the_samples(0) <= samples_q(0)(31 downto 24);
the_samples(1) <= samples_q(0)(23 downto 16);
the_samples(2) <= samples_q(0)(15 downto 8 );
the_samples(3) <= samples_q(0)(7 downto 0 );
the_samples(4) <= samples_q(1)(31 downto 24);
the_samples(5) <= samples_q(1)(23 downto 16);
the_samples(6) <= samples_q(1)(15 downto 8 );
the_samples(7) <= samples_q(1)(7 downto 0 );
the_samples(8) <= samples_q(2)(31 downto 24);
the_samples(9) <= samples_q(2)(23 downto 16);
the_samples(10) <= samples_q(2)(15 downto 8 );
the_samples(11) <= samples_q(2)(7 downto 0 );
the_samples(12) <= samples_q(3)(31 downto 24);
the_samples(13) <= samples_q(3)(23 downto 16);
the_samples(14) <= samples_q(3)(15 downto 8 );
the_samples(15) <= samples_q(3)(7 downto 0 );
the_samples(16) <= samples_q(4)(7 downto 0 );
the_samples(17) <= samples_q(5)(31 downto 24);
the_samples(18) <= samples_q(5)(23 downto 16);
the_samples(19) <= samples_q(5)(15 downto 8 );
the_samples(20) <= samples_q(5)(7 downto 0 );
the_samples(21) <= samples_q(6)(31 downto 24);
the_samples(22) <= samples_q(6)(23 downto 16);
the_samples(23) <= samples_q(6)(15 downto 8 );
the_samples(24) <= samples_q(6)(7 downto 0 );
the_samples(25) <= samples_q(7)(31 downto 24);
the_samples(26) <= samples_q(7)(23 downto 16);
the_samples(27) <= samples_q(7)(15 downto 8 );
the_samples(28) <= samples_q(7)(7 downto 0 );
the_samples(29) <= samples_q(8)(31 downto 24);
the_samples(30) <= samples_q(8)(23 downto 16);
the_samples(31) <= samples_q(8)(15 downto 8 );
the_samples(32) <= samples_q(8)(7 downto 0 );
sample_array( 0 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 0 )));
sample_array( 0 )( 1 ) <= unsigned(std_logic_vector'("00"&the_samples( 1 )));
sample_array( 0 )( 2 ) <= unsigned(std_logic_vector'("00"&the_samples( 2 )));
sample_array( 0 )( 3 ) <= unsigned(std_logic_vector'("00"&the_samples( 3 )));
sample_array( 0 )( 4 ) <= unsigned(std_logic_vector'("00"&the_samples( 4 )));
sample_array( 0 )( 5 ) <= unsigned(std_logic_vector'("00"&the_samples( 5 )));
sample_array( 0 )( 6 ) <= unsigned(std_logic_vector'("00"&the_samples( 6 )));
sample_array( 0 )( 7 ) <= unsigned(std_logic_vector'("00"&the_samples( 7 )));
sample_array( 0 )( 8 ) <= unsigned(std_logic_vector'("00"&the_samples( 8 )));
sample_array( 0 )( 9 ) <= unsigned(std_logic_vector'("00"&the_samples( 9 )));
sample_array( 0 )( 10 ) <= unsigned(std_logic_vector'("00"&the_samples( 10 )));
sample_array( 0 )( 11 ) <= unsigned(std_logic_vector'("00"&the_samples( 11 )));
sample_array( 0 )( 12 ) <= unsigned(std_logic_vector'("00"&the_samples( 12 )));
sample_array( 0 )( 13 ) <= unsigned(std_logic_vector'("00"&the_samples( 13 )));
sample_array( 0 )( 14 ) <= unsigned(std_logic_vector'("00"&the_samples( 14 )));
sample_array( 0 )( 15 ) <= unsigned(std_logic_vector'("00"&the_samples( 15 )));
sample_array( 0 )( 16 ) <= unsigned(std_logic_vector'("00"&the_samples( 16 )));
sample_array( 1 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 17 )));
sample_array( 2 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 18 )));
sample_array( 3 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 19 )));
sample_array( 4 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 20 )));
sample_array( 5 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 21 )));
sample_array( 6 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 22 )));
sample_array( 7 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 23 )));
sample_array( 8 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 24 )));
sample_array( 9 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 25 )));
sample_array( 10 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 26 )));
sample_array( 11 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 27 )));
sample_array( 12 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 28 )));
sample_array( 13 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 29 )));
sample_array( 14 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 30 )));
sample_array( 15 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 31 )));
sample_array( 16 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 32 )));
--calculate dc values
dc_4_value <= shift_right(("000000"&sample_array(1)(0)) +
("000000"&sample_array(2)(0)) +
("000000"&sample_array(3)(0)) +
("000000"&sample_array(4)(0)) +
("000000"&sample_array(0)(1)) +
("000000"&sample_array(0)(2)) +
("000000"&sample_array(0)(3)) +
("000000"&sample_array(0)(4)) +
to_unsigned(4, 16), 3) when (and_reduce(availible_mask(31 downto 28)) and
and_reduce(availible_mask(15 downto 12))) = '1' else
shift_right(("000000"&sample_array(1)(0)) +
("000000"&sample_array(2)(0)) +
("000000"&sample_array(3)(0)) +
("000000"&sample_array(4)(0)) +
to_unsigned(2, 16), 2) when and_reduce(availible_mask(31 downto 28)) = '1' else
shift_right(("000000"&sample_array(0)(1)) +
("000000"&sample_array(0)(2)) +
("000000"&sample_array(0)(3)) +
("000000"&sample_array(0)(4)) +
to_unsigned(2, 16), 2) when and_reduce(availible_mask(15 downto 12)) = '1' else
dc_default;
--dc_8_value <= shift_right(("000000"&sample_array(1)(0)) +
-- ("000000"&sample_array(2)(0)) +
-- ("000000"&sample_array(3)(0)) +
-- ("000000"&sample_array(4)(0)) +
-- ("000000"&sample_array(5)(0)) +
-- ("000000"&sample_array(6)(0)) +
-- ("000000"&sample_array(7)(0)) +
-- ("000000"&sample_array(8)(0)) +
-- ("000000"&sample_array(0)(1)) +
-- ("000000"&sample_array(0)(2)) +
-- ("000000"&sample_array(0)(3)) +
-- ("000000"&sample_array(0)(4)) +
-- ("000000"&sample_array(0)(5)) +
-- ("000000"&sample_array(0)(6)) +
-- ("000000"&sample_array(0)(7)) +
-- ("000000"&sample_array(0)(8)) +
-- to_unsigned(8, 16), 4) when (and_reduce(availible_mask(31 downto 24)) and
-- and_reduce(availible_mask(15 downto 8))) = '1' else
-- shift_right(("000000"&sample_array(1)(0)) +
-- ("000000"&sample_array(2)(0)) +
-- ("000000"&sample_array(3)(0)) +
-- ("000000"&sample_array(4)(0)) +
-- ("000000"&sample_array(4)(0)) +
-- ("000000"&sample_array(5)(0)) +
-- ("000000"&sample_array(6)(0)) +
-- ("000000"&sample_array(7)(0)) +
-- ("000000"&sample_array(8)(0)) +
-- to_unsigned(4, 16), 3) when and_reduce(availible_mask(31 downto 24)) = '1' else
-- shift_right(("000000"&sample_array(0)(1)) +
-- ("000000"&sample_array(0)(2)) +
-- ("000000"&sample_array(0)(3)) +
-- ("000000"&sample_array(0)(4)) +
-- ("000000"&sample_array(0)(4)) +
-- ("000000"&sample_array(0)(5)) +
-- ("000000"&sample_array(0)(6)) +
-- ("000000"&sample_array(0)(7)) +
-- ("000000"&sample_array(0)(8)) +
-- to_unsigned(4, 16), 3) when and_reduce(availible_mask(15 downto 8)) = '1' else
-- dc_default;
dc_16_value <= shift_right(("000000"&sample_array(1 )(0)) +
("000000"&sample_array(2 )(0)) +
("000000"&sample_array(3 )(0)) +
("000000"&sample_array(4 )(0)) +
("000000"&sample_array(5 )(0)) +
("000000"&sample_array(6 )(0)) +
("000000"&sample_array(7 )(0)) +
("000000"&sample_array(8 )(0)) +
("000000"&sample_array(9 )(0)) +
("000000"&sample_array(10)(0)) +
("000000"&sample_array(11)(0)) +
("000000"&sample_array(12)(0)) +
("000000"&sample_array(13)(0)) +
("000000"&sample_array(14)(0)) +
("000000"&sample_array(15)(0)) +
("000000"&sample_array(16)(0)) +
("000000"&sample_array(0)(1 )) +
("000000"&sample_array(0)(2 )) +
("000000"&sample_array(0)(3 )) +
("000000"&sample_array(0)(4 )) +
("000000"&sample_array(0)(5 )) +
("000000"&sample_array(0)(6 )) +
("000000"&sample_array(0)(7 )) +
("000000"&sample_array(0)(8 )) +
("000000"&sample_array(0)(9 )) +
("000000"&sample_array(0)(10)) +
("000000"&sample_array(0)(11)) +
("000000"&sample_array(0)(12)) +
("000000"&sample_array(0)(13)) +
("000000"&sample_array(0)(14)) +
("000000"&sample_array(0)(15)) +
("000000"&sample_array(0)(16)) +
to_unsigned(16, 16), 5) when and_reduce(availible_mask(31 downto 0)) = '1' else
shift_right(("000000"&sample_array(1 )(0)) +
("000000"&sample_array(2 )(0)) +
("000000"&sample_array(3 )(0)) +
("000000"&sample_array(4 )(0)) +
("000000"&sample_array(5 )(0)) +
("000000"&sample_array(6 )(0)) +
("000000"&sample_array(7 )(0)) +
("000000"&sample_array(8 )(0)) +
("000000"&sample_array(9 )(0)) +
("000000"&sample_array(10)(0)) +
("000000"&sample_array(11)(0)) +
("000000"&sample_array(12)(0)) +
("000000"&sample_array(13)(0)) +
("000000"&sample_array(14)(0)) +
("000000"&sample_array(15)(0)) +
("000000"&sample_array(16)(0)) +
to_unsigned(8, 16), 4) when and_reduce(availible_mask(31 downto 16)) = '1' else
shift_right(("000000"&sample_array(0)(1 )) +
("000000"&sample_array(0)(2 )) +
("000000"&sample_array(0)(3 )) +
("000000"&sample_array(0)(4 )) +
("000000"&sample_array(0)(5 )) +
("000000"&sample_array(0)(6 )) +
("000000"&sample_array(0)(7 )) +
("000000"&sample_array(0)(8 )) +
("000000"&sample_array(0)(9 )) +
("000000"&sample_array(0)(10)) +
("000000"&sample_array(0)(11)) +
("000000"&sample_array(0)(12)) +
("000000"&sample_array(0)(13)) +
("000000"&sample_array(0)(14)) +
("000000"&sample_array(0)(15)) +
("000000"&sample_array(0)(16)) +
to_unsigned(8, 16), 4) when and_reduce(availible_mask(15 downto 0)) = '1' else
dc_default;
dc_value <= dc_4_value(9 downto 0) when block_size = to_unsigned(4, 8) else
--dc_8_value(9 downto 0) when block_size = to_unsigned(8, 8) else
dc_16_value(9 downto 0) when block_size = to_unsigned(16, 8) else
"1010101010"; --make errors obvious
-- some values needed for plane mode
a <= signed(shift_left( ("0000000000000000"&sample_array(0)(16)) + ("000000000000000"&sample_array(16)(0)), 4)) when block_size = 16 else
signed(shift_left( ("0000000000000000"&sample_array(0)(8 )) + ("000000000000000"&sample_array(8 )(0)), 4));
b <= shift_right( to_signed(5, 8) * h(7) + to_signed(32, 26) , 6) when block_size = 16 else
shift_right( to_signed(34, 8) * h(7) + to_signed(32, 26) , 6);
c <= shift_right( to_signed(5, 8) * v(7) + to_signed(32, 26) , 6) when block_size = 16 else
shift_right( to_signed(34, 8) * v(7) + to_signed(32, 26) , 6);
v(0) <= to_signed(1, 8) * (signed(sample_array(9)(0)) - signed(sample_array(7)(0))) when block_size = 16 else
to_signed(1, 8) * (signed(sample_array(5)(0)) - signed(sample_array(3)(0)));
h(0) <= to_signed(1, 8) * (signed(sample_array(0)(9)) - signed(sample_array(0)(7))) when block_size = 16 else
to_signed(1, 8) * (signed(sample_array(0)(5)) - signed(sample_array(0)(3)));
calc_h_v_plane: for xy in 7 downto 1 generate
v(xy) <= v(xy-1) + to_signed(xy+1,8) * (signed(sample_array(9+xy)(0)) - signed(sample_array(7-xy)(0))) when block_size = 16 else
v(xy-1) + to_signed(xy+1,8) * (signed(sample_array(5+xy)(0)) - signed(sample_array(3-xy)(0))) when block_size = 8 and xy <= 3 else
v(xy-1);
h(xy) <= h(xy-1) + to_signed(xy+1,8) * (signed(sample_array(0)(9+xy)) - signed(sample_array(0)(7-xy))) when block_size = 16 else
h(xy-1) + to_signed(xy+1,8) * (signed(sample_array(0)(5+xy)) - signed(sample_array(0)(3-xy))) when block_size = 8 and xy <= 3 else
h(xy-1);
end generate;
--calculate predicted samples
calculate_samples_row: for i in 16 downto 1 generate
calculate_samples_col: for j in 16 downto 1 generate
constant x : integer := j-1;
constant y : integer := i-1;
constant zVR : integer := 2 * x - y;
constant zVR_mod_2 : integer := zVR mod 2;
constant zVR_sign : integer := integer(sign(real(zVR)));
constant zHD : integer := 2 * y - x;
constant zHD_mod_2 : integer := zHD mod 2;
constant zHD_sign : integer := integer(sign(real(zHD)));
constant y_mod_2 : integer := y mod 2;
constant zHU : integer := x + 2 * y;
constant zHU_mod_2 : integer := zHU mod 2;
constant zHU_13_comp : integer := integer(sign(real(zHU-13)));
signal plane_pre_clip : plane_value_array_type;
signal plane_value : sample_array_type;
begin
plane_pre_clip(i)(j) <= shift_right(("00000000"&a) + b * to_signed(x-7, 8) + c * to_signed(y-7, 8) + to_signed(16, 34) , 5) when block_size = 16 else
shift_right(("00000000"&a) + b * to_signed(x-3, 8) + c * to_signed(y-3, 8) + to_signed(16, 34) , 5);
plane_value(i)(j) <= to_unsigned(0, 10) when plane_pre_clip(i)(j) < to_signed(0, 34) else
to_unsigned(255, 10) when plane_pre_clip(i)(j) > to_signed(255, 34) else
unsigned(plane_pre_clip(i)(j)(9 downto 0));
sample_array(i)(j) <=
--vertical
sample_array(i-1)(j) when mode = 0 else
--horizontal
sample_array(i)(j-1) when mode = 1 else
--dc prediction
dc_value when mode = 2 else
--diag down left
shift_right(sample_array(0)(7) + to_unsigned(3,2) * sample_array(0)(8)(7 downto 0) + to_unsigned(2,10) , 2) when mode = 3 and block_size = 4 and x = 3 and y = 3 else
shift_right(sample_array(0)((y+x+1) mod 17) + to_unsigned(2,2) * sample_array(0)((y+x+2) mod 17)(7 downto 0) + sample_array(0)((y+x+3) mod 17) + to_unsigned(2,10) , 2) when mode = 3 and block_size = 4 and (not(x = 3 and y = 3)) and ((y+x+3) <= 16) else
--shift_right(sample_array(0)(15) + to_unsigned(3,2) * sample_array(0)(16)(7 downto 0) + to_unsigned(2,10) , 2) when mode = 3 and block_size = 8 and x = 7 and y = 7 else
--shift_right(sample_array(0)((y+x+1) mod 17) + to_unsigned(2,2) * sample_array(0)((y+x+2) mod 17)(7 downto 0) + sample_array(0)((y+x+3) mod 17) + to_unsigned(2,10) , 2) when mode = 3 and block_size = 8 and (not(x = 7 and y = 7)) and ((y+x+3) <= 16) else
--diag down right
shift_right(sample_array(abs(y-x-1))(0) + to_unsigned(2,2) * sample_array(abs(y-x))(0)(7 downto 0) + sample_array(abs(y-x+1))(0) + to_unsigned(2,10) , 2) when mode = 4 and (block_size = 4) and (y > x) and ((y-x-1) >= 0)else
shift_right(sample_array(0)(abs(x-y-1)) + to_unsigned(2,2) * sample_array(0)(abs(x-y))(7 downto 0) + sample_array(0)(abs(x-y+1)) + to_unsigned(2,10) , 2) when mode = 4 and (block_size = 4) and (y < x) and ((x-y-1) >= 0)else
shift_right(sample_array(1)(0) + to_unsigned(2,2) * sample_array(0)(0)(7 downto 0) + sample_array(0)(1) + to_unsigned(2,10) , 2) when mode = 4 and (block_size = 4) and (y = x) else
--vertical right
shift_right(sample_array(0)(abs(x - y/2 ) mod 17) + sample_array(0)(abs(x - y/2 + 1) mod 17)(7 downto 0) + to_unsigned(1,10) , 1) when mode = 5 and (block_size = 4) and (zVR_mod_2 = 0) and ((x - y/2 ) >= 0) else
shift_right(sample_array(0)(abs(x - y/2 -1) mod 17) + to_unsigned(2,2) * sample_array(0)(abs(x - y/2 ) mod 17)(7 downto 0) + sample_array(0)(abs(x - y/2+1) mod 17) + to_unsigned(2,10) , 2) when mode = 5 and (block_size = 4) and (zVR_mod_2 = 1) and ((x - y/2 -1) >= 0) else
shift_right(sample_array(1)(0) + to_unsigned(2,2) * sample_array(0)(0)(7 downto 0) + sample_array(0)(1) + to_unsigned(2,10) , 2) when mode = 5 and (block_size = 4) and (zVR = -1) else
shift_right(sample_array(y)(0) + to_unsigned(2,2) * sample_array(y-1)(0)(7 downto 0) + sample_array(y-2)(0) + to_unsigned(2,10) , 2) when mode = 5 and (block_size = 4) and (zVR < -1) and ((y-2) >= 0) else
--horizontal down
shift_right(sample_array(abs(y - x/2) mod 17)(0) + sample_array(abs(y - x/2 + 1) mod 17)(0)(7 downto 0) + to_unsigned(1,10) , 1) when mode = 6 and (block_size = 4) and (zHD_mod_2 = 0) and (zHD >= 0) and ((y - x/2) >= 0)else
shift_right(sample_array(abs(y - x/2-1) mod 17)(0) + to_unsigned(2,2) * sample_array(abs(y - x/2 ) mod 17)(0)(7 downto 0) + sample_array(abs(y - x/2 + 1) mod 17)(0) + to_unsigned(2,10) , 2) when mode = 6 and (block_size = 4) and (zHD_mod_2 = 1) and (zHD >= 0) and ((y - x/2 - 1) >= 0) else
shift_right(sample_array(0)(1) + to_unsigned(2,2) * sample_array(0)(0)(7 downto 0) + sample_array(1)(0) + to_unsigned(2,10) , 2) when mode = 6 and (block_size = 4) and (zHD = -1) else
shift_right(sample_array(0)(x) + to_unsigned(2,2) * sample_array(0)(x-1)(7 downto 0) + sample_array(0)(x-2) + to_unsigned(2,10) , 2) when mode = 6 and (block_size = 4) and (zHD < -1) and ((x-2) >= 0) else
--vertical left
shift_right(sample_array(0)((x + y /2 + 1) mod 17) + sample_array(0)((x+y/2+2) mod 17)(7 downto 0) + to_unsigned(1,10) , 1) when mode = 7 and (block_size = 4) and y_mod_2 = 0 and ((x + y/2+2) <= 16) else
shift_right(sample_array(0)((x + y /2 + 1) mod 17) + to_unsigned(2,2) * sample_array(0)((x+y/2+2) mod 17)(7 downto 0) + sample_array(0)((x+y/2+3) mod 17) + to_unsigned(2,10) , 2) when mode = 7 and (block_size = 4) and y_mod_2 /= 0 and ((x + y/2+3) <= 16) else
--horizontal up
shift_right(sample_array((y + x/2 + 1) mod 17)(0) + sample_array((y+x/2+2) mod 17)(0)(7 downto 0) + to_unsigned(1,10) , 1) when mode = 8 and ((block_size = 4 and zHU < 5) ) and (zHU >= 0) and zHU_mod_2 = 0 else
shift_right(sample_array((y + x/2 + 1) mod 17)(0) + to_unsigned(2,2) * sample_array((y+x/2+2) mod 17)(0)(7 downto 0) + sample_array((y+x/2+3) mod 17)(0) + to_unsigned(2,10) , 2) when mode = 8 and ((block_size = 4 and zHU < 5) ) and (zHU >= 0) and zHU_mod_2 = 1 else
--shift_right(sample_array(7)(0) + to_unsigned(3,2) * sample_array(8)(0)(7 downto 0) + to_unsigned(2,10) , 2) when mode = 8 and block_size = 8 and zHU = 13 else
shift_right(sample_array(3)(0) + to_unsigned(3,2) * sample_array(4)(0)(7 downto 0) + to_unsigned(2,10) , 2) when mode = 8 and block_size = 4 and zHU = 5 else
--sample_array(8)(0) when mode = 8 and block_size = 8 and zHU > 13 else
sample_array(4)(0) when mode = 8 and block_size = 4 and zHU > 5 else
--plane
plane_value(i)(j) when mode = 3 and (block_size = 16 or block_size = 8) else
"0000000001";
end generate;
end generate;
--assign calculated samples to output macro block
assign_smpls_2_mb_row: for i in 15 downto 0 generate
assign_smpls_2_mb_col: for j in 15 downto 0 generate
macroblock(i)(j) <= sample_array(i+1)(j+1)(7 downto 0);
end generate;
end generate;
--output selected macroblock row
--todo: replace with something more reasonable...
row_data <= macroblock(0 )(0)¯oblock(0 )(1)¯oblock(0 )(2)¯oblock(0 )(3)¯oblock(0 )(4)¯oblock(0 )(5)¯oblock(0 )(6)¯oblock(0 )(7)¯oblock(0 )(8)¯oblock(0 )(9)¯oblock(0 )(10)¯oblock(0 )(11)¯oblock(0 )(12)¯oblock(0 )(13)¯oblock(0 )(14)¯oblock(0 )(15) when row_addr = to_unsigned(0 , 8) else
macroblock(1 )(0)¯oblock(1 )(1)¯oblock(1 )(2)¯oblock(1 )(3)¯oblock(1 )(4)¯oblock(1 )(5)¯oblock(1 )(6)¯oblock(1 )(7)¯oblock(1 )(8)¯oblock(1 )(9)¯oblock(1 )(10)¯oblock(1 )(11)¯oblock(1 )(12)¯oblock(1 )(13)¯oblock(1 )(14)¯oblock(1 )(15) when row_addr = to_unsigned(1 , 8) else
macroblock(2 )(0)¯oblock(2 )(1)¯oblock(2 )(2)¯oblock(2 )(3)¯oblock(2 )(4)¯oblock(2 )(5)¯oblock(2 )(6)¯oblock(2 )(7)¯oblock(2 )(8)¯oblock(2 )(9)¯oblock(2 )(10)¯oblock(2 )(11)¯oblock(2 )(12)¯oblock(2 )(13)¯oblock(2 )(14)¯oblock(2 )(15) when row_addr = to_unsigned(2 , 8) else
macroblock(3 )(0)¯oblock(3 )(1)¯oblock(3 )(2)¯oblock(3 )(3)¯oblock(3 )(4)¯oblock(3 )(5)¯oblock(3 )(6)¯oblock(3 )(7)¯oblock(3 )(8)¯oblock(3 )(9)¯oblock(3 )(10)¯oblock(3 )(11)¯oblock(3 )(12)¯oblock(3 )(13)¯oblock(3 )(14)¯oblock(3 )(15) when row_addr = to_unsigned(3 , 8) else
macroblock(4 )(0)¯oblock(4 )(1)¯oblock(4 )(2)¯oblock(4 )(3)¯oblock(4 )(4)¯oblock(4 )(5)¯oblock(4 )(6)¯oblock(4 )(7)¯oblock(4 )(8)¯oblock(4 )(9)¯oblock(4 )(10)¯oblock(4 )(11)¯oblock(4 )(12)¯oblock(4 )(13)¯oblock(4 )(14)¯oblock(4 )(15) when row_addr = to_unsigned(4 , 8) else
macroblock(5 )(0)¯oblock(5 )(1)¯oblock(5 )(2)¯oblock(5 )(3)¯oblock(5 )(4)¯oblock(5 )(5)¯oblock(5 )(6)¯oblock(5 )(7)¯oblock(5 )(8)¯oblock(5 )(9)¯oblock(5 )(10)¯oblock(5 )(11)¯oblock(5 )(12)¯oblock(5 )(13)¯oblock(5 )(14)¯oblock(5 )(15) when row_addr = to_unsigned(5 , 8) else
macroblock(6 )(0)¯oblock(6 )(1)¯oblock(6 )(2)¯oblock(6 )(3)¯oblock(6 )(4)¯oblock(6 )(5)¯oblock(6 )(6)¯oblock(6 )(7)¯oblock(6 )(8)¯oblock(6 )(9)¯oblock(6 )(10)¯oblock(6 )(11)¯oblock(6 )(12)¯oblock(6 )(13)¯oblock(6 )(14)¯oblock(6 )(15) when row_addr = to_unsigned(6 , 8) else
macroblock(7 )(0)¯oblock(7 )(1)¯oblock(7 )(2)¯oblock(7 )(3)¯oblock(7 )(4)¯oblock(7 )(5)¯oblock(7 )(6)¯oblock(7 )(7)¯oblock(7 )(8)¯oblock(7 )(9)¯oblock(7 )(10)¯oblock(7 )(11)¯oblock(7 )(12)¯oblock(7 )(13)¯oblock(7 )(14)¯oblock(7 )(15) when row_addr = to_unsigned(7 , 8) else
macroblock(8 )(0)¯oblock(8 )(1)¯oblock(8 )(2)¯oblock(8 )(3)¯oblock(8 )(4)¯oblock(8 )(5)¯oblock(8 )(6)¯oblock(8 )(7)¯oblock(8 )(8)¯oblock(8 )(9)¯oblock(8 )(10)¯oblock(8 )(11)¯oblock(8 )(12)¯oblock(8 )(13)¯oblock(8 )(14)¯oblock(8 )(15) when row_addr = to_unsigned(8 , 8) else
macroblock(9 )(0)¯oblock(9 )(1)¯oblock(9 )(2)¯oblock(9 )(3)¯oblock(9 )(4)¯oblock(9 )(5)¯oblock(9 )(6)¯oblock(9 )(7)¯oblock(9 )(8)¯oblock(9 )(9)¯oblock(9 )(10)¯oblock(9 )(11)¯oblock(9 )(12)¯oblock(9 )(13)¯oblock(9 )(14)¯oblock(9 )(15) when row_addr = to_unsigned(9 , 8) else
macroblock(10)(0)¯oblock(10)(1)¯oblock(10)(2)¯oblock(10)(3)¯oblock(10)(4)¯oblock(10)(5)¯oblock(10)(6)¯oblock(10)(7)¯oblock(10)(8)¯oblock(10)(9)¯oblock(10)(10)¯oblock(10)(11)¯oblock(10)(12)¯oblock(10)(13)¯oblock(10)(14)¯oblock(10)(15) when row_addr = to_unsigned(10, 8) else
macroblock(11)(0)¯oblock(11)(1)¯oblock(11)(2)¯oblock(11)(3)¯oblock(11)(4)¯oblock(11)(5)¯oblock(11)(6)¯oblock(11)(7)¯oblock(11)(8)¯oblock(11)(9)¯oblock(11)(10)¯oblock(11)(11)¯oblock(11)(12)¯oblock(11)(13)¯oblock(11)(14)¯oblock(11)(15) when row_addr = to_unsigned(11, 8) else
macroblock(12)(0)¯oblock(12)(1)¯oblock(12)(2)¯oblock(12)(3)¯oblock(12)(4)¯oblock(12)(5)¯oblock(12)(6)¯oblock(12)(7)¯oblock(12)(8)¯oblock(12)(9)¯oblock(12)(10)¯oblock(12)(11)¯oblock(12)(12)¯oblock(12)(13)¯oblock(12)(14)¯oblock(12)(15) when row_addr = to_unsigned(12, 8) else
macroblock(13)(0)¯oblock(13)(1)¯oblock(13)(2)¯oblock(13)(3)¯oblock(13)(4)¯oblock(13)(5)¯oblock(13)(6)¯oblock(13)(7)¯oblock(13)(8)¯oblock(13)(9)¯oblock(13)(10)¯oblock(13)(11)¯oblock(13)(12)¯oblock(13)(13)¯oblock(13)(14)¯oblock(13)(15) when row_addr = to_unsigned(13, 8) else
macroblock(14)(0)¯oblock(14)(1)¯oblock(14)(2)¯oblock(14)(3)¯oblock(14)(4)¯oblock(14)(5)¯oblock(14)(6)¯oblock(14)(7)¯oblock(14)(8)¯oblock(14)(9)¯oblock(14)(10)¯oblock(14)(11)¯oblock(14)(12)¯oblock(14)(13)¯oblock(14)(14)¯oblock(14)(15) when row_addr = to_unsigned(14, 8) else
macroblock(15)(0)¯oblock(15)(1)¯oblock(15)(2)¯oblock(15)(3)¯oblock(15)(4)¯oblock(15)(5)¯oblock(15)(6)¯oblock(15)(7)¯oblock(15)(8)¯oblock(15)(9)¯oblock(15)(10)¯oblock(15)(11)¯oblock(15)(12)¯oblock(15)(13)¯oblock(15)(14)¯oblock(15)(15) when row_addr = to_unsigned(15, 8) else
to_unsigned(0, 128);
end architecture rtl; | mit | 7e0fad887e209f316ba99b263391deea | 0.470641 | 3.594665 | false | false | false | false |
freecores/line_codes | rtl/vhdl/hdb1_enc.vhd | 1 | 949 |
-- implementation of the HDB1 encoder.
entity hdb1_enc is
port (
clr_bar,
clk : in bit; -- clock input.
e : in bit; -- input.
s0, s1 : out bit -- output.
);
end hdb1_enc;
architecture behaviour of hdb1_enc is
signal q0, q1, q2 : bit; -- 3 flipflops for 6 states.
begin
process (clk, clr_bar) begin
if clr_bar = '0' then
q0 <= '0';
q1 <= '0';
q2 <= '0';
s0 <= '0';
s1 <= '0';
elsif clk'event and clk = '1' then
q0 <= (e and (not q1))
or ((not e) and (not q0) and q1 and q2 )
or ((not e) and q0 and q1 and (not q2) );
q1 <= (e and (not q1))
or ((not q1) and q2)
or ((not e) and q1 and (not q2));
q2 <= (not e) and (not q2);
s0 <= ((not q1) and (not q2))
or ((not e)and q1 and q2);
s1 <= (q1 and (not q2))
or ((not e) and (not q1) and q2);
end if;
end process;
end behaviour;
| gpl-2.0 | 07d3b8e1f943c527fcdd99aff15383dc | 0.483667 | 2.557951 | false | false | false | false |
boztalay/OldProjects | FPGA/Components/Comp_16bitShiftReg/Comp_16bitShiftReg/Comp_16bitShiftReg.vhd | 1 | 2,295 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 15:07:41 06/08/2009
-- Design Name:
-- Module Name: Comp_16bitShiftReg - Behavioral
-- Project Name: 16-Bit Shift Register
-- Target Devices:
-- Tool versions:
-- Description: A 16-bit shift register, no reset, activates on the falling edge
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity Comp_16bitShiftReg is
Port ( CLK : in STD_LOGIC;
Data : in STD_LOGIC;
Parallel : out STD_LOGIC_VECTOR (15 downto 0);
Carry : out STD_LOGIC);
end Comp_16bitShiftReg;
architecture Behavioral of Comp_16bitShiftReg is
--\Signals/--
signal Buf_CLK : STD_LOGIC;
signal Buf_Data : STD_LOGIC;
--/Signals\--
begin
--\BUFG Instantiations/--
BUFG_BufCLK : BUFG
port map (
O => Buf_CLK,
I => CLK
);
BUFG_BufData : BUFG
port map (
O => Buf_Data,
I => Data
);
--/BUFG Instantiations\--
main : process(Buf_CLK, Buf_Data)
variable storage : STD_LOGIC_VECTOR(15 downto 0) := "0000000000000000";
variable storage2 : STD_LOGIC_VECTOR(15 downto 0) := "0000000000000000";
begin
if (Buf_CLK'event and Buf_CLK = '0') then
storage2(0) := Buf_Data;
storage2(1) := storage(0);
storage2(2) := storage(1);
storage2(3) := storage(2);
storage2(4) := storage(3);
storage2(5) := storage(4);
storage2(6) := storage(5);
storage2(7) := storage(6);
storage2(8) := storage(7);
storage2(9) := storage(8);
storage2(10) := storage(9);
storage2(11) := storage(10);
storage2(12) := storage(11);
storage2(13) := storage(12);
storage2(14) := storage(13);
storage2(15) := storage(14);
Carry <= storage(15);
storage := storage2;
Parallel <= storage;
end if;
end process;
end Behavioral;
| mit | f3eeacd427c51b46399cb77201223a25 | 0.576906 | 3.316474 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/tsotnep/volume_pregain_v1_0/75ddc6aa/hdl/Volume_Pregain_v1_0_S00_AXI.vhd | 2 | 16,087 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Volume_Pregain_v1_0_S00_AXI is
generic (
-- Users to add parameters here
INTBIT_WIDTH : integer;
FRACBIT_WIDTH : integer;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
OUT_VOLCTRL_L : out signed((24 - 1) downto 0) := (others => '0'); -- 24 bit signed output
OUT_VOLCTRL_R : out signed((24 - 1) downto 0) := (others => '0'); -- 24 bit signed output
OUT_RDY : out STD_LOGIC;
IN_SIG_L : in signed((24 - 1) downto 0); --amplifier input signal 24-bit
IN_SIG_R : in signed((24 - 1) downto 0); --amplifier input signal 24-bit
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end Volume_Pregain_v1_0_S00_AXI;
architecture arch_imp of Volume_Pregain_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 4
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00" =>
reg_data_out <= slv_reg0;
when b"01" =>
reg_data_out <= slv_reg1;
when b"10" =>
reg_data_out <= slv_reg2;
when b"11" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
Volume_Pregain_Top_Module_inst : entity work.Volume_Pregain_Top_Module
generic map(
INTBIT_WIDTH => INTBIT_WIDTH,
FRACBIT_WIDTH => FRACBIT_WIDTH
)
port map(
OUT_VOLCTRL_L => OUT_VOLCTRL_L,
OUT_VOLCTRL_R => OUT_VOLCTRL_R,
OUT_RDY => OUT_RDY,
IN_SIG_L => IN_SIG_L,
IN_SIG_R => IN_SIG_R,
CLK_100mhz => S_AXI_ACLK,
IN_COEF_L => signed(slv_reg0),
IN_COEF_R => signed(slv_reg1),
RESET => (not S_AXI_ARESETN)
);
-- User logic ends
end arch_imp;
| lgpl-3.0 | fb044c6d76338e0e1a33370f2b9e19b0 | 0.609561 | 3.458083 | false | false | false | false |
boztalay/OldProjects | FPGA/Components/Comp_FrequencyDivider/Comp_FrequencyDivider.vhd | 1 | 1,772 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 22:15:19 04/10/2009
-- Design Name:
-- Module Name: Comp_DivideBy50Mil - Behavioral
-- Project Name: Frequency Divider
-- Target Devices:
-- Tool versions:
-- Description: A frequency divider for use by a digital clock. Takes the Nexys 2 50Mhz clock
-- and produces a 1Hz clock and 500Hz clock.
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Comp_FrequencyDivider is
Port ( SysCLK : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end Comp_FrequencyDivider;
architecture Behavioral of Comp_FrequencyDivider is
signal cntr : STD_LOGIC_VECTOR (25 downto 0);
signal cntr2 : STD_LOGIC_VECTOR (16 downto 0);
begin
process (SysCLK)
begin
if SysCLK'event and SysCLK = '0' then
cntr <= cntr + 1;
if cntr = "01011111010111100001000000" then
out1 <= '1';
end if;
if cntr = "10111110101111000010000000" then
out1 <= '0';
cntr <= "00000000000000000000000000";
end if;
end if;
if SysCLK'event and SysCLK = '0' then
cntr2 <= cntr2 + 1;
if cntr2 = "01100001101010000" then
out2 <= '1';
end if;
if cntr2 = "11000011010100000" then
out2 <= '0';
cntr2 <= "00000000000000000";
end if;
end if;
end process;
end Behavioral;
| mit | 0bc0a418175b0621d13a9df93027bd2f | 0.611174 | 3.623722 | false | false | false | false |
boztalay/OldProjects | FPGA/FlashProgrammer/FlashProgrammer_TB.vhd | 1 | 3,351 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:08:29 11/26/2009
-- Design Name:
-- Module Name: E:/FPGA/Projects/Current Projects/Subsystems/FlashProgrammer/FlashProgrammer_TB.vhd
-- Project Name: FlashProgrammer
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: FlashProgrammer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY FlashProgrammer_TB IS
END FlashProgrammer_TB;
ARCHITECTURE behavior OF FlashProgrammer_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT FlashProgrammer
PORT(
board_clk : IN std_logic;
start_button : IN std_logic;
flashSTS : IN std_logic;
flashWE : OUT std_logic;
flashOE : OUT std_logic;
flashCE : OUT std_logic;
flashADDR : OUT std_logic_vector(22 downto 0);
flashDATA : INOUT std_logic_vector(15 downto 0);
flashRP : OUT std_logic;
flashDATA_to_LEDs : OUT std_logic_vector(6 downto 0);
status_LED : OUT std_logic
);
END COMPONENT;
--Inputs
signal board_clk : std_logic := '0';
signal start_button : std_logic := '0';
signal flashSTS : std_logic := '0';
--BiDirs
signal flashDATA : std_logic_vector(15 downto 0);
--Outputs
signal flashWE : std_logic;
signal flashOE : std_logic;
signal flashCE : std_logic;
signal flashADDR : std_logic_vector(22 downto 0);
signal flashRP : std_logic;
signal flashDATA_to_LEDs : std_logic_vector(6 downto 0);
signal status_LED : std_logic;
-- Clock period definitions
constant board_clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: FlashProgrammer PORT MAP (
board_clk => board_clk,
start_button => start_button,
flashSTS => flashSTS,
flashWE => flashWE,
flashOE => flashOE,
flashCE => flashCE,
flashADDR => flashADDR,
flashDATA => flashDATA,
flashRP => flashRP,
flashDATA_to_LEDs => flashDATA_to_LEDs,
status_LED => status_LED
);
-- Clock process definitions
board_clk_process :process
begin
board_clk <= '0';
wait for board_clk_period/2;
board_clk <= '1';
wait for board_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 5000 ns;
start_button <= '1';
wait for 8000 ns;
start_button <= '0';
flashSTS <= '0';
wait for 4000 ns;
flashSTS <= '1';
wait;
end process;
END;
| mit | a8db085031398580b7421bf8eb5dca05 | 0.583408 | 3.838488 | false | true | false | false |
DaveyPocket/btrace448 | core/debounce.vhd | 1 | 1,273 | -- Btrace 448
-- Debounce Device
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity debouncer is
generic(DD, k: integer);
port(input, clk, reset: in std_logic;
output: out std_logic);
end debouncer;
architecture circuit of debouncer is
component debounceCounter
generic(k: integer);
port(en, rst, clk: in std_logic;
Q: out std_logic_vector(k-1 downto 0));
end component;
component dff
port(D, clk, set, rst: in std_logic;
Q: out std_logic);
end component;
signal previous_input: std_logic;
signal count: std_logic;
signal Q: std_logic_vector(k-1 downto 0);
signal mux_out: std_logic;
signal inReset: std_logic;
signal force1: std_logic;
signal onCompare: std_logic;
signal bufOut: std_logic;
begin
flip: dff port map (input, clk, '0', '0', previous_input);
flop: dff port map (mux_out, clk, '0', '0', bufOut);
sandal: dff port map (count, clk, force1, inReset, count);
counter: debounceCounter generic map (k) port map (count, inReset, clk, Q);
force1 <= (input xor previous_input) and not(count);
inReset <= reset or onCompare;
onCompare <= '1' when (to_integer(unsigned(Q)) = (DD - 1)) else '0';
mux_out <= input when count = '0' else bufOut;
output <= bufOut;
end circuit;
| gpl-3.0 | b142a13296c6723e1817470d9319bbe7 | 0.692852 | 2.867117 | false | false | false | false |
DaveyPocket/btrace448 | core/compare.vhd | 1 | 909 | -- Btrace 448
-- (un)signed Comparison
-- Bradley Boccuzzi
-- 2016
--! Remove from project
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.btrace_pack.all;
entity compare is
generic(N: integer := 8;
op: comp_op);
port(a, b: in std_logic_vector(N-1 downto 0);
c: out std_logic);
end compare;
architecture arch_unsigned of compare is
signal comparison: boolean;
begin
with op select
comparison <= unsigned(a) > unsigned(b) when gt,
unsigned(a) >= unsigned(b) when gte,
unsigned(a) = unsigned(b) when others;
c <= '1' when comparison = true else '0';
end arch_unsigned;
architecture arch_signed of compare is
signal comparison: boolean;
begin
with op select
comparison <= signed(a) > signed(b) when gt,
signed(a) >= signed(b) when gte,
signed(a) = signed(b) when others;
c <= '1' when comparison = true else '0';
end arch_signed;
| gpl-3.0 | 4c8b45853987858897ae9d0192dd9c81 | 0.677668 | 3.123711 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/user.org/zed_audio_v1_0/8de2dafc/hdl/clocking.vhd | 2 | 4,725 |
------------------------------------------------------------------------------
-- Simplified clock generation of Hamster Work's design
-- DC9ST
-- TU Kaiserslautern, Germany
-- 2014
-- simple clock generator based on MMCME2_ADV primitive to generate 48 MHz out of 100 MHz system clock
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____48.000______0.000______50.0______273.634____296.868
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clocking is
port
(-- Clock in ports
CLK_100 : in std_logic;
-- Clock out ports
CLK_48 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end clocking;
architecture xilinx of clocking is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clocking,clk_wiz_v3_6,{component_name=clocking,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal zed_audio_clk_48M : std_logic;
signal clk_feedback : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_100);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are left open
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
--COMPENSATION => "ZHOLD",
--COMPENSATION => "BUF_IN",
COMPENSATION => "INTERNAL",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 5,
CLKFBOUT_MULT_F => 49.500,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 20.625,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clk_feedback,
CLKFBOUTB => open,
CLKOUT0 => zed_audio_clk_48M,
CLKOUT0B => open,
CLKOUT1 => open,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => clk_feedback,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => CLK_48,
I => zed_audio_clk_48M);
end xilinx;
| lgpl-3.0 | 7d6267fe38fbe505dbc2fcce01d9e63f | 0.486349 | 4.133858 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia/rs232out.vhd | 1 | 6,083 | -- ########################################################################
-- $Software: busiac
-- $section : hardware component
-- $Id: rs232out.vhd 322 2015-05-29 06:43:59Z ia $
-- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/rs232out.vhd $
-- $Author : Ivan Auge (Email: [email protected])
-- ########################################################################
--
-- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge.
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- BUSIAC software is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY ; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-- Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with the GNU C Library; see the file COPYING. If not, write to the Free
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
-- ######################################################################*/
-------------------------------------------------------------------------------
-- ATTENTION:
-- Ceci un template, les trous marqués "..." doivent être comblés pour
-- pouvoir être compilé, puis fonctionné.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Ce module sérialise l'entrée DATA de 8 bits sur la sortie TX.
--
-- le format écrit est:
-- - 1 start bit
-- - 8 bit de données
-- - 1 stop bits
--
-- La sortie BUSY indique que le module est en train de sérialiser.
--
-- Pour sérialiser une nouvelle valeur, il faut:
-- * attendre que BUSY soit nul.
-- * la positionner sur DATA et mettre NDATA à 1 au moins 1 cycle.
--
-- Pour fixer le BAUD du composant utilisez les paramètres génériques
-- BAUD et FREQ ci dessous.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity rs232out is
generic(
FREQ : integer := 50000000; -- Frequence de clk
BAUD : integer := 9600); -- Baud de Rx
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
Tx : out STD_LOGIC;
Data : in STD_LOGIC_VECTOR(7 downto 0);
Ndata : in STD_LOGIC;
Busy : out STD_LOGIC);
end rs232out;
architecture montage of rs232out is
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
type T_CMD_i is (NOOP, COUNT, INIT);
signal CMD_i : T_CMD_i ;
signal R_i : integer RANGE 0 TO 15;
signal VT_endLoop: STD_LOGIC;
type T_CMD_baud is (NOOP, COUNT, INIT);
signal CMD_baud : T_CMD_baud ;
signal R_baud: integer RANGE 0 TO (FREQ)/BAUD;
signal VT_endbaud: STD_LOGIC;
type T_CMD_data is (NOOP, SHIFT, INIT);
signal CMD_data : T_CMD_data ;
signal R_data : STD_LOGIC_VECTOR(8 downto 0); -- 0 : 1 start bit
-- 8:1 : 8 data bits
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
--Description des états
type STATE_TYPE is (ST_BEGIN, ST_FOR, ST_ATT, ST_ADV);
signal state : STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
process (clk)
begin if clk'event and clk = '1' then
-- R_i
if ( CMD_i = INIT ) then
R_i <= 11 ;
elsif ( CMD_i = COUNT ) then
R_i <= R_i - 1;
else
R_i <= R_i;
end if;
-- R_baud
if ( CMD_baud = INIT ) then
R_baud <= FREQ/BAUD ;
elsif ( CMD_baud = COUNT ) then
R_baud <= R_baud - 1;
else
R_baud <= R_baud;
end if;
-- R_data
if ( CMD_data = INIT ) then
-- V = E + '0'
R_data(8 downto 1) <= Data;
R_data(0) <= '0';
elsif ( CMD_data = SHIFT ) then
-- v = '1' + (v >> 1)
R_data(7 downto 0) <= R_data(8 downto 1);
R_data(8) <= '1';
else
R_data <= R_data;
end if ;
end if; end process;
VT_endbaud <= '1' WHEN R_Baud = 0 ELSE '0' ;
VT_endLoop <= '1' WHEN R_i = 0 ELSE '0' ;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: Ndata VT_endLoop VT_endBaud
-- Outputs: Tx Busy CMD_i CMD_baud CMD_data
-------------------------------------------------------------------------------
-- fonction de transitition
process (reset,clk)
begin
if reset = '1' then
state <= ST_BEGIN;
elsif clk'event and clk = '1' then
case state is
when ST_BEGIN =>
-- si go, alors on commence à serialiser
if Ndata = '1' then
state <= ST_FOR;
end if;
when ST_FOR =>
if VT_endLoop = '1' then
state <= ST_BEGIN;
else
state <= ST_ATT;
end if;
when ST_ATT =>
if VT_endbaud = '1' then
state <= ST_ADV;
end if;
when ST_ADV =>
state <= ST_FOR;
end case;
end if;
end process;
-- fonction de sortie
with state select tx <=
'1' when ST_BEGIN,
R_Data(0) when others
;
with state select busy <=
'0' when ST_BEGIN,
'1' when others
;
with state select CMD_i <=
INIT when ST_BEGIN,
COUNT when ST_ADV,
NOOP when others
;
with state select CMD_baud <=
COUNT when ST_ATT,
INIT when others
;
with state select CMD_data <=
INIT when ST_BEGIN,
SHIFT when ST_ADV,
NOOP when others
;
end montage;
| gpl-3.0 | b1a6b3f478524f636346f55985bf6287 | 0.479129 | 3.629341 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/bd/week1/ip/week1_Volume_Pregain_0_1/synth/week1_Volume_Pregain_0_1.vhd | 1 | 9,117 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: tsotnep:userLibrary:Volume_Pregain:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY week1_Volume_Pregain_0_1 IS
PORT (
OUT_VOLCTRL_L : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
OUT_VOLCTRL_R : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
OUT_RDY : OUT STD_LOGIC;
IN_SIG_L : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
IN_SIG_R : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END week1_Volume_Pregain_0_1;
ARCHITECTURE week1_Volume_Pregain_0_1_arch OF week1_Volume_Pregain_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF week1_Volume_Pregain_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT Volume_Pregain_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
INTBIT_WIDTH : INTEGER
);
PORT (
OUT_VOLCTRL_L : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
OUT_VOLCTRL_R : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
OUT_RDY : OUT STD_LOGIC;
IN_SIG_L : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
IN_SIG_R : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT Volume_Pregain_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF week1_Volume_Pregain_0_1_arch: ARCHITECTURE IS "Volume_Pregain_v1_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF week1_Volume_Pregain_0_1_arch : ARCHITECTURE IS "week1_Volume_Pregain_0_1,Volume_Pregain_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
BEGIN
U0 : Volume_Pregain_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
INTBIT_WIDTH => 24
)
PORT MAP (
OUT_VOLCTRL_L => OUT_VOLCTRL_L,
OUT_VOLCTRL_R => OUT_VOLCTRL_R,
OUT_RDY => OUT_RDY,
IN_SIG_L => IN_SIG_L,
IN_SIG_R => IN_SIG_R,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END week1_Volume_Pregain_0_1_arch;
| lgpl-3.0 | 7cd9eb6770877162fd70e23a19e43081 | 0.701876 | 3.21928 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/network_interface.vhd | 1 | 6,865 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity network_interface is
generic(
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
--clk, reset
clk : in std_logic;
rst : in std_logic;
--user sending interface
send_data : in std_logic_vector(data_width-1 downto 0);
dest_addr : in std_logic_vector(addr_width-1 downto 0);
set_tail_flit : in std_logic;
send_flit : in std_logic;
ready_to_send : out std_logic;
--user receiving interface
recv_data : out std_logic_vector(data_width-1 downto 0);
src_addr : out std_logic_vector(addr_width-1 downto 0);
is_tail_flit : out std_logic;
data_in_buffer : out std_logic_vector(num_vc-1 downto 0);
dequeue : in std_logic_vector(num_vc-1 downto 0);
select_vc_read : in std_logic_vector(vc_sel_width-1 downto 0);
--interface to network
send_putFlit_flit_in : out std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
EN_send_putFlit : out std_logic;
EN_send_getNonFullVCs : out std_logic;
send_getNonFullVCs : in std_logic_vector(num_vc-1 downto 0);
EN_recv_getFlit : out std_logic;
recv_getFlit : in std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
recv_putNonFullVCs_nonFullVCs : out std_logic_vector(num_vc-1 downto 0);
EN_recv_putNonFullVCs : out std_logic;
recv_info_getRecvPortID : in std_logic_vector(addr_width-1 downto 0)
);
end entity network_interface;
architecture structural of network_interface is
--fifo buffer for reciving
component fifo_buffer is
generic(
word_len : integer := 64;
buff_len : integer := 8
);
port(
write_data : in std_logic_vector(word_len-1 downto 0);
read_data : out std_logic_vector(word_len-1 downto 0);
buffer_full : out std_logic;
buffer_empty : out std_logic;
enqueue : in std_logic;
dequeue : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component fifo_buffer;
type fifo_io is array(num_vc-1 downto 0) of std_logic_vector(vc_sel_width+data_width+addr_width+1 downto 0);
signal write_vc, read_vc: fifo_io;
signal buffer_full_vc, buffer_empty_vc, enqueue_vc, dequeue_vc: std_logic_vector(num_vc-1 downto 0);
signal receive_vc: std_logic_vector(vc_sel_width-1 downto 0);
-- priority encoder
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
signal selected_vc : std_logic_vector(vc_sel_width-1 downto 0);
--constants to parse flits
constant data_msb : integer := data_width-1;
constant data_lsb : integer := 0;
constant vc_msb : integer := vc_sel_width+data_width-1;
constant vc_lsb : integer := data_width;
constant addr_msb : integer := vc_sel_width+data_width+addr_width-1;
constant addr_lsb : integer := vc_sel_width+data_width;
constant is_tail_index : integer := vc_sel_width+data_width+addr_width;
constant is_valid_index : integer := vc_sel_width+data_width+addr_width+1;
constant flit_size : integer := vc_sel_width+data_width+addr_width+2;
begin
---------------------------------------------------------------------------
--RECEIVE SIDE ------------------------------------------------------------
---------------------------------------------------------------------------
-- create and map 1 buffer for each VC
receive_buffer: for i in num_vc-1 downto 0 generate
signal vc_select : integer;
signal flit_valid : std_logic;
begin
ur_i: fifo_buffer generic map(data_width+addr_width+vc_sel_width+2, flit_buff_depth)
port map(write_vc(i), read_vc(i), buffer_full_vc(i), buffer_empty_vc(i),
enqueue_vc(i), dequeue_vc(i), clk, rst);
vc_select <= to_integer(unsigned(recv_getFlit(vc_msb downto vc_lsb)));
flit_valid <= recv_getFlit(is_valid_index);
write_vc(i) <= recv_getFlit when i = vc_select else std_logic_vector(to_unsigned(0,flit_size));
enqueue_vc(i) <= flit_valid when i = vc_select else '0';
end generate;
-- IO for receive side of controller
EN_recv_getFlit <= '1'; -- always read to receive flits as long as buffers aren't full
recv_putNonFullVCs_nonFullVCs <= not buffer_full_vc;
data_in_buffer <= not buffer_empty_vc;
recv_data <= read_vc(to_integer(unsigned(select_vc_read)))(data_msb downto data_lsb);
dequeue_vc <= dequeue;
is_tail_flit <= read_vc(to_integer(unsigned(select_vc_read)))(is_tail_index);
src_addr <= read_vc(to_integer(unsigned(select_vc_read)))(addr_msb downto addr_lsb);
EN_recv_putNonFullVCs <= '1'; -- readme is not clear about what this does, assuming it is not need for peek flow control
---------------------------------------------------------------------------
--SEND SIDE ---------------------------------------------------------------
---------------------------------------------------------------------------
-------- priority encoder to determine which vc to use
------us_0: priority_encoder generic map(vc_sel_width)
------ port map(send_getNonFullVCs, selected_vc);
------
------
-------- IO for sending side of controller
------send_putFlit_flit_in <= send_flit & set_tail_flit & dest_addr & selected_vc & send_data;
--------ready_to_send <= '0' when to_integer(unsigned(send_getNonFullVCs)) = 0 else '1';
------ready_to_send <= or_reduce(send_getNonFullVCs);
------EN_send_putFlit <= send_flit;
------EN_send_getNonFullVCs <= '1'; --always read to recieve credits
------
------
-- test version which only sends on VC0
-- priority encoder to determine which vc to use
selected_vc <= (others => '0');
-- IO for sending side of controller
send_putFlit_flit_in <= send_flit & set_tail_flit & dest_addr & selected_vc & send_data;
ready_to_send <= send_getNonFullVCs(0);
EN_send_putFlit <= send_flit;
EN_send_getNonFullVCs <= '1'; --always read to recieve credits
end architecture structural;
| mit | ac80e3d7098390f82c0585d6779ead35 | 0.563729 | 3.761644 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/noc_interface.vhd | 1 | 6,917 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity noc_interface is
generic(
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8;
use_vc : integer := 0
);
port(
--clk, reset
clk : in std_logic;
rst : in std_logic;
--user sending interface
send_data : in std_logic_vector(data_width-1 downto 0);
dest_addr : in std_logic_vector(addr_width-1 downto 0);
set_tail_flit : in std_logic;
send_flit : in std_logic;
ready_to_send : out std_logic;
--user receiving interface
recv_data : out std_logic_vector(data_width-1 downto 0);
src_addr : out std_logic_vector(addr_width-1 downto 0);
is_tail_flit : out std_logic;
data_in_buffer : out std_logic_vector(num_vc-1 downto 0);
dequeue : in std_logic_vector(num_vc-1 downto 0);
select_vc_read : in std_logic_vector(vc_sel_width-1 downto 0);
--interface to network
send_putFlit_flit_in : out std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
EN_send_putFlit : out std_logic;
EN_send_getNonFullVCs : out std_logic;
send_getNonFullVCs : in std_logic_vector(num_vc-1 downto 0);
EN_recv_getFlit : out std_logic;
recv_getFlit : in std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
recv_putNonFullVCs_nonFullVCs : out std_logic_vector(num_vc-1 downto 0);
EN_recv_putNonFullVCs : out std_logic;
recv_info_getRecvPortID : in std_logic_vector(addr_width-1 downto 0)
);
end entity noc_interface;
architecture structural of noc_interface is
--fifo buffer for reciving
component fifo_buffer is
generic(
word_len : integer := 64;
buff_len : integer := 8
);
port(
write_data : in std_logic_vector(word_len-1 downto 0);
read_data : out std_logic_vector(word_len-1 downto 0);
buffer_full : out std_logic;
buffer_empty : out std_logic;
enqueue : in std_logic;
dequeue : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component fifo_buffer;
type fifo_io is array(num_vc-1 downto 0) of std_logic_vector(vc_sel_width+data_width+addr_width+1 downto 0);
signal write_vc, read_vc: fifo_io;
signal buffer_full_vc, buffer_empty_vc, enqueue_vc, dequeue_vc: std_logic_vector(num_vc-1 downto 0);
signal receive_vc: std_logic_vector(vc_sel_width-1 downto 0);
-- priority encoder
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
signal selected_vc : std_logic_vector(vc_sel_width-1 downto 0);
--constants to parse flits
constant data_msb : integer := data_width-1;
constant data_lsb : integer := 0;
constant vc_msb : integer := vc_sel_width+data_width-1;
constant vc_lsb : integer := data_width;
constant addr_msb : integer := vc_sel_width+data_width+addr_width-1;
constant addr_lsb : integer := vc_sel_width+data_width;
constant is_tail_index : integer := vc_sel_width+data_width+addr_width;
constant is_valid_index : integer := vc_sel_width+data_width+addr_width+1;
constant flit_size : integer := vc_sel_width+data_width+addr_width+2;
begin
---------------------------------------------------------------------------
--RECEIVE SIDE ------------------------------------------------------------
---------------------------------------------------------------------------
-- create and map 1 buffer for each VC
receive_buffer: for i in num_vc-1 downto 0 generate
signal vc_select : integer;
signal flit_valid : std_logic;
begin
ur_i: fifo_buffer generic map(data_width+addr_width+vc_sel_width+2, flit_buff_depth)
port map(write_vc(i), read_vc(i), buffer_full_vc(i), buffer_empty_vc(i),
enqueue_vc(i), dequeue_vc(i), clk, rst);
vc_select <= to_integer(unsigned(recv_getFlit(vc_msb downto vc_lsb)));
flit_valid <= recv_getFlit(is_valid_index);
write_vc(i) <= recv_getFlit when i = vc_select else std_logic_vector(to_unsigned(0,flit_size));
enqueue_vc(i) <= flit_valid when i = vc_select else '0';
end generate;
-- IO for receive side of controller
EN_recv_getFlit <= '1'; -- always read to receive flits as long as buffers aren't full
recv_putNonFullVCs_nonFullVCs <= not buffer_full_vc;
data_in_buffer <= not buffer_empty_vc;
recv_data <= read_vc(to_integer(unsigned(select_vc_read)))(data_msb downto data_lsb);
dequeue_vc <= dequeue;
is_tail_flit <= read_vc(to_integer(unsigned(select_vc_read)))(is_tail_index);
src_addr <= read_vc(to_integer(unsigned(select_vc_read)))(addr_msb downto addr_lsb);
EN_recv_putNonFullVCs <= '1'; -- readme is not clear about what this does, assuming it is not need for peek flow control
---------------------------------------------------------------------------
--SEND SIDE ---------------------------------------------------------------
---------------------------------------------------------------------------
-------- priority encoder to determine which vc to use
------us_0: priority_encoder generic map(vc_sel_width)
------ port map(send_getNonFullVCs, selected_vc);
------
------
-------- IO for sending side of controller
------send_putFlit_flit_in <= send_flit & set_tail_flit & dest_addr & selected_vc & send_data;
--------ready_to_send <= '0' when to_integer(unsigned(send_getNonFullVCs)) = 0 else '1';
------ready_to_send <= or_reduce(send_getNonFullVCs);
------EN_send_putFlit <= send_flit;
------EN_send_getNonFullVCs <= '1'; --always read to recieve credits
------
------
-- test version which only sends on VC0
-- priority encoder to determine which vc to use
selected_vc <= std_logic_vector(to_unsigned(use_vc, vc_sel_width));
-- IO for sending side of controller
send_putFlit_flit_in <= send_flit & set_tail_flit & dest_addr & selected_vc & send_data;
ready_to_send <= send_getNonFullVCs(use_vc);
EN_send_putFlit <= send_flit;
EN_send_getNonFullVCs <= '1'; --always read to recieve credits
end architecture structural;
| mit | 12ffd84f0da662c2c48f05e0c9ad6219 | 0.56484 | 3.736899 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/inverse_quant.vhd | 2 | 4,064 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity inverse_quant is
generic(
in_sample_width : integer := 8;
out_sample_width : integer := 16;
qp_width : integer := 8;
wo_dc_width : integer := 8
);
port(
quantized_samples : in std_logic_vector((16*in_sample_width)-1 downto 0);
quant_param : in std_logic_vector(qp_width-1 downto 0);
without_dc : in std_logic_vector(wo_dc_width-1 downto 0);
dequant_samples : out std_logic_vector((16*out_sample_width)-1 downto 0)
);
end entity inverse_quant;
architecture initial of inverse_quant is
--- TYPES -----------------------------------------------------------------
type block_type is array(15 downto 0) of integer;
--- CONSTANTS -------------------------------------------------------------
constant factor_table_entry_0 : block_type := (10,13,10,13,13,16,13,16,10,13,10,13,13,16,13,16);
constant factor_table_entry_1 : block_type := (11,14,11,14,14,18,14,18,11,14,11,14,14,18,14,18);
constant factor_table_entry_2 : block_type := (13,16,13,16,16,20,16,20,13,16,13,16,16,20,16,20);
constant factor_table_entry_3 : block_type := (14,18,14,18,18,23,18,23,14,18,14,18,18,23,18,23);
constant factor_table_entry_4 : block_type := (16,20,16,20,20,25,20,25,16,20,16,20,20,25,20,25);
constant factor_table_entry_5 : block_type := (18,23,18,23,23,29,23,29,18,23,18,23,23,29,23,29);
--- SIGNALS ---------------------------------------------------------------
signal quantization_bits : integer;
signal quantized_block : block_type;
signal dequantized_block : block_type;
signal block_item_signs : block_type;
signal the_factors : block_type;
signal factor_selector : integer;
signal quant_shift : signed(31 downto 0);
begin
-- determine correct factor table entry to use
factor_selector <= to_integer(unsigned( quant_param )) mod 6;
the_factors <= factor_table_entry_0 when factor_selector = 0 else
factor_table_entry_1 when factor_selector = 1 else
factor_table_entry_2 when factor_selector = 2 else
factor_table_entry_3 when factor_selector = 3 else
factor_table_entry_4 when factor_selector = 4 else
factor_table_entry_5;
-- parse the input into integers
-- and find the signs
signs: for i in 15 downto 0 generate
constant lower_index : integer := i * in_sample_width;
constant upper_index : integer := lower_index + in_sample_width - 1;
begin
quantized_block(i) <= to_integer(signed( quantized_samples(upper_index downto lower_index) ));
block_item_signs(i) <= -1 when quantized_block(i) < 0 else 1;
end generate;
--perform the algorithm on samples 15..1
quantization_bits <= to_integer(signed(quant_param))/6;
quant_shift <= shift_left(to_signed(1,32), quantization_bits);
alg: for i in 15 downto 1 generate
begin
dequantized_block(i) <= block_item_signs(i) *
(abs(quantized_block(i)) * the_factors(15-i) * to_integer(quant_shift)
);
end generate;
--perform the algorithm on the special case of 0
dequantized_block(0) <= quantized_block(0) when or_reduce(without_dc) = '1' else
block_item_signs(0) *
(abs(quantized_block(0)) *
the_factors(15) *
to_integer(quant_shift)
);
--format the output
output: for i in 15 downto 0 generate
constant lower_index : integer := i * out_sample_width;
constant upper_index : integer := lower_index + out_sample_width - 1;
begin
dequant_samples(upper_index downto lower_index) <= std_logic_vector(to_signed(dequantized_block(i), out_sample_width));
end generate;
end architecture initial; | mit | 791ca4be4828a6789b477ee6b113a2e9 | 0.583661 | 3.564912 | false | false | false | false |
boztalay/OldProjects | FPGA/LCD_Control/TestCPU1_RegFile_TB.vhd | 1 | 4,262 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:08:51 10/04/2009
-- Design Name:
-- Module Name: C:/Users/Ben/Desktop/Folders/FPGA/Projects/Current Projects/Systems/TestCPU1/TestCPU1_RegFile_TB.vhd
-- Project Name: TestCPU1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: TestCPU1_RegFile
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY TestCPU1_RegFile_TB IS
END TestCPU1_RegFile_TB;
ARCHITECTURE behavior OF TestCPU1_RegFile_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TestCPU1_RegFile
PORT(
clock : IN std_logic;
reset : IN std_logic;
ld_val : IN std_logic;
ALUB_out : IN std_logic;
src1_addr : IN std_logic_vector(2 downto 0);
src2_addr : IN std_logic_vector(2 downto 0);
dest_addr : IN std_logic_vector(2 downto 0);
data_to_load : IN std_logic_vector(15 downto 0);
to_ALUA_out : OUT std_logic_vector(15 downto 0);
to_ALUB_out : OUT std_logic_vector(15 downto 0);
data_collection_1 : out STD_LOGIC_VECTOR(15 downto 0); --for simulation purposes only
data_collection_2 : out STD_LOGIC_VECTOR(15 downto 0); --
data_collection_3 : out STD_LOGIC_VECTOR(15 downto 0)); --
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal ld_val : std_logic := '0';
signal ALUB_out : std_logic := '0';
signal src1_addr : std_logic_vector(2 downto 0) := (others => '0');
signal src2_addr : std_logic_vector(2 downto 0) := (others => '0');
signal dest_addr : std_logic_vector(2 downto 0) := (others => '0');
signal data_to_load : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal to_ALUA_out : std_logic_vector(15 downto 0);
signal to_ALUB_out : std_logic_vector(15 downto 0);
signal data_collection_1 : STD_LOGIC_VECTOR(15 downto 0); --for simulation purposes only
signal data_collection_2 : STD_LOGIC_VECTOR(15 downto 0); --
signal data_collection_3 : STD_LOGIC_VECTOR(15 downto 0); --
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TestCPU1_RegFile PORT MAP (
clock => clock,
reset => reset,
ld_val => ld_val,
ALUB_out => ALUB_out,
src1_addr => src1_addr,
src2_addr => src2_addr,
dest_addr => dest_addr,
data_to_load => data_to_load,
to_ALUA_out => to_ALUA_out,
to_ALUB_out => to_ALUB_out,
data_collection_1 => data_collection_1,
data_collection_2 => data_collection_2,
data_collection_3 => data_collection_3
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 15 ns;
ld_val <= '1';
dest_addr <= b"001";
data_to_load <= x"0001";
wait for 10 ns;
dest_addr <= b"010";
data_to_load <= x"0002";
wait for 10 ns;
dest_addr <= b"011";
data_to_load <= x"0003";
wait for 10 ns;
ld_val <= '0';
ALUB_out <= '1';
src1_addr <= b"001";
wait for 10 ns;
src1_addr <= b"010";
src2_addr <= b"011";
wait for 10 ns;
ALUB_out <= '0';
wait for 10 ns;
reset <= '1';
wait;
end process;
END;
| mit | 147564d52f3946a076ae5c7899fdc9d4 | 0.579305 | 3.417803 | false | true | false | false |
boztalay/OldProjects | FPGA/Systems/Sys_DigitalTimer2/Sys_DigitalTimer2.vhd | 1 | 6,866 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 23:31:37 04/11/2009
-- Design Name:
-- Module Name: Sys_DigitalTimer2 - Behavioral
-- Project Name: Digital Timer
-- Target Devices:
-- Tool versions:
-- Description: A digital miute timer. Starts at 00:00, goes to 99:59. Resetable.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
---------Begin-----------
--Frequency Divder Code--
---------Begin-----------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FrequencyDivider is
Port ( SysCLK : in STD_LOGIC;
Reset : in STD_LOGIC;
CLK1Hz : out STD_LOGIC;
CLK400Hz : out STD_LOGIC);
end FrequencyDivider;
architecture Behavioral of FrequencyDivider is
begin
main : process(SysCLK)
variable cnt1, cnt2 : integer := 0;
begin
if (SysCLK'event and SysCLK = '1') then
if (Reset = '1') then
cnt1 := 0;
else
cnt1 := cnt1 + 1;
end if;
cnt2 := cnt2 + 1;
if (cnt1 = 25000000) then
CLK1Hz <= '1';
end if;
if (cnt2 = 62500) then
CLK400Hz <= '1';
end if;
if (cnt1 = 50000000) then
CLK1Hz <= '0';
cnt1 := 0;
end if;
if (cnt2 = 125000) then
CLK400Hz <= '0';
cnt2 := 0;
end if;
end if;
end process;
end architecture Behavioral;
----------End------------
--Frequency Divder Code--
----------End------------
----------------------------------------------------------------------------------
--------Begin---------
--Digital Timer Code--
--------Begin---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity Sys_DigitalTimer2 is
Port ( SysCLK : in STD_LOGIC;
Reset : in STD_LOGIC;
segs : out STD_LOGIC_VECTOR (6 downto 0);
anodes : out STD_LOGIC_VECTOR (3 downto 0));
end Sys_DigitalTimer2;
--Architecture--
architecture Behavioral of Sys_DigitalTimer2 is
--\Components/--
component FrequencyDivider is
Port ( SysCLK : in STD_LOGIC;
Reset : in STD_LOGIC;
CLK1Hz : out STD_LOGIC;
CLK400Hz : out STD_LOGIC);
end component;
--/Components\--
--\Signals/--
signal Buf_CLK : STD_LOGIC;
signal CLK1 : STD_LOGIC;
signal CLK400 : STD_LOGIC;
signal Buf_CLK1 : STD_LOGIC;
signal Buf_CLK400 : STD_LOGIC;
signal dig1s : STD_LOGIC_VECTOR (3 downto 0);
signal dig2s : STD_LOGIC_VECTOR (3 downto 0);
signal dig3s : STD_LOGIC_VECTOR (3 downto 0);
signal dig4s : STD_LOGIC_VECTOR (3 downto 0);
--/Signals\--
--Architecture Begin--
begin
--\BUFG Instantiations-/--
BUFG_BufCLK : BUFG
port map (
O => Buf_CLK,
I => SysCLK
);
BUFG_CLK1 : BUFG
port map (
O => Buf_CLK1,
I => CLK1
);
BUFG_CLK400 : BUFG
port map (
O => Buf_CLK400,
I => CLK400
);
--/BUFG Instantiations\--
G1: FrequencyDivider port map (Buf_CLK, Reset, CLK1, CLK400);
main : process(Reset, Buf_CLK1)
variable dig1, dig2, dig3, dig4 : STD_LOGIC_VECTOR (3 downto 0);
variable cnt, count : integer := 1;
begin
--First Digit Incriment
if (Buf_CLK1'event and Buf_CLK1 = '1') then
dig1 := dig1 + 1;
if (dig1 > 9) then
dig1 := "0000";
dig2 := dig2 + 1;
if (dig2 > 5) then
dig2 := "0000";
dig3 := dig3 + 1;
if (dig3 > 9) then
dig3 := "0000";
dig4 := dig4 + 1;
if (dig4 > 9) then
dig4 := "0000";
end if;
end if;
end if;
end if;
end if;
if (Reset = '1') then
dig1 := "0000";
dig2 := "0000";
dig3 := "0000";
dig4 := "0000";
end if;
dig1s <= dig1;
dig2s <= dig2;
dig3s <= dig3;
dig4s <= dig4;
end process;
--Displays the digits
display : process(Buf_CLK400)
variable cnt, count : integer := 1;
begin
if (Buf_CLK400'event and Buf_CLK400 = '1') then
--If cnt is 1, then display the first digit
if (cnt = 1) then
count := cnt + 1;
case (dig1s) is
when "0000" =>
segs <= "1000000";
when "0001" =>
segs <= "1111001";
when "0010" =>
segs <= "0100100";
when "0011" =>
segs <= "0110000";
when "0100" =>
segs <= "0011001";
when "0101" =>
segs <= "0010010";
when "0110" =>
segs <= "0000010";
when "0111" =>
segs <= "1111000";
when "1000" =>
segs <= "0000000";
when "1001" =>
segs <= "0010000";
when others =>
segs <= "1000000";
end case;
anodes <= "1110";
end if;
--If cnt is 2, then display the second digit
if (cnt = 2) then
count := cnt + 1;
case (dig2s) is
when "0000" =>
segs <= "1000000";
when "0001" =>
segs <= "1111001";
when "0010" =>
segs <= "0100100";
when "0011" =>
segs <= "0110000";
when "0100" =>
segs <= "0011001";
when "0101" =>
segs <= "0010010";
when "0110" =>
segs <= "0000010";
when "0111" =>
segs <= "1111000";
when "1000" =>
segs <= "0000000";
when "1001" =>
segs <= "0010000";
when others =>
segs <= "1000000";
end case;
anodes <= "1101";
end if;
--If cnt is 3, then display the third digit
if (cnt = 3) then
count := cnt + 1;
case (dig3s) is
when "0000" =>
segs <= "1000000";
when "0001" =>
segs <= "1111001";
when "0010" =>
segs <= "0100100";
when "0011" =>
segs <= "0110000";
when "0100" =>
segs <= "0011001";
when "0101" =>
segs <= "0010010";
when "0110" =>
segs <= "0000010";
when "0111" =>
segs <= "1111000";
when "1000" =>
segs <= "0000000";
when "1001" =>
segs <= "0010000";
when others =>
segs <= "1000000";
end case;
anodes <= "1011";
end if;
--If cnt is 4, then display the fourth digit
if (cnt = 4) then
count := 1;
case (dig4s) is
when "0000" =>
segs <= "1000000";
when "0001" =>
segs <= "1111001";
when "0010" =>
segs <= "0100100";
when "0011" =>
segs <= "0110000";
when "0100" =>
segs <= "0011001";
when "0101" =>
segs <= "0010010";
when "0110" =>
segs <= "0000010";
when "0111" =>
segs <= "1111000";
when "1000" =>
segs <= "0000000";
when "1001" =>
segs <= "0010000";
when others =>
segs <= "1000000";
end case;
anodes <= "0111";
end if;
cnt := count;
end if;
end process;
end Behavioral;
---------End----------
--Digital Timer Code--
---------End----------
| mit | 11527a142b8ea4b00c4caeab452dc62c | 0.519808 | 3.123749 | false | false | false | false |
DaveyPocket/btrace448 | core/counter.vhd | 1 | 850 | -- Btrace 448
-- Up/down counter
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
generic(n: integer := 5);
port(clk, reset: in std_logic;
ld, up, down: in std_logic;
d: in std_logic_vector(n-1 downto 0);
q: out std_logic_vector(n-1 downto 0) := (others => '0'));
end counter;
architecture arch of counter is
signal q_next: std_logic_vector(n-1 downto 0);
begin
process(clk, reset)
begin
if (reset = '1') then
q_next <= (others => '0');
elsif rising_edge(clk) then
if (ld = '1') then
q_next <= d;
elsif (up = '1') then
q_next <= std_logic_vector(unsigned(q_next) + 1);
elsif (down = '1') then
q_next <= std_logic_vector(unsigned(q_next) - 1);
end if;
end if;
end process;
q <= q_next;
end arch;
| gpl-3.0 | 6b902937b91f0250912198adf16426ca | 0.596471 | 2.664577 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/tsotnep/volume_pregain_v1_0/75ddc6aa/src/Volume_Pregain_Top_Module.vhd | 2 | 3,061 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Volume_Pregain_Top_Module is
generic(
INTBIT_WIDTH : integer;
FRACBIT_WIDTH : integer
);
port(
OUT_VOLCTRL_L : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); -- 24 bit signed output
OUT_VOLCTRL_R : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); -- 24 bit signed output
OUT_RDY : out STD_LOGIC;
IN_SIG_L : in signed((INTBIT_WIDTH - 1) downto 0); --amplifier input signal 24-bit
IN_SIG_R : in signed((INTBIT_WIDTH - 1) downto 0); --amplifier input signal 24-bit
IN_COEF_L : in signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); -- 32 bit COEF from a register. Last 8 bits are fractional for volume control 0<-->1
IN_COEF_R : in signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); -- 32 bit COEF from a register. Last 8 bits are fractional for volume control 0<-->1
CLK_100mhz : in STD_LOGIC;
RESET : in STD_LOGIC
);
end Volume_Pregain_Top_Module;
architecture Behavioral of Volume_Pregain_Top_Module is
component AmplifierFP
generic ( INTBIT_WIDTH : integer;
FRACBIT_WIDTH : integer);
port(
CLK : in std_logic;
RESET : in std_logic;
IN_SIG : in signed((INTBIT_WIDTH - 1) downto 0); --amplifier input signal 24-bit
IN_COEF : in signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); -- 32 bit COEF from a register. Last 8 bits are fractional for volume control 0<-->1
OUT_AMP : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); --amplifier output
OUT_RDY : out std_logic
);
end component;
signal AMP_OUT_L, AMP_OUT_R : signed((INTBIT_WIDTH - 1) downto 0) := (others => '0');
signal VOLCTRL_L, VOLCTRL_R : signed((INTBIT_WIDTH - 1) downto 0) := (others => '0');
signal volctrl_ready_l : std_logic := '0';
signal volctrl_ready_r : std_logic := '0';
begin
AmplifierFP_L : AmplifierFP
generic map(
INTBIT_WIDTH => INTBIT_WIDTH,
FRACBIT_WIDTH => FRACBIT_WIDTH
)port map(
CLK => CLK_100mhz,
RESET => RESET,
IN_SIG => IN_SIG_L,
IN_COEF => IN_COEF_L,
OUT_AMP => AMP_OUT_L,
OUT_RDY => volctrl_ready_l
);
AmplifierFP_R : AmplifierFP
generic map(
INTBIT_WIDTH => INTBIT_WIDTH,
FRACBIT_WIDTH => FRACBIT_WIDTH
)port map(
CLK => CLK_100mhz,
RESET => RESET,
IN_SIG => IN_SIG_R,
IN_COEF => IN_COEF_R,
OUT_AMP => AMP_OUT_R,
OUT_RDY => volctrl_ready_r
);
seq_proc : process(CLK_100mhz)
begin
if (CLK_100mhz'event and CLK_100mhz = '1') then
-- update the ready signal when new values gets written to the buffer
if (volctrl_ready_l = '1') then
VOLCTRL_L <= AMP_OUT_L;
end if;
if (volctrl_ready_r = '1') then
VOLCTRL_R <= AMP_OUT_R;
end if;
end if;
end process;
OUT_RDY <= volctrl_ready_l or volctrl_ready_r;
OUT_VOLCTRL_L <= VOLCTRL_L;
OUT_VOLCTRL_R <= VOLCTRL_R;
end Behavioral; | lgpl-3.0 | 6162068ee7486c87b84d64c22cbfa048 | 0.604051 | 3.104462 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia/checker.vhd | 1 | 4,722 | -------------------------------------------------------------------------------
--
-- Ce bloc envoie des messages tous les 1000 ticks au PC
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY checker IS
GENERIC(
MYADDR : STD_LOGIC_VECTOR(7 downto 0) := "00001010" -- 10
);
PORT(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- interface busin
busin : in STD_LOGIC_VECTOR(43 downto 0);
busin_valid : in STD_LOGIC;
busin_eated : out STD_LOGIC;
-- interface busout
busout : out STD_LOGIC_VECTOR(43 downto 0);
busout_valid : out STD_LOGIC;
busout_eated : in STD_LOGIC;
);
END checker;
ARCHITECTURE montage OF checker IS
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
-- Registre de transfert entre busin et busout
type T_CMD_tft is (INIT, NOOP);
signal CMD_tft : T_CMD_tft ;
signal R_tft : STD_LOGIC_VECTOR (43 downto 0);
-- Commande pour 'busmsg'
-- LOAD => chargement du message
-- NOOP => charge un message vide (NOOP)
TYPE T_CMD_Msg IS (LOAD, NOOP);
signal CMD_Msg : T_CMD_Msg ;
-- registre stockant les 32 valeurs du 7 segments configurées (7 * 32 = 224)
signal R_SS : STD_LOGIC_VECTOR(229 downto 0);
-- registre stockant V (nombre de master clock à attendre avant de générer un tick)
signal R_N_CLOCK : STD_LOGIC_VECTOR(21 downto 0);
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- adresse destination
alias busin_addrdest : STD_LOGIC_VECTOR(7 downto 0) is busin(31 downto 24);
type STATE_TYPE is (
ST_READ_BUSIN, ST_WRITE_OUT, ST_LOAD_MSG
);
signal state : STATE_TYPE;
BEGIN
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
PROCESS (reset, clk)
BEGIN
-- si on reset
IF reset = '1' THEN
-- 5 000 000 <=> 100 ticks par secondes
-- 5 000 000 / 2 = 2 500 000 = 0b1001100010010110100000
R_N_CLOCK <= "1001100010010110100000";
-- configure le serpentin pour qu'il soit vide
R_SS <= (5 => '1', others => '0');
ELSIF clk'event AND clk = '1' THEN
-- commandes de transfert bus ia
-- si l'on doit lire le message, on le stocke
-- dans le registre 'R_tft'
IF CMD_tft = INIT THEN
R_tft <= busin ;
END IF;
-- si le message doit être chargé
-- on met à jour le registre de stockage
IF CMD_Msg = LOAD THEN
-- switch l'id du message
CASE R_tft(23 downto 22) IS
-- hinit(n_clock)
WHEN "00" =>
R_N_CLOCK <= R_tft(21 downto 0);
-- clr(s)
WHEN "01" =>
R_SS <= (5 => '1', others => '0');
-- si commande set-N(n)
WHEN "10" =>
R_SS(5 downto 0) <= R_tft(5 downto 0);
-- si commande set-val(i, v)
WHEN "11" =>
-- TODO
-- R_SS((i + 1) * 7 - 1, i * 7) <= R_Msg(6 downto 0);
END CASE;
END IF ;
END IF;
END PROCESS;
-- sortie
busNClock <= R_N_CLOCK;
busSS <= R_SS;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: busin_valid, busout_eated, busin_addrdest
-- Outputs: busin_eated, busout_valid, CMD_tft
-------------------------------------------------------------------------------
-- fonction de transitition
PROCESS (reset,clk)
BEGIN
IF reset = '1' THEN
state <= ST_READ_BUSIN;
ELSIF clk'event AND clk = '1' THEN
CASE state IS
WHEN ST_READ_BUSIN =>
IF busin_valid='1' THEN
IF busin_addrdest = MYADDR THEN
state <= ST_LOAD_MSG ;
ELSE
state <= ST_WRITE_OUT ;
END IF ;
END IF ;
WHEN ST_WRITE_OUT =>
IF busout_eated = '1' THEN
state <= ST_READ_BUSIN;
END IF ;
WHEN ST_LOAD_MSG =>
state <= ST_READ_BUSIN;
END CASE;
END IF;
END PROCESS;
-- fonction de sortie
WITH state SELECT busin_eated <=
'1' WHEN ST_READ_BUSIN,
'0' WHEN others
;
WITH state SELECT busout_valid <=
'1' WHEN ST_WRITE_OUT,
'0' WHEN others
;
WITH state SELECT CMD_tft <=
INIT WHEN ST_READ_BUSIN,
NOOP WHEN others
;
WITH state SELECT CMD_Msg <=
LOAD WHEN ST_LOAD_MSG,
NOOP WHEN others
;
end montage;
| gpl-3.0 | 00e4ecabcc799e4b2e56db32e352c530 | 0.480365 | 3.607198 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/bd/week1/ip/week1_audio_to_AXI_0_1/synth/week1_audio_to_AXI_0_1.vhd | 1 | 9,029 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:audio_to_AXI:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY week1_audio_to_AXI_0_1 IS
PORT (
audio_in_l : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_in_r : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_in_valid : IN STD_LOGIC;
audio_out_valid_irq : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END week1_audio_to_AXI_0_1;
ARCHITECTURE week1_audio_to_AXI_0_1_arch OF week1_audio_to_AXI_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF week1_audio_to_AXI_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT audio_to_AXI_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER -- Width of S_AXI address bus
);
PORT (
audio_in_l : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_in_r : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_in_valid : IN STD_LOGIC;
audio_out_valid_irq : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT audio_to_AXI_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF week1_audio_to_AXI_0_1_arch: ARCHITECTURE IS "audio_to_AXI_v1_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF week1_audio_to_AXI_0_1_arch : ARCHITECTURE IS "week1_audio_to_AXI_0_1,audio_to_AXI_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF audio_out_valid_irq: SIGNAL IS "xilinx.com:signal:interrupt:1.0 audio_out_valid_irq INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
BEGIN
U0 : audio_to_AXI_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4
)
PORT MAP (
audio_in_l => audio_in_l,
audio_in_r => audio_in_r,
audio_in_valid => audio_in_valid,
audio_out_valid_irq => audio_out_valid_irq,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END week1_audio_to_AXI_0_1_arch;
| lgpl-3.0 | 3ef75304b0051cf538f9d460c3d15081 | 0.703068 | 3.178106 | false | false | false | false |
pyrohaz/SSD1306_VHDLImplementation | SSD1306.vhd | 1 | 1,971 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SSD1306 is
port(
PDO: out std_logic_vector(7 downto 0);
MADDR: out std_logic_vector(9 downto 0);
MemDI: in std_logic_vector(7 downto 0);
Clk, Rst, Bsy: in std_logic;
Trig, CD: out std_logic
);
end SSD1306;
architecture Ar of SSD1306 is
constant AMNT_INSTRS: natural := 27;
type IAR is array (0 to AMNT_INSTRS-1) of std_logic_vector(7 downto 0);
signal Instrs: IAR := (x"A8", x"3F", x"D3", x"00", x"40", x"A1", x"DA", x"12", x"81", x"7F", x"20", x"00", x"21", x"00", x"7F", x"22", x"00", x"07", x"A6", x"DB", x"40", x"A4", x"D5", x"80", x"8D", x"14", x"AF");
type PStates is (Init, Draw);
type SStates is (BusyWaitA, BusyWaitB, Writing, Done);
signal SPISt: SStates := Done;
signal PSt: PStates := Init;
signal PInstr: unsigned(7 downto 0);
signal MemAddr: unsigned(9 downto 0);
begin
process(Clk, Rst, Bsy)
begin
MADDR <= std_logic_vector(MemAddr);
if(Rst = '0') then
PSt <= Init;
SPISt <= Done;
PInstr <= (others => '0');
elsif(rising_edge(Clk)) then
if(PSt = Init) then
CD <= '0';
if(SPISt = Done) then
PDO <= (Instrs(to_integer(PInstr)));
Trig <= '1';
SPISt <= BusyWaitA;
elsif(SPISt = BusyWaitA) then
if(Bsy = '1') then
PInstr <= PInstr + 1;
SPISt <= Writing;
Trig <= '0';
end if;
else
if(Bsy = '0') then
SPISt <= Done;
if(PInstr = AMNT_INSTRS) then
PSt <= Draw;
PInstr <= (others => '0');
MemAddr(0) <= '1';
end if;
end if;
end if;
else --Draw
CD <= '1';
if(SPISt = Done) then
PDO <= MemDI;
Trig <= '1';
SPISt <= BusyWaitA;
elsif(SPISt = BusyWaitA) then
if(Bsy = '1') then
MemAddr <= MemAddr + 1;
PInstr <= PInstr + 1;
SPISt <= Writing;
Trig <= '0';
end if;
else
if(Bsy = '0') then SPISt <= Done; end if;
end if;
end if;
end if;
end process;
end Ar;
| mit | e9936e3d47e08efd1b46e95c538563f7 | 0.560629 | 2.621011 | false | false | false | false |
boztalay/OldProjects | FPGA/LCD_Control/TestCPU1_Cntl.vhd | 1 | 4,652 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 23:42:02 10/08/2009
-- Design Name:
-- Module Name: TestCPU1_Cntl - Behavioral
-- Project Name: Test CPU 1
-- Target Devices:
-- Tool versions:
-- Description: The instruction decoder and control block for Test CPU 1
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestCPU1_Cntl is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
main_bus : in STD_LOGIC_VECTOR(15 downto 0);
ALUB_out : out STD_LOGIC_VECTOR(15 downto 0);
ALU_op : out STD_LOGIC := '0';
ALU_to_bus_e : out STD_LOGIC;
opins_act : out STD_LOGIC;
RFile_ld_val : out STD_LOGIC;
RFile_ALUB_out : out STD_LOGIC;
RFile_src1_addr : out STD_LOGIC_VECTOR(2 downto 0);
RFile_src2_addr : out STD_LOGIC_VECTOR(2 downto 0);
RFile_dest_addr : out STD_LOGIC_VECTOR(2 downto 0);
instruction : in STD_LOGIC_VECTOR(15 downto 0);
program_count : out STD_LOGIC_VECTOR(10 downto 0));
end TestCPU1_Cntl;
architecture Behavioral of TestCPU1_Cntl is
signal PC_take_alt_addr : STD_LOGIC;
signal PC_alt_addr : STD_LOGIC_VECTOR(10 downto 0);
signal zero : STD_LOGIC;
begin
Cntl: process (clock, reset, instruction, zero) is
begin
ALUB_out <= x"0000";
ALU_op <= '0';
ALU_to_bus_e <= '0';
opins_act <= '0';
PC_take_alt_addr <= '0';
PC_alt_addr <= b"00000000000";
RFile_ld_val <= '0';
RFile_ALUB_out <= '0';
RFile_src1_addr <= b"000";
RFile_src2_addr <= b"000";
RFile_dest_addr <= b"000";
case instruction(15 downto 11) is --I know it's shameful to implement the decoder like this, but I tried the
when "00000" => --more efficient way, then added on, etc, and it got too complex, so I started
ALU_to_bus_e <= '1'; --over. I'll probably re-do this sometime soon.
RFile_ld_val <= '1';
RFile_ALUB_out <= '1';
RFile_dest_addr <= instruction(10 downto 8);
RFile_src1_addr <= instruction(7 downto 5);
RFile_src2_addr <= instruction(4 downto 2);
when "00001" =>
ALU_op <= '1';
ALU_to_bus_e <= '1';
RFile_ld_val <= '1';
RFile_ALUB_out <= '1';
RFile_dest_addr <= instruction(10 downto 8);
RFile_src1_addr <= instruction(7 downto 5);
RFile_src2_addr <= instruction(4 downto 2);
when "00010" =>
ALU_to_bus_e <= '1';
RFile_ld_val <= '1';
RFile_dest_addr <= instruction(10 downto 8);
RFile_src1_addr <= instruction(7 downto 5);
ALUB_out <= b"00000000000" & instruction(4 downto 0);
when "00011" =>
ALU_op <= '1';
ALU_to_bus_e <= '1';
RFile_ld_val <= '1';
RFile_dest_addr <= instruction(10 downto 8);
RFile_src1_addr <= instruction(7 downto 5);
ALUB_out <= b"00000000000" & instruction(4 downto 0);
when "00100" =>
ALU_op <= '1';
ALU_to_bus_e <= '1';
RFile_ALUB_out <= '1';
RFile_dest_addr <= instruction(10 downto 8);
RFile_src1_addr <= instruction(7 downto 5);
RFile_src2_addr <= instruction(4 downto 2);
when "01000" =>
if zero = '1' then
PC_take_alt_addr <= '1';
PC_alt_addr <= b"000" & instruction(7 downto 0);
end if;
when "01001" =>
PC_take_alt_addr <= '1';
PC_alt_addr <= instruction(10 downto 0);
when "10000" =>
ALU_to_bus_e <= '1';
RFile_src1_addr <= b"000";
opins_act <= '1';
ALUB_out <= b"00000" & instruction(10 downto 0);
when others =>
null; --do nothing
end case;
end process;
PC: process (clock, reset) is
variable PC_reg : STD_LOGIC_VECTOR(10 downto 0) := b"00000000000";
begin
if rising_edge(clock) then
if reset = '1' then
PC_reg := b"00000000000";
elsif PC_take_alt_addr = '1' then
PC_reg := PC_alt_addr;
else
PC_reg := PC_reg + 1;
end if;
end if;
program_count <= PC_reg(10 downto 0);
end process;
zflag: process(clock, reset) is
variable z_reg : STD_LOGIC;
begin
if rising_edge(clock) then
if main_bus = x"0000" then
z_reg := '1';
else
z_reg := '0';
end if;
end if;
zero <= z_reg;
end process;
end Behavioral;
| mit | 8d0a92d2de33966a7bad0327c82355fc | 0.573517 | 3.064559 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/tsotnep/filter_iir_v1_0/263d46e2/src/IIR_Biquad_II_v3.vhd | 2 | 10,609 | --/////////////////////////////////////////////////IIR_Biquad////////////////////////////////////////////////////////////
-- FileName: IIR_Biquad_II_v3.vhd
-- This is a direct Form1, 2nd Order IIR Filter. This code was created from the original version which you can find at:
-- https://eewiki.net/display/LOGIC/IIR+Filter+Design+in+VHDL+Targeted+for+18-Bit,+48+KHz+Audio+Signal+Use#IIRFilterDesigninVHDLTargetedfor18-Bit,48KHzAudioSignalUse-InstantiatingtheIIR_Biquad.vhdFilterModule
-- Credit must be given to Tony Storey of DIGI-KEY for providing the original code upon which this version has been created from.
--
-- Original Version History
-- Version 1.0 7/31/2012 Tony Storey
-- Initial Public Releaselibrary ieee;
--
-- Current Version History
-- Version 3.0 27/05/2015 Ovie, Tsotne, Juri, and Silvester.
--
-- A lot of changes and updates have been made to this version. This version uses a single "shift add" multiplier instead of five DSP multipliers.
-- This version has a reduced area size due to the scheduling and sharing of resource, but with a trade off of time.
--
--
-- IIR_Biquad_II_v3.vhd IS PROVIDED "AS IS." WE EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL WE
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
-- WE ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
-- INFRINGEMENT.
--
--/////////////////////////////////Recommendations on how to use this component.///////////////////////////////////////////
-- The current configuration has coefficient width of 32 bits and sample data width of 32 bits (24 bits but padded with zeros)
-- , it takes approximately 350 clock circles to perform a
-- single filter operation. With this configuration the approximate minimum frequency of operation of the filter should be
-- 16.8Mhz
--/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity IIR_Biquad_II_v3 is
port(
Coef_b0 : std_logic_vector(31 downto 0);
Coef_b1 : std_logic_vector(31 downto 0);
Coef_b2 : std_logic_vector(31 downto 0);
Coef_a1 : std_logic_vector(31 downto 0);
Coef_a2 : std_logic_vector(31 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR(23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR(23 downto 0)
);
end IIR_Biquad_II_v3;
architecture arch of IIR_Biquad_II_v3 is
signal ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define each post gain 64 bit sample
signal pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad : signed(63 downto 0) := (others => '0');
signal mul_result : signed(63 downto 0) := (others => '0');
-- define each post gain 32 but truncated sample
signal pgZFF_X0, pgZFF_X1, pgZFF_X2, pgZFF_Y1, pgZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define output double reg
signal Y_out_double : std_logic_vector(31 downto 0) := (others => '0');
-- state machine signals
type state_type is (idle, run);
signal state_reg, state_next : state_type;
-- counter signals
signal q_reg, q_next : unsigned(2 downto 0);
signal q_reset, q_add : std_logic;
signal counter : integer := 1;
signal rst_cnt, s_trigger, s_multiply : std_logic;
constant shiftAddMultiply : boolean := true;
-- constant DSPMultiply : boolean := false;
signal mul_coefs, trunc_prods, sum_stg_a, trunc_out, Mul_stage_over, Mul_Ready : std_logic;
signal ZFF, Coef : std_logic_vector(31 downto 0) := (others => '0');
begin
-- process to shift samples
process(clk)
begin
if (rising_edge(clk)) then
if (rst = '1') then
ZFF_X0 <= (others => '0');
ZFF_X1 <= (others => '0');
ZFF_X2 <= (others => '0');
ZFF_Y1 <= (others => '0');
ZFF_Y2 <= (others => '0');
else
if (sample_trig = '1' and state_reg = idle) then
ZFF_X0 <= X_in(23) & X_in(23) & X_in & B"0000_00";
ZFF_X1 <= ZFF_X0;
ZFF_X2 <= ZFF_X1;
ZFF_Y1 <= Y_out_double;
ZFF_Y2 <= ZFF_Y1;
end if;
end if;
end if;
end process;
-- STATE UPDATE AND TIMING
process(clk)
begin
if (rising_edge(clk)) then
if (rst = '1') then
state_reg <= idle;
q_reg <= (others => '0'); -- reset counter
else
state_reg <= state_next; -- update the state
q_reg <= q_next;
end if;
end if;
end process;
-- COUNTER FOR TIMING
q_next <= (others => '0') when q_reset = '1' else -- resets the counter
q_reg + 2 when q_add = '1' and q_reg = 1 else q_reg + 1 when q_add = '1' else -- increment count if commanded
q_reg;
-- process for control of data path flags
process(q_reg, state_reg, sample_trig, Mul_stage_over)
begin
-- defaults
q_reset <= '0';
q_add <= '0';
mul_coefs <= '0';
trunc_prods <= '0';
sum_stg_a <= '0';
trunc_out <= '0';
filter_done <= '0';
rst_cnt <= '1';
case state_reg is
when idle =>
if (sample_trig = '1') then
state_next <= run;
else
state_next <= idle;
end if;
when run =>
if (q_reg < B"001") then
q_add <= '1';
state_next <= run;
elsif (q_reg < "011") then
rst_cnt <= '0'; -- allow counter to run so that it can count how many multiplication has been performed.
mul_coefs <= '1';
q_add <= '0';
-- seize the counter from counting until
if Mul_stage_over = '1' then -- multiplication is done.
q_add <= '1';
end if;
state_next <= run;
elsif (q_reg < "100") then
trunc_prods <= '1';
q_add <= '1';
state_next <= run;
elsif (q_reg < "101") then
sum_stg_a <= '1';
q_add <= '1';
state_next <= run;
elsif (q_reg < "110") then
trunc_out <= '1';
q_add <= '1';
state_next <= run;
else
q_reset <= '1';
filter_done <= '1';
state_next <= idle;
end if;
end case;
end process;
--Mul_Ready<= Mul_Ready1 and Mul_Ready2 and Mul_Ready3 and Mul_Ready4 and Mul_Ready5;
mul : entity work.multiplier
generic map(
MultiplierIsShiftAdd => shiftAddMultiply, --DSPMultiply,--
BIT_WIDTH => 32, COUNT_WIDTH => 6)
port map(CLK => clk, TRIGGER => s_multiply, A => signed(Coef), B => signed(ZFF), RES => mul_result, READY => Mul_Ready);
s_multiply <= mul_coefs and s_trigger;
Count_Multiplication : process(rst_cnt, Mul_Ready, rst)
begin
--if rising_edge(clk) then
if rst_cnt = '1' or rst = '1' then
counter <= 0;
elsif rising_edge(Mul_Ready) then
if mul_coefs = '1' then
counter <= counter + 1;
end if;
end if;
--end if;
end process;
--Mul_stage_over <= '1' when counter = 5 else '0';
Stage_input_values_for_multiplier : process(counter, Coef_b0, Coef_b1, Coef_b2, Coef_a1, Coef_a2, ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2)
begin
case counter is
when 0 =>
Coef <= Coef_b0;
ZFF <= ZFF_X0;
when 1 =>
Coef <= Coef_b1;
ZFF <= ZFF_X1;
when 2 =>
Coef <= Coef_b2;
ZFF <= ZFF_X2;
when 3 =>
Coef <= Coef_a1;
ZFF <= ZFF_Y1;
when 4 =>
Coef <= Coef_a2;
ZFF <= ZFF_Y2;
when others =>
Coef <= (others => '0');
ZFF <= (others => '0');
end case;
end process;
Stage_Multiplication_Result : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
pgZFF_X0_quad <= (others => '0');
pgZFF_X1_quad <= (others => '0');
pgZFF_X2_quad <= (others => '0');
pgZFF_Y1_quad <= (others => '0');
pgZFF_Y2_quad <= (others => '0');
s_trigger <= '1';
else
s_trigger <= '1';
Mul_stage_over <= '0';
case counter is
when 1 =>
if Mul_Ready = '1' then
pgZFF_X0_quad <= mul_result;
s_trigger <= '0';
end if;
when 2 =>
if Mul_Ready = '1' then
pgZFF_X1_quad <= mul_result;
s_trigger <= '0';
end if;
when 3 =>
if Mul_Ready = '1' then
pgZFF_X2_quad <= mul_result;
s_trigger <= '0';
end if;
when 4 =>
if Mul_Ready = '1' then
pgZFF_Y1_quad <= mul_result;
s_trigger <= '0';
end if;
when 5 =>
if Mul_Ready = '1' then
pgZFF_Y2_quad <= mul_result;
--s_trigger <= '0';
Mul_stage_over <= '1';
end if;
when others =>
-- pgZFF_X0_quad <= (others => '0');
-- pgZFF_X1_quad <= (others => '0');
-- pgZFF_X2_quad <= (others => '0');
-- pgZFF_Y1_quad <= (others => '0');
-- pgZFF_Y2_quad <= (others => '0');
end case;
end if;
end if;
end process;
-- truncate the output to summation block
process(clk)
begin
if rising_edge(clk) then
if (trunc_prods = '1') then
pgZFF_X0 <= std_logic_vector(pgZFF_X0_quad(61 downto 30));
pgZFF_X2 <= std_logic_vector(pgZFF_X2_quad(61 downto 30));
pgZFF_X1 <= std_logic_vector(pgZFF_X1_quad(61 downto 30));
pgZFF_Y1 <= std_logic_vector(pgZFF_Y1_quad(61 downto 30));
pgZFF_Y2 <= std_logic_vector(pgZFF_Y2_quad(61 downto 30));
end if;
end if;
end process;
-- sum all post gain feedback and feedfoward paths
-- Y[z] = X[z]*bo + X[z]*b1*Z^-1 + X[z]*b2*Z^-2 - Y[z]*a1*z^-1 + Y[z]*a2*z^-2
process(clk)
begin
if (rising_edge(clk)) then
if (sum_stg_a = '1') then
Y_out_double <= std_logic_vector(signed(pgZFF_X0) + signed(pgZFF_X1) + signed(pgZFF_X2) - signed(pgZFF_Y1) - signed(pgZFF_Y2));
end if;
end if;
end process;
-- output truncation block
process(clk)
begin
if rising_edge(clk) then
if (trunc_out = '1') then
Y_out <= Y_out_double(30 downto 7);
end if;
end if;
end process;
end arch; | lgpl-3.0 | 81554ba50c1e9fc5b957391def9ae4c3 | 0.564332 | 3.037217 | false | false | false | false |
peladex/RHD2132_FPGA | src/spi_master_slave/spi_master.vhd | 1 | 43,690 | -----------------------------------------------------------------------------------------------------------------------
-- Author: Jonny Doin, [email protected], [email protected]
--
-- Create Date: 12:18:12 04/25/2011
-- Module Name: SPI_MASTER - RTL
-- Project Name: SPI MASTER / SLAVE INTERFACE
-- Target Devices: Spartan-6
-- Tool versions: ISE 13.1
-- Description:
--
-- This block is the SPI master interface, implemented in one single entity.
-- All internal core operations are synchronous to the 'sclk_i', and a spi base clock is generated by dividing sclk_i downto
-- a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
-- All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
-- 'sclk_i' clock.
-- For optimized use of longlines, connect 'sclk_i' and 'pclk_i' to the same global clock line.
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
-- clock domains.
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
-- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), lookahead prefetch signaling
-- ('PREFETCH'), and spi base clock division from sclk_i ('SPI_2X_CLK_DIV').
--
-- SPI CLOCK GENERATION
-- ====================
--
-- The clock generation for the SPI SCK is derived from the high-speed 'sclk_i' clock. The core divides this reference
-- clock to form the SPI base clock, by the 'SPI_2X_CLK_DIV' generic parameter. The user must set the divider value for the
-- SPI_2X clock, which is 2x the desired SCK frequency.
-- All registers in the core are clocked by the high-speed clocks, and clock enables are used to run the FSM and other logic
-- at lower rates. This architecture preserves FPGA clock resources like global clock buffers, and avoids path delays caused
-- by combinatorial clock dividers outputs.
-- The core has async clock domain circuitry to handle asynchronous clocks for the SPI and parallel interfaces.
--
-- PARALLEL WRITE INTERFACE
-- ========================
-- The parallel interface has an input port 'di_i' and an output port 'do_o'.
-- Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'. 'di_req_o' is a look ahead data request line,
-- that is set 'PREFETCH' clock cycles in advance to synchronize a pipelined memory or fifo to present the
-- next input data at 'di_i' in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
-- For a pipelined sync RAM, a PREFETCH of 2 cycles allows an address generator to present the new adress to the RAM in one
-- cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the shifter.
-- If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
-- The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last SPI clock cycle,
-- if continuous transmission is intended. If 'wren_i' is not valid 2 SPI clock cycles after the last transmitted bit, the interface
-- enters idle state and deasserts SSEL.
-- When the interface is idle, 'wren_i' write strobe loads the data and starts transmission. 'di_req_o' will strobe when entering
-- idle state, if a previously loaded data has already been transferred.
--
-- PARALLEL WRITE SEQUENCE
-- =======================
-- __ __ __ __ __ __ __
-- pclk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- parallel interface clock
-- ___________
-- di_req_o ________/ \_____________________... -- 'di_req_o' asserted on rising edge of 'pclk_i'
-- ______________ ___________________________...
-- di_i __old_data____X______new_data_____________... -- user circuit loads data on 'di_i' at next 'pclk_i' rising edge
-- _______
-- wren_i __________________________/ \_______... -- user strobes 'wren_i' for one cycle of 'pclk_i'
--
--
-- PARALLEL READ INTERFACE
-- =======================
-- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete word is received,
-- the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_clk'.
-- The signal 'do_valid_o' is set one 'spi_clk' clock after, to directly drive a synchronous memory or fifo write enable.
-- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'pclk_i'.
-- When the interface is idle, data at the 'do_o' port holds the last word received.
--
-- PARALLEL READ SEQUENCE
-- ======================
-- ______ ______ ______ ______
-- spi_clk bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- internal spi 2x base clock
-- _ __ __ __ __ __ __ __ __
-- pclk_i \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- parallel interface clock (may be async to sclk_i)
-- _____________ _____________________________________... -- 1) rx data is transferred to 'do_buffer_reg'
-- do_o ___old_data__X__________new_data___________________... -- after last rx bit, at rising 'spi_clk'.
-- ____________
-- do_valid_o ____________________________/ \_________... -- 2) 'do_valid_o' strobed for 2 'pclk_i' cycles
-- -- on the 3rd 'pclk_i' rising edge.
--
--
-- The propagation delay of spi_sck_o and spi_mosi_o, referred to the internal clock, is balanced by similar path delays,
-- but the sampling delay of spi_miso_i imposes a setup time referred to the sck signal that limits the high frequency
-- of the interface, for full duplex operation.
--
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave
--
-- Author(s): Jonny Doin, [email protected], [email protected]
--
-- Copyright (C) 2011 Jonny Doin
-- -----------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.gnu.org/licenses/lgpl.txt
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2011/04/28 v0.01.0010 [JD] shifter implemented as a sequential process. timing problems and async issues in synthesis.
-- 2011/05/01 v0.01.0030 [JD] changed original shifter design to a fully pipelined RTL fsmd. solved all synthesis issues.
-- 2011/05/05 v0.01.0034 [JD] added an internal buffer register for rx_data, to allow greater liberty in data load/store.
-- 2011/05/08 v0.10.0038 [JD] increased one state to have SSEL start one cycle before SCK. Implemented full CPOL/CPHA
-- logic, based on generics, and do_valid_o signal.
-- 2011/05/13 v0.20.0045 [JD] streamlined signal names, added PREFETCH parameter, added assertions.
-- 2011/05/17 v0.80.0049 [JD] added explicit clock synchronization circuitry across clock boundaries.
-- 2011/05/18 v0.95.0050 [JD] clock generation circuitry, with generators for all-rising-edge clock core.
-- 2011/06/05 v0.96.0053 [JD] changed async clear to sync resets.
-- 2011/06/07 v0.97.0065 [JD] added cross-clock buffers, fixed fsm async glitches.
-- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce
-- synthesis LUT overhead in Spartan-6 architecture.
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
-- 2011/06/12 v0.97.0079 [JD] streamlined wr_ack for all cases and eliminated unnecessary register resets.
-- 2011/06/14 v0.97.0083 [JD] (bug CPHA effect) : redesigned SCK output circuit.
-- (minor bug) : removed fsm registers from (not rst_i) chip enable.
-- 2011/06/15 v0.97.0086 [JD] removed master MISO input register, to relax MISO data setup time (to get higher speed).
-- 2011/07/09 v1.00.0095 [JD] changed all clocking scheme to use a single high-speed clock with clock enables to control lower
-- frequency sequential circuits, to preserve clocking resources and avoid path delay glitches.
-- 2011/07/10 v1.00.0098 [JD] implemented SCK clock divider circuit to generate spi clock directly from system clock.
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz,
-- 7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
-- 2011/07/17 v1.11.0080 [JD] BUG: CPOL='1', CPHA='1' @50MHz causes MOSI to be shifted one bit earlier.
-- BUG: CPOL='0', CPHA='1' causes SCK to have one extra pulse with one sclk_i width at the end.
-- 2011/07/18 v1.12.0105 [JD] CHG: spi sck output register changed to remove glitch at last clock when CPHA='1'.
-- for CPHA='1', max spi clock is 25MHz. for CPHA= '0', max spi clock is >50MHz.
-- 2011/07/24 v1.13.0125 [JD] FIX: 'sck_ena_ce' is on half-cycle advanced to 'fsm_ce', elliminating CPHA='1' glitches.
-- Core verified for all CPOL, CPHA at up to 50MHz, simulates to over 100MHz.
-- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
-- 2011/08/01 v1.15.0135 [JD] Fixed latch inference for spi_mosi_o driver at the fsm.
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
-- 2011/08/04 v1.15.0136 [JD] Fixed assertions (PREFETCH >= 1) and minor comment bugs.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
-- ====
--
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
--================================================================================================================
-- SYNTHESIS CONSIDERATIONS
-- ========================
-- There are several output ports that are used to simulate and verify the core operation.
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- circuitry.
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
-- synthesis tool will remove the receive logic from the generated circuitry.
-- Alternatively, you can remove these ports and related circuitry once the core is verified and
-- integrated to your circuit.
--================================================================================================================
entity spi_master is
Generic (
N : positive := 16; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2; -- prefetch lookahead cycles
SPI_2X_CLK_DIV : positive := 2); -- for a 100MHz sclk_i, yields a 25MHz SCK
Port (
sclk_i : in std_logic := 'X'; -- high-speed serial interface system clock
pclk_i : in std_logic := 'X'; -- high-speed parallel interface system clock
rst_i : in std_logic := 'X'; -- reset core
---- serial interface ----
spi_ssel_o : out std_logic; -- spi bus slave select line
spi_sck_o : out std_logic; -- spi bus sck
spi_mosi_o : out std_logic; -- spi bus mosi output
spi_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
---- parallel interface ----
di_req_o : out std_logic; -- preload lookahead data request line
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel data in (clocked on rising spi_clk after last bit)
wren_i : in std_logic := 'X'; -- user data write enable, starts transmission when interface is idle
wr_ack_o : out std_logic; -- write acknowledge
do_valid_o : out std_logic; -- do_o data valid signal, valid during one spi_clk rising edge.
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked on rising spi_clk after last bit)
--- debug ports: can be removed or left unconnected for the application circuit ---
sck_ena_o : out std_logic; -- debug: internal sck enable signal
sck_ena_ce_o : out std_logic; -- debug: internal sck clock enable signal
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_reg_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
core_clk_o : out std_logic;
core_n_clk_o : out std_logic;
core_ce_o : out std_logic;
core_n_ce_o : out std_logic;
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end spi_master;
--================================================================================================================
-- this architecture is a pipelined register-transfer description.
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
--================================================================================================================
architecture rtl of spi_master is
-- core clocks, generated from 'sclk_i': initialized at GSR to differential values
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
signal core_ce : std_logic := '0'; -- core clock enable, positive logic
signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
-- spi bus clock, generated from the CPOL selected core clock polarity
signal spi_2x_ce : std_logic := '1'; -- spi_2x clock enable
signal spi_clk : std_logic := '0'; -- spi bus output clock
signal spi_clk_reg : std_logic; -- output pipeline delay for spi sck (do NOT global initialize)
-- core fsm clock enables
signal fsm_ce : std_logic := '1'; -- fsm clock enable
signal sck_ena_ce : std_logic := '1'; -- SCK clock enable
signal samp_ce : std_logic := '1'; -- data sampling clock enable
--
-- GLOBAL RESET:
-- all signals are initialized to zero at GSR (global set/reset) by giving explicit
-- initialization values at declaration. This is needed for all Xilinx FPGAs, and
-- especially for the Spartan-6 and newer CLB architectures, where a async reset can
-- reduce the usability of the slice registers, due to the need to share the control
-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
-- By using GSR for the initialization, and reducing async RESET local init to the bare
-- essential, the model achieves better LUT/FF packing and CLB usability.
--
-- internal state signals for register and combinatorial stages
signal state_next : natural range N+1 downto 0 := 0;
signal state_reg : natural range N+1 downto 0 := 0;
-- shifter signals for register and combinatorial stages
signal sh_next : std_logic_vector (N-1 downto 0);
signal sh_reg : std_logic_vector (N-1 downto 0);
-- input bit sampled buffer
signal rx_bit_reg : std_logic := '0';
-- buffered di_i data signals for register and combinatorial stages
signal di_reg : std_logic_vector (N-1 downto 0);
-- internal wren_i stretcher for fsm combinatorial stage
signal wren : std_logic;
signal wr_ack_next : std_logic := '0';
signal wr_ack_reg : std_logic := '0';
-- internal SSEL enable control signals
signal ssel_ena_next : std_logic := '0';
signal ssel_ena_reg : std_logic := '0';
-- internal SCK enable control signals
signal sck_ena_next : std_logic;
signal sck_ena_reg : std_logic;
-- buffered do_o data signals for register and combinatorial stages
signal do_buffer_next : std_logic_vector (N-1 downto 0);
signal do_buffer_reg : std_logic_vector (N-1 downto 0);
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
-- internal input data request signal
signal di_req_next : std_logic := '0';
signal di_req_reg : std_logic := '0';
-- cross-clock do_transfer_reg -> do_valid_o_reg pipeline
signal do_valid_A : std_logic := '0';
signal do_valid_B : std_logic := '0';
signal do_valid_C : std_logic := '0';
signal do_valid_D : std_logic := '0';
signal do_valid_next : std_logic := '0';
signal do_valid_o_reg : std_logic := '0';
-- cross-clock di_req_reg -> di_req_o_reg pipeline
signal di_req_o_A : std_logic := '0';
signal di_req_o_B : std_logic := '0';
signal di_req_o_C : std_logic := '0';
signal di_req_o_D : std_logic := '0';
signal di_req_o_next : std_logic := '1';
signal di_req_o_reg : std_logic := '1';
begin
--=============================================================================================
-- GENERICS CONSTRAINTS CHECKING
--=============================================================================================
-- minimum word width is 8 bits
assert N >= 8
report "Generic parameter 'N' (shift register size) needs to be 8 bits minimum"
severity FAILURE;
-- minimum prefetch lookahead check
assert PREFETCH >= 1
report "Generic parameter 'PREFETCH' (lookahead count) needs to be 1 minimum"
severity FAILURE;
-- maximum prefetch lookahead check
assert PREFETCH <= N-5
report "Generic parameter 'PREFETCH' (lookahead count) out of range, needs to be N-5 maximum"
severity FAILURE;
-- SPI_2X_CLK_DIV clock divider value must not be zero
assert SPI_2X_CLK_DIV > 0
report "Generic parameter 'SPI_2X_CLK_DIV' must not be zero"
severity FAILURE;
--=============================================================================================
-- CLOCK GENERATION
--=============================================================================================
-- In order to preserve global clocking resources, the core clocking scheme is completely based
-- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
-- the spi clock generator and the input sampling clock.
-- The clock generation block derives 2 continuous antiphase signals from the 2x spi base clock
-- for the core clocking.
-- The 2 clock phases are generated by separate and synchronous FFs, and should have only
-- differential interconnect delay skew.
-- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock
-- enables are used to control clocking of all internal synchronous circuitry.
-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
-- based on the configuration of CPOL and CPHA.
-- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
-- modes, by a single high-speed global clock, preserving clock resources and clock to data skew.
-----------------------------------------------------------------------------------------------
-- generate the 2x spi base clock enable from the serial high-speed input clock
spi_2x_ce_gen_proc: process (sclk_i) is
variable clk_cnt : integer range SPI_2X_CLK_DIV-1 downto 0 := 0;
begin
if sclk_i'event and sclk_i = '1' then
if clk_cnt = SPI_2X_CLK_DIV-1 then
spi_2x_ce <= '1';
clk_cnt := 0;
else
spi_2x_ce <= '0';
clk_cnt := clk_cnt + 1;
end if;
end if;
end process spi_2x_ce_gen_proc;
-----------------------------------------------------------------------------------------------
-- generate the core antiphase clocks and clock enables from the 2x base CE.
core_clock_gen_proc : process (sclk_i) is
begin
if sclk_i'event and sclk_i = '1' then
if spi_2x_ce = '1' then
-- generate the 2 antiphase core clocks
core_clk <= core_n_clk;
core_n_clk <= not core_n_clk;
-- generate the 2 phase core clock enables
core_ce <= core_n_clk;
core_n_ce <= not core_n_clk;
else
core_ce <= '0';
core_n_ce <= '0';
end if;
end if;
end process core_clock_gen_proc;
--=============================================================================================
-- GENERATE BLOCKS
--=============================================================================================
-- spi clk generator: generate spi_clk from core_clk depending on CPOL
spi_sck_cpol_0_proc: if CPOL = '0' generate
begin
spi_clk <= core_clk; -- for CPOL=0, spi clk has idle LOW
end generate;
spi_sck_cpol_1_proc: if CPOL = '1' generate
begin
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH
end generate;
-----------------------------------------------------------------------------------------------
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
-- always sample data at the half-cycle of the fsm update cell
samp_ce_cpha_0_proc: if CPHA = '0' generate
begin
samp_ce <= core_ce;
end generate;
samp_ce_cpha_1_proc: if CPHA = '1' generate
begin
samp_ce <= core_n_ce;
end generate;
-----------------------------------------------------------------------------------------------
-- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA
fsm_ce_cpha_0_proc: if CPHA = '0' generate
begin
fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable
end generate;
fsm_ce_cpha_1_proc: if CPHA = '1' generate
begin
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable
end generate;
-----------------------------------------------------------------------------------------------
-- sck enable control: control sck advance phase for CPHA='1' relative to fsm clock
sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle
--=============================================================================================
-- REGISTERED INPUTS
--=============================================================================================
-- rx bit flop: capture rx bit after SAMPLE edge of sck
rx_bit_proc : process (sclk_i, spi_miso_i) is
begin
if sclk_i'event and sclk_i = '1' then
if samp_ce = '1' then
rx_bit_reg <= spi_miso_i;
end if;
end if;
end process rx_bit_proc;
--=============================================================================================
-- CROSS-CLOCK PIPELINE TRANSFER LOGIC
--=============================================================================================
-- do_valid_o and di_req_o strobe output logic
-- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a
-- fixed-length delayed pulse for the output flags, at the parallel clock domain
out_transfer_proc : process ( pclk_i, do_transfer_reg, di_req_reg,
do_valid_A, do_valid_B, do_valid_D,
di_req_o_A, di_req_o_B, di_req_o_D ) is
begin
if pclk_i'event and pclk_i = '1' then -- clock at parallel port clock
-- do_transfer_reg -> do_valid_o_reg
do_valid_A <= do_transfer_reg; -- the input signal must be at least 2 clocks long
do_valid_B <= do_valid_A; -- feed it to a ripple chain of FFDs
do_valid_C <= do_valid_B;
do_valid_D <= do_valid_C;
do_valid_o_reg <= do_valid_next; -- registered output pulse
--------------------------------
-- di_req_reg -> di_req_o_reg
di_req_o_A <= di_req_reg; -- the input signal must be at least 2 clocks long
di_req_o_B <= di_req_o_A; -- feed it to a ripple chain of FFDs
di_req_o_C <= di_req_o_B;
di_req_o_D <= di_req_o_C;
di_req_o_reg <= di_req_o_next; -- registered output pulse
end if;
-- generate a 2-clocks pulse at the 3rd clock cycle
do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
end process out_transfer_proc;
-- parallel load input registers: data register and write enable
in_transfer_proc: process ( pclk_i, wren_i, wr_ack_reg ) is
begin
-- registered data input, input register with clock enable
if pclk_i'event and pclk_i = '1' then
if wren_i = '1' then
di_reg <= di_i; -- parallel data input buffer register
end if;
end if;
-- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
if pclk_i'event and pclk_i = '1' then
if wren_i = '1' then -- wren_i is the sync preset for wren
wren <= '1';
elsif wr_ack_reg = '1' then -- wr_ack is the sync reset for wren
wren <= '0';
end if;
end if;
end process in_transfer_proc;
--=============================================================================================
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers: synchronous to the spi base reference clock
core_reg_proc : process (sclk_i) is
begin
-- FF registers clocked on rising edge and cleared on sync rst_i
if sclk_i'event and sclk_i = '1' then
if rst_i = '1' then -- sync reset
state_reg <= 0; -- only provide local reset for the state machine
elsif fsm_ce = '1' then -- fsm_ce is clock enable for the fsm
state_reg <= state_next; -- state register
end if;
end if;
-- FF registers clocked synchronous to the fsm state
if sclk_i'event and sclk_i = '1' then
if fsm_ce = '1' then
sh_reg <= sh_next; -- shift register
ssel_ena_reg <= ssel_ena_next; -- spi select enable
do_buffer_reg <= do_buffer_next; -- registered output data buffer
do_transfer_reg <= do_transfer_next; -- output data transferred to buffer
di_req_reg <= di_req_next; -- input data request
wr_ack_reg <= wr_ack_next; -- write acknowledge for data load synchronization
end if;
end if;
-- FF registers clocked one-half cycle earlier than the fsm state
if sclk_i'event and sclk_i = '1' then
if sck_ena_ce = '1' then
sck_ena_reg <= sck_ena_next; -- spi clock enable: look ahead logic
end if;
end if;
end process core_reg_proc;
--=============================================================================================
-- COMBINATORIAL LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinatorial logic
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg,
do_transfer_reg, wr_ack_reg, di_req_reg, di_reg, wren ) is
begin
sh_next <= sh_reg; -- all output signals are assigned to (avoid latches)
ssel_ena_next <= ssel_ena_reg; -- controls the slave select line
sck_ena_next <= sck_ena_reg; -- controls the clock enable of spi sck line
do_buffer_next <= do_buffer_reg; -- output data buffer
do_transfer_next <= do_transfer_reg; -- output data flag
wr_ack_next <= wr_ack_reg; -- write acknowledge
di_req_next <= di_req_reg; -- prefetch data request
spi_mosi_o <= sh_reg(N-1); -- default to avoid latch inference
state_next <= state_reg; -- next state
case state_reg is
when (N+1) => -- this state is to enable SSEL before SCK
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
ssel_ena_next <= '1'; -- tx in progress: will assert SSEL
sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle)
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N) => -- deassert 'di_rdy' and stretch do_valid
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N-1) downto (PREFETCH+3) => -- remove 'do_transfer' and shift bits
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- reset 'do_valid' transfer signal
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (PREFETCH+2) downto 2 => -- raise prefetch 'di_req_o' signal
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when 1 => -- transfer rx data to do_buffer and restart if new data is written
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer
do_transfer_next <= '1'; -- signal transfer to do_buffer
if wren = '1' then -- load tx register if valid data present at di_i
state_next <= N; -- next state is top bit of new data
sh_next <= di_reg; -- load parallel data from di_reg into shifter
sck_ena_next <= '1'; -- SCK enabled
wr_ack_next <= '1'; -- acknowledge data in transfer
else
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
end if;
when 0 => -- idle state: start and end of transmission
di_req_next <= '1'; -- will request data if shifter empty
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
if wren = '1' then -- load tx register if valid data present at di_i
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead)
ssel_ena_next <= '1'; -- enable interface SSEL
state_next <= N+1; -- start from idle: let one cycle for SSEL settling
sh_next <= di_reg; -- load bits from di_reg into shifter
wr_ack_next <= '1'; -- acknowledge data in transfer
else
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
ssel_ena_next <= '0'; -- deassert SSEL: interface is idle
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= 0; -- when idle, keep this state
end if;
when others =>
state_next <= 0; -- state 0 is safe state
end case;
end process core_combi_proc;
--=============================================================================================
-- OUTPUT LOGIC PROCESSES
--=============================================================================================
-- data output processes
spi_ssel_o_proc: spi_ssel_o <= not ssel_ena_reg; -- active-low slave select line
do_o_proc: do_o <= do_buffer_reg; -- parallel data out
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- data out valid
di_req_o_proc: di_req_o <= di_req_o_reg; -- input data request for next cycle
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- write acknowledge
-----------------------------------------------------------------------------------------------
-- SCK out logic: pipeline phase compensation for the SCK line
-----------------------------------------------------------------------------------------------
-- This is a MUX with an output register.
-- The register gives us a pipeline delay for the SCK line, pairing with the state machine moore
-- output pipeline delay for the MOSI line, and thus enabling higher SCK frequency.
spi_sck_o_gen_proc : process (sclk_i, sck_ena_reg, spi_clk, spi_clk_reg) is
begin
if sclk_i'event and sclk_i = '1' then
if sck_ena_reg = '1' then
spi_clk_reg <= spi_clk; -- copy the selected clock polarity
else
spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity
end if;
end if;
spi_sck_o <= spi_clk_reg; -- connect register to output
end process spi_sck_o_gen_proc;
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- these signals are useful for verification, and can be deleted after debug.
do_transfer_proc: do_transfer_o <= do_transfer_reg;
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4));
rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg;
wren_o_proc: wren_o <= wren;
sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg;
core_clk_o_proc: core_clk_o <= core_clk;
core_n_clk_o_proc: core_n_clk_o <= core_n_clk;
core_ce_o_proc: core_ce_o <= core_ce;
core_n_ce_o_proc: core_n_ce_o <= core_n_ce;
sck_ena_o_proc: sck_ena_o <= sck_ena_reg;
sck_ena_ce_o_proc: sck_ena_ce_o <= sck_ena_ce;
end architecture rtl;
| gpl-3.0 | 2b2eb854952e76c2caf976f47559d4b6 | 0.485077 | 4.629159 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/inter_core_reg_file.vhd | 1 | 3,758 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity inter_core_reg_file is
generic(
size_x : integer := 20;
size_y : integer := 20;
interp_x : integer := 1;
interp_y : integer := 1;
sample_size : integer := 4;
samples_per_wr : integer := 1
);
port(
clk : in std_logic;
rst : in std_logic;
--read interface
rd_addr_x : in std_logic_vector(7 downto 0);
rd_addr_y : in std_logic_vector(7 downto 0);
rd_samples : out std_logic_vector((interp_x+5)*(interp_y+5)*sample_size-1 downto 0);
--write interface
wr_addr_x : in std_logic_vector(7 downto 0);
wr_addr_y : in std_logic_vector(7 downto 0);
wr_enable : in std_logic;
wr_samples : in std_logic_vector(samples_per_wr*sample_size-1 downto 0)
);
end entity inter_core_reg_file;
architecture rtl of inter_core_reg_file is
signal register_bits_d : std_logic_vector(size_x*size_y*sample_size-1 downto 0);
signal register_bits_q : std_logic_vector(size_x*size_y*sample_size-1 downto 0);
signal offset : natural;
signal rd_addr_x_int : integer;
signal rd_addr_y_int : integer;
begin
--register process
process(clk, rst)
begin
if rst = '1' then
register_bits_q <= (others => '0');
elsif rising_edge(clk) then
register_bits_q <= register_bits_d;
end if;
end process;
--register update logic
assert ((size_x*size_y) mod samples_per_wr) = 0 report "bad samples_per_wr" severity error;
g0: for n in ((size_x*size_y)/samples_per_wr)-1 downto 0 generate
constant x_location : integer := n mod (size_x/samples_per_wr);
constant y_location : integer := n / (size_x/samples_per_wr);
constant vector_index_low : integer := n * sample_size * samples_per_wr;
constant vector_index_high : integer := vector_index_low + sample_size * samples_per_wr - 1;
begin
register_bits_d(vector_index_high downto vector_index_low) <=
(others => '0') when rst = '1' else
wr_samples
when to_integer(unsigned(wr_addr_x)) = x_location
and to_integer(unsigned(wr_addr_y)) = y_location
and wr_enable = '1' else
register_bits_q(vector_index_high downto vector_index_low);
end generate;
--read logic
assert ((size_x - 4) mod interp_x) = 0 report "size_x/interp_x conflict" severity warning;
assert ((size_y - 4) mod interp_y) = 0 report "size_y/interp_y conflict" severity warning;
rd_addr_x_int <= to_integer(signed(rd_addr_x));
rd_addr_y_int <= to_integer(signed(rd_addr_y));
--offset <= ((rd_addr_x_int-2) + ((rd_addr_y_int-2) * size_x)) * sample_size when (rd_addr_x_int >= 2) and (rd_addr_y_int >= 2) else 0;
offset <= 256 when rd_addr_y_int = 4 else 0;
g1: for n in (interp_y+5)-1 downto 0 generate
--indexes into the result vector
constant bits_per_row : integer := (interp_x+5) * sample_size;
constant rd_samples_low : integer := n * bits_per_row;
constant rd_samples_high : integer := rd_samples_low + bits_per_row - 1;
--indexes relative to offset of read data
constant rel_lin_addr : integer := n * size_x * sample_size;
begin
rd_samples(rd_samples_high downto rd_samples_low) <= register_bits_q(offset + rel_lin_addr + bits_per_row -1
downto offset + rel_lin_addr);
--rd_samples(rd_samples_high downto rd_samples_low) <= register_bits_q(bits_per_row -1
-- downto 0);
end generate;
end architecture rtl; | mit | 76de91f2396569e0b8b653f00defb716 | 0.600319 | 3.070261 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/inter_node.vhd | 1 | 13,261 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity inter_node is
generic(
size_x : integer := 9;
size_y : integer := 9;
interp_x : integer := 4;
interp_y : integer := 4;
sample_size : integer := 8;
samples_per_wr : integer := 8;
data_width : integer := 64;
addr_width : integer := 4;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic
);
end entity inter_node;
architecture fsmd of inter_node is
---------------------------------------------------------------------------
-- Constants --------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Components -------------------------------------------------------------
---------------------------------------------------------------------------
component inter_core is
generic(
x_len : integer := 4;
y_len : integer := 4;
sample_size : integer := 8
);
port(
samples : in std_logic_vector((x_len+5)*(y_len+5)*sample_size-1 downto 0);
sel : in std_logic_vector(7 downto 0);
result : out std_logic_vector(x_len*y_len*sample_size-1 downto 0)
);
end component inter_core;
component inter_core_reg_file is
generic(
size_x : integer := 20;
size_y : integer := 20;
interp_x : integer := 1;
interp_y : integer := 1;
sample_size : integer := 4;
samples_per_wr : integer := 1
);
port(
clk : in std_logic;
rst : in std_logic;
--read interface
rd_addr_x : in std_logic_vector(7 downto 0);
rd_addr_y : in std_logic_vector(7 downto 0);
rd_samples : out std_logic_vector((interp_x+5)*(interp_y+5)*sample_size-1 downto 0);
--write interface
wr_addr_x : in std_logic_vector(7 downto 0);
wr_addr_y : in std_logic_vector(7 downto 0);
wr_enable : in std_logic;
wr_samples : in std_logic_vector(samples_per_wr*sample_size-1 downto 0)
);
end component inter_core_reg_file;
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
---------------------------------------------------------------------------
-- Types ------------------------------------------------------------------
---------------------------------------------------------------------------
type inter_states is (idle, sel_vc, init_rx, rx, rx_dequeue, wait_rx, init_tx, gen_resp, wait_tx, tx);
---------------------------------------------------------------------------
-- Signals ----------------------------------------------------------------
---------------------------------------------------------------------------
--component interfaces
signal rd_addr_x : std_logic_vector(7 downto 0);
signal rd_addr_y : std_logic_vector(7 downto 0);
signal rd_samples : std_logic_vector((interp_x+5)*(interp_y+5)*sample_size-1 downto 0);
signal wr_addr_x : std_logic_vector(7 downto 0);
signal wr_addr_y : std_logic_vector(7 downto 0);
signal wr_enable : std_logic;
signal wr_samples : std_logic_vector(samples_per_wr*sample_size-1 downto 0);
signal sel : std_logic_vector(7 downto 0);
signal result : std_logic_vector(interp_x*interp_y*sample_size-1 downto 0);
-- FSMD registers and signals
signal interp_mode_d : std_logic_vector(7 downto 0);
signal interp_mode_q : std_logic_vector(7 downto 0);
signal cmd_width_d : std_logic_vector(7 downto 0);
signal cmd_width_q : std_logic_vector(7 downto 0);
signal cmd_height_d : std_logic_vector(7 downto 0);
signal cmd_height_q : std_logic_vector(7 downto 0);
signal part_width_d : std_logic_vector(7 downto 0);
signal part_width_q : std_logic_vector(7 downto 0);
signal part_height_d : std_logic_vector(7 downto 0);
signal part_height_q : std_logic_vector(7 downto 0);
signal ref_num_d : std_logic_vector(31 downto 0);
signal ref_num_q : std_logic_vector(31 downto 0);
signal counter_d : unsigned(7 downto 0);
signal counter_q : unsigned(7 downto 0);
signal tx_max_count : unsigned(7 downto 0);
signal selected_vc_encoder : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_one_hot : std_logic_vector(num_vc-1 downto 0);
signal wr_addr_x_int : integer;
signal wr_addr_y_int : integer;
signal rd_addr_x_int : integer;
signal rd_addr_y_int : integer;
-- state machine signals
signal state : inter_states;
signal next_state : inter_states;
begin
---------------------------------------------------------------------------
-- Datapath ---------------------------------------------------------------
---------------------------------------------------------------------------
u0: component inter_core
generic map(
x_len => interp_x,
y_len => interp_y,
sample_size => sample_size
)
port map(
samples => rd_samples,
sel => sel,
result => result
);
u1: component inter_core_reg_file
generic map(
size_x => size_x,
size_y => size_y,
interp_x => interp_x,
interp_y => interp_y,
sample_size => sample_size,
samples_per_wr => samples_per_wr
)
port map(
clk => clk,
rst => rst,
rd_addr_x => rd_addr_x,
rd_addr_y => rd_addr_y,
rd_samples => rd_samples,
wr_addr_x => wr_addr_x,
wr_addr_y => wr_addr_y,
wr_enable => wr_enable,
wr_samples => wr_samples
);
u2: component priority_encoder
generic map(
encoded_word_size => vc_sel_width
)
Port map(
input => data_in_buffer,
output => selected_vc_encoder
);
--datapath registers
process(clk, rst)
begin
if rst = '1' then
interp_mode_q <= (others => '0');
cmd_width_q <= (others => '0');
cmd_height_q <= (others => '0');
part_width_q <= (others => '0');
part_height_q <= (others => '0');
ref_num_q <= (others => '0');
counter_q <= (others => '0');
selected_vc_q <= (others => '0');
elsif rising_edge(clk) then
interp_mode_q <= interp_mode_d;
cmd_width_q <= cmd_width_d;
cmd_height_q <= cmd_height_d;
part_width_q <= part_width_d;
part_height_q <= part_height_d;
ref_num_q <= ref_num_d;
counter_q <= counter_d;
selected_vc_q <= selected_vc_d;
end if;
end process;
--Parser logic
ref_num_d <= recv_data(31 downto 0 ) when state = rx and counter_q = x"00" else ref_num_q;
interp_mode_d <= recv_data(7 downto 0 ) when state = rx and counter_q = x"01" else interp_mode_q;
part_width_d <= recv_data(15 downto 8) when state = rx and counter_q = x"01" else part_width_q;
part_height_d <= recv_data(23 downto 16) when state = rx and counter_q = x"01" else part_height_q;
sel <= interp_mode_q;
wr_samples <= recv_data(sample_size*samples_per_wr-1 downto 0);
selected_vc_one_hot <= "10" when selected_vc_d = "1" else "01"; --todo make generic
--calculate buffer write addresses
wr_addr_x_int <= to_integer(unsigned(counter_q - to_unsigned(2, 8))) mod (size_x/samples_per_wr);
wr_addr_y_int <= to_integer(unsigned(counter_q - to_unsigned(2, 8))) / (size_x/samples_per_wr);
wr_addr_x <= std_logic_vector(to_unsigned(wr_addr_x_int, 8));
wr_addr_y <= std_logic_vector(to_unsigned(wr_addr_y_int, 8));
--buffer controls
wr_enable <= '1' when state = rx and counter_q >= to_unsigned(2, 8) else '0';
--counter update
counter_d <= counter_q + to_unsigned(1, 8) when state = rx_dequeue or state = gen_resp else
to_unsigned(0, 8) when state = init_tx or state = sel_vc else
counter_q;
--select virtual channel
selected_vc_d <= selected_vc_encoder when state = sel_vc else selected_vc_q;
--packet generation logic
assert interp_x*interp_y*sample_size = data_width report "inter_prediction_node: interpolation-block/flit-size mismatch" severity error;
send_data <= X"00000000" & ref_num_q when counter_q = x"01" else result;
rd_addr_x_int <= 2; -- todo: this really shouldn't be a constant, some generic parameters will not work...
rd_addr_x <= std_logic_vector(to_unsigned(rd_addr_x_int, 8));
rd_addr_y_int <= (to_integer(unsigned(counter_q)) - 2)*2 + 2;
rd_addr_y <= std_logic_vector(to_unsigned(rd_addr_y_int, 8));
tx_max_count <= unsigned(part_height_q) + to_unsigned(1, 8);
--output logic (Noc control stuff)
dequeue <= selected_vc_one_hot when state = rx_dequeue else (others => '0');
select_vc_read <= selected_vc_q;
dest_addr <= std_logic_vector(to_unsigned(7, addr_width));
set_tail_flit <= '1' when (state = tx or state = wait_tx) and counter_q >= tx_max_count else '0';
send_flit <= '1' when state = tx else '0';
---------------------------------------------------------------------------
-- State Machine ----------------------------------------------------------
---------------------------------------------------------------------------
process(clk, rst)
begin
if rst = '1' then
state <= idle;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;
process(state, data_in_buffer, is_tail_flit, selected_vc_one_hot, ready_to_send, counter_q, tx_max_count)
begin
--default
next_state <= state;
if state = idle and or_reduce(data_in_buffer) = '1' then
next_state <= sel_vc;
end if;
if state = sel_vc then
next_state <= init_rx;
end if;
if state = init_rx then
next_state <= rx;
end if;
if state = rx then
next_state <= rx_dequeue;
end if;
if state = rx_dequeue and is_tail_flit = '0' then
next_state <= wait_rx;
end if;
if state = rx_dequeue and is_tail_flit = '1' then
next_state <= init_tx;
end if;
if state = wait_rx and or_reduce(selected_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx;
end if;
if state = init_tx then
next_state <= gen_resp;
end if;
if state = gen_resp then
next_state <= wait_tx;
end if;
if state = wait_tx and ready_to_send = '1' then
next_state <= tx;
end if;
if state = tx and counter_q < tx_max_count then
next_state <= gen_resp;
end if;
if state = tx and counter_q >= tx_max_count then
next_state <= idle;
end if;
end process;
end architecture fsmd; | mit | a0e75d484dae488211b49031f1916d94 | 0.47553 | 3.858307 | false | false | false | false |
boztalay/OldProjects | FPGA/Sys_SecondTimer/Comp_DataMUX4x4.vhd | 1 | 1,733 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 15:51:47 07/30/2009
-- Design Name:
-- Module Name: Comp_DataMUX - Behavioral
-- Project Name: Data Multiplexer
-- Target Devices:
-- Tool versions:
-- Description: A multiplexer that multiplexes inputs with two or more bits each.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - First draft written
-- Revision 0.15 - Syntax errors fixed
-- Revision 0.30 - UCF file written
-- Revision 1.00 - Generated programming file with successul hardware test
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Comp_DataMUX4x4 is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC_VECTOR (3 downto 0);
D : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC_VECTOR (3 downto 0));
end Comp_DataMUX4x4;
architecture Behavioral of Comp_DataMUX4x4 is
begin
main : process(A, B, C, D, sel) is
begin
case sel is
when b"00" =>
output <= A;
when b"01" =>
output <= B;
when b"10" =>
output <= C;
when b"11" =>
output <= D;
when others =>
output <= b"0000";
end case;
end process main;
end Behavioral;
| mit | df156f68013c90ebf9fe93225866a6c7 | 0.576457 | 3.580579 | false | false | false | false |
boztalay/OldProjects | FPGA/testytest/top_level.vhd | 1 | 5,051 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top_level is
Port (
mclk : in std_logic;
rst : in std_logic;
CQ_write_en : in STD_LOGIC;
VQ_read_en : in STD_LOGIC;
-- switches : in STD_LOGIC_VECTOR(7 downto 0);
memory_address_bus: inout std_logic_vector(22 downto 0);
memory_data_bus : inout std_logic_vector(15 downto 0);
anodes : out STD_LOGIC_VECTOR(3 downto 0);
decoder_out : out STD_LOGIC_VECTOR(6 downto 0);
RAM_oe : out std_logic;
RAM_we : out std_logic;
RAM_adv : out std_logic;
RAM_clk : out std_logic;
RAM_ub : out std_logic;
RAM_lb : out std_logic;
RAM_ce : out std_logic;
RAM_cre : out std_logic;
RAM_wait : in std_logic;
LEDs : out std_logic_vector(7 downto 0)
);
end top_level;
architecture Behavioral of top_level is
component DCMi_80 is
port ( CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLK0_OUT : out std_logic);
end component;
component four_dig_7seg is
Port ( clock : in STD_LOGIC;
display_data : in STD_LOGIC_VECTOR (15 downto 0);
anodes : out STD_LOGIC_VECTOR (3 downto 0);
to_display : out STD_LOGIC_VECTOR (6 downto 0));
end component;
component memory is
Port (
clk80 : in std_logic;
rst : in std_logic;
cam_vs : in STD_LOGIC;
vid_vs : in STD_LOGIC;
empty : out STD_LOGIC;
full : out STD_LOGIC;
CQ_write_en : in STD_LOGIC;
-- CQ_write_clk : in STD_LOGIC;
CQ_data_in : in STD_LOGIC_VECTOR(15 downto 0);
VQ_read_en : in STD_LOGIC;
-- VQ_read_clk : in STD_LOGIC;
VQ_data_out : out STD_LOGIC_VECTOR(15 downto 0);
-- VQ_data_out_dumb : out STD_LOGIC_VECTOR(15 downto 0);
RAM_addr : out std_logic_vector(22 downto 0);
RAM_data_out : out std_logic_vector(15 downto 0);
RAM_data_in : in std_logic_vector(15 downto 0);
RAM_oe : out std_logic;
RAM_we : out std_logic;
RAM_adv : out std_logic;
RAM_clk_en : out std_logic;
RAM_ub : out std_logic;
RAM_lb : out std_logic;
RAM_ce : out std_logic;
RAM_cre : out std_logic;
RAM_wait : in std_logic;
led : out std_logic_vector(7 downto 0)
);
end component;
signal clk80, dcm_clk_25, RAM_clk_en : std_logic;
signal count : std_logic_vector(24 downto 0);
signal CQ_write_clk : STD_LOGIC;
signal VQ_read_clk : STD_LOGIC;
signal display_data : STD_LOGIC_VECTOR(15 downto 0);
signal RAM_addr_s : std_logic_vector(22 downto 0);
signal RAM_data_in, RAM_data_out, RAM_data_reg : std_logic_vector(15 downto 0);
signal RAM_oe_s, RAM_oe_reg, RAM_we_s, RAM_adv_s, RAM_ub_s, RAM_lb_s, RAM_ce_s, RAM_cre_s : std_logic;
signal pclk25, clk25:std_logic;
signal clk_625 : STD_LOGIC;
signal CQ_data_in_sig : STD_LOGIC_VECTOR(15 downto 0);
begin
clk25 <= count(0);
pclk25 <= clk25;
RAM_clk <= clk80; --when RAM_clk_en='1' else 'Z';
--CQ_write_clk <= count(3);
--VQ_read_clk <= count(3);
LEDs(0) <= count(24);
--50 MHz clock divider
mclk_proc: process(mclk, rst)
begin
if rst = '1' then
count <= (others => '0');
elsif mclk'event and mclk = '1' then
count <= count + 1;
end if;
end process;
--Note, clk80 is now at 100 MHz, not 80
DCM1: DCMi_80 port map (
CLKIN_IN => pclk25,
CLKFX_OUT => clk80,
CLK0_OUT => dcm_clk_25
);
display: four_dig_7seg port map(
clock => mclk,
display_data => display_data,
anodes => anodes,
to_display => decoder_out);
MainMem: memory Port map (
clk80 => clk80,
rst => rst,
empty => LEDs(1),
full => LEDs(2),
cam_vs => '0',
vid_vs => '1',
CQ_write_en => CQ_write_en,
--CQ_write_clk => CQ_write_clk,
CQ_data_in => CQ_data_in_sig,
VQ_read_en => VQ_read_en,
--VQ_read_clk => VQ_read_clk,
VQ_data_out => display_data,
RAM_addr => RAM_addr_s,
RAM_data_out => RAM_data_out,
RAM_data_in => RAM_data_in,
RAM_oe => RAM_oe_s,
RAM_we => RAM_we_s,
RAM_adv => RAM_adv_s,
RAM_clk_en => RAM_clk_en,
RAM_ub => RAM_ub_s,
RAM_lb => RAM_lb_s,
RAM_ce => RAM_ce_s,
RAM_cre => RAM_cre_s,
RAM_wait => RAM_wait
);
OutputRegs: process(clk80, rst)
begin
if rst='1' then
memory_address_bus <= (others=>'0');
RAM_data_reg <= (others=>'0');
RAM_oe_reg <= '1';
RAM_we <= '1';
RAM_adv <= '1';
RAM_ub <= '1';
RAM_lb <= '1';
RAM_ce <= '1';
RAM_cre <= '0';
elsif clk80'event and clk80='0' then
memory_address_bus <= RAM_addr_s;
RAM_data_reg <= RAM_data_out;
RAM_oe_reg <= RAM_oe_s;
RAM_we <= RAM_we_s;
RAM_adv <= RAM_adv_s;
RAM_ub <= RAM_ub_s;
RAM_lb <= RAM_lb_s;
RAM_ce <= RAM_ce_s;
RAM_cre <= RAM_cre_s;
end if;
end process;
RAM_oe <= RAM_oe_reg;
memory_data_bus <= RAM_data_reg when RAM_oe_reg='1' else (others=>'Z');
RAM_data_in <= memory_data_bus;
CQ_data_in_sig <= x"6E6E";
LEDs(7 downto 3) <= (others => '0');
end Behavioral;
| mit | a89fa7dce09462558d2b38983dfa680f | 0.585825 | 2.596915 | false | false | false | false |
boztalay/OldProjects | FPGA/Sys_SecondTimer/Comp_ClockGen400Hz.vhd | 1 | 1,740 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 14:57:12 07/30/2009
-- Design Name:
-- Module Name: Comp_ClockGen - Behavioral
-- Project Name: Clock Generator
-- Target Devices:
-- Tool versions:
-- Description: A device that generates a buffered clock signal in refernce to
-- a 50 MHz outside clock. The output can be reconfigured through
-- software to generate a different frequency.
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - First draft written
-- Revision 0.15 - Sytax errors fixed
-- Revision 0.30 - UCF File written
-- Revision 1.00 - Generated programming file with a successful hardware test
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Comp_ClockGen400Hz is
Port ( Board_Clk : in STD_LOGIC;
Clock_Out : out STD_LOGIC);
end Comp_ClockGen400Hz;
architecture Behavioral of Comp_ClockGen400Hz is
begin
main : process(Board_Clk) is
constant hertz : integer := 400;
constant cycles : integer := (25_000_000/hertz);
variable count : integer := 0;
variable output : STD_LOGIC := '0';
begin
if rising_edge(Board_Clk) then
count := count + 1;
if count > cycles then
count := 0;
output := not output;
end if;
end if;
Clock_Out <= output;
end process main;
end Behavioral;
| mit | 58f8648b5a79695d466c946b345d80c8 | 0.62069 | 3.866667 | false | false | false | false |
peladex/RHD2132_FPGA | quartus/test_spi_comm/m_control_sim.vhd | 1 | 6,550 | -----------------------------------------------------------------------------------------------------------------------
-- Author:
--
-- Create Date: 12/11/2016 -- dd/mm/yyyy
-- Module Name: m_control_sim
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Este bloque simula la operacion del bloque master_control en cuanto al envio de palabras a los spi.
-- Si recibe un flanco en la entrada send_1_i(send_2_i), en el proximo flanco de reloj carga un dato
-- en la salida mc_do_1_o(mc_do_2_o) y en el siguiente flanco de reloj da un pulso de 1 Tclk en
-- la salida mc_wren_1_o(mc_wren_2_o).
-- Las entradas send_1_i y send_2_i no pueden estar activas a la vez.
--
-----------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
ENTITY m_control_sim IS
PORT(
m_clk : in std_logic; -- master clock
m_reset : in std_logic; -- master reset
---- master_control interface ----
mc_di_1_i : in std_logic_vector(15 downto 0);
mc_do_1_o : out std_logic_vector(15 downto 0);
mc_wren_1_o : out std_logic;
mc_drdy_1_i : in std_logic;
mc_rdreq_1_o : out std_logic;
mc_di_2_i : in std_logic_vector(15 downto 0);
mc_do_2_o : out std_logic_vector(15 downto 0);
mc_wren_2_o : out std_logic;
mc_drdy_2_i : in std_logic;
mc_rdreq_2_o : out std_logic;
---- user interface ----
send_1_i : in std_logic;
send_2_i : in std_logic
);
END m_control_sim;
ARCHITECTURE behav OF m_control_sim IS
-- regs
signal sg_do_1, sg_do_2 : std_logic_vector(15 downto 0);
signal sg_counter_1, sg_counter_2 : std_logic_vector(15 downto 0);
-- states
--type state_type IS (st_init, st_wait0, st_wait1, st_delay1, st_send);
type state_type IS (st_wait0, st_wait1, st_delay1, st_send);
attribute enum_encoding : string;
attribute enum_encoding of state_type : type is "one-hot";
signal STATE, NXSTATE : state_type;
BEGIN
state_machine:process (m_clk, m_reset, STATE, send_1_i, send_2_i)
begin
if m_reset = '1' then
--STATE <= st_init;
STATE <= st_wait1;
elsif m_clk'event and m_clk = '1' then
case STATE is
--when st_init =>
--sg_counter_1 <= X"A000";
--sg_counter_2 <= X"B000";
--STATE <= st_wait1;
--mc_wren_1_o <= '0';
--mc_wren_2_o <= '0';
when st_wait1 =>
if (send_1_i ='1' and send_2_i ='0') or (send_1_i ='0' and send_2_i ='1') then
STATE <= st_delay1;
--sg_do_1 <= sg_counter_1;
--elsif send_1_i ='0' and send_2_i ='1' then
-- STATE <= st_delay1;
--sg_do_2 <= sg_counter_2;
else
STATE <= st_wait1;
end if;
--mc_wren_1_o <= '0';
--mc_wren_2_o <= '0';
when st_delay1 =>
STATE <= st_send;
when st_send =>
STATE <= st_wait0;
--if send_1_i ='1' and send_2_i ='0' then
--sg_counter_1 <= sg_counter_1 + 1;
--mc_wren_1_o <= '1';
--mc_wren_2_o <= '0';
--elsif send_1_i ='0' and send_2_i ='1' then
--sg_counter_2 <= sg_counter_2 + 1;
--mc_wren_1_o <= '0';
--mc_wren_2_o <= '1';
--else
--mc_wren_1_o <= '0';
--mc_wren_2_o <= '0';
--end if;
when st_wait0 =>
if send_1_i ='1' or send_2_i ='1' then
STATE <= st_wait0;
else
STATE <= st_wait1;
end if;
--mc_wren_1_o <= '0';
--mc_wren_2_o <= '0';
when others =>
-- STATE <= st_init;
STATE <= st_wait1;
--mc_wren_1_o <= '0';
--mc_wren_2_o <= '0';
end case;
end if;
end process;
counters:process (m_reset, m_clk, STATE, send_1_i, send_2_i)
begin
if m_reset = '1' then
sg_counter_1 <= X"0000";
sg_counter_2 <= X"0000";
elsif m_clk'event and m_clk = '1' then
if STATE = st_send and send_1_i ='1' and send_2_i ='0' then
if sg_counter_1 = X"FFFF" then
sg_counter_1 <= X"0000";
else
sg_counter_1 <= sg_counter_1 + 1;
end if;
elsif STATE = st_send and send_1_i ='0' and send_2_i ='1' then
if sg_counter_2 = X"FFFF" then
sg_counter_2 <= X"0000";
else
sg_counter_2 <= sg_counter_2 + 1;
end if;
end if;
end if;
end process;
output_registers:process (m_reset, m_clk, STATE, send_1_i, send_2_i)
begin
if m_reset = '1' then
sg_do_1 <= X"0000";
sg_do_2 <= X"0000";
elsif m_clk'event and m_clk = '1' then
if STATE = st_wait1 and send_1_i ='1' and send_2_i ='0' then
sg_do_1 <= sg_counter_1;
elsif STATE = st_wait1 and send_1_i ='0' and send_2_i ='1' then
sg_do_2 <= sg_counter_2;
end if;
end if;
end process;
outputs:process (STATE, send_1_i, send_2_i)
begin
case STATE is
when st_wait1 =>
mc_wren_1_o <= '0';
mc_wren_2_o <= '0';
when st_delay1 =>
mc_wren_1_o <= '0';
mc_wren_2_o <= '0';
when st_send =>
if send_1_i ='1' and send_2_i ='0' then
mc_wren_1_o <= '1';
mc_wren_2_o <= '0';
elsif send_1_i ='0' and send_2_i ='1' then
mc_wren_1_o <= '0';
mc_wren_2_o <= '1';
else
mc_wren_1_o <= '0';
mc_wren_2_o <= '0';
end if;
when st_wait0 =>
mc_wren_1_o <= '0';
mc_wren_2_o <= '0';
when others =>
mc_wren_1_o <= '0';
mc_wren_2_o <= '0';
end case;
end process;
mc_do_1_o <= sg_do_1;
mc_do_2_o <= sg_do_2;
mc_rdreq_1_o <= '0';
mc_rdreq_2_o <= '0';
END behav; | gpl-3.0 | 01d00c47b53e277f3c478ac374e3fba7 | 0.441832 | 3.139981 | false | false | false | false |
boztalay/OldProjects | FPGA/Current Projects/Subsystems/SequenceDetectorEx.vhd | 1 | 2,104 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 21:41:11 09/24/2009
-- Design Name:
-- Module Name: SequenceDetectorEx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: A simple state machine that detects sequences of three 1s in a
-- binary string and outputs a 1 with the third 1 of every sequence.
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.70 - VHDL Written and debugged
-- Revision 1.00 - Successful simulation
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SequenceDetectorEx is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC);
end SequenceDetectorEx;
architecture StateMachine of SequenceDetectorEx is
type states is (A, B, C);
signal present_state, next_state : states;
begin
goto_state: process (clock, reset, next_state) is
begin
if reset = '1' then
present_state <= A;
elsif (rising_edge(clock)) then
present_state <= next_state;
end if;
end process;
states_proc: process (clock, reset, input, present_state) is
begin
case present_state is
when A =>
output <= '0';
if input = '1' then
next_state <= B;
else
next_state <= A;
end if;
when B =>
output <= '0';
if input = '1' then
next_state <= C;
else
next_state <= A;
end if;
when C =>
if input = '1' then
output <= '1';
next_state <= C;
else
output <= '0';
next_state <= A;
end if;
end case;
end process;
end StateMachine;
| mit | f372c8af9032e4057fa3271c99fb4f91 | 0.559886 | 3.554054 | false | false | false | false |
boztalay/OldProjects | FPGA/Sync_memory_test2/SM_mem_init_test.vhd | 1 | 9,107 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity SM_mem_init_test is
Port (clock : in STD_LOGIC;
reset : in STD_LOGIC;
RAM_wait : in STD_LOGIC;
memory_data_bus : inout STD_LOGIC_VECTOR(15 downto 0);
memory_address_bus : out STD_LOGIC_VECTOR(22 downto 0);
anodes : out STD_LOGIC_VECTOR(3 downto 0);
decoder_out : out STD_LOGIC_VECTOR(6 downto 0);
SM_reset : out STD_LOGIC;
RAM_ce : out STD_LOGIC;
RAM_we : out STD_LOGIC;
RAM_oe : out STD_LOGIC;
RAM_lb : out STD_LOGIC;
RAM_ub : out STD_LOGIC;
RAM_cre : out STD_LOGIC;
RAM_adv : out STD_LOGIC;
RAM_clk : out STD_LOGIC);
end entity;
architecture Behavioral of SM_mem_init_test is
component four_dig_7seg is
Port ( clock : in STD_LOGIC;
display_data : in STD_LOGIC_VECTOR (15 downto 0);
anodes : out STD_LOGIC_VECTOR (3 downto 0);
to_display : out STD_LOGIC_VECTOR (6 downto 0));
end component;
signal state : STD_LOGIC_VECTOR(4 downto 0);
signal SM_wait_counter : STD_LOGIC_VECTOR(2 downto 0);
signal clk_100MHz : STD_LOGIC;
signal RAM_clk_en : STD_LOGIC;
signal output_enable : STD_LOGIC;
signal memory_data_bus_in : STD_LOGIC_VECTOR(15 downto 0);
signal memory_data_bus_out : STD_LOGIC_VECTOR(15 downto 0);
signal collected_data : STD_LOGIC_VECTOR(15 downto 0);
begin
DCM_1 : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 2, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 20.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "HIGH", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLKFX => clk_100MHz, -- DCM CLK synthesis out (M/D)
CLKIN => clock
);
--The state machine
process (clk_100MHz, reset)
begin
if reset = '1' then
state <= "00000";
SM_reset <= '1';
SM_wait_counter <= "000";
output_enable <= '0';
RAM_ce <= '1';
RAM_we <= '1';
RAM_oe <= '0';
RAM_adv <= '1';
RAM_lb <= '0';
RAM_ub <= '0';
RAM_cre <= '0';
RAM_clk_en <= '0';
elsif falling_edge(clk_100MHz) then
case state is
--These first states put the memory into synchronous mode
--Read cycle one
when "00000" =>
SM_reset <= '1';
RAM_ce <= '0';
RAM_we <= '1';
RAM_oe <= '0';
RAM_lb <= '0';
RAM_ub <= '0';
RAM_clk_en <= '0';
RAM_cre <= '0';
memory_address_bus <= (others => '1');
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00001";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00000";
end if;
when "00001" =>
RAM_ce <= '1';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00010";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00001";
end if;
--Read cycle two
when "00010" =>
RAM_ce <= '0';
memory_address_bus <= (others => '1');
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00011";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00010";
end if;
when "00011" =>
RAM_ce <= '1';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00100";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00011";
end if;
--Write cycle one
when "00100" =>
--Setup state for the first write cycle
RAM_oe <= '1';
RAM_ce <= '0';
memory_address_bus <= (others => '1');
output_enable <= '1';
memory_data_bus_out <= x"0001";
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00101";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00100";
end if;
when "00101" =>
--Second half of the first write cycle
RAM_we <= '0';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00110";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00101";
end if;
when "00110" =>
RAM_ce <= '1';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00111";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00110";
end if;
--Second write cycle
when "00111" =>
RAM_ce <= '0';
memory_data_bus_out <= b"0001110101001111"; --BCR data
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "01000";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00111";
end if;
when "01000" =>
output_enable <= '0';
RAM_ce <= '1';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "01001";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "01000";
end if;
--End of initialization, begin normal operation
--Wait state, also enable RAM_clk
when "01001" =>
RAM_clk_en <= '1';
output_enable <= '1';
state <= "01010";
--Set up the signals for a write
when "01010" =>
RAM_ce <= '0';
RAM_adv <= '0';
RAM_we <= '0';
RAM_oe <= '1';
memory_address_bus <= b"00000000000000000000001";
state <= "01011";
--Wait for RAM_wait
when "01100" =>
RAM_adv <= '0';
if RAM_wait = '1' then
state <= "01101";
else
state <= "01100";
end if;
--Begin the writes
when "01101" =>
memory_data_bus_out <= x"000F";
state <= "01110";
when "01110" =>
memory_data_bus_out <= x"000E";
state <= "01111";
when "01111" =>
memory_data_bus_out <= x"000D";
state <= "10000";
when "10000" =>
memory_data_bus_out <= x"000C";
state <= "10001";
--End the write
when "10001" =>
RAM_ce <= '1';
state <= "10010";
--A wait cycle
when "10010" =>
state <= "10011";
--Set up the signals for a read
when "10011" =>
RAM_ce <= '0';
RAM_adv <= '0';
RAM_oe <= '0';
RAM_we <= '1';
output_enable <= '0';
memory_address_bus <= b"00000000000000000000001";
state <= "10100";
--Read into a register
when "10100" =>
collected_data(3 downto 0) <= memory_data_bus_in(3 downto 0);
state <= "10101";
when "10101" =>
collected_data(7 downto 4) <= memory_data_bus_in(3 downto 0);
state <= "10110";
when "10110" =>
collected_data(11 downto 8) <= memory_data_bus_in(3 downto 0);
state <= "10111";
when "10111" =>
collected_data(15 downto 12) <= memory_data_bus_in(3 downto 0);
state <= "11000";
--End the read and wait here
when "11000" =>
RAM_ce <= '1';
RAM_oe <= '1';
RAM_we <= '1';
state <= "11000";
when others =>
state <= "00000";
end case;
end if;
end process;
--A tristate buffer for the memory data bus
tristate : process (output_enable, memory_data_bus_in)
begin
if output_enable = '1' then
memory_data_bus <= memory_data_bus_out;
else
memory_data_bus <= (others => 'Z');
end if;
memory_data_bus_in <= memory_data_bus;
end process;
--Handles the enabling of the RAM clock
RAM_clock : process (clk_100MHz, RAM_clk_en)
begin
if RAM_clk_en = '1' then
RAM_clk <= clk_100MHz;
else
RAM_clk <= 'Z';
end if;
end process;
display: four_dig_7seg port map (clock => clock,
display_data => collected_data,
anodes => anodes,
to_display => decoder_out);
end Behavioral; | mit | 536fa2147dc836ebe0a1774b1d4d21b6 | 0.522236 | 3.161055 | false | false | false | false |
boztalay/OldProjects | FPGA/LCD_Control/TestCPU1_Cntl_TB.vhd | 1 | 4,666 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:19:17 10/09/2009
-- Design Name:
-- Module Name: E:/FPGA/Projects/Current Projects/Systems/TestCPU1/TestCPU1_Cntl_TB.vhd
-- Project Name: TestCPU1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: TestCPU1_Cntl
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY TestCPU1_Cntl_TB IS
END TestCPU1_Cntl_TB;
ARCHITECTURE behavior OF TestCPU1_Cntl_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TestCPU1_Cntl
PORT(
clock : IN std_logic;
Z_flag : IN std_logic;
instruction : IN std_logic_vector(15 downto 0);
ALUB_out : OUT std_logic_vector(15 downto 0);
addr_bus : OUT std_logic_vector(7 downto 0);
ALU_op : OUT std_logic;
ALU_to_bus_e : out STD_LOGIC;
opins_act : OUT std_logic;
PC_take_alt_addr : OUT std_logic;
RFile_ld_val : OUT std_logic;
RFile_ALUB_out : OUT std_logic;
RFile_src1_addr : OUT std_logic_vector(2 downto 0);
RFile_src2_addr : OUT std_logic_vector(2 downto 0);
RFile_dest_addr : OUT std_logic_vector(2 downto 0);
dRAM_write_e : OUT std_logic;
dRAM_read_e : OUT std_logic);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal Z_flag : std_logic := '0';
signal instruction : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal ALUB_out : std_logic_vector(15 downto 0);
signal addr_bus : std_logic_vector(7 downto 0);
signal ALU_op : std_logic;
signal ALU_to_bus_e : std_logic;
signal opins_act : std_logic;
signal PC_take_alt_addr : std_logic;
signal RFile_ld_val : std_logic;
signal RFile_ALUB_out : std_logic;
signal RFile_src1_addr : std_logic_vector(2 downto 0);
signal RFile_src2_addr : std_logic_vector(2 downto 0);
signal RFile_dest_addr : std_logic_vector(2 downto 0);
signal dRAM_write_e : std_logic;
signal dRAM_read_e : std_logic;
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TestCPU1_Cntl PORT MAP (
clock => clock,
Z_flag => Z_flag,
instruction => instruction,
ALUB_out => ALUB_out,
addr_bus => addr_bus,
ALU_op => ALU_op,
ALU_to_bus_e => ALU_to_bus_e,
opins_act => opins_act,
PC_take_alt_addr => PC_take_alt_addr,
RFile_ld_val => RFile_ld_val,
RFile_ALUB_out => RFile_ALUB_out,
RFile_src1_addr => RFile_src1_addr,
RFile_src2_addr => RFile_src2_addr,
RFile_dest_addr => RFile_dest_addr,
dRAM_write_e => dRAM_write_e,
dRAM_read_e => dRAM_read_e
);
-- Clock process definitions
clock_process :process
begin
clock <= '1';
wait for clock_period/2;
clock <= '0';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 20 ns;
instruction <= b"0000000101001100"; --add r1, r2, r3;
wait for 10 ns;
instruction <= b"0000100101001100"; --sub r1, r2, r3;
wait for 10 ns;
instruction <= b"0001100101000011"; --subi r1, r2, 3;
wait for 10 ns;
instruction <= b"0001000101000011"; --addi r1, r2, 3;
wait for 10 ns;
instruction <= b"0010000001001100"; --cp r2, r3;
wait for 10 ns;
instruction <= b"0100000000000111"; --bz r0, 7;
wait for 10 ns;
Z_flag <= '1';
wait for 10 ns;
Z_flag <= '0';
instruction <= b"0100100000000111"; --jp 7;
wait for 10 ns;
instruction <= b"1000000000100001"; --opin 1, 1;
wait for 10 ns;
instruction <= b"1100000100000111"; --str r1, 7;
wait for 10 ns;
instruction <= b"1100100100000111"; --ld r1, 7;
wait;
end process;
END;
| mit | d89f17fab199edf97c118fe08a67124e | 0.582297 | 3.418315 | false | true | false | false |
DaveyPocket/btrace448 | btrace/vector_reg.vhd | 1 | 555 | -- Btrace 448
-- Vector Register
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
use work.btrace_pack.all;
entity vector_reg is
port(clk, rst, en: in std_logic;
Din: in vector;
Dout: out vector);
end vector_reg;
architecture arch of vector_reg is
constant zero_vector: vector := ((others => '0'), (others => '0'), (others => '0'));
begin
process(clk, rst)
begin
if rst = '1' then
Dout <= zero_vector;
elsif rising_edge(clk) then
if en = '1' then
Dout <= Din;
end if;
end if;
end process;
end arch;
| gpl-3.0 | f8b7e652c5f7203f7d4a1e70d2e323ec | 0.641441 | 2.831633 | false | false | false | false |
boztalay/OldProjects | FPGA/LCD_Control/TestCPU1_SynthBench.vhd | 1 | 5,927 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:36:51 10/15/2009
-- Design Name:
-- Module Name: TestCPU1_SynthBench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity TestCPU1_SynthBench is
Port ( board_clk : in STD_LOGIC;
anodes : out STD_LOGIC_VECTOR(3 downto 0);
out_pins : out STD_LOGIC_VECTOR(31 downto 0);
LCD_DB : out STD_LOGIC_VECTOR(7 downto 0);
r2 : out STD_LOGIC_VECTOR(15 downto 0);
r5 : out STD_LOGIC_VECTOR(15 downto 0);
CPU_clk : out STD_LOGIC);
end TestCPU1_SynthBench;
architecture Behavioral of TestCPU1_SynthBench is
--//Component Declarations\\--
component TestCPU1 is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
out_pins : out STD_LOGIC_VECTOR(31 downto 0);
reg_1 : out STD_LOGIC_VECTOR(15 downto 0);
reg_2 : out STD_LOGIC_VECTOR(15 downto 0);
reg_5 : out STD_LOGIC_VECTOR(15 downto 0));
end component;
component mROM is
Port ( enable : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (4 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0));
end component;
--\\Component Declarations//--
--//Signal Declarations\\--
signal buf_board_clk : STD_LOGIC;
signal buf_clock : STD_LOGIC;
signal clk_to_CPU : STD_LOGIC;
signal buf_clk_to_CPU : STD_LOGIC;
signal DCM_sig : STD_LOGIC;
signal mROM_e : STD_LOGIC;
signal mROM_addr : STD_LOGIC_VECTOR(15 downto 0);
signal output_pins : STD_LOGIC_VECTOR(31 downto 0);
--\\Signal Declarations//--
begin
IBUFG_inst : IBUFG
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => buf_board_clk, -- Clock buffer output
I => board_clk -- Clock buffer input (connect directly to top-level port)
);
BUFG_CPUclk : BUFG
port map (
O => buf_clk_to_CPU,
I => clk_to_CPU
);
DCM_main_clk : DCM --Divides 50 MHz clock to 5 MHz
-- The following generics are only necessary if you wish to change the default behavior.
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 20, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 20.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLKFX => DCM_sig, -- DCM CLK synthesis out (M/D)
CLKIN => buf_board_clk -- Clock input (from IBUFG, BUFG or DCM)
);
DCM_smaller_clk : DCM --Divides 5 MHz down to 1 MHz
-- The following generics are only necessary if you wish to change the default behavior.
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 10, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 50.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLKFX => clk_to_CPU, -- DCM CLK synthesis out (M/D)
CLKIN => DCM_sig -- Clock input (from IBUFG, BUFG or DCM)
);
CPU: TestCPU1 port map (clock => buf_clk_to_CPU, out_pins => output_pins, reset => '0',
reg_1 => mROM_addr, reg_2 => r2, reg_5 => r5);
MessageROM: mROM port map (output_pins(3), mROM_addr(4 downto 0), LCD_DB);
CPU_clk <= buf_clk_to_CPU;
out_pins <= output_pins;
anodes <= b"1111";
end Behavioral;
| mit | 4efef482b3662361b0868ed13a3d46af | 0.588831 | 3.460012 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/hps_fpga/hps_fpga_inst.vhd | 1 | 24,763 | component hps_fpga is
port (
clk_clk : in std_logic := 'X'; -- clk
cpu_0_rx_0_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
cpu_0_rx_1_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
cpu_0_rx_2_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
cpu_0_rx_3_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
cpu_0_rx_4_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
cpu_0_rx_5_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
cpu_0_rx_6_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
cpu_0_rx_7_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
cpu_0_tx_0_external_connection_export : out std_logic_vector(31 downto 0); -- export
cpu_0_tx_1_external_connection_export : out std_logic_vector(31 downto 0); -- export
cpu_0_tx_2_external_connection_export : out std_logic_vector(31 downto 0); -- export
cpu_0_tx_3_external_connection_export : out std_logic_vector(31 downto 0); -- export
cpu_0_tx_4_external_connection_export : out std_logic_vector(31 downto 0); -- export
cpu_0_tx_5_external_connection_export : out std_logic_vector(31 downto 0); -- export
cpu_0_tx_6_external_connection_export : out std_logic_vector(31 downto 0); -- export
cpu_0_tx_7_external_connection_export : out std_logic_vector(31 downto 0); -- export
cpu_1_rx_0_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
cpu_1_rx_1_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
cpu_1_rx_2_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
cpu_1_rx_3_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
cpu_1_rx_4_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
cpu_1_rx_5_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
cpu_1_rx_6_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
cpu_1_rx_7_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
cpu_1_tx_0_external_connection_export : out std_logic_vector(31 downto 0); -- export
cpu_1_tx_1_external_connection_export : out std_logic_vector(31 downto 0); -- export
cpu_1_tx_2_external_connection_export : out std_logic_vector(31 downto 0); -- export
cpu_1_tx_3_external_connection_export : out std_logic_vector(31 downto 0); -- export
cpu_1_tx_4_external_connection_export : out std_logic_vector(31 downto 0); -- export
cpu_1_tx_5_external_connection_export : out std_logic_vector(31 downto 0); -- export
cpu_1_tx_6_external_connection_export : out std_logic_vector(31 downto 0); -- export
cpu_1_tx_7_external_connection_export : out std_logic_vector(31 downto 0); -- export
hps_0_h2f_reset_reset_n : out std_logic; -- reset_n
hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
led_external_connection_export : out std_logic_vector(9 downto 0); -- export
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
noc_clock_clk : out std_logic; -- clk
noc_ctrl_0_external_connection_export : out std_logic_vector(31 downto 0); -- export
noc_ctrl_1_external_connection_export : out std_logic_vector(31 downto 0); -- export
noc_status_0_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
noc_status_1_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
pll_0_outclk0_clk : out std_logic; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sw_external_connection_export : in std_logic_vector(9 downto 0) := (others => 'X') -- export
);
end component hps_fpga;
u0 : component hps_fpga
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
cpu_0_rx_0_external_connection_export => CONNECTED_TO_cpu_0_rx_0_external_connection_export, -- cpu_0_rx_0_external_connection.export
cpu_0_rx_1_external_connection_export => CONNECTED_TO_cpu_0_rx_1_external_connection_export, -- cpu_0_rx_1_external_connection.export
cpu_0_rx_2_external_connection_export => CONNECTED_TO_cpu_0_rx_2_external_connection_export, -- cpu_0_rx_2_external_connection.export
cpu_0_rx_3_external_connection_export => CONNECTED_TO_cpu_0_rx_3_external_connection_export, -- cpu_0_rx_3_external_connection.export
cpu_0_rx_4_external_connection_export => CONNECTED_TO_cpu_0_rx_4_external_connection_export, -- cpu_0_rx_4_external_connection.export
cpu_0_rx_5_external_connection_export => CONNECTED_TO_cpu_0_rx_5_external_connection_export, -- cpu_0_rx_5_external_connection.export
cpu_0_rx_6_external_connection_export => CONNECTED_TO_cpu_0_rx_6_external_connection_export, -- cpu_0_rx_6_external_connection.export
cpu_0_rx_7_external_connection_export => CONNECTED_TO_cpu_0_rx_7_external_connection_export, -- cpu_0_rx_7_external_connection.export
cpu_0_tx_0_external_connection_export => CONNECTED_TO_cpu_0_tx_0_external_connection_export, -- cpu_0_tx_0_external_connection.export
cpu_0_tx_1_external_connection_export => CONNECTED_TO_cpu_0_tx_1_external_connection_export, -- cpu_0_tx_1_external_connection.export
cpu_0_tx_2_external_connection_export => CONNECTED_TO_cpu_0_tx_2_external_connection_export, -- cpu_0_tx_2_external_connection.export
cpu_0_tx_3_external_connection_export => CONNECTED_TO_cpu_0_tx_3_external_connection_export, -- cpu_0_tx_3_external_connection.export
cpu_0_tx_4_external_connection_export => CONNECTED_TO_cpu_0_tx_4_external_connection_export, -- cpu_0_tx_4_external_connection.export
cpu_0_tx_5_external_connection_export => CONNECTED_TO_cpu_0_tx_5_external_connection_export, -- cpu_0_tx_5_external_connection.export
cpu_0_tx_6_external_connection_export => CONNECTED_TO_cpu_0_tx_6_external_connection_export, -- cpu_0_tx_6_external_connection.export
cpu_0_tx_7_external_connection_export => CONNECTED_TO_cpu_0_tx_7_external_connection_export, -- cpu_0_tx_7_external_connection.export
cpu_1_rx_0_external_connection_export => CONNECTED_TO_cpu_1_rx_0_external_connection_export, -- cpu_1_rx_0_external_connection.export
cpu_1_rx_1_external_connection_export => CONNECTED_TO_cpu_1_rx_1_external_connection_export, -- cpu_1_rx_1_external_connection.export
cpu_1_rx_2_external_connection_export => CONNECTED_TO_cpu_1_rx_2_external_connection_export, -- cpu_1_rx_2_external_connection.export
cpu_1_rx_3_external_connection_export => CONNECTED_TO_cpu_1_rx_3_external_connection_export, -- cpu_1_rx_3_external_connection.export
cpu_1_rx_4_external_connection_export => CONNECTED_TO_cpu_1_rx_4_external_connection_export, -- cpu_1_rx_4_external_connection.export
cpu_1_rx_5_external_connection_export => CONNECTED_TO_cpu_1_rx_5_external_connection_export, -- cpu_1_rx_5_external_connection.export
cpu_1_rx_6_external_connection_export => CONNECTED_TO_cpu_1_rx_6_external_connection_export, -- cpu_1_rx_6_external_connection.export
cpu_1_rx_7_external_connection_export => CONNECTED_TO_cpu_1_rx_7_external_connection_export, -- cpu_1_rx_7_external_connection.export
cpu_1_tx_0_external_connection_export => CONNECTED_TO_cpu_1_tx_0_external_connection_export, -- cpu_1_tx_0_external_connection.export
cpu_1_tx_1_external_connection_export => CONNECTED_TO_cpu_1_tx_1_external_connection_export, -- cpu_1_tx_1_external_connection.export
cpu_1_tx_2_external_connection_export => CONNECTED_TO_cpu_1_tx_2_external_connection_export, -- cpu_1_tx_2_external_connection.export
cpu_1_tx_3_external_connection_export => CONNECTED_TO_cpu_1_tx_3_external_connection_export, -- cpu_1_tx_3_external_connection.export
cpu_1_tx_4_external_connection_export => CONNECTED_TO_cpu_1_tx_4_external_connection_export, -- cpu_1_tx_4_external_connection.export
cpu_1_tx_5_external_connection_export => CONNECTED_TO_cpu_1_tx_5_external_connection_export, -- cpu_1_tx_5_external_connection.export
cpu_1_tx_6_external_connection_export => CONNECTED_TO_cpu_1_tx_6_external_connection_export, -- cpu_1_tx_6_external_connection.export
cpu_1_tx_7_external_connection_export => CONNECTED_TO_cpu_1_tx_7_external_connection_export, -- cpu_1_tx_7_external_connection.export
hps_0_h2f_reset_reset_n => CONNECTED_TO_hps_0_h2f_reset_reset_n, -- hps_0_h2f_reset.reset_n
hps_io_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CLK, -- hps_io.hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
hps_io_hps_io_sdio_inst_CMD => CONNECTED_TO_hps_io_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK => CONNECTED_TO_hps_io_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK => CONNECTED_TO_hps_io_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP => CONNECTED_TO_hps_io_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR => CONNECTED_TO_hps_io_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT => CONNECTED_TO_hps_io_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
hps_io_hps_io_uart0_inst_RX => CONNECTED_TO_hps_io_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX => CONNECTED_TO_hps_io_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
led_external_connection_export => CONNECTED_TO_led_external_connection_export, -- led_external_connection.export
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
noc_clock_clk => CONNECTED_TO_noc_clock_clk, -- noc_clock.clk
noc_ctrl_0_external_connection_export => CONNECTED_TO_noc_ctrl_0_external_connection_export, -- noc_ctrl_0_external_connection.export
noc_ctrl_1_external_connection_export => CONNECTED_TO_noc_ctrl_1_external_connection_export, -- noc_ctrl_1_external_connection.export
noc_status_0_external_connection_export => CONNECTED_TO_noc_status_0_external_connection_export, -- noc_status_0_external_connection.export
noc_status_1_external_connection_export => CONNECTED_TO_noc_status_1_external_connection_export, -- noc_status_1_external_connection.export
pll_0_outclk0_clk => CONNECTED_TO_pll_0_outclk0_clk, -- pll_0_outclk0.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sw_external_connection_export => CONNECTED_TO_sw_external_connection_export -- sw_external_connection.export
);
| mit | 76eb2d4b35f68d6bbf38f227ef6c3e9c | 0.495093 | 3.297337 | false | false | false | false |
fkolacek/FIT-VUT | INP1/fpga/sim/ledc8x8_tb.vhd | 4 | 754 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity testbench is
end testbench;
architecture behv of testbench is
component ledc8x8 is
port ( SMCLK, RESET: in std_logic;
ROW, LED: out std_logic_vector(0 to 7)
);
end component;
signal smclk: std_logic := '0';
signal reset: std_logic;
signal row, led: std_logic_vector(0 to 7);
constant period: time := 20 ns;
begin
uut: ledc8x8 port map(smclk, reset, row, led);
smclk <= not smclk after period / 2;
test: process
begin
reset <= '1';
wait until smclk'event and smclk = '1';
reset <= '0';
wait;
end process;
end behv;
| apache-2.0 | 3420382cc06d139534af6e7c8c512b64 | 0.599469 | 3.506977 | false | true | false | false |
boztalay/OldProjects | FPGA/Sys_SecondTimer/Sys_SecondTimer.vhd | 1 | 5,729 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 17:45:06 07/30/2009
-- Design Name:
-- Module Name: Sys_SecondTimer - Structural
-- Project Name: Second Timer
-- Target Devices:
-- Tool versions:
-- Description: A simple second timer with four digits (counts from 0 to 9999).
-- Synchronous reset.
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - Modified all component VHD files
-- Revision 0.11 - Created all component instantiations
-- Revision 0.12 - Created all signals
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity Sys_SecondTimer is
Port ( BoardClock : in STD_LOGIC;
Reset : in STD_LOGIC;
Segments : out STD_LOGIC_VECTOR (6 downto 0);
Anodes : out STD_LOGIC_VECTOR (3 downto 0));
end Sys_SecondTimer;
--Architecture--
architecture Structural of Sys_SecondTimer is
--\Components/--
component Comp_ClockGen1Hz is
Port ( Board_Clk : in STD_LOGIC;
Clock_Out : out STD_LOGIC);
end component;
-----
component Comp_ClockGen400Hz is
Port ( Board_Clk : in STD_LOGIC;
Clock_Out : out STD_LOGIC);
end component;
-----
component Comp_Counter4bit is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (3 downto 0));
end component;
-----
component Comp_ValChk9 is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
equal : out STD_LOGIC);
end component;
-----
component Comp_GateOR is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Q : out STD_LOGIC);
end component;
-----
component Comp_DataMUX4x4 is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC_VECTOR (3 downto 0);
D : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC_VECTOR (3 downto 0));
end component;
-----
component Comp_Counter2bit is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (1 downto 0));
end component;
-----
component Comp_DecadeCnt4bit is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
outputs : out STD_LOGIC_VECTOR (3 downto 0));
end component;
-----
component Comp_7segDecode is
Port ( number : in STD_LOGIC_VECTOR (3 downto 0);
segments : out STD_LOGIC_VECTOR (6 downto 0));
end component;
--/Components\--
--\Signals/--
signal Buf_BoardClock : STD_LOGIC;
signal Buf_Clock1Hz : STD_LOGIC;
signal Buf_Clock400Hz : STD_LOGIC;
signal Unbuf_Clock1Hz : STD_LOGIC;
signal Unbuf_Clock400Hz : STD_LOGIC;
signal Dig1CounterOut : STD_LOGIC_VECTOR (3 downto 0);
signal Dig2CounterOut : STD_LOGIC_VECTOR (3 downto 0);
signal Dig3CounterOut : STD_LOGIC_VECTOR (3 downto 0);
signal Dig4CounterOut : STD_LOGIC_VECTOR (3 downto 0);
signal Dig1ValChkOut : STD_LOGIC;
signal Dig2ValChkOut : STD_LOGIC;
signal Dig3ValChkOut : STD_LOGIC;
signal Dig4ValChkOut : STD_LOGIC;
signal Dig1Reset : STD_LOGIC;
signal Dig2Reset : STD_LOGIC;
signal Dig3Reset : STD_LOGIC;
signal Dig4Reset : STD_LOGIC;
signal MultiplexerOut : STD_LOGIC_VECTOR (3 downto 0);
signal Counter2bitOut : STD_LOGIC_VECTOR (1 downto 0);
signal DecadeCountOut : STD_LOGIC_VECTOR (3 downto 0);
signal ZeroSig : STD_LOGIC := '0';
--/Signals\--
--Architecture Begin--
begin
--\BUFG Instantiations-/--
BUFG_BufBoardClock : BUFG
port map (
O => Buf_BoardClock,
I => BoardClock
);
BUFG_BufClock1Hz : BUFG
port map (
O => Buf_Clock1Hz,
I => Unbuf_Clock1Hz
);
BUFG_BufClock400Hz : BUFG
port map (
O => Buf_Clock400Hz,
I => Unbuf_Clock400Hz
);
--/BUFG Instantiations\--
--\Port Maps/--
Clock1 : Comp_ClockGen1Hz port map (Buf_BoardClock, Unbuf_Clock1Hz);
Clock2 : Comp_ClockGen400Hz port map (Buf_BoardClock, Unbuf_Clock400Hz);
Dig1 : Comp_Counter4bit port map (Buf_Clock1Hz, Dig1Reset, Dig1CounterOut);
Dig2 : Comp_Counter4bit port map (Dig1ValChkOut, Dig2Reset, Dig2CounterOut);
Dig3 : Comp_Counter4bit port map (Dig2ValChkOut, Dig3Reset, Dig3CounterOut);
Dig4 : Comp_Counter4bit port map (Dig3ValChkOut, Dig4Reset, Dig4CounterOut);
Dig1ValChk : Comp_ValChk9 port map (Dig1CounterOut, Dig1ValChkOut);
Dig2ValChk : Comp_ValChk9 port map (Dig2CounterOut, Dig2ValChkOut);
Dig3ValChk : Comp_ValChk9 port map (Dig3CounterOut, Dig3ValChkOut);
Dig4ValChk : Comp_ValChk9 port map (Dig4CounterOut, Dig4ValChkOut);
Dig1ResetOR : Comp_GateOR port map (Dig1ValChkOut, Reset, Dig1Reset);
Dig2ResetOR : Comp_GateOR port map (Dig2ValChkOut, Reset, Dig2Reset);
Dig3ResetOR : Comp_GateOR port map (Dig3ValChkOut, Reset, Dig3Reset);
Dig4ResetOR : Comp_GateOR port map (Dig4ValChkOut, Reset, Dig4Reset);
Multiplexer : Comp_DataMUX4x4 port map (Dig1CounterOut, Dig2CounterOut, Dig3CounterOut,
Dig4CounterOut, Counter2bitOut, MultiplexerOut);
Count2bit : Comp_Counter2bit port map (Buf_Clock400Hz, ZeroSig, Counter2bitOut);
DecCount : Comp_DecadeCnt4bit port map (Buf_Clock400Hz, ZeroSig, DecadeCountOut);
SegDecode : Comp_7segDecode port map (MultiplexerOut, Segments);
Anodes <= (not DecadeCountOut);
--/Port Maps\--
end Structural;
--End Architecture--
| mit | 3354af5f9890c49ed9b71802b8bf1421 | 0.659277 | 3.40404 | false | false | false | false |
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